1@c Copyright 2005, 2006, 2009, 2010 2@c Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@ifset GENERIC 6@page 7@node Blackfin-Dependent 8@chapter Blackfin Dependent Features 9@end ifset 10@ifclear GENERIC 11@node Machine Dependencies 12@chapter Blackfin Dependent Features 13@end ifclear 14 15@cindex Blackfin support 16@menu 17* Blackfin Options:: Blackfin Options 18* Blackfin Syntax:: Blackfin Syntax 19* Blackfin Directives:: Blackfin Directives 20@end menu 21 22@node Blackfin Options 23@section Options 24@cindex Blackfin options (none) 25@cindex options for Blackfin (none) 26 27@table @code 28 29@cindex @code{-mcpu=} command line option, Blackfin 30@item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]} 31This option specifies the target processor. The optional @var{sirevision} 32is not used in assembler. It's here such that GCC can easily pass down its 33@code{-mcpu=} option. The assembler will issue an 34error message if an attempt is made to assemble an instruction which 35will not execute on the target processor. The following processor names are 36recognized: 37@code{bf504}, 38@code{bf506}, 39@code{bf512}, 40@code{bf514}, 41@code{bf516}, 42@code{bf518}, 43@code{bf522}, 44@code{bf523}, 45@code{bf524}, 46@code{bf525}, 47@code{bf526}, 48@code{bf527}, 49@code{bf531}, 50@code{bf532}, 51@code{bf533}, 52@code{bf534}, 53@code{bf535} (not implemented yet), 54@code{bf536}, 55@code{bf537}, 56@code{bf538}, 57@code{bf539}, 58@code{bf542}, 59@code{bf542m}, 60@code{bf544}, 61@code{bf544m}, 62@code{bf547}, 63@code{bf547m}, 64@code{bf548}, 65@code{bf548m}, 66@code{bf549}, 67@code{bf549m}, 68@code{bf561}, 69and 70@code{bf592}. 71 72@cindex @code{-mfdpic} command line option, Blackfin 73@item -mfdpic 74Assemble for the FDPIC ABI. 75 76@cindex @code{-mno-fdpic} command line option, Blackfin 77@cindex @code{-mnopic} command line option, Blackfin 78@item -mno-fdpic 79@itemx -mnopic 80Disable -mfdpic. 81@end table 82 83@node Blackfin Syntax 84@section Syntax 85@cindex Blackfin syntax 86@cindex syntax, Blackfin 87 88@table @code 89@item Special Characters 90Assembler input is free format and may appear anywhere on the line. 91One instruction may extend across multiple lines or more than one 92instruction may appear on the same line. White space (space, tab, 93comments or newline) may appear anywhere between tokens. A token must 94not have embedded spaces. Tokens include numbers, register names, 95keywords, user identifiers, and also some multicharacter special 96symbols like "+=", "/*" or "||". 97 98@item Instruction Delimiting 99A semicolon must terminate every instruction. Sometimes a complete 100instruction will consist of more than one operation. There are two 101cases where this occurs. The first is when two general operations 102are combined. Normally a comma separates the different parts, as in 103 104@smallexample 105a0= r3.h * r2.l, a1 = r3.l * r2.h ; 106@end smallexample 107 108The second case occurs when a general instruction is combined with one 109or two memory references for joint issue. The latter portions are 110set off by a "||" token. 111 112@smallexample 113a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 114@end smallexample 115 116@item Register Names 117 118The assembler treats register names and instruction keywords in a case 119insensitive manner. User identifiers are case sensitive. Thus, R3.l, 120R3.L, r3.l and r3.L are all equivalent input to the assembler. 121 122Register names are reserved and may not be used as program identifiers. 123 124Some operations (such as "Move Register") require a register pair. 125Register pairs are always data registers and are denoted using a colon, 126eg., R3:2. The larger number must be written firsts. Note that the 127hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0. 128 129Some instructions (such as --SP (Push Multiple)) require a group of 130adjacent registers. Adjacent registers are denoted in the syntax by 131the range enclosed in parentheses and separated by a colon, eg., (R7:3). 132Again, the larger number appears first. 133 134Portions of a particular register may be individually specified. This 135is written with a dot (".") following the register name and then a 136letter denoting the desired portion. For 32-bit registers, ".H" 137denotes the most significant ("High") portion. ".L" denotes the 138least-significant portion. The subdivisions of the 40-bit registers 139are described later. 140 141@item Accumulators 142The set of 40-bit registers A1 and A0 that normally contain data that 143is being manipulated. Each accumulator can be accessed in four ways. 144 145@table @code 146@item one 40-bit register 147The register will be referred to as A1 or A0. 148@item one 32-bit register 149The registers are designated as A1.W or A0.W. 150@item two 16-bit registers 151The registers are designated as A1.H, A1.L, A0.H or A0.L. 152@item one 8-bit register 153The registers are designated as A1.X or A0.X for the bits that 154extend beyond bit 31. 155@end table 156 157@item Data Registers 158The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that 159normally contain data for manipulation. These are abbreviated as 160D-register or Dreg. Data registers can be accessed as 32-bit registers 161or as two independent 16-bit registers. The least significant 16 bits 162of each register is called the "low" half and is designated with ".L" 163following the register name. The most significant 16 bits are called 164the "high" half and is designated with ".H" following the name. 165 166@smallexample 167 R7.L, r2.h, r4.L, R0.H 168@end smallexample 169 170@item Pointer Registers 171The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that 172normally contain byte addresses of data structures. These are 173abbreviated as P-register or Preg. 174 175@smallexample 176p2, p5, fp, sp 177@end smallexample 178 179@item Stack Pointer SP 180The stack pointer contains the 32-bit address of the last occupied 181byte location in the stack. The stack grows by decrementing the 182stack pointer. 183 184@item Frame Pointer FP 185The frame pointer contains the 32-bit address of the previous frame 186pointer in the stack. It is located at the top of a frame. 187 188@item Loop Top 189LT0 and LT1. These registers contain the 32-bit address of the top of 190a zero overhead loop. 191 192@item Loop Count 193LC0 and LC1. These registers contain the 32-bit counter of the zero 194overhead loop executions. 195 196@item Loop Bottom 197LB0 and LB1. These registers contain the 32-bit address of the bottom 198of a zero overhead loop. 199 200@item Index Registers 201The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte 202addresses of data structures. Abbreviated I-register or Ireg. 203 204@item Modify Registers 205The set of 32-bit registers (M0, M1, M2, M3) that normally contain 206offset values that are added and subracted to one of the index 207registers. Abbreviated as Mreg. 208 209@item Length Registers 210The set of 32-bit registers (L0, L1, L2, L3) that normally contain the 211length in bytes of the circular buffer. Abbreviated as Lreg. Clear 212the Lreg to disable circular addressing for the corresponding Ireg. 213 214@item Base Registers 215The set of 32-bit registers (B0, B1, B2, B3) that normally contain the 216base address in bytes of the circular buffer. Abbreviated as Breg. 217 218@item Floating Point 219The Blackfin family has no hardware floating point but the .float 220directive generates ieee floating point numbers for use with software 221floating point libraries. 222 223@item Blackfin Opcodes 224For detailed information on the Blackfin machine instruction set, see 225the Blackfin(r) Processor Instruction Set Reference. 226 227@end table 228 229@node Blackfin Directives 230@section Directives 231@cindex Blackfin directives 232@cindex directives, Blackfin 233 234The following directives are provided for compatibility with the VDSP assembler. 235 236@table @code 237@item .byte2 238Initializes a four byte data object. 239@item .byte4 240Initializes a two byte data object. 241@item .db 242TBD 243@item .dd 244TBD 245@item .dw 246TBD 247@item .var 248Define and initialize a 32 bit data object. 249@end table 250