1@c Copyright (C) 2006-2018 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4 5@ifset GENERIC 6@page 7@node AVR-Dependent 8@chapter AVR Dependent Features 9@end ifset 10 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter AVR Dependent Features 14@end ifclear 15 16@cindex AVR support 17@menu 18* AVR Options:: Options 19* AVR Syntax:: Syntax 20* AVR Opcodes:: Opcodes 21* AVR Pseudo Instructions:: Pseudo Instructions 22@end menu 23 24@node AVR Options 25@section Options 26@cindex AVR options (none) 27@cindex options for AVR (none) 28 29@table @code 30 31@cindex @code{-mmcu=} command line option, AVR 32@item -mmcu=@var{mcu} 33Specify ATMEL AVR instruction set or MCU type. 34 35Instruction set avr1 is for the minimal AVR core, not supported by the C 36compiler, only for assembler programs (MCU types: at90s1200, 37attiny11, attiny12, attiny15, attiny28). 38 39Instruction set avr2 (default) is for the classic AVR core with up to 408K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343, 41attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534, 42at90s8535). 43 44Instruction set avr25 is for the classic AVR core with up to 8K program memory 45space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313, 46attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, 47attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, 48attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 49attiny828, at86rf401, ata6289, ata5272). 50 51Instruction set avr3 is for the classic AVR core with up to 128K program 52memory space (MCU types: at43usb355, at76c711). 53 54Instruction set avr31 is for the classic AVR core with exactly 128K program 55memory space (MCU types: atmega103, at43usb320). 56 57Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP 58instructions (MCU types: attiny167, attiny1634, at90usb82, at90usb162, 59atmega8u2, atmega16u2, atmega32u2, ata5505). 60 61Instruction set avr4 is for the enhanced AVR core with up to 8K program 62memory space (MCU types: atmega48, atmega48a, atmega48pa, atmega48p, atmega8, 63atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, 64atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, 65ata6285, ata6286). 66 67Instruction set avr5 is for the enhanced AVR core with up to 128K program 68memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, 69atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 70atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 71atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, 72atmega324p, atmega324pa, atmega325, atmega325a, atmega32, atmega32a, atmega323, 73atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 74atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, 75atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, 76atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, 77atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, atmega644p, 78atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, 79atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, 80atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, 81atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, at90pwm161, 82at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, 83atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, 84at90scr100, ata5790, ata5795). 85 86Instruction set avr51 is for the enhanced AVR core with exactly 128K 87program memory space (MCU types: atmega128, atmega128a, atmega1280, 88atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, 89atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000). 90 91Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 92(MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). 93 94Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 95program memory space and less than 64K data space (MCU types: 96atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, 97atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, 98atxmega8e5, atxmega32e5, atxmega32x1). 99 100Instruction set avrxmega3 is for the XMEGA AVR core with up to 64K 101of combined program memory and RAM, and with program memory 102visible in the RAM address space (MCU types: 103attiny212, attiny214, attiny412, attiny414, attiny416, attiny417, 104attiny814, attiny816, attiny817, attiny1614, attiny1616, attiny1617, 105attiny3214, attiny3216, attiny3217). 106 107Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 108program memory space and less than 64K data space (MCU types: 109atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, 110atxmega64c3, atxmega64d3, atxmega64d4). 111 112Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 113program memory space and greater than 64K data space (MCU types: 114atxmega64a1, atxmega64a1u). 115 116Instruction set avrxmega6 is for the XMEGA AVR core with larger than 11764K program memory space and less than 64K data space (MCU types: 118atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, 119atxmega192a3, atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, 120atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, 121atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, 122atxmega256d3). 123 124Instruction set avrxmega7 is for the XMEGA AVR core with larger than 12564K program memory space and greater than 64K data space (MCU types: 126atxmega128a1, atxmega128a1u, atxmega128a4u). 127 128Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 129microcontrollers. 130 131@cindex @code{-mall-opcodes} command line option, AVR 132@item -mall-opcodes 133Accept all AVR opcodes, even if not supported by @code{-mmcu}. 134 135@cindex @code{-mno-skip-bug} command line option, AVR 136@item -mno-skip-bug 137This option disable warnings for skipping two-word instructions. 138 139@cindex @code{-mno-wrap} command line option, AVR 140@item -mno-wrap 141This option reject @code{rjmp/rcall} instructions with 8K wrap-around. 142 143@cindex @code{-mrmw} command line option, AVR 144@item -mrmw 145Accept Read-Modify-Write (@code{XCH,LAC,LAS,LAT}) instructions. 146 147@cindex @code{-mlink-relax} command line option, AVR 148@item -mlink-relax 149Enable support for link-time relaxation. This is now on by default 150and this flag no longer has any effect. 151 152@cindex @code{-mno-link-relax} command line option, AVR 153@item -mno-link-relax 154Disable support for link-time relaxation. The assembler will resolve 155relocations when it can, and may be able to better compress some debug 156information. 157 158@cindex @code{-mgcc-isr} command line option, AVR 159@item -mgcc-isr 160Enable the @code{__gcc_isr} pseudo instruction. 161 162@end table 163 164 165@node AVR Syntax 166@section Syntax 167@menu 168* AVR-Chars:: Special Characters 169* AVR-Regs:: Register Names 170* AVR-Modifiers:: Relocatable Expression Modifiers 171@end menu 172 173@node AVR-Chars 174@subsection Special Characters 175 176@cindex line comment character, AVR 177@cindex AVR line comment character 178 179The presence of a @samp{;} anywhere on a line indicates the start of a 180comment that extends to the end of that line. 181 182If a @samp{#} appears as the first character of a line, the whole line 183is treated as a comment, but in this case the line can also be a 184logical line number directive (@pxref{Comments}) or a preprocessor 185control command (@pxref{Preprocessing}). 186 187@cindex line separator, AVR 188@cindex statement separator, AVR 189@cindex AVR line separator 190 191The @samp{$} character can be used instead of a newline to separate 192statements. 193 194@node AVR-Regs 195@subsection Register Names 196 197@cindex AVR register names 198@cindex register names, AVR 199 200The AVR has 32 x 8-bit general purpose working registers @samp{r0}, 201@samp{r1}, ... @samp{r31}. 202Six of the 32 registers can be used as three 16-bit indirect address 203register pointers for Data Space addressing. One of the these address 204pointers can also be used as an address pointer for look up tables in 205Flash program memory. These added function registers are the 16-bit 206@samp{X}, @samp{Y} and @samp{Z} - registers. 207 208@smallexample 209X = @r{r26:r27} 210Y = @r{r28:r29} 211Z = @r{r30:r31} 212@end smallexample 213 214@node AVR-Modifiers 215@subsection Relocatable Expression Modifiers 216 217@cindex AVR modifiers 218@cindex syntax, AVR 219 220The assembler supports several modifiers when using relocatable addresses 221in AVR instruction operands. The general syntax is the following: 222 223@smallexample 224modifier(relocatable-expression) 225@end smallexample 226 227@table @code 228@cindex symbol modifiers 229 230@item lo8 231 232This modifier allows you to use bits 0 through 7 of 233an address expression as 8 bit relocatable expression. 234 235@item hi8 236 237This modifier allows you to use bits 7 through 15 of an address expression 238as 8 bit relocatable expression. This is useful with, for example, the 239AVR @samp{ldi} instruction and @samp{lo8} modifier. 240 241For example 242 243@smallexample 244ldi r26, lo8(sym+10) 245ldi r27, hi8(sym+10) 246@end smallexample 247 248@item hh8 249 250This modifier allows you to use bits 16 through 23 of 251an address expression as 8 bit relocatable expression. 252Also, can be useful for loading 32 bit constants. 253 254@item hlo8 255 256Synonym of @samp{hh8}. 257 258@item hhi8 259 260This modifier allows you to use bits 24 through 31 of 261an expression as 8 bit expression. This is useful with, for example, the 262AVR @samp{ldi} instruction and @samp{lo8}, @samp{hi8}, @samp{hlo8}, 263@samp{hhi8}, modifier. 264 265For example 266 267@smallexample 268ldi r26, lo8(285774925) 269ldi r27, hi8(285774925) 270ldi r28, hlo8(285774925) 271ldi r29, hhi8(285774925) 272; r29,r28,r27,r26 = 285774925 273@end smallexample 274 275@item pm_lo8 276 277This modifier allows you to use bits 0 through 7 of 278an address expression as 8 bit relocatable expression. 279This modifier useful for addressing data or code from 280Flash/Program memory. The using of @samp{pm_lo8} similar 281to @samp{lo8}. 282 283@item pm_hi8 284 285This modifier allows you to use bits 8 through 15 of 286an address expression as 8 bit relocatable expression. 287This modifier useful for addressing data or code from 288Flash/Program memory. 289 290@item pm_hh8 291 292This modifier allows you to use bits 15 through 23 of 293an address expression as 8 bit relocatable expression. 294This modifier useful for addressing data or code from 295Flash/Program memory. 296 297@end table 298 299@node AVR Opcodes 300@section Opcodes 301 302@cindex AVR opcode summary 303@cindex opcode summary, AVR 304@cindex mnemonics, AVR 305@cindex instruction summary, AVR 306For detailed information on the AVR machine instruction set, see 307@url{www.atmel.com/products/AVR}. 308 309@code{@value{AS}} implements all the standard AVR opcodes. 310The following table summarizes the AVR opcodes, and their arguments. 311 312@smallexample 313@i{Legend:} 314 r @r{any register} 315 d @r{`ldi' register (r16-r31)} 316 v @r{`movw' even register (r0, r2, ..., r28, r30)} 317 a @r{`fmul' register (r16-r23)} 318 w @r{`adiw' register (r24,r26,r28,r30)} 319 e @r{pointer registers (X,Y,Z)} 320 b @r{base pointer register and displacement ([YZ]+disp)} 321 z @r{Z pointer register (for [e]lpm Rd,Z[+])} 322 M @r{immediate value from 0 to 255} 323 n @r{immediate value from 0 to 255 ( n = ~M ). Relocation impossible} 324 s @r{immediate value from 0 to 7} 325 P @r{Port address value from 0 to 63. (in, out)} 326 p @r{Port address value from 0 to 31. (cbi, sbi, sbic, sbis)} 327 K @r{immediate value from 0 to 63 (used in `adiw', `sbiw')} 328 i @r{immediate value} 329 l @r{signed pc relative offset from -64 to 63} 330 L @r{signed pc relative offset from -2048 to 2047} 331 h @r{absolute code address (call, jmp)} 332 S @r{immediate value from 0 to 7 (S = s << 4)} 333 ? @r{use this opcode entry if no parameters, else use next opcode entry} 334 3351001010010001000 clc 3361001010011011000 clh 3371001010011111000 cli 3381001010010101000 cln 3391001010011001000 cls 3401001010011101000 clt 3411001010010111000 clv 3421001010010011000 clz 3431001010000001000 sec 3441001010001011000 seh 3451001010001111000 sei 3461001010000101000 sen 3471001010001001000 ses 3481001010001101000 set 3491001010000111000 sev 3501001010000011000 sez 351100101001SSS1000 bclr S 352100101000SSS1000 bset S 3531001010100001001 icall 3541001010000001001 ijmp 3551001010111001000 lpm ? 3561001000ddddd010+ lpm r,z 3571001010111011000 elpm ? 3581001000ddddd011+ elpm r,z 3590000000000000000 nop 3601001010100001000 ret 3611001010100011000 reti 3621001010110001000 sleep 3631001010110011000 break 3641001010110101000 wdr 3651001010111101000 spm 366000111rdddddrrrr adc r,r 367000011rdddddrrrr add r,r 368001000rdddddrrrr and r,r 369000101rdddddrrrr cp r,r 370000001rdddddrrrr cpc r,r 371000100rdddddrrrr cpse r,r 372001001rdddddrrrr eor r,r 373001011rdddddrrrr mov r,r 374100111rdddddrrrr mul r,r 375001010rdddddrrrr or r,r 376000010rdddddrrrr sbc r,r 377000110rdddddrrrr sub r,r 378001001rdddddrrrr clr r 379000011rdddddrrrr lsl r 380000111rdddddrrrr rol r 381001000rdddddrrrr tst r 3820111KKKKddddKKKK andi d,M 3830111KKKKddddKKKK cbr d,n 3841110KKKKddddKKKK ldi d,M 38511101111dddd1111 ser d 3860110KKKKddddKKKK ori d,M 3870110KKKKddddKKKK sbr d,M 3880011KKKKddddKKKK cpi d,M 3890100KKKKddddKKKK sbci d,M 3900101KKKKddddKKKK subi d,M 3911111110rrrrr0sss sbrc r,s 3921111111rrrrr0sss sbrs r,s 3931111100ddddd0sss bld r,s 3941111101ddddd0sss bst r,s 39510110PPdddddPPPP in r,P 39610111PPrrrrrPPPP out P,r 39710010110KKddKKKK adiw w,K 39810010111KKddKKKK sbiw w,K 39910011000pppppsss cbi p,s 40010011010pppppsss sbi p,s 40110011001pppppsss sbic p,s 40210011011pppppsss sbis p,s 403111101lllllll000 brcc l 404111100lllllll000 brcs l 405111100lllllll001 breq l 406111101lllllll100 brge l 407111101lllllll101 brhc l 408111100lllllll101 brhs l 409111101lllllll111 brid l 410111100lllllll111 brie l 411111100lllllll000 brlo l 412111100lllllll100 brlt l 413111100lllllll010 brmi l 414111101lllllll001 brne l 415111101lllllll010 brpl l 416111101lllllll000 brsh l 417111101lllllll110 brtc l 418111100lllllll110 brts l 419111101lllllll011 brvc l 420111100lllllll011 brvs l 421111101lllllllsss brbc s,l 422111100lllllllsss brbs s,l 4231101LLLLLLLLLLLL rcall L 4241100LLLLLLLLLLLL rjmp L 4251001010hhhhh111h call h 4261001010hhhhh110h jmp h 4271001010rrrrr0101 asr r 4281001010rrrrr0000 com r 4291001010rrrrr1010 dec r 4301001010rrrrr0011 inc r 4311001010rrrrr0110 lsr r 4321001010rrrrr0001 neg r 4331001000rrrrr1111 pop r 4341001001rrrrr1111 push r 4351001010rrrrr0111 ror r 4361001010rrrrr0010 swap r 43700000001ddddrrrr movw v,v 43800000010ddddrrrr muls d,d 439000000110ddd0rrr mulsu a,a 440000000110ddd1rrr fmul a,a 441000000111ddd0rrr fmuls a,a 442000000111ddd1rrr fmulsu a,a 4431001001ddddd0000 sts i,r 4441001000ddddd0000 lds r,i 44510o0oo0dddddbooo ldd r,b 446100!000dddddee-+ ld r,e 44710o0oo1rrrrrbooo std b,r 448100!001rrrrree-+ st e,r 4491001010100011001 eicall 4501001010000011001 eijmp 451@end smallexample 452 453@node AVR Pseudo Instructions 454@section Pseudo Instructions 455 456The only available pseudo-instruction @code{__gcc_isr} can be activated by 457option @option{-mgcc-isr}. 458 459@table @code 460 461@item __gcc_isr 1 462Emit code chunk to be used in avr-gcc ISR prologue. 463It will expand to at most six 1-word instructions, all optional: 464push of @code{tmp_reg}, push of @code{SREG}, 465push and clear of @code{zero_reg}, push of @var{Reg}. 466 467@item __gcc_isr 2 468Emit code chunk to be used in an avr-gcc ISR epilogue. 469It will expand to at most five 1-word instructions, all optional: 470pop of @var{Reg}, pop of @code{zero_reg}, 471pop of @code{SREG}, pop of @code{tmp_reg}. 472 473@item __gcc_isr 0, @var{Reg} 474Finish avr-gcc ISR function. Scan code since the last prologue 475for usage of: @code{SREG}, @code{tmp_reg}, @code{zero_reg}. 476Prologue chunk and epilogue chunks will be replaced by appropriate code 477to save / restore @code{SREG}, @code{tmp_reg}, @code{zero_reg} and @var{Reg}. 478 479@end table 480 481Example input: 482 483@example 484__vector1: 485 __gcc_isr 1 486 lds r24, var 487 inc r24 488 sts var, r24 489 __gcc_isr 2 490 reti 491 __gcc_isr 0, r24 492@end example 493 494Example output: 495 496@example 49700000000 <__vector1>: 498 0: 8f 93 push r24 499 2: 8f b7 in r24, 0x3f 500 4: 8f 93 push r24 501 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> 502 a: 83 95 inc r24 503 c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> 504 10: 8f 91 pop r24 505 12: 8f bf out 0x3f, r24 506 14: 8f 91 pop r24 507 16: 18 95 reti 508@end example 509