1This is as.info, produced by makeinfo version 4.8 from as.texinfo. 2 3INFO-DIR-SECTION Software development 4START-INFO-DIR-ENTRY 5* As: (as). The GNU assembler. 6* Gas: (as). The GNU assembler. 7END-INFO-DIR-ENTRY 8 9 This file documents the GNU Assembler "as". 10 11 Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 122000, 2001, 2002, 2006, 2007, 2008, 2009, 2010, 2011 Free Software 13Foundation, Inc. 14 15 Permission is granted to copy, distribute and/or modify this document 16under the terms of the GNU Free Documentation License, Version 1.3 or 17any later version published by the Free Software Foundation; with no 18Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 19Texts. A copy of the license is included in the section entitled "GNU 20Free Documentation License". 21 22 23File: as.info, Node: Top, Next: Overview, Up: (dir) 24 25Using as 26******** 27 28This file is a user guide to the GNU assembler `as' (GNU Binutils) 29version 2.21.1. 30 31 This document is distributed under the terms of the GNU Free 32Documentation License. A copy of the license is included in the 33section entitled "GNU Free Documentation License". 34 35* Menu: 36 37* Overview:: Overview 38* Invoking:: Command-Line Options 39* Syntax:: Syntax 40* Sections:: Sections and Relocation 41* Symbols:: Symbols 42* Expressions:: Expressions 43* Pseudo Ops:: Assembler Directives 44 45* Object Attributes:: Object Attributes 46* Machine Dependencies:: Machine Dependent Features 47* Reporting Bugs:: Reporting Bugs 48* Acknowledgements:: Who Did What 49* GNU Free Documentation License:: GNU Free Documentation License 50* AS Index:: AS Index 51 52 53File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 54 551 Overview 56********** 57 58Here is a brief summary of how to invoke `as'. For details, see *Note 59Command-Line Options: Invoking. 60 61 as [-a[cdghlns][=FILE]] [-alternate] [-D] 62 [-compress-debug-sections] [-nocompress-debug-sections] 63 [-debug-prefix-map OLD=NEW] 64 [-defsym SYM=VAL] [-f] [-g] [-gstabs] 65 [-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J] 66 [-K] [-L] [-listing-lhs-width=NUM] 67 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] 68 [-listing-cont-lines=NUM] [-keep-locals] [-o 69 OBJFILE] [-R] [-reduce-memory-overheads] [-statistics] 70 [-v] [-version] [-version] [-W] [-warn] 71 [-fatal-warnings] [-w] [-x] [-Z] [@FILE] 72 [-size-check=[error|warning]] 73 [-target-help] [TARGET-OPTIONS] 74 [-|FILES ...] 75 76 _Target Alpha options:_ 77 [-mCPU] 78 [-mdebug | -no-mdebug] 79 [-replace | -noreplace] 80 [-relax] [-g] [-GSIZE] 81 [-F] [-32addr] 82 83 _Target ARC options:_ 84 [-marc[5|6|7|8]] 85 [-EB|-EL] 86 87 _Target ARM options:_ 88 [-mcpu=PROCESSOR[+EXTENSION...]] 89 [-march=ARCHITECTURE[+EXTENSION...]] 90 [-mfpu=FLOATING-POINT-FORMAT] 91 [-mfloat-abi=ABI] 92 [-meabi=VER] 93 [-mthumb] 94 [-EB|-EL] 95 [-mapcs-32|-mapcs-26|-mapcs-float| 96 -mapcs-reentrant] 97 [-mthumb-interwork] [-k] 98 99 _Target Blackfin options:_ 100 [-mcpu=PROCESSOR[-SIREVISION]] 101 [-mfdpic] 102 [-mno-fdpic] 103 [-mnopic] 104 105 _Target CRIS options:_ 106 [-underscore | -no-underscore] 107 [-pic] [-N] 108 [-emulation=criself | -emulation=crisaout] 109 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] 110 111 _Target D10V options:_ 112 [-O] 113 114 _Target D30V options:_ 115 [-O|-n|-N] 116 117 _Target H8/300 options:_ 118 [-h-tick-hex] 119 120 _Target i386 options:_ 121 [-32|-64] [-n] 122 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 123 124 _Target i960 options:_ 125 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB| 126 -AKC|-AMC] 127 [-b] [-no-relax] 128 129 _Target IA-64 options:_ 130 [-mconstant-gp|-mauto-pic] 131 [-milp32|-milp64|-mlp64|-mp64] 132 [-mle|mbe] 133 [-mtune=itanium1|-mtune=itanium2] 134 [-munwind-check=warning|-munwind-check=error] 135 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 136 [-x|-xexplicit] [-xauto] [-xdebug] 137 138 _Target IP2K options:_ 139 [-mip2022|-mip2022ext] 140 141 _Target M32C options:_ 142 [-m32c|-m16c] [-relax] [-h-tick-hex] 143 144 _Target M32R options:_ 145 [-m32rx|-[no-]warn-explicit-parallel-conflicts| 146 -W[n]p] 147 148 _Target M680X0 options:_ 149 [-l] [-m68000|-m68010|-m68020|...] 150 151 _Target M68HC11 options:_ 152 [-m68hc11|-m68hc12|-m68hcs12] 153 [-mshort|-mlong] 154 [-mshort-double|-mlong-double] 155 [-force-long-branches] [-short-branches] 156 [-strict-direct-mode] [-print-insn-syntax] 157 [-print-opcodes] [-generate-example] 158 159 _Target MCORE options:_ 160 [-jsri2bsr] [-sifilter] [-relax] 161 [-mcpu=[210|340]] 162 _Target MICROBLAZE options:_ 163 164 _Target MIPS options:_ 165 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 166 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 167 [-non_shared] [-xgot [-mvxworks-pic] 168 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 169 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 170 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 171 [-mips64] [-mips64r2] 172 [-construct-floats] [-no-construct-floats] 173 [-trap] [-no-break] [-break] [-no-trap] 174 [-mips16] [-no-mips16] 175 [-msmartmips] [-mno-smartmips] 176 [-mips3d] [-no-mips3d] 177 [-mdmx] [-no-mdmx] 178 [-mdsp] [-mno-dsp] 179 [-mdspr2] [-mno-dspr2] 180 [-mmt] [-mno-mt] 181 [-mfix7000] [-mno-fix7000] 182 [-mfix-vr4120] [-mno-fix-vr4120] 183 [-mfix-vr4130] [-mno-fix-vr4130] 184 [-mdebug] [-no-mdebug] 185 [-mpdr] [-mno-pdr] 186 187 _Target MMIX options:_ 188 [-fixed-special-register-names] [-globalize-symbols] 189 [-gnu-syntax] [-relax] [-no-predefined-symbols] 190 [-no-expand] [-no-merge-gregs] [-x] 191 [-linker-allocated-gregs] 192 193 _Target PDP11 options:_ 194 [-mpic|-mno-pic] [-mall] [-mno-extensions] 195 [-mEXTENSION|-mno-EXTENSION] 196 [-mCPU] [-mMACHINE] 197 198 _Target picoJava options:_ 199 [-mb|-me] 200 201 _Target PowerPC options:_ 202 [-a32|-a64] 203 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| 204 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64| 205 -m620|-me500|-e500x2|-me500mc|-me500mc64|-mppc64bridge|-mbooke| 206 -mpower4|-mpr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6| 207 -mpower7|-mpw7|-ma2|-mcell|-mspe|-mtitan|-me300|-mcom] 208 [-many] [-maltivec|-mvsx] 209 [-mregnames|-mno-regnames] 210 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] 211 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] 212 [-msolaris|-mno-solaris] 213 [-nops=COUNT] 214 215 _Target RX options:_ 216 [-mlittle-endian|-mbig-endian] 217 [-m32bit-ints|-m16bit-ints] 218 [-m32bit-doubles|-m64bit-doubles] 219 220 _Target s390 options:_ 221 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 222 [-mregnames|-mno-regnames] 223 [-mwarn-areg-zero] 224 225 _Target SCORE options:_ 226 [-EB][-EL][-FIXDD][-NWARN] 227 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 228 [-march=score7][-march=score3] 229 [-USE_R1][-KPIC][-O0][-G NUM][-V] 230 231 _Target SPARC options:_ 232 [-Av6|-Av7|-Av8|-Asparclet|-Asparclite 233 -Av8plus|-Av8plusa|-Av9|-Av9a] 234 [-xarch=v8plus|-xarch=v8plusa] [-bump] 235 [-32|-64] 236 237 _Target TIC54X options:_ 238 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 239 [-merrors-to-file <FILENAME>|-me <FILENAME>] 240 241 242 _Target TIC6X options:_ 243 [-march=ARCH] [-matomic|-mno-atomic] 244 [-mbig-endian|-mlittle-endian] [-mdsbt|-mno-dsbt] 245 [-mpid=no|-mpid=near|-mpid=far] [-mpic|-mno-pic] 246 247 248 _Target Z80 options:_ 249 [-z80] [-r800] 250 [ -ignore-undocumented-instructions] [-Wnud] 251 [ -ignore-unportable-instructions] [-Wnup] 252 [ -warn-undocumented-instructions] [-Wud] 253 [ -warn-unportable-instructions] [-Wup] 254 [ -forbid-undocumented-instructions] [-Fud] 255 [ -forbid-unportable-instructions] [-Fup] 256 257 258 _Target Xtensa options:_ 259 [-[no-]text-section-literals] [-[no-]absolute-literals] 260 [-[no-]target-align] [-[no-]longcalls] 261 [-[no-]transform] 262 [-rename-section OLDNAME=NEWNAME] 263 264`@FILE' 265 Read command-line options from FILE. The options read are 266 inserted in place of the original @FILE option. If FILE does not 267 exist, or cannot be read, then the option will be treated 268 literally, and not removed. 269 270 Options in FILE are separated by whitespace. A whitespace 271 character may be included in an option by surrounding the entire 272 option in either single or double quotes. Any character 273 (including a backslash) may be included by prefixing the character 274 to be included with a backslash. The FILE may itself contain 275 additional @FILE options; any such options will be processed 276 recursively. 277 278`-a[cdghlmns]' 279 Turn on listings, in any of a variety of ways: 280 281 `-ac' 282 omit false conditionals 283 284 `-ad' 285 omit debugging directives 286 287 `-ag' 288 include general information, like as version and options 289 passed 290 291 `-ah' 292 include high-level source 293 294 `-al' 295 include assembly 296 297 `-am' 298 include macro expansions 299 300 `-an' 301 omit forms processing 302 303 `-as' 304 include symbols 305 306 `=file' 307 set the name of the listing file 308 309 You may combine these options; for example, use `-aln' for assembly 310 listing without forms processing. The `=file' option, if used, 311 must be the last one. By itself, `-a' defaults to `-ahls'. 312 313`--alternate' 314 Begin in alternate macro mode. *Note `.altmacro': Altmacro. 315 316`--compress-debug-sections' 317 Compress DWARF debug sections using zlib. The debug sections are 318 renamed to begin with `.zdebug', and the resulting object file may 319 not be compatible with older linkers and object file utilities. 320 321`--nocompress-debug-sections' 322 Do not compress DWARF debug sections. This is the default. 323 324`-D' 325 Ignored. This option is accepted for script compatibility with 326 calls to other assemblers. 327 328`--debug-prefix-map OLD=NEW' 329 When assembling files in directory `OLD', record debugging 330 information describing them as in `NEW' instead. 331 332`--defsym SYM=VALUE' 333 Define the symbol SYM to be VALUE before assembling the input file. 334 VALUE must be an integer constant. As in C, a leading `0x' 335 indicates a hexadecimal value, and a leading `0' indicates an octal 336 value. The value of the symbol can be overridden inside a source 337 file via the use of a `.set' pseudo-op. 338 339`-f' 340 "fast"--skip whitespace and comment preprocessing (assume source is 341 compiler output). 342 343`-g' 344`--gen-debug' 345 Generate debugging information for each assembler source line 346 using whichever debug format is preferred by the target. This 347 currently means either STABS, ECOFF or DWARF2. 348 349`--gstabs' 350 Generate stabs debugging information for each assembler line. This 351 may help debugging assembler code, if the debugger can handle it. 352 353`--gstabs+' 354 Generate stabs debugging information for each assembler line, with 355 GNU extensions that probably only gdb can handle, and that could 356 make other debuggers crash or refuse to read your program. This 357 may help debugging assembler code. Currently the only GNU 358 extension is the location of the current working directory at 359 assembling time. 360 361`--gdwarf-2' 362 Generate DWARF2 debugging information for each assembler line. 363 This may help debugging assembler code, if the debugger can handle 364 it. Note--this option is only supported by some targets, not all 365 of them. 366 367`--size-check=error' 368`--size-check=warning' 369 Issue an error or warning for invalid ELF .size directive. 370 371`--help' 372 Print a summary of the command line options and exit. 373 374`--target-help' 375 Print a summary of all target specific options and exit. 376 377`-I DIR' 378 Add directory DIR to the search list for `.include' directives. 379 380`-J' 381 Don't warn about signed overflow. 382 383`-K' 384 Issue warnings when difference tables altered for long 385 displacements. 386 387`-L' 388`--keep-locals' 389 Keep (in the symbol table) local symbols. These symbols start with 390 system-specific local label prefixes, typically `.L' for ELF 391 systems or `L' for traditional a.out systems. *Note Symbol 392 Names::. 393 394`--listing-lhs-width=NUMBER' 395 Set the maximum width, in words, of the output data column for an 396 assembler listing to NUMBER. 397 398`--listing-lhs-width2=NUMBER' 399 Set the maximum width, in words, of the output data column for 400 continuation lines in an assembler listing to NUMBER. 401 402`--listing-rhs-width=NUMBER' 403 Set the maximum width of an input source line, as displayed in a 404 listing, to NUMBER bytes. 405 406`--listing-cont-lines=NUMBER' 407 Set the maximum number of lines printed in a listing for a single 408 line of input to NUMBER + 1. 409 410`-o OBJFILE' 411 Name the object-file output from `as' OBJFILE. 412 413`-R' 414 Fold the data section into the text section. 415 416 Set the default size of GAS's hash tables to a prime number close 417 to NUMBER. Increasing this value can reduce the length of time it 418 takes the assembler to perform its tasks, at the expense of 419 increasing the assembler's memory requirements. Similarly 420 reducing this value can reduce the memory requirements at the 421 expense of speed. 422 423`--reduce-memory-overheads' 424 This option reduces GAS's memory requirements, at the expense of 425 making the assembly processes slower. Currently this switch is a 426 synonym for `--hash-size=4051', but in the future it may have 427 other effects as well. 428 429`--statistics' 430 Print the maximum space (in bytes) and total time (in seconds) 431 used by assembly. 432 433`--strip-local-absolute' 434 Remove local absolute symbols from the outgoing symbol table. 435 436`-v' 437`-version' 438 Print the `as' version. 439 440`--version' 441 Print the `as' version and exit. 442 443`-W' 444`--no-warn' 445 Suppress warning messages. 446 447`--fatal-warnings' 448 Treat warnings as errors. 449 450`--warn' 451 Don't suppress warning messages or treat them as errors. 452 453`-w' 454 Ignored. 455 456`-x' 457 Ignored. 458 459`-Z' 460 Generate an object file even after errors. 461 462`-- | FILES ...' 463 Standard input, or source files to assemble. 464 465 466 The following options are available when as is configured for an ARC 467processor. 468 469`-marc[5|6|7|8]' 470 This option selects the core processor variant. 471 472`-EB | -EL' 473 Select either big-endian (-EB) or little-endian (-EL) output. 474 475 The following options are available when as is configured for the ARM 476processor family. 477 478`-mcpu=PROCESSOR[+EXTENSION...]' 479 Specify which ARM processor variant is the target. 480 481`-march=ARCHITECTURE[+EXTENSION...]' 482 Specify which ARM architecture variant is used by the target. 483 484`-mfpu=FLOATING-POINT-FORMAT' 485 Select which Floating Point architecture is the target. 486 487`-mfloat-abi=ABI' 488 Select which floating point ABI is in use. 489 490`-mthumb' 491 Enable Thumb only instruction decoding. 492 493`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' 494 Select which procedure calling convention is in use. 495 496`-EB | -EL' 497 Select either big-endian (-EB) or little-endian (-EL) output. 498 499`-mthumb-interwork' 500 Specify that the code has been generated with interworking between 501 Thumb and ARM code in mind. 502 503`-k' 504 Specify that PIC code has been generated. 505 506 The following options are available when as is configured for the 507Blackfin processor family. 508 509`-mcpu=PROCESSOR[-SIREVISION]' 510 This option specifies the target processor. The optional 511 SIREVISION is not used in assembler. 512 513`-mfdpic' 514 Assemble for the FDPIC ABI. 515 516`-mno-fdpic' 517`-mnopic' 518 Disable -mfdpic. 519 520 See the info pages for documentation of the CRIS-specific options. 521 522 The following options are available when as is configured for a D10V 523processor. 524`-O' 525 Optimize output by parallelizing instructions. 526 527 The following options are available when as is configured for a D30V 528processor. 529`-O' 530 Optimize output by parallelizing instructions. 531 532`-n' 533 Warn when nops are generated. 534 535`-N' 536 Warn when a nop after a 32-bit multiply instruction is generated. 537 538 The following options are available when as is configured for the 539Intel 80960 processor. 540 541`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 542 Specify which variant of the 960 architecture is the target. 543 544`-b' 545 Add code to collect statistics about branches taken. 546 547`-no-relax' 548 Do not alter compare-and-branch instructions for long 549 displacements; error if necessary. 550 551 552 The following options are available when as is configured for the 553Ubicom IP2K series. 554 555`-mip2022ext' 556 Specifies that the extended IP2022 instructions are allowed. 557 558`-mip2022' 559 Restores the default behaviour, which restricts the permitted 560 instructions to just the basic IP2022 ones. 561 562 563 The following options are available when as is configured for the 564Renesas M32C and M16C processors. 565 566`-m32c' 567 Assemble M32C instructions. 568 569`-m16c' 570 Assemble M16C instructions (the default). 571 572`-relax' 573 Enable support for link-time relaxations. 574 575`-h-tick-hex' 576 Support H'00 style hex constants in addition to 0x00 style. 577 578 579 The following options are available when as is configured for the 580Renesas M32R (formerly Mitsubishi M32R) series. 581 582`--m32rx' 583 Specify which processor in the M32R family is the target. The 584 default is normally the M32R, but this option changes it to the 585 M32RX. 586 587`--warn-explicit-parallel-conflicts or --Wp' 588 Produce warning messages when questionable parallel constructs are 589 encountered. 590 591`--no-warn-explicit-parallel-conflicts or --Wnp' 592 Do not produce warning messages when questionable parallel 593 constructs are encountered. 594 595 596 The following options are available when as is configured for the 597Motorola 68000 series. 598 599`-l' 600 Shorten references to undefined symbols, to one word instead of 601 two. 602 603`-m68000 | -m68008 | -m68010 | -m68020 | -m68030' 604`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' 605`| -m68333 | -m68340 | -mcpu32 | -m5200' 606 Specify what processor in the 68000 family is the target. The 607 default is normally the 68020, but this can be changed at 608 configuration time. 609 610`-m68881 | -m68882 | -mno-68881 | -mno-68882' 611 The target machine does (or does not) have a floating-point 612 coprocessor. The default is to assume a coprocessor for 68020, 613 68030, and cpu32. Although the basic 68000 is not compatible with 614 the 68881, a combination of the two can be specified, since it's 615 possible to do emulation of the coprocessor instructions with the 616 main processor. 617 618`-m68851 | -mno-68851' 619 The target machine does (or does not) have a memory-management 620 unit coprocessor. The default is to assume an MMU for 68020 and 621 up. 622 623 624 For details about the PDP-11 machine dependent features options, see 625*Note PDP-11-Options::. 626 627`-mpic | -mno-pic' 628 Generate position-independent (or position-dependent) code. The 629 default is `-mpic'. 630 631`-mall' 632`-mall-extensions' 633 Enable all instruction set extensions. This is the default. 634 635`-mno-extensions' 636 Disable all instruction set extensions. 637 638`-mEXTENSION | -mno-EXTENSION' 639 Enable (or disable) a particular instruction set extension. 640 641`-mCPU' 642 Enable the instruction set extensions supported by a particular 643 CPU, and disable all other extensions. 644 645`-mMACHINE' 646 Enable the instruction set extensions supported by a particular 647 machine model, and disable all other extensions. 648 649 The following options are available when as is configured for a 650picoJava processor. 651 652`-mb' 653 Generate "big endian" format output. 654 655`-ml' 656 Generate "little endian" format output. 657 658 659 The following options are available when as is configured for the 660Motorola 68HC11 or 68HC12 series. 661 662`-m68hc11 | -m68hc12 | -m68hcs12' 663 Specify what processor is the target. The default is defined by 664 the configuration option when building the assembler. 665 666`-mshort' 667 Specify to use the 16-bit integer ABI. 668 669`-mlong' 670 Specify to use the 32-bit integer ABI. 671 672`-mshort-double' 673 Specify to use the 32-bit double ABI. 674 675`-mlong-double' 676 Specify to use the 64-bit double ABI. 677 678`--force-long-branches' 679 Relative branches are turned into absolute ones. This concerns 680 conditional branches, unconditional branches and branches to a sub 681 routine. 682 683`-S | --short-branches' 684 Do not turn relative branches into absolute ones when the offset 685 is out of range. 686 687`--strict-direct-mode' 688 Do not turn the direct addressing mode into extended addressing 689 mode when the instruction does not support direct addressing mode. 690 691`--print-insn-syntax' 692 Print the syntax of instruction in case of error. 693 694`--print-opcodes' 695 print the list of instructions with syntax and then exit. 696 697`--generate-example' 698 print an example of instruction for each possible instruction and 699 then exit. This option is only useful for testing `as'. 700 701 702 The following options are available when `as' is configured for the 703SPARC architecture: 704 705`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 706`-Av8plus | -Av8plusa | -Av9 | -Av9a' 707 Explicitly select a variant of the SPARC architecture. 708 709 `-Av8plus' and `-Av8plusa' select a 32 bit environment. `-Av9' 710 and `-Av9a' select a 64 bit environment. 711 712 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 713 UltraSPARC extensions. 714 715`-xarch=v8plus | -xarch=v8plusa' 716 For compatibility with the Solaris v9 assembler. These options are 717 equivalent to -Av8plus and -Av8plusa, respectively. 718 719`-bump' 720 Warn when the assembler switches to another architecture. 721 722 The following options are available when as is configured for the 723'c54x architecture. 724 725`-mfar-mode' 726 Enable extended addressing mode. All addresses and relocations 727 will assume extended addressing (usually 23 bits). 728 729`-mcpu=CPU_VERSION' 730 Sets the CPU version being compiled for. 731 732`-merrors-to-file FILENAME' 733 Redirect error output to a file, for broken systems which don't 734 support such behaviour in the shell. 735 736 The following options are available when as is configured for a MIPS 737processor. 738 739`-G NUM' 740 This option sets the largest size of an object that can be 741 referenced implicitly with the `gp' register. It is only accepted 742 for targets that use ECOFF format, such as a DECstation running 743 Ultrix. The default value is 8. 744 745`-EB' 746 Generate "big endian" format output. 747 748`-EL' 749 Generate "little endian" format output. 750 751`-mips1' 752`-mips2' 753`-mips3' 754`-mips4' 755`-mips5' 756`-mips32' 757`-mips32r2' 758`-mips64' 759`-mips64r2' 760 Generate code for a particular MIPS Instruction Set Architecture 761 level. `-mips1' is an alias for `-march=r3000', `-mips2' is an 762 alias for `-march=r6000', `-mips3' is an alias for `-march=r4000' 763 and `-mips4' is an alias for `-march=r8000'. `-mips5', `-mips32', 764 `-mips32r2', `-mips64', and `-mips64r2' correspond to generic 765 `MIPS V', `MIPS32', `MIPS32 Release 2', `MIPS64', and `MIPS64 766 Release 2' ISA processors, respectively. 767 768`-march=CPU' 769 Generate code for a particular MIPS cpu. 770 771`-mtune=CPU' 772 Schedule and tune for a particular MIPS cpu. 773 774`-mfix7000' 775`-mno-fix7000' 776 Cause nops to be inserted if the read of the destination register 777 of an mfhi or mflo instruction occurs in the following two 778 instructions. 779 780`-mdebug' 781`-no-mdebug' 782 Cause stabs-style debugging output to go into an ECOFF-style 783 .mdebug section instead of the standard ELF .stabs sections. 784 785`-mpdr' 786`-mno-pdr' 787 Control generation of `.pdr' sections. 788 789`-mgp32' 790`-mfp32' 791 The register sizes are normally inferred from the ISA and ABI, but 792 these flags force a certain group of registers to be treated as 32 793 bits wide at all times. `-mgp32' controls the size of 794 general-purpose registers and `-mfp32' controls the size of 795 floating-point registers. 796 797`-mips16' 798`-no-mips16' 799 Generate code for the MIPS 16 processor. This is equivalent to 800 putting `.set mips16' at the start of the assembly file. 801 `-no-mips16' turns off this option. 802 803`-msmartmips' 804`-mno-smartmips' 805 Enables the SmartMIPS extension to the MIPS32 instruction set. 806 This is equivalent to putting `.set smartmips' at the start of the 807 assembly file. `-mno-smartmips' turns off this option. 808 809`-mips3d' 810`-no-mips3d' 811 Generate code for the MIPS-3D Application Specific Extension. 812 This tells the assembler to accept MIPS-3D instructions. 813 `-no-mips3d' turns off this option. 814 815`-mdmx' 816`-no-mdmx' 817 Generate code for the MDMX Application Specific Extension. This 818 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 819 off this option. 820 821`-mdsp' 822`-mno-dsp' 823 Generate code for the DSP Release 1 Application Specific Extension. 824 This tells the assembler to accept DSP Release 1 instructions. 825 `-mno-dsp' turns off this option. 826 827`-mdspr2' 828`-mno-dspr2' 829 Generate code for the DSP Release 2 Application Specific Extension. 830 This option implies -mdsp. This tells the assembler to accept DSP 831 Release 2 instructions. `-mno-dspr2' turns off this option. 832 833`-mmt' 834`-mno-mt' 835 Generate code for the MT Application Specific Extension. This 836 tells the assembler to accept MT instructions. `-mno-mt' turns 837 off this option. 838 839`--construct-floats' 840`--no-construct-floats' 841 The `--no-construct-floats' option disables the construction of 842 double width floating point constants by loading the two halves of 843 the value into the two single width floating point registers that 844 make up the double width register. By default 845 `--construct-floats' is selected, allowing construction of these 846 floating point constants. 847 848`--emulation=NAME' 849 This option causes `as' to emulate `as' configured for some other 850 target, in all respects, including output format (choosing between 851 ELF and ECOFF only), handling of pseudo-opcodes which may generate 852 debugging information or store symbol table information, and 853 default endianness. The available configuration names are: 854 `mipsecoff', `mipself', `mipslecoff', `mipsbecoff', `mipslelf', 855 `mipsbelf'. The first two do not alter the default endianness 856 from that of the primary target for which the assembler was 857 configured; the others change the default to little- or big-endian 858 as indicated by the `b' or `l' in the name. Using `-EB' or `-EL' 859 will override the endianness selection in any case. 860 861 This option is currently supported only when the primary target 862 `as' is configured for is a MIPS ELF or ECOFF target. 863 Furthermore, the primary target or others specified with 864 `--enable-targets=...' at configuration time must include support 865 for the other format, if both are to be available. For example, 866 the Irix 5 configuration includes support for both. 867 868 Eventually, this option will support more configurations, with more 869 fine-grained control over the assembler's behavior, and will be 870 supported for more processors. 871 872`-nocpp' 873 `as' ignores this option. It is accepted for compatibility with 874 the native tools. 875 876`--trap' 877`--no-trap' 878`--break' 879`--no-break' 880 Control how to deal with multiplication overflow and division by 881 zero. `--trap' or `--no-break' (which are synonyms) take a trap 882 exception (and only work for Instruction Set Architecture level 2 883 and higher); `--break' or `--no-trap' (also synonyms, and the 884 default) take a break exception. 885 886`-n' 887 When this option is used, `as' will issue a warning every time it 888 generates a nop instruction from a macro. 889 890 The following options are available when as is configured for an 891MCore processor. 892 893`-jsri2bsr' 894`-nojsri2bsr' 895 Enable or disable the JSRI to BSR transformation. By default this 896 is enabled. The command line option `-nojsri2bsr' can be used to 897 disable it. 898 899`-sifilter' 900`-nosifilter' 901 Enable or disable the silicon filter behaviour. By default this 902 is disabled. The default can be overridden by the `-sifilter' 903 command line option. 904 905`-relax' 906 Alter jump instructions for long displacements. 907 908`-mcpu=[210|340]' 909 Select the cpu type on the target hardware. This controls which 910 instructions can be assembled. 911 912`-EB' 913 Assemble for a big endian target. 914 915`-EL' 916 Assemble for a little endian target. 917 918 919 See the info pages for documentation of the MMIX-specific options. 920 921 See the info pages for documentation of the RX-specific options. 922 923 The following options are available when as is configured for the 924s390 processor family. 925 926`-m31' 927`-m64' 928 Select the word size, either 31/32 bits or 64 bits. 929 930`-mesa' 931 932`-mzarch' 933 Select the architecture mode, either the Enterprise System 934 Architecture (esa) or the z/Architecture mode (zarch). 935 936`-march=PROCESSOR' 937 Specify which s390 processor variant is the target, `g6', `g6', 938 `z900', `z990', `z9-109', `z9-ec', or `z10'. 939 940`-mregnames' 941`-mno-regnames' 942 Allow or disallow symbolic names for registers. 943 944`-mwarn-areg-zero' 945 Warn whenever the operand for a base or index register has been 946 specified but evaluates to zero. 947 948 The following options are available when as is configured for a 949TMS320C6000 processor. 950 951`-march=ARCH' 952 Enable (only) instructions from architecture ARCH. By default, 953 all instructions are permitted. 954 955 The following values of ARCH are accepted: `c62x', `c64x', 956 `c64x+', `c67x', `c67x+', `c674x'. 957 958`-matomic' 959`-mno-atomic' 960 Enable or disable the optional C64x+ atomic operation instructions. 961 By default, they are enabled if no `-march' option is given, or if 962 an architecture is specified with `-march' that implies these 963 instructions are present (currently, there are no such 964 architectures); they are disabled if an architecture is specified 965 with `-march' on which the instructions are optional or not 966 present. This option overrides such a default from the 967 architecture, independent of the order in which the `-march' or 968 `-matomic' or `-mno-atomic' options are passed. 969 970`-mdsbt' 971`-mno-dsbt' 972 The `-mdsbt' option causes the assembler to generate the 973 `Tag_ABI_DSBT' attribute with a value of 1, indicating that the 974 code is using DSBT addressing. The `-mno-dsbt' option, the 975 default, causes the tag to have a value of 0, indicating that the 976 code does not use DSBT addressing. The linker will emit a warning 977 if objects of different type (DSBT and non-DSBT) are linked 978 together. 979 980`-mpid=no' 981`-mpid=near' 982`-mpid=far' 983 The `-mpid=' option causes the assembler to generate the 984 `Tag_ABI_PID' attribute with a value indicating the form of data 985 addressing used by the code. `-mpid=no', the default, indicates 986 position-dependent data addressing, `-mpid=near' indicates 987 position-independent addressing with GOT accesses using near DP 988 addressing, and `-mpid=far' indicates position-independent 989 addressing with GOT accesses using far DP addressing. The linker 990 will emit a warning if objects built with different settings of 991 this option are linked together. 992 993`-mpic' 994`-mno-pic' 995 The `-mpic' option causes the assembler to generate the 996 `Tag_ABI_PIC' attribute with a value of 1, indicating that the 997 code is using position-independent code addressing, The 998 `-mno-pic' option, the default, causes the tag to have a value of 999 0, indicating position-dependent code addressing. The linker will 1000 emit a warning if objects of different type (position-dependent and 1001 position-independent) are linked together. 1002 1003`-mbig-endian' 1004`-mlittle-endian' 1005 Generate code for the specified endianness. The default is 1006 little-endian. 1007 1008 The following options are available when as is configured for an 1009Xtensa processor. 1010 1011`--text-section-literals | --no-text-section-literals' 1012 With `--text-section-literals', literal pools are interspersed in 1013 the text section. The default is `--no-text-section-literals', 1014 which places literals in a separate section in the output file. 1015 These options only affect literals referenced via PC-relative 1016 `L32R' instructions; literals for absolute mode `L32R' 1017 instructions are handled separately. 1018 1019`--absolute-literals | --no-absolute-literals' 1020 Indicate to the assembler whether `L32R' instructions use absolute 1021 or PC-relative addressing. The default is to assume absolute 1022 addressing if the Xtensa processor includes the absolute `L32R' 1023 addressing option. Otherwise, only the PC-relative `L32R' mode 1024 can be used. 1025 1026`--target-align | --no-target-align' 1027 Enable or disable automatic alignment to reduce branch penalties 1028 at the expense of some code density. The default is 1029 `--target-align'. 1030 1031`--longcalls | --no-longcalls' 1032 Enable or disable transformation of call instructions to allow 1033 calls across a greater range of addresses. The default is 1034 `--no-longcalls'. 1035 1036`--transform | --no-transform' 1037 Enable or disable all assembler transformations of Xtensa 1038 instructions. The default is `--transform'; `--no-transform' 1039 should be used only in the rare cases when the instructions must 1040 be exactly as specified in the assembly source. 1041 1042`--rename-section OLDNAME=NEWNAME' 1043 When generating output sections, rename the OLDNAME section to 1044 NEWNAME. 1045 1046 The following options are available when as is configured for a Z80 1047family processor. 1048`-z80' 1049 Assemble for Z80 processor. 1050 1051`-r800' 1052 Assemble for R800 processor. 1053 1054`-ignore-undocumented-instructions' 1055`-Wnud' 1056 Assemble undocumented Z80 instructions that also work on R800 1057 without warning. 1058 1059`-ignore-unportable-instructions' 1060`-Wnup' 1061 Assemble all undocumented Z80 instructions without warning. 1062 1063`-warn-undocumented-instructions' 1064`-Wud' 1065 Issue a warning for undocumented Z80 instructions that also work 1066 on R800. 1067 1068`-warn-unportable-instructions' 1069`-Wup' 1070 Issue a warning for undocumented Z80 instructions that do not work 1071 on R800. 1072 1073`-forbid-undocumented-instructions' 1074`-Fud' 1075 Treat all undocumented instructions as errors. 1076 1077`-forbid-unportable-instructions' 1078`-Fup' 1079 Treat undocumented Z80 instructions that do not work on R800 as 1080 errors. 1081 1082* Menu: 1083 1084* Manual:: Structure of this Manual 1085* GNU Assembler:: The GNU Assembler 1086* Object Formats:: Object File Formats 1087* Command Line:: Command Line 1088* Input Files:: Input Files 1089* Object:: Output (Object) File 1090* Errors:: Error and Warning Messages 1091 1092 1093File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1094 10951.1 Structure of this Manual 1096============================ 1097 1098This manual is intended to describe what you need to know to use GNU 1099`as'. We cover the syntax expected in source files, including notation 1100for symbols, constants, and expressions; the directives that `as' 1101understands; and of course how to invoke `as'. 1102 1103 This manual also describes some of the machine-dependent features of 1104various flavors of the assembler. 1105 1106 On the other hand, this manual is _not_ intended as an introduction 1107to programming in assembly language--let alone programming in general! 1108In a similar vein, we make no attempt to introduce the machine 1109architecture; we do _not_ describe the instruction set, standard 1110mnemonics, registers or addressing modes that are standard to a 1111particular architecture. You may want to consult the manufacturer's 1112machine architecture manual for this information. 1113 1114 1115File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1116 11171.2 The GNU Assembler 1118===================== 1119 1120GNU `as' is really a family of assemblers. If you use (or have used) 1121the GNU assembler on one architecture, you should find a fairly similar 1122environment when you use it on another architecture. Each version has 1123much in common with the others, including object file formats, most 1124assembler directives (often called "pseudo-ops") and assembler syntax. 1125 1126 `as' is primarily intended to assemble the output of the GNU C 1127compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried 1128to make `as' assemble correctly everything that other assemblers for 1129the same machine would assemble. Any exceptions are documented 1130explicitly (*note Machine Dependencies::). This doesn't mean `as' 1131always uses the same syntax as another assembler for the same 1132architecture; for example, we know of several incompatible versions of 1133680x0 assembly language syntax. 1134 1135 Unlike older assemblers, `as' is designed to assemble a source 1136program in one pass of the source file. This has a subtle impact on the 1137`.org' directive (*note `.org': Org.). 1138 1139 1140File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1141 11421.3 Object File Formats 1143======================= 1144 1145The GNU assembler can be configured to produce several alternative 1146object file formats. For the most part, this does not affect how you 1147write assembly language programs; but directives for debugging symbols 1148are typically different in different file formats. *Note Symbol 1149Attributes: Symbol Attributes. 1150 1151 1152File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1153 11541.4 Command Line 1155================ 1156 1157After the program name `as', the command line may contain options and 1158file names. Options may appear in any order, and may be before, after, 1159or between file names. The order of file names is significant. 1160 1161 `--' (two hyphens) by itself names the standard input file 1162explicitly, as one of the files for `as' to assemble. 1163 1164 Except for `--' any command line argument that begins with a hyphen 1165(`-') is an option. Each option changes the behavior of `as'. No 1166option changes the way another option works. An option is a `-' 1167followed by one or more letters; the case of the letter is important. 1168All options are optional. 1169 1170 Some options expect exactly one file name to follow them. The file 1171name may either immediately follow the option's letter (compatible with 1172older assemblers) or it may be the next command argument (GNU 1173standard). These two command lines are equivalent: 1174 1175 as -o my-object-file.o mumble.s 1176 as -omy-object-file.o mumble.s 1177 1178 1179File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1180 11811.5 Input Files 1182=============== 1183 1184We use the phrase "source program", abbreviated "source", to describe 1185the program input to one run of `as'. The program may be in one or 1186more files; how the source is partitioned into files doesn't change the 1187meaning of the source. 1188 1189 The source program is a concatenation of the text in all the files, 1190in the order specified. 1191 1192 Each time you run `as' it assembles exactly one source program. The 1193source program is made up of one or more files. (The standard input is 1194also a file.) 1195 1196 You give `as' a command line that has zero or more input file names. 1197The input files are read (from left file name to right). A command 1198line argument (in any position) that has no special meaning is taken to 1199be an input file name. 1200 1201 If you give `as' no file names it attempts to read one input file 1202from the `as' standard input, which is normally your terminal. You may 1203have to type <ctl-D> to tell `as' there is no more program to assemble. 1204 1205 Use `--' if you need to explicitly name the standard input file in 1206your command line. 1207 1208 If the source is empty, `as' produces a small, empty object file. 1209 1210Filenames and Line-numbers 1211-------------------------- 1212 1213There are two ways of locating a line in the input file (or files) and 1214either may be used in reporting error messages. One way refers to a 1215line number in a physical file; the other refers to a line number in a 1216"logical" file. *Note Error and Warning Messages: Errors. 1217 1218 "Physical files" are those files named in the command line given to 1219`as'. 1220 1221 "Logical files" are simply names declared explicitly by assembler 1222directives; they bear no relation to physical files. Logical file 1223names help error messages reflect the original source file, when `as' 1224source is itself synthesized from other files. `as' understands the 1225`#' directives emitted by the `gcc' preprocessor. See also *Note 1226`.file': File. 1227 1228 1229File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1230 12311.6 Output (Object) File 1232======================== 1233 1234Every time you run `as' it produces an output file, which is your 1235assembly language program translated into numbers. This file is the 1236object file. Its default name is `a.out'. You can give it another 1237name by using the `-o' option. Conventionally, object file names end 1238with `.o'. The default name is used for historical reasons: older 1239assemblers were capable of assembling self-contained programs directly 1240into a runnable program. (For some formats, this isn't currently 1241possible, but it can be done for the `a.out' format.) 1242 1243 The object file is meant for input to the linker `ld'. It contains 1244assembled program code, information to help `ld' integrate the 1245assembled program into a runnable file, and (optionally) symbolic 1246information for the debugger. 1247 1248 1249File: as.info, Node: Errors, Prev: Object, Up: Overview 1250 12511.7 Error and Warning Messages 1252============================== 1253 1254`as' may write warnings and error messages to the standard error file 1255(usually your terminal). This should not happen when a compiler runs 1256`as' automatically. Warnings report an assumption made so that `as' 1257could keep assembling a flawed program; errors report a grave problem 1258that stops the assembly. 1259 1260 Warning messages have the format 1261 1262 file_name:NNN:Warning Message Text 1263 1264(where NNN is a line number). If a logical file name has been given 1265(*note `.file': File.) it is used for the filename, otherwise the name 1266of the current input file is used. If a logical line number was given 1267(*note `.line': Line.) then it is used to calculate the number printed, 1268otherwise the actual line in the current source file is printed. The 1269message text is intended to be self explanatory (in the grand Unix 1270tradition). 1271 1272 Error messages have the format 1273 file_name:NNN:FATAL:Error Message Text 1274 The file name and line number are derived as for warning messages. 1275The actual message text may be rather less explanatory because many of 1276them aren't supposed to happen. 1277 1278 1279File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1280 12812 Command-Line Options 1282********************** 1283 1284This chapter describes command-line options available in _all_ versions 1285of the GNU assembler; see *Note Machine Dependencies::, for options 1286specific to particular machine architectures. 1287 1288 If you are invoking `as' via the GNU C compiler, you can use the 1289`-Wa' option to pass arguments through to the assembler. The assembler 1290arguments must be separated from each other (and the `-Wa') by commas. 1291For example: 1292 1293 gcc -c -g -O -Wa,-alh,-L file.c 1294 1295This passes two options to the assembler: `-alh' (emit a listing to 1296standard output with high-level and assembly source) and `-L' (retain 1297local symbols in the symbol table). 1298 1299 Usually you do not need to use this `-Wa' mechanism, since many 1300compiler command-line options are automatically passed to the assembler 1301by the compiler. (You can call the GNU compiler driver with the `-v' 1302option to see precisely what options it passes to each compilation 1303pass, including the assembler.) 1304 1305* Menu: 1306 1307* a:: -a[cdghlns] enable listings 1308* alternate:: --alternate enable alternate macro syntax 1309* D:: -D for compatibility 1310* f:: -f to work faster 1311* I:: -I for .include search path 1312 1313* K:: -K for difference tables 1314 1315* L:: -L to retain local symbols 1316* listing:: --listing-XXX to configure listing output 1317* M:: -M or --mri to assemble in MRI compatibility mode 1318* MD:: --MD for dependency tracking 1319* o:: -o to name the object file 1320* R:: -R to join data and text sections 1321* statistics:: --statistics to see statistics about assembly 1322* traditional-format:: --traditional-format for compatible output 1323* v:: -v to announce version 1324* W:: -W, --no-warn, --warn, --fatal-warnings to control warnings 1325* Z:: -Z to make object file even after errors 1326 1327 1328File: as.info, Node: a, Next: alternate, Up: Invoking 1329 13302.1 Enable Listings: `-a[cdghlns]' 1331================================== 1332 1333These options enable listing output from the assembler. By itself, 1334`-a' requests high-level, assembly, and symbols listing. You can use 1335other letters to select specific options for the list: `-ah' requests a 1336high-level language listing, `-al' requests an output-program assembly 1337listing, and `-as' requests a symbol table listing. High-level 1338listings require that a compiler debugging option like `-g' be used, 1339and that assembly listings (`-al') be requested also. 1340 1341 Use the `-ag' option to print a first section with general assembly 1342information, like as version, switches passed, or time stamp. 1343 1344 Use the `-ac' option to omit false conditionals from a listing. Any 1345lines which are not assembled because of a false `.if' (or `.ifdef', or 1346any other conditional), or a true `.if' followed by an `.else', will be 1347omitted from the listing. 1348 1349 Use the `-ad' option to omit debugging directives from the listing. 1350 1351 Once you have specified one of these options, you can further control 1352listing output and its appearance using the directives `.list', 1353`.nolist', `.psize', `.eject', `.title', and `.sbttl'. The `-an' 1354option turns off all forms processing. If you do not request listing 1355output with one of the `-a' options, the listing-control directives 1356have no effect. 1357 1358 The letters after `-a' may be combined into one option, _e.g._, 1359`-aln'. 1360 1361 Note if the assembler source is coming from the standard input (e.g., 1362because it is being created by `gcc' and the `-pipe' command line switch 1363is being used) then the listing will not contain any comments or 1364preprocessor directives. This is because the listing code buffers 1365input source lines from stdin only after they have been preprocessed by 1366the assembler. This reduces memory usage and makes the code more 1367efficient. 1368 1369 1370File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1371 13722.2 `--alternate' 1373================= 1374 1375Begin in alternate macro mode, see *Note `.altmacro': Altmacro. 1376 1377 1378File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1379 13802.3 `-D' 1381======== 1382 1383This option has no effect whatsoever, but it is accepted to make it more 1384likely that scripts written for other assemblers also work with `as'. 1385 1386 1387File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1388 13892.4 Work Faster: `-f' 1390===================== 1391 1392`-f' should only be used when assembling programs written by a 1393(trusted) compiler. `-f' stops the assembler from doing whitespace and 1394comment preprocessing on the input file(s) before assembling them. 1395*Note Preprocessing: Preprocessing. 1396 1397 _Warning:_ if you use `-f' when the files actually need to be 1398 preprocessed (if they contain comments, for example), `as' does 1399 not work correctly. 1400 1401 1402File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1403 14042.5 `.include' Search Path: `-I' PATH 1405===================================== 1406 1407Use this option to add a PATH to the list of directories `as' searches 1408for files specified in `.include' directives (*note `.include': 1409Include.). You may use `-I' as many times as necessary to include a 1410variety of paths. The current working directory is always searched 1411first; after that, `as' searches any `-I' directories in the same order 1412as they were specified (left to right) on the command line. 1413 1414 1415File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1416 14172.6 Difference Tables: `-K' 1418=========================== 1419 1420`as' sometimes alters the code emitted for directives of the form 1421`.word SYM1-SYM2'. *Note `.word': Word. You can use the `-K' option 1422if you want a warning issued when this is done. 1423 1424 1425File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1426 14272.7 Include Local Symbols: `-L' 1428=============================== 1429 1430Symbols beginning with system-specific local label prefixes, typically 1431`.L' for ELF systems or `L' for traditional a.out systems, are called 1432"local symbols". *Note Symbol Names::. Normally you do not see such 1433symbols when debugging, because they are intended for the use of 1434programs (like compilers) that compose assembler programs, not for your 1435notice. Normally both `as' and `ld' discard such symbols, so you do 1436not normally debug with them. 1437 1438 This option tells `as' to retain those local symbols in the object 1439file. Usually if you do this you also tell the linker `ld' to preserve 1440those symbols. 1441 1442 1443File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1444 14452.8 Configuring listing output: `--listing' 1446=========================================== 1447 1448The listing feature of the assembler can be enabled via the command 1449line switch `-a' (*note a::). This feature combines the input source 1450file(s) with a hex dump of the corresponding locations in the output 1451object file, and displays them as a listing file. The format of this 1452listing can be controlled by directives inside the assembler source 1453(i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl' 1454(*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::) 1455and also by the following switches: 1456 1457`--listing-lhs-width=`number'' 1458 Sets the maximum width, in words, of the first line of the hex 1459 byte dump. This dump appears on the left hand side of the listing 1460 output. 1461 1462`--listing-lhs-width2=`number'' 1463 Sets the maximum width, in words, of any further lines of the hex 1464 byte dump for a given input source line. If this value is not 1465 specified, it defaults to being the same as the value specified 1466 for `--listing-lhs-width'. If neither switch is used the default 1467 is to one. 1468 1469`--listing-rhs-width=`number'' 1470 Sets the maximum width, in characters, of the source line that is 1471 displayed alongside the hex dump. The default value for this 1472 parameter is 100. The source line is displayed on the right hand 1473 side of the listing output. 1474 1475`--listing-cont-lines=`number'' 1476 Sets the maximum number of continuation lines of hex dump that 1477 will be displayed for a given single line of source input. The 1478 default value is 4. 1479 1480 1481File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1482 14832.9 Assemble in MRI Compatibility Mode: `-M' 1484============================================ 1485 1486The `-M' or `--mri' option selects MRI compatibility mode. This 1487changes the syntax and pseudo-op handling of `as' to make it compatible 1488with the `ASM68K' or the `ASM960' (depending upon the configured 1489target) assembler from Microtec Research. The exact nature of the MRI 1490syntax will not be documented here; see the MRI manuals for more 1491information. Note in particular that the handling of macros and macro 1492arguments is somewhat different. The purpose of this option is to 1493permit assembling existing MRI assembler code using `as'. 1494 1495 The MRI compatibility is not complete. Certain operations of the 1496MRI assembler depend upon its object file format, and can not be 1497supported using other object file formats. Supporting these would 1498require enhancing each object file format individually. These are: 1499 1500 * global symbols in common section 1501 1502 The m68k MRI assembler supports common sections which are merged 1503 by the linker. Other object file formats do not support this. 1504 `as' handles common sections by treating them as a single common 1505 symbol. It permits local symbols to be defined within a common 1506 section, but it can not support global symbols, since it has no 1507 way to describe them. 1508 1509 * complex relocations 1510 1511 The MRI assemblers support relocations against a negated section 1512 address, and relocations which combine the start addresses of two 1513 or more sections. These are not support by other object file 1514 formats. 1515 1516 * `END' pseudo-op specifying start address 1517 1518 The MRI `END' pseudo-op permits the specification of a start 1519 address. This is not supported by other object file formats. The 1520 start address may instead be specified using the `-e' option to 1521 the linker, or in a linker script. 1522 1523 * `IDNT', `.ident' and `NAME' pseudo-ops 1524 1525 The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module 1526 name to the output file. This is not supported by other object 1527 file formats. 1528 1529 * `ORG' pseudo-op 1530 1531 The m68k MRI `ORG' pseudo-op begins an absolute section at a given 1532 address. This differs from the usual `as' `.org' pseudo-op, which 1533 changes the location within the current section. Absolute 1534 sections are not supported by other object file formats. The 1535 address of a section may be assigned within a linker script. 1536 1537 There are some other features of the MRI assembler which are not 1538supported by `as', typically either because they are difficult or 1539because they seem of little consequence. Some of these may be 1540supported in future releases. 1541 1542 * EBCDIC strings 1543 1544 EBCDIC strings are not supported. 1545 1546 * packed binary coded decimal 1547 1548 Packed binary coded decimal is not supported. This means that the 1549 `DC.P' and `DCB.P' pseudo-ops are not supported. 1550 1551 * `FEQU' pseudo-op 1552 1553 The m68k `FEQU' pseudo-op is not supported. 1554 1555 * `NOOBJ' pseudo-op 1556 1557 The m68k `NOOBJ' pseudo-op is not supported. 1558 1559 * `OPT' branch control options 1560 1561 The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL', 1562 and `BRW'--are ignored. `as' automatically relaxes all branches, 1563 whether forward or backward, to an appropriate size, so these 1564 options serve no purpose. 1565 1566 * `OPT' list control options 1567 1568 The following m68k `OPT' list control options are ignored: `C', 1569 `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'. 1570 1571 * other `OPT' options 1572 1573 The following m68k `OPT' options are ignored: `NEST', `O', `OLD', 1574 `OP', `P', `PCO', `PCR', `PCS', `R'. 1575 1576 * `OPT' `D' option is default 1577 1578 The m68k `OPT' `D' option is the default, unlike the MRI assembler. 1579 `OPT NOD' may be used to turn it off. 1580 1581 * `XREF' pseudo-op. 1582 1583 The m68k `XREF' pseudo-op is ignored. 1584 1585 * `.debug' pseudo-op 1586 1587 The i960 `.debug' pseudo-op is not supported. 1588 1589 * `.extended' pseudo-op 1590 1591 The i960 `.extended' pseudo-op is not supported. 1592 1593 * `.list' pseudo-op. 1594 1595 The various options of the i960 `.list' pseudo-op are not 1596 supported. 1597 1598 * `.optimize' pseudo-op 1599 1600 The i960 `.optimize' pseudo-op is not supported. 1601 1602 * `.output' pseudo-op 1603 1604 The i960 `.output' pseudo-op is not supported. 1605 1606 * `.setreal' pseudo-op 1607 1608 The i960 `.setreal' pseudo-op is not supported. 1609 1610 1611 1612File: as.info, Node: MD, Next: o, Prev: M, Up: Invoking 1613 16142.10 Dependency Tracking: `--MD' 1615================================ 1616 1617`as' can generate a dependency file for the file it creates. This file 1618consists of a single rule suitable for `make' describing the 1619dependencies of the main source file. 1620 1621 The rule is written to the file named in its argument. 1622 1623 This feature is used in the automatic updating of makefiles. 1624 1625 1626File: as.info, Node: o, Next: R, Prev: MD, Up: Invoking 1627 16282.11 Name the Object File: `-o' 1629=============================== 1630 1631There is always one object file output when you run `as'. By default 1632it has the name `a.out' (or `b.out', for Intel 960 targets only). You 1633use this option (which takes exactly one filename) to give the object 1634file a different name. 1635 1636 Whatever the object file is called, `as' overwrites any existing 1637file of the same name. 1638 1639 1640File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1641 16422.12 Join Data and Text Sections: `-R' 1643====================================== 1644 1645`-R' tells `as' to write the object file as if all data-section data 1646lives in the text section. This is only done at the very last moment: 1647your binary data are the same, but data section parts are relocated 1648differently. The data section part of your object file is zero bytes 1649long because all its bytes are appended to the text section. (*Note 1650Sections and Relocation: Sections.) 1651 1652 When you specify `-R' it would be possible to generate shorter 1653address displacements (because we do not have to cross between text and 1654data section). We refrain from doing this simply for compatibility with 1655older versions of `as'. In future, `-R' may work this way. 1656 1657 When `as' is configured for COFF or ELF output, this option is only 1658useful if you use sections named `.text' and `.data'. 1659 1660 `-R' is not supported for any of the HPPA targets. Using `-R' 1661generates a warning from `as'. 1662 1663 1664File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1665 16662.13 Display Assembly Statistics: `--statistics' 1667================================================ 1668 1669Use `--statistics' to display two statistics about the resources used by 1670`as': the maximum amount of space allocated during the assembly (in 1671bytes), and the total execution time taken for the assembly (in CPU 1672seconds). 1673 1674 1675File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1676 16772.14 Compatible Output: `--traditional-format' 1678============================================== 1679 1680For some targets, the output of `as' is different in some ways from the 1681output of some existing assembler. This switch requests `as' to use 1682the traditional format instead. 1683 1684 For example, it disables the exception frame optimizations which 1685`as' normally does by default on `gcc' output. 1686 1687 1688File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1689 16902.15 Announce Version: `-v' 1691=========================== 1692 1693You can find out what version of as is running by including the option 1694`-v' (which you can also spell as `-version') on the command line. 1695 1696 1697File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1698 16992.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings' 1700====================================================================== 1701 1702`as' should never give a warning or error message when assembling 1703compiler output. But programs written by people often cause `as' to 1704give a warning that a particular assumption was made. All such 1705warnings are directed to the standard error file. 1706 1707 If you use the `-W' and `--no-warn' options, no warnings are issued. 1708This only affects the warning messages: it does not change any 1709particular of how `as' assembles your file. Errors, which stop the 1710assembly, are still reported. 1711 1712 If you use the `--fatal-warnings' option, `as' considers files that 1713generate warnings to be in error. 1714 1715 You can switch these options off again by specifying `--warn', which 1716causes warnings to be output as usual. 1717 1718 1719File: as.info, Node: Z, Prev: W, Up: Invoking 1720 17212.17 Generate Object File in Spite of Errors: `-Z' 1722================================================== 1723 1724After an error message, `as' normally produces no output. If for some 1725reason you are interested in object file output even after `as' gives 1726an error message on your program, use the `-Z' option. If there are 1727any errors, `as' continues anyways, and writes an object file after a 1728final warning message of the form `N errors, M warnings, generating bad 1729object file.' 1730 1731 1732File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1733 17343 Syntax 1735******** 1736 1737This chapter describes the machine-independent syntax allowed in a 1738source file. `as' syntax is similar to what many other assemblers use; 1739it is inspired by the BSD 4.2 assembler, except that `as' does not 1740assemble Vax bit-fields. 1741 1742* Menu: 1743 1744* Preprocessing:: Preprocessing 1745* Whitespace:: Whitespace 1746* Comments:: Comments 1747* Symbol Intro:: Symbols 1748* Statements:: Statements 1749* Constants:: Constants 1750 1751 1752File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 1753 17543.1 Preprocessing 1755================= 1756 1757The `as' internal preprocessor: 1758 * adjusts and removes extra whitespace. It leaves one space or tab 1759 before the keywords on a line, and turns any other whitespace on 1760 the line into a single space. 1761 1762 * removes all comments, replacing them with a single space, or an 1763 appropriate number of newlines. 1764 1765 * converts character constants into the appropriate numeric values. 1766 1767 It does not do macro processing, include file handling, or anything 1768else you may get from your C compiler's preprocessor. You can do 1769include file processing with the `.include' directive (*note 1770`.include': Include.). You can use the GNU C compiler driver to get 1771other "CPP" style preprocessing by giving the input file a `.S' suffix. 1772*Note Options Controlling the Kind of Output: (gcc.info)Overall 1773Options. 1774 1775 Excess whitespace, comments, and character constants cannot be used 1776in the portions of the input text that are not preprocessed. 1777 1778 If the first line of an input file is `#NO_APP' or if you use the 1779`-f' option, whitespace and comments are not removed from the input 1780file. Within an input file, you can ask for whitespace and comment 1781removal in specific portions of the by putting a line that says `#APP' 1782before the text that may contain whitespace or comments, and putting a 1783line that says `#NO_APP' after this text. This feature is mainly 1784intend to support `asm' statements in compilers whose output is 1785otherwise free of comments and whitespace. 1786 1787 1788File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 1789 17903.2 Whitespace 1791============== 1792 1793"Whitespace" is one or more blanks or tabs, in any order. Whitespace 1794is used to separate symbols, and to make programs neater for people to 1795read. Unless within character constants (*note Character Constants: 1796Characters.), any whitespace means the same as exactly one space. 1797 1798 1799File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 1800 18013.3 Comments 1802============ 1803 1804There are two ways of rendering comments to `as'. In both cases the 1805comment is equivalent to one space. 1806 1807 Anything from `/*' through the next `*/' is a comment. This means 1808you may not nest these comments. 1809 1810 /* 1811 The only way to include a newline ('\n') in a comment 1812 is to use this sort of comment. 1813 */ 1814 1815 /* This sort of comment does not nest. */ 1816 1817 Anything from the "line comment" character to the next newline is 1818considered a comment and is ignored. The line comment character is `;' 1819on the ARC; `@' on the ARM; `;' for the H8/300 family; `;' for the HPPA; 1820`#' on the i386 and x86-64; `#' on the i960; `;' for the PDP-11; `;' 1821for picoJava; `#' for Motorola PowerPC; `#' for IBM S/390; `#' for the 1822Sunplus SCORE; `!' for the Renesas / SuperH SH; `!' on the SPARC; `#' 1823on the ip2k; `#' on the m32c; `#' on the m32r; `|' on the 680x0; `#' on 1824the 68HC11 and 68HC12; `#' on the RX; `;' on the TMS320C6X; `#' on the 1825Vax; `;' for the Z80; `!' for the Z8000; `#' on the V850; `#' for 1826Xtensa systems; see *Note Machine Dependencies::. 1827 1828 On some machines there are two different line comment characters. 1829One character only begins a comment if it is the first non-whitespace 1830character on a line, while the other always begins a comment. 1831 1832 The V850 assembler also supports a double dash as starting a comment 1833that extends to the end of the line. 1834 1835 `--'; 1836 1837 To be compatible with past assemblers, lines that begin with `#' 1838have a special interpretation. Following the `#' should be an absolute 1839expression (*note Expressions::): the logical line number of the _next_ 1840line. Then a string (*note Strings: Strings.) is allowed: if present 1841it is a new logical file name. The rest of the line, if any, should be 1842whitespace. 1843 1844 If the first non-whitespace characters on the line are not numeric, 1845the line is ignored. (Just like a comment.) 1846 1847 # This is an ordinary comment. 1848 # 42-6 "new_file_name" # New logical file name 1849 # This is logical line # 36. 1850 This feature is deprecated, and may disappear from future versions 1851of `as'. 1852 1853 1854File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 1855 18563.4 Symbols 1857=========== 1858 1859A "symbol" is one or more characters chosen from the set of all letters 1860(both upper and lower case), digits and the three characters `_.$'. On 1861most machines, you can also use `$' in symbol names; exceptions are 1862noted in *Note Machine Dependencies::. No symbol may begin with a 1863digit. Case is significant. There is no length limit: all characters 1864are significant. Symbols are delimited by characters not in that set, 1865or by the beginning of a file (since the source program must end with a 1866newline, the end of a file is not a possible symbol delimiter). *Note 1867Symbols::. 1868 1869 1870File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 1871 18723.5 Statements 1873============== 1874 1875A "statement" ends at a newline character (`\n') or line separator 1876character. (The line separator is usually `;', unless this conflicts 1877with the comment character; see *Note Machine Dependencies::.) The 1878newline or separator character is considered part of the preceding 1879statement. Newlines and separators within character constants are an 1880exception: they do not end statements. 1881 1882It is an error to end any statement with end-of-file: the last 1883character of any input file should be a newline. 1884 1885 An empty statement is allowed, and may include whitespace. It is 1886ignored. 1887 1888 A statement begins with zero or more labels, optionally followed by a 1889key symbol which determines what kind of statement it is. The key 1890symbol determines the syntax of the rest of the statement. If the 1891symbol begins with a dot `.' then the statement is an assembler 1892directive: typically valid for any computer. If the symbol begins with 1893a letter the statement is an assembly language "instruction": it 1894assembles into a machine language instruction. Different versions of 1895`as' for different computers recognize different instructions. In 1896fact, the same symbol may represent a different instruction in a 1897different computer's assembly language. 1898 1899 A label is a symbol immediately followed by a colon (`:'). 1900Whitespace before a label or after a colon is permitted, but you may not 1901have whitespace between a label's symbol and its colon. *Note Labels::. 1902 1903 For HPPA targets, labels need not be immediately followed by a 1904colon, but the definition of a label must begin in column zero. This 1905also implies that only one label may be defined on each line. 1906 1907 label: .directive followed by something 1908 another_label: # This is an empty statement. 1909 instruction operand_1, operand_2, ... 1910 1911 1912File: as.info, Node: Constants, Prev: Statements, Up: Syntax 1913 19143.6 Constants 1915============= 1916 1917A constant is a number, written so that its value is known by 1918inspection, without knowing any context. Like this: 1919 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 1920 .ascii "Ring the bell\7" # A string constant. 1921 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 1922 .float 0f-314159265358979323846264338327\ 1923 95028841971.693993751E-40 # - pi, a flonum. 1924 1925* Menu: 1926 1927* Characters:: Character Constants 1928* Numbers:: Number Constants 1929 1930 1931File: as.info, Node: Characters, Next: Numbers, Up: Constants 1932 19333.6.1 Character Constants 1934------------------------- 1935 1936There are two kinds of character constants. A "character" stands for 1937one character in one byte and its value may be used in numeric 1938expressions. String constants (properly called string _literals_) are 1939potentially many bytes and their values may not be used in arithmetic 1940expressions. 1941 1942* Menu: 1943 1944* Strings:: Strings 1945* Chars:: Characters 1946 1947 1948File: as.info, Node: Strings, Next: Chars, Up: Characters 1949 19503.6.1.1 Strings 1951............... 1952 1953A "string" is written between double-quotes. It may contain 1954double-quotes or null characters. The way to get special characters 1955into a string is to "escape" these characters: precede them with a 1956backslash `\' character. For example `\\' represents one backslash: 1957the first `\' is an escape which tells `as' to interpret the second 1958character literally as a backslash (which prevents `as' from 1959recognizing the second `\' as an escape character). The complete list 1960of escapes follows. 1961 1962`\b' 1963 Mnemonic for backspace; for ASCII this is octal code 010. 1964 1965`\f' 1966 Mnemonic for FormFeed; for ASCII this is octal code 014. 1967 1968`\n' 1969 Mnemonic for newline; for ASCII this is octal code 012. 1970 1971`\r' 1972 Mnemonic for carriage-Return; for ASCII this is octal code 015. 1973 1974`\t' 1975 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 1976 1977`\ DIGIT DIGIT DIGIT' 1978 An octal character code. The numeric code is 3 octal digits. For 1979 compatibility with other Unix systems, 8 and 9 are accepted as 1980 digits: for example, `\008' has the value 010, and `\009' the 1981 value 011. 1982 1983`\`x' HEX-DIGITS...' 1984 A hex character code. All trailing hex digits are combined. 1985 Either upper or lower case `x' works. 1986 1987`\\' 1988 Represents one `\' character. 1989 1990`\"' 1991 Represents one `"' character. Needed in strings to represent this 1992 character, because an unescaped `"' would end the string. 1993 1994`\ ANYTHING-ELSE' 1995 Any other character when escaped by `\' gives a warning, but 1996 assembles as if the `\' was not present. The idea is that if you 1997 used an escape sequence you clearly didn't want the literal 1998 interpretation of the following character. However `as' has no 1999 other interpretation, so `as' knows it is giving you the wrong 2000 code and warns you of the fact. 2001 2002 Which characters are escapable, and what those escapes represent, 2003varies widely among assemblers. The current set is what we think the 2004BSD 4.2 assembler recognizes, and is a subset of what most C compilers 2005recognize. If you are in doubt, do not use an escape sequence. 2006 2007 2008File: as.info, Node: Chars, Prev: Strings, Up: Characters 2009 20103.6.1.2 Characters 2011.................. 2012 2013A single character may be written as a single quote immediately 2014followed by that character. The same escapes apply to characters as to 2015strings. So if you want to write the character backslash, you must 2016write `'\\' where the first `\' escapes the second `\'. As you can 2017see, the quote is an acute accent, not a grave accent. A newline 2018immediately following an acute accent is taken as a literal character 2019and does not count as the end of a statement. The value of a character 2020constant in a numeric expression is the machine's byte-wide code for 2021that character. `as' assumes your character code is ASCII: `'A' means 202265, `'B' means 66, and so on. 2023 2024 2025File: as.info, Node: Numbers, Prev: Characters, Up: Constants 2026 20273.6.2 Number Constants 2028---------------------- 2029 2030`as' distinguishes three kinds of numbers according to how they are 2031stored in the target machine. _Integers_ are numbers that would fit 2032into an `int' in the C language. _Bignums_ are integers, but they are 2033stored in more than 32 bits. _Flonums_ are floating point numbers, 2034described below. 2035 2036* Menu: 2037 2038* Integers:: Integers 2039* Bignums:: Bignums 2040* Flonums:: Flonums 2041 2042 2043File: as.info, Node: Integers, Next: Bignums, Up: Numbers 2044 20453.6.2.1 Integers 2046................ 2047 2048A binary integer is `0b' or `0B' followed by zero or more of the binary 2049digits `01'. 2050 2051 An octal integer is `0' followed by zero or more of the octal digits 2052(`01234567'). 2053 2054 A decimal integer starts with a non-zero digit followed by zero or 2055more digits (`0123456789'). 2056 2057 A hexadecimal integer is `0x' or `0X' followed by one or more 2058hexadecimal digits chosen from `0123456789abcdefABCDEF'. 2059 2060 Integers have the usual values. To denote a negative integer, use 2061the prefix operator `-' discussed under expressions (*note Prefix 2062Operators: Prefix Ops.). 2063 2064 2065File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 2066 20673.6.2.2 Bignums 2068............... 2069 2070A "bignum" has the same syntax and semantics as an integer except that 2071the number (or its negative) takes more than 32 bits to represent in 2072binary. The distinction is made because in some places integers are 2073permitted while bignums are not. 2074 2075 2076File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2077 20783.6.2.3 Flonums 2079............... 2080 2081A "flonum" represents a floating point number. The translation is 2082indirect: a decimal floating point number from the text is converted by 2083`as' to a generic binary floating point number of more than sufficient 2084precision. This generic floating point number is converted to a 2085particular computer's floating point format (or formats) by a portion 2086of `as' specialized to that computer. 2087 2088 A flonum is written by writing (in order) 2089 * The digit `0'. (`0' is optional on the HPPA.) 2090 2091 * A letter, to tell `as' the rest of the number is a flonum. `e' is 2092 recommended. Case is not important. 2093 2094 On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the 2095 letter must be one of the letters `DFPRSX' (in upper or lower 2096 case). 2097 2098 On the ARC, the letter must be one of the letters `DFRS' (in upper 2099 or lower case). 2100 2101 On the Intel 960 architecture, the letter must be one of the 2102 letters `DFT' (in upper or lower case). 2103 2104 On the HPPA architecture, the letter must be `E' (upper case only). 2105 2106 * An optional sign: either `+' or `-'. 2107 2108 * An optional "integer part": zero or more decimal digits. 2109 2110 * An optional "fractional part": `.' followed by zero or more 2111 decimal digits. 2112 2113 * An optional exponent, consisting of: 2114 2115 * An `E' or `e'. 2116 2117 * Optional sign: either `+' or `-'. 2118 2119 * One or more decimal digits. 2120 2121 2122 At least one of the integer part or the fractional part must be 2123present. The floating point number has the usual base-10 value. 2124 2125 `as' does all processing using integers. Flonums are computed 2126independently of any floating point hardware in the computer running 2127`as'. 2128 2129 2130File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2131 21324 Sections and Relocation 2133************************* 2134 2135* Menu: 2136 2137* Secs Background:: Background 2138* Ld Sections:: Linker Sections 2139* As Sections:: Assembler Internal Sections 2140* Sub-Sections:: Sub-Sections 2141* bss:: bss Section 2142 2143 2144File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2145 21464.1 Background 2147============== 2148 2149Roughly, a section is a range of addresses, with no gaps; all data "in" 2150those addresses is treated the same for some particular purpose. For 2151example there may be a "read only" section. 2152 2153 The linker `ld' reads many object files (partial programs) and 2154combines their contents to form a runnable program. When `as' emits an 2155object file, the partial program is assumed to start at address 0. 2156`ld' assigns the final addresses for the partial program, so that 2157different partial programs do not overlap. This is actually an 2158oversimplification, but it suffices to explain how `as' uses sections. 2159 2160 `ld' moves blocks of bytes of your program to their run-time 2161addresses. These blocks slide to their run-time addresses as rigid 2162units; their length does not change and neither does the order of bytes 2163within them. Such a rigid unit is called a _section_. Assigning 2164run-time addresses to sections is called "relocation". It includes the 2165task of adjusting mentions of object-file addresses so they refer to 2166the proper run-time addresses. For the H8/300, and for the Renesas / 2167SuperH SH, `as' pads sections if needed to ensure they end on a word 2168(sixteen bit) boundary. 2169 2170 An object file written by `as' has at least three sections, any of 2171which may be empty. These are named "text", "data" and "bss" sections. 2172 2173 When it generates COFF or ELF output, `as' can also generate 2174whatever other named sections you specify using the `.section' 2175directive (*note `.section': Section.). If you do not use any 2176directives that place output in the `.text' or `.data' sections, these 2177sections still exist, but are empty. 2178 2179 When `as' generates SOM or ELF output for the HPPA, `as' can also 2180generate whatever other named sections you specify using the `.space' 2181and `.subspace' directives. See `HP9000 Series 800 Assembly Language 2182Reference Manual' (HP 92432-90001) for details on the `.space' and 2183`.subspace' assembler directives. 2184 2185 Additionally, `as' uses different names for the standard text, data, 2186and bss sections when generating SOM output. Program text is placed 2187into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'. 2188 2189 Within the object file, the text section starts at address `0', the 2190data section follows, and the bss section follows the data section. 2191 2192 When generating either SOM or ELF output files on the HPPA, the text 2193section starts at address `0', the data section at address `0x4000000', 2194and the bss section follows the data section. 2195 2196 To let `ld' know which data changes when the sections are relocated, 2197and how to change that data, `as' also writes to the object file 2198details of the relocation needed. To perform relocation `ld' must 2199know, each time an address in the object file is mentioned: 2200 * Where in the object file is the beginning of this reference to an 2201 address? 2202 2203 * How long (in bytes) is this reference? 2204 2205 * Which section does the address refer to? What is the numeric 2206 value of 2207 (ADDRESS) - (START-ADDRESS OF SECTION)? 2208 2209 * Is the reference to an address "Program-Counter relative"? 2210 2211 In fact, every address `as' ever uses is expressed as 2212 (SECTION) + (OFFSET INTO SECTION) 2213 Further, most expressions `as' computes have this section-relative 2214nature. (For some object formats, such as SOM for the HPPA, some 2215expressions are symbol-relative instead.) 2216 2217 In this manual we use the notation {SECNAME N} to mean "offset N 2218into section SECNAME." 2219 2220 Apart from text, data and bss sections you need to know about the 2221"absolute" section. When `ld' mixes partial programs, addresses in the 2222absolute section remain unchanged. For example, address `{absolute 0}' 2223is "relocated" to run-time address 0 by `ld'. Although the linker 2224never arranges two partial programs' data sections with overlapping 2225addresses after linking, _by definition_ their absolute sections must 2226overlap. Address `{absolute 239}' in one part of a program is always 2227the same address when the program is running as address `{absolute 2228239}' in any other part of the program. 2229 2230 The idea of sections is extended to the "undefined" section. Any 2231address whose section is unknown at assembly time is by definition 2232rendered {undefined U}--where U is filled in later. Since numbers are 2233always defined, the only way to generate an undefined address is to 2234mention an undefined symbol. A reference to a named common block would 2235be such a symbol: its value is unknown at assembly time so it has 2236section _undefined_. 2237 2238 By analogy the word _section_ is used to describe groups of sections 2239in the linked program. `ld' puts all partial programs' text sections 2240in contiguous addresses in the linked program. It is customary to 2241refer to the _text section_ of a program, meaning all the addresses of 2242all partial programs' text sections. Likewise for data and bss 2243sections. 2244 2245 Some sections are manipulated by `ld'; others are invented for use 2246of `as' and have no meaning except during assembly. 2247 2248 2249File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2250 22514.2 Linker Sections 2252=================== 2253 2254`ld' deals with just four kinds of sections, summarized below. 2255 2256*named sections* 2257*text section* 2258*data section* 2259 These sections hold your program. `as' and `ld' treat them as 2260 separate but equal sections. Anything you can say of one section 2261 is true of another. When the program is running, however, it is 2262 customary for the text section to be unalterable. The text 2263 section is often shared among processes: it contains instructions, 2264 constants and the like. The data section of a running program is 2265 usually alterable: for example, C variables would be stored in the 2266 data section. 2267 2268*bss section* 2269 This section contains zeroed bytes when your program begins 2270 running. It is used to hold uninitialized variables or common 2271 storage. The length of each partial program's bss section is 2272 important, but because it starts out containing zeroed bytes there 2273 is no need to store explicit zero bytes in the object file. The 2274 bss section was invented to eliminate those explicit zeros from 2275 object files. 2276 2277*absolute section* 2278 Address 0 of this section is always "relocated" to runtime address 2279 0. This is useful if you want to refer to an address that `ld' 2280 must not change when relocating. In this sense we speak of 2281 absolute addresses being "unrelocatable": they do not change 2282 during relocation. 2283 2284*undefined section* 2285 This "section" is a catch-all for address references to objects 2286 not in the preceding sections. 2287 2288 An idealized example of three relocatable sections follows. The 2289example uses the traditional section names `.text' and `.data'. Memory 2290addresses are on the horizontal axis. 2291 2292 +-----+----+--+ 2293 partial program # 1: |ttttt|dddd|00| 2294 +-----+----+--+ 2295 2296 text data bss 2297 seg. seg. seg. 2298 2299 +---+---+---+ 2300 partial program # 2: |TTT|DDD|000| 2301 +---+---+---+ 2302 2303 +--+---+-----+--+----+---+-----+~~ 2304 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2305 +--+---+-----+--+----+---+-----+~~ 2306 2307 addresses: 0 ... 2308 2309 2310File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2311 23124.3 Assembler Internal Sections 2313=============================== 2314 2315These sections are meant only for the internal use of `as'. They have 2316no meaning at run-time. You do not really need to know about these 2317sections for most purposes; but they can be mentioned in `as' warning 2318messages, so it might be helpful to have an idea of their meanings to 2319`as'. These sections are used to permit the value of every expression 2320in your assembly language program to be a section-relative address. 2321 2322ASSEMBLER-INTERNAL-LOGIC-ERROR! 2323 An internal assembler logic error has been found. This means 2324 there is a bug in the assembler. 2325 2326expr section 2327 The assembler stores complex expression internally as combinations 2328 of symbols. When it needs to represent an expression as a symbol, 2329 it puts it in the expr section. 2330 2331 2332File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2333 23344.4 Sub-Sections 2335================ 2336 2337Assembled bytes conventionally fall into two sections: text and data. 2338You may have separate groups of data in named sections that you want to 2339end up near to each other in the object file, even though they are not 2340contiguous in the assembler source. `as' allows you to use 2341"subsections" for this purpose. Within each section, there can be 2342numbered subsections with values from 0 to 8192. Objects assembled 2343into the same subsection go into the object file together with other 2344objects in the same subsection. For example, a compiler might want to 2345store constants in the text section, but might not want to have them 2346interspersed with the program being assembled. In this case, the 2347compiler could issue a `.text 0' before each section of code being 2348output, and a `.text 1' before each group of constants being output. 2349 2350Subsections are optional. If you do not use subsections, everything 2351goes in subsection number zero. 2352 2353 Each subsection is zero-padded up to a multiple of four bytes. 2354(Subsections may be padded a different amount on different flavors of 2355`as'.) 2356 2357 Subsections appear in your object file in numeric order, lowest 2358numbered to highest. (All this to be compatible with other people's 2359assemblers.) The object file contains no representation of 2360subsections; `ld' and other programs that manipulate object files see 2361no trace of them. They just see all your text subsections as a text 2362section, and all your data subsections as a data section. 2363 2364 To specify which subsection you want subsequent statements assembled 2365into, use a numeric argument to specify it, in a `.text EXPRESSION' or 2366a `.data EXPRESSION' statement. When generating COFF output, you can 2367also use an extra subsection argument with arbitrary named sections: 2368`.section NAME, EXPRESSION'. When generating ELF output, you can also 2369use the `.subsection' directive (*note SubSection::) to specify a 2370subsection: `.subsection EXPRESSION'. EXPRESSION should be an absolute 2371expression (*note Expressions::). If you just say `.text' then `.text 23720' is assumed. Likewise `.data' means `.data 0'. Assembly begins in 2373`text 0'. For instance: 2374 .text 0 # The default subsection is text 0 anyway. 2375 .ascii "This lives in the first text subsection. *" 2376 .text 1 2377 .ascii "But this lives in the second text subsection." 2378 .data 0 2379 .ascii "This lives in the data section," 2380 .ascii "in the first data subsection." 2381 .text 0 2382 .ascii "This lives in the first text section," 2383 .ascii "immediately following the asterisk (*)." 2384 2385 Each section has a "location counter" incremented by one for every 2386byte assembled into that section. Because subsections are merely a 2387convenience restricted to `as' there is no concept of a subsection 2388location counter. There is no way to directly manipulate a location 2389counter--but the `.align' directive changes it, and any label 2390definition captures its current value. The location counter of the 2391section where statements are being assembled is said to be the "active" 2392location counter. 2393 2394 2395File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2396 23974.5 bss Section 2398=============== 2399 2400The bss section is used for local common variable storage. You may 2401allocate address space in the bss section, but you may not dictate data 2402to load into it before your program executes. When your program starts 2403running, all the contents of the bss section are zeroed bytes. 2404 2405 The `.lcomm' pseudo-op defines a symbol in the bss section; see 2406*Note `.lcomm': Lcomm. 2407 2408 The `.comm' pseudo-op may be used to declare a common symbol, which 2409is another form of uninitialized symbol; see *Note `.comm': Comm. 2410 2411 When assembling for a target which supports multiple sections, such 2412as ELF or COFF, you may switch into the `.bss' section and define 2413symbols as usual; see *Note `.section': Section. You may only assemble 2414zero values into the section. Typically the section will only contain 2415symbol definitions and `.skip' directives (*note `.skip': Skip.). 2416 2417 2418File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2419 24205 Symbols 2421********* 2422 2423Symbols are a central concept: the programmer uses symbols to name 2424things, the linker uses symbols to link, and the debugger uses symbols 2425to debug. 2426 2427 _Warning:_ `as' does not place symbols in the object file in the 2428 same order they were declared. This may break some debuggers. 2429 2430* Menu: 2431 2432* Labels:: Labels 2433* Setting Symbols:: Giving Symbols Other Values 2434* Symbol Names:: Symbol Names 2435* Dot:: The Special Dot Symbol 2436* Symbol Attributes:: Symbol Attributes 2437 2438 2439File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2440 24415.1 Labels 2442========== 2443 2444A "label" is written as a symbol immediately followed by a colon `:'. 2445The symbol then represents the current value of the active location 2446counter, and is, for example, a suitable instruction operand. You are 2447warned if you use the same symbol to represent two different locations: 2448the first definition overrides any other definitions. 2449 2450 On the HPPA, the usual form for a label need not be immediately 2451followed by a colon, but instead must start in column zero. Only one 2452label may be defined on a single line. To work around this, the HPPA 2453version of `as' also provides a special directive `.label' for defining 2454labels more flexibly. 2455 2456 2457File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2458 24595.2 Giving Symbols Other Values 2460=============================== 2461 2462A symbol can be given an arbitrary value by writing a symbol, followed 2463by an equals sign `=', followed by an expression (*note Expressions::). 2464This is equivalent to using the `.set' directive. *Note `.set': Set. 2465In the same way, using a double equals sign `='`=' here represents an 2466equivalent of the `.eqv' directive. *Note `.eqv': Eqv. 2467 2468 Blackfin does not support symbol assignment with `='. 2469 2470 2471File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2472 24735.3 Symbol Names 2474================ 2475 2476Symbol names begin with a letter or with one of `._'. On most 2477machines, you can also use `$' in symbol names; exceptions are noted in 2478*Note Machine Dependencies::. That character may be followed by any 2479string of digits, letters, dollar signs (unless otherwise noted for a 2480particular target machine), and underscores. 2481 2482Case of letters is significant: `foo' is a different symbol name than 2483`Foo'. 2484 2485 Each symbol has exactly one name. Each name in an assembly language 2486program refers to exactly one symbol. You may use that symbol name any 2487number of times in a program. 2488 2489Local Symbol Names 2490------------------ 2491 2492A local symbol is any symbol beginning with certain local label 2493prefixes. By default, the local label prefix is `.L' for ELF systems or 2494`L' for traditional a.out systems, but each target may have its own set 2495of local label prefixes. On the HPPA local symbols begin with `L$'. 2496 2497 Local symbols are defined and used within the assembler, but they are 2498normally not saved in object files. Thus, they are not visible when 2499debugging. You may use the `-L' option (*note Include Local Symbols: 2500`-L': L.) to retain the local symbols in the object files. 2501 2502Local Labels 2503------------ 2504 2505Local labels help compilers and programmers use names temporarily. 2506They create symbols which are guaranteed to be unique over the entire 2507scope of the input source code and which can be referred to by a simple 2508notation. To define a local label, write a label of the form `N:' 2509(where N represents any positive integer). To refer to the most recent 2510previous definition of that label write `Nb', using the same number as 2511when you defined the label. To refer to the next definition of a local 2512label, write `Nf'--the `b' stands for "backwards" and the `f' stands 2513for "forwards". 2514 2515 There is no restriction on how you can use these labels, and you can 2516reuse them too. So that it is possible to repeatedly define the same 2517local label (using the same number `N'), although you can only refer to 2518the most recently defined local label of that number (for a backwards 2519reference) or the next definition of a specific local label for a 2520forward reference. It is also worth noting that the first 10 local 2521labels (`0:'...`9:') are implemented in a slightly more efficient 2522manner than the others. 2523 2524 Here is an example: 2525 2526 1: branch 1f 2527 2: branch 1b 2528 1: branch 2f 2529 2: branch 1b 2530 2531 Which is the equivalent of: 2532 2533 label_1: branch label_3 2534 label_2: branch label_1 2535 label_3: branch label_4 2536 label_4: branch label_3 2537 2538 Local label names are only a notational device. They are immediately 2539transformed into more conventional symbol names before the assembler 2540uses them. The symbol names are stored in the symbol table, appear in 2541error messages, and are optionally emitted to the object file. The 2542names are constructed using these parts: 2543 2544`_local label prefix_' 2545 All local symbols begin with the system-specific local label 2546 prefix. Normally both `as' and `ld' forget symbols that start 2547 with the local label prefix. These labels are used for symbols 2548 you are never intended to see. If you use the `-L' option then 2549 `as' retains these symbols in the object file. If you also 2550 instruct `ld' to retain these symbols, you may use them in 2551 debugging. 2552 2553`NUMBER' 2554 This is the number that was used in the local label definition. 2555 So if the label is written `55:' then the number is `55'. 2556 2557`C-B' 2558 This unusual character is included so you do not accidentally 2559 invent a symbol of the same name. The character has ASCII value 2560 of `\002' (control-B). 2561 2562`_ordinal number_' 2563 This is a serial number to keep the labels distinct. The first 2564 definition of `0:' gets the number `1'. The 15th definition of 2565 `0:' gets the number `15', and so on. Likewise the first 2566 definition of `1:' gets the number `1' and its 15th definition 2567 gets `15' as well. 2568 2569 So for example, the first `1:' may be named `.L1C-B1', and the 44th 2570`3:' may be named `.L3C-B44'. 2571 2572Dollar Local Labels 2573------------------- 2574 2575`as' also supports an even more local form of local labels called 2576dollar labels. These labels go out of scope (i.e., they become 2577undefined) as soon as a non-local label is defined. Thus they remain 2578valid for only a small region of the input source code. Normal local 2579labels, by contrast, remain in scope for the entire file, or until they 2580are redefined by another occurrence of the same local label. 2581 2582 Dollar labels are defined in exactly the same way as ordinary local 2583labels, except that they have a dollar sign suffix to their numeric 2584value, e.g., `55$:'. 2585 2586 They can also be distinguished from ordinary local labels by their 2587transformed names which use ASCII character `\001' (control-A) as the 2588magic character to distinguish them from ordinary labels. For example, 2589the fifth definition of `6$' may be named `.L6C-A5'. 2590 2591 2592File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2593 25945.4 The Special Dot Symbol 2595========================== 2596 2597The special symbol `.' refers to the current address that `as' is 2598assembling into. Thus, the expression `melvin: .long .' defines 2599`melvin' to contain its own address. Assigning a value to `.' is 2600treated the same as a `.org' directive. Thus, the expression `.=.+4' 2601is the same as saying `.space 4'. 2602 2603 2604File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2605 26065.5 Symbol Attributes 2607===================== 2608 2609Every symbol has, as well as its name, the attributes "Value" and 2610"Type". Depending on output format, symbols can also have auxiliary 2611attributes. 2612 2613 If you use a symbol without defining it, `as' assumes zero for all 2614these attributes, and probably won't warn you. This makes the symbol 2615an externally defined symbol, which is generally what you would want. 2616 2617* Menu: 2618 2619* Symbol Value:: Value 2620* Symbol Type:: Type 2621 2622 2623* a.out Symbols:: Symbol Attributes: `a.out' 2624 2625* COFF Symbols:: Symbol Attributes for COFF 2626 2627* SOM Symbols:: Symbol Attributes for SOM 2628 2629 2630File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2631 26325.5.1 Value 2633----------- 2634 2635The value of a symbol is (usually) 32 bits. For a symbol which labels a 2636location in the text, data, bss or absolute sections the value is the 2637number of addresses from the start of that section to the label. 2638Naturally for text, data and bss sections the value of a symbol changes 2639as `ld' changes section base addresses during linking. Absolute 2640symbols' values do not change during linking: that is why they are 2641called absolute. 2642 2643 The value of an undefined symbol is treated in a special way. If it 2644is 0 then the symbol is not defined in this assembler source file, and 2645`ld' tries to determine its value from other files linked into the same 2646program. You make this kind of symbol simply by mentioning a symbol 2647name without defining it. A non-zero value represents a `.comm' common 2648declaration. The value is how much common storage to reserve, in bytes 2649(addresses). The symbol refers to the first address of the allocated 2650storage. 2651 2652 2653File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2654 26555.5.2 Type 2656---------- 2657 2658The type attribute of a symbol contains relocation (section) 2659information, any flag settings indicating that a symbol is external, and 2660(optionally), other information for linkers and debuggers. The exact 2661format depends on the object-code output format in use. 2662 2663 2664File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2665 26665.5.3 Symbol Attributes: `a.out' 2667-------------------------------- 2668 2669* Menu: 2670 2671* Symbol Desc:: Descriptor 2672* Symbol Other:: Other 2673 2674 2675File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2676 26775.5.3.1 Descriptor 2678.................. 2679 2680This is an arbitrary 16-bit value. You may establish a symbol's 2681descriptor value by using a `.desc' statement (*note `.desc': Desc.). 2682A descriptor value means nothing to `as'. 2683 2684 2685File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2686 26875.5.3.2 Other 2688............. 2689 2690This is an arbitrary 8-bit value. It means nothing to `as'. 2691 2692 2693File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2694 26955.5.4 Symbol Attributes for COFF 2696-------------------------------- 2697 2698The COFF format supports a multitude of auxiliary symbol attributes; 2699like the primary symbol attributes, they are set between `.def' and 2700`.endef' directives. 2701 27025.5.4.1 Primary Attributes 2703.......................... 2704 2705The symbol name is set with `.def'; the value and type, respectively, 2706with `.val' and `.type'. 2707 27085.5.4.2 Auxiliary Attributes 2709............................ 2710 2711The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and 2712`.weak' can generate auxiliary symbol table information for COFF. 2713 2714 2715File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2716 27175.5.5 Symbol Attributes for SOM 2718------------------------------- 2719 2720The SOM format for the HPPA supports a multitude of symbol attributes 2721set with the `.EXPORT' and `.IMPORT' directives. 2722 2723 The attributes are described in `HP9000 Series 800 Assembly Language 2724Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT' 2725assembler directive documentation. 2726 2727 2728File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 2729 27306 Expressions 2731************* 2732 2733An "expression" specifies an address or numeric value. Whitespace may 2734precede and/or follow an expression. 2735 2736 The result of an expression must be an absolute number, or else an 2737offset into a particular section. If an expression is not absolute, 2738and there is not enough information when `as' sees the expression to 2739know its section, a second pass over the source program might be 2740necessary to interpret the expression--but the second pass is currently 2741not implemented. `as' aborts with an error message in this situation. 2742 2743* Menu: 2744 2745* Empty Exprs:: Empty Expressions 2746* Integer Exprs:: Integer Expressions 2747 2748 2749File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 2750 27516.1 Empty Expressions 2752===================== 2753 2754An empty expression has no value: it is just whitespace or null. 2755Wherever an absolute expression is required, you may omit the 2756expression, and `as' assumes a value of (absolute) 0. This is 2757compatible with other assemblers. 2758 2759 2760File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 2761 27626.2 Integer Expressions 2763======================= 2764 2765An "integer expression" is one or more _arguments_ delimited by 2766_operators_. 2767 2768* Menu: 2769 2770* Arguments:: Arguments 2771* Operators:: Operators 2772* Prefix Ops:: Prefix Operators 2773* Infix Ops:: Infix Operators 2774 2775 2776File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 2777 27786.2.1 Arguments 2779--------------- 2780 2781"Arguments" are symbols, numbers or subexpressions. In other contexts 2782arguments are sometimes called "arithmetic operands". In this manual, 2783to avoid confusing them with the "instruction operands" of the machine 2784language, we use the term "argument" to refer to parts of expressions 2785only, reserving the word "operand" to refer only to machine instruction 2786operands. 2787 2788 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 2789text, data, bss, absolute, or undefined. NNN is a signed, 2's 2790complement 32 bit integer. 2791 2792 Numbers are usually integers. 2793 2794 A number can be a flonum or bignum. In this case, you are warned 2795that only the low order 32 bits are used, and `as' pretends these 32 2796bits are an integer. You may write integer-manipulating instructions 2797that act on exotic constants, compatible with other assemblers. 2798 2799 Subexpressions are a left parenthesis `(' followed by an integer 2800expression, followed by a right parenthesis `)'; or a prefix operator 2801followed by an argument. 2802 2803 2804File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 2805 28066.2.2 Operators 2807--------------- 2808 2809"Operators" are arithmetic functions, like `+' or `%'. Prefix 2810operators are followed by an argument. Infix operators appear between 2811their arguments. Operators may be preceded and/or followed by 2812whitespace. 2813 2814 2815File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 2816 28176.2.3 Prefix Operator 2818--------------------- 2819 2820`as' has the following "prefix operators". They each take one 2821argument, which must be absolute. 2822 2823`-' 2824 "Negation". Two's complement negation. 2825 2826`~' 2827 "Complementation". Bitwise not. 2828 2829 2830File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 2831 28326.2.4 Infix Operators 2833--------------------- 2834 2835"Infix operators" take two arguments, one on either side. Operators 2836have precedence, but operations with equal precedence are performed left 2837to right. Apart from `+' or `-', both arguments must be absolute, and 2838the result is absolute. 2839 2840 1. Highest Precedence 2841 2842 `*' 2843 "Multiplication". 2844 2845 `/' 2846 "Division". Truncation is the same as the C operator `/' 2847 2848 `%' 2849 "Remainder". 2850 2851 `<<' 2852 "Shift Left". Same as the C operator `<<'. 2853 2854 `>>' 2855 "Shift Right". Same as the C operator `>>'. 2856 2857 2. Intermediate precedence 2858 2859 `|' 2860 "Bitwise Inclusive Or". 2861 2862 `&' 2863 "Bitwise And". 2864 2865 `^' 2866 "Bitwise Exclusive Or". 2867 2868 `!' 2869 "Bitwise Or Not". 2870 2871 3. Low Precedence 2872 2873 `+' 2874 "Addition". If either argument is absolute, the result has 2875 the section of the other argument. You may not add together 2876 arguments from different sections. 2877 2878 `-' 2879 "Subtraction". If the right argument is absolute, the result 2880 has the section of the left argument. If both arguments are 2881 in the same section, the result is absolute. You may not 2882 subtract arguments from different sections. 2883 2884 `==' 2885 "Is Equal To" 2886 2887 `<>' 2888 `!=' 2889 "Is Not Equal To" 2890 2891 `<' 2892 "Is Less Than" 2893 2894 `>' 2895 "Is Greater Than" 2896 2897 `>=' 2898 "Is Greater Than Or Equal To" 2899 2900 `<=' 2901 "Is Less Than Or Equal To" 2902 2903 The comparison operators can be used as infix operators. A 2904 true results has a value of -1 whereas a false result has a 2905 value of 0. Note, these operators perform signed 2906 comparisons. 2907 2908 4. Lowest Precedence 2909 2910 `&&' 2911 "Logical And". 2912 2913 `||' 2914 "Logical Or". 2915 2916 These two logical operations can be used to combine the 2917 results of sub expressions. Note, unlike the comparison 2918 operators a true result returns a value of 1 but a false 2919 results does still return 0. Also note that the logical or 2920 operator has a slightly lower precedence than logical and. 2921 2922 2923 In short, it's only meaningful to add or subtract the _offsets_ in an 2924address; you can only have a defined section in one of the two 2925arguments. 2926 2927 2928File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 2929 29307 Assembler Directives 2931********************** 2932 2933All assembler directives have names that begin with a period (`.'). 2934The rest of the name is letters, usually in lower case. 2935 2936 This chapter discusses directives that are available regardless of 2937the target machine configuration for the GNU assembler. Some machine 2938configurations provide additional directives. *Note Machine 2939Dependencies::. 2940 2941* Menu: 2942 2943* Abort:: `.abort' 2944 2945* ABORT (COFF):: `.ABORT' 2946 2947* Align:: `.align ABS-EXPR , ABS-EXPR' 2948* Altmacro:: `.altmacro' 2949* Ascii:: `.ascii "STRING"'... 2950* Asciz:: `.asciz "STRING"'... 2951* Balign:: `.balign ABS-EXPR , ABS-EXPR' 2952* Byte:: `.byte EXPRESSIONS' 2953* CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc. 2954* Comm:: `.comm SYMBOL , LENGTH ' 2955* Data:: `.data SUBSECTION' 2956 2957* Def:: `.def NAME' 2958 2959* Desc:: `.desc SYMBOL, ABS-EXPRESSION' 2960 2961* Dim:: `.dim' 2962 2963* Double:: `.double FLONUMS' 2964* Eject:: `.eject' 2965* Else:: `.else' 2966* Elseif:: `.elseif' 2967* End:: `.end' 2968 2969* Endef:: `.endef' 2970 2971* Endfunc:: `.endfunc' 2972* Endif:: `.endif' 2973* Equ:: `.equ SYMBOL, EXPRESSION' 2974* Equiv:: `.equiv SYMBOL, EXPRESSION' 2975* Eqv:: `.eqv SYMBOL, EXPRESSION' 2976* Err:: `.err' 2977* Error:: `.error STRING' 2978* Exitm:: `.exitm' 2979* Extern:: `.extern' 2980* Fail:: `.fail' 2981* File:: `.file' 2982* Fill:: `.fill REPEAT , SIZE , VALUE' 2983* Float:: `.float FLONUMS' 2984* Func:: `.func' 2985* Global:: `.global SYMBOL', `.globl SYMBOL' 2986 2987* Gnu_attribute:: `.gnu_attribute TAG,VALUE' 2988* Hidden:: `.hidden NAMES' 2989 2990* hword:: `.hword EXPRESSIONS' 2991* Ident:: `.ident' 2992* If:: `.if ABSOLUTE EXPRESSION' 2993* Incbin:: `.incbin "FILE"[,SKIP[,COUNT]]' 2994* Include:: `.include "FILE"' 2995* Int:: `.int EXPRESSIONS' 2996 2997* Internal:: `.internal NAMES' 2998 2999* Irp:: `.irp SYMBOL,VALUES'... 3000* Irpc:: `.irpc SYMBOL,VALUES'... 3001* Lcomm:: `.lcomm SYMBOL , LENGTH' 3002* Lflags:: `.lflags' 3003 3004* Line:: `.line LINE-NUMBER' 3005 3006* Linkonce:: `.linkonce [TYPE]' 3007* List:: `.list' 3008* Ln:: `.ln LINE-NUMBER' 3009* Loc:: `.loc FILENO LINENO' 3010* Loc_mark_labels:: `.loc_mark_labels ENABLE' 3011 3012* Local:: `.local NAMES' 3013 3014* Long:: `.long EXPRESSIONS' 3015 3016* Macro:: `.macro NAME ARGS'... 3017* MRI:: `.mri VAL' 3018* Noaltmacro:: `.noaltmacro' 3019* Nolist:: `.nolist' 3020* Octa:: `.octa BIGNUMS' 3021* Org:: `.org NEW-LC, FILL' 3022* P2align:: `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3023 3024* PopSection:: `.popsection' 3025* Previous:: `.previous' 3026 3027* Print:: `.print STRING' 3028 3029* Protected:: `.protected NAMES' 3030 3031* Psize:: `.psize LINES, COLUMNS' 3032* Purgem:: `.purgem NAME' 3033 3034* PushSection:: `.pushsection NAME' 3035 3036* Quad:: `.quad BIGNUMS' 3037* Reloc:: `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 3038* Rept:: `.rept COUNT' 3039* Sbttl:: `.sbttl "SUBHEADING"' 3040 3041* Scl:: `.scl CLASS' 3042 3043* Section:: `.section NAME[, FLAGS]' 3044 3045* Set:: `.set SYMBOL, EXPRESSION' 3046* Short:: `.short EXPRESSIONS' 3047* Single:: `.single FLONUMS' 3048 3049* Size:: `.size [NAME , EXPRESSION]' 3050 3051* Skip:: `.skip SIZE , FILL' 3052 3053* Sleb128:: `.sleb128 EXPRESSIONS' 3054 3055* Space:: `.space SIZE , FILL' 3056 3057* Stab:: `.stabd, .stabn, .stabs' 3058 3059* String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"' 3060* Struct:: `.struct EXPRESSION' 3061 3062* SubSection:: `.subsection' 3063* Symver:: `.symver NAME,NAME2@NODENAME' 3064 3065 3066* Tag:: `.tag STRUCTNAME' 3067 3068* Text:: `.text SUBSECTION' 3069* Title:: `.title "HEADING"' 3070 3071* Type:: `.type <INT | NAME , TYPE DESCRIPTION>' 3072 3073* Uleb128:: `.uleb128 EXPRESSIONS' 3074 3075* Val:: `.val ADDR' 3076 3077 3078* Version:: `.version "STRING"' 3079* VTableEntry:: `.vtable_entry TABLE, OFFSET' 3080* VTableInherit:: `.vtable_inherit CHILD, PARENT' 3081 3082* Warning:: `.warning STRING' 3083* Weak:: `.weak NAMES' 3084* Weakref:: `.weakref ALIAS, SYMBOL' 3085* Word:: `.word EXPRESSIONS' 3086* Deprecated:: Deprecated Directives 3087 3088 3089File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3090 30917.1 `.abort' 3092============ 3093 3094This directive stops the assembly immediately. It is for compatibility 3095with other assemblers. The original idea was that the assembly 3096language source would be piped into the assembler. If the sender of 3097the source quit, it could use this directive tells `as' to quit also. 3098One day `.abort' will not be supported. 3099 3100 3101File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3102 31037.2 `.ABORT' (COFF) 3104=================== 3105 3106When producing COFF output, `as' accepts this directive as a synonym 3107for `.abort'. 3108 3109 3110File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3111 31127.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3113========================================= 3114 3115Pad the location counter (in the current subsection) to a particular 3116storage boundary. The first expression (which must be absolute) is the 3117alignment required, as described below. 3118 3119 The second expression (also absolute) gives the fill value to be 3120stored in the padding bytes. It (and the comma) may be omitted. If it 3121is omitted, the padding bytes are normally zero. However, on some 3122systems, if the section is marked as containing code and the fill value 3123is omitted, the space is filled with no-op instructions. 3124 3125 The third expression is also absolute, and is also optional. If it 3126is present, it is the maximum number of bytes that should be skipped by 3127this alignment directive. If doing the alignment would require 3128skipping more bytes than the specified maximum, then the alignment is 3129not done at all. You can omit the fill value (the second argument) 3130entirely by simply using two commas after the required alignment; this 3131can be useful if you want the alignment to be filled with no-op 3132instructions when appropriate. 3133 3134 The way the required alignment is specified varies from system to 3135system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32, 3136s390, sparc, tic4x, tic80 and xtensa, the first expression is the 3137alignment request in bytes. For example `.align 8' advances the 3138location counter until it is a multiple of 8. If the location counter 3139is already a multiple of 8, no change is needed. For the tic54x, the 3140first expression is the alignment request in words. 3141 3142 For other systems, including ppc, i386 using a.out format, arm and 3143strongarm, it is the number of low-order zero bits the location counter 3144must have after advancement. For example `.align 3' advances the 3145location counter until it a multiple of 8. If the location counter is 3146already a multiple of 8, no change is needed. 3147 3148 This inconsistency is due to the different behaviors of the various 3149native assemblers for these systems which GAS must emulate. GAS also 3150provides `.balign' and `.p2align' directives, described later, which 3151have a consistent behavior across all architectures (but are specific 3152to GAS). 3153 3154 3155File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3156 31577.4 `.altmacro' 3158=============== 3159 3160Enable alternate macro mode, enabling: 3161 3162`LOCAL NAME [ , ... ]' 3163 One additional directive, `LOCAL', is available. It is used to 3164 generate a string replacement for each of the NAME arguments, and 3165 replace any instances of NAME in each macro expansion. The 3166 replacement string is unique in the assembly, and different for 3167 each separate macro expansion. `LOCAL' allows you to write macros 3168 that define symbols, without fear of conflict between separate 3169 macro expansions. 3170 3171`String delimiters' 3172 You can write strings delimited in these other ways besides 3173 `"STRING"': 3174 3175 `'STRING'' 3176 You can delimit strings with single-quote characters. 3177 3178 `<STRING>' 3179 You can delimit strings with matching angle brackets. 3180 3181`single-character string escape' 3182 To include any single character literally in a string (even if the 3183 character would otherwise have some special meaning), you can 3184 prefix the character with `!' (an exclamation mark). For example, 3185 you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 > 3186 5.4!'. 3187 3188`Expression results as strings' 3189 You can write `%EXPR' to evaluate the expression EXPR and use the 3190 result as a string. 3191 3192 3193File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3194 31957.5 `.ascii "STRING"'... 3196======================== 3197 3198`.ascii' expects zero or more string literals (*note Strings::) 3199separated by commas. It assembles each string (with no automatic 3200trailing zero byte) into consecutive addresses. 3201 3202 3203File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops 3204 32057.6 `.asciz "STRING"'... 3206======================== 3207 3208`.asciz' is just like `.ascii', but each string is followed by a zero 3209byte. The "z" in `.asciz' stands for "zero". 3210 3211 3212File: as.info, Node: Balign, Next: Byte, Prev: Asciz, Up: Pseudo Ops 3213 32147.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 3215============================================== 3216 3217Pad the location counter (in the current subsection) to a particular 3218storage boundary. The first expression (which must be absolute) is the 3219alignment request in bytes. For example `.balign 8' advances the 3220location counter until it is a multiple of 8. If the location counter 3221is already a multiple of 8, no change is needed. 3222 3223 The second expression (also absolute) gives the fill value to be 3224stored in the padding bytes. It (and the comma) may be omitted. If it 3225is omitted, the padding bytes are normally zero. However, on some 3226systems, if the section is marked as containing code and the fill value 3227is omitted, the space is filled with no-op instructions. 3228 3229 The third expression is also absolute, and is also optional. If it 3230is present, it is the maximum number of bytes that should be skipped by 3231this alignment directive. If doing the alignment would require 3232skipping more bytes than the specified maximum, then the alignment is 3233not done at all. You can omit the fill value (the second argument) 3234entirely by simply using two commas after the required alignment; this 3235can be useful if you want the alignment to be filled with no-op 3236instructions when appropriate. 3237 3238 The `.balignw' and `.balignl' directives are variants of the 3239`.balign' directive. The `.balignw' directive treats the fill pattern 3240as a two byte word value. The `.balignl' directives treats the fill 3241pattern as a four byte longword value. For example, `.balignw 32424,0x368d' will align to a multiple of 4. If it skips two bytes, they 3243will be filled in with the value 0x368d (the exact placement of the 3244bytes depends upon the endianness of the processor). If it skips 1 or 32453 bytes, the fill value is undefined. 3246 3247 3248File: as.info, Node: Byte, Next: CFI directives, Prev: Balign, Up: Pseudo Ops 3249 32507.8 `.byte EXPRESSIONS' 3251======================= 3252 3253`.byte' expects zero or more expressions, separated by commas. Each 3254expression is assembled into the next byte. 3255 3256 3257File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3258 32597.9 `.cfi_sections SECTION_LIST' 3260================================ 3261 3262`.cfi_sections' may be used to specify whether CFI directives should 3263emit `.eh_frame' section and/or `.debug_frame' section. If 3264SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is 3265`.debug_frame', `.debug_frame' is emitted. To emit both use 3266`.eh_frame, .debug_frame'. The default if this directive is not used 3267is `.cfi_sections .eh_frame'. 3268 32697.10 `.cfi_startproc [simple]' 3270============================== 3271 3272`.cfi_startproc' is used at the beginning of each function that should 3273have an entry in `.eh_frame'. It initializes some internal data 3274structures. Don't forget to close the function by `.cfi_endproc'. 3275 3276 Unless `.cfi_startproc' is used along with parameter `simple' it 3277also emits some architecture dependent initial CFI instructions. 3278 32797.11 `.cfi_endproc' 3280=================== 3281 3282`.cfi_endproc' is used at the end of a function where it closes its 3283unwind entry previously opened by `.cfi_startproc', and emits it to 3284`.eh_frame'. 3285 32867.12 `.cfi_personality ENCODING [, EXP]' 3287======================================== 3288 3289`.cfi_personality' defines personality routine and its encoding. 3290ENCODING must be a constant determining how the personality should be 3291encoded. If it is 255 (`DW_EH_PE_omit'), second argument is not 3292present, otherwise second argument should be a constant or a symbol 3293name. When using indirect encodings, the symbol provided should be the 3294location where personality can be loaded from, not the personality 3295routine itself. The default after `.cfi_startproc' is 3296`.cfi_personality 0xff', no personality routine. 3297 32987.13 `.cfi_lsda ENCODING [, EXP]' 3299================================= 3300 3301`.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant 3302determining how the LSDA should be encoded. If it is 255 3303(`DW_EH_PE_omit'), second argument is not present, otherwise second 3304argument should be a constant or a symbol name. The default after 3305`.cfi_startproc' is `.cfi_lsda 0xff', no LSDA. 3306 33077.14 `.cfi_def_cfa REGISTER, OFFSET' 3308==================================== 3309 3310`.cfi_def_cfa' defines a rule for computing CFA as: take address from 3311REGISTER and add OFFSET to it. 3312 33137.15 `.cfi_def_cfa_register REGISTER' 3314===================================== 3315 3316`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on 3317REGISTER will be used instead of the old one. Offset remains the same. 3318 33197.16 `.cfi_def_cfa_offset OFFSET' 3320================================= 3321 3322`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register 3323remains the same, but OFFSET is new. Note that it is the absolute 3324offset that will be added to a defined register to compute CFA address. 3325 33267.17 `.cfi_adjust_cfa_offset OFFSET' 3327==================================== 3328 3329Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is 3330added/substracted from the previous offset. 3331 33327.18 `.cfi_offset REGISTER, OFFSET' 3333=================================== 3334 3335Previous value of REGISTER is saved at offset OFFSET from CFA. 3336 33377.19 `.cfi_rel_offset REGISTER, OFFSET' 3338======================================= 3339 3340Previous value of REGISTER is saved at offset OFFSET from the current 3341CFA register. This is transformed to `.cfi_offset' using the known 3342displacement of the CFA register from the CFA. This is often easier to 3343use, because the number will match the code it's annotating. 3344 33457.20 `.cfi_register REGISTER1, REGISTER2' 3346========================================= 3347 3348Previous value of REGISTER1 is saved in register REGISTER2. 3349 33507.21 `.cfi_restore REGISTER' 3351============================ 3352 3353`.cfi_restore' says that the rule for REGISTER is now the same as it 3354was at the beginning of the function, after all initial instruction 3355added by `.cfi_startproc' were executed. 3356 33577.22 `.cfi_undefined REGISTER' 3358============================== 3359 3360From now on the previous value of REGISTER can't be restored anymore. 3361 33627.23 `.cfi_same_value REGISTER' 3363=============================== 3364 3365Current value of REGISTER is the same like in the previous frame, i.e. 3366no restoration needed. 3367 33687.24 `.cfi_remember_state', 3369=========================== 3370 3371First save all current rules for all registers by `.cfi_remember_state', 3372then totally screw them up by subsequent `.cfi_*' directives and when 3373everything is hopelessly bad, use `.cfi_restore_state' to restore the 3374previous saved state. 3375 33767.25 `.cfi_return_column REGISTER' 3377================================== 3378 3379Change return column REGISTER, i.e. the return address is either 3380directly in REGISTER or can be accessed by rules for REGISTER. 3381 33827.26 `.cfi_signal_frame' 3383======================== 3384 3385Mark current function as signal trampoline. 3386 33877.27 `.cfi_window_save' 3388======================= 3389 3390SPARC register window has been saved. 3391 33927.28 `.cfi_escape' EXPRESSION[, ...] 3393==================================== 3394 3395Allows the user to add arbitrary bytes to the unwind info. One might 3396use this to add OS-specific CFI opcodes, or generic CFI opcodes that 3397GAS does not yet support. 3398 33997.29 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' 3400====================================================== 3401 3402The current value of REGISTER is LABEL. The value of LABEL will be 3403encoded in the output file according to ENCODING; see the description 3404of `.cfi_personality' for details on this encoding. 3405 3406 The usefulness of equating a register to a fixed label is probably 3407limited to the return address register. Here, it can be useful to mark 3408a code segment that has only one return address which is reached by a 3409direct branch and no copy of the return address exists in memory or 3410another register. 3411 3412 3413File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3414 34157.30 `.comm SYMBOL , LENGTH ' 3416============================= 3417 3418`.comm' declares a common symbol named SYMBOL. When linking, a common 3419symbol in one object file may be merged with a defined or common symbol 3420of the same name in another object file. If `ld' does not see a 3421definition for the symbol-just one or more common symbols-then it will 3422allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3423absolute expression. If `ld' sees multiple common symbols with the 3424same name, and they do not all have the same size, it will allocate 3425space using the largest size. 3426 3427 When using ELF or (as a GNU extension) PE, the `.comm' directive 3428takes an optional third argument. This is the desired alignment of the 3429symbol, specified for ELF as a byte boundary (for example, an alignment 3430of 16 means that the least significant 4 bits of the address should be 3431zero), and for PE as a power of two (for example, an alignment of 5 3432means aligned to a 32-byte boundary). The alignment must be an 3433absolute expression, and it must be a power of two. If `ld' allocates 3434uninitialized memory for the common symbol, it will use the alignment 3435when placing the symbol. If no alignment is specified, `as' will set 3436the alignment to the largest power of two less than or equal to the 3437size of the symbol, up to a maximum of 16 on ELF, or the default 3438section alignment of 4 on PE(1). 3439 3440 The syntax for `.comm' differs slightly on the HPPA. The syntax is 3441`SYMBOL .comm, LENGTH'; SYMBOL is optional. 3442 3443 ---------- Footnotes ---------- 3444 3445 (1) This is not the same as the executable image file alignment 3446controlled by `ld''s `--section-alignment' option; image file sections 3447in PE are aligned to multiples of 4096, which is far too large an 3448alignment for ordinary variables. It is rather the default alignment 3449for (non-debug) sections within object (`*.o') files, which are less 3450strictly aligned. 3451 3452 3453File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops 3454 34557.31 `.data SUBSECTION' 3456======================= 3457 3458`.data' tells `as' to assemble the following statements onto the end of 3459the data subsection numbered SUBSECTION (which is an absolute 3460expression). If SUBSECTION is omitted, it defaults to zero. 3461 3462 3463File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops 3464 34657.32 `.def NAME' 3466================ 3467 3468Begin defining debugging information for a symbol NAME; the definition 3469extends until the `.endef' directive is encountered. 3470 3471 3472File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 3473 34747.33 `.desc SYMBOL, ABS-EXPRESSION' 3475=================================== 3476 3477This directive sets the descriptor of the symbol (*note Symbol 3478Attributes::) to the low 16 bits of an absolute expression. 3479 3480 The `.desc' directive is not available when `as' is configured for 3481COFF output; it is only for `a.out' or `b.out' object format. For the 3482sake of compatibility, `as' accepts it, but produces no output, when 3483configured for COFF. 3484 3485 3486File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 3487 34887.34 `.dim' 3489=========== 3490 3491This directive is generated by compilers to include auxiliary debugging 3492information in the symbol table. It is only permitted inside 3493`.def'/`.endef' pairs. 3494 3495 3496File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 3497 34987.35 `.double FLONUMS' 3499====================== 3500 3501`.double' expects zero or more flonums, separated by commas. It 3502assembles floating point numbers. The exact kind of floating point 3503numbers emitted depends on how `as' is configured. *Note Machine 3504Dependencies::. 3505 3506 3507File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 3508 35097.36 `.eject' 3510============= 3511 3512Force a page break at this point, when generating assembly listings. 3513 3514 3515File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 3516 35177.37 `.else' 3518============ 3519 3520`.else' is part of the `as' support for conditional assembly; see *Note 3521`.if': If. It marks the beginning of a section of code to be assembled 3522if the condition for the preceding `.if' was false. 3523 3524 3525File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 3526 35277.38 `.elseif' 3528============== 3529 3530`.elseif' is part of the `as' support for conditional assembly; see 3531*Note `.if': If. It is shorthand for beginning a new `.if' block that 3532would otherwise fill the entire `.else' section. 3533 3534 3535File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 3536 35377.39 `.end' 3538=========== 3539 3540`.end' marks the end of the assembly file. `as' does not process 3541anything in the file past the `.end' directive. 3542 3543 3544File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 3545 35467.40 `.endef' 3547============= 3548 3549This directive flags the end of a symbol definition begun with `.def'. 3550 3551 3552File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 3553 35547.41 `.endfunc' 3555=============== 3556 3557`.endfunc' marks the end of a function specified with `.func'. 3558 3559 3560File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 3561 35627.42 `.endif' 3563============= 3564 3565`.endif' is part of the `as' support for conditional assembly; it marks 3566the end of a block of code that is only assembled conditionally. *Note 3567`.if': If. 3568 3569 3570File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 3571 35727.43 `.equ SYMBOL, EXPRESSION' 3573============================== 3574 3575This directive sets the value of SYMBOL to EXPRESSION. It is 3576synonymous with `.set'; see *Note `.set': Set. 3577 3578 The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'. 3579 3580 The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'. On the 3581Z80 it is an eror if SYMBOL is already defined, but the symbol is not 3582protected from later redefinition. Compare *Note Equiv::. 3583 3584 3585File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 3586 35877.44 `.equiv SYMBOL, EXPRESSION' 3588================================ 3589 3590The `.equiv' directive is like `.equ' and `.set', except that the 3591assembler will signal an error if SYMBOL is already defined. Note a 3592symbol which has been referenced but not actually defined is considered 3593to be undefined. 3594 3595 Except for the contents of the error message, this is roughly 3596equivalent to 3597 .ifdef SYM 3598 .err 3599 .endif 3600 .equ SYM,VAL 3601 plus it protects the symbol from later redefinition. 3602 3603 3604File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 3605 36067.45 `.eqv SYMBOL, EXPRESSION' 3607============================== 3608 3609The `.eqv' directive is like `.equiv', but no attempt is made to 3610evaluate the expression or any part of it immediately. Instead each 3611time the resulting symbol is used in an expression, a snapshot of its 3612current value is taken. 3613 3614 3615File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 3616 36177.46 `.err' 3618=========== 3619 3620If `as' assembles a `.err' directive, it will print an error message 3621and, unless the `-Z' option was used, it will not generate an object 3622file. This can be used to signal an error in conditionally compiled 3623code. 3624 3625 3626File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 3627 36287.47 `.error "STRING"' 3629====================== 3630 3631Similarly to `.err', this directive emits an error, but you can specify 3632a string that will be emitted as the error message. If you don't 3633specify the message, it defaults to `".error directive invoked in 3634source file"'. *Note Error and Warning Messages: Errors. 3635 3636 .error "This code has not been assembled and tested." 3637 3638 3639File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 3640 36417.48 `.exitm' 3642============= 3643 3644Exit early from the current macro definition. *Note Macro::. 3645 3646 3647File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 3648 36497.49 `.extern' 3650============== 3651 3652`.extern' is accepted in the source program--for compatibility with 3653other assemblers--but it is ignored. `as' treats all undefined symbols 3654as external. 3655 3656 3657File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 3658 36597.50 `.fail EXPRESSION' 3660======================= 3661 3662Generates an error or a warning. If the value of the EXPRESSION is 500 3663or more, `as' will print a warning message. If the value is less than 3664500, `as' will print an error message. The message will include the 3665value of EXPRESSION. This can occasionally be useful inside complex 3666nested macros or conditional assembly. 3667 3668 3669File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 3670 36717.51 `.file' 3672============ 3673 3674There are two different versions of the `.file' directive. Targets 3675that support DWARF2 line number information use the DWARF2 version of 3676`.file'. Other targets use the default version. 3677 3678Default Version 3679--------------- 3680 3681This version of the `.file' directive tells `as' that we are about to 3682start a new logical file. The syntax is: 3683 3684 .file STRING 3685 3686 STRING is the new file name. In general, the filename is recognized 3687whether or not it is surrounded by quotes `"'; but if you wish to 3688specify an empty file name, you must give the quotes-`""'. This 3689statement may go away in future: it is only recognized to be compatible 3690with old `as' programs. 3691 3692DWARF2 Version 3693-------------- 3694 3695When emitting DWARF2 line number information, `.file' assigns filenames 3696to the `.debug_line' file name table. The syntax is: 3697 3698 .file FILENO FILENAME 3699 3700 The FILENO operand should be a unique positive integer to use as the 3701index of the entry in the table. The FILENAME operand is a C string 3702literal. 3703 3704 The detail of filename indices is exposed to the user because the 3705filename table is shared with the `.debug_info' section of the DWARF2 3706debugging information, and thus the user must know the exact indices 3707that table entries will have. 3708 3709 3710File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 3711 37127.52 `.fill REPEAT , SIZE , VALUE' 3713================================== 3714 3715REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 3716copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 3717more, but if it is more than 8, then it is deemed to have the value 8, 3718compatible with other people's assemblers. The contents of each REPEAT 3719bytes is taken from an 8-byte number. The highest order 4 bytes are 3720zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 3721an integer on the computer `as' is assembling for. Each SIZE bytes in 3722a repetition is taken from the lowest order SIZE bytes of this number. 3723Again, this bizarre behavior is compatible with other people's 3724assemblers. 3725 3726 SIZE and VALUE are optional. If the second comma and VALUE are 3727absent, VALUE is assumed zero. If the first comma and following tokens 3728are absent, SIZE is assumed to be 1. 3729 3730 3731File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 3732 37337.53 `.float FLONUMS' 3734===================== 3735 3736This directive assembles zero or more flonums, separated by commas. It 3737has the same effect as `.single'. The exact kind of floating point 3738numbers emitted depends on how `as' is configured. *Note Machine 3739Dependencies::. 3740 3741 3742File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 3743 37447.54 `.func NAME[,LABEL]' 3745========================= 3746 3747`.func' emits debugging information to denote function NAME, and is 3748ignored unless the file is assembled with debugging enabled. Only 3749`--gstabs[+]' is currently supported. LABEL is the entry point of the 3750function and if omitted NAME prepended with the `leading char' is used. 3751`leading char' is usually `_' or nothing, depending on the target. All 3752functions are currently defined to have `void' return type. The 3753function must be terminated with `.endfunc'. 3754 3755 3756File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 3757 37587.55 `.global SYMBOL', `.globl SYMBOL' 3759====================================== 3760 3761`.global' makes the symbol visible to `ld'. If you define SYMBOL in 3762your partial program, its value is made available to other partial 3763programs that are linked with it. Otherwise, SYMBOL takes its 3764attributes from a symbol of the same name from another file linked into 3765the same program. 3766 3767 Both spellings (`.globl' and `.global') are accepted, for 3768compatibility with other assemblers. 3769 3770 On the HPPA, `.global' is not always enough to make it accessible to 3771other partial programs. You may need the HPPA-only `.EXPORT' directive 3772as well. *Note HPPA Assembler Directives: HPPA Directives. 3773 3774 3775File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 3776 37777.56 `.gnu_attribute TAG,VALUE' 3778=============================== 3779 3780Record a GNU object attribute for this file. *Note Object Attributes::. 3781 3782 3783File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 3784 37857.57 `.hidden NAMES' 3786==================== 3787 3788This is one of the ELF visibility directives. The other two are 3789`.internal' (*note `.internal': Internal.) and `.protected' (*note 3790`.protected': Protected.). 3791 3792 This directive overrides the named symbols default visibility (which 3793is set by their binding: local, global or weak). The directive sets 3794the visibility to `hidden' which means that the symbols are not visible 3795to other components. Such symbols are always considered to be 3796`protected' as well. 3797 3798 3799File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 3800 38017.58 `.hword EXPRESSIONS' 3802========================= 3803 3804This expects zero or more EXPRESSIONS, and emits a 16 bit number for 3805each. 3806 3807 This directive is a synonym for `.short'; depending on the target 3808architecture, it may also be a synonym for `.word'. 3809 3810 3811File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 3812 38137.59 `.ident' 3814============= 3815 3816This directive is used by some assemblers to place tags in object 3817files. The behavior of this directive varies depending on the target. 3818When using the a.out object file format, `as' simply accepts the 3819directive for source-file compatibility with existing assemblers, but 3820does not emit anything for it. When using COFF, comments are emitted 3821to the `.comment' or `.rdata' section, depending on the target. When 3822using ELF, comments are emitted to the `.comment' section. 3823 3824 3825File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 3826 38277.60 `.if ABSOLUTE EXPRESSION' 3828============================== 3829 3830`.if' marks the beginning of a section of code which is only considered 3831part of the source program being assembled if the argument (which must 3832be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 3833section of code must be marked by `.endif' (*note `.endif': Endif.); 3834optionally, you may include code for the alternative condition, flagged 3835by `.else' (*note `.else': Else.). If you have several conditions to 3836check, `.elseif' may be used to avoid nesting blocks if/else within 3837each subsequent `.else' block. 3838 3839 The following variants of `.if' are also supported: 3840`.ifdef SYMBOL' 3841 Assembles the following section of code if the specified SYMBOL 3842 has been defined. Note a symbol which has been referenced but not 3843 yet defined is considered to be undefined. 3844 3845`.ifb TEXT' 3846 Assembles the following section of code if the operand is blank 3847 (empty). 3848 3849`.ifc STRING1,STRING2' 3850 Assembles the following section of code if the two strings are the 3851 same. The strings may be optionally quoted with single quotes. 3852 If they are not quoted, the first string stops at the first comma, 3853 and the second string stops at the end of the line. Strings which 3854 contain whitespace should be quoted. The string comparison is 3855 case sensitive. 3856 3857`.ifeq ABSOLUTE EXPRESSION' 3858 Assembles the following section of code if the argument is zero. 3859 3860`.ifeqs STRING1,STRING2' 3861 Another form of `.ifc'. The strings must be quoted using double 3862 quotes. 3863 3864`.ifge ABSOLUTE EXPRESSION' 3865 Assembles the following section of code if the argument is greater 3866 than or equal to zero. 3867 3868`.ifgt ABSOLUTE EXPRESSION' 3869 Assembles the following section of code if the argument is greater 3870 than zero. 3871 3872`.ifle ABSOLUTE EXPRESSION' 3873 Assembles the following section of code if the argument is less 3874 than or equal to zero. 3875 3876`.iflt ABSOLUTE EXPRESSION' 3877 Assembles the following section of code if the argument is less 3878 than zero. 3879 3880`.ifnb TEXT' 3881 Like `.ifb', but the sense of the test is reversed: this assembles 3882 the following section of code if the operand is non-blank 3883 (non-empty). 3884 3885`.ifnc STRING1,STRING2.' 3886 Like `.ifc', but the sense of the test is reversed: this assembles 3887 the following section of code if the two strings are not the same. 3888 3889`.ifndef SYMBOL' 3890`.ifnotdef SYMBOL' 3891 Assembles the following section of code if the specified SYMBOL 3892 has not been defined. Both spelling variants are equivalent. 3893 Note a symbol which has been referenced but not yet defined is 3894 considered to be undefined. 3895 3896`.ifne ABSOLUTE EXPRESSION' 3897 Assembles the following section of code if the argument is not 3898 equal to zero (in other words, this is equivalent to `.if'). 3899 3900`.ifnes STRING1,STRING2' 3901 Like `.ifeqs', but the sense of the test is reversed: this 3902 assembles the following section of code if the two strings are not 3903 the same. 3904 3905 3906File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 3907 39087.61 `.incbin "FILE"[,SKIP[,COUNT]]' 3909==================================== 3910 3911The `incbin' directive includes FILE verbatim at the current location. 3912You can control the search paths used with the `-I' command-line option 3913(*note Command-Line Options: Invoking.). Quotation marks are required 3914around FILE. 3915 3916 The SKIP argument skips a number of bytes from the start of the 3917FILE. The COUNT argument indicates the maximum number of bytes to 3918read. Note that the data is not aligned in any way, so it is the user's 3919responsibility to make sure that proper alignment is provided both 3920before and after the `incbin' directive. 3921 3922 3923File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 3924 39257.62 `.include "FILE"' 3926====================== 3927 3928This directive provides a way to include supporting files at specified 3929points in your source program. The code from FILE is assembled as if 3930it followed the point of the `.include'; when the end of the included 3931file is reached, assembly of the original file continues. You can 3932control the search paths used with the `-I' command-line option (*note 3933Command-Line Options: Invoking.). Quotation marks are required around 3934FILE. 3935 3936 3937File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 3938 39397.63 `.int EXPRESSIONS' 3940======================= 3941 3942Expect zero or more EXPRESSIONS, of any section, separated by commas. 3943For each expression, emit a number that, at run time, is the value of 3944that expression. The byte order and bit size of the number depends on 3945what kind of target the assembly is for. 3946 3947 3948File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 3949 39507.64 `.internal NAMES' 3951====================== 3952 3953This is one of the ELF visibility directives. The other two are 3954`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note 3955`.protected': Protected.). 3956 3957 This directive overrides the named symbols default visibility (which 3958is set by their binding: local, global or weak). The directive sets 3959the visibility to `internal' which means that the symbols are 3960considered to be `hidden' (i.e., not visible to other components), and 3961that some extra, processor specific processing must also be performed 3962upon the symbols as well. 3963 3964 3965File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 3966 39677.65 `.irp SYMBOL,VALUES'... 3968============================ 3969 3970Evaluate a sequence of statements assigning different values to SYMBOL. 3971The sequence of statements starts at the `.irp' directive, and is 3972terminated by an `.endr' directive. For each VALUE, SYMBOL is set to 3973VALUE, and the sequence of statements is assembled. If no VALUE is 3974listed, the sequence of statements is assembled once, with SYMBOL set 3975to the null string. To refer to SYMBOL within the sequence of 3976statements, use \SYMBOL. 3977 3978 For example, assembling 3979 3980 .irp param,1,2,3 3981 move d\param,sp@- 3982 .endr 3983 3984 is equivalent to assembling 3985 3986 move d1,sp@- 3987 move d2,sp@- 3988 move d3,sp@- 3989 3990 For some caveats with the spelling of SYMBOL, see also *Note Macro::. 3991 3992 3993File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 3994 39957.66 `.irpc SYMBOL,VALUES'... 3996============================= 3997 3998Evaluate a sequence of statements assigning different values to SYMBOL. 3999The sequence of statements starts at the `.irpc' directive, and is 4000terminated by an `.endr' directive. For each character in VALUE, 4001SYMBOL is set to the character, and the sequence of statements is 4002assembled. If no VALUE is listed, the sequence of statements is 4003assembled once, with SYMBOL set to the null string. To refer to SYMBOL 4004within the sequence of statements, use \SYMBOL. 4005 4006 For example, assembling 4007 4008 .irpc param,123 4009 move d\param,sp@- 4010 .endr 4011 4012 is equivalent to assembling 4013 4014 move d1,sp@- 4015 move d2,sp@- 4016 move d3,sp@- 4017 4018 For some caveats with the spelling of SYMBOL, see also the discussion 4019at *Note Macro::. 4020 4021 4022File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 4023 40247.67 `.lcomm SYMBOL , LENGTH' 4025============================= 4026 4027Reserve LENGTH (an absolute expression) bytes for a local common 4028denoted by SYMBOL. The section and value of SYMBOL are those of the 4029new local common. The addresses are allocated in the bss section, so 4030that at run-time the bytes start off zeroed. SYMBOL is not declared 4031global (*note `.global': Global.), so is normally not visible to `ld'. 4032 4033 Some targets permit a third argument to be used with `.lcomm'. This 4034argument specifies the desired alignment of the symbol in the bss 4035section. 4036 4037 The syntax for `.lcomm' differs slightly on the HPPA. The syntax is 4038`SYMBOL .lcomm, LENGTH'; SYMBOL is optional. 4039 4040 4041File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 4042 40437.68 `.lflags' 4044============== 4045 4046`as' accepts this directive, for compatibility with other assemblers, 4047but ignores it. 4048 4049 4050File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 4051 40527.69 `.line LINE-NUMBER' 4053======================== 4054 4055Change the logical line number. LINE-NUMBER must be an absolute 4056expression. The next line has that logical line number. Therefore any 4057other statements on the current line (after a statement separator 4058character) are reported as on logical line number LINE-NUMBER - 1. One 4059day `as' will no longer support this directive: it is recognized only 4060for compatibility with existing assembler programs. 4061 4062Even though this is a directive associated with the `a.out' or `b.out' 4063object-code formats, `as' still recognizes it when producing COFF 4064output, and treats `.line' as though it were the COFF `.ln' _if_ it is 4065found outside a `.def'/`.endef' pair. 4066 4067 Inside a `.def', `.line' is, instead, one of the directives used by 4068compilers to generate auxiliary symbol information for debugging. 4069 4070 4071File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4072 40737.70 `.linkonce [TYPE]' 4074======================= 4075 4076Mark the current section so that the linker only includes a single copy 4077of it. This may be used to include the same section in several 4078different object files, but ensure that the linker will only include it 4079once in the final output file. The `.linkonce' pseudo-op must be used 4080for each instance of the section. Duplicate sections are detected 4081based on the section name, so it should be unique. 4082 4083 This directive is only supported by a few object file formats; as of 4084this writing, the only object file format which supports it is the 4085Portable Executable format used on Windows NT. 4086 4087 The TYPE argument is optional. If specified, it must be one of the 4088following strings. For example: 4089 .linkonce same_size 4090 Not all types may be supported on all object file formats. 4091 4092`discard' 4093 Silently discard duplicate sections. This is the default. 4094 4095`one_only' 4096 Warn if there are duplicate sections, but still keep only one copy. 4097 4098`same_size' 4099 Warn if any of the duplicates have different sizes. 4100 4101`same_contents' 4102 Warn if any of the duplicates do not have exactly the same 4103 contents. 4104 4105 4106File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4107 41087.71 `.list' 4109============ 4110 4111Control (in conjunction with the `.nolist' directive) whether or not 4112assembly listings are generated. These two directives maintain an 4113internal counter (which is zero initially). `.list' increments the 4114counter, and `.nolist' decrements it. Assembly listings are generated 4115whenever the counter is greater than zero. 4116 4117 By default, listings are disabled. When you enable them (with the 4118`-a' command line option; *note Command-Line Options: Invoking.), the 4119initial value of the listing counter is one. 4120 4121 4122File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4123 41247.72 `.ln LINE-NUMBER' 4125====================== 4126 4127`.ln' is a synonym for `.line'. 4128 4129 4130File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4131 41327.73 `.loc FILENO LINENO [COLUMN] [OPTIONS]' 4133============================================ 4134 4135When emitting DWARF2 line number information, the `.loc' directive will 4136add a row to the `.debug_line' line number matrix corresponding to the 4137immediately following assembly instruction. The FILENO, LINENO, and 4138optional COLUMN arguments will be applied to the `.debug_line' state 4139machine before the row is added. 4140 4141 The OPTIONS are a sequence of the following tokens in any order: 4142 4143`basic_block' 4144 This option will set the `basic_block' register in the 4145 `.debug_line' state machine to `true'. 4146 4147`prologue_end' 4148 This option will set the `prologue_end' register in the 4149 `.debug_line' state machine to `true'. 4150 4151`epilogue_begin' 4152 This option will set the `epilogue_begin' register in the 4153 `.debug_line' state machine to `true'. 4154 4155`is_stmt VALUE' 4156 This option will set the `is_stmt' register in the `.debug_line' 4157 state machine to `value', which must be either 0 or 1. 4158 4159`isa VALUE' 4160 This directive will set the `isa' register in the `.debug_line' 4161 state machine to VALUE, which must be an unsigned integer. 4162 4163`discriminator VALUE' 4164 This directive will set the `discriminator' register in the 4165 `.debug_line' state machine to VALUE, which must be an unsigned 4166 integer. 4167 4168 4169 4170File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4171 41727.74 `.loc_mark_labels ENABLE' 4173============================== 4174 4175When emitting DWARF2 line number information, the `.loc_mark_labels' 4176directive makes the assembler emit an entry to the `.debug_line' line 4177number matrix with the `basic_block' register in the state machine set 4178whenever a code label is seen. The ENABLE argument should be either 1 4179or 0, to enable or disable this function respectively. 4180 4181 4182File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4183 41847.75 `.local NAMES' 4185=================== 4186 4187This directive, which is available for ELF targets, marks each symbol in 4188the comma-separated list of `names' as a local symbol so that it will 4189not be externally visible. If the symbols do not already exist, they 4190will be created. 4191 4192 For targets where the `.lcomm' directive (*note Lcomm::) does not 4193accept an alignment argument, which is the case for most ELF targets, 4194the `.local' directive can be used in combination with `.comm' (*note 4195Comm::) to define aligned local common data. 4196 4197 4198File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4199 42007.76 `.long EXPRESSIONS' 4201======================== 4202 4203`.long' is the same as `.int'. *Note `.int': Int. 4204 4205 4206File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4207 42087.77 `.macro' 4209============= 4210 4211The commands `.macro' and `.endm' allow you to define macros that 4212generate assembly output. For example, this definition specifies a 4213macro `sum' that puts a sequence of numbers into memory: 4214 4215 .macro sum from=0, to=5 4216 .long \from 4217 .if \to-\from 4218 sum "(\from+1)",\to 4219 .endif 4220 .endm 4221 4222With that definition, `SUM 0,5' is equivalent to this assembly input: 4223 4224 .long 0 4225 .long 1 4226 .long 2 4227 .long 3 4228 .long 4 4229 .long 5 4230 4231`.macro MACNAME' 4232`.macro MACNAME MACARGS ...' 4233 Begin the definition of a macro called MACNAME. If your macro 4234 definition requires arguments, specify their names after the macro 4235 name, separated by commas or spaces. You can qualify the macro 4236 argument to indicate whether all invocations must specify a 4237 non-blank value (through `:`req''), or whether it takes all of the 4238 remaining arguments (through `:`vararg''). You can supply a 4239 default value for any macro argument by following the name with 4240 `=DEFLT'. You cannot define two macros with the same MACNAME 4241 unless it has been subject to the `.purgem' directive (*note 4242 Purgem::) between the two definitions. For example, these are all 4243 valid `.macro' statements: 4244 4245 `.macro comm' 4246 Begin the definition of a macro called `comm', which takes no 4247 arguments. 4248 4249 `.macro plus1 p, p1' 4250 `.macro plus1 p p1' 4251 Either statement begins the definition of a macro called 4252 `plus1', which takes two arguments; within the macro 4253 definition, write `\p' or `\p1' to evaluate the arguments. 4254 4255 `.macro reserve_str p1=0 p2' 4256 Begin the definition of a macro called `reserve_str', with two 4257 arguments. The first argument has a default value, but not 4258 the second. After the definition is complete, you can call 4259 the macro either as `reserve_str A,B' (with `\p1' evaluating 4260 to A and `\p2' evaluating to B), or as `reserve_str ,B' (with 4261 `\p1' evaluating as the default, in this case `0', and `\p2' 4262 evaluating to B). 4263 4264 `.macro m p1:req, p2=0, p3:vararg' 4265 Begin the definition of a macro called `m', with at least 4266 three arguments. The first argument must always have a value 4267 specified, but not the second, which instead has a default 4268 value. The third formal will get assigned all remaining 4269 arguments specified at invocation time. 4270 4271 When you call a macro, you can specify the argument values 4272 either by position, or by keyword. For example, `sum 9,17' 4273 is equivalent to `sum to=17, from=9'. 4274 4275 4276 Note that since each of the MACARGS can be an identifier exactly 4277 as any other one permitted by the target architecture, there may be 4278 occasional problems if the target hand-crafts special meanings to 4279 certain characters when they occur in a special position. For 4280 example, if the colon (`:') is generally permitted to be part of a 4281 symbol name, but the architecture specific code special-cases it 4282 when occurring as the final character of a symbol (to denote a 4283 label), then the macro parameter replacement code will have no way 4284 of knowing that and consider the whole construct (including the 4285 colon) an identifier, and check only this identifier for being the 4286 subject to parameter substitution. So for example this macro 4287 definition: 4288 4289 .macro label l 4290 \l: 4291 .endm 4292 4293 might not work as expected. Invoking `label foo' might not create 4294 a label called `foo' but instead just insert the text `\l:' into 4295 the assembler source, probably generating an error about an 4296 unrecognised identifier. 4297 4298 Similarly problems might occur with the period character (`.') 4299 which is often allowed inside opcode names (and hence identifier 4300 names). So for example constructing a macro to build an opcode 4301 from a base name and a length specifier like this: 4302 4303 .macro opcode base length 4304 \base.\length 4305 .endm 4306 4307 and invoking it as `opcode store l' will not create a `store.l' 4308 instruction but instead generate some kind of error as the 4309 assembler tries to interpret the text `\base.\length'. 4310 4311 There are several possible ways around this problem: 4312 4313 `Insert white space' 4314 If it is possible to use white space characters then this is 4315 the simplest solution. eg: 4316 4317 .macro label l 4318 \l : 4319 .endm 4320 4321 `Use `\()'' 4322 The string `\()' can be used to separate the end of a macro 4323 argument from the following text. eg: 4324 4325 .macro opcode base length 4326 \base\().\length 4327 .endm 4328 4329 `Use the alternate macro syntax mode' 4330 In the alternative macro syntax mode the ampersand character 4331 (`&') can be used as a separator. eg: 4332 4333 .altmacro 4334 .macro label l 4335 l&: 4336 .endm 4337 4338 Note: this problem of correctly identifying string parameters to 4339 pseudo ops also applies to the identifiers used in `.irp' (*note 4340 Irp::) and `.irpc' (*note Irpc::) as well. 4341 4342`.endm' 4343 Mark the end of a macro definition. 4344 4345`.exitm' 4346 Exit early from the current macro definition. 4347 4348`\@' 4349 `as' maintains a counter of how many macros it has executed in 4350 this pseudo-variable; you can copy that number to your output with 4351 `\@', but _only within a macro definition_. 4352 4353`LOCAL NAME [ , ... ]' 4354 _Warning: `LOCAL' is only available if you select "alternate macro 4355 syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro': 4356 Altmacro. 4357 4358 4359File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4360 43617.78 `.mri VAL' 4362=============== 4363 4364If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero, 4365this tells `as' to exit MRI mode. This change affects code assembled 4366until the next `.mri' directive, or until the end of the file. *Note 4367MRI mode: M. 4368 4369 4370File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4371 43727.79 `.noaltmacro' 4373================== 4374 4375Disable alternate macro mode. *Note Altmacro::. 4376 4377 4378File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops 4379 43807.80 `.nolist' 4381============== 4382 4383Control (in conjunction with the `.list' directive) whether or not 4384assembly listings are generated. These two directives maintain an 4385internal counter (which is zero initially). `.list' increments the 4386counter, and `.nolist' decrements it. Assembly listings are generated 4387whenever the counter is greater than zero. 4388 4389 4390File: as.info, Node: Octa, Next: Org, Prev: Nolist, Up: Pseudo Ops 4391 43927.81 `.octa BIGNUMS' 4393==================== 4394 4395This directive expects zero or more bignums, separated by commas. For 4396each bignum, it emits a 16-byte integer. 4397 4398 The term "octa" comes from contexts in which a "word" is two bytes; 4399hence _octa_-word for 16 bytes. 4400 4401 4402File: as.info, Node: Org, Next: P2align, Prev: Octa, Up: Pseudo Ops 4403 44047.82 `.org NEW-LC , FILL' 4405========================= 4406 4407Advance the location counter of the current section to NEW-LC. NEW-LC 4408is either an absolute expression or an expression with the same section 4409as the current subsection. That is, you can't use `.org' to cross 4410sections: if NEW-LC has the wrong section, the `.org' directive is 4411ignored. To be compatible with former assemblers, if the section of 4412NEW-LC is absolute, `as' issues a warning, then pretends the section of 4413NEW-LC is the same as the current subsection. 4414 4415 `.org' may only increase the location counter, or leave it 4416unchanged; you cannot use `.org' to move the location counter backwards. 4417 4418 Because `as' tries to assemble programs in one pass, NEW-LC may not 4419be undefined. If you really detest this restriction we eagerly await a 4420chance to share your improved assembler. 4421 4422 Beware that the origin is relative to the start of the section, not 4423to the start of the subsection. This is compatible with other people's 4424assemblers. 4425 4426 When the location counter (of the current subsection) is advanced, 4427the intervening bytes are filled with FILL which should be an absolute 4428expression. If the comma and FILL are omitted, FILL defaults to zero. 4429 4430 4431File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 4432 44337.83 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 4434================================================ 4435 4436Pad the location counter (in the current subsection) to a particular 4437storage boundary. The first expression (which must be absolute) is the 4438number of low-order zero bits the location counter must have after 4439advancement. For example `.p2align 3' advances the location counter 4440until it a multiple of 8. If the location counter is already a 4441multiple of 8, no change is needed. 4442 4443 The second expression (also absolute) gives the fill value to be 4444stored in the padding bytes. It (and the comma) may be omitted. If it 4445is omitted, the padding bytes are normally zero. However, on some 4446systems, if the section is marked as containing code and the fill value 4447is omitted, the space is filled with no-op instructions. 4448 4449 The third expression is also absolute, and is also optional. If it 4450is present, it is the maximum number of bytes that should be skipped by 4451this alignment directive. If doing the alignment would require 4452skipping more bytes than the specified maximum, then the alignment is 4453not done at all. You can omit the fill value (the second argument) 4454entirely by simply using two commas after the required alignment; this 4455can be useful if you want the alignment to be filled with no-op 4456instructions when appropriate. 4457 4458 The `.p2alignw' and `.p2alignl' directives are variants of the 4459`.p2align' directive. The `.p2alignw' directive treats the fill 4460pattern as a two byte word value. The `.p2alignl' directives treats the 4461fill pattern as a four byte longword value. For example, `.p2alignw 44622,0x368d' will align to a multiple of 4. If it skips two bytes, they 4463will be filled in with the value 0x368d (the exact placement of the 4464bytes depends upon the endianness of the processor). If it skips 1 or 44653 bytes, the fill value is undefined. 4466 4467 4468File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 4469 44707.84 `.popsection' 4471================== 4472 4473This is one of the ELF section stack manipulation directives. The 4474others are `.section' (*note Section::), `.subsection' (*note 4475SubSection::), `.pushsection' (*note PushSection::), and `.previous' 4476(*note Previous::). 4477 4478 This directive replaces the current section (and subsection) with 4479the top section (and subsection) on the section stack. This section is 4480popped off the stack. 4481 4482 4483File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 4484 44857.85 `.previous' 4486================ 4487 4488This is one of the ELF section stack manipulation directives. The 4489others are `.section' (*note Section::), `.subsection' (*note 4490SubSection::), `.pushsection' (*note PushSection::), and `.popsection' 4491(*note PopSection::). 4492 4493 This directive swaps the current section (and subsection) with most 4494recently referenced section/subsection pair prior to this one. Multiple 4495`.previous' directives in a row will flip between two sections (and 4496their subsections). For example: 4497 4498 .section A 4499 .subsection 1 4500 .word 0x1234 4501 .subsection 2 4502 .word 0x5678 4503 .previous 4504 .word 0x9abc 4505 4506 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 4507subsection 2 of section A. Whilst: 4508 4509 .section A 4510 .subsection 1 4511 # Now in section A subsection 1 4512 .word 0x1234 4513 .section B 4514 .subsection 0 4515 # Now in section B subsection 0 4516 .word 0x5678 4517 .subsection 1 4518 # Now in section B subsection 1 4519 .word 0x9abc 4520 .previous 4521 # Now in section B subsection 0 4522 .word 0xdef0 4523 4524 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 45250 of section B and 0x9abc into subsection 1 of section B. 4526 4527 In terms of the section stack, this directive swaps the current 4528section with the top section on the section stack. 4529 4530 4531File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 4532 45337.86 `.print STRING' 4534==================== 4535 4536`as' will print STRING on the standard output during assembly. You 4537must put STRING in double quotes. 4538 4539 4540File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 4541 45427.87 `.protected NAMES' 4543======================= 4544 4545This is one of the ELF visibility directives. The other two are 4546`.hidden' (*note Hidden::) and `.internal' (*note Internal::). 4547 4548 This directive overrides the named symbols default visibility (which 4549is set by their binding: local, global or weak). The directive sets 4550the visibility to `protected' which means that any references to the 4551symbols from within the components that defines them must be resolved 4552to the definition in that component, even if a definition in another 4553component would normally preempt this. 4554 4555 4556File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 4557 45587.88 `.psize LINES , COLUMNS' 4559============================= 4560 4561Use this directive to declare the number of lines--and, optionally, the 4562number of columns--to use for each page, when generating listings. 4563 4564 If you do not use `.psize', listings use a default line-count of 60. 4565You may omit the comma and COLUMNS specification; the default width is 4566200 columns. 4567 4568 `as' generates formfeeds whenever the specified number of lines is 4569exceeded (or whenever you explicitly request one, using `.eject'). 4570 4571 If you specify LINES as `0', no formfeeds are generated save those 4572explicitly specified with `.eject'. 4573 4574 4575File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 4576 45777.89 `.purgem NAME' 4578=================== 4579 4580Undefine the macro NAME, so that later uses of the string will not be 4581expanded. *Note Macro::. 4582 4583 4584File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 4585 45867.90 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' 4587======================================================================== 4588 4589This is one of the ELF section stack manipulation directives. The 4590others are `.section' (*note Section::), `.subsection' (*note 4591SubSection::), `.popsection' (*note PopSection::), and `.previous' 4592(*note Previous::). 4593 4594 This directive pushes the current section (and subsection) onto the 4595top of the section stack, and then replaces the current section and 4596subsection with `name' and `subsection'. The optional `flags', `type' 4597and `arguments' are treated the same as in the `.section' (*note 4598Section::) directive. 4599 4600 4601File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 4602 46037.91 `.quad BIGNUMS' 4604==================== 4605 4606`.quad' expects zero or more bignums, separated by commas. For each 4607bignum, it emits an 8-byte integer. If the bignum won't fit in 8 4608bytes, it prints a warning message; and just takes the lowest order 8 4609bytes of the bignum. 4610 4611 The term "quad" comes from contexts in which a "word" is two bytes; 4612hence _quad_-word for 8 bytes. 4613 4614 4615File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 4616 46177.92 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 4618============================================== 4619 4620Generate a relocation at OFFSET of type RELOC_NAME with value 4621EXPRESSION. If OFFSET is a number, the relocation is generated in the 4622current section. If OFFSET is an expression that resolves to a symbol 4623plus offset, the relocation is generated in the given symbol's section. 4624EXPRESSION, if present, must resolve to a symbol plus addend or to an 4625absolute value, but note that not all targets support an addend. e.g. 4626ELF REL targets such as i386 store an addend in the section contents 4627rather than in the relocation. This low level interface does not 4628support addends stored in the section. 4629 4630 4631File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 4632 46337.93 `.rept COUNT' 4634================== 4635 4636Repeat the sequence of lines between the `.rept' directive and the next 4637`.endr' directive COUNT times. 4638 4639 For example, assembling 4640 4641 .rept 3 4642 .long 0 4643 .endr 4644 4645 is equivalent to assembling 4646 4647 .long 0 4648 .long 0 4649 .long 0 4650 4651 4652File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 4653 46547.94 `.sbttl "SUBHEADING"' 4655========================== 4656 4657Use SUBHEADING as the title (third line, immediately after the title 4658line) when generating assembly listings. 4659 4660 This directive affects subsequent pages, as well as the current page 4661if it appears within ten lines of the top of a page. 4662 4663 4664File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 4665 46667.95 `.scl CLASS' 4667================= 4668 4669Set the storage-class value for a symbol. This directive may only be 4670used inside a `.def'/`.endef' pair. Storage class may flag whether a 4671symbol is static or external, or it may record further symbolic 4672debugging information. 4673 4674 4675File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 4676 46777.96 `.section NAME' 4678==================== 4679 4680Use the `.section' directive to assemble the following code into a 4681section named NAME. 4682 4683 This directive is only supported for targets that actually support 4684arbitrarily named sections; on `a.out' targets, for example, it is not 4685accepted, even with a standard `a.out' section name. 4686 4687COFF Version 4688------------ 4689 4690 For COFF targets, the `.section' directive is used in one of the 4691following ways: 4692 4693 .section NAME[, "FLAGS"] 4694 .section NAME[, SUBSECTION] 4695 4696 If the optional argument is quoted, it is taken as flags to use for 4697the section. Each flag is a single character. The following flags are 4698recognized: 4699`b' 4700 bss section (uninitialized data) 4701 4702`n' 4703 section is not loaded 4704 4705`w' 4706 writable section 4707 4708`d' 4709 data section 4710 4711`r' 4712 read-only section 4713 4714`x' 4715 executable section 4716 4717`s' 4718 shared section (meaningful for PE targets) 4719 4720`a' 4721 ignored. (For compatibility with the ELF version) 4722 4723`y' 4724 section is not readable (meaningful for PE targets) 4725 4726`0-9' 4727 single-digit power-of-two section alignment (GNU extension) 4728 4729 If no flags are specified, the default flags depend upon the section 4730name. If the section name is not recognized, the default will be for 4731the section to be loaded and writable. Note the `n' and `w' flags 4732remove attributes from the section, rather than adding them, so if they 4733are used on their own it will be as if no flags had been specified at 4734all. 4735 4736 If the optional argument to the `.section' directive is not quoted, 4737it is taken as a subsection number (*note Sub-Sections::). 4738 4739ELF Version 4740----------- 4741 4742 This is one of the ELF section stack manipulation directives. The 4743others are `.subsection' (*note SubSection::), `.pushsection' (*note 4744PushSection::), `.popsection' (*note PopSection::), and `.previous' 4745(*note Previous::). 4746 4747 For ELF targets, the `.section' directive is used like this: 4748 4749 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 4750 4751 The optional FLAGS argument is a quoted string which may contain any 4752combination of the following characters: 4753`a' 4754 section is allocatable 4755 4756`e' 4757 section is excluded from executable and shared library. 4758 4759`w' 4760 section is writable 4761 4762`x' 4763 section is executable 4764 4765`M' 4766 section is mergeable 4767 4768`S' 4769 section contains zero terminated strings 4770 4771`G' 4772 section is a member of a section group 4773 4774`T' 4775 section is used for thread-local-storage 4776 4777`?' 4778 section is a member of the previously-current section's group, if 4779 any 4780 4781 The optional TYPE argument may contain one of the following 4782constants: 4783`@progbits' 4784 section contains data 4785 4786`@nobits' 4787 section does not contain data (i.e., section only occupies space) 4788 4789`@note' 4790 section contains data which is used by things other than the 4791 program 4792 4793`@init_array' 4794 section contains an array of pointers to init functions 4795 4796`@fini_array' 4797 section contains an array of pointers to finish functions 4798 4799`@preinit_array' 4800 section contains an array of pointers to pre-init functions 4801 4802 Many targets only support the first three section types. 4803 4804 Note on targets where the `@' character is the start of a comment (eg 4805ARM) then another character is used instead. For example the ARM port 4806uses the `%' character. 4807 4808 If FLAGS contains the `M' symbol then the TYPE argument must be 4809specified as well as an extra argument--ENTSIZE--like this: 4810 4811 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 4812 4813 Sections with the `M' flag but not `S' flag must contain fixed size 4814constants, each ENTSIZE octets long. Sections with both `M' and `S' 4815must contain zero terminated strings where each character is ENTSIZE 4816bytes long. The linker may remove duplicates within sections with the 4817same name, same entity size and same flags. ENTSIZE must be an 4818absolute expression. For sections with both `M' and `S', a string 4819which is a suffix of a larger string is considered a duplicate. Thus 4820`"def"' will be merged with `"abcdef"'; A reference to the first 4821`"def"' will be changed to a reference to `"abcdef"+3'. 4822 4823 If FLAGS contains the `G' symbol then the TYPE argument must be 4824present along with an additional field like this: 4825 4826 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 4827 4828 The GROUPNAME field specifies the name of the section group to which 4829this particular section belongs. The optional linkage field can 4830contain: 4831`comdat' 4832 indicates that only one copy of this section should be retained 4833 4834`.gnu.linkonce' 4835 an alias for comdat 4836 4837 Note: if both the M and G flags are present then the fields for the 4838Merge flag should come first, like this: 4839 4840 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 4841 4842 If FLAGS contains the `?' symbol then it may not also contain the 4843`G' symbol and the GROUPNAME or LINKAGE fields should not be present. 4844Instead, `?' says to consider the section that's current before this 4845directive. If that section used `G', then the new section will use `G' 4846with those same GROUPNAME and LINKAGE fields implicitly. If not, then 4847the `?' symbol has no effect. 4848 4849 If no flags are specified, the default flags depend upon the section 4850name. If the section name is not recognized, the default will be for 4851the section to have none of the above flags: it will not be allocated 4852in memory, nor writable, nor executable. The section will contain data. 4853 4854 For ELF targets, the assembler supports another type of `.section' 4855directive for compatibility with the Solaris assembler: 4856 4857 .section "NAME"[, FLAGS...] 4858 4859 Note that the section name is quoted. There may be a sequence of 4860comma separated flags: 4861`#alloc' 4862 section is allocatable 4863 4864`#write' 4865 section is writable 4866 4867`#execinstr' 4868 section is executable 4869 4870`#exclude' 4871 section is excluded from executable and shared library. 4872 4873`#tls' 4874 section is used for thread local storage 4875 4876 This directive replaces the current section and subsection. See the 4877contents of the gas testsuite directory `gas/testsuite/gas/elf' for 4878some examples of how this directive and the other section stack 4879directives work. 4880 4881 4882File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 4883 48847.97 `.set SYMBOL, EXPRESSION' 4885============================== 4886 4887Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and 4888type to conform to EXPRESSION. If SYMBOL was flagged as external, it 4889remains flagged (*note Symbol Attributes::). 4890 4891 You may `.set' a symbol many times in the same assembly. 4892 4893 If you `.set' a global symbol, the value stored in the object file 4894is the last value stored into it. 4895 4896 On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION' 4897instead. 4898 4899 4900File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 4901 49027.98 `.short EXPRESSIONS' 4903========================= 4904 4905`.short' is normally the same as `.word'. *Note `.word': Word. 4906 4907 In some configurations, however, `.short' and `.word' generate 4908numbers of different lengths. *Note Machine Dependencies::. 4909 4910 4911File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 4912 49137.99 `.single FLONUMS' 4914====================== 4915 4916This directive assembles zero or more flonums, separated by commas. It 4917has the same effect as `.float'. The exact kind of floating point 4918numbers emitted depends on how `as' is configured. *Note Machine 4919Dependencies::. 4920 4921 4922File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 4923 49247.100 `.size' 4925============= 4926 4927This directive is used to set the size associated with a symbol. 4928 4929COFF Version 4930------------ 4931 4932 For COFF targets, the `.size' directive is only permitted inside 4933`.def'/`.endef' pairs. It is used like this: 4934 4935 .size EXPRESSION 4936 4937ELF Version 4938----------- 4939 4940 For ELF targets, the `.size' directive is used like this: 4941 4942 .size NAME , EXPRESSION 4943 4944 This directive sets the size associated with a symbol NAME. The 4945size in bytes is computed from EXPRESSION which can make use of label 4946arithmetic. This directive is typically used to set the size of 4947function symbols. 4948 4949 4950File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 4951 49527.101 `.skip SIZE , FILL' 4953========================= 4954 4955This directive emits SIZE bytes, each of value FILL. Both SIZE and 4956FILL are absolute expressions. If the comma and FILL are omitted, FILL 4957is assumed to be zero. This is the same as `.space'. 4958 4959 4960File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 4961 49627.102 `.sleb128 EXPRESSIONS' 4963============================ 4964 4965SLEB128 stands for "signed little endian base 128." This is a compact, 4966variable length representation of numbers used by the DWARF symbolic 4967debugging format. *Note `.uleb128': Uleb128. 4968 4969 4970File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 4971 49727.103 `.space SIZE , FILL' 4973========================== 4974 4975This directive emits SIZE bytes, each of value FILL. Both SIZE and 4976FILL are absolute expressions. If the comma and FILL are omitted, FILL 4977is assumed to be zero. This is the same as `.skip'. 4978 4979 _Warning:_ `.space' has a completely different meaning for HPPA 4980 targets; use `.block' as a substitute. See `HP9000 Series 800 4981 Assembly Language Reference Manual' (HP 92432-90001) for the 4982 meaning of the `.space' directive. *Note HPPA Assembler 4983 Directives: HPPA Directives, for a summary. 4984 4985 4986File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 4987 49887.104 `.stabd, .stabn, .stabs' 4989============================== 4990 4991There are three directives that begin `.stab'. All emit symbols (*note 4992Symbols::), for use by symbolic debuggers. The symbols are not entered 4993in the `as' hash table: they cannot be referenced elsewhere in the 4994source file. Up to five fields are required: 4995 4996STRING 4997 This is the symbol's name. It may contain any character except 4998 `\000', so is more general than ordinary symbol names. Some 4999 debuggers used to code arbitrarily complex structures into symbol 5000 names using this field. 5001 5002TYPE 5003 An absolute expression. The symbol's type is set to the low 8 5004 bits of this expression. Any bit pattern is permitted, but `ld' 5005 and debuggers choke on silly bit patterns. 5006 5007OTHER 5008 An absolute expression. The symbol's "other" attribute is set to 5009 the low 8 bits of this expression. 5010 5011DESC 5012 An absolute expression. The symbol's descriptor is set to the low 5013 16 bits of this expression. 5014 5015VALUE 5016 An absolute expression which becomes the symbol's value. 5017 5018 If a warning is detected while reading a `.stabd', `.stabn', or 5019`.stabs' statement, the symbol has probably already been created; you 5020get a half-formed symbol in your object file. This is compatible with 5021earlier assemblers! 5022 5023`.stabd TYPE , OTHER , DESC' 5024 The "name" of the symbol generated is not even an empty string. 5025 It is a null pointer, for compatibility. Older assemblers used a 5026 null pointer so they didn't waste space in object files with empty 5027 strings. 5028 5029 The symbol's value is set to the location counter, relocatably. 5030 When your program is linked, the value of this symbol is the 5031 address of the location counter when the `.stabd' was assembled. 5032 5033`.stabn TYPE , OTHER , DESC , VALUE' 5034 The name of the symbol is set to the empty string `""'. 5035 5036`.stabs STRING , TYPE , OTHER , DESC , VALUE' 5037 All five fields are specified. 5038 5039 5040File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 5041 50427.105 `.string' "STR", `.string8' "STR", `.string16' 5043==================================================== 5044 5045"STR", `.string32' "STR", `.string64' "STR" 5046 5047 Copy the characters in STR to the object file. You may specify more 5048than one string to copy, separated by commas. Unless otherwise 5049specified for a particular machine, the assembler marks the end of each 5050string with a 0 byte. You can use any of the escape sequences 5051described in *Note Strings: Strings. 5052 5053 The variants `string16', `string32' and `string64' differ from the 5054`string' pseudo opcode in that each 8-bit character from STR is copied 5055and expanded to 16, 32 or 64 bits respectively. The expanded characters 5056are stored in target endianness byte order. 5057 5058 Example: 5059 .string32 "BYE" 5060 expands to: 5061 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5062 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5063 5064 5065File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5066 50677.106 `.struct EXPRESSION' 5068========================== 5069 5070Switch to the absolute section, and set the section offset to 5071EXPRESSION, which must be an absolute expression. You might use this 5072as follows: 5073 .struct 0 5074 field1: 5075 .struct field1 + 4 5076 field2: 5077 .struct field2 + 4 5078 field3: 5079 This would define the symbol `field1' to have the value 0, the symbol 5080`field2' to have the value 4, and the symbol `field3' to have the value 50818. Assembly would be left in the absolute section, and you would need 5082to use a `.section' directive of some sort to change to some other 5083section before further assembly. 5084 5085 5086File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5087 50887.107 `.subsection NAME' 5089======================== 5090 5091This is one of the ELF section stack manipulation directives. The 5092others are `.section' (*note Section::), `.pushsection' (*note 5093PushSection::), `.popsection' (*note PopSection::), and `.previous' 5094(*note Previous::). 5095 5096 This directive replaces the current subsection with `name'. The 5097current section is not changed. The replaced subsection is put onto 5098the section stack in place of the then current top of stack subsection. 5099 5100 5101File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5102 51037.108 `.symver' 5104=============== 5105 5106Use the `.symver' directive to bind symbols to specific version nodes 5107within a source file. This is only supported on ELF platforms, and is 5108typically used when assembling files to be linked into a shared library. 5109There are cases where it may make sense to use this in objects to be 5110bound into an application itself so as to override a versioned symbol 5111from a shared library. 5112 5113 For ELF targets, the `.symver' directive can be used like this: 5114 .symver NAME, NAME2@NODENAME 5115 If the symbol NAME is defined within the file being assembled, the 5116`.symver' directive effectively creates a symbol alias with the name 5117NAME2@NODENAME, and in fact the main reason that we just don't try and 5118create a regular alias is that the @ character isn't permitted in 5119symbol names. The NAME2 part of the name is the actual name of the 5120symbol by which it will be externally referenced. The name NAME itself 5121is merely a name of convenience that is used so that it is possible to 5122have definitions for multiple versions of a function within a single 5123source file, and so that the compiler can unambiguously know which 5124version of a function is being mentioned. The NODENAME portion of the 5125alias should be the name of a node specified in the version script 5126supplied to the linker when building a shared library. If you are 5127attempting to override a versioned symbol from a shared library, then 5128NODENAME should correspond to the nodename of the symbol you are trying 5129to override. 5130 5131 If the symbol NAME is not defined within the file being assembled, 5132all references to NAME will be changed to NAME2@NODENAME. If no 5133reference to NAME is made, NAME2@NODENAME will be removed from the 5134symbol table. 5135 5136 Another usage of the `.symver' directive is: 5137 .symver NAME, NAME2@@NODENAME 5138 In this case, the symbol NAME must exist and be defined within the 5139file being assembled. It is similar to NAME2@NODENAME. The difference 5140is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5141the linker. 5142 5143 The third usage of the `.symver' directive is: 5144 .symver NAME, NAME2@@@NODENAME 5145 When NAME is not defined within the file being assembled, it is 5146treated as NAME2@NODENAME. When NAME is defined within the file being 5147assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5148 5149 5150File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5151 51527.109 `.tag STRUCTNAME' 5153======================= 5154 5155This directive is generated by compilers to include auxiliary debugging 5156information in the symbol table. It is only permitted inside 5157`.def'/`.endef' pairs. Tags are used to link structure definitions in 5158the symbol table with instances of those structures. 5159 5160 5161File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5162 51637.110 `.text SUBSECTION' 5164======================== 5165 5166Tells `as' to assemble the following statements onto the end of the 5167text subsection numbered SUBSECTION, which is an absolute expression. 5168If SUBSECTION is omitted, subsection number zero is used. 5169 5170 5171File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops 5172 51737.111 `.title "HEADING"' 5174======================== 5175 5176Use HEADING as the title (second line, immediately after the source 5177file name and pagenumber) when generating assembly listings. 5178 5179 This directive affects subsequent pages, as well as the current page 5180if it appears within ten lines of the top of a page. 5181 5182 5183File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops 5184 51857.112 `.type' 5186============= 5187 5188This directive is used to set the type of a symbol. 5189 5190COFF Version 5191------------ 5192 5193 For COFF targets, this directive is permitted only within 5194`.def'/`.endef' pairs. It is used like this: 5195 5196 .type INT 5197 5198 This records the integer INT as the type attribute of a symbol table 5199entry. 5200 5201ELF Version 5202----------- 5203 5204 For ELF targets, the `.type' directive is used like this: 5205 5206 .type NAME , TYPE DESCRIPTION 5207 5208 This sets the type of symbol NAME to be either a function symbol or 5209an object symbol. There are five different syntaxes supported for the 5210TYPE DESCRIPTION field, in order to provide compatibility with various 5211other assemblers. 5212 5213 Because some of the characters used in these syntaxes (such as `@' 5214and `#') are comment characters for some architectures, some of the 5215syntaxes below do not work on all architectures. The first variant 5216will be accepted by the GNU assembler on all architectures so that 5217variant should be used for maximum portability, if you do not need to 5218assemble your code with other assemblers. 5219 5220 The syntaxes supported are: 5221 5222 .type <name> STT_<TYPE_IN_UPPER_CASE> 5223 .type <name>,#<type> 5224 .type <name>,@<type> 5225 .type <name>,%<type> 5226 .type <name>,"<type>" 5227 5228 The types supported are: 5229 5230`STT_FUNC' 5231`function' 5232 Mark the symbol as being a function name. 5233 5234`STT_GNU_IFUNC' 5235`gnu_indirect_function' 5236 Mark the symbol as an indirect function when evaluated during reloc 5237 processing. (This is only supported on Linux targeted assemblers). 5238 5239`STT_OBJECT' 5240`object' 5241 Mark the symbol as being a data object. 5242 5243`STT_TLS' 5244`tls_object' 5245 Mark the symbol as being a thead-local data object. 5246 5247`STT_COMMON' 5248`common' 5249 Mark the symbol as being a common data object. 5250 5251`STT_NOTYPE' 5252`notype' 5253 Does not mark the symbol in any way. It is supported just for 5254 completeness. 5255 5256`gnu_unique_object' 5257 Marks the symbol as being a globally unique data object. The 5258 dynamic linker will make sure that in the entire process there is 5259 just one symbol with this name and type in use. (This is only 5260 supported on Linux targeted assemblers). 5261 5262 5263 Note: Some targets support extra types in addition to those listed 5264above. 5265 5266 5267File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 5268 52697.113 `.uleb128 EXPRESSIONS' 5270============================ 5271 5272ULEB128 stands for "unsigned little endian base 128." This is a 5273compact, variable length representation of numbers used by the DWARF 5274symbolic debugging format. *Note `.sleb128': Sleb128. 5275 5276 5277File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 5278 52797.114 `.val ADDR' 5280================= 5281 5282This directive, permitted only within `.def'/`.endef' pairs, records 5283the address ADDR as the value attribute of a symbol table entry. 5284 5285 5286File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 5287 52887.115 `.version "STRING"' 5289========================= 5290 5291This directive creates a `.note' section and places into it an ELF 5292formatted note of type NT_VERSION. The note's name is set to `string'. 5293 5294 5295File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 5296 52977.116 `.vtable_entry TABLE, OFFSET' 5298=================================== 5299 5300This directive finds or creates a symbol `table' and creates a 5301`VTABLE_ENTRY' relocation for it with an addend of `offset'. 5302 5303 5304File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 5305 53067.117 `.vtable_inherit CHILD, PARENT' 5307===================================== 5308 5309This directive finds the symbol `child' and finds or creates the symbol 5310`parent' and then creates a `VTABLE_INHERIT' relocation for the parent 5311whose addend is the value of the child symbol. As a special case the 5312parent name of `0' is treated as referring to the `*ABS*' section. 5313 5314 5315File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 5316 53177.118 `.warning "STRING"' 5318========================= 5319 5320Similar to the directive `.error' (*note `.error "STRING"': Error.), 5321but just emits a warning. 5322 5323 5324File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 5325 53267.119 `.weak NAMES' 5327=================== 5328 5329This directive sets the weak attribute on the comma separated list of 5330symbol `names'. If the symbols do not already exist, they will be 5331created. 5332 5333 On COFF targets other than PE, weak symbols are a GNU extension. 5334This directive sets the weak attribute on the comma separated list of 5335symbol `names'. If the symbols do not already exist, they will be 5336created. 5337 5338 On the PE target, weak symbols are supported natively as weak 5339aliases. When a weak symbol is created that is not an alias, GAS 5340creates an alternate symbol to hold the default value. 5341 5342 5343File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 5344 53457.120 `.weakref ALIAS, TARGET' 5346============================== 5347 5348This directive creates an alias to the target symbol that enables the 5349symbol to be referenced with weak-symbol semantics, but without 5350actually making it weak. If direct references or definitions of the 5351symbol are present, then the symbol will not be weak, but if all 5352references to it are through weak references, the symbol will be marked 5353as weak in the symbol table. 5354 5355 The effect is equivalent to moving all references to the alias to a 5356separate assembly source file, renaming the alias to the symbol in it, 5357declaring the symbol as weak there, and running a reloadable link to 5358merge the object files resulting from the assembly of the new source 5359file and the old source file that had the references to the alias 5360removed. 5361 5362 The alias itself never makes to the symbol table, and is entirely 5363handled within the assembler. 5364 5365 5366File: as.info, Node: Word, Next: Deprecated, Prev: Weakref, Up: Pseudo Ops 5367 53687.121 `.word EXPRESSIONS' 5369========================= 5370 5371This directive expects zero or more EXPRESSIONS, of any section, 5372separated by commas. 5373 5374 The size of the number emitted, and its byte order, depend on what 5375target computer the assembly is for. 5376 5377 _Warning: Special Treatment to support Compilers_ 5378 5379 Machines with a 32-bit address space, but that do less than 32-bit 5380addressing, require the following special treatment. If the machine of 5381interest to you does 32-bit addressing (or doesn't require it; *note 5382Machine Dependencies::), you can ignore this issue. 5383 5384 In order to assemble compiler output into something that works, `as' 5385occasionally does strange things to `.word' directives. Directives of 5386the form `.word sym1-sym2' are often emitted by compilers as part of 5387jump tables. Therefore, when `as' assembles a directive of the form 5388`.word sym1-sym2', and the difference between `sym1' and `sym2' does 5389not fit in 16 bits, `as' creates a "secondary jump table", immediately 5390before the next label. This secondary jump table is preceded by a 5391short-jump to the first byte after the secondary table. This 5392short-jump prevents the flow of control from accidentally falling into 5393the new table. Inside the table is a long-jump to `sym2'. The 5394original `.word' contains `sym1' minus the address of the long-jump to 5395`sym2'. 5396 5397 If there were several occurrences of `.word sym1-sym2' before the 5398secondary jump table, all of them are adjusted. If there was a `.word 5399sym3-sym4', that also did not fit in sixteen bits, a long-jump to 5400`sym4' is included in the secondary jump table, and the `.word' 5401directives are adjusted to contain `sym3' minus the address of the 5402long-jump to `sym4'; and so on, for as many entries in the original 5403jump table as necessary. 5404 5405 5406File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops 5407 54087.122 Deprecated Directives 5409=========================== 5410 5411One day these directives won't work. They are included for 5412compatibility with older assemblers. 5413.abort 5414 5415.line 5416 5417 5418File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 5419 54208 Object Attributes 5421******************* 5422 5423`as' assembles source files written for a specific architecture into 5424object files for that architecture. But not all object files are alike. 5425Many architectures support incompatible variations. For instance, 5426floating point arguments might be passed in floating point registers if 5427the object file requires hardware floating point support--or floating 5428point arguments might be passed in integer registers if the object file 5429supports processors with no hardware floating point unit. Or, if two 5430objects are built for different generations of the same architecture, 5431the combination may require the newer generation at run-time. 5432 5433 This information is useful during and after linking. At link time, 5434`ld' can warn about incompatible object files. After link time, tools 5435like `gdb' can use it to process the linked file correctly. 5436 5437 Compatibility information is recorded as a series of object 5438attributes. Each attribute has a "vendor", "tag", and "value". The 5439vendor is a string, and indicates who sets the meaning of the tag. The 5440tag is an integer, and indicates what property the attribute describes. 5441The value may be a string or an integer, and indicates how the 5442property affects this object. Missing attributes are the same as 5443attributes with a zero value or empty string value. 5444 5445 Object attributes were developed as part of the ABI for the ARM 5446Architecture. The file format is documented in `ELF for the ARM 5447Architecture'. 5448 5449* Menu: 5450 5451* GNU Object Attributes:: GNU Object Attributes 5452* Defining New Object Attributes:: Defining New Object Attributes 5453 5454 5455File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 5456 54578.1 GNU Object Attributes 5458========================= 5459 5460The `.gnu_attribute' directive records an object attribute with vendor 5461`gnu'. 5462 5463 Except for `Tag_compatibility', which has both an integer and a 5464string for its value, GNU attributes have a string value if the tag 5465number is odd and an integer value if the tag number is even. The 5466second bit (`TAG & 2' is set for architecture-independent attributes 5467and clear for architecture-dependent ones. 5468 54698.1.1 Common GNU attributes 5470--------------------------- 5471 5472These attributes are valid on all architectures. 5473 5474Tag_compatibility (32) 5475 The compatibility attribute takes an integer flag value and a 5476 vendor name. If the flag value is 0, the file is compatible with 5477 other toolchains. If it is 1, then the file is only compatible 5478 with the named toolchain. If it is greater than 1, the file can 5479 only be processed by other toolchains under some private 5480 arrangement indicated by the flag value and the vendor name. 5481 54828.1.2 MIPS Attributes 5483--------------------- 5484 5485Tag_GNU_MIPS_ABI_FP (4) 5486 The floating-point ABI used by this object file. The value will 5487 be: 5488 5489 * 0 for files not affected by the floating-point ABI. 5490 5491 * 1 for files using the hardware floating-point with a standard 5492 double-precision FPU. 5493 5494 * 2 for files using the hardware floating-point ABI with a 5495 single-precision FPU. 5496 5497 * 3 for files using the software floating-point ABI. 5498 5499 * 4 for files using the hardware floating-point ABI with 64-bit 5500 wide double-precision floating-point registers and 32-bit 5501 wide general purpose registers. 5502 55038.1.3 PowerPC Attributes 5504------------------------ 5505 5506Tag_GNU_Power_ABI_FP (4) 5507 The floating-point ABI used by this object file. The value will 5508 be: 5509 5510 * 0 for files not affected by the floating-point ABI. 5511 5512 * 1 for files using double-precision hardware floating-point 5513 ABI. 5514 5515 * 2 for files using the software floating-point ABI. 5516 5517 * 3 for files using single-precision hardware floating-point 5518 ABI. 5519 5520Tag_GNU_Power_ABI_Vector (8) 5521 The vector ABI used by this object file. The value will be: 5522 5523 * 0 for files not affected by the vector ABI. 5524 5525 * 1 for files using general purpose registers to pass vectors. 5526 5527 * 2 for files using AltiVec registers to pass vectors. 5528 5529 * 3 for files using SPE registers to pass vectors. 5530 5531 5532File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 5533 55348.2 Defining New Object Attributes 5535================================== 5536 5537If you want to define a new GNU object attribute, here are the places 5538you will need to modify. New attributes should be discussed on the 5539`binutils' mailing list. 5540 5541 * This manual, which is the official register of attributes. 5542 5543 * The header for your architecture `include/elf', to define the tag. 5544 5545 * The `bfd' support file for your architecture, to merge the 5546 attribute and issue any appropriate link warnings. 5547 5548 * Test cases in `ld/testsuite' for merging and link warnings. 5549 5550 * `binutils/readelf.c' to display your attribute. 5551 5552 * GCC, if you want the compiler to mark the attribute automatically. 5553 5554 5555File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 5556 55579 Machine Dependent Features 5558**************************** 5559 5560The machine instruction sets are (almost by definition) different on 5561each machine where `as' runs. Floating point representations vary as 5562well, and `as' often supports a few additional directives or 5563command-line options for compatibility with other assemblers on a 5564particular platform. Finally, some versions of `as' support special 5565pseudo-instructions for branch optimization. 5566 5567 This chapter discusses most of these differences, though it does not 5568include details on any machine's instruction set. For details on that 5569subject, see the hardware manufacturer's manual. 5570 5571* Menu: 5572 5573 5574* Alpha-Dependent:: Alpha Dependent Features 5575 5576* ARC-Dependent:: ARC Dependent Features 5577 5578* ARM-Dependent:: ARM Dependent Features 5579 5580* AVR-Dependent:: AVR Dependent Features 5581 5582* Blackfin-Dependent:: Blackfin Dependent Features 5583 5584* CR16-Dependent:: CR16 Dependent Features 5585 5586* CRIS-Dependent:: CRIS Dependent Features 5587 5588* D10V-Dependent:: D10V Dependent Features 5589 5590* D30V-Dependent:: D30V Dependent Features 5591 5592* H8/300-Dependent:: Renesas H8/300 Dependent Features 5593 5594* HPPA-Dependent:: HPPA Dependent Features 5595 5596* ESA/390-Dependent:: IBM ESA/390 Dependent Features 5597 5598* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 5599 5600* i860-Dependent:: Intel 80860 Dependent Features 5601 5602* i960-Dependent:: Intel 80960 Dependent Features 5603 5604* IA-64-Dependent:: Intel IA-64 Dependent Features 5605 5606* IP2K-Dependent:: IP2K Dependent Features 5607 5608* LM32-Dependent:: LM32 Dependent Features 5609 5610* M32C-Dependent:: M32C Dependent Features 5611 5612* M32R-Dependent:: M32R Dependent Features 5613 5614* M68K-Dependent:: M680x0 Dependent Features 5615 5616* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 5617 5618* MicroBlaze-Dependent:: MICROBLAZE Dependent Features 5619 5620* MIPS-Dependent:: MIPS Dependent Features 5621 5622* MMIX-Dependent:: MMIX Dependent Features 5623 5624* MSP430-Dependent:: MSP430 Dependent Features 5625 5626* SH-Dependent:: Renesas / SuperH SH Dependent Features 5627* SH64-Dependent:: SuperH SH64 Dependent Features 5628 5629* PDP-11-Dependent:: PDP-11 Dependent Features 5630 5631* PJ-Dependent:: picoJava Dependent Features 5632 5633* PPC-Dependent:: PowerPC Dependent Features 5634 5635* RX-Dependent:: RX Dependent Features 5636 5637* S/390-Dependent:: IBM S/390 Dependent Features 5638 5639* SCORE-Dependent:: SCORE Dependent Features 5640 5641* Sparc-Dependent:: SPARC Dependent Features 5642 5643* TIC54X-Dependent:: TI TMS320C54x Dependent Features 5644 5645* TIC6X-Dependent :: TI TMS320C6x Dependent Features 5646 5647* V850-Dependent:: V850 Dependent Features 5648 5649* Xtensa-Dependent:: Xtensa Dependent Features 5650 5651* Z80-Dependent:: Z80 Dependent Features 5652 5653* Z8000-Dependent:: Z8000 Dependent Features 5654 5655* Vax-Dependent:: VAX Dependent Features 5656 5657 5658File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Up: Machine Dependencies 5659 56609.1 Alpha Dependent Features 5661============================ 5662 5663* Menu: 5664 5665* Alpha Notes:: Notes 5666* Alpha Options:: Options 5667* Alpha Syntax:: Syntax 5668* Alpha Floating Point:: Floating Point 5669* Alpha Directives:: Alpha Machine Directives 5670* Alpha Opcodes:: Opcodes 5671 5672 5673File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 5674 56759.1.1 Notes 5676----------- 5677 5678The documentation here is primarily for the ELF object format. `as' 5679also supports the ECOFF and EVAX formats, but features specific to 5680these formats are not yet documented. 5681 5682 5683File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 5684 56859.1.2 Options 5686------------- 5687 5688`-mCPU' 5689 This option specifies the target processor. If an attempt is made 5690 to assemble an instruction which will not execute on the target 5691 processor, the assembler may either expand the instruction as a 5692 macro or issue an error message. This option is equivalent to the 5693 `.arch' directive. 5694 5695 The following processor names are recognized: `21064', `21064a', 5696 `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a', 5697 `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6', 5698 `ev67', `ev68'. The special name `all' may be used to allow the 5699 assembler to accept instructions valid for any Alpha processor. 5700 5701 In order to support existing practice in OSF/1 with respect to 5702 `.arch', and existing practice within `MILO' (the Linux ARC 5703 bootloader), the numbered processor names (e.g. 21064) enable the 5704 processor-specific PALcode instructions, while the 5705 "electro-vlasic" names (e.g. `ev4') do not. 5706 5707`-mdebug' 5708`-no-mdebug' 5709 Enables or disables the generation of `.mdebug' encapsulation for 5710 stabs directives and procedure descriptors. The default is to 5711 automatically enable `.mdebug' when the first stabs directive is 5712 seen. 5713 5714`-relax' 5715 This option forces all relocations to be put into the object file, 5716 instead of saving space and resolving some relocations at assembly 5717 time. Note that this option does not propagate all symbol 5718 arithmetic into the object file, because not all symbol arithmetic 5719 can be represented. However, the option can still be useful in 5720 specific applications. 5721 5722`-replace' 5723`-noreplace' 5724 Enables or disables the optimization of procedure calls, both at 5725 assemblage and at link time. These options are only available for 5726 VMS targets and `-replace' is the default. See section 1.4.1 of 5727 the OpenVMS Linker Utility Manual. 5728 5729`-g' 5730 This option is used when the compiler generates debug information. 5731 When `gcc' is using `mips-tfile' to generate debug information 5732 for ECOFF, local labels must be passed through to the object file. 5733 Otherwise this option has no effect. 5734 5735`-GSIZE' 5736 A local common symbol larger than SIZE is placed in `.bss', while 5737 smaller symbols are placed in `.sbss'. 5738 5739`-F' 5740`-32addr' 5741 These options are ignored for backward compatibility. 5742 5743 5744File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 5745 57469.1.3 Syntax 5747------------ 5748 5749The assembler syntax closely follow the Alpha Reference Manual; 5750assembler directives and general syntax closely follow the OSF/1 and 5751OpenVMS syntax, with a few differences for ELF. 5752 5753* Menu: 5754 5755* Alpha-Chars:: Special Characters 5756* Alpha-Regs:: Register Names 5757* Alpha-Relocs:: Relocations 5758 5759 5760File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 5761 57629.1.3.1 Special Characters 5763.......................... 5764 5765`#' is the line comment character. 5766 5767 `;' can be used instead of a newline to separate statements. 5768 5769 5770File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 5771 57729.1.3.2 Register Names 5773...................... 5774 5775The 32 integer registers are referred to as `$N' or `$rN'. In 5776addition, registers 15, 28, 29, and 30 may be referred to by the 5777symbols `$fp', `$at', `$gp', and `$sp' respectively. 5778 5779 The 32 floating-point registers are referred to as `$fN'. 5780 5781 5782File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 5783 57849.1.3.3 Relocations 5785................... 5786 5787Some of these relocations are available for ECOFF, but mostly only for 5788ELF. They are modeled after the relocation format introduced in 5789Digital Unix 4.0, but there are additions. 5790 5791 The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the 5792relocation. In some cases NUMBER is used to relate specific 5793instructions. 5794 5795 The relocation is placed at the end of the instruction like so: 5796 5797 ldah $0,a($29) !gprelhigh 5798 lda $0,a($0) !gprellow 5799 ldq $1,b($29) !literal!100 5800 ldl $2,0($1) !lituse_base!100 5801 5802`!literal' 5803`!literal!N' 5804 Used with an `ldq' instruction to load the address of a symbol 5805 from the GOT. 5806 5807 A sequence number N is optional, and if present is used to pair 5808 `lituse' relocations with this `literal' relocation. The `lituse' 5809 relocations are used by the linker to optimize the code based on 5810 the final location of the symbol. 5811 5812 Note that these optimizations are dependent on the data flow of the 5813 program. Therefore, if _any_ `lituse' is paired with a `literal' 5814 relocation, then _all_ uses of the register set by the `literal' 5815 instruction must also be marked with `lituse' relocations. This 5816 is because the original `literal' instruction may be deleted or 5817 transformed into another instruction. 5818 5819 Also note that there may be a one-to-many relationship between 5820 `literal' and `lituse', but not a many-to-one. That is, if there 5821 are two code paths that load up the same address and feed the 5822 value to a single use, then the use may not use a `lituse' 5823 relocation. 5824 5825`!lituse_base!N' 5826 Used with any memory format instruction (e.g. `ldl') to indicate 5827 that the literal is used for an address load. The offset field of 5828 the instruction must be zero. During relaxation, the code may be 5829 altered to use a gp-relative load. 5830 5831`!lituse_jsr!N' 5832 Used with a register branch format instruction (e.g. `jsr') to 5833 indicate that the literal is used for a call. During relaxation, 5834 the code may be altered to use a direct branch (e.g. `bsr'). 5835 5836`!lituse_jsrdirect!N' 5837 Similar to `lituse_jsr', but also that this call cannot be vectored 5838 through a PLT entry. This is useful for functions with special 5839 calling conventions which do not allow the normal call-clobbered 5840 registers to be clobbered. 5841 5842`!lituse_bytoff!N' 5843 Used with a byte mask instruction (e.g. `extbl') to indicate that 5844 only the low 3 bits of the address are relevant. During 5845 relaxation, the code may be altered to use an immediate instead of 5846 a register shift. 5847 5848`!lituse_addr!N' 5849 Used with any other instruction to indicate that the original 5850 address is in fact used, and the original `ldq' instruction may 5851 not be altered or deleted. This is useful in conjunction with 5852 `lituse_jsr' to test whether a weak symbol is defined. 5853 5854 ldq $27,foo($29) !literal!1 5855 beq $27,is_undef !lituse_addr!1 5856 jsr $26,($27),foo !lituse_jsr!1 5857 5858`!lituse_tlsgd!N' 5859 Used with a register branch format instruction to indicate that the 5860 literal is the call to `__tls_get_addr' used to compute the 5861 address of the thread-local storage variable whose descriptor was 5862 loaded with `!tlsgd!N'. 5863 5864`!lituse_tlsldm!N' 5865 Used with a register branch format instruction to indicate that the 5866 literal is the call to `__tls_get_addr' used to compute the 5867 address of the base of the thread-local storage block for the 5868 current module. The descriptor for the module must have been 5869 loaded with `!tlsldm!N'. 5870 5871`!gpdisp!N' 5872 Used with `ldah' and `lda' to load the GP from the current 5873 address, a-la the `ldgp' macro. The source register for the 5874 `ldah' instruction must contain the address of the `ldah' 5875 instruction. There must be exactly one `lda' instruction paired 5876 with the `ldah' instruction, though it may appear anywhere in the 5877 instruction stream. The immediate operands must be zero. 5878 5879 bsr $26,foo 5880 ldah $29,0($26) !gpdisp!1 5881 lda $29,0($29) !gpdisp!1 5882 5883`!gprelhigh' 5884 Used with an `ldah' instruction to add the high 16 bits of a 5885 32-bit displacement from the GP. 5886 5887`!gprellow' 5888 Used with any memory format instruction to add the low 16 bits of a 5889 32-bit displacement from the GP. 5890 5891`!gprel' 5892 Used with any memory format instruction to add a 16-bit 5893 displacement from the GP. 5894 5895`!samegp' 5896 Used with any branch format instruction to skip the GP load at the 5897 target address. The referenced symbol must have the same GP as the 5898 source object file, and it must be declared to either not use `$27' 5899 or perform a standard GP load in the first two instructions via the 5900 `.prologue' directive. 5901 5902`!tlsgd' 5903`!tlsgd!N' 5904 Used with an `lda' instruction to load the address of a TLS 5905 descriptor for a symbol in the GOT. 5906 5907 The sequence number N is optional, and if present it used to pair 5908 the descriptor load with both the `literal' loading the address of 5909 the `__tls_get_addr' function and the `lituse_tlsgd' marking the 5910 call to that function. 5911 5912 For proper relaxation, both the `tlsgd', `literal' and `lituse' 5913 relocations must be in the same extended basic block. That is, 5914 the relocation with the lowest address must be executed first at 5915 runtime. 5916 5917`!tlsldm' 5918`!tlsldm!N' 5919 Used with an `lda' instruction to load the address of a TLS 5920 descriptor for the current module in the GOT. 5921 5922 Similar in other respects to `tlsgd'. 5923 5924`!gotdtprel' 5925 Used with an `ldq' instruction to load the offset of the TLS 5926 symbol within its module's thread-local storage block. Also known 5927 as the dynamic thread pointer offset or dtp-relative offset. 5928 5929`!dtprelhi' 5930`!dtprello' 5931`!dtprel' 5932 Like `gprel' relocations except they compute dtp-relative offsets. 5933 5934`!gottprel' 5935 Used with an `ldq' instruction to load the offset of the TLS 5936 symbol from the thread pointer. Also known as the tp-relative 5937 offset. 5938 5939`!tprelhi' 5940`!tprello' 5941`!tprel' 5942 Like `gprel' relocations except they compute tp-relative offsets. 5943 5944 5945File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 5946 59479.1.4 Floating Point 5948-------------------- 5949 5950The Alpha family uses both IEEE and VAX floating-point numbers. 5951 5952 5953File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 5954 59559.1.5 Alpha Assembler Directives 5956-------------------------------- 5957 5958`as' for the Alpha supports many additional directives for 5959compatibility with the native assembler. This section describes them 5960only briefly. 5961 5962 These are the additional directives in `as' for the Alpha: 5963 5964`.arch CPU' 5965 Specifies the target processor. This is equivalent to the `-mCPU' 5966 command-line option. *Note Options: Alpha Options, for a list of 5967 values for CPU. 5968 5969`.ent FUNCTION[, N]' 5970 Mark the beginning of FUNCTION. An optional number may follow for 5971 compatibility with the OSF/1 assembler, but is ignored. When 5972 generating `.mdebug' information, this will create a procedure 5973 descriptor for the function. In ELF, it will mark the symbol as a 5974 function a-la the generic `.type' directive. 5975 5976`.end FUNCTION' 5977 Mark the end of FUNCTION. In ELF, it will set the size of the 5978 symbol a-la the generic `.size' directive. 5979 5980`.mask MASK, OFFSET' 5981 Indicate which of the integer registers are saved in the current 5982 function's stack frame. MASK is interpreted a bit mask in which 5983 bit N set indicates that register N is saved. The registers are 5984 saved in a block located OFFSET bytes from the "canonical frame 5985 address" (CFA) which is the value of the stack pointer on entry to 5986 the function. The registers are saved sequentially, except that 5987 the return address register (normally `$26') is saved first. 5988 5989 This and the other directives that describe the stack frame are 5990 currently only used when generating `.mdebug' information. They 5991 may in the future be used to generate DWARF2 `.debug_frame' unwind 5992 information for hand written assembly. 5993 5994`.fmask MASK, OFFSET' 5995 Indicate which of the floating-point registers are saved in the 5996 current stack frame. The MASK and OFFSET parameters are 5997 interpreted as with `.mask'. 5998 5999`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' 6000 Describes the shape of the stack frame. The frame pointer in use 6001 is FRAMEREG; normally this is either `$fp' or `$sp'. The frame 6002 pointer is FRAMEOFFSET bytes below the CFA. The return address is 6003 initially located in RETREG until it is saved as indicated in 6004 `.mask'. For compatibility with OSF/1 an optional ARGOFFSET 6005 parameter is accepted and ignored. It is believed to indicate the 6006 offset from the CFA to the saved argument registers. 6007 6008`.prologue N' 6009 Indicate that the stack frame is set up and all registers have been 6010 spilled. The argument N indicates whether and how the function 6011 uses the incoming "procedure vector" (the address of the called 6012 function) in `$27'. 0 indicates that `$27' is not used; 1 6013 indicates that the first two instructions of the function use `$27' 6014 to perform a load of the GP register; 2 indicates that `$27' is 6015 used in some non-standard way and so the linker cannot elide the 6016 load of the procedure vector during relaxation. 6017 6018`.usepv FUNCTION, WHICH' 6019 Used to indicate the use of the `$27' register, similar to 6020 `.prologue', but without the other semantics of needing to be 6021 inside an open `.ent'/`.end' block. 6022 6023 The WHICH argument should be either `no', indicating that `$27' is 6024 not used, or `std', indicating that the first two instructions of 6025 the function perform a GP load. 6026 6027 One might use this directive instead of `.prologue' if you are 6028 also using dwarf2 CFI directives. 6029 6030`.gprel32 EXPRESSION' 6031 Computes the difference between the address in EXPRESSION and the 6032 GP for the current object file, and stores it in 4 bytes. In 6033 addition to being smaller than a full 8 byte address, this also 6034 does not require a dynamic relocation when used in a shared 6035 library. 6036 6037`.t_floating EXPRESSION' 6038 Stores EXPRESSION as an IEEE double precision value. 6039 6040`.s_floating EXPRESSION' 6041 Stores EXPRESSION as an IEEE single precision value. 6042 6043`.f_floating EXPRESSION' 6044 Stores EXPRESSION as a VAX F format value. 6045 6046`.g_floating EXPRESSION' 6047 Stores EXPRESSION as a VAX G format value. 6048 6049`.d_floating EXPRESSION' 6050 Stores EXPRESSION as a VAX D format value. 6051 6052`.set FEATURE' 6053 Enables or disables various assembler features. Using the positive 6054 name of the feature enables while using `noFEATURE' disables. 6055 6056 `at' 6057 Indicates that macro expansions may clobber the "assembler 6058 temporary" (`$at' or `$28') register. Some macros may not be 6059 expanded without this and will generate an error message if 6060 `noat' is in effect. When `at' is in effect, a warning will 6061 be generated if `$at' is used by the programmer. 6062 6063 `macro' 6064 Enables the expansion of macro instructions. Note that 6065 variants of real instructions, such as `br label' vs `br 6066 $31,label' are considered alternate forms and not macros. 6067 6068 `move' 6069 `reorder' 6070 `volatile' 6071 These control whether and how the assembler may re-order 6072 instructions. Accepted for compatibility with the OSF/1 6073 assembler, but `as' does not do instruction scheduling, so 6074 these features are ignored. 6075 6076 The following directives are recognized for compatibility with the 6077OSF/1 assembler but are ignored. 6078 6079 .proc .aproc 6080 .reguse .livereg 6081 .option .aent 6082 .ugen .eflag 6083 .alias .noalias 6084 6085 6086File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 6087 60889.1.6 Opcodes 6089------------- 6090 6091For detailed information on the Alpha machine instruction set, see the 6092Alpha Architecture Handbook 6093(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 6094 6095 6096File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 6097 60989.2 ARC Dependent Features 6099========================== 6100 6101* Menu: 6102 6103* ARC Options:: Options 6104* ARC Syntax:: Syntax 6105* ARC Floating Point:: Floating Point 6106* ARC Directives:: ARC Machine Directives 6107* ARC Opcodes:: Opcodes 6108 6109 6110File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 6111 61129.2.1 Options 6113------------- 6114 6115`-marc[5|6|7|8]' 6116 This option selects the core processor variant. Using `-marc' is 6117 the same as `-marc6', which is also the default. 6118 6119 `arc5' 6120 Base instruction set. 6121 6122 `arc6' 6123 Jump-and-link (jl) instruction. No requirement of an 6124 instruction between setting flags and conditional jump. For 6125 example: 6126 6127 mov.f r0,r1 6128 beq foo 6129 6130 `arc7' 6131 Break (brk) and sleep (sleep) instructions. 6132 6133 `arc8' 6134 Software interrupt (swi) instruction. 6135 6136 6137 Note: the `.option' directive can to be used to select a core 6138 variant from within assembly code. 6139 6140`-EB' 6141 This option specifies that the output generated by the assembler 6142 should be marked as being encoded for a big-endian processor. 6143 6144`-EL' 6145 This option specifies that the output generated by the assembler 6146 should be marked as being encoded for a little-endian processor - 6147 this is the default. 6148 6149 6150 6151File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent 6152 61539.2.2 Syntax 6154------------ 6155 6156* Menu: 6157 6158* ARC-Chars:: Special Characters 6159* ARC-Regs:: Register Names 6160 6161 6162File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 6163 61649.2.2.1 Special Characters 6165.......................... 6166 6167*TODO* 6168 6169 6170File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 6171 61729.2.2.2 Register Names 6173...................... 6174 6175*TODO* 6176 6177 6178File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Syntax, Up: ARC-Dependent 6179 61809.2.3 Floating Point 6181-------------------- 6182 6183The ARC core does not currently have hardware floating point support. 6184Software floating point support is provided by `GCC' and uses IEEE 6185floating-point numbers. 6186 6187 6188File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Point, Up: ARC-Dependent 6189 61909.2.4 ARC Machine Directives 6191---------------------------- 6192 6193The ARC version of `as' supports the following additional machine 6194directives: 6195 6196`.2byte EXPRESSIONS' 6197 *TODO* 6198 6199`.3byte EXPRESSIONS' 6200 *TODO* 6201 6202`.4byte EXPRESSIONS' 6203 *TODO* 6204 6205`.extAuxRegister NAME,ADDRESS,MODE' 6206 The ARCtangent A4 has extensible auxiliary register space. The 6207 auxiliary registers can be defined in the assembler source code by 6208 using this directive. The first parameter is the NAME of the new 6209 auxiallry register. The second parameter is the ADDRESS of the 6210 register in the auxiliary register memory map for the variant of 6211 the ARC. The third parameter specifies the MODE in which the 6212 register can be operated is and it can be one of: 6213 6214 `r (readonly)' 6215 6216 `w (write only)' 6217 6218 `r|w (read or write)' 6219 6220 For example: 6221 6222 .extAuxRegister mulhi,0x12,w 6223 6224 This specifies an extension auxiliary register called _mulhi_ 6225 which is at address 0x12 in the memory space and which is only 6226 writable. 6227 6228`.extCondCode SUFFIX,VALUE' 6229 The condition codes on the ARCtangent A4 are extensible and can be 6230 specified by means of this assembler directive. They are specified 6231 by the suffix and the value for the condition code. They can be 6232 used to specify extra condition codes with any values. For 6233 example: 6234 6235 .extCondCode is_busy,0x14 6236 6237 add.is_busy r1,r2,r3 6238 bis_busy _main 6239 6240`.extCoreRegister NAME,REGNUM,MODE,SHORTCUT' 6241 Specifies an extension core register NAME for the application. 6242 This allows a register NAME with a valid REGNUM between 0 and 60, 6243 with the following as valid values for MODE 6244 6245 `_r_ (readonly)' 6246 6247 `_w_ (write only)' 6248 6249 `_r|w_ (read or write)' 6250 6251 The other parameter gives a description of the register having a 6252 SHORTCUT in the pipeline. The valid values are: 6253 6254 `can_shortcut' 6255 6256 `cannot_shortcut' 6257 6258 For example: 6259 6260 .extCoreRegister mlo,57,r,can_shortcut 6261 6262 This defines an extension core register mlo with the value 57 which 6263 can shortcut the pipeline. 6264 6265`.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS' 6266 The ARCtangent A4 allows the user to specify extension 6267 instructions. The extension instructions are not macros. The 6268 assembler creates encodings for use of these instructions 6269 according to the specification by the user. The parameters are: 6270 6271 *NAME 6272 Name of the extension instruction 6273 6274 *OPCODE 6275 Opcode to be used. (Bits 27:31 in the encoding). Valid values 6276 0x10-0x1f or 0x03 6277 6278 *SUBOPCODE 6279 Subopcode to be used. Valid values are from 0x09-0x3f. 6280 However the correct value also depends on SYNTAXCLASS 6281 6282 *SUFFIXCLASS 6283 Determines the kinds of suffixes to be allowed. Valid values 6284 are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' which 6285 indicates the absence or presence of conditional suffixes and 6286 flag setting by the extension instruction. It is also 6287 possible to specify that an instruction sets the flags and is 6288 conditional by using `SUFFIX_CODE' | `SUFFIX_FLAG'. 6289 6290 *SYNTAXCLASS 6291 Determines the syntax class for the instruction. It can have 6292 the following values: 6293 6294 ``SYNTAX_2OP':' 6295 2 Operand Instruction 6296 6297 ``SYNTAX_3OP':' 6298 3 Operand Instruction 6299 6300 In addition there could be modifiers for the syntax class as 6301 described below: 6302 6303 Syntax Class Modifiers are: 6304 6305 - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP, 6306 specifying that the first operand of a three-operand 6307 instruction must be an immediate (i.e., the result is 6308 discarded). OP1_MUST_BE_IMM is used by bitwise ORing it 6309 with SYNTAX_3OP as given in the example below. This 6310 could usually be used to set the flags using specific 6311 instructions and not retain results. 6312 6313 - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it 6314 specifies that there is an implied immediate destination 6315 operand which does not appear in the syntax. For 6316 example, if the source code contains an instruction like: 6317 6318 inst r1,r2 6319 6320 it really means that the first argument is an implied 6321 immediate (that is, the result is discarded). This is 6322 the same as though the source code were: inst 0,r1,r2. 6323 You use OP1_IMM_IMPLIED by bitwise ORing it with 6324 SYNTAX_20P. 6325 6326 6327 For example, defining 64-bit multiplier with immediate operands: 6328 6329 .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , 6330 SYNTAX_3OP|OP1_MUST_BE_IMM 6331 6332 The above specifies an extension instruction called mp64 which has 6333 3 operands, sets the flags, can be used with a condition code, for 6334 which the first operand is an immediate. (Equivalent to 6335 discarding the result of the operation). 6336 6337 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED 6338 6339 This describes a 2 operand instruction with an implicit first 6340 immediate operand. The result of this operation would be 6341 discarded. 6342 6343`.half EXPRESSIONS' 6344 *TODO* 6345 6346`.long EXPRESSIONS' 6347 *TODO* 6348 6349`.option ARC|ARC5|ARC6|ARC7|ARC8' 6350 The `.option' directive must be followed by the desired core 6351 version. Again `arc' is an alias for `arc6'. 6352 6353 Note: the `.option' directive overrides the command line option 6354 `-marc'; a warning is emitted when the version is not consistent 6355 between the two - even for the implicit default core version 6356 (arc6). 6357 6358`.short EXPRESSIONS' 6359 *TODO* 6360 6361`.word EXPRESSIONS' 6362 *TODO* 6363 6364 6365 6366File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent 6367 63689.2.5 Opcodes 6369------------- 6370 6371For information on the ARC instruction set, see `ARC Programmers 6372Reference Manual', ARC International (www.arc.com) 6373 6374 6375File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 6376 63779.3 ARM Dependent Features 6378========================== 6379 6380* Menu: 6381 6382* ARM Options:: Options 6383* ARM Syntax:: Syntax 6384* ARM Floating Point:: Floating Point 6385* ARM Directives:: ARM Machine Directives 6386* ARM Opcodes:: Opcodes 6387* ARM Mapping Symbols:: Mapping Symbols 6388* ARM Unwinding Tutorial:: Unwinding 6389 6390 6391File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 6392 63939.3.1 Options 6394------------- 6395 6396`-mcpu=PROCESSOR[+EXTENSION...]' 6397 This option specifies the target processor. The assembler will 6398 issue an error message if an attempt is made to assemble an 6399 instruction which will not execute on the target processor. The 6400 following processor names are recognized: `arm1', `arm2', `arm250', 6401 `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', 6402 `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', 6403 `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t', 6404 `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi', 6405 `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1', 6406 `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920', 6407 `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday 6408 FA526 processor), `fa626' (Faraday FA626 processor), `arm9e', 6409 `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', 6410 `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t', 6411 `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e', 6412 `arm1022e', `arm1026ej-s', `fa626te' (Faraday FA626TE processor), 6413 `fa726te' (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s', 6414 `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', 6415 `mpcore', `mpcorenovfp', `cortex-a5', `cortex-a8', `cortex-a9', 6416 `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-m4', `cortex-m3', 6417 `cortex-m1', `cortex-m0', `ep9312' (ARM920 with Cirrus Maverick 6418 coprocessor), `i80200' (Intel XScale processor) `iwmmxt' (Intel(r) 6419 XScale processor with Wireless MMX(tm) technology coprocessor) and 6420 `xscale'. The special name `all' may be used to allow the 6421 assembler to accept instructions valid for any ARM processor. 6422 6423 In addition to the basic instruction set, the assembler can be 6424 told to accept various extension mnemonics that extend the 6425 processor using the co-processor instruction space. For example, 6426 `-mcpu=arm920+maverick' is equivalent to specifying `-mcpu=ep9312'. 6427 6428 Multiple extensions may be specified, separated by a `+'. The 6429 extensions should be specified in ascending alphabetical order. 6430 6431 Some extensions may be restricted to particular architectures; 6432 this is documented in the list of extensions below. 6433 6434 Extension mnemonics may also be removed from those the assembler 6435 accepts. This is done be prepending `no' to the option that adds 6436 the extension. Extensions that are removed should be listed after 6437 all extensions which have been added, again in ascending 6438 alphabetical order. For example, `-mcpu=ep9312+nomaverick' is 6439 equivalent to specifying `-mcpu=arm920'. 6440 6441 The following extensions are currently supported: `idiv', (Integer 6442 Divide Extensions for v7-A architecture), `iwmmxt', `iwmmxt2', 6443 `maverick', `mp' (Multiprocessing Extensions for v7-A and v7-R 6444 architectures), `os' (Operating System for v6M architecture), 6445 `sec' (Security Extensions for v6K and v7-A architectures), `virt' 6446 (Virtualization Extensions for v7-A architecture, implies `idiv'), 6447 and `xscale'. 6448 6449`-march=ARCHITECTURE[+EXTENSION...]' 6450 This option specifies the target architecture. The assembler will 6451 issue an error message if an attempt is made to assemble an 6452 instruction which will not execute on the target architecture. 6453 The following architecture names are recognized: `armv1', `armv2', 6454 `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm', 6455 `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te', 6456 `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk', 6457 `armv6-m', `armv6s-m', `armv7', `armv7-a', `armv7-r', `armv7-m', 6458 `armv7e-m', `iwmmxt' and `xscale'. If both `-mcpu' and `-march' 6459 are specified, the assembler will use the setting for `-mcpu'. 6460 6461 The architecture option can be extended with the same instruction 6462 set extension options as the `-mcpu' option. 6463 6464`-mfpu=FLOATING-POINT-FORMAT' 6465 This option specifies the floating point format to assemble for. 6466 The assembler will issue an error message if an attempt is made to 6467 assemble an instruction which will not execute on the target 6468 floating point unit. The following format options are recognized: 6469 `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11', 6470 `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0', 6471 `vfp9', `vfpxd', `vfpv2', `vfpv3', `vfpv3-fp16', `vfpv3-d16', 6472 `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-d16', `vfpv4', `vfpv4-d16', 6473 `fpv4-sp-d16', `arm1020t', `arm1020e', `arm1136jf-s', `maverick', 6474 `neon', and `neon-vfpv4'. 6475 6476 In addition to determining which instructions are assembled, this 6477 option also affects the way in which the `.double' assembler 6478 directive behaves when assembling little-endian code. 6479 6480 The default is dependent on the processor selected. For 6481 Architecture 5 or later, the default is to assembler for VFP 6482 instructions; for earlier architectures the default is to assemble 6483 for FPA instructions. 6484 6485`-mthumb' 6486 This option specifies that the assembler should start assembling 6487 Thumb instructions; that is, it should behave as though the file 6488 starts with a `.code 16' directive. 6489 6490`-mthumb-interwork' 6491 This option specifies that the output generated by the assembler 6492 should be marked as supporting interworking. 6493 6494`-mimplicit-it=never' 6495`-mimplicit-it=always' 6496`-mimplicit-it=arm' 6497`-mimplicit-it=thumb' 6498 The `-mimplicit-it' option controls the behavior of the assembler 6499 when conditional instructions are not enclosed in IT blocks. 6500 There are four possible behaviors. If `never' is specified, such 6501 constructs cause a warning in ARM code and an error in Thumb-2 6502 code. If `always' is specified, such constructs are accepted in 6503 both ARM and Thumb-2 code, where the IT instruction is added 6504 implicitly. If `arm' is specified, such constructs are accepted 6505 in ARM code and cause an error in Thumb-2 code. If `thumb' is 6506 specified, such constructs cause a warning in ARM code and are 6507 accepted in Thumb-2 code. If you omit this option, the behavior 6508 is equivalent to `-mimplicit-it=arm'. 6509 6510`-mapcs-26' 6511`-mapcs-32' 6512 These options specify that the output generated by the assembler 6513 should be marked as supporting the indicated version of the Arm 6514 Procedure. Calling Standard. 6515 6516`-matpcs' 6517 This option specifies that the output generated by the assembler 6518 should be marked as supporting the Arm/Thumb Procedure Calling 6519 Standard. If enabled this option will cause the assembler to 6520 create an empty debugging section in the object file called 6521 .arm.atpcs. Debuggers can use this to determine the ABI being 6522 used by. 6523 6524`-mapcs-float' 6525 This indicates the floating point variant of the APCS should be 6526 used. In this variant floating point arguments are passed in FP 6527 registers rather than integer registers. 6528 6529`-mapcs-reentrant' 6530 This indicates that the reentrant variant of the APCS should be 6531 used. This variant supports position independent code. 6532 6533`-mfloat-abi=ABI' 6534 This option specifies that the output generated by the assembler 6535 should be marked as using specified floating point ABI. The 6536 following values are recognized: `soft', `softfp' and `hard'. 6537 6538`-meabi=VER' 6539 This option specifies which EABI version the produced object files 6540 should conform to. The following values are recognized: `gnu', `4' 6541 and `5'. 6542 6543`-EB' 6544 This option specifies that the output generated by the assembler 6545 should be marked as being encoded for a big-endian processor. 6546 6547`-EL' 6548 This option specifies that the output generated by the assembler 6549 should be marked as being encoded for a little-endian processor. 6550 6551`-k' 6552 This option specifies that the output of the assembler should be 6553 marked as position-independent code (PIC). 6554 6555`--fix-v4bx' 6556 Allow `BX' instructions in ARMv4 code. This is intended for use 6557 with the linker option of the same name. 6558 6559`-mwarn-deprecated' 6560`-mno-warn-deprecated' 6561 Enable or disable warnings about using deprecated options or 6562 features. The default is to warn. 6563 6564 6565 6566File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 6567 65689.3.2 Syntax 6569------------ 6570 6571* Menu: 6572 6573* ARM-Instruction-Set:: Instruction Set 6574* ARM-Chars:: Special Characters 6575* ARM-Regs:: Register Names 6576* ARM-Relocations:: Relocations 6577* ARM-Neon-Alignment:: NEON Alignment Specifiers 6578 6579 6580File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 6581 65829.3.2.1 Instruction Set Syntax 6583.............................. 6584 6585Two slightly different syntaxes are support for ARM and THUMB 6586instructions. The default, `divided', uses the old style where ARM and 6587THUMB instructions had their own, separate syntaxes. The new, 6588`unified' syntax, which can be selected via the `.syntax' directive, 6589and has the following main features: 6590 6591* 6592 Immediate operands do not require a `#' prefix. 6593 6594* 6595 The `IT' instruction may appear, and if it does it is validated 6596 against subsequent conditional affixes. In ARM mode it does not 6597 generate machine code, in THUMB mode it does. 6598 6599* 6600 For ARM instructions the conditional affixes always appear at the 6601 end of the instruction. For THUMB instructions conditional 6602 affixes can be used, but only inside the scope of an `IT' 6603 instruction. 6604 6605* 6606 All of the instructions new to the V6T2 architecture (and later) 6607 are available. (Only a few such instructions can be written in the 6608 `divided' syntax). 6609 6610* 6611 The `.N' and `.W' suffixes are recognized and honored. 6612 6613* 6614 All instructions set the flags if and only if they have an `s' 6615 affix. 6616 6617 6618File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 6619 66209.3.2.2 Special Characters 6621.......................... 6622 6623The presence of a `@' on a line indicates the start of a comment that 6624extends to the end of the current line. If a `#' appears as the first 6625character of a line, the whole line is treated as a comment. 6626 6627 The `;' character can be used instead of a newline to separate 6628statements. 6629 6630 Either `#' or `$' can be used to indicate immediate operands. 6631 6632 *TODO* Explain about /data modifier on symbols. 6633 6634 6635File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 6636 66379.3.2.3 Register Names 6638...................... 6639 6640*TODO* Explain about ARM register naming, and the predefined names. 6641 6642 6643File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 6644 66459.3.2.4 NEON Alignment Specifiers 6646................................. 6647 6648Some NEON load/store instructions allow an optional address alignment 6649qualifier. The ARM documentation specifies that this is indicated by 6650`@ ALIGN'. However GAS already interprets the `@' character as a "line 6651comment" start, so `: ALIGN' is used instead. For example: 6652 6653 vld1.8 {q0}, [r0, :128] 6654 6655 6656File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 6657 66589.3.3 Floating Point 6659-------------------- 6660 6661The ARM family uses IEEE floating-point numbers. 6662 6663 6664File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 6665 66669.3.3.1 ARM relocation generation 6667................................. 6668 6669Specific data relocations can be generated by putting the relocation 6670name in parentheses after the symbol name. For example: 6671 6672 .word foo(TARGET1) 6673 6674 This will generate an `R_ARM_TARGET1' relocation against the symbol 6675FOO. The following relocations are supported: `GOT', `GOTOFF', 6676`TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `GOTTPOFF', 6677`GOT_PREL' and `TPOFF'. 6678 6679 For compatibility with older toolchains the assembler also accepts 6680`(PLT)' after branch targets. This will generate the deprecated 6681`R_ARM_PLT32' relocation. 6682 6683 Relocations for `MOVW' and `MOVT' instructions can be generated by 6684prefixing the value with `#:lower16:' and `#:upper16' respectively. 6685For example to load the 32-bit address of foo into r0: 6686 6687 MOVW r0, #:lower16:foo 6688 MOVT r0, #:upper16:foo 6689 6690 6691File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 6692 66939.3.4 ARM Machine Directives 6694---------------------------- 6695 6696`.2byte EXPRESSION [, EXPRESSION]*' 6697`.4byte EXPRESSION [, EXPRESSION]*' 6698`.8byte EXPRESSION [, EXPRESSION]*' 6699 These directives write 2, 4 or 8 byte values to the output section. 6700 6701`.align EXPRESSION [, EXPRESSION]' 6702 This is the generic .ALIGN directive. For the ARM however if the 6703 first argument is zero (ie no alignment is needed) the assembler 6704 will behave as if the argument had been 2 (ie pad to the next four 6705 byte boundary). This is for compatibility with ARM's own 6706 assembler. 6707 6708`.arch NAME' 6709 Select the target architecture. Valid values for NAME are the 6710 same as for the `-march' commandline option. 6711 6712 Specifying `.arch' clears any previously selected architecture 6713 extensions. 6714 6715`.arch_extension NAME' 6716 Add or remove an architecture extension to the target 6717 architecture. Valid values for NAME are the same as those 6718 accepted as architectural extensions by the `-mcpu' commandline 6719 option. 6720 6721 `.arch_extension' may be used multiple times to add or remove 6722 extensions incrementally to the architecture being compiled for. 6723 6724`.arm' 6725 This performs the same action as .CODE 32. 6726 6727`.pad #COUNT' 6728 Generate unwinder annotations for a stack adjustment of COUNT 6729 bytes. A positive value indicates the function prologue allocated 6730 stack space by decrementing the stack pointer. 6731 6732`.bss' 6733 This directive switches to the `.bss' section. 6734 6735`.cantunwind' 6736 Prevents unwinding through the current function. No personality 6737 routine or exception table data is required or permitted. 6738 6739`.code `[16|32]'' 6740 This directive selects the instruction set being generated. The 6741 value 16 selects Thumb, with the value 32 selecting ARM. 6742 6743`.cpu NAME' 6744 Select the target processor. Valid values for NAME are the same as 6745 for the `-mcpu' commandline option. 6746 6747 Specifying `.cpu' clears any previously selected architecture 6748 extensions. 6749 6750`NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' 6751`NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' 6752 The `dn' and `qn' directives are used to create typed and/or 6753 indexed register aliases for use in Advanced SIMD Extension (Neon) 6754 instructions. The former should be used to create aliases of 6755 double-precision registers, and the latter to create aliases of 6756 quad-precision registers. 6757 6758 If these directives are used to create typed aliases, those 6759 aliases can be used in Neon instructions instead of writing types 6760 after the mnemonic or after each operand. For example: 6761 6762 x .dn d2.f32 6763 y .dn d3.f32 6764 z .dn d4.f32[1] 6765 vmul x,y,z 6766 6767 This is equivalent to writing the following: 6768 6769 vmul.f32 d2,d3,d4[1] 6770 6771 Aliases created using `dn' or `qn' can be destroyed using `unreq'. 6772 6773`.eabi_attribute TAG, VALUE' 6774 Set the EABI object attribute TAG to VALUE. 6775 6776 The TAG is either an attribute number, or one of the following: 6777 `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch', 6778 `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use', 6779 `Tag_FP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch', 6780 `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data', 6781 `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use', 6782 `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding', 6783 `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions', 6784 `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model', 6785 `Tag_ABI_align_needed', `Tag_ABI_align_preserved', 6786 `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args', 6787 `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals', 6788 `Tag_ABI_FP_optimization_goals', `Tag_compatibility', 6789 `Tag_CPU_unaligned_access', `Tag_FP_HP_extension', 6790 `Tag_ABI_FP_16bit_format', `Tag_MPextension_use', `Tag_DIV_use', 6791 `Tag_nodefaults', `Tag_also_compatible_with', `Tag_conformance', 6792 `Tag_T2EE_use', `Tag_Virtualization_use' 6793 6794 The VALUE is either a `number', `"string"', or `number, "string"' 6795 depending on the tag. 6796 6797 Note - the following legacy values are also accepted by TAG: 6798 `Tag_VFP_arch', `Tag_ABI_align8_needed', 6799 `Tag_ABI_align8_preserved', `Tag_VFP_HP_extension', 6800 6801`.even' 6802 This directive aligns to an even-numbered address. 6803 6804`.extend EXPRESSION [, EXPRESSION]*' 6805`.ldouble EXPRESSION [, EXPRESSION]*' 6806 These directives write 12byte long double floating-point values to 6807 the output section. These are not compatible with current ARM 6808 processors or ABIs. 6809 6810`.fnend' 6811 Marks the end of a function with an unwind table entry. The 6812 unwind index table entry is created when this directive is 6813 processed. 6814 6815 If no personality routine has been specified then standard 6816 personality routine 0 or 1 will be used, depending on the number 6817 of unwind opcodes required. 6818 6819`.fnstart' 6820 Marks the start of a function with an unwind table entry. 6821 6822`.force_thumb' 6823 This directive forces the selection of Thumb instructions, even if 6824 the target processor does not support those instructions 6825 6826`.fpu NAME' 6827 Select the floating-point unit to assemble for. Valid values for 6828 NAME are the same as for the `-mfpu' commandline option. 6829 6830`.handlerdata' 6831 Marks the end of the current function, and the start of the 6832 exception table entry for that function. Anything between this 6833 directive and the `.fnend' directive will be added to the 6834 exception table entry. 6835 6836 Must be preceded by a `.personality' or `.personalityindex' 6837 directive. 6838 6839`.inst OPCODE [ , ... ]' 6840`.inst.n OPCODE [ , ... ]' 6841`.inst.w OPCODE [ , ... ]' 6842 Generates the instruction corresponding to the numerical value 6843 OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size 6844 to be specified explicitly, overriding the normal encoding rules. 6845 6846`.ldouble EXPRESSION [, EXPRESSION]*' 6847 See `.extend'. 6848 6849`.ltorg' 6850 This directive causes the current contents of the literal pool to 6851 be dumped into the current section (which is assumed to be the 6852 .text section) at the current location (aligned to a word 6853 boundary). `GAS' maintains a separate literal pool for each 6854 section and each sub-section. The `.ltorg' directive will only 6855 affect the literal pool of the current section and sub-section. 6856 At the end of assembly all remaining, un-empty literal pools will 6857 automatically be dumped. 6858 6859 Note - older versions of `GAS' would dump the current literal pool 6860 any time a section change occurred. This is no longer done, since 6861 it prevents accurate control of the placement of literal pools. 6862 6863`.movsp REG [, #OFFSET]' 6864 Tell the unwinder that REG contains an offset from the current 6865 stack pointer. If OFFSET is not specified then it is assumed to be 6866 zero. 6867 6868`.object_arch NAME' 6869 Override the architecture recorded in the EABI object attribute 6870 section. Valid values for NAME are the same as for the `.arch' 6871 directive. Typically this is useful when code uses runtime 6872 detection of CPU features. 6873 6874`.packed EXPRESSION [, EXPRESSION]*' 6875 This directive writes 12-byte packed floating-point values to the 6876 output section. These are not compatible with current ARM 6877 processors or ABIs. 6878 6879`.pad #COUNT' 6880 Generate unwinder annotations for a stack adjustment of COUNT 6881 bytes. A positive value indicates the function prologue allocated 6882 stack space by decrementing the stack pointer. 6883 6884`.personality NAME' 6885 Sets the personality routine for the current function to NAME. 6886 6887`.personalityindex INDEX' 6888 Sets the personality routine for the current function to the EABI 6889 standard routine number INDEX 6890 6891`.pool' 6892 This is a synonym for .ltorg. 6893 6894`NAME .req REGISTER NAME' 6895 This creates an alias for REGISTER NAME called NAME. For example: 6896 6897 foo .req r0 6898 6899`.save REGLIST' 6900 Generate unwinder annotations to restore the registers in REGLIST. 6901 The format of REGLIST is the same as the corresponding 6902 store-multiple instruction. 6903 6904 _core registers_ 6905 .save {r4, r5, r6, lr} 6906 stmfd sp!, {r4, r5, r6, lr} 6907 _FPA registers_ 6908 .save f4, 2 6909 sfmfd f4, 2, [sp]! 6910 _VFP registers_ 6911 .save {d8, d9, d10} 6912 fstmdx sp!, {d8, d9, d10} 6913 _iWMMXt registers_ 6914 .save {wr10, wr11} 6915 wstrd wr11, [sp, #-8]! 6916 wstrd wr10, [sp, #-8]! 6917 or 6918 .save wr11 6919 wstrd wr11, [sp, #-8]! 6920 .save wr10 6921 wstrd wr10, [sp, #-8]! 6922 6923`.setfp FPREG, SPREG [, #OFFSET]' 6924 Make all unwinder annotations relative to a frame pointer. 6925 Without this the unwinder will use offsets from the stack pointer. 6926 6927 The syntax of this directive is the same as the `add' or `mov' 6928 instruction used to set the frame pointer. SPREG must be either 6929 `sp' or mentioned in a previous `.movsp' directive. 6930 6931 .movsp ip 6932 mov ip, sp 6933 ... 6934 .setfp fp, ip, #4 6935 add fp, ip, #4 6936 6937`.secrel32 EXPRESSION [, EXPRESSION]*' 6938 This directive emits relocations that evaluate to the 6939 section-relative offset of each expression's symbol. This 6940 directive is only supported for PE targets. 6941 6942`.syntax [`unified' | `divided']' 6943 This directive sets the Instruction Set Syntax as described in the 6944 *Note ARM-Instruction-Set:: section. 6945 6946`.thumb' 6947 This performs the same action as .CODE 16. 6948 6949`.thumb_func' 6950 This directive specifies that the following symbol is the name of a 6951 Thumb encoded function. This information is necessary in order to 6952 allow the assembler and linker to generate correct code for 6953 interworking between Arm and Thumb instructions and should be used 6954 even if interworking is not going to be performed. The presence 6955 of this directive also implies `.thumb' 6956 6957 This directive is not neccessary when generating EABI objects. On 6958 these targets the encoding is implicit when generating Thumb code. 6959 6960`.thumb_set' 6961 This performs the equivalent of a `.set' directive in that it 6962 creates a symbol which is an alias for another symbol (possibly 6963 not yet defined). This directive also has the added property in 6964 that it marks the aliased symbol as being a thumb function entry 6965 point, in the same way that the `.thumb_func' directive does. 6966 6967`.unreq ALIAS-NAME' 6968 This undefines a register alias which was previously defined using 6969 the `req', `dn' or `qn' directives. For example: 6970 6971 foo .req r0 6972 .unreq foo 6973 6974 An error occurs if the name is undefined. Note - this pseudo op 6975 can be used to delete builtin in register name aliases (eg 'r0'). 6976 This should only be done if it is really necessary. 6977 6978`.unwind_raw OFFSET, BYTE1, ...' 6979 Insert one of more arbitary unwind opcode bytes, which are known 6980 to adjust the stack pointer by OFFSET bytes. 6981 6982 For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save 6983 {r0}' 6984 6985`.vsave VFP-REGLIST' 6986 Generate unwinder annotations to restore the VFP registers in 6987 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are 6988 to be restored using VLDM. The format of VFP-REGLIST is the same 6989 as the corresponding store-multiple instruction. 6990 6991 _VFP registers_ 6992 .vsave {d8, d9, d10} 6993 fstmdd sp!, {d8, d9, d10} 6994 _VFPv3 registers_ 6995 .vsave {d15, d16, d17} 6996 vstm sp!, {d15, d16, d17} 6997 6998 Since FLDMX and FSTMX are now deprecated, this directive should be 6999 used in favour of `.save' for saving VFP registers for ARMv6 and 7000 above. 7001 7002 7003 7004File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 7005 70069.3.5 Opcodes 7007------------- 7008 7009`as' implements all the standard ARM opcodes. It also implements 7010several pseudo opcodes, including several synthetic load instructions. 7011 7012`NOP' 7013 nop 7014 7015 This pseudo op will always evaluate to a legal ARM instruction 7016 that does nothing. Currently it will evaluate to MOV r0, r0. 7017 7018`LDR' 7019 ldr <register> , = <expression> 7020 7021 If expression evaluates to a numeric constant then a MOV or MVN 7022 instruction will be used in place of the LDR instruction, if the 7023 constant can be generated by either of these instructions. 7024 Otherwise the constant will be placed into the nearest literal 7025 pool (if it not already there) and a PC relative LDR instruction 7026 will be generated. 7027 7028`ADR' 7029 adr <register> <label> 7030 7031 This instruction will load the address of LABEL into the indicated 7032 register. The instruction will evaluate to a PC relative ADD or 7033 SUB instruction depending upon where the label is located. If the 7034 label is out of range, or if it is not defined in the same file 7035 (and section) as the ADR instruction, then an error will be 7036 generated. This instruction will not make use of the literal pool. 7037 7038`ADRL' 7039 adrl <register> <label> 7040 7041 This instruction will load the address of LABEL into the indicated 7042 register. The instruction will evaluate to one or two PC relative 7043 ADD or SUB instructions depending upon where the label is located. 7044 If a second instruction is not needed a NOP instruction will be 7045 generated in its place, so that this instruction is always 8 bytes 7046 long. 7047 7048 If the label is out of range, or if it is not defined in the same 7049 file (and section) as the ADRL instruction, then an error will be 7050 generated. This instruction will not make use of the literal pool. 7051 7052 7053 For information on the ARM or Thumb instruction sets, see `ARM 7054Software Development Toolkit Reference Manual', Advanced RISC Machines 7055Ltd. 7056 7057 7058File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 7059 70609.3.6 Mapping Symbols 7061--------------------- 7062 7063The ARM ELF specification requires that special symbols be inserted 7064into object files to mark certain features: 7065 7066`$a' 7067 At the start of a region of code containing ARM instructions. 7068 7069`$t' 7070 At the start of a region of code containing THUMB instructions. 7071 7072`$d' 7073 At the start of a region of data. 7074 7075 7076 The assembler will automatically insert these symbols for you - there 7077is no need to code them yourself. Support for tagging symbols ($b, $f, 7078$p and $m) which is also mentioned in the current ARM ELF specification 7079is not implemented. This is because they have been dropped from the 7080new EABI and so tools cannot rely upon their presence. 7081 7082 7083File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 7084 70859.3.7 Unwinding 7086--------------- 7087 7088The ABI for the ARM Architecture specifies a standard format for 7089exception unwind information. This information is used when an 7090exception is thrown to determine where control should be transferred. 7091In particular, the unwind information is used to determine which 7092function called the function that threw the exception, and which 7093function called that one, and so forth. This information is also used 7094to restore the values of callee-saved registers in the function 7095catching the exception. 7096 7097 If you are writing functions in assembly code, and those functions 7098call other functions that throw exceptions, you must use assembly 7099pseudo ops to ensure that appropriate exception unwind information is 7100generated. Otherwise, if one of the functions called by your assembly 7101code throws an exception, the run-time library will be unable to unwind 7102the stack through your assembly code and your program will not behave 7103correctly. 7104 7105 To illustrate the use of these pseudo ops, we will examine the code 7106that G++ generates for the following C++ input: 7107 7108 7109void callee (int *); 7110 7111int 7112caller () 7113{ 7114 int i; 7115 callee (&i); 7116 return i; 7117} 7118 7119 This example does not show how to throw or catch an exception from 7120assembly code. That is a much more complex operation and should always 7121be done in a high-level language, such as C++, that directly supports 7122exceptions. 7123 7124 The code generated by one particular version of G++ when compiling 7125the example above is: 7126 7127 7128_Z6callerv: 7129 .fnstart 7130.LFB2: 7131 @ Function supports interworking. 7132 @ args = 0, pretend = 0, frame = 8 7133 @ frame_needed = 1, uses_anonymous_args = 0 7134 stmfd sp!, {fp, lr} 7135 .save {fp, lr} 7136.LCFI0: 7137 .setfp fp, sp, #4 7138 add fp, sp, #4 7139.LCFI1: 7140 .pad #8 7141 sub sp, sp, #8 7142.LCFI2: 7143 sub r3, fp, #8 7144 mov r0, r3 7145 bl _Z6calleePi 7146 ldr r3, [fp, #-8] 7147 mov r0, r3 7148 sub sp, fp, #4 7149 ldmfd sp!, {fp, lr} 7150 bx lr 7151.LFE2: 7152 .fnend 7153 7154 Of course, the sequence of instructions varies based on the options 7155you pass to GCC and on the version of GCC in use. The exact 7156instructions are not important since we are focusing on the pseudo ops 7157that are used to generate unwind information. 7158 7159 An important assumption made by the unwinder is that the stack frame 7160does not change during the body of the function. In particular, since 7161we assume that the assembly code does not itself throw an exception, 7162the only point where an exception can be thrown is from a call, such as 7163the `bl' instruction above. At each call site, the same saved 7164registers (including `lr', which indicates the return address) must be 7165located in the same locations relative to the frame pointer. 7166 7167 The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op 7168appears immediately before the first instruction of the function while 7169the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears 7170immediately after the last instruction of the function. These pseudo 7171ops specify the range of the function. 7172 7173 Only the order of the other pseudos ops (e.g., `.setfp' or `.pad') 7174matters; their exact locations are irrelevant. In the example above, 7175the compiler emits the pseudo ops with particular instructions. That 7176makes it easier to understand the code, but it is not required for 7177correctness. It would work just as well to emit all of the pseudo ops 7178other than `.fnend' in the same order, but immediately after `.fnstart'. 7179 7180 The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates 7181registers that have been saved to the stack so that they can be 7182restored before the function returns. The argument to the `.save' 7183pseudo op is a list of registers to save. If a register is 7184"callee-saved" (as specified by the ABI) and is modified by the 7185function you are writing, then your code must save the value before it 7186is modified and restore the original value before the function returns. 7187If an exception is thrown, the run-time library restores the values of 7188these registers from their locations on the stack before returning 7189control to the exception handler. (Of course, if an exception is not 7190thrown, the function that contains the `.save' pseudo op restores these 7191registers in the function epilogue, as is done with the `ldmfd' 7192instruction above.) 7193 7194 You do not have to save callee-saved registers at the very beginning 7195of the function and you do not need to use the `.save' pseudo op 7196immediately following the point at which the registers are saved. 7197However, if you modify a callee-saved register, you must save it on the 7198stack before modifying it and before calling any functions which might 7199throw an exception. And, you must use the `.save' pseudo op to 7200indicate that you have done so. 7201 7202 The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification 7203of the stack pointer that does not save any registers. The argument is 7204the number of bytes (in decimal) that are subtracted from the stack 7205pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 7206the stack pointer increases the size of the stack.) 7207 7208 The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op 7209indicates the register that contains the frame pointer. The first 7210argument is the register that is set, which is typically `fp'. The 7211second argument indicates the register from which the frame pointer 7212takes its value. The third argument, if present, is the value (in 7213decimal) added to the register specified by the second argument to 7214compute the value of the frame pointer. You should not modify the 7215frame pointer in the body of the function. 7216 7217 If you do not use a frame pointer, then you should not use the 7218`.setfp' pseudo op. If you do not use a frame pointer, then you should 7219avoid modifying the stack pointer outside of the function prologue. 7220Otherwise, the run-time library will be unable to find saved registers 7221when it is unwinding the stack. 7222 7223 The pseudo ops described above are sufficient for writing assembly 7224code that calls functions which may throw exceptions. If you need to 7225know more about the object-file format used to represent unwind 7226information, you may consult the `Exception Handling ABI for the ARM 7227Architecture' available from `http://infocenter.arm.com'. 7228 7229 7230File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 7231 72329.4 AVR Dependent Features 7233========================== 7234 7235* Menu: 7236 7237* AVR Options:: Options 7238* AVR Syntax:: Syntax 7239* AVR Opcodes:: Opcodes 7240 7241 7242File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 7243 72449.4.1 Options 7245------------- 7246 7247`-mmcu=MCU' 7248 Specify ATMEL AVR instruction set or MCU type. 7249 7250 Instruction set avr1 is for the minimal AVR core, not supported by 7251 the C compiler, only for assembler programs (MCU types: at90s1200, 7252 attiny11, attiny12, attiny15, attiny28). 7253 7254 Instruction set avr2 (default) is for the classic AVR core with up 7255 to 8K program memory space (MCU types: at90s2313, at90s2323, 7256 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 7257 at90s4434, at90s8515, at90c8534, at90s8535). 7258 7259 Instruction set avr25 is for the classic AVR core with up to 8K 7260 program memory space plus the MOVW instruction (MCU types: 7261 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 7262 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 7263 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 7264 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 7265 at86rf401, ata6289). 7266 7267 Instruction set avr3 is for the classic AVR core with up to 128K 7268 program memory space (MCU types: at43usb355, at76c711). 7269 7270 Instruction set avr31 is for the classic AVR core with exactly 7271 128K program memory space (MCU types: atmega103, at43usb320). 7272 7273 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 7274 JMP instructions (MCU types: attiny167, at90usb82, at90usb162, 7275 atmega8u2, atmega16u2, atmega32u2). 7276 7277 Instruction set avr4 is for the enhanced AVR core with up to 8K 7278 program memory space (MCU types: atmega48, atmega48a, atmega48p, 7279 atmega8, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, 7280 atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, 7281 at90pwm3b, at90pwm81). 7282 7283 Instruction set avr5 is for the enhanced AVR core with up to 128K 7284 program memory space (MCU types: atmega16, atmega16a, atmega161, 7285 atmega162, atmega163, atmega164a, atmega164p, atmega165, 7286 atmega165a, atmega165p, atmega168, atmega168a, atmega168p, 7287 atmega169, atmega169a, atmega169p, atmega169pa, atmega32, 7288 atmega323, atmega324a, atmega324p, atmega325, atmega325a, 7289 atmega325p, atmega3250, atmega3250a, atmega3250p, atmega328, 7290 atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, 7291 atmega3290, atmega3290a, atmega3290p, atmega406, atmega64, 7292 atmega640, atmega644, atmega644a, atmega644p, atmega644pa, 7293 atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, 7294 atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, 7295 atmega6490a, atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, 7296 atmega32hvb, atmega64hve, at90can32, at90can64, at90pwm216, 7297 at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, 7298 atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, 7299 at90usb647, at94k, at90scr100). 7300 7301 Instruction set avr51 is for the enhanced AVR core with exactly 7302 128K program memory space (MCU types: atmega128, atmega1280, 7303 atmega1281, atmega1284p, atmega128rfa1, at90can128, at90usb1286, 7304 at90usb1287, m3000). 7305 7306 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 7307 (MCU types: atmega2560, atmega2561). 7308 7309`-mall-opcodes' 7310 Accept all AVR opcodes, even if not supported by `-mmcu'. 7311 7312`-mno-skip-bug' 7313 This option disable warnings for skipping two-word instructions. 7314 7315`-mno-wrap' 7316 This option reject `rjmp/rcall' instructions with 8K wrap-around. 7317 7318 7319 7320File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 7321 73229.4.2 Syntax 7323------------ 7324 7325* Menu: 7326 7327* AVR-Chars:: Special Characters 7328* AVR-Regs:: Register Names 7329* AVR-Modifiers:: Relocatable Expression Modifiers 7330 7331 7332File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 7333 73349.4.2.1 Special Characters 7335.......................... 7336 7337The presence of a `;' on a line indicates the start of a comment that 7338extends to the end of the current line. If a `#' appears as the first 7339character of a line, the whole line is treated as a comment. 7340 7341 The `$' character can be used instead of a newline to separate 7342statements. 7343 7344 7345File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 7346 73479.4.2.2 Register Names 7348...................... 7349 7350The AVR has 32 x 8-bit general purpose working registers `r0', `r1', 7351... `r31'. Six of the 32 registers can be used as three 16-bit 7352indirect address register pointers for Data Space addressing. One of 7353the these address pointers can also be used as an address pointer for 7354look up tables in Flash program memory. These added function registers 7355are the 16-bit `X', `Y' and `Z' - registers. 7356 7357 X = r26:r27 7358 Y = r28:r29 7359 Z = r30:r31 7360 7361 7362File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 7363 73649.4.2.3 Relocatable Expression Modifiers 7365........................................ 7366 7367The assembler supports several modifiers when using relocatable 7368addresses in AVR instruction operands. The general syntax is the 7369following: 7370 7371 modifier(relocatable-expression) 7372 7373`lo8' 7374 This modifier allows you to use bits 0 through 7 of an address 7375 expression as 8 bit relocatable expression. 7376 7377`hi8' 7378 This modifier allows you to use bits 7 through 15 of an address 7379 expression as 8 bit relocatable expression. This is useful with, 7380 for example, the AVR `ldi' instruction and `lo8' modifier. 7381 7382 For example 7383 7384 ldi r26, lo8(sym+10) 7385 ldi r27, hi8(sym+10) 7386 7387`hh8' 7388 This modifier allows you to use bits 16 through 23 of an address 7389 expression as 8 bit relocatable expression. Also, can be useful 7390 for loading 32 bit constants. 7391 7392`hlo8' 7393 Synonym of `hh8'. 7394 7395`hhi8' 7396 This modifier allows you to use bits 24 through 31 of an 7397 expression as 8 bit expression. This is useful with, for example, 7398 the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8', 7399 modifier. 7400 7401 For example 7402 7403 ldi r26, lo8(285774925) 7404 ldi r27, hi8(285774925) 7405 ldi r28, hlo8(285774925) 7406 ldi r29, hhi8(285774925) 7407 ; r29,r28,r27,r26 = 285774925 7408 7409`pm_lo8' 7410 This modifier allows you to use bits 0 through 7 of an address 7411 expression as 8 bit relocatable expression. This modifier useful 7412 for addressing data or code from Flash/Program memory. The using 7413 of `pm_lo8' similar to `lo8'. 7414 7415`pm_hi8' 7416 This modifier allows you to use bits 8 through 15 of an address 7417 expression as 8 bit relocatable expression. This modifier useful 7418 for addressing data or code from Flash/Program memory. 7419 7420`pm_hh8' 7421 This modifier allows you to use bits 15 through 23 of an address 7422 expression as 8 bit relocatable expression. This modifier useful 7423 for addressing data or code from Flash/Program memory. 7424 7425 7426 7427File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent 7428 74299.4.3 Opcodes 7430------------- 7431 7432For detailed information on the AVR machine instruction set, see 7433`www.atmel.com/products/AVR'. 7434 7435 `as' implements all the standard AVR opcodes. The following table 7436summarizes the AVR opcodes, and their arguments. 7437 7438 Legend: 7439 r any register 7440 d `ldi' register (r16-r31) 7441 v `movw' even register (r0, r2, ..., r28, r30) 7442 a `fmul' register (r16-r23) 7443 w `adiw' register (r24,r26,r28,r30) 7444 e pointer registers (X,Y,Z) 7445 b base pointer register and displacement ([YZ]+disp) 7446 z Z pointer register (for [e]lpm Rd,Z[+]) 7447 M immediate value from 0 to 255 7448 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 7449 s immediate value from 0 to 7 7450 P Port address value from 0 to 63. (in, out) 7451 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 7452 K immediate value from 0 to 63 (used in `adiw', `sbiw') 7453 i immediate value 7454 l signed pc relative offset from -64 to 63 7455 L signed pc relative offset from -2048 to 2047 7456 h absolute code address (call, jmp) 7457 S immediate value from 0 to 7 (S = s << 4) 7458 ? use this opcode entry if no parameters, else use next opcode entry 7459 7460 1001010010001000 clc 7461 1001010011011000 clh 7462 1001010011111000 cli 7463 1001010010101000 cln 7464 1001010011001000 cls 7465 1001010011101000 clt 7466 1001010010111000 clv 7467 1001010010011000 clz 7468 1001010000001000 sec 7469 1001010001011000 seh 7470 1001010001111000 sei 7471 1001010000101000 sen 7472 1001010001001000 ses 7473 1001010001101000 set 7474 1001010000111000 sev 7475 1001010000011000 sez 7476 100101001SSS1000 bclr S 7477 100101000SSS1000 bset S 7478 1001010100001001 icall 7479 1001010000001001 ijmp 7480 1001010111001000 lpm ? 7481 1001000ddddd010+ lpm r,z 7482 1001010111011000 elpm ? 7483 1001000ddddd011+ elpm r,z 7484 0000000000000000 nop 7485 1001010100001000 ret 7486 1001010100011000 reti 7487 1001010110001000 sleep 7488 1001010110011000 break 7489 1001010110101000 wdr 7490 1001010111101000 spm 7491 000111rdddddrrrr adc r,r 7492 000011rdddddrrrr add r,r 7493 001000rdddddrrrr and r,r 7494 000101rdddddrrrr cp r,r 7495 000001rdddddrrrr cpc r,r 7496 000100rdddddrrrr cpse r,r 7497 001001rdddddrrrr eor r,r 7498 001011rdddddrrrr mov r,r 7499 100111rdddddrrrr mul r,r 7500 001010rdddddrrrr or r,r 7501 000010rdddddrrrr sbc r,r 7502 000110rdddddrrrr sub r,r 7503 001001rdddddrrrr clr r 7504 000011rdddddrrrr lsl r 7505 000111rdddddrrrr rol r 7506 001000rdddddrrrr tst r 7507 0111KKKKddddKKKK andi d,M 7508 0111KKKKddddKKKK cbr d,n 7509 1110KKKKddddKKKK ldi d,M 7510 11101111dddd1111 ser d 7511 0110KKKKddddKKKK ori d,M 7512 0110KKKKddddKKKK sbr d,M 7513 0011KKKKddddKKKK cpi d,M 7514 0100KKKKddddKKKK sbci d,M 7515 0101KKKKddddKKKK subi d,M 7516 1111110rrrrr0sss sbrc r,s 7517 1111111rrrrr0sss sbrs r,s 7518 1111100ddddd0sss bld r,s 7519 1111101ddddd0sss bst r,s 7520 10110PPdddddPPPP in r,P 7521 10111PPrrrrrPPPP out P,r 7522 10010110KKddKKKK adiw w,K 7523 10010111KKddKKKK sbiw w,K 7524 10011000pppppsss cbi p,s 7525 10011010pppppsss sbi p,s 7526 10011001pppppsss sbic p,s 7527 10011011pppppsss sbis p,s 7528 111101lllllll000 brcc l 7529 111100lllllll000 brcs l 7530 111100lllllll001 breq l 7531 111101lllllll100 brge l 7532 111101lllllll101 brhc l 7533 111100lllllll101 brhs l 7534 111101lllllll111 brid l 7535 111100lllllll111 brie l 7536 111100lllllll000 brlo l 7537 111100lllllll100 brlt l 7538 111100lllllll010 brmi l 7539 111101lllllll001 brne l 7540 111101lllllll010 brpl l 7541 111101lllllll000 brsh l 7542 111101lllllll110 brtc l 7543 111100lllllll110 brts l 7544 111101lllllll011 brvc l 7545 111100lllllll011 brvs l 7546 111101lllllllsss brbc s,l 7547 111100lllllllsss brbs s,l 7548 1101LLLLLLLLLLLL rcall L 7549 1100LLLLLLLLLLLL rjmp L 7550 1001010hhhhh111h call h 7551 1001010hhhhh110h jmp h 7552 1001010rrrrr0101 asr r 7553 1001010rrrrr0000 com r 7554 1001010rrrrr1010 dec r 7555 1001010rrrrr0011 inc r 7556 1001010rrrrr0110 lsr r 7557 1001010rrrrr0001 neg r 7558 1001000rrrrr1111 pop r 7559 1001001rrrrr1111 push r 7560 1001010rrrrr0111 ror r 7561 1001010rrrrr0010 swap r 7562 00000001ddddrrrr movw v,v 7563 00000010ddddrrrr muls d,d 7564 000000110ddd0rrr mulsu a,a 7565 000000110ddd1rrr fmul a,a 7566 000000111ddd0rrr fmuls a,a 7567 000000111ddd1rrr fmulsu a,a 7568 1001001ddddd0000 sts i,r 7569 1001000ddddd0000 lds r,i 7570 10o0oo0dddddbooo ldd r,b 7571 100!000dddddee-+ ld r,e 7572 10o0oo1rrrrrbooo std b,r 7573 100!001rrrrree-+ st e,r 7574 1001010100011001 eicall 7575 1001010000011001 eijmp 7576 7577 7578File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 7579 75809.5 Blackfin Dependent Features 7581=============================== 7582 7583* Menu: 7584 7585* Blackfin Options:: Blackfin Options 7586* Blackfin Syntax:: Blackfin Syntax 7587* Blackfin Directives:: Blackfin Directives 7588 7589 7590File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 7591 75929.5.1 Options 7593------------- 7594 7595`-mcpu=PROCESSOR[-SIREVISION]' 7596 This option specifies the target processor. The optional 7597 SIREVISION is not used in assembler. It's here such that GCC can 7598 easily pass down its `-mcpu=' option. The assembler will issue an 7599 error message if an attempt is made to assemble an instruction 7600 which will not execute on the target processor. The following 7601 processor names are recognized: `bf504', `bf506', `bf512', `bf514', 7602 `bf516', `bf518', `bf522', `bf523', `bf524', `bf525', `bf526', 7603 `bf527', `bf531', `bf532', `bf533', `bf534', `bf535' (not 7604 implemented yet), `bf536', `bf537', `bf538', `bf539', `bf542', 7605 `bf542m', `bf544', `bf544m', `bf547', `bf547m', `bf548', `bf548m', 7606 `bf549', `bf549m', `bf561', and `bf592'. 7607 7608`-mfdpic' 7609 Assemble for the FDPIC ABI. 7610 7611`-mno-fdpic' 7612`-mnopic' 7613 Disable -mfdpic. 7614 7615 7616File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 7617 76189.5.2 Syntax 7619------------ 7620 7621`Special Characters' 7622 Assembler input is free format and may appear anywhere on the line. 7623 One instruction may extend across multiple lines or more than one 7624 instruction may appear on the same line. White space (space, tab, 7625 comments or newline) may appear anywhere between tokens. A token 7626 must not have embedded spaces. Tokens include numbers, register 7627 names, keywords, user identifiers, and also some multicharacter 7628 special symbols like "+=", "/*" or "||". 7629 7630`Instruction Delimiting' 7631 A semicolon must terminate every instruction. Sometimes a complete 7632 instruction will consist of more than one operation. There are two 7633 cases where this occurs. The first is when two general operations 7634 are combined. Normally a comma separates the different parts, as 7635 in 7636 7637 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 7638 7639 The second case occurs when a general instruction is combined with 7640 one or two memory references for joint issue. The latter portions 7641 are set off by a "||" token. 7642 7643 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 7644 7645`Register Names' 7646 The assembler treats register names and instruction keywords in a 7647 case insensitive manner. User identifiers are case sensitive. 7648 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 7649 assembler. 7650 7651 Register names are reserved and may not be used as program 7652 identifiers. 7653 7654 Some operations (such as "Move Register") require a register pair. 7655 Register pairs are always data registers and are denoted using a 7656 colon, eg., R3:2. The larger number must be written firsts. Note 7657 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 7658 R3:2, and R1:0. 7659 7660 Some instructions (such as -SP (Push Multiple)) require a group of 7661 adjacent registers. Adjacent registers are denoted in the syntax 7662 by the range enclosed in parentheses and separated by a colon, 7663 eg., (R7:3). Again, the larger number appears first. 7664 7665 Portions of a particular register may be individually specified. 7666 This is written with a dot (".") following the register name and 7667 then a letter denoting the desired portion. For 32-bit registers, 7668 ".H" denotes the most significant ("High") portion. ".L" denotes 7669 the least-significant portion. The subdivisions of the 40-bit 7670 registers are described later. 7671 7672`Accumulators' 7673 The set of 40-bit registers A1 and A0 that normally contain data 7674 that is being manipulated. Each accumulator can be accessed in 7675 four ways. 7676 7677 `one 40-bit register' 7678 The register will be referred to as A1 or A0. 7679 7680 `one 32-bit register' 7681 The registers are designated as A1.W or A0.W. 7682 7683 `two 16-bit registers' 7684 The registers are designated as A1.H, A1.L, A0.H or A0.L. 7685 7686 `one 8-bit register' 7687 The registers are designated as A1.X or A0.X for the bits that 7688 extend beyond bit 31. 7689 7690`Data Registers' 7691 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 7692 that normally contain data for manipulation. These are 7693 abbreviated as D-register or Dreg. Data registers can be accessed 7694 as 32-bit registers or as two independent 16-bit registers. The 7695 least significant 16 bits of each register is called the "low" 7696 half and is designated with ".L" following the register name. The 7697 most significant 16 bits are called the "high" half and is 7698 designated with ".H" following the name. 7699 7700 R7.L, r2.h, r4.L, R0.H 7701 7702`Pointer Registers' 7703 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 7704 that normally contain byte addresses of data structures. These are 7705 abbreviated as P-register or Preg. 7706 7707 p2, p5, fp, sp 7708 7709`Stack Pointer SP' 7710 The stack pointer contains the 32-bit address of the last occupied 7711 byte location in the stack. The stack grows by decrementing the 7712 stack pointer. 7713 7714`Frame Pointer FP' 7715 The frame pointer contains the 32-bit address of the previous frame 7716 pointer in the stack. It is located at the top of a frame. 7717 7718`Loop Top' 7719 LT0 and LT1. These registers contain the 32-bit address of the 7720 top of a zero overhead loop. 7721 7722`Loop Count' 7723 LC0 and LC1. These registers contain the 32-bit counter of the 7724 zero overhead loop executions. 7725 7726`Loop Bottom' 7727 LB0 and LB1. These registers contain the 32-bit address of the 7728 bottom of a zero overhead loop. 7729 7730`Index Registers' 7731 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 7732 byte addresses of data structures. Abbreviated I-register or Ireg. 7733 7734`Modify Registers' 7735 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 7736 offset values that are added and subracted to one of the index 7737 registers. Abbreviated as Mreg. 7738 7739`Length Registers' 7740 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 7741 the length in bytes of the circular buffer. Abbreviated as Lreg. 7742 Clear the Lreg to disable circular addressing for the 7743 corresponding Ireg. 7744 7745`Base Registers' 7746 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 7747 the base address in bytes of the circular buffer. Abbreviated as 7748 Breg. 7749 7750`Floating Point' 7751 The Blackfin family has no hardware floating point but the .float 7752 directive generates ieee floating point numbers for use with 7753 software floating point libraries. 7754 7755`Blackfin Opcodes' 7756 For detailed information on the Blackfin machine instruction set, 7757 see the Blackfin(r) Processor Instruction Set Reference. 7758 7759 7760 7761File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 7762 77639.5.3 Directives 7764---------------- 7765 7766The following directives are provided for compatibility with the VDSP 7767assembler. 7768 7769`.byte2' 7770 Initializes a four byte data object. 7771 7772`.byte4' 7773 Initializes a two byte data object. 7774 7775`.db' 7776 TBD 7777 7778`.dd' 7779 TBD 7780 7781`.dw' 7782 TBD 7783 7784`.var' 7785 Define and initialize a 32 bit data object. 7786 7787 7788File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 7789 77909.6 CR16 Dependent Features 7791=========================== 7792 7793* Menu: 7794 7795* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 7796 7797 7798File: as.info, Node: CR16 Operand Qualifiers, Up: CR16-Dependent 7799 78009.6.1 CR16 Operand Qualifiers 7801----------------------------- 7802 7803The National Semiconductor CR16 target of `as' has a few machine 7804dependent operand qualifiers. 7805 7806 Operand expression type qualifier is an optional field in the 7807instruction operand, to determines the type of the expression field of 7808an operand. The `@' is required. CR16 architecture uses one of the 7809following expression qualifiers: 7810 7811`s' 7812 - `Specifies expression operand type as small' 7813 7814`m' 7815 - `Specifies expression operand type as medium' 7816 7817`l' 7818 - `Specifies expression operand type as large' 7819 7820`c' 7821 - `Specifies the CR16 Assembler generates a relocation entry for 7822 the operand, where pc has implied bit, the expression is adjusted 7823 accordingly. The linker uses the relocation entry to update the 7824 operand address at link time.' 7825 7826`got/GOT' 7827 - `Specifies the CR16 Assembler generates a relocation entry for 7828 the operand, offset from Global Offset Table. The linker uses this 7829 relocation entry to update the operand address at link time' 7830 7831`cgot/cGOT' 7832 - `Specifies the CompactRISC Assembler generates a relocation 7833 entry for the operand, where pc has implied bit, the expression is 7834 adjusted accordingly. The linker uses the relocation entry to 7835 update the operand address at link time.' 7836 7837 CR16 target operand qualifiers and its size (in bits): 7838 7839`Immediate Operand' 7840 - s --- 4 bits 7841 7842`' 7843 - m --- 16 bits, for movb and movw instructions. 7844 7845`' 7846 - m --- 20 bits, movd instructions. 7847 7848`' 7849 - l --- 32 bits 7850 7851`Absolute Operand' 7852 - s --- Illegal specifier for this operand. 7853 7854`' 7855 - m --- 20 bits, movd instructions. 7856 7857`Displacement Operand' 7858 - s --- 8 bits 7859 7860`' 7861 - m --- 16 bits 7862 7863`' 7864 - l --- 24 bits 7865 7866 For example: 7867 1 `movw $_myfun@c,r1' 7868 7869 This loads the address of _myfun, shifted right by 1, into r1. 7870 7871 2 `movd $_myfun@c,(r2,r1)' 7872 7873 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 7874 7875 3 `_myfun_ptr:' 7876 `.long _myfun@c' 7877 `loadd _myfun_ptr, (r1,r0)' 7878 `jal (r1,r0)' 7879 7880 This .long directive, the address of _myfunc, shifted right by 1 at link time. 7881 7882 4 `loadd _data1@GOT(r12), (r1,r0)' 7883 7884 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 7885 7886 5 `loadd _myfunc@cGOT(r12), (r1,r0)' 7887 7888 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 7889 7890 7891File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 7892 78939.7 CRIS Dependent Features 7894=========================== 7895 7896* Menu: 7897 7898* CRIS-Opts:: Command-line Options 7899* CRIS-Expand:: Instruction expansion 7900* CRIS-Symbols:: Symbols 7901* CRIS-Syntax:: Syntax 7902 7903 7904File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 7905 79069.7.1 Command-line Options 7907-------------------------- 7908 7909The CRIS version of `as' has these machine-dependent command-line 7910options. 7911 7912 The format of the generated object files can be either ELF or a.out, 7913specified by the command-line options `--emulation=crisaout' and 7914`--emulation=criself'. The default is ELF (criself), unless `as' has 7915been configured specifically for a.out by using the configuration name 7916`cris-axis-aout'. 7917 7918 There are two different link-incompatible ELF object file variants 7919for CRIS, for use in environments where symbols are expected to be 7920prefixed by a leading `_' character and for environments without such a 7921symbol prefix. The variant used for GNU/Linux port has no symbol 7922prefix. Which variant to produce is specified by either of the options 7923`--underscore' and `--no-underscore'. The default is `--underscore'. 7924Since symbols in CRIS a.out objects are expected to have a `_' prefix, 7925specifying `--no-underscore' when generating a.out objects is an error. 7926Besides the object format difference, the effect of this option is to 7927parse register names differently (*note crisnous::). The 7928`--no-underscore' option makes a `$' register prefix mandatory. 7929 7930 The option `--pic' must be passed to `as' in order to recognize the 7931symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 7932crispic::). This will also affect expansion of instructions. The 7933expansion with `--pic' will use PC-relative rather than (slightly 7934faster) absolute addresses in those expansions. 7935 7936 The option `--march=ARCHITECTURE' specifies the recognized 7937instruction set and recognized register names. It also controls the 7938architecture type of the object file. Valid values for ARCHITECTURE 7939are: 7940`v0_v10' 7941 All instructions and register names for any architecture variant 7942 in the set v0...v10 are recognized. This is the default if the 7943 target is configured as cris-*. 7944 7945`v10' 7946 Only instructions and register names for CRIS v10 (as found in 7947 ETRAX 100 LX) are recognized. This is the default if the target 7948 is configured as crisv10-*. 7949 7950`v32' 7951 Only instructions and register names for CRIS v32 (code name 7952 Guinness) are recognized. This is the default if the target is 7953 configured as crisv32-*. This value implies `--no-mul-bug-abort'. 7954 (A subsequent `--mul-bug-abort' will turn it back on.) 7955 7956`common_v10_v32' 7957 Only instructions with register names and addressing modes with 7958 opcodes common to the v10 and v32 are recognized. 7959 7960 When `-N' is specified, `as' will emit a warning when a 16-bit 7961branch instruction is expanded into a 32-bit multiple-instruction 7962construct (*note CRIS-Expand::). 7963 7964 Some versions of the CRIS v10, for example in the Etrax 100 LX, 7965contain a bug that causes destabilizing memory accesses when a multiply 7966instruction is executed with certain values in the first operand just 7967before a cache-miss. When the `--mul-bug-abort' command line option is 7968active (the default value), `as' will refuse to assemble a file 7969containing a multiply instruction at a dangerous offset, one that could 7970be the last on a cache-line, or is in a section with insufficient 7971alignment. This placement checking does not catch any case where the 7972multiply instruction is dangerously placed because it is located in a 7973delay-slot. The `--mul-bug-abort' command line option turns off the 7974checking. 7975 7976 7977File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 7978 79799.7.2 Instruction expansion 7980--------------------------- 7981 7982`as' will silently choose an instruction that fits the operand size for 7983`[register+constant]' operands. For example, the offset `127' in 7984`move.d [r3+127],r4' fits in an instruction using a signed-byte offset. 7985Similarly, `move.d [r2+32767],r1' will generate an instruction using a 798616-bit offset. For symbolic expressions and constants that do not fit 7987in 16 bits including the sign bit, a 32-bit offset is generated. 7988 7989 For branches, `as' will expand from a 16-bit branch instruction into 7990a sequence of instructions that can reach a full 32-bit address. Since 7991this does not correspond to a single instruction, such expansions can 7992optionally be warned about. *Note CRIS-Opts::. 7993 7994 If the operand is found to fit the range, a `lapc' mnemonic will 7995translate to a `lapcq' instruction. Use `lapc.d' to force the 32-bit 7996`lapc' instruction. 7997 7998 Similarly, the `addo' mnemonic will translate to the shortest 7999fitting instruction of `addoq', `addo.w' and `addo.d', when used with a 8000operand that is a constant known at assembly time. 8001 8002 8003File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 8004 80059.7.3 Symbols 8006------------- 8007 8008Some symbols are defined by the assembler. They're intended to be used 8009in conditional assembly, for example: 8010 .if ..asm.arch.cris.v32 8011 CODE FOR CRIS V32 8012 .elseif ..asm.arch.cris.common_v10_v32 8013 CODE COMMON TO CRIS V32 AND CRIS V10 8014 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 8015 CODE FOR V10 8016 .else 8017 .error "Code needs to be added here." 8018 .endif 8019 8020 These symbols are defined in the assembler, reflecting command-line 8021options, either when specified or the default. They are always 8022defined, to 0 or 1. 8023`..asm.arch.cris.any_v0_v10' 8024 This symbol is non-zero when `--march=v0_v10' is specified or the 8025 default. 8026 8027`..asm.arch.cris.common_v10_v32' 8028 Set according to the option `--march=common_v10_v32'. 8029 8030`..asm.arch.cris.v10' 8031 Reflects the option `--march=v10'. 8032 8033`..asm.arch.cris.v32' 8034 Corresponds to `--march=v10'. 8035 8036 Speaking of symbols, when a symbol is used in code, it can have a 8037suffix modifying its value for use in position-independent code. *Note 8038CRIS-Pic::. 8039 8040 8041File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 8042 80439.7.4 Syntax 8044------------ 8045 8046There are different aspects of the CRIS assembly syntax. 8047 8048* Menu: 8049 8050* CRIS-Chars:: Special Characters 8051* CRIS-Pic:: Position-Independent Code Symbols 8052* CRIS-Regs:: Register Names 8053* CRIS-Pseudos:: Assembler Directives 8054 8055 8056File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 8057 80589.7.4.1 Special Characters 8059.......................... 8060 8061The character `#' is a line comment character. It starts a comment if 8062and only if it is placed at the beginning of a line. 8063 8064 A `;' character starts a comment anywhere on the line, causing all 8065characters up to the end of the line to be ignored. 8066 8067 A `@' character is handled as a line separator equivalent to a 8068logical new-line character (except in a comment), so separate 8069instructions can be specified on a single line. 8070 8071 8072File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 8073 80749.7.4.2 Symbols in position-independent code 8075............................................ 8076 8077When generating position-independent code (SVR4 PIC) for use in 8078cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 8079suffixes are used to specify what kind of run-time symbol lookup will 8080be used, expressed in the object as different _relocation types_. 8081Usually, all absolute symbol values must be located in a table, the 8082_global offset table_, leaving the code position-independent; 8083independent of values of global symbols and independent of the address 8084of the code. The suffix modifies the value of the symbol, into for 8085example an index into the global offset table where the real symbol 8086value is entered, or a PC-relative value, or a value relative to the 8087start of the global offset table. All symbol suffixes start with the 8088character `:' (omitted in the list below). Every symbol use in code or 8089a read-only section must therefore have a PIC suffix to enable a useful 8090shared library to be created. Usually, these constructs must not be 8091used with an additive constant offset as is usually allowed, i.e. no 4 8092as in `symbol + 4' is allowed. This restriction is checked at 8093link-time, not at assembly-time. 8094 8095`GOT' 8096 Attaching this suffix to a symbol in an instruction causes the 8097 symbol to be entered into the global offset table. The value is a 8098 32-bit index for that symbol into the global offset table. The 8099 name of the corresponding relocation is `R_CRIS_32_GOT'. Example: 8100 `move.d [$r0+extsym:GOT],$r9' 8101 8102`GOT16' 8103 Same as for `GOT', but the value is a 16-bit index into the global 8104 offset table. The corresponding relocation is `R_CRIS_16_GOT'. 8105 Example: `move.d [$r0+asymbol:GOT16],$r10' 8106 8107`PLT' 8108 This suffix is used for function symbols. It causes a _procedure 8109 linkage table_, an array of code stubs, to be created at the time 8110 the shared object is created or linked against, together with a 8111 global offset table entry. The value is a pc-relative offset to 8112 the corresponding stub code in the procedure linkage table. This 8113 arrangement causes the run-time symbol resolver to be called to 8114 look up and set the value of the symbol the first time the 8115 function is called (at latest; depending environment variables). 8116 It is only safe to leave the symbol unresolved this way if all 8117 references are function calls. The name of the relocation is 8118 `R_CRIS_32_PLT_PCREL'. Example: `add.d fnname:PLT,$pc' 8119 8120`PLTG' 8121 Like PLT, but the value is relative to the beginning of the global 8122 offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example: 8123 `move.d fnname:PLTG,$r3' 8124 8125`GOTPLT' 8126 Similar to `PLT', but the value of the symbol is a 32-bit index 8127 into the global offset table. This is somewhat of a mix between 8128 the effect of the `GOT' and the `PLT' suffix; the difference to 8129 `GOT' is that there will be a procedure linkage table entry 8130 created, and that the symbol is assumed to be a function entry and 8131 will be resolved by the run-time resolver as with `PLT'. The 8132 relocation is `R_CRIS_32_GOTPLT'. Example: `jsr 8133 [$r0+fnname:GOTPLT]' 8134 8135`GOTPLT16' 8136 A variant of `GOTPLT' giving a 16-bit value. Its relocation name 8137 is `R_CRIS_16_GOTPLT'. Example: `jsr [$r0+fnname:GOTPLT16]' 8138 8139`GOTOFF' 8140 This suffix must only be attached to a local symbol, but may be 8141 used in an expression adding an offset. The value is the address 8142 of the symbol relative to the start of the global offset table. 8143 The relocation name is `R_CRIS_32_GOTREL'. Example: `move.d 8144 [$r0+localsym:GOTOFF],r3' 8145 8146 8147File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 8148 81499.7.4.3 Register names 8150...................... 8151 8152A `$' character may always prefix a general or special register name in 8153an instruction operand but is mandatory when the option 8154`--no-underscore' is specified or when the `.syntax register_prefix' 8155directive is in effect (*note crisnous::). Register names are 8156case-insensitive. 8157 8158 8159File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 8160 81619.7.4.4 Assembler Directives 8162............................ 8163 8164There are a few CRIS-specific pseudo-directives in addition to the 8165generic ones. *Note Pseudo Ops::. Constants emitted by 8166pseudo-directives are in little-endian order for CRIS. There is no 8167support for floating-point-specific directives for CRIS. 8168 8169`.dword EXPRESSIONS' 8170 The `.dword' directive is a synonym for `.int', expecting zero or 8171 more EXPRESSIONS, separated by commas. For each expression, a 8172 32-bit little-endian constant is emitted. 8173 8174`.syntax ARGUMENT' 8175 The `.syntax' directive takes as ARGUMENT one of the following 8176 case-sensitive choices. 8177 8178 `no_register_prefix' 8179 The `.syntax no_register_prefix' directive makes a `$' 8180 character prefix on all registers optional. It overrides a 8181 previous setting, including the corresponding effect of the 8182 option `--no-underscore'. If this directive is used when 8183 ordinary symbols do not have a `_' character prefix, care 8184 must be taken to avoid ambiguities whether an operand is a 8185 register or a symbol; using symbols with names the same as 8186 general or special registers then invoke undefined behavior. 8187 8188 `register_prefix' 8189 This directive makes a `$' character prefix on all registers 8190 mandatory. It overrides a previous setting, including the 8191 corresponding effect of the option `--underscore'. 8192 8193 `leading_underscore' 8194 This is an assertion directive, emitting an error if the 8195 `--no-underscore' option is in effect. 8196 8197 `no_leading_underscore' 8198 This is the opposite of the `.syntax leading_underscore' 8199 directive and emits an error if the option `--underscore' is 8200 in effect. 8201 8202`.arch ARGUMENT' 8203 This is an assertion directive, giving an error if the specified 8204 ARGUMENT is not the same as the specified or default value for the 8205 `--march=ARCHITECTURE' option (*note march-option::). 8206 8207 8208 8209File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 8210 82119.8 D10V Dependent Features 8212=========================== 8213 8214* Menu: 8215 8216* D10V-Opts:: D10V Options 8217* D10V-Syntax:: Syntax 8218* D10V-Float:: Floating Point 8219* D10V-Opcodes:: Opcodes 8220 8221 8222File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 8223 82249.8.1 D10V Options 8225------------------ 8226 8227The Mitsubishi D10V version of `as' has a few machine dependent options. 8228 8229`-O' 8230 The D10V can often execute two sub-instructions in parallel. When 8231 this option is used, `as' will attempt to optimize its output by 8232 detecting when instructions can be executed in parallel. 8233 8234`--nowarnswap' 8235 To optimize execution performance, `as' will sometimes swap the 8236 order of instructions. Normally this generates a warning. When 8237 this option is used, no warning will be generated when 8238 instructions are swapped. 8239 8240`--gstabs-packing' 8241`--no-gstabs-packing' 8242 `as' packs adjacent short instructions into a single packed 8243 instruction. `--no-gstabs-packing' turns instruction packing off if 8244 `--gstabs' is specified as well; `--gstabs-packing' (the default) 8245 turns instruction packing on even when `--gstabs' is specified. 8246 8247 8248File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 8249 82509.8.2 Syntax 8251------------ 8252 8253The D10V syntax is based on the syntax in Mitsubishi's D10V 8254architecture manual. The differences are detailed below. 8255 8256* Menu: 8257 8258* D10V-Size:: Size Modifiers 8259* D10V-Subs:: Sub-Instructions 8260* D10V-Chars:: Special Characters 8261* D10V-Regs:: Register Names 8262* D10V-Addressing:: Addressing Modes 8263* D10V-Word:: @WORD Modifier 8264 8265 8266File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 8267 82689.8.2.1 Size Modifiers 8269...................... 8270 8271The D10V version of `as' uses the instruction names in the D10V 8272Architecture Manual. However, the names in the manual are sometimes 8273ambiguous. There are instruction names that can assemble to a short or 8274long form opcode. How does the assembler pick the correct form? `as' 8275will always pick the smallest form if it can. When dealing with a 8276symbol that is not defined yet when a line is being assembled, it will 8277always use the long form. If you need to force the assembler to use 8278either the short or long form of the instruction, you can append either 8279`.s' (short) or `.l' (long) to it. For example, if you are writing an 8280assembly program and you want to do a branch to a symbol that is 8281defined later in your program, you can write `bra.s foo'. Objdump 8282and GDB will always append `.s' or `.l' to instructions which have both 8283short and long forms. 8284 8285 8286File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 8287 82889.8.2.2 Sub-Instructions 8289........................ 8290 8291The D10V assembler takes as input a series of instructions, either 8292one-per-line, or in the special two-per-line format described in the 8293next section. Some of these instructions will be short-form or 8294sub-instructions. These sub-instructions can be packed into a single 8295instruction. The assembler will do this automatically. It will also 8296detect when it should not pack instructions. For example, when a label 8297is defined, the next instruction will never be packaged with the 8298previous one. Whenever a branch and link instruction is called, it 8299will not be packaged with the next instruction so the return address 8300will be valid. Nops are automatically inserted when necessary. 8301 8302 If you do not want the assembler automatically making these 8303decisions, you can control the packaging and execution type (parallel 8304or sequential) with the special execution symbols described in the next 8305section. 8306 8307 8308File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 8309 83109.8.2.3 Special Characters 8311.......................... 8312 8313`;' and `#' are the line comment characters. Sub-instructions may be 8314executed in order, in reverse-order, or in parallel. Instructions 8315listed in the standard one-per-line format will be executed 8316sequentially. To specify the executing order, use the following 8317symbols: 8318`->' 8319 Sequential with instruction on the left first. 8320 8321`<-' 8322 Sequential with instruction on the right first. 8323 8324`||' 8325 Parallel 8326 The D10V syntax allows either one instruction per line, one 8327instruction per line with the execution symbol, or two instructions per 8328line. For example 8329`abs a1 -> abs r0' 8330 Execute these sequentially. The instruction on the right is in 8331 the right container and is executed second. 8332 8333`abs r0 <- abs a1' 8334 Execute these reverse-sequentially. The instruction on the right 8335 is in the right container, and is executed first. 8336 8337`ld2w r2,@r8+ || mac a0,r0,r7' 8338 Execute these in parallel. 8339 8340`ld2w r2,@r8+ ||' 8341`mac a0,r0,r7' 8342 Two-line format. Execute these in parallel. 8343 8344`ld2w r2,@r8+' 8345`mac a0,r0,r7' 8346 Two-line format. Execute these sequentially. Assembler will put 8347 them in the proper containers. 8348 8349`ld2w r2,@r8+ ->' 8350`mac a0,r0,r7' 8351 Two-line format. Execute these sequentially. Same as above but 8352 second instruction will always go into right container. 8353 Since `$' has no special meaning, you may use it in symbol names. 8354 8355 8356File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 8357 83589.8.2.4 Register Names 8359...................... 8360 8361You can use the predefined symbols `r0' through `r15' to refer to the 8362D10V registers. You can also use `sp' as an alias for `r15'. The 8363accumulators are `a0' and `a1'. There are special register-pair names 8364that may optionally be used in opcodes that require even-numbered 8365registers. Register names are not case sensitive. 8366 8367 Register Pairs 8368`r0-r1' 8369 8370`r2-r3' 8371 8372`r4-r5' 8373 8374`r6-r7' 8375 8376`r8-r9' 8377 8378`r10-r11' 8379 8380`r12-r13' 8381 8382`r14-r15' 8383 8384 The D10V also has predefined symbols for these control registers and 8385status bits: 8386`psw' 8387 Processor Status Word 8388 8389`bpsw' 8390 Backup Processor Status Word 8391 8392`pc' 8393 Program Counter 8394 8395`bpc' 8396 Backup Program Counter 8397 8398`rpt_c' 8399 Repeat Count 8400 8401`rpt_s' 8402 Repeat Start address 8403 8404`rpt_e' 8405 Repeat End address 8406 8407`mod_s' 8408 Modulo Start address 8409 8410`mod_e' 8411 Modulo End address 8412 8413`iba' 8414 Instruction Break Address 8415 8416`f0' 8417 Flag 0 8418 8419`f1' 8420 Flag 1 8421 8422`c' 8423 Carry flag 8424 8425 8426File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 8427 84289.8.2.5 Addressing Modes 8429........................ 8430 8431`as' understands the following addressing modes for the D10V. `RN' in 8432the following refers to any of the numbered registers, but _not_ the 8433control registers. 8434`RN' 8435 Register direct 8436 8437`@RN' 8438 Register indirect 8439 8440`@RN+' 8441 Register indirect with post-increment 8442 8443`@RN-' 8444 Register indirect with post-decrement 8445 8446`@-SP' 8447 Register indirect with pre-decrement 8448 8449`@(DISP, RN)' 8450 Register indirect with displacement 8451 8452`ADDR' 8453 PC relative address (for branch or rep). 8454 8455`#IMM' 8456 Immediate data (the `#' is optional and ignored) 8457 8458 8459File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 8460 84619.8.2.6 @WORD Modifier 8462...................... 8463 8464Any symbol followed by `@word' will be replaced by the symbol's value 8465shifted right by 2. This is used in situations such as loading a 8466register with the address of a function (or any other code fragment). 8467For example, if you want to load a register with the location of the 8468function `main' then jump to that function, you could do it as follows: 8469 ldi r2, main@word 8470 jmp r2 8471 8472 8473File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 8474 84759.8.3 Floating Point 8476-------------------- 8477 8478The D10V has no hardware floating point, but the `.float' and `.double' 8479directives generates IEEE floating-point numbers for compatibility with 8480other development tools. 8481 8482 8483File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 8484 84859.8.4 Opcodes 8486------------- 8487 8488For detailed information on the D10V machine instruction set, see `D10V 8489Architecture: A VLIW Microprocessor for Multimedia Applications' 8490(Mitsubishi Electric Corp.). `as' implements all the standard D10V 8491opcodes. The only changes are those described in the section on size 8492modifiers 8493 8494 8495File: as.info, Node: D30V-Dependent, Next: H8/300-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 8496 84979.9 D30V Dependent Features 8498=========================== 8499 8500* Menu: 8501 8502* D30V-Opts:: D30V Options 8503* D30V-Syntax:: Syntax 8504* D30V-Float:: Floating Point 8505* D30V-Opcodes:: Opcodes 8506 8507 8508File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 8509 85109.9.1 D30V Options 8511------------------ 8512 8513The Mitsubishi D30V version of `as' has a few machine dependent options. 8514 8515`-O' 8516 The D30V can often execute two sub-instructions in parallel. When 8517 this option is used, `as' will attempt to optimize its output by 8518 detecting when instructions can be executed in parallel. 8519 8520`-n' 8521 When this option is used, `as' will issue a warning every time it 8522 adds a nop instruction. 8523 8524`-N' 8525 When this option is used, `as' will issue a warning if it needs to 8526 insert a nop after a 32-bit multiply before a load or 16-bit 8527 multiply instruction. 8528 8529 8530File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 8531 85329.9.2 Syntax 8533------------ 8534 8535The D30V syntax is based on the syntax in Mitsubishi's D30V 8536architecture manual. The differences are detailed below. 8537 8538* Menu: 8539 8540* D30V-Size:: Size Modifiers 8541* D30V-Subs:: Sub-Instructions 8542* D30V-Chars:: Special Characters 8543* D30V-Guarded:: Guarded Execution 8544* D30V-Regs:: Register Names 8545* D30V-Addressing:: Addressing Modes 8546 8547 8548File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 8549 85509.9.2.1 Size Modifiers 8551...................... 8552 8553The D30V version of `as' uses the instruction names in the D30V 8554Architecture Manual. However, the names in the manual are sometimes 8555ambiguous. There are instruction names that can assemble to a short or 8556long form opcode. How does the assembler pick the correct form? `as' 8557will always pick the smallest form if it can. When dealing with a 8558symbol that is not defined yet when a line is being assembled, it will 8559always use the long form. If you need to force the assembler to use 8560either the short or long form of the instruction, you can append either 8561`.s' (short) or `.l' (long) to it. For example, if you are writing an 8562assembly program and you want to do a branch to a symbol that is 8563defined later in your program, you can write `bra.s foo'. Objdump and 8564GDB will always append `.s' or `.l' to instructions which have both 8565short and long forms. 8566 8567 8568File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 8569 85709.9.2.2 Sub-Instructions 8571........................ 8572 8573The D30V assembler takes as input a series of instructions, either 8574one-per-line, or in the special two-per-line format described in the 8575next section. Some of these instructions will be short-form or 8576sub-instructions. These sub-instructions can be packed into a single 8577instruction. The assembler will do this automatically. It will also 8578detect when it should not pack instructions. For example, when a label 8579is defined, the next instruction will never be packaged with the 8580previous one. Whenever a branch and link instruction is called, it 8581will not be packaged with the next instruction so the return address 8582will be valid. Nops are automatically inserted when necessary. 8583 8584 If you do not want the assembler automatically making these 8585decisions, you can control the packaging and execution type (parallel 8586or sequential) with the special execution symbols described in the next 8587section. 8588 8589 8590File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 8591 85929.9.2.3 Special Characters 8593.......................... 8594 8595`;' and `#' are the line comment characters. Sub-instructions may be 8596executed in order, in reverse-order, or in parallel. Instructions 8597listed in the standard one-per-line format will be executed 8598sequentially unless you use the `-O' option. 8599 8600 To specify the executing order, use the following symbols: 8601`->' 8602 Sequential with instruction on the left first. 8603 8604`<-' 8605 Sequential with instruction on the right first. 8606 8607`||' 8608 Parallel 8609 8610 The D30V syntax allows either one instruction per line, one 8611instruction per line with the execution symbol, or two instructions per 8612line. For example 8613`abs r2,r3 -> abs r4,r5' 8614 Execute these sequentially. The instruction on the right is in 8615 the right container and is executed second. 8616 8617`abs r2,r3 <- abs r4,r5' 8618 Execute these reverse-sequentially. The instruction on the right 8619 is in the right container, and is executed first. 8620 8621`abs r2,r3 || abs r4,r5' 8622 Execute these in parallel. 8623 8624`ldw r2,@(r3,r4) ||' 8625`mulx r6,r8,r9' 8626 Two-line format. Execute these in parallel. 8627 8628`mulx a0,r8,r9' 8629`stw r2,@(r3,r4)' 8630 Two-line format. Execute these sequentially unless `-O' option is 8631 used. If the `-O' option is used, the assembler will determine if 8632 the instructions could be done in parallel (the above two 8633 instructions can be done in parallel), and if so, emit them as 8634 parallel instructions. The assembler will put them in the proper 8635 containers. In the above example, the assembler will put the 8636 `stw' instruction in left container and the `mulx' instruction in 8637 the right container. 8638 8639`stw r2,@(r3,r4) ->' 8640`mulx a0,r8,r9' 8641 Two-line format. Execute the `stw' instruction followed by the 8642 `mulx' instruction sequentially. The first instruction goes in the 8643 left container and the second instruction goes into right 8644 container. The assembler will give an error if the machine 8645 ordering constraints are violated. 8646 8647`stw r2,@(r3,r4) <-' 8648`mulx a0,r8,r9' 8649 Same as previous example, except that the `mulx' instruction is 8650 executed before the `stw' instruction. 8651 8652 Since `$' has no special meaning, you may use it in symbol names. 8653 8654 8655File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 8656 86579.9.2.4 Guarded Execution 8658......................... 8659 8660`as' supports the full range of guarded execution directives for each 8661instruction. Just append the directive after the instruction proper. 8662The directives are: 8663 8664`/tx' 8665 Execute the instruction if flag f0 is true. 8666 8667`/fx' 8668 Execute the instruction if flag f0 is false. 8669 8670`/xt' 8671 Execute the instruction if flag f1 is true. 8672 8673`/xf' 8674 Execute the instruction if flag f1 is false. 8675 8676`/tt' 8677 Execute the instruction if both flags f0 and f1 are true. 8678 8679`/tf' 8680 Execute the instruction if flag f0 is true and flag f1 is false. 8681 8682 8683File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 8684 86859.9.2.5 Register Names 8686...................... 8687 8688You can use the predefined symbols `r0' through `r63' to refer to the 8689D30V registers. You can also use `sp' as an alias for `r63' and `link' 8690as an alias for `r62'. The accumulators are `a0' and `a1'. 8691 8692 The D30V also has predefined symbols for these control registers and 8693status bits: 8694`psw' 8695 Processor Status Word 8696 8697`bpsw' 8698 Backup Processor Status Word 8699 8700`pc' 8701 Program Counter 8702 8703`bpc' 8704 Backup Program Counter 8705 8706`rpt_c' 8707 Repeat Count 8708 8709`rpt_s' 8710 Repeat Start address 8711 8712`rpt_e' 8713 Repeat End address 8714 8715`mod_s' 8716 Modulo Start address 8717 8718`mod_e' 8719 Modulo End address 8720 8721`iba' 8722 Instruction Break Address 8723 8724`f0' 8725 Flag 0 8726 8727`f1' 8728 Flag 1 8729 8730`f2' 8731 Flag 2 8732 8733`f3' 8734 Flag 3 8735 8736`f4' 8737 Flag 4 8738 8739`f5' 8740 Flag 5 8741 8742`f6' 8743 Flag 6 8744 8745`f7' 8746 Flag 7 8747 8748`s' 8749 Same as flag 4 (saturation flag) 8750 8751`v' 8752 Same as flag 5 (overflow flag) 8753 8754`va' 8755 Same as flag 6 (sticky overflow flag) 8756 8757`c' 8758 Same as flag 7 (carry/borrow flag) 8759 8760`b' 8761 Same as flag 7 (carry/borrow flag) 8762 8763 8764File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 8765 87669.9.2.6 Addressing Modes 8767........................ 8768 8769`as' understands the following addressing modes for the D30V. `RN' in 8770the following refers to any of the numbered registers, but _not_ the 8771control registers. 8772`RN' 8773 Register direct 8774 8775`@RN' 8776 Register indirect 8777 8778`@RN+' 8779 Register indirect with post-increment 8780 8781`@RN-' 8782 Register indirect with post-decrement 8783 8784`@-SP' 8785 Register indirect with pre-decrement 8786 8787`@(DISP, RN)' 8788 Register indirect with displacement 8789 8790`ADDR' 8791 PC relative address (for branch or rep). 8792 8793`#IMM' 8794 Immediate data (the `#' is optional and ignored) 8795 8796 8797File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 8798 87999.9.3 Floating Point 8800-------------------- 8801 8802The D30V has no hardware floating point, but the `.float' and `.double' 8803directives generates IEEE floating-point numbers for compatibility with 8804other development tools. 8805 8806 8807File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 8808 88099.9.4 Opcodes 8810------------- 8811 8812For detailed information on the D30V machine instruction set, see `D30V 8813Architecture: A VLIW Microprocessor for Multimedia Applications' 8814(Mitsubishi Electric Corp.). `as' implements all the standard D30V 8815opcodes. The only changes are those described in the section on size 8816modifiers 8817 8818 8819File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 8820 88219.10 H8/300 Dependent Features 8822============================== 8823 8824* Menu: 8825 8826* H8/300 Options:: Options 8827* H8/300 Syntax:: Syntax 8828* H8/300 Floating Point:: Floating Point 8829* H8/300 Directives:: H8/300 Machine Directives 8830* H8/300 Opcodes:: Opcodes 8831 8832 8833File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 8834 88359.10.1 Options 8836-------------- 8837 8838The Renesas H8/300 version of `as' has one machine-dependent option: 8839 8840`-h-tick-hex' 8841 Support H'00 style hex constants in addition to 0x00 style. 8842 8843 8844 8845File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 8846 88479.10.2 Syntax 8848------------- 8849 8850* Menu: 8851 8852* H8/300-Chars:: Special Characters 8853* H8/300-Regs:: Register Names 8854* H8/300-Addressing:: Addressing Modes 8855 8856 8857File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 8858 88599.10.2.1 Special Characters 8860........................... 8861 8862`;' is the line comment character. 8863 8864 `$' can be used instead of a newline to separate statements. 8865Therefore _you may not use `$' in symbol names_ on the H8/300. 8866 8867 8868File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 8869 88709.10.2.2 Register Names 8871....................... 8872 8873You can use predefined symbols of the form `rNh' and `rNl' to refer to 8874the H8/300 registers as sixteen 8-bit general-purpose registers. N is 8875a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid 8876register names. 8877 8878 You can also use the eight predefined symbols `rN' to refer to the 8879H8/300 registers as 16-bit registers (you must use this form for 8880addressing). 8881 8882 On the H8/300H, you can also use the eight predefined symbols `erN' 8883(`er0' ... `er7') to refer to the 32-bit general purpose registers. 8884 8885 The two control registers are called `pc' (program counter; a 16-bit 8886register, except on the H8/300H where it is 24 bits) and `ccr' 8887(condition code register; an 8-bit register). `r7' is used as the 8888stack pointer, and can also be called `sp'. 8889 8890 8891File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 8892 88939.10.2.3 Addressing Modes 8894......................... 8895 8896as understands the following addressing modes for the H8/300: 8897`rN' 8898 Register direct 8899 8900`@rN' 8901 Register indirect 8902 8903`@(D, rN)' 8904`@(D:16, rN)' 8905`@(D:24, rN)' 8906 Register indirect: 16-bit or 24-bit displacement D from register 8907 N. (24-bit displacements are only meaningful on the H8/300H.) 8908 8909`@rN+' 8910 Register indirect with post-increment 8911 8912`@-rN' 8913 Register indirect with pre-decrement 8914 8915``@'AA' 8916``@'AA:8' 8917``@'AA:16' 8918``@'AA:24' 8919 Absolute address `aa'. (The address size `:24' only makes sense 8920 on the H8/300H.) 8921 8922`#XX' 8923`#XX:8' 8924`#XX:16' 8925`#XX:32' 8926 Immediate data XX. You may specify the `:8', `:16', or `:32' for 8927 clarity, if you wish; but `as' neither requires this nor uses 8928 it--the data size required is taken from context. 8929 8930``@'`@'AA' 8931``@'`@'AA:8' 8932 Memory indirect. You may specify the `:8' for clarity, if you 8933 wish; but `as' neither requires this nor uses it. 8934 8935 8936File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 8937 89389.10.3 Floating Point 8939--------------------- 8940 8941The H8/300 family has no hardware floating point, but the `.float' 8942directive generates IEEE floating-point numbers for compatibility with 8943other development tools. 8944 8945 8946File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 8947 89489.10.4 H8/300 Machine Directives 8949-------------------------------- 8950 8951`as' has the following machine-dependent directives for the H8/300: 8952 8953`.h8300h' 8954 Recognize and emit additional instructions for the H8/300H 8955 variant, and also make `.int' emit 32-bit numbers rather than the 8956 usual (16-bit) for the H8/300 family. 8957 8958`.h8300s' 8959 Recognize and emit additional instructions for the H8S variant, and 8960 also make `.int' emit 32-bit numbers rather than the usual (16-bit) 8961 for the H8/300 family. 8962 8963`.h8300hn' 8964 Recognize and emit additional instructions for the H8/300H variant 8965 in normal mode, and also make `.int' emit 32-bit numbers rather 8966 than the usual (16-bit) for the H8/300 family. 8967 8968`.h8300sn' 8969 Recognize and emit additional instructions for the H8S variant in 8970 normal mode, and also make `.int' emit 32-bit numbers rather than 8971 the usual (16-bit) for the H8/300 family. 8972 8973 On the H8/300 family (including the H8/300H) `.word' directives 8974generate 16-bit numbers. 8975 8976 8977File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 8978 89799.10.5 Opcodes 8980-------------- 8981 8982For detailed information on the H8/300 machine instruction set, see 8983`H8/300 Series Programming Manual'. For information specific to the 8984H8/300H, see `H8/300H Series Programming Manual' (Renesas). 8985 8986 `as' implements all the standard H8/300 opcodes. No additional 8987pseudo-instructions are needed on this family. 8988 8989 The following table summarizes the H8/300 opcodes, and their 8990arguments. Entries marked `*' are opcodes used only on the H8/300H. 8991 8992 Legend: 8993 Rs source register 8994 Rd destination register 8995 abs absolute address 8996 imm immediate data 8997 disp:N N-bit displacement from a register 8998 pcrel:N N-bit displacement relative to program counter 8999 9000 add.b #imm,rd * andc #imm,ccr 9001 add.b rs,rd band #imm,rd 9002 add.w rs,rd band #imm,@rd 9003 * add.w #imm,rd band #imm,@abs:8 9004 * add.l rs,rd bra pcrel:8 9005 * add.l #imm,rd * bra pcrel:16 9006 adds #imm,rd bt pcrel:8 9007 addx #imm,rd * bt pcrel:16 9008 addx rs,rd brn pcrel:8 9009 and.b #imm,rd * brn pcrel:16 9010 and.b rs,rd bf pcrel:8 9011 * and.w rs,rd * bf pcrel:16 9012 * and.w #imm,rd bhi pcrel:8 9013 * and.l #imm,rd * bhi pcrel:16 9014 * and.l rs,rd bls pcrel:8 9015 9016 * bls pcrel:16 bld #imm,rd 9017 bcc pcrel:8 bld #imm,@rd 9018 * bcc pcrel:16 bld #imm,@abs:8 9019 bhs pcrel:8 bnot #imm,rd 9020 * bhs pcrel:16 bnot #imm,@rd 9021 bcs pcrel:8 bnot #imm,@abs:8 9022 * bcs pcrel:16 bnot rs,rd 9023 blo pcrel:8 bnot rs,@rd 9024 * blo pcrel:16 bnot rs,@abs:8 9025 bne pcrel:8 bor #imm,rd 9026 * bne pcrel:16 bor #imm,@rd 9027 beq pcrel:8 bor #imm,@abs:8 9028 * beq pcrel:16 bset #imm,rd 9029 bvc pcrel:8 bset #imm,@rd 9030 * bvc pcrel:16 bset #imm,@abs:8 9031 bvs pcrel:8 bset rs,rd 9032 * bvs pcrel:16 bset rs,@rd 9033 bpl pcrel:8 bset rs,@abs:8 9034 * bpl pcrel:16 bsr pcrel:8 9035 bmi pcrel:8 bsr pcrel:16 9036 * bmi pcrel:16 bst #imm,rd 9037 bge pcrel:8 bst #imm,@rd 9038 * bge pcrel:16 bst #imm,@abs:8 9039 blt pcrel:8 btst #imm,rd 9040 * blt pcrel:16 btst #imm,@rd 9041 bgt pcrel:8 btst #imm,@abs:8 9042 * bgt pcrel:16 btst rs,rd 9043 ble pcrel:8 btst rs,@rd 9044 * ble pcrel:16 btst rs,@abs:8 9045 bclr #imm,rd bxor #imm,rd 9046 bclr #imm,@rd bxor #imm,@rd 9047 bclr #imm,@abs:8 bxor #imm,@abs:8 9048 bclr rs,rd cmp.b #imm,rd 9049 bclr rs,@rd cmp.b rs,rd 9050 bclr rs,@abs:8 cmp.w rs,rd 9051 biand #imm,rd cmp.w rs,rd 9052 biand #imm,@rd * cmp.w #imm,rd 9053 biand #imm,@abs:8 * cmp.l #imm,rd 9054 bild #imm,rd * cmp.l rs,rd 9055 bild #imm,@rd daa rs 9056 bild #imm,@abs:8 das rs 9057 bior #imm,rd dec.b rs 9058 bior #imm,@rd * dec.w #imm,rd 9059 bior #imm,@abs:8 * dec.l #imm,rd 9060 bist #imm,rd divxu.b rs,rd 9061 bist #imm,@rd * divxu.w rs,rd 9062 bist #imm,@abs:8 * divxs.b rs,rd 9063 bixor #imm,rd * divxs.w rs,rd 9064 bixor #imm,@rd eepmov 9065 bixor #imm,@abs:8 * eepmovw 9066 9067 * exts.w rd mov.w rs,@abs:16 9068 * exts.l rd * mov.l #imm,rd 9069 * extu.w rd * mov.l rs,rd 9070 * extu.l rd * mov.l @rs,rd 9071 inc rs * mov.l @(disp:16,rs),rd 9072 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 9073 * inc.l #imm,rd * mov.l @rs+,rd 9074 jmp @rs * mov.l @abs:16,rd 9075 jmp abs * mov.l @abs:24,rd 9076 jmp @@abs:8 * mov.l rs,@rd 9077 jsr @rs * mov.l rs,@(disp:16,rd) 9078 jsr abs * mov.l rs,@(disp:24,rd) 9079 jsr @@abs:8 * mov.l rs,@-rd 9080 ldc #imm,ccr * mov.l rs,@abs:16 9081 ldc rs,ccr * mov.l rs,@abs:24 9082 * ldc @abs:16,ccr movfpe @abs:16,rd 9083 * ldc @abs:24,ccr movtpe rs,@abs:16 9084 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 9085 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 9086 * ldc @rs+,ccr * mulxs.b rs,rd 9087 * ldc @rs,ccr * mulxs.w rs,rd 9088 * mov.b @(disp:24,rs),rd neg.b rs 9089 * mov.b rs,@(disp:24,rd) * neg.w rs 9090 mov.b @abs:16,rd * neg.l rs 9091 mov.b rs,rd nop 9092 mov.b @abs:8,rd not.b rs 9093 mov.b rs,@abs:8 * not.w rs 9094 mov.b rs,rd * not.l rs 9095 mov.b #imm,rd or.b #imm,rd 9096 mov.b @rs,rd or.b rs,rd 9097 mov.b @(disp:16,rs),rd * or.w #imm,rd 9098 mov.b @rs+,rd * or.w rs,rd 9099 mov.b @abs:8,rd * or.l #imm,rd 9100 mov.b rs,@rd * or.l rs,rd 9101 mov.b rs,@(disp:16,rd) orc #imm,ccr 9102 mov.b rs,@-rd pop.w rs 9103 mov.b rs,@abs:8 * pop.l rs 9104 mov.w rs,@rd push.w rs 9105 * mov.w @(disp:24,rs),rd * push.l rs 9106 * mov.w rs,@(disp:24,rd) rotl.b rs 9107 * mov.w @abs:24,rd * rotl.w rs 9108 * mov.w rs,@abs:24 * rotl.l rs 9109 mov.w rs,rd rotr.b rs 9110 mov.w #imm,rd * rotr.w rs 9111 mov.w @rs,rd * rotr.l rs 9112 mov.w @(disp:16,rs),rd rotxl.b rs 9113 mov.w @rs+,rd * rotxl.w rs 9114 mov.w @abs:16,rd * rotxl.l rs 9115 mov.w rs,@(disp:16,rd) rotxr.b rs 9116 mov.w rs,@-rd * rotxr.w rs 9117 9118 * rotxr.l rs * stc ccr,@(disp:24,rd) 9119 bpt * stc ccr,@-rd 9120 rte * stc ccr,@abs:16 9121 rts * stc ccr,@abs:24 9122 shal.b rs sub.b rs,rd 9123 * shal.w rs sub.w rs,rd 9124 * shal.l rs * sub.w #imm,rd 9125 shar.b rs * sub.l rs,rd 9126 * shar.w rs * sub.l #imm,rd 9127 * shar.l rs subs #imm,rd 9128 shll.b rs subx #imm,rd 9129 * shll.w rs subx rs,rd 9130 * shll.l rs * trapa #imm 9131 shlr.b rs xor #imm,rd 9132 * shlr.w rs xor rs,rd 9133 * shlr.l rs * xor.w #imm,rd 9134 sleep * xor.w rs,rd 9135 stc ccr,rd * xor.l #imm,rd 9136 * stc ccr,@rs * xor.l rs,rd 9137 * stc ccr,@(disp:16,rd) xorc #imm,ccr 9138 9139 Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined 9140with variants using the suffixes `.b', `.w', and `.l' to specify the 9141size of a memory operand. `as' supports these suffixes, but does not 9142require them; since one of the operands is always a register, `as' can 9143deduce the correct size. 9144 9145 For example, since `r0' refers to a 16-bit register, 9146 mov r0,@foo 9147is equivalent to 9148 mov.w r0,@foo 9149 9150 If you use the size suffixes, `as' issues a warning when the suffix 9151and the register size do not match. 9152 9153 9154File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 9155 91569.11 HPPA Dependent Features 9157============================ 9158 9159* Menu: 9160 9161* HPPA Notes:: Notes 9162* HPPA Options:: Options 9163* HPPA Syntax:: Syntax 9164* HPPA Floating Point:: Floating Point 9165* HPPA Directives:: HPPA Machine Directives 9166* HPPA Opcodes:: Opcodes 9167 9168 9169File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 9170 91719.11.1 Notes 9172------------ 9173 9174As a back end for GNU CC `as' has been throughly tested and should work 9175extremely well. We have tested it only minimally on hand written 9176assembly code and no one has tested it much on the assembly output from 9177the HP compilers. 9178 9179 The format of the debugging sections has changed since the original 9180`as' port (version 1.3X) was released; therefore, you must rebuild all 9181HPPA objects and libraries with the new assembler so that you can debug 9182the final executable. 9183 9184 The HPPA `as' port generates a small subset of the relocations 9185available in the SOM and ELF object file formats. Additional relocation 9186support will be added as it becomes necessary. 9187 9188 9189File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 9190 91919.11.2 Options 9192-------------- 9193 9194`as' has no machine-dependent command-line options for the HPPA. 9195 9196 9197File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 9198 91999.11.3 Syntax 9200------------- 9201 9202The assembler syntax closely follows the HPPA instruction set reference 9203manual; assembler directives and general syntax closely follow the HPPA 9204assembly language reference manual, with a few noteworthy differences. 9205 9206 First, a colon may immediately follow a label definition. This is 9207simply for compatibility with how most assembly language programmers 9208write code. 9209 9210 Some obscure expression parsing problems may affect hand written 9211code which uses the `spop' instructions, or code which makes significant 9212use of the `!' line separator. 9213 9214 `as' is much less forgiving about missing arguments and other 9215similar oversights than the HP assembler. `as' notifies you of missing 9216arguments as syntax errors; this is regarded as a feature, not a bug. 9217 9218 Finally, `as' allows you to use an external symbol without 9219explicitly importing the symbol. _Warning:_ in the future this will be 9220an error for HPPA targets. 9221 9222 Special characters for HPPA targets include: 9223 9224 `;' is the line comment character. 9225 9226 `!' can be used instead of a newline to separate statements. 9227 9228 Since `$' has no special meaning, you may use it in symbol names. 9229 9230 9231File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 9232 92339.11.4 Floating Point 9234--------------------- 9235 9236The HPPA family uses IEEE floating-point numbers. 9237 9238 9239File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 9240 92419.11.5 HPPA Assembler Directives 9242-------------------------------- 9243 9244`as' for the HPPA supports many additional directives for compatibility 9245with the native assembler. This section describes them only briefly. 9246For detailed information on HPPA-specific assembler directives, see 9247`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). 9248 9249 `as' does _not_ support the following assembler directives described 9250in the HP manual: 9251 9252 .endm .liston 9253 .enter .locct 9254 .leave .macro 9255 .listoff 9256 9257 Beyond those implemented for compatibility, `as' supports one 9258additional assembler directive for the HPPA: `.param'. It conveys 9259register argument locations for static functions. Its syntax closely 9260follows the `.export' directive. 9261 9262 These are the additional directives in `as' for the HPPA: 9263 9264`.block N' 9265`.blockz N' 9266 Reserve N bytes of storage, and initialize them to zero. 9267 9268`.call' 9269 Mark the beginning of a procedure call. Only the special case 9270 with _no arguments_ is allowed. 9271 9272`.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' 9273 Specify a number of parameters and flags that define the 9274 environment for a procedure. 9275 9276 PARAM may be any of `frame' (frame size), `entry_gr' (end of 9277 general register range), `entry_fr' (end of float register range), 9278 `entry_sr' (end of space register range). 9279 9280 The values for FLAG are `calls' or `caller' (proc has 9281 subroutines), `no_calls' (proc does not call subroutines), 9282 `save_rp' (preserve return pointer), `save_sp' (proc preserves 9283 stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' 9284 (proc is interrupt routine). 9285 9286`.code' 9287 Assemble into the standard section called `$TEXT$', subsection 9288 `$CODE$'. 9289 9290`.copyright "STRING"' 9291 In the SOM object format, insert STRING into the object code, 9292 marked as a copyright string. 9293 9294`.copyright "STRING"' 9295 In the ELF object format, insert STRING into the object code, 9296 marked as a version string. 9297 9298`.enter' 9299 Not yet supported; the assembler rejects programs containing this 9300 directive. 9301 9302`.entry' 9303 Mark the beginning of a procedure. 9304 9305`.exit' 9306 Mark the end of a procedure. 9307 9308`.export NAME [ ,TYP ] [ ,PARAM=R ]' 9309 Make a procedure NAME available to callers. TYP, if present, must 9310 be one of `absolute', `code' (ELF only, not SOM), `data', `entry', 9311 `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'. 9312 9313 PARAM, if present, provides either relocation information for the 9314 procedure arguments and result, or a privilege level. PARAM may be 9315 `argwN' (where N ranges from `0' to `3', and indicates one of four 9316 one-word arguments); `rtnval' (the procedure's result); or 9317 `priv_lev' (privilege level). For arguments or the result, R 9318 specifies how to relocate, and must be one of `no' (not 9319 relocatable), `gr' (argument is in general register), `fr' (in 9320 floating point register), or `fu' (upper half of float register). 9321 For `priv_lev', R is an integer. 9322 9323`.half N' 9324 Define a two-byte integer constant N; synonym for the portable 9325 `as' directive `.short'. 9326 9327`.import NAME [ ,TYP ]' 9328 Converse of `.export'; make a procedure available to call. The 9329 arguments use the same conventions as the first two arguments for 9330 `.export'. 9331 9332`.label NAME' 9333 Define NAME as a label for the current assembly location. 9334 9335`.leave' 9336 Not yet supported; the assembler rejects programs containing this 9337 directive. 9338 9339`.origin LC' 9340 Advance location counter to LC. Synonym for the `as' portable 9341 directive `.org'. 9342 9343`.param NAME [ ,TYP ] [ ,PARAM=R ]' 9344 Similar to `.export', but used for static procedures. 9345 9346`.proc' 9347 Use preceding the first statement of a procedure. 9348 9349`.procend' 9350 Use following the last statement of a procedure. 9351 9352`LABEL .reg EXPR' 9353 Synonym for `.equ'; define LABEL with the absolute expression EXPR 9354 as its value. 9355 9356`.space SECNAME [ ,PARAMS ]' 9357 Switch to section SECNAME, creating a new section by that name if 9358 necessary. You may only use PARAMS when creating a new section, 9359 not when switching to an existing one. SECNAME may identify a 9360 section by number rather than by name. 9361 9362 If specified, the list PARAMS declares attributes of the section, 9363 identified by keywords. The keywords recognized are `spnum=EXP' 9364 (identify this section by the number EXP, an absolute expression), 9365 `sort=EXP' (order sections according to this sort key when linking; 9366 EXP is an absolute expression), `unloadable' (section contains no 9367 loadable data), `notdefined' (this section defined elsewhere), and 9368 `private' (data in this section not available to other programs). 9369 9370`.spnum SECNAM' 9371 Allocate four bytes of storage, and initialize them with the 9372 section number of the section named SECNAM. (You can define the 9373 section number with the HPPA `.space' directive.) 9374 9375`.string "STR"' 9376 Copy the characters in the string STR to the object file. *Note 9377 Strings: Strings, for information on escape sequences you can use 9378 in `as' strings. 9379 9380 _Warning!_ The HPPA version of `.string' differs from the usual 9381 `as' definition: it does _not_ write a zero byte after copying STR. 9382 9383`.stringz "STR"' 9384 Like `.string', but appends a zero byte after copying STR to object 9385 file. 9386 9387`.subspa NAME [ ,PARAMS ]' 9388`.nsubspa NAME [ ,PARAMS ]' 9389 Similar to `.space', but selects a subsection NAME within the 9390 current section. You may only specify PARAMS when you create a 9391 subsection (in the first instance of `.subspa' for this NAME). 9392 9393 If specified, the list PARAMS declares attributes of the 9394 subsection, identified by keywords. The keywords recognized are 9395 `quad=EXPR' ("quadrant" for this subsection), `align=EXPR' 9396 (alignment for beginning of this subsection; a power of two), 9397 `access=EXPR' (value for "access rights" field), `sort=EXPR' 9398 (sorting order for this subspace in link), `code_only' (subsection 9399 contains only code), `unloadable' (subsection cannot be loaded 9400 into memory), `comdat' (subsection is comdat), `common' 9401 (subsection is common block), `dup_comm' (subsection may have 9402 duplicate names), or `zero' (subsection is all zeros, do not write 9403 in object file). 9404 9405 `.nsubspa' always creates a new subspace with the given name, even 9406 if one with the same name already exists. 9407 9408 `comdat', `common' and `dup_comm' can be used to implement various 9409 flavors of one-only support when using the SOM linker. The SOM 9410 linker only supports specific combinations of these flags. The 9411 details are not documented. A brief description is provided here. 9412 9413 `comdat' provides a form of linkonce support. It is useful for 9414 both code and data subspaces. A `comdat' subspace has a key symbol 9415 marked by the `is_comdat' flag or `ST_COMDAT'. Only the first 9416 subspace for any given key is selected. The key symbol becomes 9417 universal in shared links. This is similar to the behavior of 9418 `secondary_def' symbols. 9419 9420 `common' provides Fortran named common support. It is only useful 9421 for data subspaces. Symbols with the flag `is_common' retain this 9422 flag in shared links. Referencing a `is_common' symbol in a shared 9423 library from outside the library doesn't work. Thus, `is_common' 9424 symbols must be output whenever they are needed. 9425 9426 `common' and `dup_comm' together provide Cobol common support. 9427 The subspaces in this case must all be the same length. 9428 Otherwise, this support is similar to the Fortran common support. 9429 9430 `dup_comm' by itself provides a type of one-only support for code. 9431 Only the first `dup_comm' subspace is selected. There is a rather 9432 complex algorithm to compare subspaces. Code symbols marked with 9433 the `dup_common' flag are hidden. This support was intended for 9434 "C++ duplicate inlines". 9435 9436 A simplified technique is used to mark the flags of symbols based 9437 on the flags of their subspace. A symbol with the scope 9438 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 9439 the corresponding settings of `comdat', `common' and `dup_comm' 9440 from the subspace, respectively. This avoids having to introduce 9441 additional directives to mark these symbols. The HP assembler 9442 sets `is_common' from `common'. However, it doesn't set the 9443 `dup_common' from `dup_comm'. It doesn't have `comdat' support. 9444 9445`.version "STR"' 9446 Write STR as version identifier in object code. 9447 9448 9449File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 9450 94519.11.6 Opcodes 9452-------------- 9453 9454For detailed information on the HPPA machine instruction set, see 9455`PA-RISC Architecture and Instruction Set Reference Manual' (HP 945609740-90039). 9457 9458 9459File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 9460 94619.12 ESA/390 Dependent Features 9462=============================== 9463 9464* Menu: 9465 9466* ESA/390 Notes:: Notes 9467* ESA/390 Options:: Options 9468* ESA/390 Syntax:: Syntax 9469* ESA/390 Floating Point:: Floating Point 9470* ESA/390 Directives:: ESA/390 Machine Directives 9471* ESA/390 Opcodes:: Opcodes 9472 9473 9474File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent 9475 94769.12.1 Notes 9477------------ 9478 9479The ESA/390 `as' port is currently intended to be a back-end for the 9480GNU CC compiler. It is not HLASM compatible, although it does support 9481a subset of some of the HLASM directives. The only supported binary 9482file format is ELF; none of the usual MVS/VM/OE/USS object file 9483formats, such as ESD or XSD, are supported. 9484 9485 When used with the GNU CC compiler, the ESA/390 `as' will produce 9486correct, fully relocated, functional binaries, and has been used to 9487compile and execute large projects. However, many aspects should still 9488be considered experimental; these include shared library support, 9489dynamically loadable objects, and any relocation other than the 31-bit 9490relocation. 9491 9492 9493File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent 9494 94959.12.2 Options 9496-------------- 9497 9498`as' has no machine-dependent command-line options for the ESA/390. 9499 9500 9501File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent 9502 95039.12.3 Syntax 9504------------- 9505 9506The opcode/operand syntax follows the ESA/390 Principles of Operation 9507manual; assembler directives and general syntax are loosely based on the 9508prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives 9509are _not_ supported for the most part, with the exception of those 9510described herein. 9511 9512 A leading dot in front of directives is optional, and the case of 9513directives is ignored; thus for example, .using and USING have the same 9514effect. 9515 9516 A colon may immediately follow a label definition. This is simply 9517for compatibility with how most assembly language programmers write 9518code. 9519 9520 `#' is the line comment character. 9521 9522 `;' can be used instead of a newline to separate statements. 9523 9524 Since `$' has no special meaning, you may use it in symbol names. 9525 9526 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, 9527fp6. By using thesse symbolic names, `as' can detect simple syntax 9528errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for 9529r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base 9530for r3 and rpgt or r.pgt for r4. 9531 9532 `*' is the current location counter. Unlike `.' it is always 9533relative to the last USING directive. Note that this means that 9534expressions cannot use multiplication, as any occurrence of `*' will be 9535interpreted as a location counter. 9536 9537 All labels are relative to the last USING. Thus, branches to a label 9538always imply the use of base+displacement. 9539 9540 Many of the usual forms of address constants / address literals are 9541supported. Thus, 9542 .using *,r3 9543 L r15,=A(some_routine) 9544 LM r6,r7,=V(some_longlong_extern) 9545 A r1,=F'12' 9546 AH r0,=H'42' 9547 ME r6,=E'3.1416' 9548 MD r6,=D'3.14159265358979' 9549 O r6,=XL4'cacad0d0' 9550 .ltorg 9551 should all behave as expected: that is, an entry in the literal pool 9552will be created (or reused if it already exists), and the instruction 9553operands will be the displacement into the literal pool using the 9554current base register (as last declared with the `.using' directive). 9555 9556 9557File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent 9558 95599.12.4 Floating Point 9560--------------------- 9561 9562The assembler generates only IEEE floating-point numbers. The older 9563floating point formats are not supported. 9564 9565 9566File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent 9567 95689.12.5 ESA/390 Assembler Directives 9569----------------------------------- 9570 9571`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler 9572directives that are documented in the main part of this documentation. 9573Several additional directives are supported in order to implement the 9574ESA/390 addressing model. The most important of these are `.using' and 9575`.ltorg' 9576 9577 These are the additional directives in `as' for the ESA/390: 9578 9579`.dc' 9580 A small subset of the usual DC directive is supported. 9581 9582`.drop REGNO' 9583 Stop using REGNO as the base register. The REGNO must have been 9584 previously declared with a `.using' directive in the same section 9585 as the current section. 9586 9587`.ebcdic STRING' 9588 Emit the EBCDIC equivalent of the indicated string. The emitted 9589 string will be null terminated. Note that the directives 9590 `.string' etc. emit ascii strings by default. 9591 9592`EQU' 9593 The standard HLASM-style EQU directive is not supported; however, 9594 the standard `as' directive .equ can be used to the same effect. 9595 9596`.ltorg' 9597 Dump the literal pool accumulated so far; begin a new literal pool. 9598 The literal pool will be written in the current section; in order 9599 to generate correct assembly, a `.using' must have been previously 9600 specified in the same section. 9601 9602`.using EXPR,REGNO' 9603 Use REGNO as the base register for all subsequent RX, RS, and SS 9604 form instructions. The EXPR will be evaluated to obtain the base 9605 address; usually, EXPR will merely be `*'. 9606 9607 This assembler allows two `.using' directives to be simultaneously 9608 outstanding, one in the `.text' section, and one in another section 9609 (typically, the `.data' section). This feature allows dynamically 9610 loaded objects to be implemented in a relatively straightforward 9611 way. A `.using' directive must always be specified in the `.text' 9612 section; this will specify the base register that will be used for 9613 branches in the `.text' section. A second `.using' may be 9614 specified in another section; this will specify the base register 9615 that is used for non-label address literals. When a second 9616 `.using' is specified, then the subsequent `.ltorg' must be put in 9617 the same section; otherwise an error will result. 9618 9619 Thus, for example, the following code uses `r3' to address branch 9620 targets and `r4' to address the literal pool, which has been 9621 written to the `.data' section. The is, the constants 9622 `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in 9623 the `.data' section. 9624 9625 .data 9626 .using LITPOOL,r4 9627 .text 9628 BASR r3,0 9629 .using *,r3 9630 B START 9631 .long LITPOOL 9632 START: 9633 L r4,4(,r3) 9634 L r15,=A(some_routine) 9635 LTR r15,r15 9636 BNE LABEL 9637 AH r0,=H'42' 9638 LABEL: 9639 ME r6,=E'3.1416' 9640 .data 9641 LITPOOL: 9642 .ltorg 9643 9644 Note that this dual-`.using' directive semantics extends and is 9645 not compatible with HLASM semantics. Note that this assembler 9646 directive does not support the full range of HLASM semantics. 9647 9648 9649 9650File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent 9651 96529.12.6 Opcodes 9653-------------- 9654 9655For detailed information on the ESA/390 machine instruction set, see 9656`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). 9657 9658 9659File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies 9660 96619.13 80386 Dependent Features 9662============================= 9663 9664 The i386 version `as' supports both the original Intel 386 9665architecture in both 16 and 32-bit mode as well as AMD x86-64 9666architecture extending the Intel architecture to 64-bits. 9667 9668* Menu: 9669 9670* i386-Options:: Options 9671* i386-Directives:: X86 specific directives 9672* i386-Syntax:: AT&T Syntax versus Intel Syntax 9673* i386-Mnemonics:: Instruction Naming 9674* i386-Regs:: Register Naming 9675* i386-Prefixes:: Instruction Prefixes 9676* i386-Memory:: Memory References 9677* i386-Jumps:: Handling of Jump Instructions 9678* i386-Float:: Floating Point 9679* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 9680* i386-LWP:: AMD's Lightweight Profiling Instructions 9681* i386-16bit:: Writing 16-bit Code 9682* i386-Arch:: Specifying an x86 CPU architecture 9683* i386-Bugs:: AT&T Syntax bugs 9684* i386-Notes:: Notes 9685 9686 9687File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 9688 96899.13.1 Options 9690-------------- 9691 9692The i386 version of `as' has a few machine dependent options: 9693 9694`--32 | --64' 9695 Select the word size, either 32 bits or 64 bits. Selecting 32-bit 9696 implies Intel i386 architecture, while 64-bit implies AMD x86-64 9697 architecture. 9698 9699 These options are only available with the ELF object file format, 9700 and require that the necessary BFD support has been included (on a 9701 32-bit platform you have to add -enable-64-bit-bfd to configure 9702 enable 64-bit usage and use x86-64 as target platform). 9703 9704`-n' 9705 By default, x86 GAS replaces multiple nop instructions used for 9706 alignment within code sections with multi-byte nop instructions 9707 such as leal 0(%esi,1),%esi. This switch disables the 9708 optimization. 9709 9710`--divide' 9711 On SVR4-derived platforms, the character `/' is treated as a 9712 comment character, which means that it cannot be used in 9713 expressions. The `--divide' option turns `/' into a normal 9714 character. This does not disable `/' at the beginning of a line 9715 starting a comment, or affect using `#' for starting a comment. 9716 9717`-march=CPU[+EXTENSION...]' 9718 This option specifies the target processor. The assembler will 9719 issue an error message if an attempt is made to assemble an 9720 instruction which will not execute on the target processor. The 9721 following processor names are recognized: `i8086', `i186', `i286', 9722 `i386', `i486', `i586', `i686', `pentium', `pentiumpro', 9723 `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona', 9724 `core', `core2', `corei7', `l1om', `k6', `k6_2', `athlon', 9725 `opteron', `k8', `amdfam10', `bdver1', `generic32' and `generic64'. 9726 9727 In addition to the basic instruction set, the assembler can be 9728 told to accept various extension mnemonics. For example, 9729 `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The 9730 following extensions are currently supported: `8087', `287', `387', 9731 `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1', 9732 `sse4.2', `sse4', `nosse', `avx', `noavx', `vmx', `smx', `xsave', 9733 `xsaveopt', `aes', `pclmul', `fsgsbase', `rdrnd', `f16c', `fma', 9734 `movbe', `ept', `clflush', `lwp', `fma4', `xop', `syscall', 9735 `rdtscp', `3dnow', `3dnowa', `sse4a', `sse5', `svme', `abm' and 9736 `padlock'. Note that rather than extending a basic instruction 9737 set, the extension mnemonics starting with `no' revoke the 9738 respective functionality. 9739 9740 When the `.arch' directive is used with `-march', the `.arch' 9741 directive will take precedent. 9742 9743`-mtune=CPU' 9744 This option specifies a processor to optimize for. When used in 9745 conjunction with the `-march' option, only instructions of the 9746 processor specified by the `-march' option will be generated. 9747 9748 Valid CPU values are identical to the processor list of 9749 `-march=CPU'. 9750 9751`-msse2avx' 9752 This option specifies that the assembler should encode SSE 9753 instructions with VEX prefix. 9754 9755`-msse-check=NONE' 9756`-msse-check=WARNING' 9757`-msse-check=ERROR' 9758 These options control if the assembler should check SSE 9759 intructions. `-msse-check=NONE' will make the assembler not to 9760 check SSE instructions, which is the default. 9761 `-msse-check=WARNING' will make the assembler issue a warning for 9762 any SSE intruction. `-msse-check=ERROR' will make the assembler 9763 issue an error for any SSE intruction. 9764 9765`-mavxscalar=128' 9766`-mavxscalar=256' 9767 This options control how the assembler should encode scalar AVX 9768 instructions. `-mavxscalar=128' will encode scalar AVX 9769 instructions with 128bit vector length, which is the default. 9770 `-mavxscalar=256' will encode scalar AVX instructions with 256bit 9771 vector length. 9772 9773`-mmnemonic=ATT' 9774`-mmnemonic=INTEL' 9775 This option specifies instruction mnemonic for matching 9776 instructions. The `.att_mnemonic' and `.intel_mnemonic' 9777 directives will take precedent. 9778 9779`-msyntax=ATT' 9780`-msyntax=INTEL' 9781 This option specifies instruction syntax when processing 9782 instructions. The `.att_syntax' and `.intel_syntax' directives 9783 will take precedent. 9784 9785`-mnaked-reg' 9786 This opetion specifies that registers don't require a `%' prefix. 9787 The `.att_syntax' and `.intel_syntax' directives will take 9788 precedent. 9789 9790 9791 9792File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 9793 97949.13.2 x86 specific Directives 9795------------------------------ 9796 9797`.lcomm SYMBOL , LENGTH[, ALIGNMENT]' 9798 Reserve LENGTH (an absolute expression) bytes for a local common 9799 denoted by SYMBOL. The section and value of SYMBOL are those of 9800 the new local common. The addresses are allocated in the bss 9801 section, so that at run-time the bytes start off zeroed. Since 9802 SYMBOL is not declared global, it is normally not visible to `ld'. 9803 The optional third parameter, ALIGNMENT, specifies the desired 9804 alignment of the symbol in the bss section. 9805 9806 This directive is only available for COFF based x86 targets. 9807 9808 9809 9810File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 9811 98129.13.3 AT&T Syntax versus Intel Syntax 9813-------------------------------------- 9814 9815`as' now supports assembly using Intel assembler syntax. 9816`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to 9817the usual AT&T mode for compatibility with the output of `gcc'. Either 9818of these directives may have an optional argument, `prefix', or 9819`noprefix' specifying whether registers require a `%' prefix. AT&T 9820System V/386 assembler syntax is quite different from Intel syntax. We 9821mention these differences because almost all 80386 documents use Intel 9822syntax. Notable differences between the two syntaxes are: 9823 9824 * AT&T immediate operands are preceded by `$'; Intel immediate 9825 operands are undelimited (Intel `push 4' is AT&T `pushl $4'). 9826 AT&T register operands are preceded by `%'; Intel register operands 9827 are undelimited. AT&T absolute (as opposed to PC relative) 9828 jump/call operands are prefixed by `*'; they are undelimited in 9829 Intel syntax. 9830 9831 * AT&T and Intel syntax use the opposite order for source and 9832 destination operands. Intel `add eax, 4' is `addl $4, %eax'. The 9833 `source, dest' convention is maintained for compatibility with 9834 previous Unix assemblers. Note that `bound', `invlpga', and 9835 instructions with 2 immediate operands, such as the `enter' 9836 instruction, do _not_ have reversed order. *Note i386-Bugs::. 9837 9838 * In AT&T syntax the size of memory operands is determined from the 9839 last character of the instruction mnemonic. Mnemonic suffixes of 9840 `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long 9841 (32-bit) and quadruple word (64-bit) memory references. Intel 9842 syntax accomplishes this by prefixing memory operands (_not_ the 9843 instruction mnemonics) with `byte ptr', `word ptr', `dword ptr' 9844 and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO, 9845 %al' in AT&T syntax. 9846 9847 In 64-bit code, `movabs' can be used to encode the `mov' 9848 instruction with the 64-bit displacement or immediate operand. 9849 9850 * Immediate form long jumps and calls are `lcall/ljmp $SECTION, 9851 $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far 9852 SECTION:OFFSET'. Also, the far return instruction is `lret 9853 $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far 9854 STACK-ADJUST'. 9855 9856 * The AT&T assembler does not provide support for multiple section 9857 programs. Unix style systems expect all programs to be single 9858 sections. 9859 9860 9861File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 9862 98639.13.4 Instruction Naming 9864------------------------- 9865 9866Instruction mnemonics are suffixed with one character modifiers which 9867specify the size of operands. The letters `b', `w', `l' and `q' 9868specify byte, word, long and quadruple word operands. If no suffix is 9869specified by an instruction then `as' tries to fill in the missing 9870suffix based on the destination register operand (the last one by 9871convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; 9872also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is 9873incompatible with the AT&T Unix assembler which assumes that a missing 9874mnemonic suffix implies long operand size. (This incompatibility does 9875not affect compiler output since compilers always explicitly specify 9876the mnemonic suffix.) 9877 9878 Almost all instructions have the same names in AT&T and Intel format. 9879There are a few exceptions. The sign extend and zero extend 9880instructions need two sizes to specify them. They need a size to 9881sign/zero extend _from_ and a size to zero extend _to_. This is 9882accomplished by using two instruction mnemonic suffixes in AT&T syntax. 9883Base names for sign extend and zero extend are `movs...' and `movz...' 9884in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction 9885mnemonic suffixes are tacked on to this base name, the _from_ suffix 9886before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for 9887"move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are 9888`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to 9889long), `bq' (from byte to quadruple word), `wq' (from word to quadruple 9890word), and `lq' (from long to quadruple word). 9891 9892 Different encoding options can be specified via optional mnemonic 9893suffix. `.s' suffix swaps 2 register operands in encoding when moving 9894from one register to another. `.d32' suffix forces 32bit displacement 9895in encoding. 9896 9897 The Intel-syntax conversion instructions 9898 9899 * `cbw' -- sign-extend byte in `%al' to word in `%ax', 9900 9901 * `cwde' -- sign-extend word in `%ax' to long in `%eax', 9902 9903 * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax', 9904 9905 * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax', 9906 9907 * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64 9908 only), 9909 9910 * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax' 9911 (x86-64 only), 9912 9913are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T 9914naming. `as' accepts either naming for these instructions. 9915 9916 Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, 9917but are `call far' and `jump far' in Intel convention. 9918 99199.13.5 AT&T Mnemonic versus Intel Mnemonic 9920------------------------------------------ 9921 9922`as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects 9923Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to 9924the usual AT&T mnemonic with AT&T syntax for compatibility with the 9925output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp', 9926`fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are 9927implemented in AT&T System V/386 assembler with different mnemonics 9928from those in Intel IA32 specification. `gcc' generates those 9929instructions with AT&T mnemonic. 9930 9931 9932File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 9933 99349.13.6 Register Naming 9935---------------------- 9936 9937Register operands are always prefixed with `%'. The 80386 registers 9938consist of 9939 9940 * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', 9941 `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' 9942 (the stack pointer). 9943 9944 * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', 9945 `%si', `%bp', and `%sp'. 9946 9947 * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', 9948 `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', 9949 `%bx', `%cx', and `%dx') 9950 9951 * the 6 section registers `%cs' (code section), `%ds' (data 9952 section), `%ss' (stack section), `%es', `%fs', and `%gs'. 9953 9954 * the 3 processor control registers `%cr0', `%cr2', and `%cr3'. 9955 9956 * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and 9957 `%db7'. 9958 9959 * the 2 test registers `%tr6' and `%tr7'. 9960 9961 * the 8 floating point register stack `%st' or equivalently 9962 `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', 9963 `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX 9964 registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' 9965 and `%mm7'. 9966 9967 * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3', 9968 `%xmm4', `%xmm5', `%xmm6' and `%xmm7'. 9969 9970 The AMD x86-64 architecture extends the register set by: 9971 9972 * enhancing the 8 32-bit registers to 64-bit: `%rax' (the 9973 accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the 9974 frame pointer), `%rsp' (the stack pointer) 9975 9976 * the 8 extended registers `%r8'-`%r15'. 9977 9978 * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d' 9979 9980 * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w' 9981 9982 * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b' 9983 9984 * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'. 9985 9986 * the 8 debug registers: `%db8'-`%db15'. 9987 9988 * the 8 SSE registers: `%xmm8'-`%xmm15'. 9989 9990 9991File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 9992 99939.13.7 Instruction Prefixes 9994--------------------------- 9995 9996Instruction prefixes are used to modify the following instruction. They 9997are used to repeat string instructions, to provide section overrides, to 9998perform bus lock operations, and to change operand and address sizes. 9999(Most instructions that normally operate on 32-bit operands will use 1000016-bit operands if the instruction has an "operand size" prefix.) 10001Instruction prefixes are best written on the same line as the 10002instruction they act upon. For example, the `scas' (scan string) 10003instruction is repeated with: 10004 10005 repne scas %es:(%edi),%al 10006 10007 You may also place prefixes on the lines immediately preceding the 10008instruction, but this circumvents checks that `as' does with prefixes, 10009and will not work with all prefixes. 10010 10011 Here is a list of instruction prefixes: 10012 10013 * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. 10014 These are automatically added by specifying using the 10015 SECTION:MEMORY-OPERAND form for memory references. 10016 10017 * Operand/Address size prefixes `data16' and `addr16' change 32-bit 10018 operands/addresses into 16-bit operands/addresses, while `data32' 10019 and `addr32' change 16-bit ones (in a `.code16' section) into 10020 32-bit operands/addresses. These prefixes _must_ appear on the 10021 same line of code as the instruction they modify. For example, in 10022 a 16-bit `.code16' section, you might write: 10023 10024 addr32 jmpl *(%ebx) 10025 10026 * The bus lock prefix `lock' inhibits interrupts during execution of 10027 the instruction it precedes. (This is only valid with certain 10028 instructions; see a 80386 manual for details). 10029 10030 * The wait for coprocessor prefix `wait' waits for the coprocessor to 10031 complete the current instruction. This should never be needed for 10032 the 80386/80387 combination. 10033 10034 * The `rep', `repe', and `repne' prefixes are added to string 10035 instructions to make them repeat `%ecx' times (`%cx' times if the 10036 current address size is 16-bits). 10037 10038 * The `rex' family of prefixes is used by x86-64 to encode 10039 extensions to i386 instruction set. The `rex' prefix has four 10040 bits -- an operand size overwrite (`64') used to change operand 10041 size from 32-bit to 64-bit and X, Y and Z extensions bits used to 10042 extend the register set. 10043 10044 You may write the `rex' prefixes directly. The `rex64xyz' 10045 instruction emits `rex' prefix with all the bits set. By omitting 10046 the `64', `x', `y' or `z' you may write other prefixes as well. 10047 Normally, there is no need to write the prefixes explicitly, since 10048 gas will automatically generate them based on the instruction 10049 operands. 10050 10051 10052File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 10053 100549.13.8 Memory References 10055------------------------ 10056 10057An Intel syntax indirect memory reference of the form 10058 10059 SECTION:[BASE + INDEX*SCALE + DISP] 10060 10061is translated into the AT&T syntax 10062 10063 SECTION:DISP(BASE, INDEX, SCALE) 10064 10065where BASE and INDEX are the optional 32-bit base and index registers, 10066DISP is the optional displacement, and SCALE, taking the values 1, 2, 100674, and 8, multiplies INDEX to calculate the address of the operand. If 10068no SCALE is specified, SCALE is taken to be 1. SECTION specifies the 10069optional section register for the memory operand, and may override the 10070default section register (see a 80386 manual for section register 10071defaults). Note that section overrides in AT&T syntax _must_ be 10072preceded by a `%'. If you specify a section override which coincides 10073with the default section register, `as' does _not_ output any section 10074register override prefixes to assemble the given instruction. Thus, 10075section overrides can be specified to emphasize which section register 10076is used for a given memory operand. 10077 10078 Here are some examples of Intel and AT&T style memory references: 10079 10080AT&T: `-4(%ebp)', Intel: `[ebp - 4]' 10081 BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default 10082 section is used (`%ss' for addressing with `%ebp' as the base 10083 register). INDEX, SCALE are both missing. 10084 10085AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]' 10086 INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other 10087 fields are missing. The section register here defaults to `%ds'. 10088 10089AT&T: `foo(,1)'; Intel `[foo]' 10090 This uses the value pointed to by `foo' as a memory operand. Note 10091 that BASE and INDEX are both missing, but there is only _one_ `,'. 10092 This is a syntactic exception. 10093 10094AT&T: `%gs:foo'; Intel `gs:foo' 10095 This selects the contents of the variable `foo' with section 10096 register SECTION being `%gs'. 10097 10098 Absolute (as opposed to PC relative) call and jump operands must be 10099prefixed with `*'. If no `*' is specified, `as' always chooses PC 10100relative addressing for jump/call labels. 10101 10102 Any instruction that has a memory operand, but no register operand, 10103_must_ specify its size (byte, word, long, or quadruple) with an 10104instruction mnemonic suffix (`b', `w', `l' or `q', respectively). 10105 10106 The x86-64 architecture adds an RIP (instruction pointer relative) 10107addressing. This addressing mode is specified by using `rip' as a base 10108register. Only constant offsets are valid. For example: 10109 10110AT&T: `1234(%rip)', Intel: `[rip + 1234]' 10111 Points to the address 1234 bytes past the end of the current 10112 instruction. 10113 10114AT&T: `symbol(%rip)', Intel: `[rip + symbol]' 10115 Points to the `symbol' in RIP relative way, this is shorter than 10116 the default absolute addressing. 10117 10118 Other addressing modes remain unchanged in x86-64 architecture, 10119except registers used are 64-bit instead of 32-bit. 10120 10121 10122File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 10123 101249.13.9 Handling of Jump Instructions 10125------------------------------------ 10126 10127Jump instructions are always optimized to use the smallest possible 10128displacements. This is accomplished by using byte (8-bit) displacement 10129jumps whenever the target is sufficiently close. If a byte displacement 10130is insufficient a long displacement is used. We do not support word 10131(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 10132instruction with the `data16' instruction prefix), since the 80386 10133insists upon masking `%eip' to 16 bits after the word displacement is 10134added. (See also *note i386-Arch::) 10135 10136 Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' 10137and `loopne' instructions only come in byte displacements, so that if 10138you use these instructions (`gcc' does not use them) you may get an 10139error message (and incorrect code). The AT&T 80386 assembler tries to 10140get around this problem by expanding `jcxz foo' to 10141 10142 jcxz cx_zero 10143 jmp cx_nonzero 10144 cx_zero: jmp foo 10145 cx_nonzero: 10146 10147 10148File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 10149 101509.13.10 Floating Point 10151---------------------- 10152 10153All 80387 floating point types except packed BCD are supported. (BCD 10154support may be added without much difficulty). These data types are 1015516-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 10156and extended (80-bit) precision floating point. Each supported type 10157has an instruction mnemonic suffix and a constructor associated with 10158it. Instruction mnemonic suffixes specify the operand's data type. 10159Constructors build these data types into memory. 10160 10161 * Floating point constructors are `.float' or `.single', `.double', 10162 and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond 10163 to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 10164 80-bit (ten byte) real. The 80387 only supports this format via 10165 the `fldt' (load 80-bit real to stack top) and `fstpt' (store 10166 80-bit real and pop stack) instructions. 10167 10168 * Integer constructors are `.word', `.long' or `.int', and `.quad' 10169 for the 16-, 32-, and 64-bit integer formats. The corresponding 10170 instruction mnemonic suffixes are `s' (single), `l' (long), and 10171 `q' (quad). As with the 80-bit real format, the 64-bit `q' format 10172 is only present in the `fildq' (load quad integer to stack top) 10173 and `fistpq' (store quad integer and pop stack) instructions. 10174 10175 Register to register operations should not use instruction mnemonic 10176suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as 10177if you wrote `fst %st, %st(1)', since all register to register 10178operations use 80-bit floating point operands. (Contrast this with 10179`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating 10180point format, then stores the result in the 4 byte location `mem') 10181 10182 10183File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 10184 101859.13.11 Intel's MMX and AMD's 3DNow! SIMD Operations 10186---------------------------------------------------- 10187 10188`as' supports Intel's MMX instruction set (SIMD instructions for 10189integer data), available on Intel's Pentium MMX processors and Pentium 10190II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 10191probably others. It also supports AMD's 3DNow! instruction set (SIMD 10192instructions for 32-bit floating point data) available on AMD's K6-2 10193processor and possibly others in the future. 10194 10195 Currently, `as' does not support Intel's floating point SIMD, Katmai 10196(KNI). 10197 10198 The eight 64-bit MMX operands, also used by 3DNow!, are called 10199`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 1020016-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 10201floating point values. The MMX registers cannot be used at the same 10202time as the floating point stack. 10203 10204 See Intel and AMD documentation, keeping in mind that the operand 10205order in instructions is reversed from the Intel syntax. 10206 10207 10208File: as.info, Node: i386-LWP, Next: i386-16bit, Prev: i386-SIMD, Up: i386-Dependent 10209 102109.13.12 AMD's Lightweight Profiling Instructions 10211------------------------------------------------ 10212 10213`as' supports AMD's Lightweight Profiling (LWP) instruction set, 10214available on AMD's Family 15h (Orochi) processors. 10215 10216 LWP enables applications to collect and manage performance data, and 10217react to performance events. The collection of performance data 10218requires no context switches. LWP runs in the context of a thread and 10219so several counters can be used independently across multiple threads. 10220LWP can be used in both 64-bit and legacy 32-bit modes. 10221 10222 For detailed information on the LWP instruction set, see the `AMD 10223Lightweight Profiling Specification' available at Lightweight Profiling 10224Specification (http://developer.amd.com/cpu/LWP). 10225 10226 10227File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-LWP, Up: i386-Dependent 10228 102299.13.13 Writing 16-bit Code 10230--------------------------- 10231 10232While `as' normally writes only "pure" 32-bit i386 code or 64-bit 10233x86-64 code depending on the default configuration, it also supports 10234writing code to run in real mode or in 16-bit protected mode code 10235segments. To do this, put a `.code16' or `.code16gcc' directive before 10236the assembly language instructions to be run in 16-bit mode. You can 10237switch `as' to writing 32-bit code with the `.code32' directive or 1023864-bit code with the `.code64' directive. 10239 10240 `.code16gcc' provides experimental support for generating 16-bit 10241code from gcc, and differs from `.code16' in that `call', `ret', 10242`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' 10243instructions default to 32-bit size. This is so that the stack pointer 10244is manipulated in the same way over function calls, allowing access to 10245function parameters at the same stack offsets as in 32-bit mode. 10246`.code16gcc' also automatically adds address size prefixes where 10247necessary to use the 32-bit addressing modes that gcc generates. 10248 10249 The code which `as' generates in 16-bit mode will not necessarily 10250run on a 16-bit pre-80386 processor. To write code that runs on such a 10251processor, you must refrain from using _any_ 32-bit constructs which 10252require `as' to output address or operand size prefixes. 10253 10254 Note that writing 16-bit code instructions by explicitly specifying a 10255prefix or an instruction mnemonic suffix within a 32-bit code section 10256generates different machine instructions than those generated for a 1025716-bit code segment. In a 32-bit code section, the following code 10258generates the machine opcode bytes `66 6a 04', which pushes the value 10259`4' onto the stack, decrementing `%esp' by 2. 10260 10261 pushw $4 10262 10263 The same code in a 16-bit code section would generate the machine 10264opcode bytes `6a 04' (i.e., without the operand size prefix), which is 10265correct since the processor default operand size is assumed to be 16 10266bits in a 16-bit code section. 10267 10268 10269File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 10270 102719.13.14 AT&T Syntax bugs 10272------------------------ 10273 10274The UnixWare assembler, and probably other AT&T derived ix86 Unix 10275assemblers, generate floating point instructions with reversed source 10276and destination registers in certain cases. Unfortunately, gcc and 10277possibly many other programs use this reversed syntax, so we're stuck 10278with it. 10279 10280 For example 10281 10282 fsub %st,%st(3) 10283 results in `%st(3)' being updated to `%st - %st(3)' rather than the 10284expected `%st(3) - %st'. This happens with all the non-commutative 10285arithmetic floating point operations with two register operands where 10286the source register is `%st' and the destination register is `%st(i)'. 10287 10288 10289File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent 10290 102919.13.15 Specifying CPU Architecture 10292----------------------------------- 10293 10294`as' may be told to assemble for a particular CPU (sub-)architecture 10295with the `.arch CPU_TYPE' directive. This directive enables a warning 10296when gas detects an instruction that is not supported on the CPU 10297specified. The choices for CPU_TYPE are: 10298 10299`i8086' `i186' `i286' `i386' 10300`i486' `i586' `i686' `pentium' 10301`pentiumpro' `pentiumii' `pentiumiii' `pentium4' 10302`prescott' `nocona' `core' `core2' 10303`corei7' `l1om' 10304`k6' `k6_2' `athlon' `k8' 10305`amdfam10' `bdver1' 10306`generic32' `generic64' 10307`.mmx' `.sse' `.sse2' `.sse3' 10308`.ssse3' `.sse4.1' `.sse4.2' `.sse4' 10309`.avx' `.vmx' `.smx' `.ept' 10310`.clflush' `.movbe' `.xsave' `.xsaveopt' 10311`.aes' `.pclmul' `.fma' `.fsgsbase' 10312`.rdrnd' `.f16c' 10313`.3dnow' `.3dnowa' `.sse4a' `.sse5' 10314`.syscall' `.rdtscp' `.svme' `.abm' 10315`.lwp' `.fma4' `.xop' 10316`.padlock' 10317 10318 Apart from the warning, there are only two other effects on `as' 10319operation; Firstly, if you specify a CPU other than `i486', then shift 10320by one instructions such as `sarl $1, %eax' will automatically use a 10321two byte opcode sequence. The larger three byte opcode sequence is 10322used on the 486 (and when no architecture is specified) because it 10323executes faster on the 486. Note that you can explicitly request the 10324two byte opcode by writing `sarl %eax'. Secondly, if you specify 10325`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte 10326offset conditional jumps will be promoted when necessary to a two 10327instruction sequence consisting of a conditional jump of the opposite 10328sense around an unconditional jump to the target. 10329 10330 Following the CPU architecture (but not a sub-architecture, which 10331are those starting with a dot), you may specify `jumps' or `nojumps' to 10332control automatic promotion of conditional jumps. `jumps' is the 10333default, and enables jump promotion; All external jumps will be of the 10334long variety, and file-local jumps will be promoted as necessary. 10335(*note i386-Jumps::) `nojumps' leaves external conditional jumps as 10336byte offset jumps, and warns about file-local conditional jumps that 10337`as' promotes. Unconditional jumps are treated as for `jumps'. 10338 10339 For example 10340 10341 .arch i8086,nojumps 10342 10343 10344File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 10345 103469.13.16 Notes 10347------------- 10348 10349There is some trickery concerning the `mul' and `imul' instructions 10350that deserves mention. The 16-, 32-, 64- and 128-bit expanding 10351multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') 10352can be output only in the one operand form. Thus, `imul %ebx, %eax' 10353does _not_ select the expanding multiply; the expanding multiply would 10354clobber the `%edx' register, and this would confuse `gcc' output. Use 10355`imul %ebx' to get the 64-bit product in `%edx:%eax'. 10356 10357 We have added a two operand form of `imul' when the first operand is 10358an immediate mode expression and the second operand is a register. 10359This is just a shorthand, so that, multiplying `%eax' by 69, for 10360example, can be done with `imul $69, %eax' rather than `imul $69, %eax, 10361%eax'. 10362 10363 10364File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 10365 103669.14 Intel i860 Dependent Features 10367================================== 10368 10369* Menu: 10370 10371* Notes-i860:: i860 Notes 10372* Options-i860:: i860 Command-line Options 10373* Directives-i860:: i860 Machine Directives 10374* Opcodes for i860:: i860 Opcodes 10375 10376 10377File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent 10378 103799.14.1 i860 Notes 10380----------------- 10381 10382This is a fairly complete i860 assembler which is compatible with the 10383UNIX System V/860 Release 4 assembler. However, it does not currently 10384support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT'). 10385 10386 Like the SVR4/860 assembler, the output object format is ELF32. 10387Currently, this is the only supported object format. If there is 10388sufficient interest, other formats such as COFF may be implemented. 10389 10390 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 10391being the default. One difference is that AT&T syntax requires the '%' 10392prefix on register names while Intel syntax does not. Another 10393difference is in the specification of relocatable expressions. The 10394Intel syntax is `ha%expression' whereas the SVR4 syntax is 10395`[expression]@ha' (and similarly for the "l" and "h" selectors). 10396 10397 10398File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent 10399 104009.14.2 i860 Command-line Options 10401-------------------------------- 10402 104039.14.2.1 SVR4 compatibility options 10404................................... 10405 10406`-V' 10407 Print assembler version. 10408 10409`-Qy' 10410 Ignored. 10411 10412`-Qn' 10413 Ignored. 10414 104159.14.2.2 Other options 10416...................... 10417 10418`-EL' 10419 Select little endian output (this is the default). 10420 10421`-EB' 10422 Select big endian output. Note that the i860 always reads 10423 instructions as little endian data, so this option only effects 10424 data and not instructions. 10425 10426`-mwarn-expand' 10427 Emit a warning message if any pseudo-instruction expansions 10428 occurred. For example, a `or' instruction with an immediate 10429 larger than 16-bits will be expanded into two instructions. This 10430 is a very undesirable feature to rely on, so this flag can help 10431 detect any code where it happens. One use of it, for instance, has 10432 been to find and eliminate any place where `gcc' may emit these 10433 pseudo-instructions. 10434 10435`-mxp' 10436 Enable support for the i860XP instructions and control registers. 10437 By default, this option is disabled so that only the base 10438 instruction set (i.e., i860XR) is supported. 10439 10440`-mintel-syntax' 10441 The i860 assembler defaults to AT&T/SVR4 syntax. This option 10442 enables the Intel syntax. 10443 10444 10445File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent 10446 104479.14.3 i860 Machine Directives 10448------------------------------ 10449 10450`.dual' 10451 Enter dual instruction mode. While this directive is supported, the 10452 preferred way to use dual instruction mode is to explicitly code 10453 the dual bit with the `d.' prefix. 10454 10455`.enddual' 10456 Exit dual instruction mode. While this directive is supported, the 10457 preferred way to use dual instruction mode is to explicitly code 10458 the dual bit with the `d.' prefix. 10459 10460`.atmp' 10461 Change the temporary register used when expanding pseudo 10462 operations. The default register is `r31'. 10463 10464 The `.dual', `.enddual', and `.atmp' directives are available only 10465in the Intel syntax mode. 10466 10467 Both syntaxes allow for the standard `.align' directive. However, 10468the Intel syntax additionally allows keywords for the alignment 10469parameter: "`.align type'", where `type' is one of `.short', `.long', 10470`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4, 10471and 8, respectively. 10472 10473 10474File: as.info, Node: Opcodes for i860, Prev: Directives-i860, Up: i860-Dependent 10475 104769.14.4 i860 Opcodes 10477------------------- 10478 10479All of the Intel i860XR and i860XP machine instructions are supported. 10480Please see either _i860 Microprocessor Programmer's Reference Manual_ 10481or _i860 Microprocessor Architecture_ for more information. 10482 104839.14.4.1 Other instruction support (pseudo-instructions) 10484........................................................ 10485 10486For compatibility with some other i860 assemblers, a number of 10487pseudo-instructions are supported. While these are supported, they are 10488a very undesirable feature that should be avoided - in particular, when 10489they result in an expansion to multiple actual i860 instructions. Below 10490are the pseudo-instructions that result in expansions. 10491 * Load large immediate into general register: 10492 10493 The pseudo-instruction `mov imm,%rn' (where the immediate does not 10494 fit within a signed 16-bit field) will be expanded into: 10495 orh large_imm@h,%r0,%rn 10496 or large_imm@l,%rn,%rn 10497 10498 * Load/store with relocatable address expression: 10499 10500 For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will 10501 be expanded into: 10502 orh addr_exp@ha,%rx,%r31 10503 ld.l addr_exp@l(%r31),%rn 10504 10505 The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, 10506 fst.x', and `pst.x' as well. 10507 10508 * Signed large immediate with add/subtract: 10509 10510 If any of the arithmetic operations `adds, addu, subs, subu' are 10511 used with an immediate larger than 16-bits (signed), then they 10512 will be expanded. For instance, the pseudo-instruction `adds 10513 large_imm,%rx,%rn' expands to: 10514 orh large_imm@h,%r0,%r31 10515 or large_imm@l,%r31,%r31 10516 adds %r31,%rx,%rn 10517 10518 * Unsigned large immediate with logical operations: 10519 10520 Logical operations (`or, andnot, or, xor') also result in 10521 expansions. The pseudo-instruction `or large_imm,%rx,%rn' results 10522 in: 10523 orh large_imm@h,%rx,%r31 10524 or large_imm@l,%r31,%rn 10525 10526 Similarly for the others, except for `and' which expands to: 10527 andnot (-1 - large_imm)@h,%rx,%r31 10528 andnot (-1 - large_imm)@l,%r31,%rn 10529 10530 10531File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies 10532 105339.15 Intel 80960 Dependent Features 10534=================================== 10535 10536* Menu: 10537 10538* Options-i960:: i960 Command-line Options 10539* Floating Point-i960:: Floating Point 10540* Directives-i960:: i960 Machine Directives 10541* Opcodes for i960:: i960 Opcodes 10542 10543 10544File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent 10545 105469.15.1 i960 Command-line Options 10547-------------------------------- 10548 10549`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 10550 Select the 80960 architecture. Instructions or features not 10551 supported by the selected architecture cause fatal errors. 10552 10553 `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. 10554 Synonyms are provided for compatibility with other tools. 10555 10556 If you do not specify any of these options, `as' generates code 10557 for any instruction or feature that is supported by _some_ version 10558 of the 960 (even if this means mixing architectures!). In 10559 principle, `as' attempts to deduce the minimal sufficient 10560 processor type if none is specified; depending on the object code 10561 format, the processor type may be recorded in the object file. If 10562 it is critical that the `as' output match a specific architecture, 10563 specify that architecture explicitly. 10564 10565`-b' 10566 Add code to collect information about conditional branches taken, 10567 for later optimization using branch prediction bits. (The 10568 conditional branch instructions have branch prediction bits in the 10569 CA, CB, and CC architectures.) If BR represents a conditional 10570 branch instruction, the following represents the code generated by 10571 the assembler when `-b' is specified: 10572 10573 call INCREMENT ROUTINE 10574 .word 0 # pre-counter 10575 Label: BR 10576 call INCREMENT ROUTINE 10577 .word 0 # post-counter 10578 10579 The counter following a branch records the number of times that 10580 branch was _not_ taken; the difference between the two counters is 10581 the number of times the branch _was_ taken. 10582 10583 A table of every such `Label' is also generated, so that the 10584 external postprocessor `gbr960' (supplied by Intel) can locate all 10585 the counters. This table is always labeled `__BRANCH_TABLE__'; 10586 this is a local symbol to permit collecting statistics for many 10587 separate object files. The table is word aligned, and begins with 10588 a two-word header. The first word, initialized to 0, is used in 10589 maintaining linked lists of branch tables. The second word is a 10590 count of the number of entries in the table, which follow 10591 immediately: each is a word, pointing to one of the labels 10592 illustrated above. 10593 10594 +------------+------------+------------+ ... +------------+ 10595 | | | | | | 10596 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | 10597 | | | | | | 10598 +------------+------------+------------+ ... +------------+ 10599 10600 __BRANCH_TABLE__ layout 10601 10602 The first word of the header is used to locate multiple branch 10603 tables, since each object file may contain one. Normally the links 10604 are maintained with a call to an initialization routine, placed at 10605 the beginning of each function in the file. The GNU C compiler 10606 generates these calls automatically when you give it a `-b' option. 10607 For further details, see the documentation of `gbr960'. 10608 10609`-no-relax' 10610 Normally, Compare-and-Branch instructions with targets that require 10611 displacements greater than 13 bits (or that have external targets) 10612 are replaced with the corresponding compare (or `chkbit') and 10613 branch instructions. You can use the `-no-relax' option to 10614 specify that `as' should generate errors instead, if the target 10615 displacement is larger than 13 bits. 10616 10617 This option does not affect the Compare-and-Jump instructions; the 10618 code emitted for them is _always_ adjusted when necessary 10619 (depending on displacement size), regardless of whether you use 10620 `-no-relax'. 10621 10622 10623File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent 10624 106259.15.2 Floating Point 10626--------------------- 10627 10628`as' generates IEEE floating-point numbers for the directives `.float', 10629`.double', `.extended', and `.single'. 10630 10631 10632File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent 10633 106349.15.3 i960 Machine Directives 10635------------------------------ 10636 10637`.bss SYMBOL, LENGTH, ALIGN' 10638 Reserve LENGTH bytes in the bss section for a local SYMBOL, 10639 aligned to the power of two specified by ALIGN. LENGTH and ALIGN 10640 must be positive absolute expressions. This directive differs 10641 from `.lcomm' only in that it permits you to specify an alignment. 10642 *Note `.lcomm': Lcomm. 10643 10644`.extended FLONUMS' 10645 `.extended' expects zero or more flonums, separated by commas; for 10646 each flonum, `.extended' emits an IEEE extended-format (80-bit) 10647 floating-point number. 10648 10649`.leafproc CALL-LAB, BAL-LAB' 10650 You can use the `.leafproc' directive in conjunction with the 10651 optimized `callj' instruction to enable faster calls of leaf 10652 procedures. If a procedure is known to call no other procedures, 10653 you may define an entry point that skips procedure prolog code 10654 (and that does not depend on system-supplied saved context), and 10655 declare it as the BAL-LAB using `.leafproc'. If the procedure 10656 also has an entry point that goes through the normal prolog, you 10657 can specify that entry point as CALL-LAB. 10658 10659 A `.leafproc' declaration is meant for use in conjunction with the 10660 optimized call instruction `callj'; the directive records the data 10661 needed later to choose between converting the `callj' into a `bal' 10662 or a `call'. 10663 10664 CALL-LAB is optional; if only one argument is present, or if the 10665 two arguments are identical, the single argument is assumed to be 10666 the `bal' entry point. 10667 10668`.sysproc NAME, INDEX' 10669 The `.sysproc' directive defines a name for a system procedure. 10670 After you define it using `.sysproc', you can use NAME to refer to 10671 the system procedure identified by INDEX when calling procedures 10672 with the optimized call instruction `callj'. 10673 10674 Both arguments are required; INDEX must be between 0 and 31 10675 (inclusive). 10676 10677 10678File: as.info, Node: Opcodes for i960, Prev: Directives-i960, Up: i960-Dependent 10679 106809.15.4 i960 Opcodes 10681------------------- 10682 10683All Intel 960 machine instructions are supported; *note i960 10684Command-line Options: Options-i960. for a discussion of selecting the 10685instruction subset for a particular 960 architecture. 10686 10687 Some opcodes are processed beyond simply emitting a single 10688corresponding instruction: `callj', and Compare-and-Branch or 10689Compare-and-Jump instructions with target displacements larger than 13 10690bits. 10691 10692* Menu: 10693 10694* callj-i960:: `callj' 10695* Compare-and-branch-i960:: Compare-and-Branch 10696 10697 10698File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 10699 107009.15.4.1 `callj' 10701................ 10702 10703You can write `callj' to have the assembler or the linker determine the 10704most appropriate form of subroutine call: `call', `bal', or `calls'. 10705If the assembly source contains enough information--a `.leafproc' or 10706`.sysproc' directive defining the operand--then `as' translates the 10707`callj'; if not, it simply emits the `callj', leaving it for the linker 10708to resolve. 10709 10710 10711File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 10712 107139.15.4.2 Compare-and-Branch 10714........................... 10715 10716The 960 architectures provide combined Compare-and-Branch instructions 10717that permit you to store the branch target in the lower 13 bits of the 10718instruction word itself. However, if you specify a branch target far 10719enough away that its address won't fit in 13 bits, the assembler can 10720either issue an error, or convert your Compare-and-Branch instruction 10721into separate instructions to do the compare and the branch. 10722 10723 Whether `as' gives an error or expands the instruction depends on 10724two choices you can make: whether you use the `-no-relax' option, and 10725whether you use a "Compare and Branch" instruction or a "Compare and 10726Jump" instruction. The "Jump" instructions are _always_ expanded if 10727necessary; the "Branch" instructions are expanded when necessary 10728_unless_ you specify `-no-relax'--in which case `as' gives an error 10729instead. 10730 10731 These are the Compare-and-Branch instructions, their "Jump" variants, 10732and the instruction pairs they may expand into: 10733 10734 Compare and 10735 Branch Jump Expanded to 10736 ------ ------ ------------ 10737 bbc chkbit; bno 10738 bbs chkbit; bo 10739 cmpibe cmpije cmpi; be 10740 cmpibg cmpijg cmpi; bg 10741 cmpibge cmpijge cmpi; bge 10742 cmpibl cmpijl cmpi; bl 10743 cmpible cmpijle cmpi; ble 10744 cmpibno cmpijno cmpi; bno 10745 cmpibne cmpijne cmpi; bne 10746 cmpibo cmpijo cmpi; bo 10747 cmpobe cmpoje cmpo; be 10748 cmpobg cmpojg cmpo; bg 10749 cmpobge cmpojge cmpo; bge 10750 cmpobl cmpojl cmpo; bl 10751 cmpoble cmpojle cmpo; ble 10752 cmpobne cmpojne cmpo; bne 10753 10754 10755File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies 10756 107579.16 IA-64 Dependent Features 10758============================= 10759 10760* Menu: 10761 10762* IA-64 Options:: Options 10763* IA-64 Syntax:: Syntax 10764* IA-64 Opcodes:: Opcodes 10765 10766 10767File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 10768 107699.16.1 Options 10770-------------- 10771 10772`-mconstant-gp' 10773 This option instructs the assembler to mark the resulting object 10774 file as using the "constant GP" model. With this model, it is 10775 assumed that the entire program uses a single global pointer (GP) 10776 value. Note that this option does not in any fashion affect the 10777 machine code emitted by the assembler. All it does is turn on the 10778 EF_IA_64_CONS_GP flag in the ELF file header. 10779 10780`-mauto-pic' 10781 This option instructs the assembler to mark the resulting object 10782 file as using the "constant GP without function descriptor" data 10783 model. This model is like the "constant GP" model, except that it 10784 additionally does away with function descriptors. What this means 10785 is that the address of a function refers directly to the 10786 function's code entry-point. Normally, such an address would 10787 refer to a function descriptor, which contains both the code 10788 entry-point and the GP-value needed by the function. Note that 10789 this option does not in any fashion affect the machine code 10790 emitted by the assembler. All it does is turn on the 10791 EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. 10792 10793`-milp32' 10794`-milp64' 10795`-mlp64' 10796`-mp64' 10797 These options select the data model. The assembler defaults to 10798 `-mlp64' (LP64 data model). 10799 10800`-mle' 10801`-mbe' 10802 These options select the byte order. The `-mle' option selects 10803 little-endian byte order (default) and `-mbe' selects big-endian 10804 byte order. Note that IA-64 machine code always uses 10805 little-endian byte order. 10806 10807`-mtune=itanium1' 10808`-mtune=itanium2' 10809 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 10810 is ITANIUM2. 10811 10812`-munwind-check=warning' 10813`-munwind-check=error' 10814 These options control what the assembler will do when performing 10815 consistency checks on unwind directives. `-munwind-check=warning' 10816 will make the assembler issue a warning when an unwind directive 10817 check fails. This is the default. `-munwind-check=error' will 10818 make the assembler issue an error when an unwind directive check 10819 fails. 10820 10821`-mhint.b=ok' 10822`-mhint.b=warning' 10823`-mhint.b=error' 10824 These options control what the assembler will do when the `hint.b' 10825 instruction is used. `-mhint.b=ok' will make the assembler accept 10826 `hint.b'. `-mint.b=warning' will make the assembler issue a 10827 warning when `hint.b' is used. `-mhint.b=error' will make the 10828 assembler treat `hint.b' as an error, which is the default. 10829 10830`-x' 10831`-xexplicit' 10832 These options turn on dependency violation checking. 10833 10834`-xauto' 10835 This option instructs the assembler to automatically insert stop 10836 bits where necessary to remove dependency violations. This is the 10837 default mode. 10838 10839`-xnone' 10840 This option turns off dependency violation checking. 10841 10842`-xdebug' 10843 This turns on debug output intended to help tracking down bugs in 10844 the dependency violation checker. 10845 10846`-xdebugn' 10847 This is a shortcut for -xnone -xdebug. 10848 10849`-xdebugx' 10850 This is a shortcut for -xexplicit -xdebug. 10851 10852 10853 10854File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 10855 108569.16.2 Syntax 10857------------- 10858 10859The assembler syntax closely follows the IA-64 Assembly Language 10860Reference Guide. 10861 10862* Menu: 10863 10864* IA-64-Chars:: Special Characters 10865* IA-64-Regs:: Register Names 10866* IA-64-Bits:: Bit Names 10867* IA-64-Relocs:: Relocations 10868 10869 10870File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 10871 108729.16.2.1 Special Characters 10873........................... 10874 10875`//' is the line comment token. 10876 10877 `;' can be used instead of a newline to separate statements. 10878 10879 10880File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 10881 108829.16.2.2 Register Names 10883....................... 10884 10885The 128 integer registers are referred to as `rN'. The 128 10886floating-point registers are referred to as `fN'. The 128 application 10887registers are referred to as `arN'. The 128 control registers are 10888referred to as `crN'. The 64 one-bit predicate registers are referred 10889to as `pN'. The 8 branch registers are referred to as `bN'. In 10890addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' 10891(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), 10892`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). 10893 10894 For convenience, the assembler also defines aliases for all named 10895application and control registers. For example, `ar.bsp' refers to the 10896register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to 10897the end-of-interrupt register (`cr67'). 10898 10899 10900File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 10901 109029.16.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 10903........................................................ 10904 10905The assembler defines bit masks for each of the bits in the IA-64 10906processor status register. For example, `psr.ic' corresponds to a 10907value of 0x2000. These masks are primarily intended for use with the 10908`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere 10909else where an integer constant is expected. 10910 10911 10912File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 10913 109149.16.2.4 Relocations 10915.................... 10916 10917In addition to the standard IA-64 relocations, the following 10918relocations are implemented by `as': 10919 10920`@slotcount(V)' 10921 Convert the address offset V into a slot count. This pseudo 10922 function is available only on VMS. The expression V must be known 10923 at assembly time: it can't reference undefined symbols or symbols 10924 in different sections. 10925 10926 10927File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 10928 109299.16.3 Opcodes 10930-------------- 10931 10932For detailed information on the IA-64 machine instruction set, see the 10933IA-64 Architecture Handbook 10934(http://developer.intel.com/design/itanium/arch_spec.htm). 10935 10936 10937File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 10938 109399.17 IP2K Dependent Features 10940============================ 10941 10942* Menu: 10943 10944* IP2K-Opts:: IP2K Options 10945 10946 10947File: as.info, Node: IP2K-Opts, Up: IP2K-Dependent 10948 109499.17.1 IP2K Options 10950------------------- 10951 10952The Ubicom IP2K version of `as' has a few machine dependent options: 10953 10954`-mip2022ext' 10955 `as' can assemble the extended IP2022 instructions, but it will 10956 only do so if this is specifically allowed via this command line 10957 option. 10958 10959`-mip2022' 10960 This option restores the assembler's default behaviour of not 10961 permitting the extended IP2022 instructions to be assembled. 10962 10963 10964 10965File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 10966 109679.18 LM32 Dependent Features 10968============================ 10969 10970* Menu: 10971 10972* LM32 Options:: Options 10973* LM32 Syntax:: Syntax 10974* LM32 Opcodes:: Opcodes 10975 10976 10977File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 10978 109799.18.1 Options 10980-------------- 10981 10982`-mmultiply-enabled' 10983 Enable multiply instructions. 10984 10985`-mdivide-enabled' 10986 Enable divide instructions. 10987 10988`-mbarrel-shift-enabled' 10989 Enable barrel-shift instructions. 10990 10991`-msign-extend-enabled' 10992 Enable sign extend instructions. 10993 10994`-muser-enabled' 10995 Enable user defined instructions. 10996 10997`-micache-enabled' 10998 Enable instruction cache related CSRs. 10999 11000`-mdcache-enabled' 11001 Enable data cache related CSRs. 11002 11003`-mbreak-enabled' 11004 Enable break instructions. 11005 11006`-mall-enabled' 11007 Enable all instructions and CSRs. 11008 11009 11010 11011File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 11012 110139.18.2 Syntax 11014------------- 11015 11016* Menu: 11017 11018* LM32-Regs:: Register Names 11019* LM32-Modifiers:: Relocatable Expression Modifiers 11020 11021 11022File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 11023 110249.18.2.1 Register Names 11025....................... 11026 11027LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'. 11028 11029 The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp' 11030- `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'. 11031 11032 LM32 has the following Control and Status Registers (CSRs). 11033 11034`IE' 11035 Interrupt enable. 11036 11037`IM' 11038 Interrupt mask. 11039 11040`IP' 11041 Interrupt pending. 11042 11043`ICC' 11044 Instruction cache control. 11045 11046`DCC' 11047 Data cache control. 11048 11049`CC' 11050 Cycle counter. 11051 11052`CFG' 11053 Configuration. 11054 11055`EBA' 11056 Exception base address. 11057 11058`DC' 11059 Debug control. 11060 11061`DEBA' 11062 Debug exception base address. 11063 11064`JTX' 11065 JTAG transmit. 11066 11067`JRX' 11068 JTAG receive. 11069 11070`BP0' 11071 Breakpoint 0. 11072 11073`BP1' 11074 Breakpoint 1. 11075 11076`BP2' 11077 Breakpoint 2. 11078 11079`BP3' 11080 Breakpoint 3. 11081 11082`WP0' 11083 Watchpoint 0. 11084 11085`WP1' 11086 Watchpoint 1. 11087 11088`WP2' 11089 Watchpoint 2. 11090 11091`WP3' 11092 Watchpoint 3. 11093 11094 11095File: as.info, Node: LM32-Modifiers, Prev: LM32-Regs, Up: LM32 Syntax 11096 110979.18.2.2 Relocatable Expression Modifiers 11098......................................... 11099 11100The assembler supports several modifiers when using relocatable 11101addresses in LM32 instruction operands. The general syntax is the 11102following: 11103 11104 modifier(relocatable-expression) 11105 11106`lo' 11107 This modifier allows you to use bits 0 through 15 of an address 11108 expression as 16 bit relocatable expression. 11109 11110`hi' 11111 This modifier allows you to use bits 16 through 23 of an address 11112 expression as 16 bit relocatable expression. 11113 11114 For example 11115 11116 ori r4, r4, lo(sym+10) 11117 orhi r4, r4, hi(sym+10) 11118 11119`gp' 11120 This modified creates a 16-bit relocatable expression that is the 11121 offset of the symbol from the global pointer. 11122 11123 mva r4, gp(sym) 11124 11125`got' 11126 This modifier places a symbol in the GOT and creates a 16-bit 11127 relocatable expression that is the offset into the GOT of this 11128 symbol. 11129 11130 lw r4, (gp+got(sym)) 11131 11132`gotofflo16' 11133 This modifier allows you to use the bits 0 through 15 of an 11134 address which is an offset from the GOT. 11135 11136`gotoffhi16' 11137 This modifier allows you to use the bits 16 through 31 of an 11138 address which is an offset from the GOT. 11139 11140 orhi r4, r4, gotoffhi16(lsym) 11141 addi r4, r4, gotofflo16(lsym) 11142 11143 11144 11145File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 11146 111479.18.3 Opcodes 11148-------------- 11149 11150For detailed information on the LM32 machine instruction set, see 11151`http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'. 11152 11153 `as' implements all the standard LM32 opcodes. 11154 11155 11156File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 11157 111589.19 M32C Dependent Features 11159============================ 11160 11161 `as' can assemble code for several different members of the Renesas 11162M32C family. Normally the default is to assemble code for the M16C 11163microprocessor. The `-m32c' option may be used to change the default 11164to the M32C microprocessor. 11165 11166* Menu: 11167 11168* M32C-Opts:: M32C Options 11169* M32C-Modifiers:: Symbolic Operand Modifiers 11170 11171 11172File: as.info, Node: M32C-Opts, Next: M32C-Modifiers, Up: M32C-Dependent 11173 111749.19.1 M32C Options 11175------------------- 11176 11177The Renesas M32C version of `as' has these machine-dependent options: 11178 11179`-m32c' 11180 Assemble M32C instructions. 11181 11182`-m16c' 11183 Assemble M16C instructions (default). 11184 11185`-relax' 11186 Enable support for link-time relaxations. 11187 11188`-h-tick-hex' 11189 Support H'00 style hex constants in addition to 0x00 style. 11190 11191 11192 11193File: as.info, Node: M32C-Modifiers, Prev: M32C-Opts, Up: M32C-Dependent 11194 111959.19.2 Symbolic Operand Modifiers 11196--------------------------------- 11197 11198The assembler supports several modifiers when using symbol addresses in 11199M32C instruction operands. The general syntax is the following: 11200 11201 %modifier(symbol) 11202 11203`%dsp8' 11204`%dsp16' 11205 These modifiers override the assembler's assumptions about how big 11206 a symbol's address is. Normally, when it sees an operand like 11207 `sym[a0]' it assumes `sym' may require the widest displacement 11208 field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers 11209 tell it to assume the address will fit in an 8 or 16 bit 11210 (respectively) unsigned displacement. Note that, of course, if it 11211 doesn't actually fit you will get linker errors. Example: 11212 11213 mov.w %dsp8(sym)[a0],r1 11214 mov.b #0,%dsp8(sym)[a0] 11215 11216`%hi8' 11217 This modifier allows you to load bits 16 through 23 of a 24 bit 11218 address into an 8 bit register. This is useful with, for example, 11219 the M16C `smovf' instruction, which expects a 20 bit address in 11220 `r1h' and `a0'. Example: 11221 11222 mov.b #%hi8(sym),r1h 11223 mov.w #%lo16(sym),a0 11224 smovf.b 11225 11226`%lo16' 11227 Likewise, this modifier allows you to load bits 0 through 15 of a 11228 24 bit address into a 16 bit register. 11229 11230`%hi16' 11231 This modifier allows you to load bits 16 through 31 of a 32 bit 11232 address into a 16 bit register. While the M32C family only has 24 11233 bits of address space, it does support addresses in pairs of 16 bit 11234 registers (like `a1a0' for the `lde' instruction). This modifier 11235 is for loading the upper half in such cases. Example: 11236 11237 mov.w #%hi16(sym),a1 11238 mov.w #%lo16(sym),a0 11239 ... 11240 lde.w [a1a0],r1 11241 11242 11243 11244File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 11245 112469.20 M32R Dependent Features 11247============================ 11248 11249* Menu: 11250 11251* M32R-Opts:: M32R Options 11252* M32R-Directives:: M32R Directives 11253* M32R-Warnings:: M32R Warnings 11254 11255 11256File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 11257 112589.20.1 M32R Options 11259------------------- 11260 11261The Renease M32R version of `as' has a few machine dependent options: 11262 11263`-m32rx' 11264 `as' can assemble code for several different members of the 11265 Renesas M32R family. Normally the default is to assemble code for 11266 the M32R microprocessor. This option may be used to change the 11267 default to the M32RX microprocessor, which adds some more 11268 instructions to the basic M32R instruction set, and some 11269 additional parameters to some of the original instructions. 11270 11271`-m32r2' 11272 This option changes the target processor to the the M32R2 11273 microprocessor. 11274 11275`-m32r' 11276 This option can be used to restore the assembler's default 11277 behaviour of assembling for the M32R microprocessor. This can be 11278 useful if the default has been changed by a previous command line 11279 option. 11280 11281`-little' 11282 This option tells the assembler to produce little-endian code and 11283 data. The default is dependent upon how the toolchain was 11284 configured. 11285 11286`-EL' 11287 This is a synonym for _-little_. 11288 11289`-big' 11290 This option tells the assembler to produce big-endian code and 11291 data. 11292 11293`-EB' 11294 This is a synonum for _-big_. 11295 11296`-KPIC' 11297 This option specifies that the output of the assembler should be 11298 marked as position-independent code (PIC). 11299 11300`-parallel' 11301 This option tells the assembler to attempts to combine two 11302 sequential instructions into a single, parallel instruction, where 11303 it is legal to do so. 11304 11305`-no-parallel' 11306 This option disables a previously enabled _-parallel_ option. 11307 11308`-no-bitinst' 11309 This option disables the support for the extended bit-field 11310 instructions provided by the M32R2. If this support needs to be 11311 re-enabled the _-bitinst_ switch can be used to restore it. 11312 11313`-O' 11314 This option tells the assembler to attempt to optimize the 11315 instructions that it produces. This includes filling delay slots 11316 and converting sequential instructions into parallel ones. This 11317 option implies _-parallel_. 11318 11319`-warn-explicit-parallel-conflicts' 11320 Instructs `as' to produce warning messages when questionable 11321 parallel instructions are encountered. This option is enabled by 11322 default, but `gcc' disables it when it invokes `as' directly. 11323 Questionable instructions are those whose behaviour would be 11324 different if they were executed sequentially. For example the 11325 code fragment `mv r1, r2 || mv r3, r1' produces a different result 11326 from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 11327 and then r2 into r1, whereas the later moves r2 into r1 and r3. 11328 11329`-Wp' 11330 This is a shorter synonym for the 11331 _-warn-explicit-parallel-conflicts_ option. 11332 11333`-no-warn-explicit-parallel-conflicts' 11334 Instructs `as' not to produce warning messages when questionable 11335 parallel instructions are encountered. 11336 11337`-Wnp' 11338 This is a shorter synonym for the 11339 _-no-warn-explicit-parallel-conflicts_ option. 11340 11341`-ignore-parallel-conflicts' 11342 This option tells the assembler's to stop checking parallel 11343 instructions for constraint violations. This ability is provided 11344 for hardware vendors testing chip designs and should not be used 11345 under normal circumstances. 11346 11347`-no-ignore-parallel-conflicts' 11348 This option restores the assembler's default behaviour of checking 11349 parallel instructions to detect constraint violations. 11350 11351`-Ip' 11352 This is a shorter synonym for the _-ignore-parallel-conflicts_ 11353 option. 11354 11355`-nIp' 11356 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 11357 option. 11358 11359`-warn-unmatched-high' 11360 This option tells the assembler to produce a warning message if a 11361 `.high' pseudo op is encountered without a matching `.low' pseudo 11362 op. The presence of such an unmatched pseudo op usually indicates 11363 a programming error. 11364 11365`-no-warn-unmatched-high' 11366 Disables a previously enabled _-warn-unmatched-high_ option. 11367 11368`-Wuh' 11369 This is a shorter synonym for the _-warn-unmatched-high_ option. 11370 11371`-Wnuh' 11372 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 11373 11374 11375 11376File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 11377 113789.20.2 M32R Directives 11379---------------------- 11380 11381The Renease M32R version of `as' has a few architecture specific 11382directives: 11383 11384`low EXPRESSION' 11385 The `low' directive computes the value of its expression and 11386 places the lower 16-bits of the result into the immediate-field of 11387 the instruction. For example: 11388 11389 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 11390 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 11391 11392`high EXPRESSION' 11393 The `high' directive computes the value of its expression and 11394 places the upper 16-bits of the result into the immediate-field of 11395 the instruction. For example: 11396 11397 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 11398 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 11399 11400`shigh EXPRESSION' 11401 The `shigh' directive is very similar to the `high' directive. It 11402 also computes the value of its expression and places the upper 11403 16-bits of the result into the immediate-field of the instruction. 11404 The difference is that `shigh' also checks to see if the lower 11405 16-bits could be interpreted as a signed number, and if so it 11406 assumes that a borrow will occur from the upper-16 bits. To 11407 compensate for this the `shigh' directive pre-biases the upper 16 11408 bit value by adding one to it. For example: 11409 11410 For example: 11411 11412 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 11413 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 11414 11415 In the second example the lower 16-bits are 0x8000. If these are 11416 treated as a signed value and sign extended to 32-bits then the 11417 value becomes 0xffff8000. If this value is then added to 11418 0x00010000 then the result is 0x00008000. 11419 11420 This behaviour is to allow for the different semantics of the 11421 `or3' and `add3' instructions. The `or3' instruction treats its 11422 16-bit immediate argument as unsigned whereas the `add3' treats 11423 its 16-bit immediate as a signed value. So for example: 11424 11425 seth r0, #shigh(0x00008000) 11426 add3 r0, r0, #low(0x00008000) 11427 11428 Produces the correct result in r0, whereas: 11429 11430 seth r0, #shigh(0x00008000) 11431 or3 r0, r0, #low(0x00008000) 11432 11433 Stores 0xffff8000 into r0. 11434 11435 Note - the `shigh' directive does not know where in the assembly 11436 source code the lower 16-bits of the value are going set, so it 11437 cannot check to make sure that an `or3' instruction is being used 11438 rather than an `add3' instruction. It is up to the programmer to 11439 make sure that correct directives are used. 11440 11441`.m32r' 11442 The directive performs a similar thing as the _-m32r_ command line 11443 option. It tells the assembler to only accept M32R instructions 11444 from now on. An instructions from later M32R architectures are 11445 refused. 11446 11447`.m32rx' 11448 The directive performs a similar thing as the _-m32rx_ command 11449 line option. It tells the assembler to start accepting the extra 11450 instructions in the M32RX ISA as well as the ordinary M32R ISA. 11451 11452`.m32r2' 11453 The directive performs a similar thing as the _-m32r2_ command 11454 line option. It tells the assembler to start accepting the extra 11455 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 11456 11457`.little' 11458 The directive performs a similar thing as the _-little_ command 11459 line option. It tells the assembler to start producing 11460 little-endian code and data. This option should be used with care 11461 as producing mixed-endian binary files is fraught with danger. 11462 11463`.big' 11464 The directive performs a similar thing as the _-big_ command line 11465 option. It tells the assembler to start producing big-endian code 11466 and data. This option should be used with care as producing 11467 mixed-endian binary files is fraught with danger. 11468 11469 11470 11471File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 11472 114739.20.3 M32R Warnings 11474-------------------- 11475 11476There are several warning and error messages that can be produced by 11477`as' which are specific to the M32R: 11478 11479`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 11480 This message is only produced if warnings for explicit parallel 11481 conflicts have been enabled. It indicates that the assembler has 11482 encountered a parallel instruction in which the destination 11483 register of the left hand instruction is used as an input register 11484 in the right hand instruction. For example in this code fragment 11485 `mv r1, r2 || neg r3, r1' register r1 is the destination of the 11486 move instruction and the input to the neg instruction. 11487 11488`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 11489 This message is only produced if warnings for explicit parallel 11490 conflicts have been enabled. It indicates that the assembler has 11491 encountered a parallel instruction in which the destination 11492 register of the right hand instruction is used as an input 11493 register in the left hand instruction. For example in this code 11494 fragment `mv r1, r2 || neg r2, r3' register r2 is the destination 11495 of the neg instruction and the input to the move instruction. 11496 11497`instruction `...' is for the M32RX only' 11498 This message is produced when the assembler encounters an 11499 instruction which is only supported by the M32Rx processor, and 11500 the `-m32rx' command line flag has not been specified to allow 11501 assembly of such instructions. 11502 11503`unknown instruction `...'' 11504 This message is produced when the assembler encounters an 11505 instruction which it does not recognize. 11506 11507`only the NOP instruction can be issued in parallel on the m32r' 11508 This message is produced when the assembler encounters a parallel 11509 instruction which does not involve a NOP instruction and the 11510 `-m32rx' command line flag has not been specified. Only the M32Rx 11511 processor is able to execute two instructions in parallel. 11512 11513`instruction `...' cannot be executed in parallel.' 11514 This message is produced when the assembler encounters a parallel 11515 instruction which is made up of one or two instructions which 11516 cannot be executed in parallel. 11517 11518`Instructions share the same execution pipeline' 11519 This message is produced when the assembler encounters a parallel 11520 instruction whoes components both use the same execution pipeline. 11521 11522`Instructions write to the same destination register.' 11523 This message is produced when the assembler encounters a parallel 11524 instruction where both components attempt to modify the same 11525 register. For example these code fragments will produce this 11526 message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, 11527 @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx 11528 r3, r4' (Both write to the condition bit) 11529 11530 11531 11532File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 11533 115349.21 M680x0 Dependent Features 11535============================== 11536 11537* Menu: 11538 11539* M68K-Opts:: M680x0 Options 11540* M68K-Syntax:: Syntax 11541* M68K-Moto-Syntax:: Motorola Syntax 11542* M68K-Float:: Floating Point 11543* M68K-Directives:: 680x0 Machine Directives 11544* M68K-opcodes:: Opcodes 11545 11546 11547File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 11548 115499.21.1 M680x0 Options 11550--------------------- 11551 11552The Motorola 680x0 version of `as' has a few machine dependent options: 11553 11554`-march=ARCHITECTURE' 11555 This option specifies a target architecture. The following 11556 architectures are recognized: `68000', `68010', `68020', `68030', 11557 `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and 11558 `cfv4e'. 11559 11560`-mcpu=CPU' 11561 This option specifies a target cpu. When used in conjunction with 11562 the `-march' option, the cpu must be within the specified 11563 architecture. Also, the generic features of the architecture are 11564 used for instruction generation, rather than those of the specific 11565 chip. 11566 11567`-m[no-]68851' 11568`-m[no-]68881' 11569`-m[no-]div' 11570`-m[no-]usp' 11571`-m[no-]float' 11572`-m[no-]mac' 11573`-m[no-]emac' 11574 Enable or disable various architecture specific features. If a 11575 chip or architecture by default supports an option (for instance 11576 `-march=isaaplus' includes the `-mdiv' option), explicitly 11577 disabling the option will override the default. 11578 11579`-l' 11580 You can use the `-l' option to shorten the size of references to 11581 undefined symbols. If you do not use the `-l' option, references 11582 to undefined symbols are wide enough for a full `long' (32 bits). 11583 (Since `as' cannot know where these symbols end up, `as' can only 11584 allocate space for the linker to fill in later. Since `as' does 11585 not know how far away these symbols are, it allocates as much 11586 space as it can.) If you use this option, the references are only 11587 one word wide (16 bits). This may be useful if you want the 11588 object file to be as small as possible, and you know that the 11589 relevant symbols are always less than 17 bits away. 11590 11591`--register-prefix-optional' 11592 For some configurations, especially those where the compiler 11593 normally does not prepend an underscore to the names of user 11594 variables, the assembler requires a `%' before any use of a 11595 register name. This is intended to let the assembler distinguish 11596 between C variables and functions named `a0' through `a7', and so 11597 on. The `%' is always accepted, but is not required for certain 11598 configurations, notably `sun3'. The `--register-prefix-optional' 11599 option may be used to permit omitting the `%' even for 11600 configurations for which it is normally required. If this is 11601 done, it will generally be impossible to refer to C variables and 11602 functions with the same names as register names. 11603 11604`--bitwise-or' 11605 Normally the character `|' is treated as a comment character, which 11606 means that it can not be used in expressions. The `--bitwise-or' 11607 option turns `|' into a normal character. In this mode, you must 11608 either use C style comments, or start comments with a `#' character 11609 at the beginning of a line. 11610 11611`--base-size-default-16 --base-size-default-32' 11612 If you use an addressing mode with a base register without 11613 specifying the size, `as' will normally use the full 32 bit value. 11614 For example, the addressing mode `%a0@(%d0)' is equivalent to 11615 `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to 11616 tell `as' to default to using the 16 bit value. In this case, 11617 `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the 11618 `--base-size-default-32' option to restore the default behaviour. 11619 11620`--disp-size-default-16 --disp-size-default-32' 11621 If you use an addressing mode with a displacement, and the value 11622 of the displacement is not known, `as' will normally assume that 11623 the value is 32 bits. For example, if the symbol `disp' has not 11624 been defined, `as' will assemble the addressing mode 11625 `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use 11626 the `--disp-size-default-16' option to tell `as' to instead assume 11627 that the displacement is 16 bits. In this case, `as' will 11628 assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You 11629 may use the `--disp-size-default-32' option to restore the default 11630 behaviour. 11631 11632`--pcrel' 11633 Always keep branches PC-relative. In the M680x0 architecture all 11634 branches are defined as PC-relative. However, on some processors 11635 they are limited to word displacements maximum. When `as' needs a 11636 long branch that is not available, it normally emits an absolute 11637 jump instead. This option disables this substitution. When this 11638 option is given and no long branches are available, only word 11639 branches will be emitted. An error message will be generated if a 11640 word branch cannot reach its target. This option has no effect on 11641 68020 and other processors that have long branches. *note Branch 11642 Improvement: M68K-Branch. 11643 11644`-m68000' 11645 `as' can assemble code for several different members of the 11646 Motorola 680x0 family. The default depends upon how `as' was 11647 configured when it was built; normally, the default is to assemble 11648 code for the 68020 microprocessor. The following options may be 11649 used to change the default. These options control which 11650 instructions and addressing modes are permitted. The members of 11651 the 680x0 family are very similar. For detailed information about 11652 the differences, see the Motorola manuals. 11653 11654 `-m68000' 11655 `-m68ec000' 11656 `-m68hc000' 11657 `-m68hc001' 11658 `-m68008' 11659 `-m68302' 11660 `-m68306' 11661 `-m68307' 11662 `-m68322' 11663 `-m68356' 11664 Assemble for the 68000. `-m68008', `-m68302', and so on are 11665 synonyms for `-m68000', since the chips are the same from the 11666 point of view of the assembler. 11667 11668 `-m68010' 11669 Assemble for the 68010. 11670 11671 `-m68020' 11672 `-m68ec020' 11673 Assemble for the 68020. This is normally the default. 11674 11675 `-m68030' 11676 `-m68ec030' 11677 Assemble for the 68030. 11678 11679 `-m68040' 11680 `-m68ec040' 11681 Assemble for the 68040. 11682 11683 `-m68060' 11684 `-m68ec060' 11685 Assemble for the 68060. 11686 11687 `-mcpu32' 11688 `-m68330' 11689 `-m68331' 11690 `-m68332' 11691 `-m68333' 11692 `-m68334' 11693 `-m68336' 11694 `-m68340' 11695 `-m68341' 11696 `-m68349' 11697 `-m68360' 11698 Assemble for the CPU32 family of chips. 11699 11700 `-m5200' 11701 `-m5202' 11702 `-m5204' 11703 `-m5206' 11704 `-m5206e' 11705 `-m521x' 11706 `-m5249' 11707 `-m528x' 11708 `-m5307' 11709 `-m5407' 11710 `-m547x' 11711 `-m548x' 11712 `-mcfv4' 11713 `-mcfv4e' 11714 Assemble for the ColdFire family of chips. 11715 11716 `-m68881' 11717 `-m68882' 11718 Assemble 68881 floating point instructions. This is the 11719 default for the 68020, 68030, and the CPU32. The 68040 and 11720 68060 always support floating point instructions. 11721 11722 `-mno-68881' 11723 Do not assemble 68881 floating point instructions. This is 11724 the default for 68000 and the 68010. The 68040 and 68060 11725 always support floating point instructions, even if this 11726 option is used. 11727 11728 `-m68851' 11729 Assemble 68851 MMU instructions. This is the default for the 11730 68020, 68030, and 68060. The 68040 accepts a somewhat 11731 different set of MMU instructions; `-m68851' and `-m68040' 11732 should not be used together. 11733 11734 `-mno-68851' 11735 Do not assemble 68851 MMU instructions. This is the default 11736 for the 68000, 68010, and the CPU32. The 68040 accepts a 11737 somewhat different set of MMU instructions. 11738 11739 11740File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 11741 117429.21.2 Syntax 11743------------- 11744 11745This syntax for the Motorola 680x0 was developed at MIT. 11746 11747 The 680x0 version of `as' uses instructions names and syntax 11748compatible with the Sun assembler. Intervening periods are ignored; 11749for example, `movl' is equivalent to `mov.l'. 11750 11751 In the following table APC stands for any of the address registers 11752(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 11753relative to the program counter (`%zpc'), a suppressed address register 11754(`%za0' through `%za7'), or it may be omitted entirely. The use of 11755SIZE means one of `w' or `l', and it may be omitted, along with the 11756leading colon, unless a scale is also specified. The use of SCALE 11757means one of `1', `2', `4', or `8', and it may always be omitted along 11758with the leading colon. 11759 11760 The following addressing modes are understood: 11761"Immediate" 11762 `#NUMBER' 11763 11764"Data Register" 11765 `%d0' through `%d7' 11766 11767"Address Register" 11768 `%a0' through `%a7' 11769 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 11770 also known as `%fp', the Frame Pointer. 11771 11772"Address Register Indirect" 11773 `%a0@' through `%a7@' 11774 11775"Address Register Postincrement" 11776 `%a0@+' through `%a7@+' 11777 11778"Address Register Predecrement" 11779 `%a0@-' through `%a7@-' 11780 11781"Indirect Plus Offset" 11782 `APC@(NUMBER)' 11783 11784"Index" 11785 `APC@(NUMBER,REGISTER:SIZE:SCALE)' 11786 11787 The NUMBER may be omitted. 11788 11789"Postindex" 11790 `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 11791 11792 The ONUMBER or the REGISTER, but not both, may be omitted. 11793 11794"Preindex" 11795 `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 11796 11797 The NUMBER may be omitted. Omitting the REGISTER produces the 11798 Postindex addressing mode. 11799 11800"Absolute" 11801 `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'. 11802 11803 11804File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 11805 118069.21.3 Motorola Syntax 11807---------------------- 11808 11809The standard Motorola syntax for this chip differs from the syntax 11810already discussed (*note Syntax: M68K-Syntax.). `as' can accept 11811Motorola syntax for operands, even if MIT syntax is used for other 11812operands in the same instruction. The two kinds of syntax are fully 11813compatible. 11814 11815 In the following table APC stands for any of the address registers 11816(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 11817relative to the program counter (`%zpc'), or a suppressed address 11818register (`%za0' through `%za7'). The use of SIZE means one of `w' or 11819`l', and it may always be omitted along with the leading dot. The use 11820of SCALE means one of `1', `2', `4', or `8', and it may always be 11821omitted along with the leading asterisk. 11822 11823 The following additional addressing modes are understood: 11824 11825"Address Register Indirect" 11826 `(%a0)' through `(%a7)' 11827 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 11828 also known as `%fp', the Frame Pointer. 11829 11830"Address Register Postincrement" 11831 `(%a0)+' through `(%a7)+' 11832 11833"Address Register Predecrement" 11834 `-(%a0)' through `-(%a7)' 11835 11836"Indirect Plus Offset" 11837 `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. 11838 11839 The NUMBER may also appear within the parentheses, as in 11840 `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 11841 (with an address register, omitting the NUMBER produces Address 11842 Register Indirect mode). 11843 11844"Index" 11845 `NUMBER(APC,REGISTER.SIZE*SCALE)' 11846 11847 The NUMBER may be omitted, or it may appear within the 11848 parentheses. The APC may be omitted. The REGISTER and the APC 11849 may appear in either order. If both APC and REGISTER are address 11850 registers, and the SIZE and SCALE are omitted, then the first 11851 register is taken as the base register, and the second as the 11852 index register. 11853 11854"Postindex" 11855 `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 11856 11857 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 11858 NUMBER or the APC may be omitted, but not both. 11859 11860"Preindex" 11861 `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 11862 11863 The NUMBER, or the APC, or the REGISTER, or any two of them, may 11864 be omitted. The ONUMBER may be omitted. The REGISTER and the APC 11865 may appear in either order. If both APC and REGISTER are address 11866 registers, and the SIZE and SCALE are omitted, then the first 11867 register is taken as the base register, and the second as the 11868 index register. 11869 11870 11871File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 11872 118739.21.4 Floating Point 11874--------------------- 11875 11876Packed decimal (P) format floating literals are not supported. Feel 11877free to add the code! 11878 11879 The floating point formats generated by directives are these. 11880 11881`.float' 11882 `Single' precision floating point constants. 11883 11884`.double' 11885 `Double' precision floating point constants. 11886 11887`.extend' 11888`.ldouble' 11889 `Extended' precision (`long double') floating point constants. 11890 11891 11892File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 11893 118949.21.5 680x0 Machine Directives 11895------------------------------- 11896 11897In order to be compatible with the Sun assembler the 680x0 assembler 11898understands the following directives. 11899 11900`.data1' 11901 This directive is identical to a `.data 1' directive. 11902 11903`.data2' 11904 This directive is identical to a `.data 2' directive. 11905 11906`.even' 11907 This directive is a special case of the `.align' directive; it 11908 aligns the output to an even byte boundary. 11909 11910`.skip' 11911 This directive is identical to a `.space' directive. 11912 11913`.arch NAME' 11914 Select the target architecture and extension features. Valid 11915 values for NAME are the same as for the `-march' command line 11916 option. This directive cannot be specified after any instructions 11917 have been assembled. If it is given multiple times, or in 11918 conjunction with the `-march' option, all uses must be for the 11919 same architecture and extension set. 11920 11921`.cpu NAME' 11922 Select the target cpu. Valid valuse for NAME are the same as for 11923 the `-mcpu' command line option. This directive cannot be 11924 specified after any instructions have been assembled. If it is 11925 given multiple times, or in conjunction with the `-mopt' option, 11926 all uses must be for the same cpu. 11927 11928 11929 11930File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 11931 119329.21.6 Opcodes 11933-------------- 11934 11935* Menu: 11936 11937* M68K-Branch:: Branch Improvement 11938* M68K-Chars:: Special Characters 11939 11940 11941File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 11942 119439.21.6.1 Branch Improvement 11944........................... 11945 11946Certain pseudo opcodes are permitted for branch instructions. They 11947expand to the shortest branch instruction that reach the target. 11948Generally these mnemonics are made by substituting `j' for `b' at the 11949start of a Motorola mnemonic. 11950 11951 The following table summarizes the pseudo-operations. A `*' flags 11952cases that are more fully described after the table: 11953 11954 Displacement 11955 +------------------------------------------------------------ 11956 | 68020 68000/10, not PC-relative OK 11957 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 11958 +------------------------------------------------------------ 11959 jbsr |bsrs bsrw bsrl jsr 11960 jra |bras braw bral jmp 11961 * jXX |bXXs bXXw bXXl bNXs;jmp 11962 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 11963 fjXX | N/A fbXXw fbXXl N/A 11964 11965 XX: condition 11966 NX: negative of condition XX 11967 `*'--see full description below 11968 `**'--this expansion mode is disallowed by `--pcrel' 11969 11970`jbsr' 11971`jra' 11972 These are the simplest jump pseudo-operations; they always map to 11973 one particular machine instruction, depending on the displacement 11974 to the branch target. This instruction will be a byte or word 11975 branch is that is sufficient. Otherwise, a long branch will be 11976 emitted if available. If no long branches are available and the 11977 `--pcrel' option is not given, an absolute long jump will be 11978 emitted instead. If no long branches are available, the `--pcrel' 11979 option is given, and a word branch cannot reach the target, an 11980 error message is generated. 11981 11982 In addition to standard branch operands, `as' allows these 11983 pseudo-operations to have all operands that are allowed for jsr 11984 and jmp, substituting these instructions if the operand given is 11985 not valid for a branch instruction. 11986 11987`jXX' 11988 Here, `jXX' stands for an entire family of pseudo-operations, 11989 where XX is a conditional branch or condition-code test. The full 11990 list of pseudo-ops in this family is: 11991 jhi jls jcc jcs jne jeq jvc 11992 jvs jpl jmi jge jlt jgt jle 11993 11994 Usually, each of these pseudo-operations expands to a single branch 11995 instruction. However, if a word branch is not sufficient, no long 11996 branches are available, and the `--pcrel' option is not given, `as' 11997 issues a longer code fragment in terms of NX, the opposite 11998 condition to XX. For example, under these conditions: 11999 jXX foo 12000 gives 12001 bNXs oof 12002 jmp foo 12003 oof: 12004 12005`dbXX' 12006 The full family of pseudo-operations covered here is 12007 dbhi dbls dbcc dbcs dbne dbeq dbvc 12008 dbvs dbpl dbmi dbge dblt dbgt dble 12009 dbf dbra dbt 12010 12011 Motorola `dbXX' instructions allow word displacements only. When 12012 a word displacement is sufficient, each of these pseudo-operations 12013 expands to the corresponding Motorola instruction. When a word 12014 displacement is not sufficient and long branches are available, 12015 when the source reads `dbXX foo', `as' emits 12016 dbXX oo1 12017 bras oo2 12018 oo1:bral foo 12019 oo2: 12020 12021 If, however, long branches are not available and the `--pcrel' 12022 option is not given, `as' emits 12023 dbXX oo1 12024 bras oo2 12025 oo1:jmp foo 12026 oo2: 12027 12028`fjXX' 12029 This family includes 12030 fjne fjeq fjge fjlt fjgt fjle fjf 12031 fjt fjgl fjgle fjnge fjngl fjngle fjngt 12032 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 12033 fjor fjseq fjsf fjsne fjst fjueq fjuge 12034 fjugt fjule fjult fjun 12035 12036 Each of these pseudo-operations always expands to a single Motorola 12037 coprocessor branch instruction, word or long. All Motorola 12038 coprocessor branch instructions allow both word and long 12039 displacements. 12040 12041 12042 12043File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 12044 120459.21.6.2 Special Characters 12046........................... 12047 12048The immediate character is `#' for Sun compatibility. The line-comment 12049character is `|' (unless the `--bitwise-or' option is used). If a `#' 12050appears at the beginning of a line, it is treated as a comment unless 12051it looks like `# line file', in which case it is treated normally. 12052 12053 12054File: as.info, Node: M68HC11-Dependent, Next: MicroBlaze-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 12055 120569.22 M68HC11 and M68HC12 Dependent Features 12057=========================================== 12058 12059* Menu: 12060 12061* M68HC11-Opts:: M68HC11 and M68HC12 Options 12062* M68HC11-Syntax:: Syntax 12063* M68HC11-Modifiers:: Symbolic Operand Modifiers 12064* M68HC11-Directives:: Assembler Directives 12065* M68HC11-Float:: Floating Point 12066* M68HC11-opcodes:: Opcodes 12067 12068 12069File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 12070 120719.22.1 M68HC11 and M68HC12 Options 12072---------------------------------- 12073 12074The Motorola 68HC11 and 68HC12 version of `as' have a few machine 12075dependent options. 12076 12077`-m68hc11' 12078 This option switches the assembler in the M68HC11 mode. In this 12079 mode, the assembler only accepts 68HC11 operands and mnemonics. It 12080 produces code for the 68HC11. 12081 12082`-m68hc12' 12083 This option switches the assembler in the M68HC12 mode. In this 12084 mode, the assembler also accepts 68HC12 operands and mnemonics. It 12085 produces code for the 68HC12. A few 68HC11 instructions are 12086 replaced by some 68HC12 instructions as recommended by Motorola 12087 specifications. 12088 12089`-m68hcs12' 12090 This option switches the assembler in the M68HCS12 mode. This 12091 mode is similar to `-m68hc12' but specifies to assemble for the 12092 68HCS12 series. The only difference is on the assembling of the 12093 `movb' and `movw' instruction when a PC-relative operand is used. 12094 12095`-mshort' 12096 This option controls the ABI and indicates to use a 16-bit integer 12097 ABI. It has no effect on the assembled instructions. This is the 12098 default. 12099 12100`-mlong' 12101 This option controls the ABI and indicates to use a 32-bit integer 12102 ABI. 12103 12104`-mshort-double' 12105 This option controls the ABI and indicates to use a 32-bit float 12106 ABI. This is the default. 12107 12108`-mlong-double' 12109 This option controls the ABI and indicates to use a 64-bit float 12110 ABI. 12111 12112`--strict-direct-mode' 12113 You can use the `--strict-direct-mode' option to disable the 12114 automatic translation of direct page mode addressing into extended 12115 mode when the instruction does not support direct mode. For 12116 example, the `clr' instruction does not support direct page mode 12117 addressing. When it is used with the direct page mode, `as' will 12118 ignore it and generate an absolute addressing. This option 12119 prevents `as' from doing this, and the wrong usage of the direct 12120 page mode will raise an error. 12121 12122`--short-branches' 12123 The `--short-branches' option turns off the translation of 12124 relative branches into absolute branches when the branch offset is 12125 out of range. By default `as' transforms the relative branch 12126 (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', 12127 `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch 12128 when the offset is out of the -128 .. 127 range. In that case, 12129 the `bsr' instruction is translated into a `jsr', the `bra' 12130 instruction is translated into a `jmp' and the conditional 12131 branches instructions are inverted and followed by a `jmp'. This 12132 option disables these translations and `as' will generate an error 12133 if a relative branch is out of range. This option does not affect 12134 the optimization associated to the `jbra', `jbsr' and `jbXX' 12135 pseudo opcodes. 12136 12137`--force-long-branches' 12138 The `--force-long-branches' option forces the translation of 12139 relative branches into absolute branches. This option does not 12140 affect the optimization associated to the `jbra', `jbsr' and 12141 `jbXX' pseudo opcodes. 12142 12143`--print-insn-syntax' 12144 You can use the `--print-insn-syntax' option to obtain the syntax 12145 description of the instruction when an error is detected. 12146 12147`--print-opcodes' 12148 The `--print-opcodes' option prints the list of all the 12149 instructions with their syntax. The first item of each line 12150 represents the instruction name and the rest of the line indicates 12151 the possible operands for that instruction. The list is printed in 12152 alphabetical order. Once the list is printed `as' exits. 12153 12154`--generate-example' 12155 The `--generate-example' option is similar to `--print-opcodes' 12156 but it generates an example for each instruction instead. 12157 12158 12159File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 12160 121619.22.2 Syntax 12162------------- 12163 12164In the M68HC11 syntax, the instruction name comes first and it may be 12165followed by one or several operands (up to three). Operands are 12166separated by comma (`,'). In the normal mode, `as' will complain if too 12167many operands are specified for a given instruction. In the MRI mode 12168(turned on with `-M' option), it will treat them as comments. Example: 12169 12170 inx 12171 lda #23 12172 bset 2,x #4 12173 brclr *bot #8 foo 12174 12175 The following addressing modes are understood for 68HC11 and 68HC12: 12176"Immediate" 12177 `#NUMBER' 12178 12179"Address Register" 12180 `NUMBER,X', `NUMBER,Y' 12181 12182 The NUMBER may be omitted in which case 0 is assumed. 12183 12184"Direct Addressing mode" 12185 `*SYMBOL', or `*DIGITS' 12186 12187"Absolute" 12188 `SYMBOL', or `DIGITS' 12189 12190 The M68HC12 has other more complex addressing modes. All of them are 12191supported and they are represented below: 12192 12193"Constant Offset Indexed Addressing Mode" 12194 `NUMBER,REG' 12195 12196 The NUMBER may be omitted in which case 0 is assumed. The 12197 register can be either `X', `Y', `SP' or `PC'. The assembler will 12198 use the smaller post-byte definition according to the constant 12199 value (5-bit constant offset, 9-bit constant offset or 16-bit 12200 constant offset). If the constant is not known by the assembler 12201 it will use the 16-bit constant offset post-byte and the value 12202 will be resolved at link time. 12203 12204"Offset Indexed Indirect" 12205 `[NUMBER,REG]' 12206 12207 The register can be either `X', `Y', `SP' or `PC'. 12208 12209"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 12210 `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' 12211 12212 The number must be in the range `-8'..`+8' and must not be 0. The 12213 register can be either `X', `Y', `SP' or `PC'. 12214 12215"Accumulator Offset" 12216 `ACC,REG' 12217 12218 The accumulator register can be either `A', `B' or `D'. The 12219 register can be either `X', `Y', `SP' or `PC'. 12220 12221"Accumulator D offset indexed-indirect" 12222 `[D,REG]' 12223 12224 The register can be either `X', `Y', `SP' or `PC'. 12225 12226 12227 For example: 12228 12229 ldab 1024,sp 12230 ldd [10,x] 12231 orab 3,+x 12232 stab -2,y- 12233 ldx a,pc 12234 sty [d,sp] 12235 12236 12237File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 12238 122399.22.3 Symbolic Operand Modifiers 12240--------------------------------- 12241 12242The assembler supports several modifiers when using symbol addresses in 1224368HC11 and 68HC12 instruction operands. The general syntax is the 12244following: 12245 12246 %modifier(symbol) 12247 12248`%addr' 12249 This modifier indicates to the assembler and linker to use the 12250 16-bit physical address corresponding to the symbol. This is 12251 intended to be used on memory window systems to map a symbol in 12252 the memory bank window. If the symbol is in a memory expansion 12253 part, the physical address corresponds to the symbol address 12254 within the memory bank window. If the symbol is not in a memory 12255 expansion part, this is the symbol address (using or not using the 12256 %addr modifier has no effect in that case). 12257 12258`%page' 12259 This modifier indicates to use the memory page number corresponding 12260 to the symbol. If the symbol is in a memory expansion part, its 12261 page number is computed by the linker as a number used to map the 12262 page containing the symbol in the memory bank window. If the 12263 symbol is not in a memory expansion part, the page number is 0. 12264 12265`%hi' 12266 This modifier indicates to use the 8-bit high part of the physical 12267 address of the symbol. 12268 12269`%lo' 12270 This modifier indicates to use the 8-bit low part of the physical 12271 address of the symbol. 12272 12273 12274 For example a 68HC12 call to a function `foo_example' stored in 12275memory expansion part could be written as follows: 12276 12277 call %addr(foo_example),%page(foo_example) 12278 12279 and this is equivalent to 12280 12281 call foo_example 12282 12283 And for 68HC11 it could be written as follows: 12284 12285 ldab #%page(foo_example) 12286 stab _page_switch 12287 jsr %addr(foo_example) 12288 12289 12290File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 12291 122929.22.4 Assembler Directives 12293--------------------------- 12294 12295The 68HC11 and 68HC12 version of `as' have the following specific 12296assembler directives: 12297 12298`.relax' 12299 The relax directive is used by the `GNU Compiler' to emit a 12300 specific relocation to mark a group of instructions for linker 12301 relaxation. The sequence of instructions within the group must be 12302 known to the linker so that relaxation can be performed. 12303 12304`.mode [mshort|mlong|mshort-double|mlong-double]' 12305 This directive specifies the ABI. It overrides the `-mshort', 12306 `-mlong', `-mshort-double' and `-mlong-double' options. 12307 12308`.far SYMBOL' 12309 This directive marks the symbol as a `far' symbol meaning that it 12310 uses a `call/rtc' calling convention as opposed to `jsr/rts'. 12311 During a final link, the linker will identify references to the 12312 `far' symbol and will verify the proper calling convention. 12313 12314`.interrupt SYMBOL' 12315 This directive marks the symbol as an interrupt entry point. This 12316 information is then used by the debugger to correctly unwind the 12317 frame across interrupts. 12318 12319`.xrefb SYMBOL' 12320 This directive is defined for compatibility with the 12321 `Specification for Motorola 8 and 16-Bit Assembly Language Input 12322 Standard' and is ignored. 12323 12324 12325 12326File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 12327 123289.22.5 Floating Point 12329--------------------- 12330 12331Packed decimal (P) format floating literals are not supported. Feel 12332free to add the code! 12333 12334 The floating point formats generated by directives are these. 12335 12336`.float' 12337 `Single' precision floating point constants. 12338 12339`.double' 12340 `Double' precision floating point constants. 12341 12342`.extend' 12343`.ldouble' 12344 `Extended' precision (`long double') floating point constants. 12345 12346 12347File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 12348 123499.22.6 Opcodes 12350-------------- 12351 12352* Menu: 12353 12354* M68HC11-Branch:: Branch Improvement 12355 12356 12357File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 12358 123599.22.6.1 Branch Improvement 12360........................... 12361 12362Certain pseudo opcodes are permitted for branch instructions. They 12363expand to the shortest branch instruction that reach the target. 12364Generally these mnemonics are made by prepending `j' to the start of 12365Motorola mnemonic. These pseudo opcodes are not affected by the 12366`--short-branches' or `--force-long-branches' options. 12367 12368 The following table summarizes the pseudo-operations. 12369 12370 Displacement Width 12371 +-------------------------------------------------------------+ 12372 | Options | 12373 | --short-branches --force-long-branches | 12374 +--------------------------+----------------------------------+ 12375 Op |BYTE WORD | BYTE WORD | 12376 +--------------------------+----------------------------------+ 12377 bsr | bsr <pc-rel> <error> | jsr <abs> | 12378 bra | bra <pc-rel> <error> | jmp <abs> | 12379 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 12380 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 12381 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 12382 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 12383 | jmp <abs> | | 12384 +--------------------------+----------------------------------+ 12385 XX: condition 12386 NX: negative of condition XX 12387 12388`jbsr' 12389`jbra' 12390 These are the simplest jump pseudo-operations; they always map to 12391 one particular machine instruction, depending on the displacement 12392 to the branch target. 12393 12394`jbXX' 12395 Here, `jbXX' stands for an entire family of pseudo-operations, 12396 where XX is a conditional branch or condition-code test. The full 12397 list of pseudo-ops in this family is: 12398 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 12399 jbcs jbne jblt jble jbls jbvc jbmi 12400 12401 For the cases of non-PC relative displacements and long 12402 displacements, `as' issues a longer code fragment in terms of NX, 12403 the opposite condition to XX. For example, for the non-PC 12404 relative case: 12405 jbXX foo 12406 gives 12407 bNXs oof 12408 jmp foo 12409 oof: 12410 12411 12412 12413File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 12414 124159.23 MicroBlaze Dependent Features 12416================================== 12417 12418 The Xilinx MicroBlaze processor family includes several variants, 12419all using the same core instruction set. This chapter covers features 12420of the GNU assembler that are specific to the MicroBlaze architecture. 12421For details about the MicroBlaze instruction set, please see the 12422`MicroBlaze Processor Reference Guide (UG081)' available at 12423www.xilinx.com. 12424 12425* Menu: 12426 12427* MicroBlaze Directives:: Directives for MicroBlaze Processors. 12428 12429 12430File: as.info, Node: MicroBlaze Directives, Up: MicroBlaze-Dependent 12431 124329.23.1 Directives 12433----------------- 12434 12435A number of assembler directives are available for MicroBlaze. 12436 12437`.data8 EXPRESSION,...' 12438 This directive is an alias for `.byte'. Each expression is 12439 assembled into an eight-bit value. 12440 12441`.data16 EXPRESSION,...' 12442 This directive is an alias for `.hword'. Each expression is 12443 assembled into an 16-bit value. 12444 12445`.data32 EXPRESSION,...' 12446 This directive is an alias for `.word'. Each expression is 12447 assembled into an 32-bit value. 12448 12449`.ent NAME[,LABEL]' 12450 This directive is an alias for `.func' denoting the start of 12451 function NAME at (optional) LABEL. 12452 12453`.end NAME[,LABEL]' 12454 This directive is an alias for `.endfunc' denoting the end of 12455 function NAME. 12456 12457`.gpword LABEL,...' 12458 This directive is an alias for `.rva'. The resolved address of 12459 LABEL is stored in the data section. 12460 12461`.weakext LABEL' 12462 Declare that LABEL is a weak external symbol. 12463 12464`.rodata' 12465 Switch to .rodata section. Equivalent to `.section .rodata' 12466 12467`.sdata2' 12468 Switch to .sdata2 section. Equivalent to `.section .sdata2' 12469 12470`.sdata' 12471 Switch to .sdata section. Equivalent to `.section .sdata' 12472 12473`.bss' 12474 Switch to .bss section. Equivalent to `.section .bss' 12475 12476`.sbss' 12477 Switch to .sbss section. Equivalent to `.section .sbss' 12478 12479 12480File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 12481 124829.24 MIPS Dependent Features 12483============================ 12484 12485 GNU `as' for MIPS architectures supports several different MIPS 12486processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 12487information about the MIPS instruction set, see `MIPS RISC 12488Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 12489of MIPS assembly conventions, see "Appendix D: Assembly Language 12490Programming" in the same work. 12491 12492* Menu: 12493 12494* MIPS Opts:: Assembler options 12495* MIPS Object:: ECOFF object code 12496* MIPS Stabs:: Directives for debugging information 12497* MIPS ISA:: Directives to override the ISA level 12498* MIPS symbol sizes:: Directives to override the size of symbols 12499* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 12500* MIPS insn:: Directive to mark data as an instruction 12501* MIPS option stack:: Directives to save and restore options 12502* MIPS ASE instruction generation overrides:: Directives to control 12503 generation of MIPS ASE instructions 12504* MIPS floating-point:: Directives to override floating-point options 12505 12506 12507File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent 12508 125099.24.1 Assembler options 12510------------------------ 12511 12512The MIPS configurations of GNU `as' support these special options: 12513 12514`-G NUM' 12515 This option sets the largest size of an object that can be 12516 referenced implicitly with the `gp' register. It is only accepted 12517 for targets that use ECOFF format. The default value is 8. 12518 12519`-EB' 12520`-EL' 12521 Any MIPS configuration of `as' can select big-endian or 12522 little-endian output at run time (unlike the other GNU development 12523 tools, which must be configured for one or the other). Use `-EB' 12524 to select big-endian output, and `-EL' for little-endian. 12525 12526`-KPIC' 12527 Generate SVR4-style PIC. This option tells the assembler to 12528 generate SVR4-style position-independent macro expansions. It 12529 also tells the assembler to mark the output file as PIC. 12530 12531`-mvxworks-pic' 12532 Generate VxWorks PIC. This option tells the assembler to generate 12533 VxWorks-style position-independent macro expansions. 12534 12535`-mips1' 12536`-mips2' 12537`-mips3' 12538`-mips4' 12539`-mips5xo' 12540`-mips32' 12541`-mips32r2' 12542`-mips64' 12543`-mips64r2' 12544 Generate code for a particular MIPS Instruction Set Architecture 12545 level. `-mips1' corresponds to the R2000 and R3000 processors, 12546 `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, 12547 and `-mips4' to the R8000 and R10000 processors. `-mips5', 12548 `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to 12549 generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 12550 RELEASE 2 ISA processors, respectively. You can also switch 12551 instruction sets during the assembly; see *Note Directives to 12552 override the ISA level: MIPS ISA. 12553 12554`-mgp32' 12555`-mfp32' 12556 Some macros have different expansions for 32-bit and 64-bit 12557 registers. The register sizes are normally inferred from the ISA 12558 and ABI, but these flags force a certain group of registers to be 12559 treated as 32 bits wide at all times. `-mgp32' controls the size 12560 of general-purpose registers and `-mfp32' controls the size of 12561 floating-point registers. 12562 12563 The `.set gp=32' and `.set fp=32' directives allow the size of 12564 registers to be changed for parts of an object. The default value 12565 is restored by `.set gp=default' and `.set fp=default'. 12566 12567 On some MIPS variants there is a 32-bit mode flag; when this flag 12568 is set, 64-bit instructions generate a trap. Also, some 32-bit 12569 OSes only save the 32-bit registers on a context switch, so it is 12570 essential never to use the 64-bit registers. 12571 12572`-mgp64' 12573`-mfp64' 12574 Assume that 64-bit registers are available. This is provided in 12575 the interests of symmetry with `-mgp32' and `-mfp32'. 12576 12577 The `.set gp=64' and `.set fp=64' directives allow the size of 12578 registers to be changed for parts of an object. The default value 12579 is restored by `.set gp=default' and `.set fp=default'. 12580 12581`-mips16' 12582`-no-mips16' 12583 Generate code for the MIPS 16 processor. This is equivalent to 12584 putting `.set mips16' at the start of the assembly file. 12585 `-no-mips16' turns off this option. 12586 12587`-msmartmips' 12588`-mno-smartmips' 12589 Enables the SmartMIPS extensions to the MIPS32 instruction set, 12590 which provides a number of new instructions which target smartcard 12591 and cryptographic applications. This is equivalent to putting 12592 `.set smartmips' at the start of the assembly file. 12593 `-mno-smartmips' turns off this option. 12594 12595`-mips3d' 12596`-no-mips3d' 12597 Generate code for the MIPS-3D Application Specific Extension. 12598 This tells the assembler to accept MIPS-3D instructions. 12599 `-no-mips3d' turns off this option. 12600 12601`-mdmx' 12602`-no-mdmx' 12603 Generate code for the MDMX Application Specific Extension. This 12604 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 12605 off this option. 12606 12607`-mdsp' 12608`-mno-dsp' 12609 Generate code for the DSP Release 1 Application Specific Extension. 12610 This tells the assembler to accept DSP Release 1 instructions. 12611 `-mno-dsp' turns off this option. 12612 12613`-mdspr2' 12614`-mno-dspr2' 12615 Generate code for the DSP Release 2 Application Specific Extension. 12616 This option implies -mdsp. This tells the assembler to accept DSP 12617 Release 2 instructions. `-mno-dspr2' turns off this option. 12618 12619`-mmt' 12620`-mno-mt' 12621 Generate code for the MT Application Specific Extension. This 12622 tells the assembler to accept MT instructions. `-mno-mt' turns 12623 off this option. 12624 12625`-mfix7000' 12626`-mno-fix7000' 12627 Cause nops to be inserted if the read of the destination register 12628 of an mfhi or mflo instruction occurs in the following two 12629 instructions. 12630 12631`-mfix-loongson2f-jump' 12632`-mno-fix-loongson2f-jump' 12633 Eliminate instruction fetch from outside 256M region to work 12634 around the Loongson2F `jump' instructions. Without it, under 12635 extreme cases, the kernel may crash. The issue has been solved in 12636 latest processor batches, but this fix has no side effect to them. 12637 12638`-mfix-loongson2f-nop' 12639`-mno-fix-loongson2f-nop' 12640 Replace nops by `or at,at,zero' to work around the Loongson2F 12641 `nop' errata. Without it, under extreme cases, cpu might 12642 deadlock. The issue has been solved in latest loongson2f batches, 12643 but this fix has no side effect to them. 12644 12645`-mfix-vr4120' 12646`-mno-fix-vr4120' 12647 Insert nops to work around certain VR4120 errata. This option is 12648 intended to be used on GCC-generated code: it is not designed to 12649 catch all problems in hand-written assembler code. 12650 12651`-mfix-vr4130' 12652`-mno-fix-vr4130' 12653 Insert nops to work around the VR4130 `mflo'/`mfhi' errata. 12654 12655`-mfix-24k' 12656`-no-mfix-24k' 12657 Insert nops to work around the 24K `eret'/`deret' errata. 12658 12659`-mfix-cn63xxp1' 12660`-mno-fix-cn63xxp1' 12661 Replace `pref' hints 0 - 4 and 6 - 24 with hint 28 to work around 12662 certain CN63XXP1 errata. 12663 12664`-m4010' 12665`-no-m4010' 12666 Generate code for the LSI R4010 chip. This tells the assembler to 12667 accept the R4010 specific instructions (`addciu', `ffc', etc.), 12668 and to not schedule `nop' instructions around accesses to the `HI' 12669 and `LO' registers. `-no-m4010' turns off this option. 12670 12671`-m4650' 12672`-no-m4650' 12673 Generate code for the MIPS R4650 chip. This tells the assembler 12674 to accept the `mad' and `madu' instruction, and to not schedule 12675 `nop' instructions around accesses to the `HI' and `LO' registers. 12676 `-no-m4650' turns off this option. 12677 12678`-m3900' 12679`-no-m3900' 12680`-m4100' 12681`-no-m4100' 12682 For each option `-mNNNN', generate code for the MIPS RNNNN chip. 12683 This tells the assembler to accept instructions specific to that 12684 chip, and to schedule for that chip's hazards. 12685 12686`-march=CPU' 12687 Generate code for a particular MIPS cpu. It is exactly equivalent 12688 to `-mCPU', except that there are more value of CPU understood. 12689 Valid CPU value are: 12690 12691 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 12692 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 12693 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 12694 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 12695 4kep, 4ksd, m4k, m4kp, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 12696 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc, 12697 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 12698 1004kf1_1, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, 12699 loongson2f, octeon, xlr 12700 12701 For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms 12702 for `Nf1_1'. These values are deprecated. 12703 12704`-mtune=CPU' 12705 Schedule and tune for a particular MIPS cpu. Valid CPU values are 12706 identical to `-march=CPU'. 12707 12708`-mabi=ABI' 12709 Record which ABI the source code uses. The recognized arguments 12710 are: `32', `n32', `o64', `64' and `eabi'. 12711 12712`-msym32' 12713`-mno-sym32' 12714 Equivalent to adding `.set sym32' or `.set nosym32' to the 12715 beginning of the assembler input. *Note MIPS symbol sizes::. 12716 12717`-nocpp' 12718 This option is ignored. It is accepted for command-line 12719 compatibility with other assemblers, which use it to turn off C 12720 style preprocessing. With GNU `as', there is no need for 12721 `-nocpp', because the GNU assembler itself never runs the C 12722 preprocessor. 12723 12724`-msoft-float' 12725`-mhard-float' 12726 Disable or enable floating-point instructions. Note that by 12727 default floating-point instructions are always allowed even with 12728 CPU targets that don't have support for these instructions. 12729 12730`-msingle-float' 12731`-mdouble-float' 12732 Disable or enable double-precision floating-point operations. Note 12733 that by default double-precision floating-point operations are 12734 always allowed even with CPU targets that don't have support for 12735 these operations. 12736 12737`--construct-floats' 12738`--no-construct-floats' 12739 The `--no-construct-floats' option disables the construction of 12740 double width floating point constants by loading the two halves of 12741 the value into the two single width floating point registers that 12742 make up the double width register. This feature is useful if the 12743 processor support the FR bit in its status register, and this bit 12744 is known (by the programmer) to be set. This bit prevents the 12745 aliasing of the double width register by the single width 12746 registers. 12747 12748 By default `--construct-floats' is selected, allowing construction 12749 of these floating point constants. 12750 12751`--trap' 12752`--no-break' 12753 `as' automatically macro expands certain division and 12754 multiplication instructions to check for overflow and division by 12755 zero. This option causes `as' to generate code to take a trap 12756 exception rather than a break exception when an error is detected. 12757 The trap instructions are only supported at Instruction Set 12758 Architecture level 2 and higher. 12759 12760`--break' 12761`--no-trap' 12762 Generate code to take a break exception rather than a trap 12763 exception when an error is detected. This is the default. 12764 12765`-mpdr' 12766`-mno-pdr' 12767 Control generation of `.pdr' sections. Off by default on IRIX, on 12768 elsewhere. 12769 12770`-mshared' 12771`-mno-shared' 12772 When generating code using the Unix calling conventions (selected 12773 by `-KPIC' or `-mcall_shared'), gas will normally generate code 12774 which can go into a shared library. The `-mno-shared' option 12775 tells gas to generate code which uses the calling convention, but 12776 can not go into a shared library. The resulting code is slightly 12777 more efficient. This option only affects the handling of the 12778 `.cpload' and `.cpsetup' pseudo-ops. 12779 12780 12781File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent 12782 127839.24.2 MIPS ECOFF object code 12784----------------------------- 12785 12786Assembling for a MIPS ECOFF target supports some additional sections 12787besides the usual `.text', `.data' and `.bss'. The additional sections 12788are `.rdata', used for read-only data, `.sdata', used for small data, 12789and `.sbss', used for small common objects. 12790 12791 When assembling for ECOFF, the assembler uses the `$gp' (`$28') 12792register to form the address of a "small object". Any object in the 12793`.sdata' or `.sbss' sections is considered "small" in this sense. For 12794external objects, or for objects in the `.bss' section, you can use the 12795`gcc' `-G' option to control the size of objects addressed via `$gp'; 12796the default value is 8, meaning that a reference to any object eight 12797bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from 12798using the `$gp' register on the basis of object size (but the assembler 12799uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of 12800an object in the `.bss' section is set by the `.comm' or `.lcomm' 12801directive that defines it. The size of an external object may be set 12802with the `.extern' directive. For example, `.extern sym,4' declares 12803that the object at `sym' is 4 bytes in length, whie leaving `sym' 12804otherwise undefined. 12805 12806 Using small ECOFF objects requires linker support, and assumes that 12807the `$gp' register is correctly initialized (normally done 12808automatically by the startup code). MIPS ECOFF assembly code must not 12809modify the `$gp' register. 12810 12811 12812File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent 12813 128149.24.3 Directives for debugging information 12815------------------------------------------- 12816 12817MIPS ECOFF `as' supports several directives used for generating 12818debugging information which are not support by traditional MIPS 12819assemblers. These are `.def', `.endef', `.dim', `.file', `.scl', 12820`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'. 12821The debugging information generated by the three `.stab' directives can 12822only be read by GDB, not by traditional MIPS debuggers (this 12823enhancement is required to fully support C++ debugging). These 12824directives are primarily used by compilers, not assembly language 12825programmers! 12826 12827 12828File: as.info, Node: MIPS symbol sizes, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 12829 128309.24.4 Directives to override the size of symbols 12831------------------------------------------------- 12832 12833The n64 ABI allows symbols to have any 64-bit value. Although this 12834provides a great deal of flexibility, it means that some macros have 12835much longer expansions than their 32-bit counterparts. For example, 12836the non-PIC expansion of `dla $4,sym' is usually: 12837 12838 lui $4,%highest(sym) 12839 lui $1,%hi(sym) 12840 daddiu $4,$4,%higher(sym) 12841 daddiu $1,$1,%lo(sym) 12842 dsll32 $4,$4,0 12843 daddu $4,$4,$1 12844 12845 whereas the 32-bit expansion is simply: 12846 12847 lui $4,%hi(sym) 12848 daddiu $4,$4,%lo(sym) 12849 12850 n64 code is sometimes constructed in such a way that all symbolic 12851constants are known to have 32-bit values, and in such cases, it's 12852preferable to use the 32-bit expansion instead of the 64-bit expansion. 12853 12854 You can use the `.set sym32' directive to tell the assembler that, 12855from this point on, all expressions of the form `SYMBOL' or `SYMBOL + 12856OFFSET' have 32-bit values. For example: 12857 12858 .set sym32 12859 dla $4,sym 12860 lw $4,sym+16 12861 sw $4,sym+0x8000($4) 12862 12863 will cause the assembler to treat `sym', `sym+16' and `sym+0x8000' 12864as 32-bit values. The handling of non-symbolic addresses is not 12865affected. 12866 12867 The directive `.set nosym32' ends a `.set sym32' block and reverts 12868to the normal behavior. It is also possible to change the symbol size 12869using the command-line options `-msym32' and `-mno-sym32'. 12870 12871 These options and directives are always accepted, but at present, 12872they have no effect for anything other than n64. 12873 12874 12875File: as.info, Node: MIPS ISA, Next: MIPS symbol sizes, Prev: MIPS Stabs, Up: MIPS-Dependent 12876 128779.24.5 Directives to override the ISA level 12878------------------------------------------- 12879 12880GNU `as' supports an additional directive to change the MIPS 12881Instruction Set Architecture level on the fly: `.set mipsN'. N should 12882be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other 12883than 0 make the assembler accept instructions for the corresponding ISA 12884level, from that point on in the assembly. `.set mipsN' affects not 12885only which instructions are permitted, but also how certain macros are 12886expanded. `.set mips0' restores the ISA level to its original level: 12887either the level you selected with command line options, or the default 12888for your configuration. You can use this feature to permit specific 12889MIPS3 instructions while assembling in 32 bit mode. Use this directive 12890with care! 12891 12892 The `.set arch=CPU' directive provides even finer control. It 12893changes the effective CPU target and allows the assembler to use 12894instructions specific to a particular CPU. All CPUs supported by the 12895`-march' command line option are also selectable by this directive. 12896The original value is restored by `.set arch=default'. 12897 12898 The directive `.set mips16' puts the assembler into MIPS 16 mode, in 12899which it will assemble instructions for the MIPS 16 processor. Use 12900`.set nomips16' to return to normal 32 bit mode. 12901 12902 Traditional MIPS assemblers do not support this directive. 12903 12904 12905File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS symbol sizes, Up: MIPS-Dependent 12906 129079.24.6 Directives for extending MIPS 16 bit instructions 12908-------------------------------------------------------- 12909 12910By default, MIPS 16 instructions are automatically extended to 32 bits 12911when necessary. The directive `.set noautoextend' will turn this off. 12912When `.set noautoextend' is in effect, any 32 bit instruction must be 12913explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The 12914directive `.set autoextend' may be used to once again automatically 12915extend instructions when necessary. 12916 12917 This directive is only meaningful when in MIPS 16 mode. Traditional 12918MIPS assemblers do not support this directive. 12919 12920 12921File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent 12922 129239.24.7 Directive to mark data as an instruction 12924----------------------------------------------- 12925 12926The `.insn' directive tells `as' that the following data is actually 12927instructions. This makes a difference in MIPS 16 mode: when loading 12928the address of a label which precedes instructions, `as' automatically 12929adds 1 to the value, so that jumping to the loaded address will do the 12930right thing. 12931 12932 The `.global' and `.globl' directives supported by `as' will by 12933default mark the symbol as pointing to a region of data not code. This 12934means that, for example, any instructions following such a symbol will 12935not be disassembled by `objdump' as it will regard them as data. To 12936change this behaviour an optional section name can be placed after the 12937symbol name in the `.global' directive. If this section exists and is 12938known to be a code section, then the symbol will be marked as poiting at 12939code not data. Ie the syntax for the directive is: 12940 12941 `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', 12942 12943 Here is a short example: 12944 12945 .global foo .text, bar, baz .data 12946 foo: 12947 nop 12948 bar: 12949 .word 0x0 12950 baz: 12951 .word 0x1 12952 12953 12954File: as.info, Node: MIPS option stack, Next: MIPS ASE instruction generation overrides, Prev: MIPS insn, Up: MIPS-Dependent 12955 129569.24.8 Directives to save and restore options 12957--------------------------------------------- 12958 12959The directives `.set push' and `.set pop' may be used to save and 12960restore the current settings for all the options which are controlled 12961by `.set'. The `.set push' directive saves the current settings on a 12962stack. The `.set pop' directive pops the stack and restores the 12963settings. 12964 12965 These directives can be useful inside an macro which must change an 12966option such as the ISA level or instruction reordering but does not want 12967to change the state of the code which invoked the macro. 12968 12969 Traditional MIPS assemblers do not support these directives. 12970 12971 12972File: as.info, Node: MIPS ASE instruction generation overrides, Next: MIPS floating-point, Prev: MIPS option stack, Up: MIPS-Dependent 12973 129749.24.9 Directives to control generation of MIPS ASE instructions 12975---------------------------------------------------------------- 12976 12977The directive `.set mips3d' makes the assembler accept instructions 12978from the MIPS-3D Application Specific Extension from that point on in 12979the assembly. The `.set nomips3d' directive prevents MIPS-3D 12980instructions from being accepted. 12981 12982 The directive `.set smartmips' makes the assembler accept 12983instructions from the SmartMIPS Application Specific Extension to the 12984MIPS32 ISA from that point on in the assembly. The `.set nosmartmips' 12985directive prevents SmartMIPS instructions from being accepted. 12986 12987 The directive `.set mdmx' makes the assembler accept instructions 12988from the MDMX Application Specific Extension from that point on in the 12989assembly. The `.set nomdmx' directive prevents MDMX instructions from 12990being accepted. 12991 12992 The directive `.set dsp' makes the assembler accept instructions 12993from the DSP Release 1 Application Specific Extension from that point 12994on in the assembly. The `.set nodsp' directive prevents DSP Release 1 12995instructions from being accepted. 12996 12997 The directive `.set dspr2' makes the assembler accept instructions 12998from the DSP Release 2 Application Specific Extension from that point 12999on in the assembly. This dirctive implies `.set dsp'. The `.set 13000nodspr2' directive prevents DSP Release 2 instructions from being 13001accepted. 13002 13003 The directive `.set mt' makes the assembler accept instructions from 13004the MT Application Specific Extension from that point on in the 13005assembly. The `.set nomt' directive prevents MT instructions from 13006being accepted. 13007 13008 Traditional MIPS assemblers do not support these directives. 13009 13010 13011File: as.info, Node: MIPS floating-point, Prev: MIPS ASE instruction generation overrides, Up: MIPS-Dependent 13012 130139.24.10 Directives to override floating-point options 13014----------------------------------------------------- 13015 13016The directives `.set softfloat' and `.set hardfloat' provide finer 13017control of disabling and enabling float-point instructions. These 13018directives always override the default (that hard-float instructions 13019are accepted) or the command-line options (`-msoft-float' and 13020`-mhard-float'). 13021 13022 The directives `.set singlefloat' and `.set doublefloat' provide 13023finer control of disabling and enabling double-precision float-point 13024operations. These directives always override the default (that 13025double-precision operations are accepted) or the command-line options 13026(`-msingle-float' and `-mdouble-float'). 13027 13028 Traditional MIPS assemblers do not support these directives. 13029 13030 13031File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 13032 130339.25 MMIX Dependent Features 13034============================ 13035 13036* Menu: 13037 13038* MMIX-Opts:: Command-line Options 13039* MMIX-Expand:: Instruction expansion 13040* MMIX-Syntax:: Syntax 13041* MMIX-mmixal:: Differences to `mmixal' syntax and semantics 13042 13043 13044File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 13045 130469.25.1 Command-line Options 13047--------------------------- 13048 13049The MMIX version of `as' has some machine-dependent options. 13050 13051 When `--fixed-special-register-names' is specified, only the register 13052names specified in *Note MMIX-Regs:: are recognized in the instructions 13053`PUT' and `GET'. 13054 13055 You can use the `--globalize-symbols' to make all symbols global. 13056This option is useful when splitting up a `mmixal' program into several 13057files. 13058 13059 The `--gnu-syntax' turns off most syntax compatibility with 13060`mmixal'. Its usability is currently doubtful. 13061 13062 The `--relax' option is not fully supported, but will eventually make 13063the object file prepared for linker relaxation. 13064 13065 If you want to avoid inadvertently calling a predefined symbol and 13066would rather get an error, for example when using `as' with a compiler 13067or other machine-generated code, specify `--no-predefined-syms'. This 13068turns off built-in predefined definitions of all such symbols, 13069including rounding-mode symbols, segment symbols, `BIT' symbols, and 13070`TRAP' symbols used in `mmix' "system calls". It also turns off 13071predefined special-register names, except when used in `PUT' and `GET' 13072instructions. 13073 13074 By default, some instructions are expanded to fit the size of the 13075operand or an external symbol (*note MMIX-Expand::). By passing 13076`--no-expand', no such expansion will be done, instead causing errors 13077at link time if the operand does not fit. 13078 13079 The `mmixal' documentation (*note mmixsite::) specifies that global 13080registers allocated with the `GREG' directive (*note MMIX-greg::) and 13081initialized to the same non-zero value, will refer to the same global 13082register. This isn't strictly enforceable in `as' since the final 13083addresses aren't known until link-time, but it will do an effort unless 13084the `--no-merge-gregs' option is specified. (Register merging isn't 13085yet implemented in `ld'.) 13086 13087 `as' will warn every time it expands an instruction to fit an 13088operand unless the option `-x' is specified. It is believed that this 13089behaviour is more useful than just mimicking `mmixal''s behaviour, in 13090which instructions are only expanded if the `-x' option is specified, 13091and assembly fails otherwise, when an instruction needs to be expanded. 13092It needs to be kept in mind that `mmixal' is both an assembler and 13093linker, while `as' will expand instructions that at link stage can be 13094contracted. (Though linker relaxation isn't yet implemented in `ld'.) 13095The option `-x' also imples `--linker-allocated-gregs'. 13096 13097 If instruction expansion is enabled, `as' can expand a `PUSHJ' 13098instruction into a series of instructions. The shortest expansion is 13099to not expand it, but just mark the call as redirectable to a stub, 13100which `ld' creates at link-time, but only if the original `PUSHJ' 13101instruction is found not to reach the target. The stub consists of the 13102necessary instructions to form a jump to the target. This happens if 13103`as' can assert that the `PUSHJ' instruction can reach such a stub. 13104The option `--no-pushj-stubs' disables this shorter expansion, and the 13105longer series of instructions is then created at assembly-time. The 13106option `--no-stubs' is a synonym, intended for compatibility with 13107future releases, where generation of stubs for other instructions may 13108be implemented. 13109 13110 Usually a two-operand-expression (*note GREG-base::) without a 13111matching `GREG' directive is treated as an error by `as'. When the 13112option `--linker-allocated-gregs' is in effect, they are instead passed 13113through to the linker, which will allocate as many global registers as 13114is needed. 13115 13116 13117File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 13118 131199.25.2 Instruction expansion 13120---------------------------- 13121 13122When `as' encounters an instruction with an operand that is either not 13123known or does not fit the operand size of the instruction, `as' (and 13124`ld') will expand the instruction into a sequence of instructions 13125semantically equivalent to the operand fitting the instruction. 13126Expansion will take place for the following instructions: 13127 13128`GETA' 13129 Expands to a sequence of four instructions: `SETL', `INCML', 13130 `INCMH' and `INCH'. The operand must be a multiple of four. 13131 13132Conditional branches 13133 A branch instruction is turned into a branch with the complemented 13134 condition and prediction bit over five instructions; four 13135 instructions setting `$255' to the operand value, which like with 13136 `GETA' must be a multiple of four, and a final `GO $255,$255,0'. 13137 13138`PUSHJ' 13139 Similar to expansion for conditional branches; four instructions 13140 set `$255' to the operand value, followed by a `PUSHGO 13141 $255,$255,0'. 13142 13143`JMP' 13144 Similar to conditional branches and `PUSHJ'. The final instruction 13145 is `GO $255,$255,0'. 13146 13147 The linker `ld' is expected to shrink these expansions for code 13148assembled with `--relax' (though not currently implemented). 13149 13150 13151File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 13152 131539.25.3 Syntax 13154------------- 13155 13156The assembly syntax is supposed to be upward compatible with that 13157described in Sections 1.3 and 1.4 of `The Art of Computer Programming, 13158Volume 1'. Draft versions of those chapters as well as other MMIX 13159information is located at 13160`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code 13161examples from the mmixal package located there should work unmodified 13162when assembled and linked as single files, with a few noteworthy 13163exceptions (*note MMIX-mmixal::). 13164 13165 Before an instruction is emitted, the current location is aligned to 13166the next four-byte boundary. If a label is defined at the beginning of 13167the line, its value will be the aligned value. 13168 13169 In addition to the traditional hex-prefix `0x', a hexadecimal number 13170can also be specified by the prefix character `#'. 13171 13172 After all operands to an MMIX instruction or directive have been 13173specified, the rest of the line is ignored, treated as a comment. 13174 13175* Menu: 13176 13177* MMIX-Chars:: Special Characters 13178* MMIX-Symbols:: Symbols 13179* MMIX-Regs:: Register Names 13180* MMIX-Pseudos:: Assembler Directives 13181 13182 13183File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 13184 131859.25.3.1 Special Characters 13186........................... 13187 13188The characters `*' and `#' are line comment characters; each start a 13189comment at the beginning of a line, but only at the beginning of a 13190line. A `#' prefixes a hexadecimal number if found elsewhere on a line. 13191 13192 Two other characters, `%' and `!', each start a comment anywhere on 13193the line. Thus you can't use the `modulus' and `not' operators in 13194expressions normally associated with these two characters. 13195 13196 A `;' is a line separator, treated as a new-line, so separate 13197instructions can be specified on a single line. 13198 13199 13200File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 13201 132029.25.3.2 Symbols 13203................ 13204 13205The character `:' is permitted in identifiers. There are two 13206exceptions to it being treated as any other symbol character: if a 13207symbol begins with `:', it means that the symbol is in the global 13208namespace and that the current prefix should not be prepended to that 13209symbol (*note MMIX-prefix::). The `:' is then not considered part of 13210the symbol. For a symbol in the label position (first on a line), a `:' 13211at the end of a symbol is silently stripped off. A label is permitted, 13212but not required, to be followed by a `:', as with many other assembly 13213formats. 13214 13215 The character `@' in an expression, is a synonym for `.', the 13216current location. 13217 13218 In addition to the common forward and backward local symbol formats 13219(*note Symbol Names::), they can be specified with upper-case `B' and 13220`F', as in `8B' and `9F'. A local label defined for the current 13221position is written with a `H' appended to the number: 13222 3H LDB $0,$1,2 13223 This and traditional local-label formats cannot be mixed: a label 13224must be defined and referred to using the same format. 13225 13226 There's a minor caveat: just as for the ordinary local symbols, the 13227local symbols are translated into ordinary symbols using control 13228characters are to hide the ordinal number of the symbol. 13229Unfortunately, these symbols are not translated back in error messages. 13230Thus you may see confusing error messages when local symbols are used. 13231Control characters `\003' (control-C) and `\004' (control-D) are used 13232for the MMIX-specific local-symbol syntax. 13233 13234 The symbol `Main' is handled specially; it is always global. 13235 13236 By defining the symbols `__.MMIX.start..text' and 13237`__.MMIX.start..data', the address of respectively the `.text' and 13238`.data' segments of the final program can be defined, though when 13239linking more than one object file, the code or data in the object file 13240containing the symbol is not guaranteed to be start at that position; 13241just the final executable. *Note MMIX-loc::. 13242 13243 13244File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 13245 132469.25.3.3 Register names 13247....................... 13248 13249Local and global registers are specified as `$0' to `$255'. The 13250recognized special register names are `rJ', `rA', `rB', `rC', `rD', 13251`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', 13252`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', 13253`rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special 13254register names. 13255 13256 Local and global symbols can be equated to register names and used in 13257place of ordinary registers. 13258 13259 Similarly for special registers, local and global symbols can be 13260used. Also, symbols equated from numbers and constant expressions are 13261allowed in place of a special register, except when either of the 13262options `--no-predefined-syms' and `--fixed-special-register-names' are 13263specified. Then only the special register names above are allowed for 13264the instructions having a special register operand; `GET' and `PUT'. 13265 13266 13267File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 13268 132699.25.3.4 Assembler Directives 13270............................. 13271 13272`LOC' 13273 The `LOC' directive sets the current location to the value of the 13274 operand field, which may include changing sections. If the 13275 operand is a constant, the section is set to either `.data' if the 13276 value is `0x2000000000000000' or larger, else it is set to `.text'. 13277 Within a section, the current location may only be changed to 13278 monotonically higher addresses. A LOC expression must be a 13279 previously defined symbol or a "pure" constant. 13280 13281 An example, which sets the label PREV to the current location, and 13282 updates the current location to eight bytes forward: 13283 prev LOC @+8 13284 13285 When a LOC has a constant as its operand, a symbol 13286 `__.MMIX.start..text' or `__.MMIX.start..data' is defined 13287 depending on the address as mentioned above. Each such symbol is 13288 interpreted as special by the linker, locating the section at that 13289 address. Note that if multiple files are linked, the first object 13290 file with that section will be mapped to that address (not 13291 necessarily the file with the LOC definition). 13292 13293`LOCAL' 13294 Example: 13295 LOCAL external_symbol 13296 LOCAL 42 13297 .local asymbol 13298 13299 This directive-operation generates a link-time assertion that the 13300 operand does not correspond to a global register. The operand is 13301 an expression that at link-time resolves to a register symbol or a 13302 number. A number is treated as the register having that number. 13303 There is one restriction on the use of this directive: the 13304 pseudo-directive must be placed in a section with contents, code 13305 or data. 13306 13307`IS' 13308 The `IS' directive: 13309 asymbol IS an_expression 13310 sets the symbol `asymbol' to `an_expression'. A symbol may not be 13311 set more than once using this directive. Local labels may be set 13312 using this directive, for example: 13313 5H IS @+4 13314 13315`GREG' 13316 This directive reserves a global register, gives it an initial 13317 value and optionally gives it a symbolic name. Some examples: 13318 13319 areg GREG 13320 breg GREG data_value 13321 GREG data_buffer 13322 .greg creg, another_data_value 13323 13324 The symbolic register name can be used in place of a (non-special) 13325 register. If a value isn't provided, it defaults to zero. Unless 13326 the option `--no-merge-gregs' is specified, non-zero registers 13327 allocated with this directive may be eliminated by `as'; another 13328 register with the same value used in its place. Any of the 13329 instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', 13330 `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', 13331 `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', 13332 `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can 13333 have a value nearby an initial value in place of its second and 13334 third operands. Here, "nearby" is defined as within the range 13335 0...255 from the initial value of such an allocated register. 13336 13337 buffer1 BYTE 0,0,0,0,0 13338 buffer2 BYTE 0,0,0,0,0 13339 ... 13340 GREG buffer1 13341 LDOU $42,buffer2 13342 In the example above, the `Y' field of the `LDOUI' instruction 13343 (LDOU with a constant Z) will be replaced with the global register 13344 allocated for `buffer1', and the `Z' field will have the value 5, 13345 the offset from `buffer1' to `buffer2'. The result is equivalent 13346 to this code: 13347 buffer1 BYTE 0,0,0,0,0 13348 buffer2 BYTE 0,0,0,0,0 13349 ... 13350 tmpreg GREG buffer1 13351 LDOU $42,tmpreg,(buffer2-buffer1) 13352 13353 Global registers allocated with this directive are allocated in 13354 order higher-to-lower within a file. Other than that, the exact 13355 order of register allocation and elimination is undefined. For 13356 example, the order is undefined when more than one file with such 13357 directives are linked together. With the options `-x' and 13358 `--linker-allocated-gregs', `GREG' directives for two-operand 13359 cases like the one mentioned above can be omitted. Sufficient 13360 global registers will then be allocated by the linker. 13361 13362`BYTE' 13363 The `BYTE' directive takes a series of operands separated by a 13364 comma. If an operand is a string (*note Strings::), each 13365 character of that string is emitted as a byte. Other operands 13366 must be constant expressions without forward references, in the 13367 range 0...255. If you need operands having expressions with 13368 forward references, use `.byte' (*note Byte::). An operand can be 13369 omitted, defaulting to a zero value. 13370 13371`WYDE' 13372`TETRA' 13373`OCTA' 13374 The directives `WYDE', `TETRA' and `OCTA' emit constants of two, 13375 four and eight bytes size respectively. Before anything else 13376 happens for the directive, the current location is aligned to the 13377 respective constant-size boundary. If a label is defined at the 13378 beginning of the line, its value will be that after the alignment. 13379 A single operand can be omitted, defaulting to a zero value 13380 emitted for the directive. Operands can be expressed as strings 13381 (*note Strings::), in which case each character in the string is 13382 emitted as a separate constant of the size indicated by the 13383 directive. 13384 13385`PREFIX' 13386 The `PREFIX' directive sets a symbol name prefix to be prepended to 13387 all symbols (except local symbols, *note MMIX-Symbols::), that are 13388 not prefixed with `:', until the next `PREFIX' directive. Such 13389 prefixes accumulate. For example, 13390 PREFIX a 13391 PREFIX b 13392 c IS 0 13393 defines a symbol `abc' with the value 0. 13394 13395`BSPEC' 13396`ESPEC' 13397 A pair of `BSPEC' and `ESPEC' directives delimit a section of 13398 special contents (without specified semantics). Example: 13399 BSPEC 42 13400 TETRA 1,2,3 13401 ESPEC 13402 The single operand to `BSPEC' must be number in the range 0...255. 13403 The `BSPEC' number 80 is used by the GNU binutils implementation. 13404 13405 13406File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 13407 134089.25.4 Differences to `mmixal' 13409------------------------------ 13410 13411The binutils `as' and `ld' combination has a few differences in 13412function compared to `mmixal' (*note mmixsite::). 13413 13414 The replacement of a symbol with a GREG-allocated register (*note 13415GREG-base::) is not handled the exactly same way in `as' as in 13416`mmixal'. This is apparent in the `mmixal' example file `inout.mms', 13417where different registers with different offsets, eventually yielding 13418the same address, are used in the first instruction. This type of 13419difference should however not affect the function of any program unless 13420it has specific assumptions about the allocated register number. 13421 13422 Line numbers (in the `mmo' object format) are currently not 13423supported. 13424 13425 Expression operator precedence is not that of mmixal: operator 13426precedence is that of the C programming language. It's recommended to 13427use parentheses to explicitly specify wanted operator precedence 13428whenever more than one type of operators are used. 13429 13430 The serialize unary operator `&', the fractional division operator 13431`//', the logical not operator `!' and the modulus operator `%' are not 13432available. 13433 13434 Symbols are not global by default, unless the option 13435`--globalize-symbols' is passed. Use the `.global' directive to 13436globalize symbols (*note Global::). 13437 13438 Operand syntax is a bit stricter with `as' than `mmixal'. For 13439example, you can't say `addu 1,2,3', instead you must write `addu 13440$1,$2,3'. 13441 13442 You can't LOC to a lower address than those already visited (i.e., 13443"backwards"). 13444 13445 A LOC directive must come before any emitted code. 13446 13447 Predefined symbols are visible as file-local symbols after use. (In 13448the ELF file, that is--the linked mmo file has no notion of a file-local 13449symbol.) 13450 13451 Some mapping of constant expressions to sections in LOC expressions 13452is attempted, but that functionality is easily confused and should be 13453avoided unless compatibility with `mmixal' is required. A LOC 13454expression to `0x2000000000000000' or higher, maps to the `.data' 13455section and lower addresses map to the `.text' section (*note 13456MMIX-loc::). 13457 13458 The code and data areas are each contiguous. Sparse programs with 13459far-away LOC directives will take up the same amount of space as a 13460contiguous program with zeros filled in the gaps between the LOC 13461directives. If you need sparse programs, you might try and get the 13462wanted effect with a linker script and splitting up the code parts into 13463sections (*note Section::). Assembly code for this, to be compatible 13464with `mmixal', would look something like: 13465 .if 0 13466 LOC away_expression 13467 .else 13468 .section away,"ax" 13469 .fi 13470 `as' will not execute the LOC directive and `mmixal' ignores the 13471lines with `.'. This construct can be used generally to help 13472compatibility. 13473 13474 Symbols can't be defined twice-not even to the same value. 13475 13476 Instruction mnemonics are recognized case-insensitive, though the 13477`IS' and `GREG' pseudo-operations must be specified in upper-case 13478characters. 13479 13480 There's no unicode support. 13481 13482 The following is a list of programs in `mmix.tar.gz', available at 13483`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last 13484checked with the version dated 2001-08-25 (md5sum 13485c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do 13486not assemble with `as': 13487 13488`silly.mms' 13489 LOC to a previous address. 13490 13491`sim.mms' 13492 Redefines symbol `Done'. 13493 13494`test.mms' 13495 Uses the serial operator `&'. 13496 13497 13498File: as.info, Node: MSP430-Dependent, Next: SH-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 13499 135009.26 MSP 430 Dependent Features 13501=============================== 13502 13503* Menu: 13504 13505* MSP430 Options:: Options 13506* MSP430 Syntax:: Syntax 13507* MSP430 Floating Point:: Floating Point 13508* MSP430 Directives:: MSP 430 Machine Directives 13509* MSP430 Opcodes:: Opcodes 13510* MSP430 Profiling Capability:: Profiling Capability 13511 13512 13513File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 13514 135159.26.1 Options 13516-------------- 13517 13518`-m' 13519 select the mpu arch. Currently has no effect. 13520 13521`-mP' 13522 enables polymorph instructions handler. 13523 13524`-mQ' 13525 enables relaxation at assembly time. DANGEROUS! 13526 13527 13528 13529File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 13530 135319.26.2 Syntax 13532------------- 13533 13534* Menu: 13535 13536* MSP430-Macros:: Macros 13537* MSP430-Chars:: Special Characters 13538* MSP430-Regs:: Register Names 13539* MSP430-Ext:: Assembler Extensions 13540 13541 13542File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 13543 135449.26.2.1 Macros 13545............... 13546 13547The macro syntax used on the MSP 430 is like that described in the MSP 13548430 Family Assembler Specification. Normal `as' macros should still 13549work. 13550 13551 Additional built-in macros are: 13552 13553`llo(exp)' 13554 Extracts least significant word from 32-bit expression 'exp'. 13555 13556`lhi(exp)' 13557 Extracts most significant word from 32-bit expression 'exp'. 13558 13559`hlo(exp)' 13560 Extracts 3rd word from 64-bit expression 'exp'. 13561 13562`hhi(exp)' 13563 Extracts 4rd word from 64-bit expression 'exp'. 13564 13565 13566 They normally being used as an immediate source operand. 13567 mov #llo(1), r10 ; == mov #1, r10 13568 mov #lhi(1), r10 ; == mov #0, r10 13569 13570 13571File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 13572 135739.26.2.2 Special Characters 13574........................... 13575 13576`;' is the line comment character. 13577 13578 The character `$' in jump instructions indicates current location and 13579implemented only for TI syntax compatibility. 13580 13581 13582File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 13583 135849.26.2.3 Register Names 13585....................... 13586 13587General-purpose registers are represented by predefined symbols of the 13588form `rN' (for global registers), where N represents a number between 13589`0' and `15'. The leading letters may be in either upper or lower 13590case; for example, `r13' and `R7' are both valid register names. 13591 13592 Register names `PC', `SP' and `SR' cannot be used as register names 13593and will be treated as variables. Use `r0', `r1', and `r2' instead. 13594 13595 13596File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 13597 135989.26.2.4 Assembler Extensions 13599............................. 13600 13601`@rN' 13602 As destination operand being treated as `0(rn)' 13603 13604`0(rN)' 13605 As source operand being treated as `@rn' 13606 13607`jCOND +N' 13608 Skips next N bytes followed by jump instruction and equivalent to 13609 `jCOND $+N+2' 13610 13611 13612 Also, there are some instructions, which cannot be found in other 13613assemblers. These are branch instructions, which has different opcodes 13614upon jump distance. They all got PC relative addressing mode. 13615 13616`beq label' 13617 A polymorph instruction which is `jeq label' in case if jump 13618 distance within allowed range for cpu's jump instruction. If not, 13619 this unrolls into a sequence of 13620 jne $+6 13621 br label 13622 13623`bne label' 13624 A polymorph instruction which is `jne label' or `jeq +4; br label' 13625 13626`blt label' 13627 A polymorph instruction which is `jl label' or `jge +4; br label' 13628 13629`bltn label' 13630 A polymorph instruction which is `jn label' or `jn +2; jmp +4; br 13631 label' 13632 13633`bltu label' 13634 A polymorph instruction which is `jlo label' or `jhs +2; br label' 13635 13636`bge label' 13637 A polymorph instruction which is `jge label' or `jl +4; br label' 13638 13639`bgeu label' 13640 A polymorph instruction which is `jhs label' or `jlo +4; br label' 13641 13642`bgt label' 13643 A polymorph instruction which is `jeq +2; jge label' or `jeq +6; 13644 jl +4; br label' 13645 13646`bgtu label' 13647 A polymorph instruction which is `jeq +2; jhs label' or `jeq +6; 13648 jlo +4; br label' 13649 13650`bleu label' 13651 A polymorph instruction which is `jeq label; jlo label' or `jeq 13652 +2; jhs +4; br label' 13653 13654`ble label' 13655 A polymorph instruction which is `jeq label; jl label' or `jeq 13656 +2; jge +4; br label' 13657 13658`jump label' 13659 A polymorph instruction which is `jmp label' or `br label' 13660 13661 13662File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 13663 136649.26.3 Floating Point 13665--------------------- 13666 13667The MSP 430 family uses IEEE 32-bit floating-point numbers. 13668 13669 13670File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 13671 136729.26.4 MSP 430 Machine Directives 13673--------------------------------- 13674 13675`.file' 13676 This directive is ignored; it is accepted for compatibility with 13677 other MSP 430 assemblers. 13678 13679 _Warning:_ in other versions of the GNU assembler, `.file' is 13680 used for the directive called `.app-file' in the MSP 430 13681 support. 13682 13683`.line' 13684 This directive is ignored; it is accepted for compatibility with 13685 other MSP 430 assemblers. 13686 13687`.arch' 13688 Currently this directive is ignored; it is accepted for 13689 compatibility with other MSP 430 assemblers. 13690 13691`.profiler' 13692 This directive instructs assembler to add new profile entry to the 13693 object file. 13694 13695 13696 13697File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 13698 136999.26.5 Opcodes 13700-------------- 13701 13702`as' implements all the standard MSP 430 opcodes. No additional 13703pseudo-instructions are needed on this family. 13704 13705 For information on the 430 machine instruction set, see `MSP430 13706User's Manual, document slau049d', Texas Instrument, Inc. 13707 13708 13709File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 13710 137119.26.6 Profiling Capability 13712--------------------------- 13713 13714It is a performance hit to use gcc's profiling approach for this tiny 13715target. Even more - jtag hardware facility does not perform any 13716profiling functions. However we've got gdb's built-in simulator where 13717we can do anything. 13718 13719 We define new section `.profiler' which holds all profiling 13720information. We define new pseudo operation `.profiler' which will 13721instruct assembler to add new profile entry to the object file. Profile 13722should take place at the present address. 13723 13724 Pseudo operation format: 13725 13726 `.profiler flags,function_to_profile [, cycle_corrector, extra]' 13727 13728 where: 13729 13730 `flags' is a combination of the following characters: 13731 13732 `s' 13733 function entry 13734 13735 `x' 13736 function exit 13737 13738 `i' 13739 function is in init section 13740 13741 `f' 13742 function is in fini section 13743 13744 `l' 13745 library call 13746 13747 `c' 13748 libc standard call 13749 13750 `d' 13751 stack value demand 13752 13753 `I' 13754 interrupt service routine 13755 13756 `P' 13757 prologue start 13758 13759 `p' 13760 prologue end 13761 13762 `E' 13763 epilogue start 13764 13765 `e' 13766 epilogue end 13767 13768 `j' 13769 long jump / sjlj unwind 13770 13771 `a' 13772 an arbitrary code fragment 13773 13774 `t' 13775 extra parameter saved (a constant value like frame size) 13776 13777`function_to_profile' 13778 a function address 13779 13780`cycle_corrector' 13781 a value which should be added to the cycle counter, zero if 13782 omitted. 13783 13784`extra' 13785 any extra parameter, zero if omitted. 13786 13787 13788 For example: 13789 .global fxx 13790 .type fxx,@function 13791 fxx: 13792 .LFrameOffset_fxx=0x08 13793 .profiler "scdP", fxx ; function entry. 13794 ; we also demand stack value to be saved 13795 push r11 13796 push r10 13797 push r9 13798 push r8 13799 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 13800 ; (this is a prologue end) 13801 ; note, that spare var filled with 13802 ; the farme size 13803 mov r15,r8 13804 ... 13805 .profiler cdE,fxx ; check stack 13806 pop r8 13807 pop r9 13808 pop r10 13809 pop r11 13810 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 13811 ret ; cause 'ret' insn takes 3 cycles 13812 13813 13814File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies 13815 138169.27 PDP-11 Dependent Features 13817============================== 13818 13819* Menu: 13820 13821* PDP-11-Options:: Options 13822* PDP-11-Pseudos:: Assembler Directives 13823* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 13824* PDP-11-Mnemonics:: Instruction Naming 13825* PDP-11-Synthetic:: Synthetic Instructions 13826 13827 13828File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 13829 138309.27.1 Options 13831-------------- 13832 13833The PDP-11 version of `as' has a rich set of machine dependent options. 13834 138359.27.1.1 Code Generation Options 13836................................ 13837 13838`-mpic | -mno-pic' 13839 Generate position-independent (or position-dependent) code. 13840 13841 The default is to generate position-independent code. 13842 138439.27.1.2 Instruction Set Extension Options 13844.......................................... 13845 13846These options enables or disables the use of extensions over the base 13847line instruction set as introduced by the first PDP-11 CPU: the KA11. 13848Most options come in two variants: a `-m'EXTENSION that enables 13849EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. 13850 13851 The default is to enable all extensions. 13852 13853`-mall | -mall-extensions' 13854 Enable all instruction set extensions. 13855 13856`-mno-extensions' 13857 Disable all instruction set extensions. 13858 13859`-mcis | -mno-cis' 13860 Enable (or disable) the use of the commercial instruction set, 13861 which consists of these instructions: `ADDNI', `ADDN', `ADDPI', 13862 `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC', 13863 `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI', 13864 `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL', 13865 `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI', 13866 `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC', 13867 `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI', 13868 `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'. 13869 13870`-mcsm | -mno-csm' 13871 Enable (or disable) the use of the `CSM' instruction. 13872 13873`-meis | -mno-eis' 13874 Enable (or disable) the use of the extended instruction set, which 13875 consists of these instructions: `ASHC', `ASH', `DIV', `MARK', 13876 `MUL', `RTT', `SOB' `SXT', and `XOR'. 13877 13878`-mfis | -mkev11' 13879`-mno-fis | -mno-kev11' 13880 Enable (or disable) the use of the KEV11 floating-point 13881 instructions: `FADD', `FDIV', `FMUL', and `FSUB'. 13882 13883`-mfpp | -mfpu | -mfp-11' 13884`-mno-fpp | -mno-fpu | -mno-fp-11' 13885 Enable (or disable) the use of FP-11 floating-point instructions: 13886 `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF', 13887 `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF', 13888 `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST', 13889 `SUBF', and `TSTF'. 13890 13891`-mlimited-eis | -mno-limited-eis' 13892 Enable (or disable) the use of the limited extended instruction 13893 set: `MARK', `RTT', `SOB', `SXT', and `XOR'. 13894 13895 The -mno-limited-eis options also implies -mno-eis. 13896 13897`-mmfpt | -mno-mfpt' 13898 Enable (or disable) the use of the `MFPT' instruction. 13899 13900`-mmultiproc | -mno-multiproc' 13901 Enable (or disable) the use of multiprocessor instructions: 13902 `TSTSET' and `WRTLCK'. 13903 13904`-mmxps | -mno-mxps' 13905 Enable (or disable) the use of the `MFPS' and `MTPS' instructions. 13906 13907`-mspl | -mno-spl' 13908 Enable (or disable) the use of the `SPL' instruction. 13909 13910 Enable (or disable) the use of the microcode instructions: `LDUB', 13911 `MED', and `XFC'. 13912 139139.27.1.3 CPU Model Options 13914.......................... 13915 13916These options enable the instruction set extensions supported by a 13917particular CPU, and disables all other extensions. 13918 13919`-mka11' 13920 KA11 CPU. Base line instruction set only. 13921 13922`-mkb11' 13923 KB11 CPU. Enable extended instruction set and `SPL'. 13924 13925`-mkd11a' 13926 KD11-A CPU. Enable limited extended instruction set. 13927 13928`-mkd11b' 13929 KD11-B CPU. Base line instruction set only. 13930 13931`-mkd11d' 13932 KD11-D CPU. Base line instruction set only. 13933 13934`-mkd11e' 13935 KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'. 13936 13937`-mkd11f | -mkd11h | -mkd11q' 13938 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended 13939 instruction set, `MFPS', and `MTPS'. 13940 13941`-mkd11k' 13942 KD11-K CPU. Enable extended instruction set, `LDUB', `MED', 13943 `MFPS', `MFPT', `MTPS', and `XFC'. 13944 13945`-mkd11z' 13946 KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS', 13947 `MFPT', `MTPS', and `SPL'. 13948 13949`-mf11' 13950 F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and 13951 `MTPS'. 13952 13953`-mj11' 13954 J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT', 13955 `MTPS', `SPL', `TSTSET', and `WRTLCK'. 13956 13957`-mt11' 13958 T11 CPU. Enable limited extended instruction set, `MFPS', and 13959 `MTPS'. 13960 139619.27.1.4 Machine Model Options 13962.............................. 13963 13964These options enable the instruction set extensions supported by a 13965particular machine model, and disables all other extensions. 13966 13967`-m11/03' 13968 Same as `-mkd11f'. 13969 13970`-m11/04' 13971 Same as `-mkd11d'. 13972 13973`-m11/05 | -m11/10' 13974 Same as `-mkd11b'. 13975 13976`-m11/15 | -m11/20' 13977 Same as `-mka11'. 13978 13979`-m11/21' 13980 Same as `-mt11'. 13981 13982`-m11/23 | -m11/24' 13983 Same as `-mf11'. 13984 13985`-m11/34' 13986 Same as `-mkd11e'. 13987 13988`-m11/34a' 13989 Ame as `-mkd11e' `-mfpp'. 13990 13991`-m11/35 | -m11/40' 13992 Same as `-mkd11a'. 13993 13994`-m11/44' 13995 Same as `-mkd11z'. 13996 13997`-m11/45 | -m11/50 | -m11/55 | -m11/70' 13998 Same as `-mkb11'. 13999 14000`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 14001 Same as `-mj11'. 14002 14003`-m11/60' 14004 Same as `-mkd11k'. 14005 14006 14007File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 14008 140099.27.2 Assembler Directives 14010--------------------------- 14011 14012The PDP-11 version of `as' has a few machine dependent assembler 14013directives. 14014 14015`.bss' 14016 Switch to the `bss' section. 14017 14018`.even' 14019 Align the location counter to an even number. 14020 14021 14022File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 14023 140249.27.3 PDP-11 Assembly Language Syntax 14025-------------------------------------- 14026 14027`as' supports both DEC syntax and BSD syntax. The only difference is 14028that in DEC syntax, a `#' character is used to denote an immediate 14029constants, while in BSD syntax the character for this purpose is `$'. 14030 14031 general-purpose registers are named `r0' through `r7'. Mnemonic 14032alternatives for `r6' and `r7' are `sp' and `pc', respectively. 14033 14034 Floating-point registers are named `ac0' through `ac3', or 14035alternatively `fr0' through `fr3'. 14036 14037 Comments are started with a `#' or a `/' character, and extend to 14038the end of the line. (FIXME: clash with immediates?) 14039 14040 14041File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 14042 140439.27.4 Instruction Naming 14044------------------------- 14045 14046Some instructions have alternative names. 14047 14048`BCC' 14049 `BHIS' 14050 14051`BCS' 14052 `BLO' 14053 14054`L2DR' 14055 `L2D' 14056 14057`L3DR' 14058 `L3D' 14059 14060`SYS' 14061 `TRAP' 14062 14063 14064File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 14065 140669.27.5 Synthetic Instructions 14067----------------------------- 14068 14069The `JBR' and `J'CC synthetic instructions are not supported yet. 14070 14071 14072File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 14073 140749.28 picoJava Dependent Features 14075================================ 14076 14077* Menu: 14078 14079* PJ Options:: Options 14080 14081 14082File: as.info, Node: PJ Options, Up: PJ-Dependent 14083 140849.28.1 Options 14085-------------- 14086 14087`as' has two additional command-line options for the picoJava 14088architecture. 14089`-ml' 14090 This option selects little endian data output. 14091 14092`-mb' 14093 This option selects big endian data output. 14094 14095 14096File: as.info, Node: PPC-Dependent, Next: RX-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 14097 140989.29 PowerPC Dependent Features 14099=============================== 14100 14101* Menu: 14102 14103* PowerPC-Opts:: Options 14104* PowerPC-Pseudo:: PowerPC Assembler Directives 14105 14106 14107File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 14108 141099.29.1 Options 14110-------------- 14111 14112The PowerPC chip family includes several successive levels, using the 14113same core instruction set, but including a few additional instructions 14114at each level. There are exceptions to this however. For details on 14115what instructions each variant supports, please see the chip's 14116architecture reference manual. 14117 14118 The following table lists all available PowerPC options. 14119 14120`-a32' 14121 Generate ELF32 or XCOFF32. 14122 14123`-a64' 14124 Generate ELF64 or XCOFF64. 14125 14126`-K PIC' 14127 Set EF_PPC_RELOCATABLE_LIB in ELF flags. 14128 14129`-mpwrx | -mpwr2' 14130 Generate code for POWER/2 (RIOS2). 14131 14132`-mpwr' 14133 Generate code for POWER (RIOS1) 14134 14135`-m601' 14136 Generate code for PowerPC 601. 14137 14138`-mppc, -mppc32, -m603, -m604' 14139 Generate code for PowerPC 603/604. 14140 14141`-m403, -m405' 14142 Generate code for PowerPC 403/405. 14143 14144`-m440' 14145 Generate code for PowerPC 440. BookE and some 405 instructions. 14146 14147`-m464' 14148 Generate code for PowerPC 464. 14149 14150`-m476' 14151 Generate code for PowerPC 476. 14152 14153`-m7400, -m7410, -m7450, -m7455' 14154 Generate code for PowerPC 7400/7410/7450/7455. 14155 14156`-m750cl' 14157 Generate code for PowerPC 750CL. 14158 14159`-mppc64, -m620' 14160 Generate code for PowerPC 620/625/630. 14161 14162`-me500, -me500x2' 14163 Generate code for Motorola e500 core complex. 14164 14165`-me500mc' 14166 Generate code for Freescale e500mc core complex. 14167 14168`-me500mc64' 14169 Generate code for Freescale e500mc64 core complex. 14170 14171`-mspe' 14172 Generate code for Motorola SPE instructions. 14173 14174`-mtitan' 14175 Generate code for AppliedMicro Titan core complex. 14176 14177`-mppc64bridge' 14178 Generate code for PowerPC 64, including bridge insns. 14179 14180`-mbooke' 14181 Generate code for 32-bit BookE. 14182 14183`-ma2' 14184 Generate code for A2 architecture. 14185 14186`-me300' 14187 Generate code for PowerPC e300 family. 14188 14189`-maltivec' 14190 Generate code for processors with AltiVec instructions. 14191 14192`-mvsx' 14193 Generate code for processors with Vector-Scalar (VSX) instructions. 14194 14195`-mpower4, -mpwr4' 14196 Generate code for Power4 architecture. 14197 14198`-mpower5, -mpwr5, -mpwr5x' 14199 Generate code for Power5 architecture. 14200 14201`-mpower6, -mpwr6' 14202 Generate code for Power6 architecture. 14203 14204`-mpower7, -mpwr7' 14205 Generate code for Power7 architecture. 14206 14207`-mcell' 14208 Generate code for Cell Broadband Engine architecture. 14209 14210`-mcom' 14211 Generate code Power/PowerPC common instructions. 14212 14213`-many' 14214 Generate code for any architecture (PWR/PWRX/PPC). 14215 14216`-mregnames' 14217 Allow symbolic names for registers. 14218 14219`-mno-regnames' 14220 Do not allow symbolic names for registers. 14221 14222`-mrelocatable' 14223 Support for GCC's -mrelocatable option. 14224 14225`-mrelocatable-lib' 14226 Support for GCC's -mrelocatable-lib option. 14227 14228`-memb' 14229 Set PPC_EMB bit in ELF flags. 14230 14231`-mlittle, -mlittle-endian, -le' 14232 Generate code for a little endian machine. 14233 14234`-mbig, -mbig-endian, -be' 14235 Generate code for a big endian machine. 14236 14237`-msolaris' 14238 Generate code for Solaris. 14239 14240`-mno-solaris' 14241 Do not generate code for Solaris. 14242 14243`-nops=COUNT' 14244 If an alignment directive inserts more than COUNT nops, put a 14245 branch at the beginning to skip execution of the nops. 14246 14247 14248File: as.info, Node: PowerPC-Pseudo, Prev: PowerPC-Opts, Up: PPC-Dependent 14249 142509.29.2 PowerPC Assembler Directives 14251----------------------------------- 14252 14253A number of assembler directives are available for PowerPC. The 14254following table is far from complete. 14255 14256`.machine "string"' 14257 This directive allows you to change the machine for which code is 14258 generated. `"string"' may be any of the -m cpu selection options 14259 (without the -m) enclosed in double quotes, `"push"', or `"pop"'. 14260 `.machine "push"' saves the currently selected cpu, which may be 14261 restored with `.machine "pop"'. 14262 14263 14264File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 14265 142669.30 RX Dependent Features 14267========================== 14268 14269* Menu: 14270 14271* RX-Opts:: RX Assembler Command Line Options 14272* RX-Modifiers:: Symbolic Operand Modifiers 14273* RX-Directives:: Assembler Directives 14274* RX-Float:: Floating Point 14275 14276 14277File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 14278 142799.30.1 RX Options 14280----------------- 14281 14282The Renesas RX port of `as' has a few target specfic command line 14283options: 14284 14285`-m32bit-doubles' 14286 This option controls the ABI and indicates to use a 32-bit float 14287 ABI. It has no effect on the assembled instructions, but it does 14288 influence the behaviour of the `.double' pseudo-op. This is the 14289 default. 14290 14291`-m64bit-doubles' 14292 This option controls the ABI and indicates to use a 64-bit float 14293 ABI. It has no effect on the assembled instructions, but it does 14294 influence the behaviour of the `.double' pseudo-op. 14295 14296`-mbig-endian' 14297 This option controls the ABI and indicates to use a big-endian data 14298 ABI. It has no effect on the assembled instructions, but it does 14299 influence the behaviour of the `.short', `.hword', `.int', 14300 `.word', `.long', `.quad' and `.octa' pseudo-ops. 14301 14302`-mlittle-endian' 14303 This option controls the ABI and indicates to use a little-endian 14304 data ABI. It has no effect on the assembled instructions, but it 14305 does influence the behaviour of the `.short', `.hword', `.int', 14306 `.word', `.long', `.quad' and `.octa' pseudo-ops. This is the 14307 default. 14308 14309`-muse-conventional-section-names' 14310 This option controls the default names given to the code (.text), 14311 initialised data (.data) and uninitialised data sections (.bss). 14312 14313`-muse-renesas-section-names' 14314 This option controls the default names given to the code (.P), 14315 initialised data (.D_1) and uninitialised data sections (.B_1). 14316 This is the default. 14317 14318`-msmall-data-limit' 14319 This option tells the assembler that the small data limit feature 14320 of the RX port of GCC is being used. This results in the assembler 14321 generating an undefined reference to a symbol called __gp for use 14322 by the relocations that are needed to support the small data limit 14323 feature. This option is not enabled by default as it would 14324 otherwise pollute the symbol table. 14325 14326 14327 14328File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 14329 143309.30.2 Symbolic Operand Modifiers 14331--------------------------------- 14332 14333The assembler supports several modifiers when using symbol addresses in 14334RX instruction operands. The general syntax is the following: 14335 14336 %modifier(symbol) 14337 14338`%gp' 14339 14340 14341File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 14342 143439.30.3 Assembler Directives 14344--------------------------- 14345 14346The RX version of `as' has the following specific assembler directives: 14347 14348`.3byte' 14349 Inserts a 3-byte value into the output file at the current 14350 location. 14351 14352 14353 14354File: as.info, Node: RX-Float, Prev: RX-Directives, Up: RX-Dependent 14355 143569.30.4 Floating Point 14357--------------------- 14358 14359The floating point formats generated by directives are these. 14360 14361`.float' 14362 `Single' precision (32-bit) floating point constants. 14363 14364`.double' 14365 If the `-m64bit-doubles' command line option has been specified 14366 then then `double' directive generates `double' precision (64-bit) 14367 floating point constants, otherwise it generates `single' 14368 precision (32-bit) floating point constants. To force the 14369 generation of 64-bit floating point constants used the `dc.d' 14370 directive instead. 14371 14372 14373 14374File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 14375 143769.31 IBM S/390 Dependent Features 14377================================= 14378 14379 The s390 version of `as' supports two architectures modes and seven 14380chip levels. The architecture modes are the Enterprise System 14381Architecture (ESA) and the newer z/Architecture mode. The chip levels 14382are g5, g6, z900, z990, z9-109, z9-ec, z10 and z196. 14383 14384* Menu: 14385 14386* s390 Options:: Command-line Options. 14387* s390 Characters:: Special Characters. 14388* s390 Syntax:: Assembler Instruction syntax. 14389* s390 Directives:: Assembler Directives. 14390* s390 Floating Point:: Floating Point. 14391 14392 14393File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 14394 143959.31.1 Options 14396-------------- 14397 14398The following table lists all available s390 specific options: 14399 14400`-m31 | -m64' 14401 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 14402 14403 These options are only available with the ELF object file format, 14404 and require that the necessary BFD support has been included (on a 14405 31-bit platform you must add -enable-64-bit-bfd on the call to the 14406 configure script to enable 64-bit usage and use s390x as target 14407 platform). 14408 14409`-mesa | -mzarch' 14410 Select the architecture mode, either the Enterprise System 14411 Architecture (esa) mode or the z/Architecture mode (zarch). 14412 14413 The 64-bit instructions are only available with the z/Architecture 14414 mode. The combination of `-m64' and `-mesa' results in a warning 14415 message. 14416 14417`-march=CPU' 14418 This option specifies the target processor. The following 14419 processor names are recognized: `g5', `g6', `z900', `z990', 14420 `z9-109', `z9-ec', `z10' and `z196'. Assembling an instruction 14421 that is not supported on the target processor results in an error 14422 message. Do not specify `g5' or `g6' with `-mzarch'. 14423 14424`-mregnames' 14425 Allow symbolic names for registers. 14426 14427`-mno-regnames' 14428 Do not allow symbolic names for registers. 14429 14430`-mwarn-areg-zero' 14431 Warn whenever the operand for a base or index register has been 14432 specified but evaluates to zero. This can indicate the misuse of 14433 general purpose register 0 as an address register. 14434 14435 14436 14437File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 14438 144399.31.2 Special Characters 14440------------------------- 14441 14442`#' is the line comment character. 14443 14444 14445File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 14446 144479.31.3 Instruction syntax 14448------------------------- 14449 14450The assembler syntax closely follows the syntax outlined in Enterprise 14451Systems Architecture/390 Principles of Operation (SA22-7201) and the 14452z/Architecture Principles of Operation (SA22-7832). 14453 14454 Each instruction has two major parts, the instruction mnemonic and 14455the instruction operands. The instruction format varies. 14456 14457* Menu: 14458 14459* s390 Register:: Register Naming 14460* s390 Mnemonics:: Instruction Mnemonics 14461* s390 Operands:: Instruction Operands 14462* s390 Formats:: Instruction Formats 14463* s390 Aliases:: Instruction Aliases 14464* s390 Operand Modifier:: Instruction Operand Modifier 14465* s390 Instruction Marker:: Instruction Marker 14466* s390 Literal Pool Entries:: Literal Pool Entries 14467 14468 14469File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 14470 144719.31.3.1 Register naming 14472........................ 14473 14474The `as' recognizes a number of predefined symbols for the various 14475processor registers. A register specification in one of the instruction 14476formats is an unsigned integer between 0 and 15. The specific 14477instruction and the position of the register in the instruction format 14478denotes the type of the register. The register symbols are prefixed with 14479`%': 14480 14481 %rN the 16 general purpose registers, 0 <= N <= 15 14482 %fN the 16 floating point registers, 0 <= N <= 15 14483 %aN the 16 access registers, 0 <= N <= 15 14484 %cN the 16 control registers, 0 <= N <= 15 14485 %lit an alias for the general purpose register %r13 14486 %sp an alias for the general purpose register %r15 14487 14488 14489File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 14490 144919.31.3.2 Instruction Mnemonics 14492.............................. 14493 14494All instructions documented in the Principles of Operation are supported 14495with the mnemonic and order of operands as described. The instruction 14496mnemonic identifies the instruction format (*Note s390 Formats::) and 14497the specific operation code for the instruction. For example, the `lr' 14498mnemonic denotes the instruction format `RR' with the operation code 14499`0x18'. 14500 14501 The definition of the various mnemonics follows a scheme, where the 14502first character usually hint at the type of the instruction: 14503 14504 a add instruction, for example `al' for add logical 32-bit 14505 b branch instruction, for example `bc' for branch on condition 14506 c compare or convert instruction, for example `cr' for compare 14507 register 32-bit 14508 d divide instruction, for example `dlr' devide logical register 14509 64-bit to 32-bit 14510 i insert instruction, for example `ic' insert character 14511 l load instruction, for example `ltr' load and test register 14512 mv move instruction, for example `mvc' move character 14513 m multiply instruction, for example `mh' multiply halfword 14514 n and instruction, for example `ni' and immediate 14515 o or instruction, for example `oc' or character 14516 sla, sll shift left single instruction 14517 sra, srl shift right single instruction 14518 st store instruction, for example `stm' store multiple 14519 s subtract instruction, for example `slr' subtract 14520 logical 32-bit 14521 t test or translate instruction, of example `tm' test under mask 14522 x exclusive or instruction, for example `xc' exclusive or 14523 character 14524 14525 Certain characters at the end of the mnemonic may describe a property 14526of the instruction: 14527 14528 c the instruction uses a 8-bit character operand 14529 f the instruction extends a 32-bit operand to 64 bit 14530 g the operands are treated as 64-bit values 14531 h the operand uses a 16-bit halfword operand 14532 i the instruction uses an immediate operand 14533 l the instruction uses unsigned, logical operands 14534 m the instruction uses a mask or operates on multiple values 14535 r if r is the last character, the instruction operates on registers 14536 y the instruction uses 20-bit displacements 14537 14538 There are many exceptions to the scheme outlined in the above lists, 14539in particular for the priviledged instructions. For non-priviledged 14540instruction it works quite well, for example the instruction `clgfr' c: 14541compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- 14542to 64-bit extension, r: register operands. The instruction compares an 1454364-bit value in a register with the zero extended 32-bit value from a 14544second register. For a complete list of all mnemonics see appendix B 14545in the Principles of Operation. 14546 14547 14548File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 14549 145509.31.3.3 Instruction Operands 14551............................. 14552 14553Instruction operands can be grouped into three classes, operands located 14554in registers, immediate operands, and operands in storage. 14555 14556 A register operand can be located in general, floating-point, access, 14557or control register. The register is identified by a four-bit field. 14558The field containing the register operand is called the R field. 14559 14560 Immediate operands are contained within the instruction and can have 145618, 16 or 32 bits. The field containing the immediate operand is called 14562the I field. Dependent on the instruction the I field is either signed 14563or unsigned. 14564 14565 A storage operand consists of an address and a length. The address 14566of a storage operands can be specified in any of these ways: 14567 14568 * The content of a single general R 14569 14570 * The sum of the content of a general register called the base 14571 register B plus the content of a displacement field D 14572 14573 * The sum of the contents of two general registers called the index 14574 register X and the base register B plus the content of a 14575 displacement field 14576 14577 * The sum of the current instruction address and a 32-bit signed 14578 immediate field multiplied by two. 14579 14580 The length of a storage operand can be: 14581 14582 * Implied by the instruction 14583 14584 * Specified by a bitmask 14585 14586 * Specified by a four-bit or eight-bit length field L 14587 14588 * Specified by the content of a general register 14589 14590 The notation for storage operand addresses formed from multiple 14591fields is as follows: 14592 14593`Dn(Bn)' 14594 the address for operand number n is formed from the content of 14595 general register Bn called the base register and the displacement 14596 field Dn. 14597 14598`Dn(Xn,Bn)' 14599 the address for operand number n is formed from the content of 14600 general register Xn called the index register, general register Bn 14601 called the base register and the displacement field Dn. 14602 14603`Dn(Ln,Bn)' 14604 the address for operand number n is formed from the content of 14605 general regiser Bn called the base register and the displacement 14606 field Dn. The length of the operand n is specified by the field 14607 Ln. 14608 14609 The base registers Bn and the index registers Xn of a storage 14610operand can be skipped. If Bn and Xn are skipped, a zero will be stored 14611to the operand field. The notation changes as follows: 14612 14613 full notation short notation 14614 ------------------------------------------ 14615 Dn(0,Bn) Dn(Bn) 14616 Dn(0,0) Dn 14617 Dn(0) Dn 14618 Dn(Ln,0) Dn(Ln) 14619 14620 14621File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 14622 146239.31.3.4 Instruction Formats 14624............................ 14625 14626The Principles of Operation manuals lists 26 instruction formats where 14627some of the formats have multiple variants. For the `.insn' pseudo 14628directive the assembler recognizes some of the formats. Typically, the 14629most general variant of the instruction format is used by the `.insn' 14630directive. 14631 14632 The following table lists the abbreviations used in the table of 14633instruction formats: 14634 14635 OpCode / OpCd Part of the op code. 14636 Bx Base register number for operand x. 14637 Dx Displacement for operand x. 14638 DLx Displacement lower 12 bits for operand x. 14639 DHx Displacement higher 8-bits for operand x. 14640 Rx Register number for operand x. 14641 Xx Index register number for operand x. 14642 Ix Signed immediate for operand x. 14643 Ux Unsigned immediate for operand x. 14644 14645 An instruction is two, four, or six bytes in length and must be 14646aligned on a 2 byte boundary. The first two bits of the instruction 14647specify the length of the instruction, 00 indicates a two byte 14648instruction, 01 and 10 indicates a four byte instruction, and 11 14649indicates a six byte instruction. 14650 14651 The following table lists the s390 instruction formats that are 14652available with the `.insn' pseudo directive: 14653 14654`E format' 14655 14656 +-------------+ 14657 | OpCode | 14658 +-------------+ 14659 0 15 14660 14661`RI format: <insn> R1,I2' 14662 14663 +--------+----+----+------------------+ 14664 | OpCode | R1 |OpCd| I2 | 14665 +--------+----+----+------------------+ 14666 0 8 12 16 31 14667 14668`RIE format: <insn> R1,R3,I2' 14669 14670 +--------+----+----+------------------+--------+--------+ 14671 | OpCode | R1 | R3 | I2 |////////| OpCode | 14672 +--------+----+----+------------------+--------+--------+ 14673 0 8 12 16 32 40 47 14674 14675`RIL format: <insn> R1,I2' 14676 14677 +--------+----+----+------------------------------------+ 14678 | OpCode | R1 |OpCd| I2 | 14679 +--------+----+----+------------------------------------+ 14680 0 8 12 16 47 14681 14682`RILU format: <insn> R1,U2' 14683 14684 +--------+----+----+------------------------------------+ 14685 | OpCode | R1 |OpCd| U2 | 14686 +--------+----+----+------------------------------------+ 14687 0 8 12 16 47 14688 14689`RIS format: <insn> R1,I2,M3,D4(B4)' 14690 14691 +--------+----+----+----+-------------+--------+--------+ 14692 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 14693 +--------+----+----+----+-------------+--------+--------+ 14694 0 8 12 16 20 32 36 47 14695 14696`RR format: <insn> R1,R2' 14697 14698 +--------+----+----+ 14699 | OpCode | R1 | R2 | 14700 +--------+----+----+ 14701 0 8 12 15 14702 14703`RRE format: <insn> R1,R2' 14704 14705 +------------------+--------+----+----+ 14706 | OpCode |////////| R1 | R2 | 14707 +------------------+--------+----+----+ 14708 0 16 24 28 31 14709 14710`RRF format: <insn> R1,R2,R3,M4' 14711 14712 +------------------+----+----+----+----+ 14713 | OpCode | R3 | M4 | R1 | R2 | 14714 +------------------+----+----+----+----+ 14715 0 16 20 24 28 31 14716 14717`RRS format: <insn> R1,R2,M3,D4(B4)' 14718 14719 +--------+----+----+----+-------------+----+----+--------+ 14720 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 14721 +--------+----+----+----+-------------+----+----+--------+ 14722 0 8 12 16 20 32 36 40 47 14723 14724`RS format: <insn> R1,R3,D2(B2)' 14725 14726 +--------+----+----+----+-------------+ 14727 | OpCode | R1 | R3 | B2 | D2 | 14728 +--------+----+----+----+-------------+ 14729 0 8 12 16 20 31 14730 14731`RSE format: <insn> R1,R3,D2(B2)' 14732 14733 +--------+----+----+----+-------------+--------+--------+ 14734 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 14735 +--------+----+----+----+-------------+--------+--------+ 14736 0 8 12 16 20 32 40 47 14737 14738`RSI format: <insn> R1,R3,I2' 14739 14740 +--------+----+----+------------------------------------+ 14741 | OpCode | R1 | R3 | I2 | 14742 +--------+----+----+------------------------------------+ 14743 0 8 12 16 47 14744 14745`RSY format: <insn> R1,R3,D2(B2)' 14746 14747 +--------+----+----+----+-------------+--------+--------+ 14748 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 14749 +--------+----+----+----+-------------+--------+--------+ 14750 0 8 12 16 20 32 40 47 14751 14752`RX format: <insn> R1,D2(X2,B2)' 14753 14754 +--------+----+----+----+-------------+ 14755 | OpCode | R1 | X2 | B2 | D2 | 14756 +--------+----+----+----+-------------+ 14757 0 8 12 16 20 31 14758 14759`RXE format: <insn> R1,D2(X2,B2)' 14760 14761 +--------+----+----+----+-------------+--------+--------+ 14762 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 14763 +--------+----+----+----+-------------+--------+--------+ 14764 0 8 12 16 20 32 40 47 14765 14766`RXF format: <insn> R1,R3,D2(X2,B2)' 14767 14768 +--------+----+----+----+-------------+----+---+--------+ 14769 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 14770 +--------+----+----+----+-------------+----+---+--------+ 14771 0 8 12 16 20 32 36 40 47 14772 14773`RXY format: <insn> R1,D2(X2,B2)' 14774 14775 +--------+----+----+----+-------------+--------+--------+ 14776 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 14777 +--------+----+----+----+-------------+--------+--------+ 14778 0 8 12 16 20 32 36 40 47 14779 14780`S format: <insn> D2(B2)' 14781 14782 +------------------+----+-------------+ 14783 | OpCode | B2 | D2 | 14784 +------------------+----+-------------+ 14785 0 16 20 31 14786 14787`SI format: <insn> D1(B1),I2' 14788 14789 +--------+---------+----+-------------+ 14790 | OpCode | I2 | B1 | D1 | 14791 +--------+---------+----+-------------+ 14792 0 8 16 20 31 14793 14794`SIY format: <insn> D1(B1),U2' 14795 14796 +--------+---------+----+-------------+--------+--------+ 14797 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 14798 +--------+---------+----+-------------+--------+--------+ 14799 0 8 16 20 32 36 40 47 14800 14801`SIL format: <insn> D1(B1),I2' 14802 14803 +------------------+----+-------------+-----------------+ 14804 | OpCode | B1 | D1 | I2 | 14805 +------------------+----+-------------+-----------------+ 14806 0 16 20 32 47 14807 14808`SS format: <insn> D1(R1,B1),D2(B3),R3' 14809 14810 +--------+----+----+----+-------------+----+------------+ 14811 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 14812 +--------+----+----+----+-------------+----+------------+ 14813 0 8 12 16 20 32 36 47 14814 14815`SSE format: <insn> D1(B1),D2(B2)' 14816 14817 +------------------+----+-------------+----+------------+ 14818 | OpCode | B1 | D1 | B2 | D2 | 14819 +------------------+----+-------------+----+------------+ 14820 0 8 12 16 20 32 36 47 14821 14822`SSF format: <insn> D1(B1),D2(B2),R3' 14823 14824 +--------+----+----+----+-------------+----+------------+ 14825 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 14826 +--------+----+----+----+-------------+----+------------+ 14827 0 8 12 16 20 32 36 47 14828 14829 14830 For the complete list of all instruction format variants see the 14831Principles of Operation manuals. 14832 14833 14834File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 14835 148369.31.3.5 Instruction Aliases 14837............................ 14838 14839A specific bit pattern can have multiple mnemonics, for example the bit 14840pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition, 14841there are a number of mnemonics recognized by `as' that are not present 14842in the Principles of Operation. These are the short forms of the 14843branch instructions, where the condition code mask operand is encoded 14844in the mnemonic. This is relevant for the branch instructions, the 14845compare and branch instructions, and the compare and trap instructions. 14846 14847 For the branch instructions there are 20 condition code strings that 14848can be used as part of the mnemonic in place of a mask operand in the 14849instruction format: 14850 14851 instruction short form 14852 ------------------------------------------ 14853 bcr M1,R2 b<m>r R2 14854 bc M1,D2(X2,B2) b<m> D2(X2,B2) 14855 brc M1,I2 j<m> I2 14856 brcl M1,I2 jg<m> I2 14857 14858 In the mnemonic for a branch instruction the condition code string 14859<m> can be any of the following: 14860 14861 o jump on overflow / if ones 14862 h jump on A high 14863 p jump on plus 14864 nle jump on not low or equal 14865 l jump on A low 14866 m jump on minus 14867 nhe jump on not high or equal 14868 lh jump on low or high 14869 ne jump on A not equal B 14870 nz jump on not zero / if not zeros 14871 e jump on A equal B 14872 z jump on zero / if zeroes 14873 nlh jump on not low or high 14874 he jump on high or equal 14875 nl jump on A not low 14876 nm jump on not minus / if not mixed 14877 le jump on low or equal 14878 nh jump on A not high 14879 np jump on not plus 14880 no jump on not overflow / if not ones 14881 14882 For the compare and branch, and compare and trap instructions there 14883are 12 condition code strings that can be used as part of the mnemonic 14884in place of a mask operand in the instruction format: 14885 14886 instruction short form 14887 -------------------------------------------------------- 14888 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 14889 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 14890 crj R1,R2,M3,I4 crj<m> R1,R2,I4 14891 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 14892 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 14893 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 14894 cij R1,I2,M3,I4 cij<m> R1,I2,I4 14895 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 14896 crt R1,R2,M3 crt<m> R1,R2 14897 cgrt R1,R2,M3 cgrt<m> R1,R2 14898 cit R1,I2,M3 cit<m> R1,I2 14899 cgit R1,I2,M3 cgit<m> R1,I2 14900 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 14901 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 14902 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 14903 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 14904 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 14905 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 14906 clij R1,I2,M3,I4 clij<m> R1,I2,I4 14907 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 14908 clrt R1,R2,M3 clrt<m> R1,R2 14909 clgrt R1,R2,M3 clgrt<m> R1,R2 14910 clfit R1,I2,M3 clfit<m> R1,I2 14911 clgit R1,I2,M3 clgit<m> R1,I2 14912 14913 In the mnemonic for a compare and branch and compare and trap 14914instruction the condition code string <m> can be any of the following: 14915 14916 h jump on A high 14917 nle jump on not low or equal 14918 l jump on A low 14919 nhe jump on not high or equal 14920 ne jump on A not equal B 14921 lh jump on low or high 14922 e jump on A equal B 14923 nlh jump on not low or high 14924 nl jump on A not low 14925 he jump on high or equal 14926 nh jump on A not high 14927 le jump on low or equal 14928 14929 14930File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 14931 149329.31.3.6 Instruction Operand Modifier 14933..................................... 14934 14935If a symbol modifier is attached to a symbol in an expression for an 14936instruction operand field, the symbol term is replaced with a reference 14937to an object in the global offset table (GOT) or the procedure linkage 14938table (PLT). The following expressions are allowed: `symbol@modifier + 14939constant', `symbol@modifier + label + constant', and `symbol@modifier - 14940label + constant'. The term `symbol' is the symbol that will be 14941entered into the GOT or PLT, `label' is a local label, and `constant' 14942is an arbitrary expression that the assembler can evaluate to a 14943constant value. 14944 14945 The term `(symbol + constant1)@modifier +/- label + constant2' is 14946also accepted but a warning message is printed and the term is 14947converted to `symbol@modifier +/- label + constant1 + constant2'. 14948 14949`@got' 14950`@got12' 14951 The @got modifier can be used for displacement fields, 16-bit 14952 immediate fields and 32-bit pc-relative immediate fields. The 14953 @got12 modifier is synonym to @got. The symbol is added to the 14954 GOT. For displacement fields and 16-bit immediate fields the 14955 symbol term is replaced with the offset from the start of the GOT 14956 to the GOT slot for the symbol. For a 32-bit pc-relative field 14957 the pc-relative offset to the GOT slot from the current 14958 instruction address is used. 14959 14960`@gotent' 14961 The @gotent modifier can be used for 32-bit pc-relative immediate 14962 fields. The symbol is added to the GOT and the symbol term is 14963 replaced with the pc-relative offset from the current instruction 14964 to the GOT slot for the symbol. 14965 14966`@gotoff' 14967 The @gotoff modifier can be used for 16-bit immediate fields. The 14968 symbol term is replaced with the offset from the start of the GOT 14969 to the address of the symbol. 14970 14971`@gotplt' 14972 The @gotplt modifier can be used for displacement fields, 16-bit 14973 immediate fields, and 32-bit pc-relative immediate fields. A 14974 procedure linkage table entry is generated for the symbol and a 14975 jump slot for the symbol is added to the GOT. For displacement 14976 fields and 16-bit immediate fields the symbol term is replaced 14977 with the offset from the start of the GOT to the jump slot for the 14978 symbol. For a 32-bit pc-relative field the pc-relative offset to 14979 the jump slot from the current instruction address is used. 14980 14981`@plt' 14982 The @plt modifier can be used for 16-bit and 32-bit pc-relative 14983 immediate fields. A procedure linkage table entry is generated for 14984 the symbol. The symbol term is replaced with the relative offset 14985 from the current instruction to the PLT entry for the symbol. 14986 14987`@pltoff' 14988 The @pltoff modifier can be used for 16-bit immediate fields. The 14989 symbol term is replaced with the offset from the start of the PLT 14990 to the address of the symbol. 14991 14992`@gotntpoff' 14993 The @gotntpoff modifier can be used for displacement fields. The 14994 symbol is added to the static TLS block and the negated offset to 14995 the symbol in the static TLS block is added to the GOT. The symbol 14996 term is replaced with the offset to the GOT slot from the start of 14997 the GOT. 14998 14999`@indntpoff' 15000 The @indntpoff modifier can be used for 32-bit pc-relative 15001 immediate fields. The symbol is added to the static TLS block and 15002 the negated offset to the symbol in the static TLS block is added 15003 to the GOT. The symbol term is replaced with the pc-relative 15004 offset to the GOT slot from the current instruction address. 15005 15006 For more information about the thread local storage modifiers 15007`gotntpoff' and `indntpoff' see the ELF extension documentation `ELF 15008Handling For Thread-Local Storage'. 15009 15010 15011File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 15012 150139.31.3.7 Instruction Marker 15014........................... 15015 15016The thread local storage instruction markers are used by the linker to 15017perform code optimization. 15018 15019`:tls_load' 15020 The :tls_load marker is used to flag the load instruction in the 15021 initial exec TLS model that retrieves the offset from the thread 15022 pointer to a thread local storage variable from the GOT. 15023 15024`:tls_gdcall' 15025 The :tls_gdcall marker is used to flag the branch-and-save 15026 instruction to the __tls_get_offset function in the global dynamic 15027 TLS model. 15028 15029`:tls_ldcall' 15030 The :tls_ldcall marker is used to flag the branch-and-save 15031 instruction to the __tls_get_offset function in the local dynamic 15032 TLS model. 15033 15034 For more information about the thread local storage instruction 15035marker and the linker optimizations see the ELF extension documentation 15036`ELF Handling For Thread-Local Storage'. 15037 15038 15039File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 15040 150419.31.3.8 Literal Pool Entries 15042............................. 15043 15044A literal pool is a collection of values. To access the values a pointer 15045to the literal pool is loaded to a register, the literal pool register. 15046Usually, register %r13 is used as the literal pool register (*Note s390 15047Register::). Literal pool entries are created by adding the suffix 15048:lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 15049instruction operand. The expression is added to the literal pool and the 15050operand is replaced with the offset to the literal in the literal pool. 15051 15052`:lit1' 15053 The literal pool entry is created as an 8-bit value. An operand 15054 modifier must not be used for the original expression. 15055 15056`:lit2' 15057 The literal pool entry is created as a 16 bit value. The operand 15058 modifier @got may be used in the original expression. The term 15059 `x@got:lit2' will put the got offset for the global symbol x to 15060 the literal pool as 16 bit value. 15061 15062`:lit4' 15063 The literal pool entry is created as a 32-bit value. The operand 15064 modifier @got and @plt may be used in the original expression. The 15065 term `x@got:lit4' will put the got offset for the global symbol x 15066 to the literal pool as a 32-bit value. The term `x@plt:lit4' will 15067 put the plt offset for the global symbol x to the literal pool as 15068 a 32-bit value. 15069 15070`:lit8' 15071 The literal pool entry is created as a 64-bit value. The operand 15072 modifier @got and @plt may be used in the original expression. The 15073 term `x@got:lit8' will put the got offset for the global symbol x 15074 to the literal pool as a 64-bit value. The term `x@plt:lit8' will 15075 put the plt offset for the global symbol x to the literal pool as 15076 a 64-bit value. 15077 15078 The assembler directive `.ltorg' is used to emit all literal pool 15079entries to the current position. 15080 15081 15082File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 15083 150849.31.4 Assembler Directives 15085--------------------------- 15086 15087`as' for s390 supports all of the standard ELF assembler directives as 15088outlined in the main part of this document. Some directives have been 15089extended and there are some additional directives, which are only 15090available for the s390 `as'. 15091 15092`.insn' 15093 This directive permits the numeric representation of an 15094 instructions and makes the assembler insert the operands according 15095 to one of the instructions formats for `.insn' (*Note s390 15096 Formats::). For example, the instruction `l %r1,24(%r15)' could 15097 be written as `.insn rx,0x58000000,%r1,24(%r15)'. 15098 15099`.short' 15100`.long' 15101`.quad' 15102 This directive places one or more 16-bit (.short), 32-bit (.long), 15103 or 64-bit (.quad) values into the current section. If an ELF or 15104 TLS modifier is used only the following expressions are allowed: 15105 `symbol@modifier + constant', `symbol@modifier + label + 15106 constant', and `symbol@modifier - label + constant'. The 15107 following modifiers are available: 15108 `@got' 15109 `@got12' 15110 The @got modifier can be used for .short, .long and .quad. 15111 The @got12 modifier is synonym to @got. The symbol is added 15112 to the GOT. The symbol term is replaced with offset from the 15113 start of the GOT to the GOT slot for the symbol. 15114 15115 `@gotoff' 15116 The @gotoff modifier can be used for .short, .long and .quad. 15117 The symbol term is replaced with the offset from the start of 15118 the GOT to the address of the symbol. 15119 15120 `@gotplt' 15121 The @gotplt modifier can be used for .long and .quad. A 15122 procedure linkage table entry is generated for the symbol and 15123 a jump slot for the symbol is added to the GOT. The symbol 15124 term is replaced with the offset from the start of the GOT to 15125 the jump slot for the symbol. 15126 15127 `@plt' 15128 The @plt modifier can be used for .long and .quad. A 15129 procedure linkage table entry us generated for the symbol. 15130 The symbol term is replaced with the address of the PLT entry 15131 for the symbol. 15132 15133 `@pltoff' 15134 The @pltoff modifier can be used for .short, .long and .quad. 15135 The symbol term is replaced with the offset from the start of 15136 the PLT to the address of the symbol. 15137 15138 `@tlsgd' 15139 `@tlsldm' 15140 The @tlsgd and @tlsldm modifier can be used for .long and 15141 .quad. A tls_index structure for the symbol is added to the 15142 GOT. The symbol term is replaced with the offset from the 15143 start of the GOT to the tls_index structure. 15144 15145 `@gotntpoff' 15146 `@indntpoff' 15147 The @gotntpoff and @indntpoff modifier can be used for .long 15148 and .quad. The symbol is added to the static TLS block and 15149 the negated offset to the symbol in the static TLS block is 15150 added to the GOT. For @gotntpoff the symbol term is replaced 15151 with the offset from the start of the GOT to the GOT slot, 15152 for @indntpoff the symbol term is replaced with the address 15153 of the GOT slot. 15154 15155 `@dtpoff' 15156 The @dtpoff modifier can be used for .long and .quad. The 15157 symbol term is replaced with the offset of the symbol 15158 relative to the start of the TLS block it is contained in. 15159 15160 `@ntpoff' 15161 The @ntpoff modifier can be used for .long and .quad. The 15162 symbol term is replaced with the offset of the symbol 15163 relative to the TCB pointer. 15164 15165 For more information about the thread local storage modifiers see 15166 the ELF extension documentation `ELF Handling For Thread-Local 15167 Storage'. 15168 15169`.ltorg' 15170 This directive causes the current contents of the literal pool to 15171 be dumped to the current location (*Note s390 Literal Pool 15172 Entries::). 15173 15174`.machine string' 15175 This directive allows you to change the machine for which code is 15176 generated. `string' may be any of the `-march=' selection options 15177 (without the -march=), `push', or `pop'. `.machine push' saves 15178 the currently selected cpu, which may be restored with `.machine 15179 pop'. Be aware that the cpu string has to be put into double 15180 quotes in case it contains characters not appropriate for 15181 identifiers. So you have to write `"z9-109"' instead of just 15182 `z9-109'. 15183 15184 15185File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 15186 151879.31.5 Floating Point 15188--------------------- 15189 15190The assembler recognizes both the IEEE floating-point instruction and 15191the hexadecimal floating-point instructions. The floating-point 15192constructors `.float', `.single', and `.double' always emit the IEEE 15193format. To assemble hexadecimal floating-point constants the `.long' 15194and `.quad' directives must be used. 15195 15196 15197File: as.info, Node: SCORE-Dependent, Next: Sparc-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 15198 151999.32 SCORE Dependent Features 15200============================= 15201 15202* Menu: 15203 15204* SCORE-Opts:: Assembler options 15205* SCORE-Pseudo:: SCORE Assembler Directives 15206 15207 15208File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 15209 152109.32.1 Options 15211-------------- 15212 15213The following table lists all available SCORE options. 15214 15215`-G NUM' 15216 This option sets the largest size of an object that can be 15217 referenced implicitly with the `gp' register. The default value is 15218 8. 15219 15220`-EB' 15221 Assemble code for a big-endian cpu 15222 15223`-EL' 15224 Assemble code for a little-endian cpu 15225 15226`-FIXDD' 15227 Assemble code for fix data dependency 15228 15229`-NWARN' 15230 Assemble code for no warning message for fix data dependency 15231 15232`-SCORE5' 15233 Assemble code for target is SCORE5 15234 15235`-SCORE5U' 15236 Assemble code for target is SCORE5U 15237 15238`-SCORE7' 15239 Assemble code for target is SCORE7, this is default setting 15240 15241`-SCORE3' 15242 Assemble code for target is SCORE3 15243 15244`-march=score7' 15245 Assemble code for target is SCORE7, this is default setting 15246 15247`-march=score3' 15248 Assemble code for target is SCORE3 15249 15250`-USE_R1' 15251 Assemble code for no warning message when using temp register r1 15252 15253`-KPIC' 15254 Generate code for PIC. This option tells the assembler to generate 15255 score position-independent macro expansions. It also tells the 15256 assembler to mark the output file as PIC. 15257 15258`-O0' 15259 Assembler will not perform any optimizations 15260 15261`-V' 15262 Sunplus release version 15263 15264 15265 15266File: as.info, Node: SCORE-Pseudo, Prev: SCORE-Opts, Up: SCORE-Dependent 15267 152689.32.2 SCORE Assembler Directives 15269--------------------------------- 15270 15271A number of assembler directives are available for SCORE. The 15272following table is far from complete. 15273 15274`.set nwarn' 15275 Let the assembler not to generate warnings if the source machine 15276 language instructions happen data dependency. 15277 15278`.set fixdd' 15279 Let the assembler to insert bubbles (32 bit nop instruction / 16 15280 bit nop! Instruction) if the source machine language instructions 15281 happen data dependency. 15282 15283`.set nofixdd' 15284 Let the assembler to generate warnings if the source machine 15285 language instructions happen data dependency. (Default) 15286 15287`.set r1' 15288 Let the assembler not to generate warnings if the source program 15289 uses r1. allow user to use r1 15290 15291`set nor1' 15292 Let the assembler to generate warnings if the source program uses 15293 r1. (Default) 15294 15295`.sdata' 15296 Tell the assembler to add subsequent data into the sdata section 15297 15298`.rdata' 15299 Tell the assembler to add subsequent data into the rdata section 15300 15301`.frame "frame-register", "offset", "return-pc-register"' 15302 Describe a stack frame. "frame-register" is the frame register, 15303 "offset" is the distance from the frame register to the virtual 15304 frame pointer, "return-pc-register" is the return program register. 15305 You must use ".ent" before ".frame" and only one ".frame" can be 15306 used per ".ent". 15307 15308`.mask "bitmask", "frameoffset"' 15309 Indicate which of the integer registers are saved in the current 15310 function's stack frame, this is for the debugger to explain the 15311 frame chain. 15312 15313`.ent "proc-name"' 15314 Set the beginning of the procedure "proc_name". Use this directive 15315 when you want to generate information for the debugger. 15316 15317`.end proc-name' 15318 Set the end of a procedure. Use this directive to generate 15319 information for the debugger. 15320 15321`.bss' 15322 Switch the destination of following statements into the bss 15323 section, which is used for data that is uninitialized anywhere. 15324 15325 15326 15327File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 15328 153299.33 Renesas / SuperH SH Dependent Features 15330=========================================== 15331 15332* Menu: 15333 15334* SH Options:: Options 15335* SH Syntax:: Syntax 15336* SH Floating Point:: Floating Point 15337* SH Directives:: SH Machine Directives 15338* SH Opcodes:: Opcodes 15339 15340 15341File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 15342 153439.33.1 Options 15344-------------- 15345 15346`as' has following command-line options for the Renesas (formerly 15347Hitachi) / SuperH SH family. 15348 15349`--little' 15350 Generate little endian code. 15351 15352`--big' 15353 Generate big endian code. 15354 15355`--relax' 15356 Alter jump instructions for long displacements. 15357 15358`--small' 15359 Align sections to 4 byte boundaries, not 16. 15360 15361`--dsp' 15362 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15363 15364`--renesas' 15365 Disable optimization with section symbol for compatibility with 15366 Renesas assembler. 15367 15368`--allow-reg-prefix' 15369 Allow '$' as a register name prefix. 15370 15371`--fdpic' 15372 Generate an FDPIC object file. 15373 15374`--isa=sh4 | sh4a' 15375 Specify the sh4 or sh4a instruction set. 15376 15377`--isa=dsp' 15378 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15379 15380`--isa=fp' 15381 Enable sh2e, sh3e, sh4, and sh4a insn sets. 15382 15383`--isa=all' 15384 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 15385 15386`-h-tick-hex' 15387 Support H'00 style hex constants in addition to 0x00 style. 15388 15389 15390 15391File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 15392 153939.33.2 Syntax 15394------------- 15395 15396* Menu: 15397 15398* SH-Chars:: Special Characters 15399* SH-Regs:: Register Names 15400* SH-Addressing:: Addressing Modes 15401 15402 15403File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 15404 154059.33.2.1 Special Characters 15406........................... 15407 15408`!' is the line comment character. 15409 15410 You can use `;' instead of a newline to separate statements. 15411 15412 Since `$' has no special meaning, you may use it in symbol names. 15413 15414 15415File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 15416 154179.33.2.2 Register Names 15418....................... 15419 15420You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', 15421`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to 15422refer to the SH registers. 15423 15424 The SH also has these control registers: 15425 15426`pr' 15427 procedure register (holds return address) 15428 15429`pc' 15430 program counter 15431 15432`mach' 15433`macl' 15434 high and low multiply accumulator registers 15435 15436`sr' 15437 status register 15438 15439`gbr' 15440 global base register 15441 15442`vbr' 15443 vector base register (for interrupt vectors) 15444 15445 15446File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 15447 154489.33.2.3 Addressing Modes 15449......................... 15450 15451`as' understands the following addressing modes for the SH. `RN' in 15452the following refers to any of the numbered registers, but _not_ the 15453control registers. 15454 15455`RN' 15456 Register direct 15457 15458`@RN' 15459 Register indirect 15460 15461`@-RN' 15462 Register indirect with pre-decrement 15463 15464`@RN+' 15465 Register indirect with post-increment 15466 15467`@(DISP, RN)' 15468 Register indirect with displacement 15469 15470`@(R0, RN)' 15471 Register indexed 15472 15473`@(DISP, GBR)' 15474 `GBR' offset 15475 15476`@(R0, GBR)' 15477 GBR indexed 15478 15479`ADDR' 15480`@(DISP, PC)' 15481 PC relative address (for branch or for addressing memory). The 15482 `as' implementation allows you to use the simpler form ADDR 15483 anywhere a PC relative address is called for; the alternate form 15484 is supported for compatibility with other assemblers. 15485 15486`#IMM' 15487 Immediate data 15488 15489 15490File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 15491 154929.33.3 Floating Point 15493--------------------- 15494 15495SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 15496SH groups can use `.float' directive to generate IEEE floating-point 15497numbers. 15498 15499 SH2E and SH3E support single-precision floating point calculations as 15500well as entirely PCAPI compatible emulation of double-precision 15501floating point calculations. SH2E and SH3E instructions are a subset of 15502the floating point calculations conforming to the IEEE754 standard. 15503 15504 In addition to single-precision and double-precision floating-point 15505operation capability, the on-chip FPU of SH4 has a 128-bit graphic 15506engine that enables 32-bit floating-point data to be processed 128 bits 15507at a time. It also supports 4 * 4 array operations and inner product 15508operations. Also, a superscalar architecture is employed that enables 15509simultaneous execution of two instructions (including FPU 15510instructions), providing performance of up to twice that of 15511conventional architectures at the same frequency. 15512 15513 15514File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 15515 155169.33.4 SH Machine Directives 15517---------------------------- 15518 15519`uaword' 15520`ualong' 15521 `as' will issue a warning when a misaligned `.word' or `.long' 15522 directive is used. You may use `.uaword' or `.ualong' to indicate 15523 that the value is intentionally misaligned. 15524 15525 15526File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 15527 155289.33.5 Opcodes 15529-------------- 15530 15531For detailed information on the SH machine instruction set, see 15532`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core 15533Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH). 15534 15535 `as' implements all the standard SH opcodes. No additional 15536pseudo-instructions are needed on this family. Note, however, that 15537because `as' supports a simpler form of PC-relative addressing, you may 15538simply write (for example) 15539 15540 mov.l bar,r0 15541 15542where other assemblers might require an explicit displacement to `bar' 15543from the program counter: 15544 15545 mov.l @(DISP, PC) 15546 15547 Here is a summary of SH opcodes: 15548 15549 Legend: 15550 Rn a numbered register 15551 Rm another numbered register 15552 #imm immediate data 15553 disp displacement 15554 disp8 8-bit displacement 15555 disp12 12-bit displacement 15556 15557 add #imm,Rn lds.l @Rn+,PR 15558 add Rm,Rn mac.w @Rm+,@Rn+ 15559 addc Rm,Rn mov #imm,Rn 15560 addv Rm,Rn mov Rm,Rn 15561 and #imm,R0 mov.b Rm,@(R0,Rn) 15562 and Rm,Rn mov.b Rm,@-Rn 15563 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 15564 bf disp8 mov.b @(disp,Rm),R0 15565 bra disp12 mov.b @(disp,GBR),R0 15566 bsr disp12 mov.b @(R0,Rm),Rn 15567 bt disp8 mov.b @Rm+,Rn 15568 clrmac mov.b @Rm,Rn 15569 clrt mov.b R0,@(disp,Rm) 15570 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 15571 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 15572 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 15573 cmp/gt Rm,Rn mov.l Rm,@-Rn 15574 cmp/hi Rm,Rn mov.l Rm,@Rn 15575 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 15576 cmp/pl Rn mov.l @(disp,GBR),R0 15577 cmp/pz Rn mov.l @(disp,PC),Rn 15578 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 15579 div0s Rm,Rn mov.l @Rm+,Rn 15580 div0u mov.l @Rm,Rn 15581 div1 Rm,Rn mov.l R0,@(disp,GBR) 15582 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 15583 exts.w Rm,Rn mov.w Rm,@-Rn 15584 extu.b Rm,Rn mov.w Rm,@Rn 15585 extu.w Rm,Rn mov.w @(disp,Rm),R0 15586 jmp @Rn mov.w @(disp,GBR),R0 15587 jsr @Rn mov.w @(disp,PC),Rn 15588 ldc Rn,GBR mov.w @(R0,Rm),Rn 15589 ldc Rn,SR mov.w @Rm+,Rn 15590 ldc Rn,VBR mov.w @Rm,Rn 15591 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 15592 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 15593 ldc.l @Rn+,VBR mova @(disp,PC),R0 15594 lds Rn,MACH movt Rn 15595 lds Rn,MACL muls Rm,Rn 15596 lds Rn,PR mulu Rm,Rn 15597 lds.l @Rn+,MACH neg Rm,Rn 15598 lds.l @Rn+,MACL negc Rm,Rn 15599 15600 nop stc VBR,Rn 15601 not Rm,Rn stc.l GBR,@-Rn 15602 or #imm,R0 stc.l SR,@-Rn 15603 or Rm,Rn stc.l VBR,@-Rn 15604 or.b #imm,@(R0,GBR) sts MACH,Rn 15605 rotcl Rn sts MACL,Rn 15606 rotcr Rn sts PR,Rn 15607 rotl Rn sts.l MACH,@-Rn 15608 rotr Rn sts.l MACL,@-Rn 15609 rte sts.l PR,@-Rn 15610 rts sub Rm,Rn 15611 sett subc Rm,Rn 15612 shal Rn subv Rm,Rn 15613 shar Rn swap.b Rm,Rn 15614 shll Rn swap.w Rm,Rn 15615 shll16 Rn tas.b @Rn 15616 shll2 Rn trapa #imm 15617 shll8 Rn tst #imm,R0 15618 shlr Rn tst Rm,Rn 15619 shlr16 Rn tst.b #imm,@(R0,GBR) 15620 shlr2 Rn xor #imm,R0 15621 shlr8 Rn xor Rm,Rn 15622 sleep xor.b #imm,@(R0,GBR) 15623 stc GBR,Rn xtrct Rm,Rn 15624 stc SR,Rn 15625 15626 15627File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 15628 156299.34 SuperH SH64 Dependent Features 15630=================================== 15631 15632* Menu: 15633 15634* SH64 Options:: Options 15635* SH64 Syntax:: Syntax 15636* SH64 Directives:: SH64 Machine Directives 15637* SH64 Opcodes:: Opcodes 15638 15639 15640File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent 15641 156429.34.1 Options 15643-------------- 15644 15645`-isa=sh4 | sh4a' 15646 Specify the sh4 or sh4a instruction set. 15647 15648`-isa=dsp' 15649 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15650 15651`-isa=fp' 15652 Enable sh2e, sh3e, sh4, and sh4a insn sets. 15653 15654`-isa=all' 15655 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 15656 15657`-isa=shmedia | -isa=shcompact' 15658 Specify the default instruction set. `SHmedia' specifies the 15659 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes 15660 compatible with previous SH families. The default depends on the 15661 ABI selected; the default for the 64-bit ABI is SHmedia, and the 15662 default for the 32-bit ABI is SHcompact. If neither the ABI nor 15663 the ISA is specified, the default is 32-bit SHcompact. 15664 15665 Note that the `.mode' pseudo-op is not permitted if the ISA is not 15666 specified on the command line. 15667 15668`-abi=32 | -abi=64' 15669 Specify the default ABI. If the ISA is specified and the ABI is 15670 not, the default ABI depends on the ISA, with SHmedia defaulting 15671 to 64-bit and SHcompact defaulting to 32-bit. 15672 15673 Note that the `.abi' pseudo-op is not permitted if the ABI is not 15674 specified on the command line. When the ABI is specified on the 15675 command line, any `.abi' pseudo-ops in the source must match it. 15676 15677`-shcompact-const-crange' 15678 Emit code-range descriptors for constants in SHcompact code 15679 sections. 15680 15681`-no-mix' 15682 Disallow SHmedia code in the same section as constants and 15683 SHcompact code. 15684 15685`-no-expand' 15686 Do not expand MOVI, PT, PTA or PTB instructions. 15687 15688`-expand-pt32' 15689 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. 15690 15691`-h-tick-hex' 15692 Support H'00 style hex constants in addition to 0x00 style. 15693 15694 15695 15696File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent 15697 156989.34.2 Syntax 15699------------- 15700 15701* Menu: 15702 15703* SH64-Chars:: Special Characters 15704* SH64-Regs:: Register Names 15705* SH64-Addressing:: Addressing Modes 15706 15707 15708File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax 15709 157109.34.2.1 Special Characters 15711........................... 15712 15713`!' is the line comment character. 15714 15715 You can use `;' instead of a newline to separate statements. 15716 15717 Since `$' has no special meaning, you may use it in symbol names. 15718 15719 15720File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax 15721 157229.34.2.2 Register Names 15723....................... 15724 15725You can use the predefined symbols `r0' through `r63' to refer to the 15726SH64 general registers, `cr0' through `cr63' for control registers, 15727`tr0' through `tr7' for target address registers, `fr0' through `fr63' 15728for single-precision floating point registers, `dr0' through `dr62' 15729(even numbered registers only) for double-precision floating point 15730registers, `fv0' through `fv60' (multiples of four only) for 15731single-precision floating point vectors, `fp0' through `fp62' (even 15732numbered registers only) for single-precision floating point pairs, 15733`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of 15734single-precision floating point registers, `pc' for the program 15735counter, and `fpscr' for the floating point status and control register. 15736 15737 You can also refer to the control registers by the mnemonics `sr', 15738`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc', 15739`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'. 15740 15741 15742File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax 15743 157449.34.2.3 Addressing Modes 15745......................... 15746 15747SH64 operands consist of either a register or immediate value. The 15748immediate value can be a constant or label reference (or portion of a 15749label reference), as in this example: 15750 15751 movi 4,r2 15752 pt function, tr4 15753 movi (function >> 16) & 65535,r0 15754 shori function & 65535, r0 15755 ld.l r0,4,r0 15756 15757 Instruction label references can reference labels in either SHmedia 15758or SHcompact. To differentiate between the two, labels in SHmedia 15759sections will always have the least significant bit set (i.e. they will 15760be odd), which SHcompact labels will have the least significant bit 15761reset (i.e. they will be even). If you need to reference the actual 15762address of a label, you can use the `datalabel' modifier, as in this 15763example: 15764 15765 .long function 15766 .long datalabel function 15767 15768 In that example, the first longword may or may not have the least 15769significant bit set depending on whether the label is an SHmedia label 15770or an SHcompact label. The second longword will be the actual address 15771of the label, regardless of what type of label it is. 15772 15773 15774File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent 15775 157769.34.3 SH64 Machine Directives 15777------------------------------ 15778 15779In addition to the SH directives, the SH64 provides the following 15780directives: 15781 15782`.mode [shmedia|shcompact]' 15783`.isa [shmedia|shcompact]' 15784 Specify the ISA for the following instructions (the two directives 15785 are equivalent). Note that programs such as `objdump' rely on 15786 symbolic labels to determine when such mode switches occur (by 15787 checking the least significant bit of the label's address), so 15788 such mode/isa changes should always be followed by a label (in 15789 practice, this is true anyway). Note that you cannot use these 15790 directives if you didn't specify an ISA on the command line. 15791 15792`.abi [32|64]' 15793 Specify the ABI for the following instructions. Note that you 15794 cannot use this directive unless you specified an ABI on the 15795 command line, and the ABIs specified must match. 15796 15797`.uaquad' 15798 Like .uaword and .ualong, this allows you to specify an 15799 intentionally unaligned quadword (64 bit word). 15800 15801 15802 15803File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent 15804 158059.34.4 Opcodes 15806-------------- 15807 15808For detailed information on the SH64 machine instruction set, see 15809`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). 15810 15811 `as' implements all the standard SH64 opcodes. In addition, the 15812following pseudo-opcodes may be expanded into one or more alternate 15813opcodes: 15814 15815`movi' 15816 If the value doesn't fit into a standard `movi' opcode, `as' will 15817 replace the `movi' with a sequence of `movi' and `shori' opcodes. 15818 15819`pt' 15820 This expands to a sequence of `movi' and `shori' opcode, followed 15821 by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on 15822 the label referenced. 15823 15824 15825 15826File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 15827 158289.35 SPARC Dependent Features 15829============================= 15830 15831* Menu: 15832 15833* Sparc-Opts:: Options 15834* Sparc-Aligned-Data:: Option to enforce aligned data 15835* Sparc-Syntax:: Syntax 15836* Sparc-Float:: Floating Point 15837* Sparc-Directives:: Sparc Machine Directives 15838 15839 15840File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 15841 158429.35.1 Options 15843-------------- 15844 15845The SPARC chip family includes several successive versions, using the 15846same core instruction set, but including a few additional instructions 15847at each version. There are exceptions to this however. For details on 15848what instructions each variant supports, please see the chip's 15849architecture reference manual. 15850 15851 By default, `as' assumes the core instruction set (SPARC v6), but 15852"bumps" the architecture level as needed: it switches to successively 15853higher architectures as it encounters instructions that only exist in 15854the higher levels. 15855 15856 If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump 15857past sparclite by default, an option must be passed to enable the v9 15858instructions. 15859 15860 GAS treats sparclite as being compatible with v8, unless an 15861architecture is explicitly requested. SPARC v9 is always incompatible 15862with sparclite. 15863 15864`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 15865`-Av8plus | -Av8plusa | -Av9 | -Av9a' 15866 Use one of the `-A' options to select one of the SPARC 15867 architectures explicitly. If you select an architecture 15868 explicitly, `as' reports a fatal error if it encounters an 15869 instruction or feature requiring an incompatible or higher level. 15870 15871 `-Av8plus' and `-Av8plusa' select a 32 bit environment. 15872 15873 `-Av9' and `-Av9a' select a 64 bit environment and are not 15874 available unless GAS is explicitly configured with 64 bit 15875 environment support. 15876 15877 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 15878 UltraSPARC extensions. 15879 15880`-xarch=v8plus | -xarch=v8plusa' 15881 For compatibility with the SunOS v9 assembler. These options are 15882 equivalent to -Av8plus and -Av8plusa, respectively. 15883 15884`-bump' 15885 Warn whenever it is necessary to switch to another level. If an 15886 architecture level is explicitly requested, GAS will not issue 15887 warnings until that level is reached, and will then bump the level 15888 as required (except between incompatible levels). 15889 15890`-32 | -64' 15891 Select the word size, either 32 bits or 64 bits. These options 15892 are only available with the ELF object file format, and require 15893 that the necessary BFD support has been included. 15894 15895 15896File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 15897 158989.35.2 Enforcing aligned data 15899----------------------------- 15900 15901SPARC GAS normally permits data to be misaligned. For example, it 15902permits the `.long' pseudo-op to be used on a byte boundary. However, 15903the native SunOS assemblers issue an error when they see misaligned 15904data. 15905 15906 You can use the `--enforce-aligned-data' option to make SPARC GAS 15907also issue an error about misaligned data, just as the SunOS assemblers 15908do. 15909 15910 The `--enforce-aligned-data' option is not the default because gcc 15911issues misaligned data pseudo-ops when it initializes certain packed 15912data structures (structures defined using the `packed' attribute). You 15913may have to assemble with GAS in order to initialize packed data 15914structures in your own code. 15915 15916 15917File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 15918 159199.35.3 Sparc Syntax 15920------------------- 15921 15922The assembler syntax closely follows The Sparc Architecture Manual, 15923versions 8 and 9, as well as most extensions defined by Sun for their 15924UltraSPARC and Niagara line of processors. 15925 15926* Menu: 15927 15928* Sparc-Chars:: Special Characters 15929* Sparc-Regs:: Register Names 15930* Sparc-Constants:: Constant Names 15931* Sparc-Relocs:: Relocations 15932* Sparc-Size-Translations:: Size Translations 15933 15934 15935File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 15936 159379.35.3.1 Special Characters 15938........................... 15939 15940`#' is the line comment character. 15941 15942 `;' can be used instead of a newline to separate statements. 15943 15944 15945File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 15946 159479.35.3.2 Register Names 15948....................... 15949 15950The Sparc integer register file is broken down into global, outgoing, 15951local, and incoming. 15952 15953 * The 8 global registers are referred to as `%gN'. 15954 15955 * The 8 outgoing registers are referred to as `%oN'. 15956 15957 * The 8 local registers are referred to as `%lN'. 15958 15959 * The 8 incoming registers are referred to as `%iN'. 15960 15961 * The frame pointer register `%i6' can be referenced using the alias 15962 `%fp'. 15963 15964 * The stack pointer register `%o6' can be referenced using the alias 15965 `%sp'. 15966 15967 Floating point registers are simply referred to as `%fN'. When 15968assembling for pre-V9, only 32 floating point registers are available. 15969For V9 and later there are 64, but there are restrictions when 15970referencing the upper 32 registers. They can only be accessed as 15971double or quad, and thus only even or quad numbered accesses are 15972allowed. For example, `%f34' is a legal floating point register, but 15973`%f35' is not. 15974 15975 Certain V9 instructions allow access to ancillary state registers. 15976Most simply they can be referred to as `%asrN' where N can be from 16 15977to 31. However, there are some aliases defined to reference ASR 15978registers defined for various UltraSPARC processors: 15979 15980 * The tick compare register is referred to as `%tick_cmpr'. 15981 15982 * The system tick register is referred to as `%stick'. An alias, 15983 `%sys_tick', exists but is deprecated and should not be used by 15984 new software. 15985 15986 * The system tick compare register is referred to as `%stick_cmpr'. 15987 An alias, `%sys_tick_cmpr', exists but is deprecated and should 15988 not be used by new software. 15989 15990 * The software interrupt register is referred to as `%softint'. 15991 15992 * The set software interrupt register is referred to as 15993 `%set_softint'. The mnemonic `%softint_set' is provided as an 15994 alias. 15995 15996 * The clear software interrupt register is referred to as 15997 `%clear_softint'. The mnemonic `%softint_clear' is provided as an 15998 alias. 15999 16000 * The performance instrumentation counters register is referred to as 16001 `%pic'. 16002 16003 * The performance control register is referred to as `%pcr'. 16004 16005 * The graphics status register is referred to as `%gsr'. 16006 16007 * The V9 dispatch control register is referred to as `%dcr'. 16008 16009 Various V9 branch and conditional move instructions allow 16010specification of which set of integer condition codes to test. These 16011are referred to as `%xcc' and `%icc'. 16012 16013 In V9, there are 4 sets of floating point condition codes which are 16014referred to as `%fccN'. 16015 16016 Several special privileged and non-privileged registers exist: 16017 16018 * The V9 address space identifier register is referred to as `%asi'. 16019 16020 * The V9 restorable windows register is referred to as `%canrestore'. 16021 16022 * The V9 savable windows register is referred to as `%cansave'. 16023 16024 * The V9 clean windows register is referred to as `%cleanwin'. 16025 16026 * The V9 current window pointer register is referred to as `%cwp'. 16027 16028 * The floating-point queue register is referred to as `%fq'. 16029 16030 * The V8 co-processor queue register is referred to as `%cq'. 16031 16032 * The floating point status register is referred to as `%fsr'. 16033 16034 * The other windows register is referred to as `%otherwin'. 16035 16036 * The V9 program counter register is referred to as `%pc'. 16037 16038 * The V9 next program counter register is referred to as `%npc'. 16039 16040 * The V9 processor interrupt level register is referred to as `%pil'. 16041 16042 * The V9 processor state register is referred to as `%pstate'. 16043 16044 * The trap base address register is referred to as `%tba'. 16045 16046 * The V9 tick register is referred to as `%tick'. 16047 16048 * The V9 trap level is referred to as `%tl'. 16049 16050 * The V9 trap program counter is referred to as `%tpc'. 16051 16052 * The V9 trap next program counter is referred to as `%tnpc'. 16053 16054 * The V9 trap state is referred to as `%tstate'. 16055 16056 * The V9 trap type is referred to as `%tt'. 16057 16058 * The V9 condition codes is referred to as `%ccr'. 16059 16060 * The V9 floating-point registers state is referred to as `%fprs'. 16061 16062 * The V9 version register is referred to as `%ver'. 16063 16064 * The V9 window state register is referred to as `%wstate'. 16065 16066 * The Y register is referred to as `%y'. 16067 16068 * The V8 window invalid mask register is referred to as `%wim'. 16069 16070 * The V8 processor state register is referred to as `%psr'. 16071 16072 * The V9 global register level register is referred to as `%gl'. 16073 16074 Several special register names exist for hypervisor mode code: 16075 16076 * The hyperprivileged processor state register is referred to as 16077 `%hpstate'. 16078 16079 * The hyperprivileged trap state register is referred to as 16080 `%htstate'. 16081 16082 * The hyperprivileged interrupt pending register is referred to as 16083 `%hintp'. 16084 16085 * The hyperprivileged trap base address register is referred to as 16086 `%htba'. 16087 16088 * The hyperprivileged implementation version register is referred to 16089 as `%hver'. 16090 16091 * The hyperprivileged system tick compare register is referred to as 16092 `%hstick_cmpr'. Note that there is no `%hstick' register, the 16093 normal `%stick' is used. 16094 16095 16096File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 16097 160989.35.3.3 Constants 16099.................. 16100 16101Several Sparc instructions take an immediate operand field for which 16102mnemonic names exist. Two such examples are `membar' and `prefetch'. 16103Another example are the set of V9 memory access instruction that allow 16104specification of an address space identifier. 16105 16106 The `membar' instruction specifies a memory barrier that is the 16107defined by the operand which is a bitmask. The supported mask 16108mnemonics are: 16109 16110 * `#Sync' requests that all operations (including nonmemory 16111 reference operations) appearing prior to the `membar' must have 16112 been performed and the effects of any exceptions become visible 16113 before any instructions after the `membar' may be initiated. This 16114 corresponds to `membar' cmask field bit 2. 16115 16116 * `#MemIssue' requests that all memory reference operations 16117 appearing prior to the `membar' must have been performed before 16118 any memory operation after the `membar' may be initiated. This 16119 corresponds to `membar' cmask field bit 1. 16120 16121 * `#Lookaside' requests that a store appearing prior to the `membar' 16122 must complete before any load following the `membar' referencing 16123 the same address can be initiated. This corresponds to `membar' 16124 cmask field bit 0. 16125 16126 * `#StoreStore' defines that the effects of all stores appearing 16127 prior to the `membar' instruction must be visible to all 16128 processors before the effect of any stores following the `membar'. 16129 Equivalent to the deprecated `stbar' instruction. This 16130 corresponds to `membar' mmask field bit 3. 16131 16132 * `#LoadStore' defines all loads appearing prior to the `membar' 16133 instruction must have been performed before the effect of any 16134 stores following the `membar' is visible to any other processor. 16135 This corresponds to `membar' mmask field bit 2. 16136 16137 * `#StoreLoad' defines that the effects of all stores appearing 16138 prior to the `membar' instruction must be visible to all 16139 processors before loads following the `membar' may be performed. 16140 This corresponds to `membar' mmask field bit 1. 16141 16142 * `#LoadLoad' defines that all loads appearing prior to the `membar' 16143 instruction must have been performed before any loads following 16144 the `membar' may be performed. This corresponds to `membar' mmask 16145 field bit 0. 16146 16147 16148 These values can be ored together, for example: 16149 16150 membar #Sync 16151 membar #StoreLoad | #LoadLoad 16152 membar #StoreLoad | #StoreStore 16153 16154 The `prefetch' and `prefetcha' instructions take a prefetch function 16155code. The following prefetch function code constant mnemonics are 16156available: 16157 16158 * `#n_reads' requests a prefetch for several reads, and corresponds 16159 to a prefetch function code of 0. 16160 16161 `#one_read' requests a prefetch for one read, and corresponds to a 16162 prefetch function code of 1. 16163 16164 `#n_writes' requests a prefetch for several writes (and possibly 16165 reads), and corresponds to a prefetch function code of 2. 16166 16167 `#one_write' requests a prefetch for one write, and corresponds to 16168 a prefetch function code of 3. 16169 16170 `#page' requests a prefetch page, and corresponds to a prefetch 16171 function code of 4. 16172 16173 `#invalidate' requests a prefetch invalidate, and corresponds to a 16174 prefetch function code of 16. 16175 16176 `#unified' requests a prefetch to the nearest unified cache, and 16177 corresponds to a prefetch function code of 17. 16178 16179 `#n_reads_strong' requests a strong prefetch for several reads, 16180 and corresponds to a prefetch function code of 20. 16181 16182 `#one_read_strong' requests a strong prefetch for one read, and 16183 corresponds to a prefetch function code of 21. 16184 16185 `#n_writes_strong' requests a strong prefetch for several writes, 16186 and corresponds to a prefetch function code of 22. 16187 16188 `#one_write_strong' requests a strong prefetch for one write, and 16189 corresponds to a prefetch function code of 23. 16190 16191 Onle one prefetch code may be specified. Here are some examples: 16192 16193 prefetch [%l0 + %l2], #one_read 16194 prefetch [%g2 + 8], #n_writes 16195 prefetcha [%g1] 0x8, #unified 16196 prefetcha [%o0 + 0x10] %asi, #n_reads 16197 16198 The actual behavior of a given prefetch function code is processor 16199 specific. If a processor does not implement a given prefetch 16200 function code, it will treat the prefetch instruction as a nop. 16201 16202 For instructions that accept an immediate address space identifier, 16203 `as' provides many mnemonics corresponding to V9 defined as well 16204 as UltraSPARC and Niagara extended values. For example, `#ASI_P' 16205 and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor 16206 specific manuals for details. 16207 16208 16209 16210File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 16211 162129.35.3.4 Relocations 16213.................... 16214 16215ELF relocations are available as defined in the 32-bit and 64-bit Sparc 16216ELF specifications. 16217 16218 `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is 16219obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix' 16220and `R_SPARC_LOX10' is obtained using `%lox'. For example: 16221 16222 sethi %hi(symbol), %g1 16223 or %g1, %lo(symbol), %g1 16224 16225 sethi %hix(symbol), %g1 16226 xor %g1, %lox(symbol), %g1 16227 16228 These "high" mnemonics extract bits 31:10 of their operand, and the 16229"low" mnemonics extract bits 9:0 of their operand. 16230 16231 V9 code model relocations can be requested as follows: 16232 16233 * `R_SPARC_HH22' is requested using `%hh'. It can also be generated 16234 using `%uhi'. 16235 16236 * `R_SPARC_HM10' is requested using `%hm'. It can also be generated 16237 using `%ulo'. 16238 16239 * `R_SPARC_LM22' is requested using `%lm'. 16240 16241 * `R_SPARC_H44' is requested using `%h44'. 16242 16243 * `R_SPARC_M44' is requested using `%m44'. 16244 16245 * `R_SPARC_L44' is requested using `%l44'. 16246 16247 The PC relative relocation `R_SPARC_PC22' can be obtained by 16248enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10' 16249relocation can be obtained using `%pc10'. These are mostly used when 16250assembling PIC code. For example, the standard PIC sequence on Sparc 16251to get the base of the global offset table, PC relative, into a 16252register, can be performed as: 16253 16254 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 16255 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 16256 16257 Several relocations exist to allow the link editor to potentially 16258optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22' 16259relocation can obtained by enclosing an operand inside of 16260`%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained 16261by enclosing an operand inside of `%gdop_lox10'. Likewise, 16262`R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of 16263`%gdop'. For example, assuming the GOT base is in register `%l7': 16264 16265 sethi %gdop_hix22(symbol), %l1 16266 xor %l1, %gdop_lox10(symbol), %l1 16267 ld [%l7 + %l1], %l2, %gdop(symbol) 16268 16269 There are many relocations that can be requested for access to 16270thread local storage variables. All of the Sparc TLS mnemonics are 16271supported: 16272 16273 * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'. 16274 16275 * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'. 16276 16277 * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'. 16278 16279 * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'. 16280 16281 * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'. 16282 16283 * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'. 16284 16285 * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'. 16286 16287 * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'. 16288 16289 * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'. 16290 16291 * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'. 16292 16293 * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'. 16294 16295 * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'. 16296 16297 * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'. 16298 16299 * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'. 16300 16301 * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'. 16302 16303 * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'. 16304 16305 * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'. 16306 16307 * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'. 16308 16309 Here are some example TLS model sequences. 16310 16311 First, General Dynamic: 16312 16313 sethi %tgd_hi22(symbol), %l1 16314 add %l1, %tgd_lo10(symbol), %l1 16315 add %l7, %l1, %o0, %tgd_add(symbol) 16316 call __tls_get_addr, %tgd_call(symbol) 16317 nop 16318 16319 Local Dynamic: 16320 16321 sethi %tldm_hi22(symbol), %l1 16322 add %l1, %tldm_lo10(symbol), %l1 16323 add %l7, %l1, %o0, %tldm_add(symbol) 16324 call __tls_get_addr, %tldm_call(symbol) 16325 nop 16326 16327 sethi %tldo_hix22(symbol), %l1 16328 xor %l1, %tldo_lox10(symbol), %l1 16329 add %o0, %l1, %l1, %tldo_add(symbol) 16330 16331 Initial Exec: 16332 16333 sethi %tie_hi22(symbol), %l1 16334 add %l1, %tie_lo10(symbol), %l1 16335 ld [%l7 + %l1], %o0, %tie_ld(symbol) 16336 add %g7, %o0, %o0, %tie_add(symbol) 16337 16338 sethi %tie_hi22(symbol), %l1 16339 add %l1, %tie_lo10(symbol), %l1 16340 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 16341 add %g7, %o0, %o0, %tie_add(symbol) 16342 16343 And finally, Local Exec: 16344 16345 sethi %tle_hix22(symbol), %l1 16346 add %l1, %tle_lox10(symbol), %l1 16347 add %g7, %l1, %l1 16348 16349 When assembling for 64-bit, and a secondary constant addend is 16350specified in an address expression that would normally generate an 16351`R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10' 16352instead. 16353 16354 16355File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 16356 163579.35.3.5 Size Translations 16358.......................... 16359 16360Often it is desirable to write code in an operand size agnostic manner. 16361`as' provides support for this via operand size opcode translations. 16362Translations are supported for loads, stores, shifts, compare-and-swap 16363atomics, and the `clr' synthetic instruction. 16364 16365 If generating 32-bit code, `as' will generate the 32-bit opcode. 16366Whereas if 64-bit code is being generated, the 64-bit opcode will be 16367emitted. For example `ldn' will be transformed into `ld' for 32-bit 16368code and `ldx' for 64-bit code. 16369 16370 Here is an example meant to demonstrate all the supported opcode 16371translations: 16372 16373 ldn [%o0], %o1 16374 ldna [%o0] %asi, %o2 16375 stn %o1, [%o0] 16376 stna %o2, [%o0] %asi 16377 slln %o3, 3, %o3 16378 srln %o4, 8, %o4 16379 sran %o5, 12, %o5 16380 casn [%o0], %o1, %o2 16381 casna [%o0] %asi, %o1, %o2 16382 clrn %g1 16383 16384 In 32-bit mode `as' will emit: 16385 16386 ld [%o0], %o1 16387 lda [%o0] %asi, %o2 16388 st %o1, [%o0] 16389 sta %o2, [%o0] %asi 16390 sll %o3, 3, %o3 16391 srl %o4, 8, %o4 16392 sra %o5, 12, %o5 16393 cas [%o0], %o1, %o2 16394 casa [%o0] %asi, %o1, %o2 16395 clr %g1 16396 16397 And in 64-bit mode `as' will emit: 16398 16399 ldx [%o0], %o1 16400 ldxa [%o0] %asi, %o2 16401 stx %o1, [%o0] 16402 stxa %o2, [%o0] %asi 16403 sllx %o3, 3, %o3 16404 srlx %o4, 8, %o4 16405 srax %o5, 12, %o5 16406 casx [%o0], %o1, %o2 16407 casxa [%o0] %asi, %o1, %o2 16408 clrx %g1 16409 16410 Finally, the `.nword' translating directive is supported as well. 16411It is documented in the section on Sparc machine directives. 16412 16413 16414File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 16415 164169.35.4 Floating Point 16417--------------------- 16418 16419The Sparc uses IEEE floating-point numbers. 16420 16421 16422File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 16423 164249.35.5 Sparc Machine Directives 16425------------------------------- 16426 16427The Sparc version of `as' supports the following additional machine 16428directives: 16429 16430`.align' 16431 This must be followed by the desired alignment in bytes. 16432 16433`.common' 16434 This must be followed by a symbol name, a positive number, and 16435 `"bss"'. This behaves somewhat like `.comm', but the syntax is 16436 different. 16437 16438`.half' 16439 This is functionally identical to `.short'. 16440 16441`.nword' 16442 On the Sparc, the `.nword' directive produces native word sized 16443 value, ie. if assembling with -32 it is equivalent to `.word', if 16444 assembling with -64 it is equivalent to `.xword'. 16445 16446`.proc' 16447 This directive is ignored. Any text following it on the same line 16448 is also ignored. 16449 16450`.register' 16451 This directive declares use of a global application or system 16452 register. It must be followed by a register name %g2, %g3, %g6 or 16453 %g7, comma and the symbol name for that register. If symbol name 16454 is `#scratch', it is a scratch register, if it is `#ignore', it 16455 just suppresses any errors about using undeclared global register, 16456 but does not emit any information about it into the object file. 16457 This can be useful e.g. if you save the register before use and 16458 restore it after. 16459 16460`.reserve' 16461 This must be followed by a symbol name, a positive number, and 16462 `"bss"'. This behaves somewhat like `.lcomm', but the syntax is 16463 different. 16464 16465`.seg' 16466 This must be followed by `"text"', `"data"', or `"data1"'. It 16467 behaves like `.text', `.data', or `.data 1'. 16468 16469`.skip' 16470 This is functionally identical to the `.space' directive. 16471 16472`.word' 16473 On the Sparc, the `.word' directive produces 32 bit values, 16474 instead of the 16 bit values it produces on many other machines. 16475 16476`.xword' 16477 On the Sparc V9 processor, the `.xword' directive produces 64 bit 16478 values. 16479 16480 16481File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 16482 164839.36 TIC54X Dependent Features 16484============================== 16485 16486* Menu: 16487 16488* TIC54X-Opts:: Command-line Options 16489* TIC54X-Block:: Blocking 16490* TIC54X-Env:: Environment Settings 16491* TIC54X-Constants:: Constants Syntax 16492* TIC54X-Subsyms:: String Substitution 16493* TIC54X-Locals:: Local Label Syntax 16494* TIC54X-Builtins:: Builtin Assembler Math Functions 16495* TIC54X-Ext:: Extended Addressing Support 16496* TIC54X-Directives:: Directives 16497* TIC54X-Macros:: Macro Features 16498* TIC54X-MMRegs:: Memory-mapped Registers 16499 16500 16501File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 16502 165039.36.1 Options 16504-------------- 16505 16506The TMS320C54X version of `as' has a few machine-dependent options. 16507 16508 You can use the `-mfar-mode' option to enable extended addressing 16509mode. All addresses will be assumed to be > 16 bits, and the 16510appropriate relocation types will be used. This option is equivalent 16511to using the `.far_mode' directive in the assembly code. If you do not 16512use the `-mfar-mode' option, all references will be assumed to be 16 16513bits. This option may be abbreviated to `-mf'. 16514 16515 You can use the `-mcpu' option to specify a particular CPU. This 16516option is equivalent to using the `.version' directive in the assembly 16517code. For recognized CPU codes, see *Note `.version': 16518TIC54X-Directives. The default CPU version is `542'. 16519 16520 You can use the `-merrors-to-file' option to redirect error output 16521to a file (this provided for those deficient environments which don't 16522provide adequate output redirection). This option may be abbreviated to 16523`-me'. 16524 16525 16526File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 16527 165289.36.2 Blocking 16529--------------- 16530 16531A blocked section or memory block is guaranteed not to cross the 16532blocking boundary (usually a page, or 128 words) if it is smaller than 16533the blocking size, or to start on a page boundary if it is larger than 16534the blocking size. 16535 16536 16537File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 16538 165399.36.3 Environment Settings 16540--------------------------- 16541 16542`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added 16543to the list of directories normally searched for source and include 16544files. `C54XDSP_DIR' will override `A_DIR'. 16545 16546 16547File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 16548 165499.36.4 Constants Syntax 16550----------------------- 16551 16552The TIC54X version of `as' allows the following additional constant 16553formats, using a suffix to indicate the radix: 16554 16555 Binary `000000B, 011000b' 16556 Octal `10Q, 224q' 16557 Hexadecimal `45h, 0FH' 16558 16559 16560File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 16561 165629.36.5 String Substitution 16563-------------------------- 16564 16565A subset of allowable symbols (which we'll call subsyms) may be assigned 16566arbitrary string values. This is roughly equivalent to C preprocessor 16567#define macros. When `as' encounters one of these symbols, the symbol 16568is replaced in the input stream by its string value. Subsym names 16569*must* begin with a letter. 16570 16571 Subsyms may be defined using the `.asg' and `.eval' directives 16572(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives. 16573 16574 Expansion is recursive until a previously encountered symbol is 16575seen, at which point substitution stops. 16576 16577 In this example, x is replaced with SYM2; SYM2 is replaced with 16578SYM1, and SYM1 is replaced with x. At this point, x has already been 16579encountered and the substitution stops. 16580 16581 .asg "x",SYM1 16582 .asg "SYM1",SYM2 16583 .asg "SYM2",x 16584 add x,a ; final code assembled is "add x, a" 16585 16586 Macro parameters are converted to subsyms; a side effect of this is 16587the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms 16588defined within a macro will have global scope, unless the `.var' 16589directive is used to identify the subsym as a local macro variable 16590*note `.var': TIC54X-Directives. 16591 16592 Substitution may be forced in situations where replacement might be 16593ambiguous by placing colons on either side of the subsym. The following 16594code: 16595 16596 .eval "10",x 16597 LAB:X: add #x, a 16598 16599 When assembled becomes: 16600 16601 LAB10 add #10, a 16602 16603 Smaller parts of the string assigned to a subsym may be accessed with 16604the following syntax: 16605 16606``:SYMBOL(CHAR_INDEX):'' 16607 Evaluates to a single-character string, the character at 16608 CHAR_INDEX. 16609 16610``:SYMBOL(START,LENGTH):'' 16611 Evaluates to a substring of SYMBOL beginning at START with length 16612 LENGTH. 16613 16614 16615File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 16616 166179.36.6 Local Labels 16618------------------- 16619 16620Local labels may be defined in two ways: 16621 16622 * $N, where N is a decimal number between 0 and 9 16623 16624 * LABEL?, where LABEL is any legal symbol name. 16625 16626 Local labels thus defined may be redefined or automatically 16627generated. The scope of a local label is based on when it may be 16628undefined or reset. This happens when one of the following situations 16629is encountered: 16630 16631 * .newblock directive *note `.newblock': TIC54X-Directives. 16632 16633 * The current section is changed (.sect, .text, or .data) 16634 16635 * Entering or leaving an included file 16636 16637 * The macro scope where the label was defined is exited 16638 16639 16640File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 16641 166429.36.7 Math Builtins 16643-------------------- 16644 16645The following built-in functions may be used to generate a 16646floating-point value. All return a floating-point value except `$cvi', 16647`$int', and `$sgn', which return an integer value. 16648 16649``$acos(EXPR)'' 16650 Returns the floating point arccosine of EXPR. 16651 16652``$asin(EXPR)'' 16653 Returns the floating point arcsine of EXPR. 16654 16655``$atan(EXPR)'' 16656 Returns the floating point arctangent of EXPR. 16657 16658``$atan2(EXPR1,EXPR2)'' 16659 Returns the floating point arctangent of EXPR1 / EXPR2. 16660 16661``$ceil(EXPR)'' 16662 Returns the smallest integer not less than EXPR as floating point. 16663 16664``$cosh(EXPR)'' 16665 Returns the floating point hyperbolic cosine of EXPR. 16666 16667``$cos(EXPR)'' 16668 Returns the floating point cosine of EXPR. 16669 16670``$cvf(EXPR)'' 16671 Returns the integer value EXPR converted to floating-point. 16672 16673``$cvi(EXPR)'' 16674 Returns the floating point value EXPR converted to integer. 16675 16676``$exp(EXPR)'' 16677 Returns the floating point value e ^ EXPR. 16678 16679``$fabs(EXPR)'' 16680 Returns the floating point absolute value of EXPR. 16681 16682``$floor(EXPR)'' 16683 Returns the largest integer that is not greater than EXPR as 16684 floating point. 16685 16686``$fmod(EXPR1,EXPR2)'' 16687 Returns the floating point remainder of EXPR1 / EXPR2. 16688 16689``$int(EXPR)'' 16690 Returns 1 if EXPR evaluates to an integer, zero otherwise. 16691 16692``$ldexp(EXPR1,EXPR2)'' 16693 Returns the floating point value EXPR1 * 2 ^ EXPR2. 16694 16695``$log10(EXPR)'' 16696 Returns the base 10 logarithm of EXPR. 16697 16698``$log(EXPR)'' 16699 Returns the natural logarithm of EXPR. 16700 16701``$max(EXPR1,EXPR2)'' 16702 Returns the floating point maximum of EXPR1 and EXPR2. 16703 16704``$min(EXPR1,EXPR2)'' 16705 Returns the floating point minimum of EXPR1 and EXPR2. 16706 16707``$pow(EXPR1,EXPR2)'' 16708 Returns the floating point value EXPR1 ^ EXPR2. 16709 16710``$round(EXPR)'' 16711 Returns the nearest integer to EXPR as a floating point number. 16712 16713``$sgn(EXPR)'' 16714 Returns -1, 0, or 1 based on the sign of EXPR. 16715 16716``$sin(EXPR)'' 16717 Returns the floating point sine of EXPR. 16718 16719``$sinh(EXPR)'' 16720 Returns the floating point hyperbolic sine of EXPR. 16721 16722``$sqrt(EXPR)'' 16723 Returns the floating point square root of EXPR. 16724 16725``$tan(EXPR)'' 16726 Returns the floating point tangent of EXPR. 16727 16728``$tanh(EXPR)'' 16729 Returns the floating point hyperbolic tangent of EXPR. 16730 16731``$trunc(EXPR)'' 16732 Returns the integer value of EXPR truncated towards zero as 16733 floating point. 16734 16735 16736 16737File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 16738 167399.36.8 Extended Addressing 16740-------------------------- 16741 16742The `LDX' pseudo-op is provided for loading the extended addressing bits 16743of a label or address. For example, if an address `_label' resides in 16744extended program memory, the value of `_label' may be loaded as follows: 16745 ldx #_label,16,a ; loads extended bits of _label 16746 or #_label,a ; loads lower 16 bits of _label 16747 bacc a ; full address is in accumulator A 16748 16749 16750File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 16751 167529.36.9 Directives 16753----------------- 16754 16755`.align [SIZE]' 16756`.even' 16757 Align the section program counter on the next boundary, based on 16758 SIZE. SIZE may be any power of 2. `.even' is equivalent to 16759 `.align' with a SIZE of 2. 16760 `1' 16761 Align SPC to word boundary 16762 16763 `2' 16764 Align SPC to longword boundary (same as .even) 16765 16766 `128' 16767 Align SPC to page boundary 16768 16769`.asg STRING, NAME' 16770 Assign NAME the string STRING. String replacement is performed on 16771 STRING before assignment. 16772 16773`.eval STRING, NAME' 16774 Evaluate the contents of string STRING and assign the result as a 16775 string to the subsym NAME. String replacement is performed on 16776 STRING before assignment. 16777 16778`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 16779 Reserve space for SYMBOL in the .bss section. SIZE is in words. 16780 If present, BLOCKING_FLAG indicates the allocated space should be 16781 aligned on a page boundary if it would otherwise cross a page 16782 boundary. If present, ALIGNMENT_FLAG causes the assembler to 16783 allocate SIZE on a long word boundary. 16784 16785`.byte VALUE [,...,VALUE_N]' 16786`.ubyte VALUE [,...,VALUE_N]' 16787`.char VALUE [,...,VALUE_N]' 16788`.uchar VALUE [,...,VALUE_N]' 16789 Place one or more bytes into consecutive words of the current 16790 section. The upper 8 bits of each word is zero-filled. If a 16791 label is used, it points to the word allocated for the first byte 16792 encountered. 16793 16794`.clink ["SECTION_NAME"]' 16795 Set STYP_CLINK flag for this section, which indicates to the 16796 linker that if no symbols from this section are referenced, the 16797 section should not be included in the link. If SECTION_NAME is 16798 omitted, the current section is used. 16799 16800`.c_mode' 16801 TBD. 16802 16803`.copy "FILENAME" | FILENAME' 16804`.include "FILENAME" | FILENAME' 16805 Read source statements from FILENAME. The normal include search 16806 path is used. Normally .copy will cause statements from the 16807 included file to be printed in the assembly listing and .include 16808 will not, but this distinction is not currently implemented. 16809 16810`.data' 16811 Begin assembling code into the .data section. 16812 16813`.double VALUE [,...,VALUE_N]' 16814`.ldouble VALUE [,...,VALUE_N]' 16815`.float VALUE [,...,VALUE_N]' 16816`.xfloat VALUE [,...,VALUE_N]' 16817 Place an IEEE single-precision floating-point representation of 16818 one or more floating-point values into the current section. All 16819 but `.xfloat' align the result on a longword boundary. Values are 16820 stored most-significant word first. 16821 16822`.drlist' 16823`.drnolist' 16824 Control printing of directives to the listing file. Ignored. 16825 16826`.emsg STRING' 16827`.mmsg STRING' 16828`.wmsg STRING' 16829 Emit a user-defined error, message, or warning, respectively. 16830 16831`.far_mode' 16832 Use extended addressing when assembling statements. This should 16833 appear only once per file, and is equivalent to the -mfar-mode 16834 option *note `-mfar-mode': TIC54X-Opts. 16835 16836`.fclist' 16837`.fcnolist' 16838 Control printing of false conditional blocks to the listing file. 16839 16840`.field VALUE [,SIZE]' 16841 Initialize a bitfield of SIZE bits in the current section. If 16842 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 16843 bits. If VALUE does not fit into SIZE bits, the value will be 16844 truncated. Successive `.field' directives will pack starting at 16845 the current word, filling the most significant bits first, and 16846 aligning to the start of the next word if the field size does not 16847 fit into the space remaining in the current word. A `.align' 16848 directive with an operand of 1 will force the next `.field' 16849 directive to begin packing into a new word. If a label is used, it 16850 points to the word that contains the specified field. 16851 16852`.global SYMBOL [,...,SYMBOL_N]' 16853`.def SYMBOL [,...,SYMBOL_N]' 16854`.ref SYMBOL [,...,SYMBOL_N]' 16855 `.def' nominally identifies a symbol defined in the current file 16856 and available to other files. `.ref' identifies a symbol used in 16857 the current file but defined elsewhere. Both map to the standard 16858 `.global' directive. 16859 16860`.half VALUE [,...,VALUE_N]' 16861`.uhalf VALUE [,...,VALUE_N]' 16862`.short VALUE [,...,VALUE_N]' 16863`.ushort VALUE [,...,VALUE_N]' 16864`.int VALUE [,...,VALUE_N]' 16865`.uint VALUE [,...,VALUE_N]' 16866`.word VALUE [,...,VALUE_N]' 16867`.uword VALUE [,...,VALUE_N]' 16868 Place one or more values into consecutive words of the current 16869 section. If a label is used, it points to the word allocated for 16870 the first value encountered. 16871 16872`.label SYMBOL' 16873 Define a special SYMBOL to refer to the load time address of the 16874 current section program counter. 16875 16876`.length' 16877`.width' 16878 Set the page length and width of the output listing file. Ignored. 16879 16880`.list' 16881`.nolist' 16882 Control whether the source listing is printed. Ignored. 16883 16884`.long VALUE [,...,VALUE_N]' 16885`.ulong VALUE [,...,VALUE_N]' 16886`.xlong VALUE [,...,VALUE_N]' 16887 Place one or more 32-bit values into consecutive words in the 16888 current section. The most significant word is stored first. 16889 `.long' and `.ulong' align the result on a longword boundary; 16890 `xlong' does not. 16891 16892`.loop [COUNT]' 16893`.break [CONDITION]' 16894`.endloop' 16895 Repeatedly assemble a block of code. `.loop' begins the block, and 16896 `.endloop' marks its termination. COUNT defaults to 1024, and 16897 indicates the number of times the block should be repeated. 16898 `.break' terminates the loop so that assembly begins after the 16899 `.endloop' directive. The optional CONDITION will cause the loop 16900 to terminate only if it evaluates to zero. 16901 16902`MACRO_NAME .macro [PARAM1][,...PARAM_N]' 16903`[.mexit]' 16904`.endm' 16905 See the section on macros for more explanation (*Note 16906 TIC54X-Macros::. 16907 16908`.mlib "FILENAME" | FILENAME' 16909 Load the macro library FILENAME. FILENAME must be an archived 16910 library (BFD ar-compatible) of text files, expected to contain 16911 only macro definitions. The standard include search path is used. 16912 16913`.mlist' 16914`.mnolist' 16915 Control whether to include macro and loop block expansions in the 16916 listing output. Ignored. 16917 16918`.mmregs' 16919 Define global symbolic names for the 'c54x registers. Supposedly 16920 equivalent to executing `.set' directives for each register with 16921 its memory-mapped value, but in reality is provided only for 16922 compatibility and does nothing. 16923 16924`.newblock' 16925 This directive resets any TIC54X local labels currently defined. 16926 Normal `as' local labels are unaffected. 16927 16928`.option OPTION_LIST' 16929 Set listing options. Ignored. 16930 16931`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 16932 Designate SECTION_NAME for blocking. Blocking guarantees that a 16933 section will start on a page boundary (128 words) if it would 16934 otherwise cross a page boundary. Only initialized sections may be 16935 designated with this directive. See also *Note TIC54X-Block::. 16936 16937`.sect "SECTION_NAME"' 16938 Define a named initialized section and make it the current section. 16939 16940`SYMBOL .set "VALUE"' 16941`SYMBOL .equ "VALUE"' 16942 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 16943 table. SYMBOL may not be previously defined. 16944 16945`.space SIZE_IN_BITS' 16946`.bes SIZE_IN_BITS' 16947 Reserve the given number of bits in the current section and 16948 zero-fill them. If a label is used with `.space', it points to the 16949 *first* word reserved. With `.bes', the label points to the 16950 *last* word reserved. 16951 16952`.sslist' 16953`.ssnolist' 16954 Controls the inclusion of subsym replacement in the listing 16955 output. Ignored. 16956 16957`.string "STRING" [,...,"STRING_N"]' 16958`.pstring "STRING" [,...,"STRING_N"]' 16959 Place 8-bit characters from STRING into the current section. 16960 `.string' zero-fills the upper 8 bits of each word, while 16961 `.pstring' puts two characters into each word, filling the 16962 most-significant bits first. Unused space is zero-filled. If a 16963 label is used, it points to the first word initialized. 16964 16965`[STAG] .struct [OFFSET]' 16966`[NAME_1] element [COUNT_1]' 16967`[NAME_2] element [COUNT_2]' 16968`[TNAME] .tag STAGX [TCOUNT]' 16969`...' 16970`[NAME_N] element [COUNT_N]' 16971`[SSIZE] .endstruct' 16972`LABEL .tag [STAG]' 16973 Assign symbolic offsets to the elements of a structure. STAG 16974 defines a symbol to use to reference the structure. OFFSET 16975 indicates a starting value to use for the first element 16976 encountered; otherwise it defaults to zero. Each element can have 16977 a named offset, NAME, which is a symbol assigned the value of the 16978 element's offset into the structure. If STAG is missing, these 16979 become global symbols. COUNT adjusts the offset that many times, 16980 as if `element' were an array. `element' may be one of `.byte', 16981 `.word', `.long', `.float', or any equivalent of those, and the 16982 structure offset is adjusted accordingly. `.field' and `.string' 16983 are also allowed; the size of `.field' is one bit, and `.string' 16984 is considered to be one word in size. Only element descriptors, 16985 structure/union tags, `.align' and conditional assembly directives 16986 are allowed within `.struct'/`.endstruct'. `.align' aligns member 16987 offsets to word boundaries only. SSIZE, if provided, will always 16988 be assigned the size of the structure. 16989 16990 The `.tag' directive, in addition to being used to define a 16991 structure/union element within a structure, may be used to apply a 16992 structure to a symbol. Once applied to LABEL, the individual 16993 structure elements may be applied to LABEL to produce the desired 16994 offsets using LABEL as the structure base. 16995 16996`.tab' 16997 Set the tab size in the output listing. Ignored. 16998 16999`[UTAG] .union' 17000`[NAME_1] element [COUNT_1]' 17001`[NAME_2] element [COUNT_2]' 17002`[TNAME] .tag UTAGX[,TCOUNT]' 17003`...' 17004`[NAME_N] element [COUNT_N]' 17005`[USIZE] .endstruct' 17006`LABEL .tag [UTAG]' 17007 Similar to `.struct', but the offset after each element is reset to 17008 zero, and the USIZE is set to the maximum of all defined elements. 17009 Starting offset for the union is always zero. 17010 17011`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 17012 Reserve space for variables in a named, uninitialized section 17013 (similar to .bss). `.usect' allows definitions sections 17014 independent of .bss. SYMBOL points to the first location reserved 17015 by this allocation. The symbol may be used as a variable name. 17016 SIZE is the allocated size in words. BLOCKING_FLAG indicates 17017 whether to block this section on a page boundary (128 words) 17018 (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the 17019 section should be longword-aligned. 17020 17021`.var SYM[,..., SYM_N]' 17022 Define a subsym to be a local variable within a macro. See *Note 17023 TIC54X-Macros::. 17024 17025`.version VERSION' 17026 Set which processor to build instructions for. Though the 17027 following values are accepted, the op is ignored. 17028 `541' 17029 `542' 17030 `543' 17031 `545' 17032 `545LP' 17033 `546LP' 17034 `548' 17035 `549' 17036 17037 17038File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 17039 170409.36.10 Macros 17041-------------- 17042 17043Macros do not require explicit dereferencing of arguments (i.e., \ARG). 17044 17045 During macro expansion, the macro parameters are converted to 17046subsyms. If the number of arguments passed the macro invocation 17047exceeds the number of parameters defined, the last parameter is 17048assigned the string equivalent of all remaining arguments. If fewer 17049arguments are given than parameters, the missing parameters are 17050assigned empty strings. To include a comma in an argument, you must 17051enclose the argument in quotes. 17052 17053 The following built-in subsym functions allow examination of the 17054string value of subsyms (or ordinary strings). The arguments are 17055strings unless otherwise indicated (subsyms passed as args will be 17056replaced by the strings they represent). 17057``$symlen(STR)'' 17058 Returns the length of STR. 17059 17060``$symcmp(STR1,STR2)'' 17061 Returns 0 if STR1 == STR2, non-zero otherwise. 17062 17063``$firstch(STR,CH)'' 17064 Returns index of the first occurrence of character constant CH in 17065 STR. 17066 17067``$lastch(STR,CH)'' 17068 Returns index of the last occurrence of character constant CH in 17069 STR. 17070 17071``$isdefed(SYMBOL)'' 17072 Returns zero if the symbol SYMBOL is not in the symbol table, 17073 non-zero otherwise. 17074 17075``$ismember(SYMBOL,LIST)'' 17076 Assign the first member of comma-separated string LIST to SYMBOL; 17077 LIST is reassigned the remainder of the list. Returns zero if 17078 LIST is a null string. Both arguments must be subsyms. 17079 17080``$iscons(EXPR)'' 17081 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 17082 4 if a character, 5 if decimal, and zero if not an integer. 17083 17084``$isname(NAME)'' 17085 Returns 1 if NAME is a valid symbol name, zero otherwise. 17086 17087``$isreg(REG)'' 17088 Returns 1 if REG is a valid predefined register name (AR0-AR7 17089 only). 17090 17091``$structsz(STAG)'' 17092 Returns the size of the structure or union represented by STAG. 17093 17094``$structacc(STAG)'' 17095 Returns the reference point of the structure or union represented 17096 by STAG. Always returns zero. 17097 17098 17099 17100File: as.info, Node: TIC54X-MMRegs, Prev: TIC54X-Macros, Up: TIC54X-Dependent 17101 171029.36.11 Memory-mapped Registers 17103------------------------------- 17104 17105The following symbols are recognized as memory-mapped registers: 17106 17107 17108 17109File: as.info, Node: TIC6X-Dependent, Next: V850-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 17110 171119.37 TIC6X Dependent Features 17112============================= 17113 17114* Menu: 17115 17116* TIC6X Options:: Options 17117* TIC6X Syntax:: Syntax 17118* TIC6X Directives:: Directives 17119 17120 17121File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 17122 171239.37.1 TIC6X Options 17124-------------------- 17125 17126`-march=ARCH' 17127 Enable (only) instructions from architecture ARCH. By default, 17128 all instructions are permitted. 17129 17130 The following values of ARCH are accepted: `c62x', `c64x', 17131 `c64x+', `c67x', `c67x+', `c674x'. 17132 17133`-matomic' 17134`-mno-atomic' 17135 Enable or disable the optional C64x+ atomic operation instructions. 17136 By default, they are enabled if no `-march' option is given, or if 17137 an architecture is specified with `-march' that implies these 17138 instructions are present (currently, there are no such 17139 architectures); they are disabled if an architecture is specified 17140 with `-march' on which the instructions are optional or not 17141 present. This option overrides such a default from the 17142 architecture, independent of the order in which the `-march' or 17143 `-matomic' or `-mno-atomic' options are passed. 17144 17145`-mdsbt' 17146`-mno-dsbt' 17147 The `-mdsbt' option causes the assembler to generate the 17148 `Tag_ABI_DSBT' attribute with a value of 1, indicating that the 17149 code is using DSBT addressing. The `-mno-dsbt' option, the 17150 default, causes the tag to have a value of 0, indicating that the 17151 code does not use DSBT addressing. The linker will emit a warning 17152 if objects of different type (DSBT and non-DSBT) are linked 17153 together. 17154 17155`-mpid=no' 17156`-mpid=near' 17157`-mpid=far' 17158 The `-mpid=' option causes the assembler to generate the 17159 `Tag_ABI_PID' attribute with a value indicating the form of data 17160 addressing used by the code. `-mpid=no', the default, indicates 17161 position-dependent data addressing, `-mpid=near' indicates 17162 position-independent addressing with GOT accesses using near DP 17163 addressing, and `-mpid=far' indicates position-independent 17164 addressing with GOT accesses using far DP addressing. The linker 17165 will emit a warning if objects built with different settings of 17166 this option are linked together. 17167 17168`-mpic' 17169`-mno-pic' 17170 The `-mpic' option causes the assembler to generate the 17171 `Tag_ABI_PIC' attribute with a value of 1, indicating that the 17172 code is using position-independent code addressing, The 17173 `-mno-pic' option, the default, causes the tag to have a value of 17174 0, indicating position-dependent code addressing. The linker will 17175 emit a warning if objects of different type (position-dependent and 17176 position-independent) are linked together. 17177 17178`-mbig-endian' 17179`-mlittle-endian' 17180 Generate code for the specified endianness. The default is 17181 little-endian. 17182 17183 17184 17185File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 17186 171879.37.2 TIC6X Syntax 17188------------------- 17189 17190The presence of a `;' on a line indicates the start of a comment that 17191extends to the end of the current line. If a `#' or `*' appears as the 17192first character of a line, the whole line is treated as a comment. 17193 17194 The `@' character can be used instead of a newline to separate 17195statements. 17196 17197 Instruction, register and functional unit names are case-insensitive. 17198`as' requires fully-specified functional unit names, such as `.S1', 17199`.L1X' or `.D1T2', on all instructions using a functional unit. 17200 17201 For some instructions, there may be syntactic ambiguity between 17202register or functional unit names and the names of labels or other 17203symbols. To avoid this, enclose the ambiguous symbol name in 17204parentheses; register and functional unit names may not be enclosed in 17205parentheses. 17206 17207 17208File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 17209 172109.37.3 TIC6X Directives 17211----------------------- 17212 17213Directives controlling the set of instructions accepted by the 17214assembler have effect for instructions between the directive and any 17215subsequent directive overriding it. 17216 17217`.arch ARCH' 17218 This has the same effect as `-march=ARCH'. 17219 17220`.atomic' 17221`.noatomic' 17222 These have the same effects as `-matomic' and `-mno-atomic'. 17223 17224`.c6xabi_attribute TAG, VALUE' 17225 Set the C6000 EABI build attribute TAG to VALUE. 17226 17227 The TAG is either an attribute number or one of `Tag_ISA', 17228 `Tag_ABI_wchar_t', `Tag_ABI_stack_align_needed', 17229 `Tag_ABI_stack_align_preserved', `Tag_ABI_DSBT', `Tag_ABI_PID', 17230 `Tag_ABI_PIC', `TAG_ABI_array_object_alignment', 17231 `TAG_ABI_array_object_align_expected', `Tag_ABI_compatibility' and 17232 `Tag_ABI_conformance'. The VALUE is either a `number', 17233 `"string"', or `number, "string"' depending on the tag. 17234 17235`.nocmp' 17236 Disallow use of C64x+ compact instructions in the current text 17237 section. 17238 17239 17240 17241File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 17242 172439.38 Z80 Dependent Features 17244=========================== 17245 17246* Menu: 17247 17248* Z80 Options:: Options 17249* Z80 Syntax:: Syntax 17250* Z80 Floating Point:: Floating Point 17251* Z80 Directives:: Z80 Machine Directives 17252* Z80 Opcodes:: Opcodes 17253 17254 17255File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 17256 172579.38.1 Options 17258-------------- 17259 17260The Zilog Z80 and Ascii R800 version of `as' have a few machine 17261dependent options. 17262`-z80' 17263 Produce code for the Z80 processor. There are additional options to 17264 request warnings and error messages for undocumented instructions. 17265 17266`-ignore-undocumented-instructions' 17267`-Wnud' 17268 Silently assemble undocumented Z80-instructions that have been 17269 adopted as documented R800-instructions. 17270 17271`-ignore-unportable-instructions' 17272`-Wnup' 17273 Silently assemble all undocumented Z80-instructions. 17274 17275`-warn-undocumented-instructions' 17276`-Wud' 17277 Issue warnings for undocumented Z80-instructions that work on 17278 R800, do not assemble other undocumented instructions without 17279 warning. 17280 17281`-warn-unportable-instructions' 17282`-Wup' 17283 Issue warnings for other undocumented Z80-instructions, do not 17284 treat any undocumented instructions as errors. 17285 17286`-forbid-undocumented-instructions' 17287`-Fud' 17288 Treat all undocumented z80-instructions as errors. 17289 17290`-forbid-unportable-instructions' 17291`-Fup' 17292 Treat undocumented z80-instructions that do not work on R800 as 17293 errors. 17294 17295`-r800' 17296 Produce code for the R800 processor. The assembler does not support 17297 undocumented instructions for the R800. In line with common 17298 practice, `as' uses Z80 instruction names for the R800 processor, 17299 as far as they exist. 17300 17301 17302File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 17303 173049.38.2 Syntax 17305------------- 17306 17307The assembler syntax closely follows the 'Z80 family CPU User Manual' by 17308Zilog. In expressions a single `=' may be used as "is equal to" 17309comparison operator. 17310 17311 Suffices can be used to indicate the radix of integer constants; `H' 17312or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o' 17313for octal, and `B' for binary. 17314 17315 The suffix `b' denotes a backreference to local label. 17316 17317* Menu: 17318 17319* Z80-Chars:: Special Characters 17320* Z80-Regs:: Register Names 17321* Z80-Case:: Case Sensitivity 17322 17323 17324File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 17325 173269.38.2.1 Special Characters 17327........................... 17328 17329The semicolon `;' is the line comment character; 17330 17331 The dollar sign `$' can be used as a prefix for hexadecimal numbers 17332and as a symbol denoting the current location counter. 17333 17334 A backslash `\' is an ordinary character for the Z80 assembler. 17335 17336 The single quote `'' must be followed by a closing quote. If there 17337is one character in between, it is a character constant, otherwise it is 17338a string constant. 17339 17340 17341File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 17342 173439.38.2.2 Register Names 17344....................... 17345 17346The registers are referred to with the letters assigned to them by 17347Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and 17348most significant octet in `ix', and similarly `iyl' and `iyh' as parts 17349of `iy'. 17350 17351 17352File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax 17353 173549.38.2.3 Case Sensitivity 17355......................... 17356 17357Upper and lower case are equivalent in register names, opcodes, 17358condition codes and assembler directives. The case of letters is 17359significant in labels and symbol names. The case is also important to 17360distinguish the suffix `b' for a backward reference to a local label 17361from the suffix `B' for a number in binary notation. 17362 17363 17364File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 17365 173669.38.3 Floating Point 17367--------------------- 17368 17369Floating-point numbers are not supported. 17370 17371 17372File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 17373 173749.38.4 Z80 Assembler Directives 17375------------------------------- 17376 17377`as' for the Z80 supports some additional directives for compatibility 17378with other assemblers. 17379 17380 These are the additional directives in `as' for the Z80: 17381 17382`db EXPRESSION|STRING[,EXPRESSION|STRING...]' 17383`defb EXPRESSION|STRING[,EXPRESSION|STRING...]' 17384 For each STRING the characters are copied to the object file, for 17385 each other EXPRESSION the value is stored in one byte. A warning 17386 is issued in case of an overflow. 17387 17388`dw EXPRESSION[,EXPRESSION...]' 17389`defw EXPRESSION[,EXPRESSION...]' 17390 For each EXPRESSION the value is stored in two bytes, ignoring 17391 overflow. 17392 17393`d24 EXPRESSION[,EXPRESSION...]' 17394`def24 EXPRESSION[,EXPRESSION...]' 17395 For each EXPRESSION the value is stored in three bytes, ignoring 17396 overflow. 17397 17398`d32 EXPRESSION[,EXPRESSION...]' 17399`def32 EXPRESSION[,EXPRESSION...]' 17400 For each EXPRESSION the value is stored in four bytes, ignoring 17401 overflow. 17402 17403`ds COUNT[, VALUE]' 17404`defs COUNT[, VALUE]' 17405 Fill COUNT bytes in the object file with VALUE, if VALUE is 17406 omitted it defaults to zero. 17407 17408`SYMBOL equ EXPRESSION' 17409`SYMBOL defl EXPRESSION' 17410 These directives set the value of SYMBOL to EXPRESSION. If `equ' 17411 is used, it is an error if SYMBOL is already defined. Symbols 17412 defined with `equ' are not protected from redefinition. 17413 17414`set' 17415 This is a normal instruction on Z80, and not an assembler 17416 directive. 17417 17418`psect NAME' 17419 A synonym for *Note Section::, no second argument should be given. 17420 17421 17422 17423File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 17424 174259.38.5 Opcodes 17426-------------- 17427 17428In line with common practice, Z80 mnemonics are used for both the Z80 17429and the R800. 17430 17431 In many instructions it is possible to use one of the half index 17432registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general 17433purpose register. This yields instructions that are documented on the 17434R800 and undocumented on the Z80. Similarly `in f,(c)' is documented 17435on the R800 and undocumented on the Z80. 17436 17437 The assembler also supports the following undocumented 17438Z80-instructions, that have not been adopted in the R800 instruction 17439set: 17440`out (c),0' 17441 Sends zero to the port pointed to by register c. 17442 17443`sli M' 17444 Equivalent to `M = (M<<1)+1', the operand M can be any operand 17445 that is valid for `sla'. One can use `sll' as a synonym for `sli'. 17446 17447`OP (ix+D), R' 17448 This is equivalent to 17449 17450 ld R, (ix+D) 17451 OPC R 17452 ld (ix+D), R 17453 17454 The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc', 17455 `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R' 17456 may be any of `a', `b', `c', `d', `e', `h' and `l'. 17457 17458`OPC (iy+D), R' 17459 As above, but with `iy' instead of `ix'. 17460 17461 The web site at `http://www.z80.info' is a good starting place to 17462find more information on programming the Z80. 17463 17464 17465File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 17466 174679.39 Z8000 Dependent Features 17468============================= 17469 17470 The Z8000 as supports both members of the Z8000 family: the 17471unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 1747224 bit addresses. 17473 17474 When the assembler is in unsegmented mode (specified with the 17475`unsegm' directive), an address takes up one word (16 bit) sized 17476register. When the assembler is in segmented mode (specified with the 17477`segm' directive), a 24-bit address takes up a long (32 bit) register. 17478*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 17479of other Z8000 specific assembler directives. 17480 17481* Menu: 17482 17483* Z8000 Options:: Command-line options for the Z8000 17484* Z8000 Syntax:: Assembler syntax for the Z8000 17485* Z8000 Directives:: Special directives for the Z8000 17486* Z8000 Opcodes:: Opcodes 17487 17488 17489File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 17490 174919.39.1 Options 17492-------------- 17493 17494`-z8001' 17495 Generate segmented code by default. 17496 17497`-z8002' 17498 Generate unsegmented code by default. 17499 17500 17501File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 17502 175039.39.2 Syntax 17504------------- 17505 17506* Menu: 17507 17508* Z8000-Chars:: Special Characters 17509* Z8000-Regs:: Register Names 17510* Z8000-Addressing:: Addressing Modes 17511 17512 17513File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 17514 175159.39.2.1 Special Characters 17516........................... 17517 17518`!' is the line comment character. 17519 17520 You can use `;' instead of a newline to separate statements. 17521 17522 17523File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 17524 175259.39.2.2 Register Names 17526....................... 17527 17528The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 17529to different sized groups of registers by register number, with the 17530prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for 1753164 bit registers. You can also refer to the contents of the first 17532eight (of the sixteen 16 bit registers) by bytes. They are named `rlN' 17533and `rhN'. 17534 17535_byte registers_ 17536 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 17537 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 17538 17539_word registers_ 17540 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 17541 17542_long word registers_ 17543 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 17544 17545_quad word registers_ 17546 rq0 rq4 rq8 rq12 17547 17548 17549File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 17550 175519.39.2.3 Addressing Modes 17552......................... 17553 17554as understands the following addressing modes for the Z8000: 17555 17556`rlN' 17557`rhN' 17558`rN' 17559`rrN' 17560`rqN' 17561 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 17562 17563`@rN' 17564`@rrN' 17565 Indirect register: @rrN in segmented mode, @rN in unsegmented 17566 mode. 17567 17568`ADDR' 17569 Direct: the 16 bit or 24 bit address (depending on whether the 17570 assembler is in segmented or unsegmented mode) of the operand is 17571 in the instruction. 17572 17573`address(rN)' 17574 Indexed: the 16 or 24 bit address is added to the 16 bit register 17575 to produce the final address in memory of the operand. 17576 17577`rN(#IMM)' 17578`rrN(#IMM)' 17579 Base Address: the 16 or 24 bit register is added to the 16 bit sign 17580 extended immediate displacement to produce the final address in 17581 memory of the operand. 17582 17583`rN(rM)' 17584`rrN(rM)' 17585 Base Index: the 16 or 24 bit register rN or rrN is added to the 17586 sign extended 16 bit index register rM to produce the final 17587 address in memory of the operand. 17588 17589`#XX' 17590 Immediate data XX. 17591 17592 17593File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 17594 175959.39.3 Assembler Directives for the Z8000 17596----------------------------------------- 17597 17598The Z8000 port of as includes additional assembler directives, for 17599compatibility with other Z8000 assemblers. These do not begin with `.' 17600(unlike the ordinary as directives). 17601 17602`segm' 17603`.z8001' 17604 Generate code for the segmented Z8001. 17605 17606`unsegm' 17607`.z8002' 17608 Generate code for the unsegmented Z8002. 17609 17610`name' 17611 Synonym for `.file' 17612 17613`global' 17614 Synonym for `.global' 17615 17616`wval' 17617 Synonym for `.word' 17618 17619`lval' 17620 Synonym for `.long' 17621 17622`bval' 17623 Synonym for `.byte' 17624 17625`sval' 17626 Assemble a string. `sval' expects one string literal, delimited by 17627 single quotes. It assembles each byte of the string into 17628 consecutive addresses. You can use the escape sequence `%XX' 17629 (where XX represents a two-digit hexadecimal number) to represent 17630 the character whose ASCII value is XX. Use this feature to 17631 describe single quote and other characters that may not appear in 17632 string literals as themselves. For example, the C statement 17633 `char *a = "he said \"it's 50% off\"";' is represented in Z8000 17634 assembly language (shown with the assembler output in hex at the 17635 left) as 17636 17637 68652073 sval 'he said %22it%27s 50%25 off%22%00' 17638 61696420 17639 22697427 17640 73203530 17641 25206F66 17642 662200 17643 17644`rsect' 17645 synonym for `.section' 17646 17647`block' 17648 synonym for `.space' 17649 17650`even' 17651 special case of `.align'; aligns output to even byte boundary. 17652 17653 17654File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 17655 176569.39.4 Opcodes 17657-------------- 17658 17659For detailed information on the Z8000 machine instruction set, see 17660`Z8000 Technical Manual'. 17661 17662 The following table summarizes the opcodes and their arguments: 17663 17664 rs 16 bit source register 17665 rd 16 bit destination register 17666 rbs 8 bit source register 17667 rbd 8 bit destination register 17668 rrs 32 bit source register 17669 rrd 32 bit destination register 17670 rqs 64 bit source register 17671 rqd 64 bit destination register 17672 addr 16/24 bit address 17673 imm immediate data 17674 17675 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 17676 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 17677 add rd,@rs clrb rbd dab rbd 17678 add rd,addr com @rd dbjnz rbd,disp7 17679 add rd,addr(rs) com addr dec @rd,imm4m1 17680 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 17681 add rd,rs com rd dec addr,imm4m1 17682 addb rbd,@rs comb @rd dec rd,imm4m1 17683 addb rbd,addr comb addr decb @rd,imm4m1 17684 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 17685 addb rbd,imm8 comb rbd decb addr,imm4m1 17686 addb rbd,rbs comflg flags decb rbd,imm4m1 17687 addl rrd,@rs cp @rd,imm16 di i2 17688 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 17689 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 17690 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 17691 addl rrd,rrs cp rd,addr div rrd,imm16 17692 and rd,@rs cp rd,addr(rs) div rrd,rs 17693 and rd,addr cp rd,imm16 divl rqd,@rs 17694 and rd,addr(rs) cp rd,rs divl rqd,addr 17695 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 17696 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 17697 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 17698 andb rbd,addr cpb rbd,@rs djnz rd,disp7 17699 andb rbd,addr(rs) cpb rbd,addr ei i2 17700 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 17701 andb rbd,rbs cpb rbd,imm8 ex rd,addr 17702 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 17703 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 17704 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 17705 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 17706 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 17707 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 17708 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 17709 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 17710 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 17711 bitb rbd,rs cpl rrd,@rs ext8f imm8 17712 bpt cpl rrd,addr exts rrd 17713 call @rd cpl rrd,addr(rs) extsb rd 17714 call addr cpl rrd,imm32 extsl rqd 17715 call addr(rd) cpl rrd,rrs halt 17716 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 17717 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 17718 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 17719 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 17720 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 17721 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 17722 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 17723 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 17724 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 17725 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 17726 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 17727 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 17728 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 17729 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 17730 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 17731 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 17732 iret ldib @rd,@rs,rr neg addr(rd) 17733 jp cc,@rd ldir @rd,@rs,rr neg rd 17734 jp cc,addr ldirb @rd,@rs,rr negb @rd 17735 jp cc,addr(rd) ldk rd,imm4 negb addr 17736 jr cc,disp8 ldl @rd,rrs negb addr(rd) 17737 ld @rd,imm16 ldl addr(rd),rrs negb rbd 17738 ld @rd,rs ldl addr,rrs nop 17739 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 17740 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 17741 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 17742 ld addr,rs ldl rrd,addr or rd,imm16 17743 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 17744 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 17745 ld rd,@rs ldl rrd,rrs orb rbd,addr 17746 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 17747 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 17748 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 17749 ld rd,rs ldm addr(rd),rs,n out @rd,rs 17750 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 17751 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 17752 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 17753 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 17754 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 17755 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 17756 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 17757 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 17758 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 17759 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 17760 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 17761 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 17762 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 17763 ldb rbd,@rs mbit popl addr,@rs 17764 ldb rbd,addr mreq rd popl rrd,@rs 17765 ldb rbd,addr(rs) mres push @rd,@rs 17766 ldb rbd,imm8 mset push @rd,addr 17767 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 17768 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 17769 push @rd,rs set addr,imm4 subl rrd,imm32 17770 pushl @rd,@rs set rd,imm4 subl rrd,rrs 17771 pushl @rd,addr set rd,rs tcc cc,rd 17772 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 17773 pushl @rd,rrs setb addr(rd),imm4 test @rd 17774 res @rd,imm4 setb addr,imm4 test addr 17775 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 17776 res addr,imm4 setb rbd,rs test rd 17777 res rd,imm4 setflg imm4 testb @rd 17778 res rd,rs sinb rbd,imm16 testb addr 17779 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 17780 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 17781 resb addr,imm4 sindb @rd,@rs,rba testl @rd 17782 resb rbd,imm4 sinib @rd,@rs,ra testl addr 17783 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 17784 resflg imm4 sla rd,imm8 testl rrd 17785 ret cc slab rbd,imm8 trdb @rd,@rs,rba 17786 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 17787 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 17788 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 17789 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 17790 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 17791 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 17792 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 17793 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 17794 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 17795 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 17796 rsvd36 sra rd,imm8 tset rd 17797 rsvd38 srab rbd,imm8 tsetb @rd 17798 rsvd78 sral rrd,imm8 tsetb addr 17799 rsvd7e srl rd,imm8 tsetb addr(rd) 17800 rsvd9d srlb rbd,imm8 tsetb rbd 17801 rsvd9f srll rrd,imm8 xor rd,@rs 17802 rsvdb9 sub rd,@rs xor rd,addr 17803 rsvdbf sub rd,addr xor rd,addr(rs) 17804 sbc rd,rs sub rd,addr(rs) xor rd,imm16 17805 sbcb rbd,rbs sub rd,imm16 xor rd,rs 17806 sc imm8 sub rd,rs xorb rbd,@rs 17807 sda rd,rs subb rbd,@rs xorb rbd,addr 17808 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 17809 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 17810 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 17811 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 17812 sdll rrd,rs subl rrd,@rs 17813 set @rd,imm4 subl rrd,addr 17814 set addr(rd),imm4 subl rrd,addr(rs) 17815 17816 17817File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies 17818 178199.40 VAX Dependent Features 17820=========================== 17821 17822* Menu: 17823 17824* VAX-Opts:: VAX Command-Line Options 17825* VAX-float:: VAX Floating Point 17826* VAX-directives:: Vax Machine Directives 17827* VAX-opcodes:: VAX Opcodes 17828* VAX-branch:: VAX Branch Improvement 17829* VAX-operands:: VAX Operands 17830* VAX-no:: Not Supported on VAX 17831 17832 17833File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 17834 178359.40.1 VAX Command-Line Options 17836------------------------------- 17837 17838The Vax version of `as' accepts any of the following options, gives a 17839warning message that the option was ignored and proceeds. These 17840options are for compatibility with scripts designed for other people's 17841assemblers. 17842 17843``-D' (Debug)' 17844``-S' (Symbol Table)' 17845``-T' (Token Trace)' 17846 These are obsolete options used to debug old assemblers. 17847 17848``-d' (Displacement size for JUMPs)' 17849 This option expects a number following the `-d'. Like options 17850 that expect filenames, the number may immediately follow the `-d' 17851 (old standard) or constitute the whole of the command line 17852 argument that follows `-d' (GNU standard). 17853 17854``-V' (Virtualize Interpass Temporary File)' 17855 Some other assemblers use a temporary file. This option commanded 17856 them to keep the information in active memory rather than in a 17857 disk file. `as' always does this, so this option is redundant. 17858 17859``-J' (JUMPify Longer Branches)' 17860 Many 32-bit computers permit a variety of branch instructions to 17861 do the same job. Some of these instructions are short (and fast) 17862 but have a limited range; others are long (and slow) but can 17863 branch anywhere in virtual memory. Often there are 3 flavors of 17864 branch: short, medium and long. Some other assemblers would emit 17865 short and medium branches, unless told by this option to emit 17866 short and long branches. 17867 17868``-t' (Temporary File Directory)' 17869 Some other assemblers may use a temporary file, and this option 17870 takes a filename being the directory to site the temporary file. 17871 Since `as' does not use a temporary disk file, this option makes 17872 no difference. `-t' needs exactly one filename. 17873 17874 The Vax version of the assembler accepts additional options when 17875compiled for VMS: 17876 17877`-h N' 17878 External symbol or section (used for global variables) names are 17879 not case sensitive on VAX/VMS and always mapped to upper case. 17880 This is contrary to the C language definition which explicitly 17881 distinguishes upper and lower case. To implement a standard 17882 conforming C compiler, names must be changed (mapped) to preserve 17883 the case information. The default mapping is to convert all lower 17884 case characters to uppercase and adding an underscore followed by 17885 a 6 digit hex value, representing a 24 digit binary value. The 17886 one digits in the binary value represent which characters are 17887 uppercase in the original symbol name. 17888 17889 The `-h N' option determines how we map names. This takes several 17890 values. No `-h' switch at all allows case hacking as described 17891 above. A value of zero (`-h0') implies names should be upper 17892 case, and inhibits the case hack. A value of 2 (`-h2') implies 17893 names should be all lower case, with no case hack. A value of 3 17894 (`-h3') implies that case should be preserved. The value 1 is 17895 unused. The `-H' option directs `as' to display every mapped 17896 symbol during assembly. 17897 17898 Symbols whose names include a dollar sign `$' are exceptions to the 17899 general name mapping. These symbols are normally only used to 17900 reference VMS library names. Such symbols are always mapped to 17901 upper case. 17902 17903`-+' 17904 The `-+' option causes `as' to truncate any symbol name larger 17905 than 31 characters. The `-+' option also prevents some code 17906 following the `_main' symbol normally added to make the object 17907 file compatible with Vax-11 "C". 17908 17909`-1' 17910 This option is ignored for backward compatibility with `as' 17911 version 1.x. 17912 17913`-H' 17914 The `-H' option causes `as' to print every symbol which was 17915 changed by case mapping. 17916 17917 17918File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 17919 179209.40.2 VAX Floating Point 17921------------------------- 17922 17923Conversion of flonums to floating point is correct, and compatible with 17924previous assemblers. Rounding is towards zero if the remainder is 17925exactly half the least significant bit. 17926 17927 `D', `F', `G' and `H' floating point formats are understood. 17928 17929 Immediate floating literals (_e.g._ `S`$6.9') are rendered 17930correctly. Again, rounding is towards zero in the boundary case. 17931 17932 The `.float' directive produces `f' format numbers. The `.double' 17933directive produces `d' format numbers. 17934 17935 17936File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 17937 179389.40.3 Vax Machine Directives 17939----------------------------- 17940 17941The Vax version of the assembler supports four directives for 17942generating Vax floating point constants. They are described in the 17943table below. 17944 17945`.dfloat' 17946 This expects zero or more flonums, separated by commas, and 17947 assembles Vax `d' format 64-bit floating point constants. 17948 17949`.ffloat' 17950 This expects zero or more flonums, separated by commas, and 17951 assembles Vax `f' format 32-bit floating point constants. 17952 17953`.gfloat' 17954 This expects zero or more flonums, separated by commas, and 17955 assembles Vax `g' format 64-bit floating point constants. 17956 17957`.hfloat' 17958 This expects zero or more flonums, separated by commas, and 17959 assembles Vax `h' format 128-bit floating point constants. 17960 17961 17962 17963File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 17964 179659.40.4 VAX Opcodes 17966------------------ 17967 17968All DEC mnemonics are supported. Beware that `case...' instructions 17969have exactly 3 operands. The dispatch table that follows the `case...' 17970instruction should be made with `.word' statements. This is compatible 17971with all unix assemblers we know of. 17972 17973 17974File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 17975 179769.40.5 VAX Branch Improvement 17977----------------------------- 17978 17979Certain pseudo opcodes are permitted. They are for branch 17980instructions. They expand to the shortest branch instruction that 17981reaches the target. Generally these mnemonics are made by substituting 17982`j' for `b' at the start of a DEC mnemonic. This feature is included 17983both for compatibility and to help compilers. If you do not need this 17984feature, avoid these opcodes. Here are the mnemonics, and the code 17985they can expand into. 17986 17987`jbsb' 17988 `Jsb' is already an instruction mnemonic, so we chose `jbsb'. 17989 (byte displacement) 17990 `bsbb ...' 17991 17992 (word displacement) 17993 `bsbw ...' 17994 17995 (long displacement) 17996 `jsb ...' 17997 17998`jbr' 17999`jr' 18000 Unconditional branch. 18001 (byte displacement) 18002 `brb ...' 18003 18004 (word displacement) 18005 `brw ...' 18006 18007 (long displacement) 18008 `jmp ...' 18009 18010`jCOND' 18011 COND may be any one of the conditional branches `neq', `nequ', 18012 `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs', 18013 `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests 18014 `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs', 18015 `lbc'. NOTCOND is the opposite condition to COND. 18016 (byte displacement) 18017 `bCOND ...' 18018 18019 (word displacement) 18020 `bNOTCOND foo ; brw ... ; foo:' 18021 18022 (long displacement) 18023 `bNOTCOND foo ; jmp ... ; foo:' 18024 18025`jacbX' 18026 X may be one of `b d f g h l w'. 18027 (word displacement) 18028 `OPCODE ...' 18029 18030 (long displacement) 18031 OPCODE ..., foo ; 18032 brb bar ; 18033 foo: jmp ... ; 18034 bar: 18035 18036`jaobYYY' 18037 YYY may be one of `lss leq'. 18038 18039`jsobZZZ' 18040 ZZZ may be one of `geq gtr'. 18041 (byte displacement) 18042 `OPCODE ...' 18043 18044 (word displacement) 18045 OPCODE ..., foo ; 18046 brb bar ; 18047 foo: brw DESTINATION ; 18048 bar: 18049 18050 (long displacement) 18051 OPCODE ..., foo ; 18052 brb bar ; 18053 foo: jmp DESTINATION ; 18054 bar: 18055 18056`aobleq' 18057`aoblss' 18058`sobgeq' 18059`sobgtr' 18060 18061 (byte displacement) 18062 `OPCODE ...' 18063 18064 (word displacement) 18065 OPCODE ..., foo ; 18066 brb bar ; 18067 foo: brw DESTINATION ; 18068 bar: 18069 18070 (long displacement) 18071 OPCODE ..., foo ; 18072 brb bar ; 18073 foo: jmp DESTINATION ; 18074 bar: 18075 18076 18077File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 18078 180799.40.6 VAX Operands 18080------------------- 18081 18082The immediate character is `$' for Unix compatibility, not `#' as DEC 18083writes it. 18084 18085 The indirect character is `*' for Unix compatibility, not `@' as DEC 18086writes it. 18087 18088 The displacement sizing character is ``' (an accent grave) for Unix 18089compatibility, not `^' as DEC writes it. The letter preceding ``' may 18090have either case. `G' is not understood, but all other letters (`b i l 18091s w') are understood. 18092 18093 Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper 18094and lower case letters are equivalent. 18095 18096 For instance 18097 tstb *w`$4(r5) 18098 18099 Any expression is permitted in an operand. Operands are comma 18100separated. 18101 18102 18103File: as.info, Node: VAX-no, Prev: VAX-operands, Up: Vax-Dependent 18104 181059.40.7 Not Supported on VAX 18106--------------------------- 18107 18108Vax bit fields can not be assembled with `as'. Someone can add the 18109required code if they really need it. 18110 18111 18112File: as.info, Node: V850-Dependent, Next: Xtensa-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 18113 181149.41 v850 Dependent Features 18115============================ 18116 18117* Menu: 18118 18119* V850 Options:: Options 18120* V850 Syntax:: Syntax 18121* V850 Floating Point:: Floating Point 18122* V850 Directives:: V850 Machine Directives 18123* V850 Opcodes:: Opcodes 18124 18125 18126File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 18127 181289.41.1 Options 18129-------------- 18130 18131`as' supports the following additional command-line options for the 18132V850 processor family: 18133 18134`-wsigned_overflow' 18135 Causes warnings to be produced when signed immediate values 18136 overflow the space available for then within their opcodes. By 18137 default this option is disabled as it is possible to receive 18138 spurious warnings due to using exact bit patterns as immediate 18139 constants. 18140 18141`-wunsigned_overflow' 18142 Causes warnings to be produced when unsigned immediate values 18143 overflow the space available for then within their opcodes. By 18144 default this option is disabled as it is possible to receive 18145 spurious warnings due to using exact bit patterns as immediate 18146 constants. 18147 18148`-mv850' 18149 Specifies that the assembled code should be marked as being 18150 targeted at the V850 processor. This allows the linker to detect 18151 attempts to link such code with code assembled for other 18152 processors. 18153 18154`-mv850e' 18155 Specifies that the assembled code should be marked as being 18156 targeted at the V850E processor. This allows the linker to detect 18157 attempts to link such code with code assembled for other 18158 processors. 18159 18160`-mv850e1' 18161 Specifies that the assembled code should be marked as being 18162 targeted at the V850E1 processor. This allows the linker to 18163 detect attempts to link such code with code assembled for other 18164 processors. 18165 18166`-mv850any' 18167 Specifies that the assembled code should be marked as being 18168 targeted at the V850 processor but support instructions that are 18169 specific to the extended variants of the process. This allows the 18170 production of binaries that contain target specific code, but 18171 which are also intended to be used in a generic fashion. For 18172 example libgcc.a contains generic routines used by the code 18173 produced by GCC for all versions of the v850 architecture, 18174 together with support routines only used by the V850E architecture. 18175 18176`-mv850e2' 18177 Specifies that the assembled code should be marked as being 18178 targeted at the V850E2 processor. This allows the linker to 18179 detect attempts to link such code with code assembled for other 18180 processors. 18181 18182`-mv850e2v3' 18183 Specifies that the assembled code should be marked as being 18184 targeted at the V850E2V3 processor. This allows the linker to 18185 detect attempts to link such code with code assembled for other 18186 processors. 18187 18188`-mrelax' 18189 Enables relaxation. This allows the .longcall and .longjump pseudo 18190 ops to be used in the assembler source code. These ops label 18191 sections of code which are either a long function call or a long 18192 branch. The assembler will then flag these sections of code and 18193 the linker will attempt to relax them. 18194 18195 18196 18197File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 18198 181999.41.2 Syntax 18200------------- 18201 18202* Menu: 18203 18204* V850-Chars:: Special Characters 18205* V850-Regs:: Register Names 18206 18207 18208File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 18209 182109.41.2.1 Special Characters 18211........................... 18212 18213`#' is the line comment character. 18214 18215 18216File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 18217 182189.41.2.2 Register Names 18219....................... 18220 18221`as' supports the following names for registers: 18222`general register 0' 18223 r0, zero 18224 18225`general register 1' 18226 r1 18227 18228`general register 2' 18229 r2, hp 18230 18231`general register 3' 18232 r3, sp 18233 18234`general register 4' 18235 r4, gp 18236 18237`general register 5' 18238 r5, tp 18239 18240`general register 6' 18241 r6 18242 18243`general register 7' 18244 r7 18245 18246`general register 8' 18247 r8 18248 18249`general register 9' 18250 r9 18251 18252`general register 10' 18253 r10 18254 18255`general register 11' 18256 r11 18257 18258`general register 12' 18259 r12 18260 18261`general register 13' 18262 r13 18263 18264`general register 14' 18265 r14 18266 18267`general register 15' 18268 r15 18269 18270`general register 16' 18271 r16 18272 18273`general register 17' 18274 r17 18275 18276`general register 18' 18277 r18 18278 18279`general register 19' 18280 r19 18281 18282`general register 20' 18283 r20 18284 18285`general register 21' 18286 r21 18287 18288`general register 22' 18289 r22 18290 18291`general register 23' 18292 r23 18293 18294`general register 24' 18295 r24 18296 18297`general register 25' 18298 r25 18299 18300`general register 26' 18301 r26 18302 18303`general register 27' 18304 r27 18305 18306`general register 28' 18307 r28 18308 18309`general register 29' 18310 r29 18311 18312`general register 30' 18313 r30, ep 18314 18315`general register 31' 18316 r31, lp 18317 18318`system register 0' 18319 eipc 18320 18321`system register 1' 18322 eipsw 18323 18324`system register 2' 18325 fepc 18326 18327`system register 3' 18328 fepsw 18329 18330`system register 4' 18331 ecr 18332 18333`system register 5' 18334 psw 18335 18336`system register 16' 18337 ctpc 18338 18339`system register 17' 18340 ctpsw 18341 18342`system register 18' 18343 dbpc 18344 18345`system register 19' 18346 dbpsw 18347 18348`system register 20' 18349 ctbp 18350 18351 18352File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 18353 183549.41.3 Floating Point 18355--------------------- 18356 18357The V850 family uses IEEE floating-point numbers. 18358 18359 18360File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 18361 183629.41.4 V850 Machine Directives 18363------------------------------ 18364 18365`.offset <EXPRESSION>' 18366 Moves the offset into the current section to the specified amount. 18367 18368`.section "name", <type>' 18369 This is an extension to the standard .section directive. It sets 18370 the current section to be <type> and creates an alias for this 18371 section called "name". 18372 18373`.v850' 18374 Specifies that the assembled code should be marked as being 18375 targeted at the V850 processor. This allows the linker to detect 18376 attempts to link such code with code assembled for other 18377 processors. 18378 18379`.v850e' 18380 Specifies that the assembled code should be marked as being 18381 targeted at the V850E processor. This allows the linker to detect 18382 attempts to link such code with code assembled for other 18383 processors. 18384 18385`.v850e1' 18386 Specifies that the assembled code should be marked as being 18387 targeted at the V850E1 processor. This allows the linker to 18388 detect attempts to link such code with code assembled for other 18389 processors. 18390 18391`.v850e2' 18392 Specifies that the assembled code should be marked as being 18393 targeted at the V850E2 processor. This allows the linker to 18394 detect attempts to link such code with code assembled for other 18395 processors. 18396 18397`.v850e2v3' 18398 Specifies that the assembled code should be marked as being 18399 targeted at the V850E2V3 processor. This allows the linker to 18400 detect attempts to link such code with code assembled for other 18401 processors. 18402 18403 18404 18405File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 18406 184079.41.5 Opcodes 18408-------------- 18409 18410`as' implements all the standard V850 opcodes. 18411 18412 `as' also implements the following pseudo ops: 18413 18414`hi0()' 18415 Computes the higher 16 bits of the given expression and stores it 18416 into the immediate operand field of the given instruction. For 18417 example: 18418 18419 `mulhi hi0(here - there), r5, r6' 18420 18421 computes the difference between the address of labels 'here' and 18422 'there', takes the upper 16 bits of this difference, shifts it 18423 down 16 bits and then multiplies it by the lower 16 bits in 18424 register 5, putting the result into register 6. 18425 18426`lo()' 18427 Computes the lower 16 bits of the given expression and stores it 18428 into the immediate operand field of the given instruction. For 18429 example: 18430 18431 `addi lo(here - there), r5, r6' 18432 18433 computes the difference between the address of labels 'here' and 18434 'there', takes the lower 16 bits of this difference and adds it to 18435 register 5, putting the result into register 6. 18436 18437`hi()' 18438 Computes the higher 16 bits of the given expression and then adds 18439 the value of the most significant bit of the lower 16 bits of the 18440 expression and stores the result into the immediate operand field 18441 of the given instruction. For example the following code can be 18442 used to compute the address of the label 'here' and store it into 18443 register 6: 18444 18445 `movhi hi(here), r0, r6' `movea lo(here), r6, r6' 18446 18447 The reason for this special behaviour is that movea performs a sign 18448 extension on its immediate operand. So for example if the address 18449 of 'here' was 0xFFFFFFFF then without the special behaviour of the 18450 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 18451 then the movea instruction would takes its immediate operand, 18452 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it 18453 into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). 18454 With the hi() pseudo op adding in the top bit of the lo() pseudo 18455 op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 18456 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - 18457 the right value. 18458 18459`hilo()' 18460 Computes the 32 bit value of the given expression and stores it 18461 into the immediate operand field of the given instruction (which 18462 must be a mov instruction). For example: 18463 18464 `mov hilo(here), r6' 18465 18466 computes the absolute address of label 'here' and puts the result 18467 into register 6. 18468 18469`sdaoff()' 18470 Computes the offset of the named variable from the start of the 18471 Small Data Area (whoes address is held in register 4, the GP 18472 register) and stores the result as a 16 bit signed value in the 18473 immediate operand field of the given instruction. For example: 18474 18475 `ld.w sdaoff(_a_variable)[gp],r6' 18476 18477 loads the contents of the location pointed to by the label 18478 '_a_variable' into register 6, provided that the label is located 18479 somewhere within +/- 32K of the address held in the GP register. 18480 [Note the linker assumes that the GP register contains a fixed 18481 address set to the address of the label called '__gp'. This can 18482 either be set up automatically by the linker, or specifically set 18483 by using the `--defsym __gp=<value>' command line option]. 18484 18485`tdaoff()' 18486 Computes the offset of the named variable from the start of the 18487 Tiny Data Area (whoes address is held in register 30, the EP 18488 register) and stores the result as a 4,5, 7 or 8 bit unsigned 18489 value in the immediate operand field of the given instruction. 18490 For example: 18491 18492 `sld.w tdaoff(_a_variable)[ep],r6' 18493 18494 loads the contents of the location pointed to by the label 18495 '_a_variable' into register 6, provided that the label is located 18496 somewhere within +256 bytes of the address held in the EP 18497 register. [Note the linker assumes that the EP register contains 18498 a fixed address set to the address of the label called '__ep'. 18499 This can either be set up automatically by the linker, or 18500 specifically set by using the `--defsym __ep=<value>' command line 18501 option]. 18502 18503`zdaoff()' 18504 Computes the offset of the named variable from address 0 and 18505 stores the result as a 16 bit signed value in the immediate 18506 operand field of the given instruction. For example: 18507 18508 `movea zdaoff(_a_variable),zero,r6' 18509 18510 puts the address of the label '_a_variable' into register 6, 18511 assuming that the label is somewhere within the first 32K of 18512 memory. (Strictly speaking it also possible to access the last 18513 32K of memory as well, as the offsets are signed). 18514 18515`ctoff()' 18516 Computes the offset of the named variable from the start of the 18517 Call Table Area (whoes address is helg in system register 20, the 18518 CTBP register) and stores the result a 6 or 16 bit unsigned value 18519 in the immediate field of then given instruction or piece of data. 18520 For example: 18521 18522 `callt ctoff(table_func1)' 18523 18524 will put the call the function whoes address is held in the call 18525 table at the location labeled 'table_func1'. 18526 18527`.longcall `name'' 18528 Indicates that the following sequence of instructions is a long 18529 call to function `name'. The linker will attempt to shorten this 18530 call sequence if `name' is within a 22bit offset of the call. Only 18531 valid if the `-mrelax' command line switch has been enabled. 18532 18533`.longjump `name'' 18534 Indicates that the following sequence of instructions is a long 18535 jump to label `name'. The linker will attempt to shorten this code 18536 sequence if `name' is within a 22bit offset of the jump. Only 18537 valid if the `-mrelax' command line switch has been enabled. 18538 18539 18540 For information on the V850 instruction set, see `V850 Family 1854132-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 18542Ltd. 18543 18544 18545File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 18546 185479.42 Xtensa Dependent Features 18548============================== 18549 18550 This chapter covers features of the GNU assembler that are specific 18551to the Xtensa architecture. For details about the Xtensa instruction 18552set, please consult the `Xtensa Instruction Set Architecture (ISA) 18553Reference Manual'. 18554 18555* Menu: 18556 18557* Xtensa Options:: Command-line Options. 18558* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 18559* Xtensa Optimizations:: Assembler Optimizations. 18560* Xtensa Relaxation:: Other Automatic Transformations. 18561* Xtensa Directives:: Directives for Xtensa Processors. 18562 18563 18564File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 18565 185669.42.1 Command Line Options 18567--------------------------- 18568 18569The Xtensa version of the GNU assembler supports these special options: 18570 18571`--text-section-literals | --no-text-section-literals' 18572 Control the treatment of literal pools. The default is 18573 `--no-text-section-literals', which places literals in separate 18574 sections in the output file. This allows the literal pool to be 18575 placed in a data RAM/ROM. With `--text-section-literals', the 18576 literals are interspersed in the text section in order to keep 18577 them as close as possible to their references. This may be 18578 necessary for large assembly files, where the literals would 18579 otherwise be out of range of the `L32R' instructions in the text 18580 section. These options only affect literals referenced via 18581 PC-relative `L32R' instructions; literals for absolute mode `L32R' 18582 instructions are handled separately. *Note literal: Literal 18583 Directive. 18584 18585`--absolute-literals | --no-absolute-literals' 18586 Indicate to the assembler whether `L32R' instructions use absolute 18587 or PC-relative addressing. If the processor includes the absolute 18588 addressing option, the default is to use absolute `L32R' 18589 relocations. Otherwise, only the PC-relative `L32R' relocations 18590 can be used. 18591 18592`--target-align | --no-target-align' 18593 Enable or disable automatic alignment to reduce branch penalties 18594 at some expense in code size. *Note Automatic Instruction 18595 Alignment: Xtensa Automatic Alignment. This optimization is 18596 enabled by default. Note that the assembler will always align 18597 instructions like `LOOP' that have fixed alignment requirements. 18598 18599`--longcalls | --no-longcalls' 18600 Enable or disable transformation of call instructions to allow 18601 calls across a greater range of addresses. *Note Function Call 18602 Relaxation: Xtensa Call Relaxation. This option should be used 18603 when call targets can potentially be out of range. It may degrade 18604 both code size and performance, but the linker can generally 18605 optimize away the unnecessary overhead when a call ends up within 18606 range. The default is `--no-longcalls'. 18607 18608`--transform | --no-transform' 18609 Enable or disable all assembler transformations of Xtensa 18610 instructions, including both relaxation and optimization. The 18611 default is `--transform'; `--no-transform' should only be used in 18612 the rare cases when the instructions must be exactly as specified 18613 in the assembly source. Using `--no-transform' causes out of range 18614 instruction operands to be errors. 18615 18616`--rename-section OLDNAME=NEWNAME' 18617 Rename the OLDNAME section to NEWNAME. This option can be used 18618 multiple times to rename multiple sections. 18619 18620 18621File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 18622 186239.42.2 Assembler Syntax 18624----------------------- 18625 18626Block comments are delimited by `/*' and `*/'. End of line comments 18627may be introduced with either `#' or `//'. 18628 18629 Instructions consist of a leading opcode or macro name followed by 18630whitespace and an optional comma-separated list of operands: 18631 18632 OPCODE [OPERAND, ...] 18633 18634 Instructions must be separated by a newline or semicolon. 18635 18636 FLIX instructions, which bundle multiple opcodes together in a single 18637instruction, are specified by enclosing the bundled opcodes inside 18638braces: 18639 18640 { 18641 [FORMAT] 18642 OPCODE0 [OPERANDS] 18643 OPCODE1 [OPERANDS] 18644 OPCODE2 [OPERANDS] 18645 ... 18646 } 18647 18648 The opcodes in a FLIX instruction are listed in the same order as the 18649corresponding instruction slots in the TIE format declaration. 18650Directives and labels are not allowed inside the braces of a FLIX 18651instruction. A particular TIE format name can optionally be specified 18652immediately after the opening brace, but this is usually unnecessary. 18653The assembler will automatically search for a format that can encode the 18654specified opcodes, so the format name need only be specified in rare 18655cases where there is more than one applicable format and where it 18656matters which of those formats is used. A FLIX instruction can also be 18657specified on a single line by separating the opcodes with semicolons: 18658 18659 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 18660 18661 If an opcode can only be encoded in a FLIX instruction but is not 18662specified as part of a FLIX bundle, the assembler will choose the 18663smallest format where the opcode can be encoded and will fill unused 18664instruction slots with no-ops. 18665 18666* Menu: 18667 18668* Xtensa Opcodes:: Opcode Naming Conventions. 18669* Xtensa Registers:: Register Naming. 18670 18671 18672File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 18673 186749.42.2.1 Opcode Names 18675..................... 18676 18677See the `Xtensa Instruction Set Architecture (ISA) Reference Manual' 18678for a complete list of opcodes and descriptions of their semantics. 18679 18680 If an opcode name is prefixed with an underscore character (`_'), 18681`as' will not transform that instruction in any way. The underscore 18682prefix disables both optimization (*note Xtensa Optimizations: Xtensa 18683Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 18684Relaxation.) for that particular instruction. Only use the underscore 18685prefix when it is essential to select the exact opcode produced by the 18686assembler. Using this feature unnecessarily makes the code less 18687efficient by disabling assembler optimization and less flexible by 18688disabling relaxation. 18689 18690 Note that this special handling of underscore prefixes only applies 18691to Xtensa opcodes, not to either built-in macros or user-defined macros. 18692When an underscore prefix is used with a macro (e.g., `_MOV'), it 18693refers to a different macro. The assembler generally provides built-in 18694macros both with and without the underscore prefix, where the underscore 18695versions behave as if the underscore carries through to the instructions 18696in the macros. For example, `_MOV' may expand to `_MOV.N'. 18697 18698 The underscore prefix only applies to individual instructions, not to 18699series of instructions. For example, if a series of instructions have 18700underscore prefixes, the assembler will not transform the individual 18701instructions, but it may insert other instructions between them (e.g., 18702to align a `LOOP' instruction). To prevent the assembler from 18703modifying a series of instructions as a whole, use the `no-transform' 18704directive. *Note transform: Transform Directive. 18705 18706 18707File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 18708 187099.42.2.2 Register Names 18710....................... 18711 18712The assembly syntax for a register file entry is the "short" name for a 18713TIE register file followed by the index into that register file. For 18714example, the general-purpose `AR' register file has a short name of 18715`a', so these registers are named `a0'...`a15'. As a special feature, 18716`sp' is also supported as a synonym for `a1'. Additional registers may 18717be added by processor configuration options and by designer-defined TIE 18718extensions. An initial `$' character is optional in all register names. 18719 18720 18721File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 18722 187239.42.3 Xtensa Optimizations 18724--------------------------- 18725 18726The optimizations currently supported by `as' are generation of density 18727instructions where appropriate and automatic branch target alignment. 18728 18729* Menu: 18730 18731* Density Instructions:: Using Density Instructions. 18732* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 18733 18734 18735File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 18736 187379.42.3.1 Using Density Instructions 18738................................... 18739 18740The Xtensa instruction set has a code density option that provides 1874116-bit versions of some of the most commonly used opcodes. Use of these 18742opcodes can significantly reduce code size. When possible, the 18743assembler automatically translates instructions from the core Xtensa 18744instruction set into equivalent instructions from the Xtensa code 18745density option. This translation can be disabled by using underscore 18746prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 18747`--no-transform' command-line option (*note Command Line Options: 18748Xtensa Options.), or by using the `no-transform' directive (*note 18749transform: Transform Directive.). 18750 18751 It is a good idea _not_ to use the density instructions directly. 18752The assembler will automatically select dense instructions where 18753possible. If you later need to use an Xtensa processor without the code 18754density option, the same assembly code will then work without 18755modification. 18756 18757 18758File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 18759 187609.42.3.2 Automatic Instruction Alignment 18761........................................ 18762 18763The Xtensa assembler will automatically align certain instructions, both 18764to optimize performance and to satisfy architectural requirements. 18765 18766 As an optimization to improve performance, the assembler attempts to 18767align branch targets so they do not cross instruction fetch boundaries. 18768(Xtensa processors can be configured with either 32-bit or 64-bit 18769instruction fetch widths.) An instruction immediately following a call 18770is treated as a branch target in this context, because it will be the 18771target of a return from the call. This alignment has the potential to 18772reduce branch penalties at some expense in code size. This 18773optimization is enabled by default. You can disable it with the 18774`--no-target-align' command-line option (*note Command Line Options: 18775Xtensa Options.). 18776 18777 The target alignment optimization is done without adding instructions 18778that could increase the execution time of the program. If there are 18779density instructions in the code preceding a target, the assembler can 18780change the target alignment by widening some of those instructions to 18781the equivalent 24-bit instructions. Extra bytes of padding can be 18782inserted immediately following unconditional jump and return 18783instructions. This approach is usually successful in aligning many, 18784but not all, branch targets. 18785 18786 The `LOOP' family of instructions must be aligned such that the 18787first instruction in the loop body does not cross an instruction fetch 18788boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be 18789on either a 1 or 2 mod 4 byte boundary). The assembler knows about 18790this restriction and inserts the minimal number of 2 or 3 byte no-op 18791instructions to satisfy it. When no-op instructions are added, any 18792label immediately preceding the original loop will be moved in order to 18793refer to the loop instruction, not the newly generated no-op 18794instruction. To preserve binary compatibility across processors with 18795different fetch widths, the assembler conservatively assumes a 32-bit 18796fetch width when aligning `LOOP' instructions (except if the first 18797instruction in the loop is a 64-bit instruction). 18798 18799 Previous versions of the assembler automatically aligned `ENTRY' 18800instructions to 4-byte boundaries, but that alignment is now the 18801programmer's responsibility. 18802 18803 18804File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 18805 188069.42.4 Xtensa Relaxation 18807------------------------ 18808 18809When an instruction operand is outside the range allowed for that 18810particular instruction field, `as' can transform the code to use a 18811functionally-equivalent instruction or sequence of instructions. This 18812process is known as "relaxation". This is typically done for branch 18813instructions because the distance of the branch targets is not known 18814until assembly-time. The Xtensa assembler offers branch relaxation and 18815also extends this concept to function calls, `MOVI' instructions and 18816other instructions with immediate fields. 18817 18818* Menu: 18819 18820* Xtensa Branch Relaxation:: Relaxation of Branches. 18821* Xtensa Call Relaxation:: Relaxation of Function Calls. 18822* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 18823 18824 18825File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 18826 188279.42.4.1 Conditional Branch Relaxation 18828...................................... 18829 18830When the target of a branch is too far away from the branch itself, 18831i.e., when the offset from the branch to the target is too large to fit 18832in the immediate field of the branch instruction, it may be necessary to 18833replace the branch with a branch around a jump. For example, 18834 18835 beqz a2, L 18836 18837 may result in: 18838 18839 bnez.n a2, M 18840 j L 18841 M: 18842 18843 (The `BNEZ.N' instruction would be used in this example only if the 18844density option is available. Otherwise, `BNEZ' would be used.) 18845 18846 This relaxation works well because the unconditional jump instruction 18847has a much larger offset range than the various conditional branches. 18848However, an error will occur if a branch target is beyond the range of a 18849jump instruction. `as' cannot relax unconditional jumps. Similarly, 18850an error will occur if the original input contains an unconditional 18851jump to a target that is out of range. 18852 18853 Branch relaxation is enabled by default. It can be disabled by using 18854underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 18855`--no-transform' command-line option (*note Command Line Options: 18856Xtensa Options.), or the `no-transform' directive (*note transform: 18857Transform Directive.). 18858 18859 18860File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 18861 188629.42.4.2 Function Call Relaxation 18863................................. 18864 18865Function calls may require relaxation because the Xtensa immediate call 18866instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a 18867PC-relative offset of only 512 Kbytes in either direction. For larger 18868programs, it may be necessary to use indirect calls (`CALLX0', 18869`CALLX4', `CALLX8' and `CALLX12') where the target address is specified 18870in a register. The Xtensa assembler can automatically relax immediate 18871call instructions into indirect call instructions. This relaxation is 18872done by loading the address of the called function into the callee's 18873return address register and then using a `CALLX' instruction. So, for 18874example: 18875 18876 call8 func 18877 18878 might be relaxed to: 18879 18880 .literal .L1, func 18881 l32r a8, .L1 18882 callx8 a8 18883 18884 Because the addresses of targets of function calls are not generally 18885known until link-time, the assembler must assume the worst and relax all 18886the calls to functions in other source files, not just those that really 18887will be out of range. The linker can recognize calls that were 18888unnecessarily relaxed, and it will remove the overhead introduced by the 18889assembler for those cases where direct calls are sufficient. 18890 18891 Call relaxation is disabled by default because it can have a negative 18892effect on both code size and performance, although the linker can 18893usually eliminate the unnecessary overhead. If a program is too large 18894and some of the calls are out of range, function call relaxation can be 18895enabled using the `--longcalls' command-line option or the `longcalls' 18896directive (*note longcalls: Longcalls Directive.). 18897 18898 18899File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 18900 189019.42.4.3 Other Immediate Field Relaxation 18902......................................... 18903 18904The assembler normally performs the following other relaxations. They 18905can be disabled by using underscore prefixes (*note Opcode Names: 18906Xtensa Opcodes.), the `--no-transform' command-line option (*note 18907Command Line Options: Xtensa Options.), or the `no-transform' directive 18908(*note transform: Transform Directive.). 18909 18910 The `MOVI' machine instruction can only materialize values in the 18911range from -2048 to 2047. Values outside this range are best 18912materialized with `L32R' instructions. Thus: 18913 18914 movi a0, 100000 18915 18916 is assembled into the following machine code: 18917 18918 .literal .L1, 100000 18919 l32r a0, .L1 18920 18921 The `L8UI' machine instruction can only be used with immediate 18922offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine 18923instructions can only be used with offsets from 0 to 510. The `L32I' 18924machine instruction can only be used with offsets from 0 to 1020. A 18925load offset outside these ranges can be materialized with an `L32R' 18926instruction if the destination register of the load is different than 18927the source address register. For example: 18928 18929 l32i a1, a0, 2040 18930 18931 is translated to: 18932 18933 .literal .L1, 2040 18934 l32r a1, .L1 18935 add a1, a0, a1 18936 l32i a1, a1, 0 18937 18938If the load destination and source address register are the same, an 18939out-of-range offset causes an error. 18940 18941 The Xtensa `ADDI' instruction only allows immediate operands in the 18942range from -128 to 127. There are a number of alternate instruction 18943sequences for the `ADDI' operation. First, if the immediate is 0, the 18944`ADDI' will be turned into a `MOV.N' instruction (or the equivalent 18945`OR' instruction if the code density option is not available). If the 18946`ADDI' immediate is outside of the range -128 to 127, but inside the 18947range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI' 18948sequence will be used. Finally, if the immediate is outside of this 18949range and a free register is available, an `L32R'/`ADD' sequence will 18950be used with a literal allocated from the literal pool. 18951 18952 For example: 18953 18954 addi a5, a6, 0 18955 addi a5, a6, 512 18956 addi a5, a6, 513 18957 addi a5, a6, 50000 18958 18959 is assembled into the following: 18960 18961 .literal .L1, 50000 18962 mov.n a5, a6 18963 addmi a5, a6, 0x200 18964 addmi a5, a6, 0x200 18965 addi a5, a5, 1 18966 l32r a5, .L1 18967 add a5, a6, a5 18968 18969 18970File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 18971 189729.42.5 Directives 18973----------------- 18974 18975The Xtensa assembler supports a region-based directive syntax: 18976 18977 .begin DIRECTIVE [OPTIONS] 18978 ... 18979 .end DIRECTIVE 18980 18981 All the Xtensa-specific directives that apply to a region of code use 18982this syntax. 18983 18984 The directive applies to code between the `.begin' and the `.end'. 18985The state of the option after the `.end' reverts to what it was before 18986the `.begin'. A nested `.begin'/`.end' region can further change the 18987state of the directive without having to be aware of its outer state. 18988For example, consider: 18989 18990 .begin no-transform 18991 L: add a0, a1, a2 18992 .begin transform 18993 M: add a0, a1, a2 18994 .end transform 18995 N: add a0, a1, a2 18996 .end no-transform 18997 18998 The `ADD' opcodes at `L' and `N' in the outer `no-transform' region 18999both result in `ADD' machine instructions, but the assembler selects an 19000`ADD.N' instruction for the `ADD' at `M' in the inner `transform' 19001region. 19002 19003 The advantage of this style is that it works well inside macros 19004which can preserve the context of their callers. 19005 19006 The following directives are available: 19007 19008* Menu: 19009 19010* Schedule Directive:: Enable instruction scheduling. 19011* Longcalls Directive:: Use Indirect Calls for Greater Range. 19012* Transform Directive:: Disable All Assembler Transformations. 19013* Literal Directive:: Intermix Literals with Instructions. 19014* Literal Position Directive:: Specify Inline Literal Pool Locations. 19015* Literal Prefix Directive:: Specify Literal Section Name Prefix. 19016* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 19017 19018 19019File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 19020 190219.42.5.1 schedule 19022................. 19023 19024The `schedule' directive is recognized only for compatibility with 19025Tensilica's assembler. 19026 19027 .begin [no-]schedule 19028 .end [no-]schedule 19029 19030 This directive is ignored and has no effect on `as'. 19031 19032 19033File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 19034 190359.42.5.2 longcalls 19036.................. 19037 19038The `longcalls' directive enables or disables function call relaxation. 19039*Note Function Call Relaxation: Xtensa Call Relaxation. 19040 19041 .begin [no-]longcalls 19042 .end [no-]longcalls 19043 19044 Call relaxation is disabled by default unless the `--longcalls' 19045command-line option is specified. The `longcalls' directive overrides 19046the default determined by the command-line options. 19047 19048 19049File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 19050 190519.42.5.3 transform 19052.................. 19053 19054This directive enables or disables all assembler transformation, 19055including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 19056optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 19057 19058 .begin [no-]transform 19059 .end [no-]transform 19060 19061 Transformations are enabled by default unless the `--no-transform' 19062option is used. The `transform' directive overrides the default 19063determined by the command-line options. An underscore opcode prefix, 19064disabling transformation of that opcode, always takes precedence over 19065both directives and command-line flags. 19066 19067 19068File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 19069 190709.42.5.4 literal 19071................ 19072 19073The `.literal' directive is used to define literal pool data, i.e., 19074read-only 32-bit data accessed via `L32R' instructions. 19075 19076 .literal LABEL, VALUE[, VALUE...] 19077 19078 This directive is similar to the standard `.word' directive, except 19079that the actual location of the literal data is determined by the 19080assembler and linker, not by the position of the `.literal' directive. 19081Using this directive gives the assembler freedom to locate the literal 19082data in the most appropriate place and possibly to combine identical 19083literals. For example, the code: 19084 19085 entry sp, 40 19086 .literal .L1, sym 19087 l32r a4, .L1 19088 19089 can be used to load a pointer to the symbol `sym' into register 19090`a4'. The value of `sym' will not be placed between the `ENTRY' and 19091`L32R' instructions; instead, the assembler puts the data in a literal 19092pool. 19093 19094 Literal pools are placed by default in separate literal sections; 19095however, when using the `--text-section-literals' option (*note Command 19096Line Options: Xtensa Options.), the literal pools for PC-relative mode 19097`L32R' instructions are placed in the current section.(1) These text 19098section literal pools are created automatically before `ENTRY' 19099instructions and manually after `.literal_position' directives (*note 19100literal_position: Literal Position Directive.). If there are no 19101preceding `ENTRY' instructions, explicit `.literal_position' directives 19102must be used to place the text section literal pools; otherwise, `as' 19103will report an error. 19104 19105 When literals are placed in separate sections, the literal section 19106names are derived from the names of the sections where the literals are 19107defined. The base literal section names are `.literal' for PC-relative 19108mode `L32R' instructions and `.lit4' for absolute mode `L32R' 19109instructions (*note absolute-literals: Absolute Literals Directive.). 19110These base names are used for literals defined in the default `.text' 19111section. For literals defined in other sections or within the scope of 19112a `literal_prefix' directive (*note literal_prefix: Literal Prefix 19113Directive.), the following rules determine the literal section name: 19114 19115 1. If the current section is a member of a section group, the literal 19116 section name includes the group name as a suffix to the base 19117 `.literal' or `.lit4' name, with a period to separate the base 19118 name and group name. The literal section is also made a member of 19119 the group. 19120 19121 2. If the current section name (or `literal_prefix' value) begins with 19122 "`.gnu.linkonce.KIND.'", the literal section name is formed by 19123 replacing "`.KIND'" with the base `.literal' or `.lit4' name. For 19124 example, for literals defined in a section named 19125 `.gnu.linkonce.t.func', the literal section will be 19126 `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'. 19127 19128 3. If the current section name (or `literal_prefix' value) ends with 19129 `.text', the literal section name is formed by replacing that 19130 suffix with the base `.literal' or `.lit4' name. For example, for 19131 literals defined in a section named `.iram0.text', the literal 19132 section will be `.iram0.literal' or `.iram0.lit4'. 19133 19134 4. If none of the preceding conditions apply, the literal section 19135 name is formed by adding the base `.literal' or `.lit4' name as a 19136 suffix to the current section name (or `literal_prefix' value). 19137 19138 ---------- Footnotes ---------- 19139 19140 (1) Literals for the `.init' and `.fini' sections are always placed 19141in separate sections, even when `--text-section-literals' is enabled. 19142 19143 19144File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 19145 191469.42.5.5 literal_position 19147......................... 19148 19149When using `--text-section-literals' to place literals inline in the 19150section being assembled, the `.literal_position' directive can be used 19151to mark a potential location for a literal pool. 19152 19153 .literal_position 19154 19155 The `.literal_position' directive is ignored when the 19156`--text-section-literals' option is not used or when `L32R' 19157instructions use the absolute addressing mode. 19158 19159 The assembler will automatically place text section literal pools 19160before `ENTRY' instructions, so the `.literal_position' directive is 19161only needed to specify some other location for a literal pool. You may 19162need to add an explicit jump instruction to skip over an inline literal 19163pool. 19164 19165 For example, an interrupt vector does not begin with an `ENTRY' 19166instruction so the assembler will be unable to automatically find a good 19167place to put a literal pool. Moreover, the code for the interrupt 19168vector must be at a specific starting address, so the literal pool 19169cannot come before the start of the code. The literal pool for the 19170vector must be explicitly positioned in the middle of the vector (before 19171any uses of the literals, due to the negative offsets used by 19172PC-relative `L32R' instructions). The `.literal_position' directive 19173can be used to do this. In the following code, the literal for `M' 19174will automatically be aligned correctly and is placed after the 19175unconditional jump. 19176 19177 .global M 19178 code_start: 19179 j continue 19180 .literal_position 19181 .align 4 19182 continue: 19183 movi a4, M 19184 19185 19186File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 19187 191889.42.5.6 literal_prefix 19189....................... 19190 19191The `literal_prefix' directive allows you to override the default 19192literal section names, which are derived from the names of the sections 19193where the literals are defined. 19194 19195 .begin literal_prefix [NAME] 19196 .end literal_prefix 19197 19198 For literals defined within the delimited region, the literal section 19199names are derived from the NAME argument instead of the name of the 19200current section. The rules used to derive the literal section names do 19201not change. *Note literal: Literal Directive. If the NAME argument is 19202omitted, the literal sections revert to the defaults. This directive 19203has no effect when using the `--text-section-literals' option (*note 19204Command Line Options: Xtensa Options.). 19205 19206 19207File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 19208 192099.42.5.7 absolute-literals 19210.......................... 19211 19212The `absolute-literals' and `no-absolute-literals' directives control 19213the absolute vs. PC-relative mode for `L32R' instructions. These are 19214relevant only for Xtensa configurations that include the absolute 19215addressing option for `L32R' instructions. 19216 19217 .begin [no-]absolute-literals 19218 .end [no-]absolute-literals 19219 19220 These directives do not change the `L32R' mode--they only cause the 19221assembler to emit the appropriate kind of relocation for `L32R' 19222instructions and to place the literal values in the appropriate section. 19223To change the `L32R' mode, the program must write the `LITBASE' special 19224register. It is the programmer's responsibility to keep track of the 19225mode and indicate to the assembler which mode is used in each region of 19226code. 19227 19228 If the Xtensa configuration includes the absolute `L32R' addressing 19229option, the default is to assume absolute `L32R' addressing unless the 19230`--no-absolute-literals' command-line option is specified. Otherwise, 19231the default is to assume PC-relative `L32R' addressing. The 19232`absolute-literals' directive can then be used to override the default 19233determined by the command-line options. 19234 19235 19236File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 19237 1923810 Reporting Bugs 19239***************** 19240 19241Your bug reports play an essential role in making `as' reliable. 19242 19243 Reporting a bug may help you by bringing a solution to your problem, 19244or it may not. But in any case the principal function of a bug report 19245is to help the entire community by making the next version of `as' work 19246better. Bug reports are your contribution to the maintenance of `as'. 19247 19248 In order for a bug report to serve its purpose, you must include the 19249information that enables us to fix the bug. 19250 19251* Menu: 19252 19253* Bug Criteria:: Have you found a bug? 19254* Bug Reporting:: How to report bugs 19255 19256 19257File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 19258 1925910.1 Have You Found a Bug? 19260========================== 19261 19262If you are not sure whether you have found a bug, here are some 19263guidelines: 19264 19265 * If the assembler gets a fatal signal, for any input whatever, that 19266 is a `as' bug. Reliable assemblers never crash. 19267 19268 * If `as' produces an error message for valid input, that is a bug. 19269 19270 * If `as' does not produce an error message for invalid input, that 19271 is a bug. However, you should note that your idea of "invalid 19272 input" might be our idea of "an extension" or "support for 19273 traditional practice". 19274 19275 * If you are an experienced user of assemblers, your suggestions for 19276 improvement of `as' are welcome in any case. 19277 19278 19279File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 19280 1928110.2 How to Report Bugs 19282======================= 19283 19284A number of companies and individuals offer support for GNU products. 19285If you obtained `as' from a support organization, we recommend you 19286contact that organization first. 19287 19288 You can find contact information for many support companies and 19289individuals in the file `etc/SERVICE' in the GNU Emacs distribution. 19290 19291 In any event, we also recommend that you send bug reports for `as' 19292to `http://www.sourceware.org/bugzilla/'. 19293 19294 The fundamental principle of reporting bugs usefully is this: 19295*report all the facts*. If you are not sure whether to state a fact or 19296leave it out, state it! 19297 19298 Often people omit facts because they think they know what causes the 19299problem and assume that some details do not matter. Thus, you might 19300assume that the name of a symbol you use in an example does not matter. 19301Well, probably it does not, but one cannot be sure. Perhaps the bug 19302is a stray memory reference which happens to fetch from the location 19303where that name is stored in memory; perhaps, if the name were 19304different, the contents of that location would fool the assembler into 19305doing the right thing despite the bug. Play it safe and give a 19306specific, complete example. That is the easiest thing for you to do, 19307and the most helpful. 19308 19309 Keep in mind that the purpose of a bug report is to enable us to fix 19310the bug if it is new to us. Therefore, always write your bug reports 19311on the assumption that the bug has not been reported previously. 19312 19313 Sometimes people give a few sketchy facts and ask, "Does this ring a 19314bell?" This cannot help us fix a bug, so it is basically useless. We 19315respond by asking for enough details to enable us to investigate. You 19316might as well expedite matters by sending them to begin with. 19317 19318 To enable us to fix the bug, you should include all these things: 19319 19320 * The version of `as'. `as' announces it if you start it with the 19321 `--version' argument. 19322 19323 Without this, we will not know whether there is any point in 19324 looking for the bug in the current version of `as'. 19325 19326 * Any patches you may have applied to the `as' source. 19327 19328 * The type of machine you are using, and the operating system name 19329 and version number. 19330 19331 * What compiler (and its version) was used to compile `as'--e.g. 19332 "`gcc-2.7'". 19333 19334 * The command arguments you gave the assembler to assemble your 19335 example and observe the bug. To guarantee you will not omit 19336 something important, list them all. A copy of the Makefile (or 19337 the output from make) is sufficient. 19338 19339 If we were to try to guess the arguments, we would probably guess 19340 wrong and then we might not encounter the bug. 19341 19342 * A complete input file that will reproduce the bug. If the bug is 19343 observed when the assembler is invoked via a compiler, send the 19344 assembler source, not the high level language source. Most 19345 compilers will produce the assembler source when run with the `-S' 19346 option. If you are using `gcc', use the options `-v 19347 --save-temps'; this will save the assembler source in a file with 19348 an extension of `.s', and also show you exactly how `as' is being 19349 run. 19350 19351 * A description of what behavior you observe that you believe is 19352 incorrect. For example, "It gets a fatal signal." 19353 19354 Of course, if the bug is that `as' gets a fatal signal, then we 19355 will certainly notice it. But if the bug is incorrect output, we 19356 might not notice unless it is glaringly wrong. You might as well 19357 not give us a chance to make a mistake. 19358 19359 Even if the problem you experience is a fatal signal, you should 19360 still say so explicitly. Suppose something strange is going on, 19361 such as, your copy of `as' is out of sync, or you have encountered 19362 a bug in the C library on your system. (This has happened!) Your 19363 copy might crash and ours would not. If you told us to expect a 19364 crash, then when ours fails to crash, we would know that the bug 19365 was not happening for us. If you had not told us to expect a 19366 crash, then we would not be able to draw any conclusion from our 19367 observations. 19368 19369 * If you wish to suggest changes to the `as' source, send us context 19370 diffs, as generated by `diff' with the `-u', `-c', or `-p' option. 19371 Always send diffs from the old file to the new file. If you even 19372 discuss something in the `as' source, refer to it by context, not 19373 by line number. 19374 19375 The line numbers in our development sources will not match those 19376 in your sources. Your line numbers would convey no useful 19377 information to us. 19378 19379 Here are some things that are not necessary: 19380 19381 * A description of the envelope of the bug. 19382 19383 Often people who encounter a bug spend a lot of time investigating 19384 which changes to the input file will make the bug go away and which 19385 changes will not affect it. 19386 19387 This is often time consuming and not very useful, because the way 19388 we will find the bug is by running a single example under the 19389 debugger with breakpoints, not by pure deduction from a series of 19390 examples. We recommend that you save your time for something else. 19391 19392 Of course, if you can find a simpler example to report _instead_ 19393 of the original one, that is a convenience for us. Errors in the 19394 output will be easier to spot, running under the debugger will take 19395 less time, and so on. 19396 19397 However, simplification is not vital; if you do not want to do 19398 this, report the bug anyway and send us the entire test case you 19399 used. 19400 19401 * A patch for the bug. 19402 19403 A patch for the bug does help us if it is a good one. But do not 19404 omit the necessary information, such as the test case, on the 19405 assumption that a patch is all we need. We might see problems 19406 with your patch and decide to fix the problem another way, or we 19407 might not understand it at all. 19408 19409 Sometimes with a program as complicated as `as' it is very hard to 19410 construct an example that will make the program follow a certain 19411 path through the code. If you do not send us the example, we will 19412 not be able to construct one, so we will not be able to verify 19413 that the bug is fixed. 19414 19415 And if we cannot understand what bug you are trying to fix, or why 19416 your patch should be an improvement, we will not install it. A 19417 test case will help us to understand. 19418 19419 * A guess about what the bug is or what it depends on. 19420 19421 Such guesses are usually wrong. Even we cannot guess right about 19422 such things without first using the debugger to find the facts. 19423 19424 19425File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 19426 1942711 Acknowledgements 19428******************* 19429 19430If you have contributed to GAS and your name isn't listed here, it is 19431not meant as a slight. We just don't know about it. Send mail to the 19432maintainer, and we'll correct the situation. Currently the maintainer 19433is Ken Raeburn (email address `raeburn@cygnus.com'). 19434 19435 Dean Elsner wrote the original GNU assembler for the VAX.(1) 19436 19437 Jay Fenlason maintained GAS for a while, adding support for 19438GDB-specific debug information and the 68k series machines, most of the 19439preprocessing pass, and extensive changes in `messages.c', 19440`input-file.c', `write.c'. 19441 19442 K. Richard Pixley maintained GAS for a while, adding various 19443enhancements and many bug fixes, including merging support for several 19444processors, breaking GAS up to handle multiple object file format back 19445ends (including heavy rewrite, testing, an integration of the coff and 19446b.out back ends), adding configuration including heavy testing and 19447verification of cross assemblers and file splits and renaming, 19448converted GAS to strictly ANSI C including full prototypes, added 19449support for m680[34]0 and cpu32, did considerable work on i960 19450including a COFF port (including considerable amounts of reverse 19451engineering), a SPARC opcode file rewrite, DECstation, rs6000, and 19452hp300hpux host ports, updated "know" assertions and made them work, 19453much other reorganization, cleanup, and lint. 19454 19455 Ken Raeburn wrote the high-level BFD interface code to replace most 19456of the code in format-specific I/O modules. 19457 19458 The original VMS support was contributed by David L. Kashtan. Eric 19459Youngdale has done much work with it since. 19460 19461 The Intel 80386 machine description was written by Eliot Dresselhaus. 19462 19463 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 19464 19465 The Motorola 88k machine description was contributed by Devon Bowen 19466of Buffalo University and Torbjorn Granlund of the Swedish Institute of 19467Computer Science. 19468 19469 Keith Knowles at the Open Software Foundation wrote the original 19470MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format 19471support (which hasn't been merged in yet). Ralph Campbell worked with 19472the MIPS code to support a.out format. 19473 19474 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 19475tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 19476Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 19477end to use BFD for some low-level operations, for use with the H8/300 19478and AMD 29k targets. 19479 19480 John Gilmore built the AMD 29000 support, added `.include' support, 19481and simplified the configuration of which versions accept which 19482directives. He updated the 68k machine description so that Motorola's 19483opcodes always produced fixed-size instructions (e.g., `jsr'), while 19484synthetic instructions remained shrinkable (`jbsr'). John fixed many 19485bugs, including true tested cross-compilation support, and one bug in 19486relaxation that took a week and required the proverbial one-bit fix. 19487 19488 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT 19489syntax for the 68k, completed support for some COFF targets (68k, i386 19490SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, 19491wrote the initial RS/6000 and PowerPC assembler, and made a few other 19492minor patches. 19493 19494 Steve Chamberlain made GAS able to generate listings. 19495 19496 Hewlett-Packard contributed support for the HP9000/300. 19497 19498 Jeff Law wrote GAS and BFD support for the native HPPA object format 19499(SOM) along with a fairly extensive HPPA testsuite (for both SOM and 19500ELF object formats). This work was supported by both the Center for 19501Software Science at the University of Utah and Cygnus Support. 19502 19503 Support for ELF format files has been worked on by Mark Eichin of 19504Cygnus Support (original, incomplete implementation for SPARC), Pete 19505Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), 19506Michael Meissner of the Open Software Foundation (i386 mainly), and Ken 19507Raeburn of Cygnus Support (sparc, and some initial 64-bit support). 19508 19509 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 19510architecture. 19511 19512 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 19513GAS and BFD support for openVMS/Alpha. 19514 19515 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 19516various tic* flavors. 19517 19518 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 19519Tensilica, Inc. added support for Xtensa processors. 19520 19521 Several engineers at Cygnus Support have also provided many small 19522bug fixes and configuration enhancements. 19523 19524 Jon Beniston added support for the Lattice Mico32 architecture. 19525 19526 Many others have contributed large or small bugfixes and 19527enhancements. If you have contributed significant work and are not 19528mentioned on this list, and want to be, let us know. Some of the 19529history has been lost; we are not intentionally leaving anyone out. 19530 19531 ---------- Footnotes ---------- 19532 19533 (1) Any more details? 19534 19535 19536File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 19537 19538Appendix A GNU Free Documentation License 19539***************************************** 19540 19541 Version 1.3, 3 November 2008 19542 19543 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 19544 `http://fsf.org/' 19545 19546 Everyone is permitted to copy and distribute verbatim copies 19547 of this license document, but changing it is not allowed. 19548 19549 0. PREAMBLE 19550 19551 The purpose of this License is to make a manual, textbook, or other 19552 functional and useful document "free" in the sense of freedom: to 19553 assure everyone the effective freedom to copy and redistribute it, 19554 with or without modifying it, either commercially or 19555 noncommercially. Secondarily, this License preserves for the 19556 author and publisher a way to get credit for their work, while not 19557 being considered responsible for modifications made by others. 19558 19559 This License is a kind of "copyleft", which means that derivative 19560 works of the document must themselves be free in the same sense. 19561 It complements the GNU General Public License, which is a copyleft 19562 license designed for free software. 19563 19564 We have designed this License in order to use it for manuals for 19565 free software, because free software needs free documentation: a 19566 free program should come with manuals providing the same freedoms 19567 that the software does. But this License is not limited to 19568 software manuals; it can be used for any textual work, regardless 19569 of subject matter or whether it is published as a printed book. 19570 We recommend this License principally for works whose purpose is 19571 instruction or reference. 19572 19573 1. APPLICABILITY AND DEFINITIONS 19574 19575 This License applies to any manual or other work, in any medium, 19576 that contains a notice placed by the copyright holder saying it 19577 can be distributed under the terms of this License. Such a notice 19578 grants a world-wide, royalty-free license, unlimited in duration, 19579 to use that work under the conditions stated herein. The 19580 "Document", below, refers to any such manual or work. Any member 19581 of the public is a licensee, and is addressed as "you". You 19582 accept the license if you copy, modify or distribute the work in a 19583 way requiring permission under copyright law. 19584 19585 A "Modified Version" of the Document means any work containing the 19586 Document or a portion of it, either copied verbatim, or with 19587 modifications and/or translated into another language. 19588 19589 A "Secondary Section" is a named appendix or a front-matter section 19590 of the Document that deals exclusively with the relationship of the 19591 publishers or authors of the Document to the Document's overall 19592 subject (or to related matters) and contains nothing that could 19593 fall directly within that overall subject. (Thus, if the Document 19594 is in part a textbook of mathematics, a Secondary Section may not 19595 explain any mathematics.) The relationship could be a matter of 19596 historical connection with the subject or with related matters, or 19597 of legal, commercial, philosophical, ethical or political position 19598 regarding them. 19599 19600 The "Invariant Sections" are certain Secondary Sections whose 19601 titles are designated, as being those of Invariant Sections, in 19602 the notice that says that the Document is released under this 19603 License. If a section does not fit the above definition of 19604 Secondary then it is not allowed to be designated as Invariant. 19605 The Document may contain zero Invariant Sections. If the Document 19606 does not identify any Invariant Sections then there are none. 19607 19608 The "Cover Texts" are certain short passages of text that are 19609 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 19610 that says that the Document is released under this License. A 19611 Front-Cover Text may be at most 5 words, and a Back-Cover Text may 19612 be at most 25 words. 19613 19614 A "Transparent" copy of the Document means a machine-readable copy, 19615 represented in a format whose specification is available to the 19616 general public, that is suitable for revising the document 19617 straightforwardly with generic text editors or (for images 19618 composed of pixels) generic paint programs or (for drawings) some 19619 widely available drawing editor, and that is suitable for input to 19620 text formatters or for automatic translation to a variety of 19621 formats suitable for input to text formatters. A copy made in an 19622 otherwise Transparent file format whose markup, or absence of 19623 markup, has been arranged to thwart or discourage subsequent 19624 modification by readers is not Transparent. An image format is 19625 not Transparent if used for any substantial amount of text. A 19626 copy that is not "Transparent" is called "Opaque". 19627 19628 Examples of suitable formats for Transparent copies include plain 19629 ASCII without markup, Texinfo input format, LaTeX input format, 19630 SGML or XML using a publicly available DTD, and 19631 standard-conforming simple HTML, PostScript or PDF designed for 19632 human modification. Examples of transparent image formats include 19633 PNG, XCF and JPG. Opaque formats include proprietary formats that 19634 can be read and edited only by proprietary word processors, SGML or 19635 XML for which the DTD and/or processing tools are not generally 19636 available, and the machine-generated HTML, PostScript or PDF 19637 produced by some word processors for output purposes only. 19638 19639 The "Title Page" means, for a printed book, the title page itself, 19640 plus such following pages as are needed to hold, legibly, the 19641 material this License requires to appear in the title page. For 19642 works in formats which do not have any title page as such, "Title 19643 Page" means the text near the most prominent appearance of the 19644 work's title, preceding the beginning of the body of the text. 19645 19646 The "publisher" means any person or entity that distributes copies 19647 of the Document to the public. 19648 19649 A section "Entitled XYZ" means a named subunit of the Document 19650 whose title either is precisely XYZ or contains XYZ in parentheses 19651 following text that translates XYZ in another language. (Here XYZ 19652 stands for a specific section name mentioned below, such as 19653 "Acknowledgements", "Dedications", "Endorsements", or "History".) 19654 To "Preserve the Title" of such a section when you modify the 19655 Document means that it remains a section "Entitled XYZ" according 19656 to this definition. 19657 19658 The Document may include Warranty Disclaimers next to the notice 19659 which states that this License applies to the Document. These 19660 Warranty Disclaimers are considered to be included by reference in 19661 this License, but only as regards disclaiming warranties: any other 19662 implication that these Warranty Disclaimers may have is void and 19663 has no effect on the meaning of this License. 19664 19665 2. VERBATIM COPYING 19666 19667 You may copy and distribute the Document in any medium, either 19668 commercially or noncommercially, provided that this License, the 19669 copyright notices, and the license notice saying this License 19670 applies to the Document are reproduced in all copies, and that you 19671 add no other conditions whatsoever to those of this License. You 19672 may not use technical measures to obstruct or control the reading 19673 or further copying of the copies you make or distribute. However, 19674 you may accept compensation in exchange for copies. If you 19675 distribute a large enough number of copies you must also follow 19676 the conditions in section 3. 19677 19678 You may also lend copies, under the same conditions stated above, 19679 and you may publicly display copies. 19680 19681 3. COPYING IN QUANTITY 19682 19683 If you publish printed copies (or copies in media that commonly 19684 have printed covers) of the Document, numbering more than 100, and 19685 the Document's license notice requires Cover Texts, you must 19686 enclose the copies in covers that carry, clearly and legibly, all 19687 these Cover Texts: Front-Cover Texts on the front cover, and 19688 Back-Cover Texts on the back cover. Both covers must also clearly 19689 and legibly identify you as the publisher of these copies. The 19690 front cover must present the full title with all words of the 19691 title equally prominent and visible. You may add other material 19692 on the covers in addition. Copying with changes limited to the 19693 covers, as long as they preserve the title of the Document and 19694 satisfy these conditions, can be treated as verbatim copying in 19695 other respects. 19696 19697 If the required texts for either cover are too voluminous to fit 19698 legibly, you should put the first ones listed (as many as fit 19699 reasonably) on the actual cover, and continue the rest onto 19700 adjacent pages. 19701 19702 If you publish or distribute Opaque copies of the Document 19703 numbering more than 100, you must either include a 19704 machine-readable Transparent copy along with each Opaque copy, or 19705 state in or with each Opaque copy a computer-network location from 19706 which the general network-using public has access to download 19707 using public-standard network protocols a complete Transparent 19708 copy of the Document, free of added material. If you use the 19709 latter option, you must take reasonably prudent steps, when you 19710 begin distribution of Opaque copies in quantity, to ensure that 19711 this Transparent copy will remain thus accessible at the stated 19712 location until at least one year after the last time you 19713 distribute an Opaque copy (directly or through your agents or 19714 retailers) of that edition to the public. 19715 19716 It is requested, but not required, that you contact the authors of 19717 the Document well before redistributing any large number of 19718 copies, to give them a chance to provide you with an updated 19719 version of the Document. 19720 19721 4. MODIFICATIONS 19722 19723 You may copy and distribute a Modified Version of the Document 19724 under the conditions of sections 2 and 3 above, provided that you 19725 release the Modified Version under precisely this License, with 19726 the Modified Version filling the role of the Document, thus 19727 licensing distribution and modification of the Modified Version to 19728 whoever possesses a copy of it. In addition, you must do these 19729 things in the Modified Version: 19730 19731 A. Use in the Title Page (and on the covers, if any) a title 19732 distinct from that of the Document, and from those of 19733 previous versions (which should, if there were any, be listed 19734 in the History section of the Document). You may use the 19735 same title as a previous version if the original publisher of 19736 that version gives permission. 19737 19738 B. List on the Title Page, as authors, one or more persons or 19739 entities responsible for authorship of the modifications in 19740 the Modified Version, together with at least five of the 19741 principal authors of the Document (all of its principal 19742 authors, if it has fewer than five), unless they release you 19743 from this requirement. 19744 19745 C. State on the Title page the name of the publisher of the 19746 Modified Version, as the publisher. 19747 19748 D. Preserve all the copyright notices of the Document. 19749 19750 E. Add an appropriate copyright notice for your modifications 19751 adjacent to the other copyright notices. 19752 19753 F. Include, immediately after the copyright notices, a license 19754 notice giving the public permission to use the Modified 19755 Version under the terms of this License, in the form shown in 19756 the Addendum below. 19757 19758 G. Preserve in that license notice the full lists of Invariant 19759 Sections and required Cover Texts given in the Document's 19760 license notice. 19761 19762 H. Include an unaltered copy of this License. 19763 19764 I. Preserve the section Entitled "History", Preserve its Title, 19765 and add to it an item stating at least the title, year, new 19766 authors, and publisher of the Modified Version as given on 19767 the Title Page. If there is no section Entitled "History" in 19768 the Document, create one stating the title, year, authors, 19769 and publisher of the Document as given on its Title Page, 19770 then add an item describing the Modified Version as stated in 19771 the previous sentence. 19772 19773 J. Preserve the network location, if any, given in the Document 19774 for public access to a Transparent copy of the Document, and 19775 likewise the network locations given in the Document for 19776 previous versions it was based on. These may be placed in 19777 the "History" section. You may omit a network location for a 19778 work that was published at least four years before the 19779 Document itself, or if the original publisher of the version 19780 it refers to gives permission. 19781 19782 K. For any section Entitled "Acknowledgements" or "Dedications", 19783 Preserve the Title of the section, and preserve in the 19784 section all the substance and tone of each of the contributor 19785 acknowledgements and/or dedications given therein. 19786 19787 L. Preserve all the Invariant Sections of the Document, 19788 unaltered in their text and in their titles. Section numbers 19789 or the equivalent are not considered part of the section 19790 titles. 19791 19792 M. Delete any section Entitled "Endorsements". Such a section 19793 may not be included in the Modified Version. 19794 19795 N. Do not retitle any existing section to be Entitled 19796 "Endorsements" or to conflict in title with any Invariant 19797 Section. 19798 19799 O. Preserve any Warranty Disclaimers. 19800 19801 If the Modified Version includes new front-matter sections or 19802 appendices that qualify as Secondary Sections and contain no 19803 material copied from the Document, you may at your option 19804 designate some or all of these sections as invariant. To do this, 19805 add their titles to the list of Invariant Sections in the Modified 19806 Version's license notice. These titles must be distinct from any 19807 other section titles. 19808 19809 You may add a section Entitled "Endorsements", provided it contains 19810 nothing but endorsements of your Modified Version by various 19811 parties--for example, statements of peer review or that the text 19812 has been approved by an organization as the authoritative 19813 definition of a standard. 19814 19815 You may add a passage of up to five words as a Front-Cover Text, 19816 and a passage of up to 25 words as a Back-Cover Text, to the end 19817 of the list of Cover Texts in the Modified Version. Only one 19818 passage of Front-Cover Text and one of Back-Cover Text may be 19819 added by (or through arrangements made by) any one entity. If the 19820 Document already includes a cover text for the same cover, 19821 previously added by you or by arrangement made by the same entity 19822 you are acting on behalf of, you may not add another; but you may 19823 replace the old one, on explicit permission from the previous 19824 publisher that added the old one. 19825 19826 The author(s) and publisher(s) of the Document do not by this 19827 License give permission to use their names for publicity for or to 19828 assert or imply endorsement of any Modified Version. 19829 19830 5. COMBINING DOCUMENTS 19831 19832 You may combine the Document with other documents released under 19833 this License, under the terms defined in section 4 above for 19834 modified versions, provided that you include in the combination 19835 all of the Invariant Sections of all of the original documents, 19836 unmodified, and list them all as Invariant Sections of your 19837 combined work in its license notice, and that you preserve all 19838 their Warranty Disclaimers. 19839 19840 The combined work need only contain one copy of this License, and 19841 multiple identical Invariant Sections may be replaced with a single 19842 copy. If there are multiple Invariant Sections with the same name 19843 but different contents, make the title of each such section unique 19844 by adding at the end of it, in parentheses, the name of the 19845 original author or publisher of that section if known, or else a 19846 unique number. Make the same adjustment to the section titles in 19847 the list of Invariant Sections in the license notice of the 19848 combined work. 19849 19850 In the combination, you must combine any sections Entitled 19851 "History" in the various original documents, forming one section 19852 Entitled "History"; likewise combine any sections Entitled 19853 "Acknowledgements", and any sections Entitled "Dedications". You 19854 must delete all sections Entitled "Endorsements." 19855 19856 6. COLLECTIONS OF DOCUMENTS 19857 19858 You may make a collection consisting of the Document and other 19859 documents released under this License, and replace the individual 19860 copies of this License in the various documents with a single copy 19861 that is included in the collection, provided that you follow the 19862 rules of this License for verbatim copying of each of the 19863 documents in all other respects. 19864 19865 You may extract a single document from such a collection, and 19866 distribute it individually under this License, provided you insert 19867 a copy of this License into the extracted document, and follow 19868 this License in all other respects regarding verbatim copying of 19869 that document. 19870 19871 7. AGGREGATION WITH INDEPENDENT WORKS 19872 19873 A compilation of the Document or its derivatives with other 19874 separate and independent documents or works, in or on a volume of 19875 a storage or distribution medium, is called an "aggregate" if the 19876 copyright resulting from the compilation is not used to limit the 19877 legal rights of the compilation's users beyond what the individual 19878 works permit. When the Document is included in an aggregate, this 19879 License does not apply to the other works in the aggregate which 19880 are not themselves derivative works of the Document. 19881 19882 If the Cover Text requirement of section 3 is applicable to these 19883 copies of the Document, then if the Document is less than one half 19884 of the entire aggregate, the Document's Cover Texts may be placed 19885 on covers that bracket the Document within the aggregate, or the 19886 electronic equivalent of covers if the Document is in electronic 19887 form. Otherwise they must appear on printed covers that bracket 19888 the whole aggregate. 19889 19890 8. TRANSLATION 19891 19892 Translation is considered a kind of modification, so you may 19893 distribute translations of the Document under the terms of section 19894 4. Replacing Invariant Sections with translations requires special 19895 permission from their copyright holders, but you may include 19896 translations of some or all Invariant Sections in addition to the 19897 original versions of these Invariant Sections. You may include a 19898 translation of this License, and all the license notices in the 19899 Document, and any Warranty Disclaimers, provided that you also 19900 include the original English version of this License and the 19901 original versions of those notices and disclaimers. In case of a 19902 disagreement between the translation and the original version of 19903 this License or a notice or disclaimer, the original version will 19904 prevail. 19905 19906 If a section in the Document is Entitled "Acknowledgements", 19907 "Dedications", or "History", the requirement (section 4) to 19908 Preserve its Title (section 1) will typically require changing the 19909 actual title. 19910 19911 9. TERMINATION 19912 19913 You may not copy, modify, sublicense, or distribute the Document 19914 except as expressly provided under this License. Any attempt 19915 otherwise to copy, modify, sublicense, or distribute it is void, 19916 and will automatically terminate your rights under this License. 19917 19918 However, if you cease all violation of this License, then your 19919 license from a particular copyright holder is reinstated (a) 19920 provisionally, unless and until the copyright holder explicitly 19921 and finally terminates your license, and (b) permanently, if the 19922 copyright holder fails to notify you of the violation by some 19923 reasonable means prior to 60 days after the cessation. 19924 19925 Moreover, your license from a particular copyright holder is 19926 reinstated permanently if the copyright holder notifies you of the 19927 violation by some reasonable means, this is the first time you have 19928 received notice of violation of this License (for any work) from 19929 that copyright holder, and you cure the violation prior to 30 days 19930 after your receipt of the notice. 19931 19932 Termination of your rights under this section does not terminate 19933 the licenses of parties who have received copies or rights from 19934 you under this License. If your rights have been terminated and 19935 not permanently reinstated, receipt of a copy of some or all of 19936 the same material does not give you any rights to use it. 19937 19938 10. FUTURE REVISIONS OF THIS LICENSE 19939 19940 The Free Software Foundation may publish new, revised versions of 19941 the GNU Free Documentation License from time to time. Such new 19942 versions will be similar in spirit to the present version, but may 19943 differ in detail to address new problems or concerns. See 19944 `http://www.gnu.org/copyleft/'. 19945 19946 Each version of the License is given a distinguishing version 19947 number. If the Document specifies that a particular numbered 19948 version of this License "or any later version" applies to it, you 19949 have the option of following the terms and conditions either of 19950 that specified version or of any later version that has been 19951 published (not as a draft) by the Free Software Foundation. If 19952 the Document does not specify a version number of this License, 19953 you may choose any version ever published (not as a draft) by the 19954 Free Software Foundation. If the Document specifies that a proxy 19955 can decide which future versions of this License can be used, that 19956 proxy's public statement of acceptance of a version permanently 19957 authorizes you to choose that version for the Document. 19958 19959 11. RELICENSING 19960 19961 "Massive Multiauthor Collaboration Site" (or "MMC Site") means any 19962 World Wide Web server that publishes copyrightable works and also 19963 provides prominent facilities for anybody to edit those works. A 19964 public wiki that anybody can edit is an example of such a server. 19965 A "Massive Multiauthor Collaboration" (or "MMC") contained in the 19966 site means any set of copyrightable works thus published on the MMC 19967 site. 19968 19969 "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0 19970 license published by Creative Commons Corporation, a not-for-profit 19971 corporation with a principal place of business in San Francisco, 19972 California, as well as future copyleft versions of that license 19973 published by that same organization. 19974 19975 "Incorporate" means to publish or republish a Document, in whole or 19976 in part, as part of another Document. 19977 19978 An MMC is "eligible for relicensing" if it is licensed under this 19979 License, and if all works that were first published under this 19980 License somewhere other than this MMC, and subsequently 19981 incorporated in whole or in part into the MMC, (1) had no cover 19982 texts or invariant sections, and (2) were thus incorporated prior 19983 to November 1, 2008. 19984 19985 The operator of an MMC Site may republish an MMC contained in the 19986 site under CC-BY-SA on the same site at any time before August 1, 19987 2009, provided the MMC is eligible for relicensing. 19988 19989 19990ADDENDUM: How to use this License for your documents 19991==================================================== 19992 19993To use this License in a document you have written, include a copy of 19994the License in the document and put the following copyright and license 19995notices just after the title page: 19996 19997 Copyright (C) YEAR YOUR NAME. 19998 Permission is granted to copy, distribute and/or modify this document 19999 under the terms of the GNU Free Documentation License, Version 1.3 20000 or any later version published by the Free Software Foundation; 20001 with no Invariant Sections, no Front-Cover Texts, and no Back-Cover 20002 Texts. A copy of the license is included in the section entitled ``GNU 20003 Free Documentation License''. 20004 20005 If you have Invariant Sections, Front-Cover Texts and Back-Cover 20006Texts, replace the "with...Texts." line with this: 20007 20008 with the Invariant Sections being LIST THEIR TITLES, with 20009 the Front-Cover Texts being LIST, and with the Back-Cover Texts 20010 being LIST. 20011 20012 If you have Invariant Sections without Cover Texts, or some other 20013combination of the three, merge those two alternatives to suit the 20014situation. 20015 20016 If your document contains nontrivial examples of program code, we 20017recommend releasing these examples in parallel under your choice of 20018free software license, such as the GNU General Public License, to 20019permit their use in free software. 20020 20021 20022File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 20023 20024AS Index 20025******** 20026 20027�[index�] 20028* Menu: 20029 20030* #: Comments. (line 39) 20031* #APP: Preprocessing. (line 27) 20032* #NO_APP: Preprocessing. (line 27) 20033* $ in symbol names <1>: D10V-Chars. (line 46) 20034* $ in symbol names <2>: D30V-Chars. (line 63) 20035* $ in symbol names <3>: SH64-Chars. (line 10) 20036* $ in symbol names: SH-Chars. (line 10) 20037* $a: ARM Mapping Symbols. (line 9) 20038* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 20039* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 20040* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 20041* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 20042* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 20043* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 20044* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 20045* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 20046* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 20047* $d: ARM Mapping Symbols. (line 15) 20048* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 20049* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 20050* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 20051* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 20052* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 20053* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 20054* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 20055* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 20056* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 20057* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 20058* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 20059* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 20060* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 20061* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 20062* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 20063* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 20064* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 20065* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 20066* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 20067* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 20068* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 20069* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 20070* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 20071* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 20072* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 20073* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 20074* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 20075* $t: ARM Mapping Symbols. (line 12) 20076* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 20077* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 20078* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 20079* -+ option, VAX/VMS: VAX-Opts. (line 71) 20080* --: Command Line. (line 10) 20081* --32 option, i386: i386-Options. (line 8) 20082* --32 option, x86-64: i386-Options. (line 8) 20083* --64 option, i386: i386-Options. (line 8) 20084* --64 option, x86-64: i386-Options. (line 8) 20085* --absolute-literals: Xtensa Options. (line 23) 20086* --allow-reg-prefix: SH Options. (line 9) 20087* --alternate: alternate. (line 6) 20088* --base-size-default-16: M68K-Opts. (line 65) 20089* --base-size-default-32: M68K-Opts. (line 65) 20090* --big: SH Options. (line 9) 20091* --bitwise-or option, M680x0: M68K-Opts. (line 58) 20092* --disp-size-default-16: M68K-Opts. (line 74) 20093* --disp-size-default-32: M68K-Opts. (line 74) 20094* --divide option, i386: i386-Options. (line 24) 20095* --dsp: SH Options. (line 9) 20096* --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9) 20097* --emulation=criself command line option, CRIS: CRIS-Opts. (line 9) 20098* --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 20099* --fatal-warnings: W. (line 16) 20100* --fdpic: SH Options. (line 31) 20101* --fix-v4bx command line option, ARM: ARM Options. (line 165) 20102* --fixed-special-register-names command line option, MMIX: MMIX-Opts. 20103 (line 8) 20104* --force-long-branches: M68HC11-Opts. (line 69) 20105* --generate-example: M68HC11-Opts. (line 86) 20106* --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12) 20107* --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16) 20108* --hash-size=NUMBER: Overview. (line 364) 20109* --linker-allocated-gregs command line option, MMIX: MMIX-Opts. 20110 (line 67) 20111* --listing-cont-lines: listing. (line 34) 20112* --listing-lhs-width: listing. (line 16) 20113* --listing-lhs-width2: listing. (line 21) 20114* --listing-rhs-width: listing. (line 28) 20115* --little: SH Options. (line 9) 20116* --longcalls: Xtensa Options. (line 37) 20117* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 33) 20118* --MD: MD. (line 6) 20119* --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 61) 20120* --no-absolute-literals: Xtensa Options. (line 23) 20121* --no-expand command line option, MMIX: MMIX-Opts. (line 31) 20122* --no-longcalls: Xtensa Options. (line 37) 20123* --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36) 20124* --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 61) 20125* --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22) 20126* --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54) 20127* --no-stubs command line option, MMIX: MMIX-Opts. (line 54) 20128* --no-target-align: Xtensa Options. (line 30) 20129* --no-text-section-literals: Xtensa Options. (line 9) 20130* --no-transform: Xtensa Options. (line 46) 20131* --no-underscore command line option, CRIS: CRIS-Opts. (line 15) 20132* --no-warn: W. (line 11) 20133* --pcrel: M68K-Opts. (line 86) 20134* --pic command line option, CRIS: CRIS-Opts. (line 27) 20135* --print-insn-syntax: M68HC11-Opts. (line 75) 20136* --print-opcodes: M68HC11-Opts. (line 79) 20137* --register-prefix-optional option, M680x0: M68K-Opts. (line 45) 20138* --relax: SH Options. (line 9) 20139* --relax command line option, MMIX: MMIX-Opts. (line 19) 20140* --rename-section: Xtensa Options. (line 54) 20141* --renesas: SH Options. (line 9) 20142* --short-branches: M68HC11-Opts. (line 54) 20143* --small: SH Options. (line 9) 20144* --statistics: statistics. (line 6) 20145* --strict-direct-mode: M68HC11-Opts. (line 44) 20146* --target-align: Xtensa Options. (line 30) 20147* --text-section-literals: Xtensa Options. (line 9) 20148* --traditional-format: traditional-format. (line 6) 20149* --transform: Xtensa Options. (line 46) 20150* --underscore command line option, CRIS: CRIS-Opts. (line 15) 20151* --warn: W. (line 19) 20152* -1 option, VAX/VMS: VAX-Opts. (line 77) 20153* -32addr command line option, Alpha: Alpha Options. (line 57) 20154* -a: a. (line 6) 20155* -A options, i960: Options-i960. (line 6) 20156* -ac: a. (line 6) 20157* -ad: a. (line 6) 20158* -ag: a. (line 6) 20159* -ah: a. (line 6) 20160* -al: a. (line 6) 20161* -an: a. (line 6) 20162* -as: a. (line 6) 20163* -Asparclet: Sparc-Opts. (line 25) 20164* -Asparclite: Sparc-Opts. (line 25) 20165* -Av6: Sparc-Opts. (line 25) 20166* -Av8: Sparc-Opts. (line 25) 20167* -Av9: Sparc-Opts. (line 25) 20168* -Av9a: Sparc-Opts. (line 25) 20169* -b option, i960: Options-i960. (line 22) 20170* -big option, M32R: M32R-Opts. (line 35) 20171* -D: D. (line 6) 20172* -D, ignored on VAX: VAX-Opts. (line 11) 20173* -d, VAX option: VAX-Opts. (line 16) 20174* -eabi= command line option, ARM: ARM Options. (line 148) 20175* -EB command line option, ARC: ARC Options. (line 31) 20176* -EB command line option, ARM: ARM Options. (line 153) 20177* -EB option (MIPS): MIPS Opts. (line 13) 20178* -EB option, M32R: M32R-Opts. (line 39) 20179* -EL command line option, ARC: ARC Options. (line 35) 20180* -EL command line option, ARM: ARM Options. (line 157) 20181* -EL option (MIPS): MIPS Opts. (line 13) 20182* -EL option, M32R: M32R-Opts. (line 32) 20183* -f: f. (line 6) 20184* -F command line option, Alpha: Alpha Options. (line 57) 20185* -G command line option, Alpha: Alpha Options. (line 53) 20186* -g command line option, Alpha: Alpha Options. (line 47) 20187* -G option (MIPS): MIPS Opts. (line 8) 20188* -h option, VAX/VMS: VAX-Opts. (line 45) 20189* -H option, VAX/VMS: VAX-Opts. (line 81) 20190* -I PATH: I. (line 6) 20191* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 20192* -Ip option, M32RX: M32R-Opts. (line 97) 20193* -J, ignored on VAX: VAX-Opts. (line 27) 20194* -K: K. (line 6) 20195* -k command line option, ARM: ARM Options. (line 161) 20196* -KPIC option, M32R: M32R-Opts. (line 42) 20197* -KPIC option, MIPS: MIPS Opts. (line 21) 20198* -L: L. (line 6) 20199* -l option, M680x0: M68K-Opts. (line 33) 20200* -little option, M32R: M32R-Opts. (line 27) 20201* -M: M. (line 6) 20202* -m11/03: PDP-11-Options. (line 140) 20203* -m11/04: PDP-11-Options. (line 143) 20204* -m11/05: PDP-11-Options. (line 146) 20205* -m11/10: PDP-11-Options. (line 146) 20206* -m11/15: PDP-11-Options. (line 149) 20207* -m11/20: PDP-11-Options. (line 149) 20208* -m11/21: PDP-11-Options. (line 152) 20209* -m11/23: PDP-11-Options. (line 155) 20210* -m11/24: PDP-11-Options. (line 155) 20211* -m11/34: PDP-11-Options. (line 158) 20212* -m11/34a: PDP-11-Options. (line 161) 20213* -m11/35: PDP-11-Options. (line 164) 20214* -m11/40: PDP-11-Options. (line 164) 20215* -m11/44: PDP-11-Options. (line 167) 20216* -m11/45: PDP-11-Options. (line 170) 20217* -m11/50: PDP-11-Options. (line 170) 20218* -m11/53: PDP-11-Options. (line 173) 20219* -m11/55: PDP-11-Options. (line 170) 20220* -m11/60: PDP-11-Options. (line 176) 20221* -m11/70: PDP-11-Options. (line 170) 20222* -m11/73: PDP-11-Options. (line 173) 20223* -m11/83: PDP-11-Options. (line 173) 20224* -m11/84: PDP-11-Options. (line 173) 20225* -m11/93: PDP-11-Options. (line 173) 20226* -m11/94: PDP-11-Options. (line 173) 20227* -m16c option, M16C: M32C-Opts. (line 12) 20228* -m31 option, s390: s390 Options. (line 8) 20229* -m32bit-doubles: RX-Opts. (line 9) 20230* -m32c option, M32C: M32C-Opts. (line 9) 20231* -m32r option, M32R: M32R-Opts. (line 21) 20232* -m32rx option, M32R2: M32R-Opts. (line 17) 20233* -m32rx option, M32RX: M32R-Opts. (line 9) 20234* -m64 option, s390: s390 Options. (line 8) 20235* -m64bit-doubles: RX-Opts. (line 15) 20236* -m68000 and related options: M68K-Opts. (line 98) 20237* -m68hc11: M68HC11-Opts. (line 9) 20238* -m68hc12: M68HC11-Opts. (line 14) 20239* -m68hcs12: M68HC11-Opts. (line 21) 20240* -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21) 20241* -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21) 20242* -m[no-]div command line option, M680x0: M68K-Opts. (line 21) 20243* -m[no-]emac command line option, M680x0: M68K-Opts. (line 21) 20244* -m[no-]float command line option, M680x0: M68K-Opts. (line 21) 20245* -m[no-]mac command line option, M680x0: M68K-Opts. (line 21) 20246* -m[no-]usp command line option, M680x0: M68K-Opts. (line 21) 20247* -mall: PDP-11-Options. (line 26) 20248* -mall-enabled command line option, LM32: LM32 Options. (line 30) 20249* -mall-extensions: PDP-11-Options. (line 26) 20250* -mall-opcodes command line option, AVR: AVR Options. (line 68) 20251* -mapcs-26 command line option, ARM: ARM Options. (line 120) 20252* -mapcs-32 command line option, ARM: ARM Options. (line 120) 20253* -mapcs-float command line option, ARM: ARM Options. (line 134) 20254* -mapcs-reentrant command line option, ARM: ARM Options. (line 139) 20255* -marc[5|6|7|8] command line option, ARC: ARC Options. (line 6) 20256* -march= command line option, ARM: ARM Options. (line 59) 20257* -march= command line option, M680x0: M68K-Opts. (line 8) 20258* -march= command line option, TIC6X: TIC6X Options. (line 6) 20259* -march= option, i386: i386-Options. (line 31) 20260* -march= option, s390: s390 Options. (line 25) 20261* -march= option, x86-64: i386-Options. (line 31) 20262* -matomic command line option, TIC6X: TIC6X Options. (line 13) 20263* -matpcs command line option, ARM: ARM Options. (line 126) 20264* -mavxscalar= option, i386: i386-Options. (line 79) 20265* -mavxscalar= option, x86-64: i386-Options. (line 79) 20266* -mbarrel-shift-enabled command line option, LM32: LM32 Options. 20267 (line 12) 20268* -mbig-endian: RX-Opts. (line 20) 20269* -mbreak-enabled command line option, LM32: LM32 Options. (line 27) 20270* -mcis: PDP-11-Options. (line 32) 20271* -mconstant-gp command line option, IA-64: IA-64 Options. (line 6) 20272* -mCPU command line option, Alpha: Alpha Options. (line 6) 20273* -mcpu option, cpu: TIC54X-Opts. (line 15) 20274* -mcpu= command line option, ARM: ARM Options. (line 6) 20275* -mcpu= command line option, Blackfin: Blackfin Options. (line 6) 20276* -mcpu= command line option, M680x0: M68K-Opts. (line 14) 20277* -mcsm: PDP-11-Options. (line 43) 20278* -mdcache-enabled command line option, LM32: LM32 Options. (line 24) 20279* -mdebug command line option, Alpha: Alpha Options. (line 25) 20280* -mdivide-enabled command line option, LM32: LM32 Options. (line 9) 20281* -mdsbt command line option, TIC6X: TIC6X Options. (line 25) 20282* -me option, stderr redirect: TIC54X-Opts. (line 20) 20283* -meis: PDP-11-Options. (line 46) 20284* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 20285* -mesa option, s390: s390 Options. (line 17) 20286* -mf option, far-mode: TIC54X-Opts. (line 8) 20287* -mf11: PDP-11-Options. (line 122) 20288* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 20289* -mfdpic command line option, Blackfin: Blackfin Options. (line 19) 20290* -mfis: PDP-11-Options. (line 51) 20291* -mfloat-abi= command line option, ARM: ARM Options. (line 143) 20292* -mfp-11: PDP-11-Options. (line 56) 20293* -mfpp: PDP-11-Options. (line 56) 20294* -mfpu: PDP-11-Options. (line 56) 20295* -mfpu= command line option, ARM: ARM Options. (line 74) 20296* -micache-enabled command line option, LM32: LM32 Options. (line 21) 20297* -mimplicit-it command line option, ARM: ARM Options. (line 104) 20298* -mip2022 option, IP2K: IP2K-Opts. (line 14) 20299* -mip2022ext option, IP2022: IP2K-Opts. (line 9) 20300* -mj11: PDP-11-Options. (line 126) 20301* -mka11: PDP-11-Options. (line 92) 20302* -mkb11: PDP-11-Options. (line 95) 20303* -mkd11a: PDP-11-Options. (line 98) 20304* -mkd11b: PDP-11-Options. (line 101) 20305* -mkd11d: PDP-11-Options. (line 104) 20306* -mkd11e: PDP-11-Options. (line 107) 20307* -mkd11f: PDP-11-Options. (line 110) 20308* -mkd11h: PDP-11-Options. (line 110) 20309* -mkd11k: PDP-11-Options. (line 114) 20310* -mkd11q: PDP-11-Options. (line 110) 20311* -mkd11z: PDP-11-Options. (line 118) 20312* -mkev11: PDP-11-Options. (line 51) 20313* -mlimited-eis: PDP-11-Options. (line 64) 20314* -mlittle-endian: RX-Opts. (line 26) 20315* -mlong: M68HC11-Opts. (line 32) 20316* -mlong-double: M68HC11-Opts. (line 40) 20317* -mmcu= command line option, AVR: AVR Options. (line 6) 20318* -mmfpt: PDP-11-Options. (line 70) 20319* -mmicrocode: PDP-11-Options. (line 83) 20320* -mmnemonic= option, i386: i386-Options. (line 87) 20321* -mmnemonic= option, x86-64: i386-Options. (line 87) 20322* -mmultiply-enabled command line option, LM32: LM32 Options. (line 6) 20323* -mmutiproc: PDP-11-Options. (line 73) 20324* -mmxps: PDP-11-Options. (line 77) 20325* -mnaked-reg option, i386: i386-Options. (line 99) 20326* -mnaked-reg option, x86-64: i386-Options. (line 99) 20327* -mno-atomic command line option, TIC6X: TIC6X Options. (line 13) 20328* -mno-cis: PDP-11-Options. (line 32) 20329* -mno-csm: PDP-11-Options. (line 43) 20330* -mno-dsbt command line option, TIC6X: TIC6X Options. (line 25) 20331* -mno-eis: PDP-11-Options. (line 46) 20332* -mno-extensions: PDP-11-Options. (line 29) 20333* -mno-fdpic command line option, Blackfin: Blackfin Options. (line 22) 20334* -mno-fis: PDP-11-Options. (line 51) 20335* -mno-fp-11: PDP-11-Options. (line 56) 20336* -mno-fpp: PDP-11-Options. (line 56) 20337* -mno-fpu: PDP-11-Options. (line 56) 20338* -mno-kev11: PDP-11-Options. (line 51) 20339* -mno-limited-eis: PDP-11-Options. (line 64) 20340* -mno-mfpt: PDP-11-Options. (line 70) 20341* -mno-microcode: PDP-11-Options. (line 83) 20342* -mno-mutiproc: PDP-11-Options. (line 73) 20343* -mno-mxps: PDP-11-Options. (line 77) 20344* -mno-pic: PDP-11-Options. (line 11) 20345* -mno-pic command line option, TIC6X: TIC6X Options. (line 48) 20346* -mno-regnames option, s390: s390 Options. (line 35) 20347* -mno-skip-bug command line option, AVR: AVR Options. (line 71) 20348* -mno-spl: PDP-11-Options. (line 80) 20349* -mno-sym32: MIPS Opts. (line 208) 20350* -mno-wrap command line option, AVR: AVR Options. (line 74) 20351* -mnopic command line option, Blackfin: Blackfin Options. (line 22) 20352* -mpic: PDP-11-Options. (line 11) 20353* -mpic command line option, TIC6X: TIC6X Options. (line 48) 20354* -mpid= command line option, TIC6X: TIC6X Options. (line 35) 20355* -mregnames option, s390: s390 Options. (line 32) 20356* -mrelax command line option, V850: V850 Options. (line 63) 20357* -mshort: M68HC11-Opts. (line 27) 20358* -mshort-double: M68HC11-Opts. (line 36) 20359* -msign-extend-enabled command line option, LM32: LM32 Options. 20360 (line 15) 20361* -msmall-data-limit: RX-Opts. (line 42) 20362* -mspl: PDP-11-Options. (line 80) 20363* -msse-check= option, i386: i386-Options. (line 69) 20364* -msse-check= option, x86-64: i386-Options. (line 69) 20365* -msse2avx option, i386: i386-Options. (line 65) 20366* -msse2avx option, x86-64: i386-Options. (line 65) 20367* -msym32: MIPS Opts. (line 208) 20368* -msyntax= option, i386: i386-Options. (line 93) 20369* -msyntax= option, x86-64: i386-Options. (line 93) 20370* -mt11: PDP-11-Options. (line 130) 20371* -mthumb command line option, ARM: ARM Options. (line 95) 20372* -mthumb-interwork command line option, ARM: ARM Options. (line 100) 20373* -mtune= option, i386: i386-Options. (line 57) 20374* -mtune= option, x86-64: i386-Options. (line 57) 20375* -muse-conventional-section-names: RX-Opts. (line 33) 20376* -muse-renesas-section-names: RX-Opts. (line 37) 20377* -muser-enabled command line option, LM32: LM32 Options. (line 18) 20378* -mv850 command line option, V850: V850 Options. (line 23) 20379* -mv850any command line option, V850: V850 Options. (line 41) 20380* -mv850e command line option, V850: V850 Options. (line 29) 20381* -mv850e1 command line option, V850: V850 Options. (line 35) 20382* -mv850e2 command line option, V850: V850 Options. (line 51) 20383* -mv850e2v3 command line option, V850: V850 Options. (line 57) 20384* -mvxworks-pic option, MIPS: MIPS Opts. (line 26) 20385* -mwarn-areg-zero option, s390: s390 Options. (line 38) 20386* -mwarn-deprecated command line option, ARM: ARM Options. (line 169) 20387* -mzarch option, s390: s390 Options. (line 17) 20388* -N command line option, CRIS: CRIS-Opts. (line 57) 20389* -nIp option, M32RX: M32R-Opts. (line 101) 20390* -no-bitinst, M32R2: M32R-Opts. (line 54) 20391* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 20392* -no-mdebug command line option, Alpha: Alpha Options. (line 25) 20393* -no-parallel option, M32RX: M32R-Opts. (line 51) 20394* -no-relax option, i960: Options-i960. (line 66) 20395* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 20396 (line 79) 20397* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 20398* -nocpp ignored (MIPS): MIPS Opts. (line 211) 20399* -noreplace command line option, Alpha: Alpha Options. (line 40) 20400* -o: o. (line 6) 20401* -O option, M32RX: M32R-Opts. (line 59) 20402* -parallel option, M32RX: M32R-Opts. (line 46) 20403* -R: R. (line 6) 20404* -r800 command line option, Z80: Z80 Options. (line 41) 20405* -relax command line option, Alpha: Alpha Options. (line 32) 20406* -replace command line option, Alpha: Alpha Options. (line 40) 20407* -S, ignored on VAX: VAX-Opts. (line 11) 20408* -t, ignored on VAX: VAX-Opts. (line 36) 20409* -T, ignored on VAX: VAX-Opts. (line 11) 20410* -v: v. (line 6) 20411* -V, redundant on VAX: VAX-Opts. (line 22) 20412* -version: v. (line 6) 20413* -W: W. (line 11) 20414* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line 65) 20415* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 20416* -Wnp option, M32RX: M32R-Opts. (line 83) 20417* -Wnuh option, M32RX: M32R-Opts. (line 117) 20418* -Wp option, M32RX: M32R-Opts. (line 75) 20419* -wsigned_overflow command line option, V850: V850 Options. (line 9) 20420* -Wuh option, M32RX: M32R-Opts. (line 114) 20421* -wunsigned_overflow command line option, V850: V850 Options. 20422 (line 16) 20423* -x command line option, MMIX: MMIX-Opts. (line 44) 20424* -z80 command line option, Z80: Z80 Options. (line 8) 20425* -z8001 command line option, Z8000: Z8000 Options. (line 6) 20426* -z8002 command line option, Z8000: Z8000 Options. (line 9) 20427* . (symbol): Dot. (line 6) 20428* .2byte directive, ARM: ARM Directives. (line 6) 20429* .4byte directive, ARM: ARM Directives. (line 6) 20430* .8byte directive, ARM: ARM Directives. (line 6) 20431* .align directive, ARM: ARM Directives. (line 11) 20432* .arch directive, ARM: ARM Directives. (line 18) 20433* .arch directive, TIC6X: TIC6X Directives. (line 10) 20434* .arch_extension directive, ARM: ARM Directives. (line 25) 20435* .arm directive, ARM: ARM Directives. (line 34) 20436* .atomic directive, TIC6X: TIC6X Directives. (line 13) 20437* .big directive, M32RX: M32R-Directives. (line 88) 20438* .bss directive, ARM: ARM Directives. (line 42) 20439* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 17) 20440* .cantunwind directive, ARM: ARM Directives. (line 45) 20441* .code directive, ARM: ARM Directives. (line 49) 20442* .cpu directive, ARM: ARM Directives. (line 53) 20443* .dn and .qn directives, ARM: ARM Directives. (line 60) 20444* .eabi_attribute directive, ARM: ARM Directives. (line 83) 20445* .even directive, ARM: ARM Directives. (line 111) 20446* .extend directive, ARM: ARM Directives. (line 114) 20447* .fnend directive, ARM: ARM Directives. (line 120) 20448* .fnstart directive, ARM: ARM Directives. (line 129) 20449* .force_thumb directive, ARM: ARM Directives. (line 132) 20450* .fpu directive, ARM: ARM Directives. (line 136) 20451* .global: MIPS insn. (line 12) 20452* .handlerdata directive, ARM: ARM Directives. (line 140) 20453* .insn: MIPS insn. (line 6) 20454* .insn directive, s390: s390 Directives. (line 11) 20455* .inst directive, ARM: ARM Directives. (line 149) 20456* .ldouble directive, ARM: ARM Directives. (line 114) 20457* .little directive, M32RX: M32R-Directives. (line 82) 20458* .long directive, s390: s390 Directives. (line 16) 20459* .ltorg directive, ARM: ARM Directives. (line 159) 20460* .ltorg directive, s390: s390 Directives. (line 88) 20461* .m32r directive, M32R: M32R-Directives. (line 66) 20462* .m32r2 directive, M32R2: M32R-Directives. (line 77) 20463* .m32rx directive, M32RX: M32R-Directives. (line 72) 20464* .machine directive, s390: s390 Directives. (line 93) 20465* .movsp directive, ARM: ARM Directives. (line 173) 20466* .noatomic directive, TIC6X: TIC6X Directives. (line 13) 20467* .nocmp directive, TIC6X: TIC6X Directives. (line 28) 20468* .o: Object. (line 6) 20469* .object_arch directive, ARM: ARM Directives. (line 178) 20470* .packed directive, ARM: ARM Directives. (line 184) 20471* .pad directive, ARM: ARM Directives. (line 37) 20472* .param on HPPA: HPPA Directives. (line 19) 20473* .personality directive, ARM: ARM Directives. (line 194) 20474* .personalityindex directive, ARM: ARM Directives. (line 197) 20475* .pool directive, ARM: ARM Directives. (line 201) 20476* .quad directive, s390: s390 Directives. (line 16) 20477* .req directive, ARM: ARM Directives. (line 204) 20478* .save directive, ARM: ARM Directives. (line 209) 20479* .secrel32 directive, ARM: ARM Directives. (line 247) 20480* .set arch=CPU: MIPS ISA. (line 18) 20481* .set autoextend: MIPS autoextend. (line 6) 20482* .set doublefloat: MIPS floating-point. (line 12) 20483* .set dsp: MIPS ASE instruction generation overrides. 20484 (line 21) 20485* .set dspr2: MIPS ASE instruction generation overrides. 20486 (line 26) 20487* .set hardfloat: MIPS floating-point. (line 6) 20488* .set mdmx: MIPS ASE instruction generation overrides. 20489 (line 16) 20490* .set mips3d: MIPS ASE instruction generation overrides. 20491 (line 6) 20492* .set mipsN: MIPS ISA. (line 6) 20493* .set mt: MIPS ASE instruction generation overrides. 20494 (line 32) 20495* .set noautoextend: MIPS autoextend. (line 6) 20496* .set nodsp: MIPS ASE instruction generation overrides. 20497 (line 21) 20498* .set nodspr2: MIPS ASE instruction generation overrides. 20499 (line 26) 20500* .set nomdmx: MIPS ASE instruction generation overrides. 20501 (line 16) 20502* .set nomips3d: MIPS ASE instruction generation overrides. 20503 (line 6) 20504* .set nomt: MIPS ASE instruction generation overrides. 20505 (line 32) 20506* .set nosmartmips: MIPS ASE instruction generation overrides. 20507 (line 11) 20508* .set nosym32: MIPS symbol sizes. (line 6) 20509* .set pop: MIPS option stack. (line 6) 20510* .set push: MIPS option stack. (line 6) 20511* .set singlefloat: MIPS floating-point. (line 12) 20512* .set smartmips: MIPS ASE instruction generation overrides. 20513 (line 11) 20514* .set softfloat: MIPS floating-point. (line 6) 20515* .set sym32: MIPS symbol sizes. (line 6) 20516* .setfp directive, ARM: ARM Directives. (line 233) 20517* .short directive, s390: s390 Directives. (line 16) 20518* .syntax directive, ARM: ARM Directives. (line 252) 20519* .thumb directive, ARM: ARM Directives. (line 256) 20520* .thumb_func directive, ARM: ARM Directives. (line 259) 20521* .thumb_set directive, ARM: ARM Directives. (line 270) 20522* .unreq directive, ARM: ARM Directives. (line 277) 20523* .unwind_raw directive, ARM: ARM Directives. (line 288) 20524* .v850 directive, V850: V850 Directives. (line 14) 20525* .v850e directive, V850: V850 Directives. (line 20) 20526* .v850e1 directive, V850: V850 Directives. (line 26) 20527* .v850e2 directive, V850: V850 Directives. (line 32) 20528* .v850e2v3 directive, V850: V850 Directives. (line 38) 20529* .vsave directive, ARM: ARM Directives. (line 295) 20530* .z8001: Z8000 Directives. (line 11) 20531* .z8002: Z8000 Directives. (line 15) 20532* 16-bit code, i386: i386-16bit. (line 6) 20533* 2byte directive, ARC: ARC Directives. (line 9) 20534* 3byte directive, ARC: ARC Directives. (line 12) 20535* 3DNow!, i386: i386-SIMD. (line 6) 20536* 3DNow!, x86-64: i386-SIMD. (line 6) 20537* 430 support: MSP430-Dependent. (line 6) 20538* 4byte directive, ARC: ARC Directives. (line 15) 20539* : (label): Statements. (line 30) 20540* @word modifier, D10V: D10V-Word. (line 6) 20541* \" (doublequote character): Strings. (line 43) 20542* \\ (\ character): Strings. (line 40) 20543* \b (backspace character): Strings. (line 15) 20544* \DDD (octal character code): Strings. (line 30) 20545* \f (formfeed character): Strings. (line 18) 20546* \n (newline character): Strings. (line 21) 20547* \r (carriage return character): Strings. (line 24) 20548* \t (tab): Strings. (line 27) 20549* \XD... (hex character code): Strings. (line 36) 20550* _ opcode prefix: Xtensa Opcodes. (line 9) 20551* a.out: Object. (line 6) 20552* a.out symbol attributes: a.out Symbols. (line 6) 20553* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 20554* ABI options, SH64: SH64 Options. (line 29) 20555* abort directive: Abort. (line 6) 20556* ABORT directive: ABORT (COFF). (line 6) 20557* absolute section: Ld Sections. (line 29) 20558* absolute-literals directive: Absolute Literals Directive. 20559 (line 6) 20560* ADDI instructions, relaxation: Xtensa Immediate Relaxation. 20561 (line 43) 20562* addition, permitted arguments: Infix Ops. (line 44) 20563* addresses: Expressions. (line 6) 20564* addresses, format of: Secs Background. (line 68) 20565* addressing modes, D10V: D10V-Addressing. (line 6) 20566* addressing modes, D30V: D30V-Addressing. (line 6) 20567* addressing modes, H8/300: H8/300-Addressing. (line 6) 20568* addressing modes, M680x0: M68K-Syntax. (line 21) 20569* addressing modes, M68HC11: M68HC11-Syntax. (line 17) 20570* addressing modes, SH: SH-Addressing. (line 6) 20571* addressing modes, SH64: SH64-Addressing. (line 6) 20572* addressing modes, Z8000: Z8000-Addressing. (line 6) 20573* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 20574* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35) 20575* advancing location counter: Org. (line 6) 20576* align directive: Align. (line 6) 20577* align directive, SPARC: Sparc-Directives. (line 9) 20578* align directive, TIC54X: TIC54X-Directives. (line 6) 20579* alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 20580* alignment of branch targets: Xtensa Automatic Alignment. 20581 (line 6) 20582* alignment of LOOP instructions: Xtensa Automatic Alignment. 20583 (line 6) 20584* Alpha floating point (IEEE): Alpha Floating Point. 20585 (line 6) 20586* Alpha line comment character: Alpha-Chars. (line 6) 20587* Alpha line separator: Alpha-Chars. (line 8) 20588* Alpha notes: Alpha Notes. (line 6) 20589* Alpha options: Alpha Options. (line 6) 20590* Alpha registers: Alpha-Regs. (line 6) 20591* Alpha relocations: Alpha-Relocs. (line 6) 20592* Alpha support: Alpha-Dependent. (line 6) 20593* Alpha Syntax: Alpha Options. (line 61) 20594* Alpha-only directives: Alpha Directives. (line 10) 20595* altered difference tables: Word. (line 12) 20596* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 20597* ARC floating point (IEEE): ARC Floating Point. (line 6) 20598* ARC machine directives: ARC Directives. (line 6) 20599* ARC opcodes: ARC Opcodes. (line 6) 20600* ARC options (none): ARC Options. (line 6) 20601* ARC register names: ARC-Regs. (line 6) 20602* ARC special characters: ARC-Chars. (line 6) 20603* ARC support: ARC-Dependent. (line 6) 20604* arc5 arc5, ARC: ARC Options. (line 10) 20605* arc6 arc6, ARC: ARC Options. (line 13) 20606* arc7 arc7, ARC: ARC Options. (line 21) 20607* arc8 arc8, ARC: ARC Options. (line 24) 20608* arch directive, i386: i386-Arch. (line 6) 20609* arch directive, M680x0: M68K-Directives. (line 22) 20610* arch directive, x86-64: i386-Arch. (line 6) 20611* architecture options, i960: Options-i960. (line 6) 20612* architecture options, IP2022: IP2K-Opts. (line 9) 20613* architecture options, IP2K: IP2K-Opts. (line 14) 20614* architecture options, M16C: M32C-Opts. (line 12) 20615* architecture options, M32C: M32C-Opts. (line 9) 20616* architecture options, M32R: M32R-Opts. (line 21) 20617* architecture options, M32R2: M32R-Opts. (line 17) 20618* architecture options, M32RX: M32R-Opts. (line 9) 20619* architecture options, M680x0: M68K-Opts. (line 98) 20620* Architecture variant option, CRIS: CRIS-Opts. (line 33) 20621* architectures, PowerPC: PowerPC-Opts. (line 6) 20622* architectures, SCORE: SCORE-Opts. (line 6) 20623* architectures, SPARC: Sparc-Opts. (line 6) 20624* arguments for addition: Infix Ops. (line 44) 20625* arguments for subtraction: Infix Ops. (line 49) 20626* arguments in expressions: Arguments. (line 6) 20627* arithmetic functions: Operators. (line 6) 20628* arithmetic operands: Arguments. (line 6) 20629* ARM data relocations: ARM-Relocations. (line 6) 20630* ARM floating point (IEEE): ARM Floating Point. (line 6) 20631* ARM identifiers: ARM-Chars. (line 15) 20632* ARM immediate character: ARM-Chars. (line 13) 20633* ARM line comment character: ARM-Chars. (line 6) 20634* ARM line separator: ARM-Chars. (line 10) 20635* ARM machine directives: ARM Directives. (line 6) 20636* ARM opcodes: ARM Opcodes. (line 6) 20637* ARM options (none): ARM Options. (line 6) 20638* ARM register names: ARM-Regs. (line 6) 20639* ARM support: ARM-Dependent. (line 6) 20640* ascii directive: Ascii. (line 6) 20641* asciz directive: Asciz. (line 6) 20642* asg directive, TIC54X: TIC54X-Directives. (line 20) 20643* assembler bugs, reporting: Bug Reporting. (line 6) 20644* assembler crash: Bug Criteria. (line 9) 20645* assembler directive .3byte, RX: RX-Directives. (line 9) 20646* assembler directive .arch, CRIS: CRIS-Pseudos. (line 45) 20647* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 20648* assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 20649* assembler directive .interrupt, M68HC11: M68HC11-Directives. 20650 (line 26) 20651* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 20652* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 20653* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 17) 20654* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 20655* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 131) 20656* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 97) 20657* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 131) 20658* assembler directive GREG, MMIX: MMIX-Pseudos. (line 50) 20659* assembler directive IS, MMIX: MMIX-Pseudos. (line 42) 20660* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 20661* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 28) 20662* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 108) 20663* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 120) 20664* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 108) 20665* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 108) 20666* assembler directives, CRIS: CRIS-Pseudos. (line 6) 20667* assembler directives, M68HC11: M68HC11-Directives. (line 6) 20668* assembler directives, M68HC12: M68HC11-Directives. (line 6) 20669* assembler directives, MMIX: MMIX-Pseudos. (line 6) 20670* assembler directives, RX: RX-Directives. (line 6) 20671* assembler internal logic error: As Sections. (line 13) 20672* assembler version: v. (line 6) 20673* assembler, and linker: Secs Background. (line 10) 20674* assembly listings, enabling: a. (line 6) 20675* assigning values to symbols <1>: Setting Symbols. (line 6) 20676* assigning values to symbols: Equ. (line 6) 20677* atmp directive, i860: Directives-i860. (line 16) 20678* att_syntax pseudo op, i386: i386-Syntax. (line 6) 20679* att_syntax pseudo op, x86-64: i386-Syntax. (line 6) 20680* attributes, symbol: Symbol Attributes. (line 6) 20681* auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 20682* auxiliary symbol information, COFF: Dim. (line 6) 20683* Av7: Sparc-Opts. (line 25) 20684* AVR line comment character: AVR-Chars. (line 6) 20685* AVR line separator: AVR-Chars. (line 10) 20686* AVR modifiers: AVR-Modifiers. (line 6) 20687* AVR opcode summary: AVR Opcodes. (line 6) 20688* AVR options (none): AVR Options. (line 6) 20689* AVR register names: AVR-Regs. (line 6) 20690* AVR support: AVR-Dependent. (line 6) 20691* backslash (\\): Strings. (line 40) 20692* backspace (\b): Strings. (line 15) 20693* balign directive: Balign. (line 6) 20694* balignl directive: Balign. (line 27) 20695* balignw directive: Balign. (line 27) 20696* bes directive, TIC54X: TIC54X-Directives. (line 196) 20697* big endian output, MIPS: Overview. (line 693) 20698* big endian output, PJ: Overview. (line 600) 20699* big-endian output, MIPS: MIPS Opts. (line 13) 20700* big-endian output, TIC6X: TIC6X Options. (line 58) 20701* bignums: Bignums. (line 6) 20702* binary constants, TIC54X: TIC54X-Constants. (line 8) 20703* binary files, including: Incbin. (line 6) 20704* binary integers: Integers. (line 6) 20705* bit names, IA-64: IA-64-Bits. (line 6) 20706* bitfields, not supported on VAX: VAX-no. (line 6) 20707* Blackfin directives: Blackfin Directives. (line 6) 20708* Blackfin options (none): Blackfin Options. (line 6) 20709* Blackfin support: Blackfin-Dependent. (line 6) 20710* Blackfin syntax: Blackfin Syntax. (line 6) 20711* block: Z8000 Directives. (line 55) 20712* branch improvement, M680x0: M68K-Branch. (line 6) 20713* branch improvement, M68HC11: M68HC11-Branch. (line 6) 20714* branch improvement, VAX: VAX-branch. (line 6) 20715* branch instructions, relaxation: Xtensa Branch Relaxation. 20716 (line 6) 20717* branch recording, i960: Options-i960. (line 22) 20718* branch statistics table, i960: Options-i960. (line 40) 20719* branch target alignment: Xtensa Automatic Alignment. 20720 (line 6) 20721* break directive, TIC54X: TIC54X-Directives. (line 143) 20722* BSD syntax: PDP-11-Syntax. (line 6) 20723* bss directive, i960: Directives-i960. (line 6) 20724* bss directive, TIC54X: TIC54X-Directives. (line 29) 20725* bss section <1>: Ld Sections. (line 20) 20726* bss section: bss. (line 6) 20727* bug criteria: Bug Criteria. (line 6) 20728* bug reports: Bug Reporting. (line 6) 20729* bugs in assembler: Reporting Bugs. (line 6) 20730* Built-in symbols, CRIS: CRIS-Symbols. (line 6) 20731* builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 20732* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 20733* bus lock prefixes, i386: i386-Prefixes. (line 36) 20734* bval: Z8000 Directives. (line 30) 20735* byte directive: Byte. (line 6) 20736* byte directive, TIC54X: TIC54X-Directives. (line 36) 20737* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 20738* c_mode directive, TIC54X: TIC54X-Directives. (line 51) 20739* call instructions, i386: i386-Mnemonics. (line 56) 20740* call instructions, relaxation: Xtensa Call Relaxation. 20741 (line 6) 20742* call instructions, x86-64: i386-Mnemonics. (line 56) 20743* callj, i960 pseudo-opcode: callj-i960. (line 6) 20744* carriage return (\r): Strings. (line 24) 20745* case sensitivity, Z80: Z80-Case. (line 6) 20746* cfi_endproc directive: CFI directives. (line 26) 20747* cfi_sections directive: CFI directives. (line 6) 20748* cfi_startproc directive: CFI directives. (line 16) 20749* char directive, TIC54X: TIC54X-Directives. (line 36) 20750* character constant, Z80: Z80-Chars. (line 13) 20751* character constants: Characters. (line 6) 20752* character escape codes: Strings. (line 15) 20753* character escapes, Z80: Z80-Chars. (line 11) 20754* character, single: Chars. (line 6) 20755* characters used in symbols: Symbol Intro. (line 6) 20756* clink directive, TIC54X: TIC54X-Directives. (line 45) 20757* code16 directive, i386: i386-16bit. (line 6) 20758* code16gcc directive, i386: i386-16bit. (line 6) 20759* code32 directive, i386: i386-16bit. (line 6) 20760* code64 directive, i386: i386-16bit. (line 6) 20761* code64 directive, x86-64: i386-16bit. (line 6) 20762* COFF auxiliary symbol information: Dim. (line 6) 20763* COFF structure debugging: Tag. (line 6) 20764* COFF symbol attributes: COFF Symbols. (line 6) 20765* COFF symbol descriptor: Desc. (line 6) 20766* COFF symbol storage class: Scl. (line 6) 20767* COFF symbol type: Type. (line 11) 20768* COFF symbols, debugging: Def. (line 6) 20769* COFF value attribute: Val. (line 6) 20770* COMDAT: Linkonce. (line 6) 20771* comm directive: Comm. (line 6) 20772* command line conventions: Command Line. (line 6) 20773* command line options, V850: V850 Options. (line 9) 20774* command-line options ignored, VAX: VAX-Opts. (line 6) 20775* comments: Comments. (line 6) 20776* comments, M680x0: M68K-Chars. (line 6) 20777* comments, removed by preprocessor: Preprocessing. (line 11) 20778* common directive, SPARC: Sparc-Directives. (line 12) 20779* common sections: Linkonce. (line 6) 20780* common variable storage: bss. (line 6) 20781* compare and jump expansions, i960: Compare-and-branch-i960. 20782 (line 13) 20783* compare/branch instructions, i960: Compare-and-branch-i960. 20784 (line 6) 20785* comparison expressions: Infix Ops. (line 55) 20786* conditional assembly: If. (line 6) 20787* constant, single character: Chars. (line 6) 20788* constants: Constants. (line 6) 20789* constants, bignum: Bignums. (line 6) 20790* constants, character: Characters. (line 6) 20791* constants, converted by preprocessor: Preprocessing. (line 14) 20792* constants, floating point: Flonums. (line 6) 20793* constants, integer: Integers. (line 6) 20794* constants, number: Numbers. (line 6) 20795* constants, Sparc: Sparc-Constants. (line 6) 20796* constants, string: Strings. (line 6) 20797* constants, TIC54X: TIC54X-Constants. (line 6) 20798* conversion instructions, i386: i386-Mnemonics. (line 37) 20799* conversion instructions, x86-64: i386-Mnemonics. (line 37) 20800* coprocessor wait, i386: i386-Prefixes. (line 40) 20801* copy directive, TIC54X: TIC54X-Directives. (line 54) 20802* cpu directive, M680x0: M68K-Directives. (line 30) 20803* CR16 Operand Qualifiers: CR16 Operand Qualifiers. 20804 (line 6) 20805* CR16 support: CR16-Dependent. (line 6) 20806* crash of assembler: Bug Criteria. (line 9) 20807* CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9) 20808* CRIS --emulation=criself command line option: CRIS-Opts. (line 9) 20809* CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 33) 20810* CRIS --mul-bug-abort command line option: CRIS-Opts. (line 61) 20811* CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 61) 20812* CRIS --no-underscore command line option: CRIS-Opts. (line 15) 20813* CRIS --pic command line option: CRIS-Opts. (line 27) 20814* CRIS --underscore command line option: CRIS-Opts. (line 15) 20815* CRIS -N command line option: CRIS-Opts. (line 57) 20816* CRIS architecture variant option: CRIS-Opts. (line 33) 20817* CRIS assembler directive .arch: CRIS-Pseudos. (line 45) 20818* CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 20819* CRIS assembler directive .syntax: CRIS-Pseudos. (line 17) 20820* CRIS assembler directives: CRIS-Pseudos. (line 6) 20821* CRIS built-in symbols: CRIS-Symbols. (line 6) 20822* CRIS instruction expansion: CRIS-Expand. (line 6) 20823* CRIS line comment characters: CRIS-Chars. (line 6) 20824* CRIS options: CRIS-Opts. (line 6) 20825* CRIS position-independent code: CRIS-Opts. (line 27) 20826* CRIS pseudo-op .arch: CRIS-Pseudos. (line 45) 20827* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 20828* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 17) 20829* CRIS pseudo-ops: CRIS-Pseudos. (line 6) 20830* CRIS register names: CRIS-Regs. (line 6) 20831* CRIS support: CRIS-Dependent. (line 6) 20832* CRIS symbols in position-independent code: CRIS-Pic. (line 6) 20833* ctbp register, V850: V850-Regs. (line 131) 20834* ctoff pseudo-op, V850: V850 Opcodes. (line 111) 20835* ctpc register, V850: V850-Regs. (line 119) 20836* ctpsw register, V850: V850-Regs. (line 122) 20837* current address: Dot. (line 6) 20838* current address, advancing: Org. (line 6) 20839* D10V @word modifier: D10V-Word. (line 6) 20840* D10V addressing modes: D10V-Addressing. (line 6) 20841* D10V floating point: D10V-Float. (line 6) 20842* D10V line comment character: D10V-Chars. (line 6) 20843* D10V opcode summary: D10V-Opcodes. (line 6) 20844* D10V optimization: Overview. (line 472) 20845* D10V options: D10V-Opts. (line 6) 20846* D10V registers: D10V-Regs. (line 6) 20847* D10V size modifiers: D10V-Size. (line 6) 20848* D10V sub-instruction ordering: D10V-Chars. (line 6) 20849* D10V sub-instructions: D10V-Subs. (line 6) 20850* D10V support: D10V-Dependent. (line 6) 20851* D10V syntax: D10V-Syntax. (line 6) 20852* D30V addressing modes: D30V-Addressing. (line 6) 20853* D30V floating point: D30V-Float. (line 6) 20854* D30V Guarded Execution: D30V-Guarded. (line 6) 20855* D30V line comment character: D30V-Chars. (line 6) 20856* D30V nops: Overview. (line 480) 20857* D30V nops after 32-bit multiply: Overview. (line 483) 20858* D30V opcode summary: D30V-Opcodes. (line 6) 20859* D30V optimization: Overview. (line 477) 20860* D30V options: D30V-Opts. (line 6) 20861* D30V registers: D30V-Regs. (line 6) 20862* D30V size modifiers: D30V-Size. (line 6) 20863* D30V sub-instruction ordering: D30V-Chars. (line 6) 20864* D30V sub-instructions: D30V-Subs. (line 6) 20865* D30V support: D30V-Dependent. (line 6) 20866* D30V syntax: D30V-Syntax. (line 6) 20867* data alignment on SPARC: Sparc-Aligned-Data. (line 6) 20868* data and text sections, joining: R. (line 6) 20869* data directive: Data. (line 6) 20870* data directive, TIC54X: TIC54X-Directives. (line 61) 20871* data relocations, ARM: ARM-Relocations. (line 6) 20872* data section: Ld Sections. (line 9) 20873* data1 directive, M680x0: M68K-Directives. (line 9) 20874* data2 directive, M680x0: M68K-Directives. (line 12) 20875* datalabel, SH64: SH64-Addressing. (line 16) 20876* dbpc register, V850: V850-Regs. (line 125) 20877* dbpsw register, V850: V850-Regs. (line 128) 20878* debuggers, and symbol order: Symbols. (line 10) 20879* debugging COFF symbols: Def. (line 6) 20880* DEC syntax: PDP-11-Syntax. (line 6) 20881* decimal integers: Integers. (line 12) 20882* def directive: Def. (line 6) 20883* def directive, TIC54X: TIC54X-Directives. (line 103) 20884* density instructions: Density Instructions. 20885 (line 6) 20886* dependency tracking: MD. (line 6) 20887* deprecated directives: Deprecated. (line 6) 20888* desc directive: Desc. (line 6) 20889* descriptor, of a.out symbol: Symbol Desc. (line 6) 20890* dfloat directive, VAX: VAX-directives. (line 10) 20891* difference tables altered: Word. (line 12) 20892* difference tables, warning: K. (line 6) 20893* differences, mmixal: MMIX-mmixal. (line 6) 20894* dim directive: Dim. (line 6) 20895* directives and instructions: Statements. (line 19) 20896* directives for PowerPC: PowerPC-Pseudo. (line 6) 20897* directives for SCORE: SCORE-Pseudo. (line 6) 20898* directives, Blackfin: Blackfin Directives. (line 6) 20899* directives, M32R: M32R-Directives. (line 6) 20900* directives, M680x0: M68K-Directives. (line 6) 20901* directives, machine independent: Pseudo Ops. (line 6) 20902* directives, Xtensa: Xtensa Directives. (line 6) 20903* directives, Z8000: Z8000 Directives. (line 6) 20904* Disable floating-point instructions: MIPS floating-point. (line 6) 20905* Disable single-precision floating-point operations: MIPS floating-point. 20906 (line 12) 20907* displacement sizing character, VAX: VAX-operands. (line 12) 20908* dollar local symbols: Symbol Names. (line 105) 20909* dot (symbol): Dot. (line 6) 20910* double directive: Double. (line 6) 20911* double directive, i386: i386-Float. (line 14) 20912* double directive, M680x0: M68K-Float. (line 14) 20913* double directive, M68HC11: M68HC11-Float. (line 14) 20914* double directive, RX: RX-Float. (line 11) 20915* double directive, TIC54X: TIC54X-Directives. (line 64) 20916* double directive, VAX: VAX-float. (line 15) 20917* double directive, x86-64: i386-Float. (line 14) 20918* doublequote (\"): Strings. (line 43) 20919* drlist directive, TIC54X: TIC54X-Directives. (line 73) 20920* drnolist directive, TIC54X: TIC54X-Directives. (line 73) 20921* dual directive, i860: Directives-i860. (line 6) 20922* ECOFF sections: MIPS Object. (line 6) 20923* ecr register, V850: V850-Regs. (line 113) 20924* eight-byte integer: Quad. (line 9) 20925* eipc register, V850: V850-Regs. (line 101) 20926* eipsw register, V850: V850-Regs. (line 104) 20927* eject directive: Eject. (line 6) 20928* ELF symbol type: Type. (line 22) 20929* else directive: Else. (line 6) 20930* elseif directive: Elseif. (line 6) 20931* empty expressions: Empty Exprs. (line 6) 20932* emsg directive, TIC54X: TIC54X-Directives. (line 77) 20933* emulation: Overview. (line 796) 20934* encoding options, i386: i386-Mnemonics. (line 32) 20935* encoding options, x86-64: i386-Mnemonics. (line 32) 20936* end directive: End. (line 6) 20937* enddual directive, i860: Directives-i860. (line 11) 20938* endef directive: Endef. (line 6) 20939* endfunc directive: Endfunc. (line 6) 20940* endianness, MIPS: Overview. (line 693) 20941* endianness, PJ: Overview. (line 600) 20942* endif directive: Endif. (line 6) 20943* endloop directive, TIC54X: TIC54X-Directives. (line 143) 20944* endm directive: Macro. (line 138) 20945* endm directive, TIC54X: TIC54X-Directives. (line 153) 20946* endstruct directive, TIC54X: TIC54X-Directives. (line 216) 20947* endunion directive, TIC54X: TIC54X-Directives. (line 250) 20948* environment settings, TIC54X: TIC54X-Env. (line 6) 20949* EOF, newline must precede: Statements. (line 13) 20950* ep register, V850: V850-Regs. (line 95) 20951* equ directive: Equ. (line 6) 20952* equ directive, TIC54X: TIC54X-Directives. (line 191) 20953* equiv directive: Equiv. (line 6) 20954* eqv directive: Eqv. (line 6) 20955* err directive: Err. (line 6) 20956* error directive: Error. (line 6) 20957* error messages: Errors. (line 6) 20958* error on valid input: Bug Criteria. (line 12) 20959* errors, caused by warnings: W. (line 16) 20960* errors, continuing after: Z. (line 6) 20961* ESA/390 floating point (IEEE): ESA/390 Floating Point. 20962 (line 6) 20963* ESA/390 support: ESA/390-Dependent. (line 6) 20964* ESA/390 Syntax: ESA/390 Options. (line 8) 20965* ESA/390-only directives: ESA/390 Directives. (line 12) 20966* escape codes, character: Strings. (line 15) 20967* eval directive, TIC54X: TIC54X-Directives. (line 24) 20968* even: Z8000 Directives. (line 58) 20969* even directive, M680x0: M68K-Directives. (line 15) 20970* even directive, TIC54X: TIC54X-Directives. (line 6) 20971* exitm directive: Macro. (line 141) 20972* expr (internal section): As Sections. (line 17) 20973* expression arguments: Arguments. (line 6) 20974* expressions: Expressions. (line 6) 20975* expressions, comparison: Infix Ops. (line 55) 20976* expressions, empty: Empty Exprs. (line 6) 20977* expressions, integer: Integer Exprs. (line 6) 20978* extAuxRegister directive, ARC: ARC Directives. (line 18) 20979* extCondCode directive, ARC: ARC Directives. (line 41) 20980* extCoreRegister directive, ARC: ARC Directives. (line 53) 20981* extend directive M680x0: M68K-Float. (line 17) 20982* extend directive M68HC11: M68HC11-Float. (line 17) 20983* extended directive, i960: Directives-i960. (line 13) 20984* extern directive: Extern. (line 6) 20985* extInstruction directive, ARC: ARC Directives. (line 78) 20986* fail directive: Fail. (line 6) 20987* far_mode directive, TIC54X: TIC54X-Directives. (line 82) 20988* faster processing (-f): f. (line 6) 20989* fatal signal: Bug Criteria. (line 9) 20990* fclist directive, TIC54X: TIC54X-Directives. (line 87) 20991* fcnolist directive, TIC54X: TIC54X-Directives. (line 87) 20992* fepc register, V850: V850-Regs. (line 107) 20993* fepsw register, V850: V850-Regs. (line 110) 20994* ffloat directive, VAX: VAX-directives. (line 14) 20995* field directive, TIC54X: TIC54X-Directives. (line 91) 20996* file directive: File. (line 6) 20997* file directive, MSP 430: MSP430 Directives. (line 6) 20998* file name, logical: File. (line 13) 20999* files, including: Include. (line 6) 21000* files, input: Input Files. (line 6) 21001* fill directive: Fill. (line 6) 21002* filling memory <1>: Skip. (line 6) 21003* filling memory: Space. (line 6) 21004* FLIX syntax: Xtensa Syntax. (line 6) 21005* float directive: Float. (line 6) 21006* float directive, i386: i386-Float. (line 14) 21007* float directive, M680x0: M68K-Float. (line 11) 21008* float directive, M68HC11: M68HC11-Float. (line 11) 21009* float directive, RX: RX-Float. (line 8) 21010* float directive, TIC54X: TIC54X-Directives. (line 64) 21011* float directive, VAX: VAX-float. (line 15) 21012* float directive, x86-64: i386-Float. (line 14) 21013* floating point numbers: Flonums. (line 6) 21014* floating point numbers (double): Double. (line 6) 21015* floating point numbers (single) <1>: Float. (line 6) 21016* floating point numbers (single): Single. (line 6) 21017* floating point, Alpha (IEEE): Alpha Floating Point. 21018 (line 6) 21019* floating point, ARC (IEEE): ARC Floating Point. (line 6) 21020* floating point, ARM (IEEE): ARM Floating Point. (line 6) 21021* floating point, D10V: D10V-Float. (line 6) 21022* floating point, D30V: D30V-Float. (line 6) 21023* floating point, ESA/390 (IEEE): ESA/390 Floating Point. 21024 (line 6) 21025* floating point, H8/300 (IEEE): H8/300 Floating Point. 21026 (line 6) 21027* floating point, HPPA (IEEE): HPPA Floating Point. (line 6) 21028* floating point, i386: i386-Float. (line 6) 21029* floating point, i960 (IEEE): Floating Point-i960. (line 6) 21030* floating point, M680x0: M68K-Float. (line 6) 21031* floating point, M68HC11: M68HC11-Float. (line 6) 21032* floating point, MSP 430 (IEEE): MSP430 Floating Point. 21033 (line 6) 21034* floating point, RX: RX-Float. (line 6) 21035* floating point, s390: s390 Floating Point. (line 6) 21036* floating point, SH (IEEE): SH Floating Point. (line 6) 21037* floating point, SPARC (IEEE): Sparc-Float. (line 6) 21038* floating point, V850 (IEEE): V850 Floating Point. (line 6) 21039* floating point, VAX: VAX-float. (line 6) 21040* floating point, x86-64: i386-Float. (line 6) 21041* floating point, Z80: Z80 Floating Point. (line 6) 21042* flonums: Flonums. (line 6) 21043* format of error messages: Errors. (line 24) 21044* format of warning messages: Errors. (line 12) 21045* formfeed (\f): Strings. (line 18) 21046* func directive: Func. (line 6) 21047* functions, in expressions: Operators. (line 6) 21048* gbr960, i960 postprocessor: Options-i960. (line 40) 21049* gfloat directive, VAX: VAX-directives. (line 18) 21050* global: Z8000 Directives. (line 21) 21051* global directive: Global. (line 6) 21052* global directive, TIC54X: TIC54X-Directives. (line 103) 21053* gp register, MIPS: MIPS Object. (line 11) 21054* gp register, V850: V850-Regs. (line 17) 21055* grouping data: Sub-Sections. (line 6) 21056* H8/300 addressing modes: H8/300-Addressing. (line 6) 21057* H8/300 floating point (IEEE): H8/300 Floating Point. 21058 (line 6) 21059* H8/300 line comment character: H8/300-Chars. (line 6) 21060* H8/300 line separator: H8/300-Chars. (line 8) 21061* H8/300 machine directives (none): H8/300 Directives. (line 6) 21062* H8/300 opcode summary: H8/300 Opcodes. (line 6) 21063* H8/300 options: H8/300 Options. (line 6) 21064* H8/300 registers: H8/300-Regs. (line 6) 21065* H8/300 size suffixes: H8/300 Opcodes. (line 163) 21066* H8/300 support: H8/300-Dependent. (line 6) 21067* H8/300H, assembling for: H8/300 Directives. (line 8) 21068* half directive, ARC: ARC Directives. (line 156) 21069* half directive, SPARC: Sparc-Directives. (line 17) 21070* half directive, TIC54X: TIC54X-Directives. (line 111) 21071* hex character code (\XD...): Strings. (line 36) 21072* hexadecimal integers: Integers. (line 15) 21073* hexadecimal prefix, Z80: Z80-Chars. (line 8) 21074* hfloat directive, VAX: VAX-directives. (line 22) 21075* hi pseudo-op, V850: V850 Opcodes. (line 33) 21076* hi0 pseudo-op, V850: V850 Opcodes. (line 10) 21077* hidden directive: Hidden. (line 6) 21078* high directive, M32R: M32R-Directives. (line 18) 21079* hilo pseudo-op, V850: V850 Opcodes. (line 55) 21080* HPPA directives not supported: HPPA Directives. (line 11) 21081* HPPA floating point (IEEE): HPPA Floating Point. (line 6) 21082* HPPA Syntax: HPPA Options. (line 8) 21083* HPPA-only directives: HPPA Directives. (line 24) 21084* hword directive: hword. (line 6) 21085* i370 support: ESA/390-Dependent. (line 6) 21086* i386 16-bit code: i386-16bit. (line 6) 21087* i386 arch directive: i386-Arch. (line 6) 21088* i386 att_syntax pseudo op: i386-Syntax. (line 6) 21089* i386 conversion instructions: i386-Mnemonics. (line 37) 21090* i386 floating point: i386-Float. (line 6) 21091* i386 immediate operands: i386-Syntax. (line 15) 21092* i386 instruction naming: i386-Mnemonics. (line 6) 21093* i386 instruction prefixes: i386-Prefixes. (line 6) 21094* i386 intel_syntax pseudo op: i386-Syntax. (line 6) 21095* i386 jump optimization: i386-Jumps. (line 6) 21096* i386 jump, call, return: i386-Syntax. (line 41) 21097* i386 jump/call operands: i386-Syntax. (line 15) 21098* i386 memory references: i386-Memory. (line 6) 21099* i386 mnemonic compatibility: i386-Mnemonics. (line 62) 21100* i386 mul, imul instructions: i386-Notes. (line 6) 21101* i386 options: i386-Options. (line 6) 21102* i386 register operands: i386-Syntax. (line 15) 21103* i386 registers: i386-Regs. (line 6) 21104* i386 sections: i386-Syntax. (line 47) 21105* i386 size suffixes: i386-Syntax. (line 29) 21106* i386 source, destination operands: i386-Syntax. (line 22) 21107* i386 support: i386-Dependent. (line 6) 21108* i386 syntax compatibility: i386-Syntax. (line 6) 21109* i80386 support: i386-Dependent. (line 6) 21110* i860 machine directives: Directives-i860. (line 6) 21111* i860 opcodes: Opcodes for i860. (line 6) 21112* i860 support: i860-Dependent. (line 6) 21113* i960 architecture options: Options-i960. (line 6) 21114* i960 branch recording: Options-i960. (line 22) 21115* i960 callj pseudo-opcode: callj-i960. (line 6) 21116* i960 compare and jump expansions: Compare-and-branch-i960. 21117 (line 13) 21118* i960 compare/branch instructions: Compare-and-branch-i960. 21119 (line 6) 21120* i960 floating point (IEEE): Floating Point-i960. (line 6) 21121* i960 machine directives: Directives-i960. (line 6) 21122* i960 opcodes: Opcodes for i960. (line 6) 21123* i960 options: Options-i960. (line 6) 21124* i960 support: i960-Dependent. (line 6) 21125* IA-64 line comment character: IA-64-Chars. (line 6) 21126* IA-64 line separator: IA-64-Chars. (line 8) 21127* IA-64 options: IA-64 Options. (line 6) 21128* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 21129* IA-64 registers: IA-64-Regs. (line 6) 21130* IA-64 relocations: IA-64-Relocs. (line 6) 21131* IA-64 support: IA-64-Dependent. (line 6) 21132* IA-64 Syntax: IA-64 Options. (line 87) 21133* ident directive: Ident. (line 6) 21134* identifiers, ARM: ARM-Chars. (line 15) 21135* identifiers, MSP 430: MSP430-Chars. (line 8) 21136* if directive: If. (line 6) 21137* ifb directive: If. (line 21) 21138* ifc directive: If. (line 25) 21139* ifdef directive: If. (line 16) 21140* ifeq directive: If. (line 33) 21141* ifeqs directive: If. (line 36) 21142* ifge directive: If. (line 40) 21143* ifgt directive: If. (line 44) 21144* ifle directive: If. (line 48) 21145* iflt directive: If. (line 52) 21146* ifnb directive: If. (line 56) 21147* ifnc directive: If. (line 61) 21148* ifndef directive: If. (line 65) 21149* ifne directive: If. (line 72) 21150* ifnes directive: If. (line 76) 21151* ifnotdef directive: If. (line 65) 21152* immediate character, ARM: ARM-Chars. (line 13) 21153* immediate character, M680x0: M68K-Chars. (line 6) 21154* immediate character, VAX: VAX-operands. (line 6) 21155* immediate fields, relaxation: Xtensa Immediate Relaxation. 21156 (line 6) 21157* immediate operands, i386: i386-Syntax. (line 15) 21158* immediate operands, x86-64: i386-Syntax. (line 15) 21159* imul instruction, i386: i386-Notes. (line 6) 21160* imul instruction, x86-64: i386-Notes. (line 6) 21161* incbin directive: Incbin. (line 6) 21162* include directive: Include. (line 6) 21163* include directive search path: I. (line 6) 21164* indirect character, VAX: VAX-operands. (line 9) 21165* infix operators: Infix Ops. (line 6) 21166* inhibiting interrupts, i386: i386-Prefixes. (line 36) 21167* input: Input Files. (line 6) 21168* input file linenumbers: Input Files. (line 35) 21169* instruction aliases, s390: s390 Aliases. (line 6) 21170* instruction expansion, CRIS: CRIS-Expand. (line 6) 21171* instruction expansion, MMIX: MMIX-Expand. (line 6) 21172* instruction formats, s390: s390 Formats. (line 6) 21173* instruction marker, s390: s390 Instruction Marker. 21174 (line 6) 21175* instruction mnemonics, s390: s390 Mnemonics. (line 6) 21176* instruction naming, i386: i386-Mnemonics. (line 6) 21177* instruction naming, x86-64: i386-Mnemonics. (line 6) 21178* instruction operand modifier, s390: s390 Operand Modifier. 21179 (line 6) 21180* instruction operands, s390: s390 Operands. (line 6) 21181* instruction prefixes, i386: i386-Prefixes. (line 6) 21182* instruction set, M680x0: M68K-opcodes. (line 6) 21183* instruction set, M68HC11: M68HC11-opcodes. (line 6) 21184* instruction summary, AVR: AVR Opcodes. (line 6) 21185* instruction summary, D10V: D10V-Opcodes. (line 6) 21186* instruction summary, D30V: D30V-Opcodes. (line 6) 21187* instruction summary, H8/300: H8/300 Opcodes. (line 6) 21188* instruction summary, LM32: LM32 Opcodes. (line 6) 21189* instruction summary, SH: SH Opcodes. (line 6) 21190* instruction summary, SH64: SH64 Opcodes. (line 6) 21191* instruction summary, Z8000: Z8000 Opcodes. (line 6) 21192* instruction syntax, s390: s390 Syntax. (line 6) 21193* instructions and directives: Statements. (line 19) 21194* int directive: Int. (line 6) 21195* int directive, H8/300: H8/300 Directives. (line 6) 21196* int directive, i386: i386-Float. (line 21) 21197* int directive, TIC54X: TIC54X-Directives. (line 111) 21198* int directive, x86-64: i386-Float. (line 21) 21199* integer expressions: Integer Exprs. (line 6) 21200* integer, 16-byte: Octa. (line 6) 21201* integer, 8-byte: Quad. (line 9) 21202* integers: Integers. (line 6) 21203* integers, 16-bit: hword. (line 6) 21204* integers, 32-bit: Int. (line 6) 21205* integers, binary: Integers. (line 6) 21206* integers, decimal: Integers. (line 12) 21207* integers, hexadecimal: Integers. (line 15) 21208* integers, octal: Integers. (line 9) 21209* integers, one byte: Byte. (line 6) 21210* intel_syntax pseudo op, i386: i386-Syntax. (line 6) 21211* intel_syntax pseudo op, x86-64: i386-Syntax. (line 6) 21212* internal assembler sections: As Sections. (line 6) 21213* internal directive: Internal. (line 6) 21214* invalid input: Bug Criteria. (line 14) 21215* invocation summary: Overview. (line 6) 21216* IP2K architecture options: IP2K-Opts. (line 14) 21217* IP2K options: IP2K-Opts. (line 6) 21218* IP2K support: IP2K-Dependent. (line 6) 21219* irp directive: Irp. (line 6) 21220* irpc directive: Irpc. (line 6) 21221* ISA options, SH64: SH64 Options. (line 6) 21222* joining text and data sections: R. (line 6) 21223* jump instructions, i386: i386-Mnemonics. (line 56) 21224* jump instructions, x86-64: i386-Mnemonics. (line 56) 21225* jump optimization, i386: i386-Jumps. (line 6) 21226* jump optimization, x86-64: i386-Jumps. (line 6) 21227* jump/call operands, i386: i386-Syntax. (line 15) 21228* jump/call operands, x86-64: i386-Syntax. (line 15) 21229* L16SI instructions, relaxation: Xtensa Immediate Relaxation. 21230 (line 23) 21231* L16UI instructions, relaxation: Xtensa Immediate Relaxation. 21232 (line 23) 21233* L32I instructions, relaxation: Xtensa Immediate Relaxation. 21234 (line 23) 21235* L8UI instructions, relaxation: Xtensa Immediate Relaxation. 21236 (line 23) 21237* label (:): Statements. (line 30) 21238* label directive, TIC54X: TIC54X-Directives. (line 123) 21239* labels: Labels. (line 6) 21240* lcomm directive: Lcomm. (line 6) 21241* lcomm directive, COFF: i386-Directives. (line 6) 21242* ld: Object. (line 15) 21243* ldouble directive M680x0: M68K-Float. (line 17) 21244* ldouble directive M68HC11: M68HC11-Float. (line 17) 21245* ldouble directive, TIC54X: TIC54X-Directives. (line 64) 21246* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 21247* leafproc directive, i960: Directives-i960. (line 18) 21248* length directive, TIC54X: TIC54X-Directives. (line 127) 21249* length of symbols: Symbol Intro. (line 14) 21250* lflags directive (ignored): Lflags. (line 6) 21251* line comment character: Comments. (line 19) 21252* line comment character, Alpha: Alpha-Chars. (line 6) 21253* line comment character, ARM: ARM-Chars. (line 6) 21254* line comment character, AVR: AVR-Chars. (line 6) 21255* line comment character, D10V: D10V-Chars. (line 6) 21256* line comment character, D30V: D30V-Chars. (line 6) 21257* line comment character, H8/300: H8/300-Chars. (line 6) 21258* line comment character, IA-64: IA-64-Chars. (line 6) 21259* line comment character, M680x0: M68K-Chars. (line 6) 21260* line comment character, MSP 430: MSP430-Chars. (line 6) 21261* line comment character, s390: s390 Characters. (line 6) 21262* line comment character, SH: SH-Chars. (line 6) 21263* line comment character, SH64: SH64-Chars. (line 6) 21264* line comment character, Sparc: Sparc-Chars. (line 6) 21265* line comment character, TIC6X: TIC6X Syntax. (line 6) 21266* line comment character, V850: V850-Chars. (line 6) 21267* line comment character, Z80: Z80-Chars. (line 6) 21268* line comment character, Z8000: Z8000-Chars. (line 6) 21269* line comment characters, CRIS: CRIS-Chars. (line 6) 21270* line comment characters, MMIX: MMIX-Chars. (line 6) 21271* line directive: Line. (line 6) 21272* line directive, MSP 430: MSP430 Directives. (line 14) 21273* line numbers, in input files: Input Files. (line 35) 21274* line numbers, in warnings/errors: Errors. (line 16) 21275* line separator character: Statements. (line 6) 21276* line separator, Alpha: Alpha-Chars. (line 8) 21277* line separator, ARM: ARM-Chars. (line 10) 21278* line separator, AVR: AVR-Chars. (line 10) 21279* line separator, H8/300: H8/300-Chars. (line 8) 21280* line separator, IA-64: IA-64-Chars. (line 8) 21281* line separator, SH: SH-Chars. (line 8) 21282* line separator, SH64: SH64-Chars. (line 8) 21283* line separator, Sparc: Sparc-Chars. (line 8) 21284* line separator, TIC6X: TIC6X Syntax. (line 10) 21285* line separator, Z8000: Z8000-Chars. (line 8) 21286* lines starting with #: Comments. (line 39) 21287* linker: Object. (line 15) 21288* linker, and assembler: Secs Background. (line 10) 21289* linkonce directive: Linkonce. (line 6) 21290* list directive: List. (line 6) 21291* list directive, TIC54X: TIC54X-Directives. (line 131) 21292* listing control, turning off: Nolist. (line 6) 21293* listing control, turning on: List. (line 6) 21294* listing control: new page: Eject. (line 6) 21295* listing control: paper size: Psize. (line 6) 21296* listing control: subtitle: Sbttl. (line 6) 21297* listing control: title line: Title. (line 6) 21298* listings, enabling: a. (line 6) 21299* literal directive: Literal Directive. (line 6) 21300* literal pool entries, s390: s390 Literal Pool Entries. 21301 (line 6) 21302* literal_position directive: Literal Position Directive. 21303 (line 6) 21304* literal_prefix directive: Literal Prefix Directive. 21305 (line 6) 21306* little endian output, MIPS: Overview. (line 696) 21307* little endian output, PJ: Overview. (line 603) 21308* little-endian output, MIPS: MIPS Opts. (line 13) 21309* little-endian output, TIC6X: TIC6X Options. (line 58) 21310* LM32 modifiers: LM32-Modifiers. (line 6) 21311* LM32 opcode summary: LM32 Opcodes. (line 6) 21312* LM32 options (none): LM32 Options. (line 6) 21313* LM32 register names: LM32-Regs. (line 6) 21314* LM32 support: LM32-Dependent. (line 6) 21315* ln directive: Ln. (line 6) 21316* lo pseudo-op, V850: V850 Opcodes. (line 22) 21317* loc directive: Loc. (line 6) 21318* loc_mark_labels directive: Loc_mark_labels. (line 6) 21319* local common symbols: Lcomm. (line 6) 21320* local directive: Local. (line 6) 21321* local labels: Symbol Names. (line 35) 21322* local symbol names: Symbol Names. (line 22) 21323* local symbols, retaining in output: L. (line 6) 21324* location counter: Dot. (line 6) 21325* location counter, advancing: Org. (line 6) 21326* location counter, Z80: Z80-Chars. (line 8) 21327* logical file name: File. (line 13) 21328* logical line number: Line. (line 6) 21329* logical line numbers: Comments. (line 39) 21330* long directive: Long. (line 6) 21331* long directive, ARC: ARC Directives. (line 159) 21332* long directive, i386: i386-Float. (line 21) 21333* long directive, TIC54X: TIC54X-Directives. (line 135) 21334* long directive, x86-64: i386-Float. (line 21) 21335* longcall pseudo-op, V850: V850 Opcodes. (line 123) 21336* longcalls directive: Longcalls Directive. (line 6) 21337* longjump pseudo-op, V850: V850 Opcodes. (line 129) 21338* loop directive, TIC54X: TIC54X-Directives. (line 143) 21339* LOOP instructions, alignment: Xtensa Automatic Alignment. 21340 (line 6) 21341* low directive, M32R: M32R-Directives. (line 9) 21342* lp register, V850: V850-Regs. (line 98) 21343* lval: Z8000 Directives. (line 27) 21344* LWP, i386: i386-LWP. (line 6) 21345* LWP, x86-64: i386-LWP. (line 6) 21346* M16C architecture option: M32C-Opts. (line 12) 21347* M32C architecture option: M32C-Opts. (line 9) 21348* M32C modifiers: M32C-Modifiers. (line 6) 21349* M32C options: M32C-Opts. (line 6) 21350* M32C support: M32C-Dependent. (line 6) 21351* M32R architecture options: M32R-Opts. (line 17) 21352* M32R directives: M32R-Directives. (line 6) 21353* M32R options: M32R-Opts. (line 6) 21354* M32R support: M32R-Dependent. (line 6) 21355* M32R warnings: M32R-Warnings. (line 6) 21356* M680x0 addressing modes: M68K-Syntax. (line 21) 21357* M680x0 architecture options: M68K-Opts. (line 98) 21358* M680x0 branch improvement: M68K-Branch. (line 6) 21359* M680x0 directives: M68K-Directives. (line 6) 21360* M680x0 floating point: M68K-Float. (line 6) 21361* M680x0 immediate character: M68K-Chars. (line 6) 21362* M680x0 line comment character: M68K-Chars. (line 6) 21363* M680x0 opcodes: M68K-opcodes. (line 6) 21364* M680x0 options: M68K-Opts. (line 6) 21365* M680x0 pseudo-opcodes: M68K-Branch. (line 6) 21366* M680x0 size modifiers: M68K-Syntax. (line 8) 21367* M680x0 support: M68K-Dependent. (line 6) 21368* M680x0 syntax: M68K-Syntax. (line 8) 21369* M68HC11 addressing modes: M68HC11-Syntax. (line 17) 21370* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 21371* M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 21372* M68HC11 assembler directive .interrupt: M68HC11-Directives. (line 26) 21373* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 21374* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 21375* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 21376* M68HC11 assembler directives: M68HC11-Directives. (line 6) 21377* M68HC11 branch improvement: M68HC11-Branch. (line 6) 21378* M68HC11 floating point: M68HC11-Float. (line 6) 21379* M68HC11 modifiers: M68HC11-Modifiers. (line 6) 21380* M68HC11 opcodes: M68HC11-opcodes. (line 6) 21381* M68HC11 options: M68HC11-Opts. (line 6) 21382* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 21383* M68HC11 syntax: M68HC11-Syntax. (line 6) 21384* M68HC12 assembler directives: M68HC11-Directives. (line 6) 21385* machine dependencies: Machine Dependencies. 21386 (line 6) 21387* machine directives, ARC: ARC Directives. (line 6) 21388* machine directives, ARM: ARM Directives. (line 6) 21389* machine directives, H8/300 (none): H8/300 Directives. (line 6) 21390* machine directives, i860: Directives-i860. (line 6) 21391* machine directives, i960: Directives-i960. (line 6) 21392* machine directives, MSP 430: MSP430 Directives. (line 6) 21393* machine directives, SH: SH Directives. (line 6) 21394* machine directives, SH64: SH64 Directives. (line 9) 21395* machine directives, SPARC: Sparc-Directives. (line 6) 21396* machine directives, TIC54X: TIC54X-Directives. (line 6) 21397* machine directives, TIC6X: TIC6X Directives. (line 6) 21398* machine directives, V850: V850 Directives. (line 6) 21399* machine directives, VAX: VAX-directives. (line 6) 21400* machine directives, x86: i386-Directives. (line 6) 21401* machine independent directives: Pseudo Ops. (line 6) 21402* machine instructions (not covered): Manual. (line 14) 21403* machine-independent syntax: Syntax. (line 6) 21404* macro directive: Macro. (line 28) 21405* macro directive, TIC54X: TIC54X-Directives. (line 153) 21406* macros: Macro. (line 6) 21407* macros, count executed: Macro. (line 143) 21408* Macros, MSP 430: MSP430-Macros. (line 6) 21409* macros, TIC54X: TIC54X-Macros. (line 6) 21410* make rules: MD. (line 6) 21411* manual, structure and purpose: Manual. (line 6) 21412* math builtins, TIC54X: TIC54X-Builtins. (line 6) 21413* Maximum number of continuation lines: listing. (line 34) 21414* memory references, i386: i386-Memory. (line 6) 21415* memory references, x86-64: i386-Memory. (line 6) 21416* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 21417* merging text and data sections: R. (line 6) 21418* messages from assembler: Errors. (line 6) 21419* MicroBlaze architectures: MicroBlaze-Dependent. 21420 (line 6) 21421* MicroBlaze directives: MicroBlaze Directives. 21422 (line 6) 21423* MicroBlaze support: MicroBlaze-Dependent. 21424 (line 13) 21425* minus, permitted arguments: Infix Ops. (line 49) 21426* MIPS architecture options: MIPS Opts. (line 29) 21427* MIPS big-endian output: MIPS Opts. (line 13) 21428* MIPS CPU override: MIPS ISA. (line 18) 21429* MIPS debugging directives: MIPS Stabs. (line 6) 21430* MIPS DSP Release 1 instruction generation override: MIPS ASE instruction generation overrides. 21431 (line 21) 21432* MIPS DSP Release 2 instruction generation override: MIPS ASE instruction generation overrides. 21433 (line 26) 21434* MIPS ECOFF sections: MIPS Object. (line 6) 21435* MIPS endianness: Overview. (line 693) 21436* MIPS ISA: Overview. (line 699) 21437* MIPS ISA override: MIPS ISA. (line 6) 21438* MIPS little-endian output: MIPS Opts. (line 13) 21439* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides. 21440 (line 16) 21441* MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides. 21442 (line 6) 21443* MIPS MT instruction generation override: MIPS ASE instruction generation overrides. 21444 (line 32) 21445* MIPS option stack: MIPS option stack. (line 6) 21446* MIPS processor: MIPS-Dependent. (line 6) 21447* MIT: M68K-Syntax. (line 6) 21448* mlib directive, TIC54X: TIC54X-Directives. (line 159) 21449* mlist directive, TIC54X: TIC54X-Directives. (line 164) 21450* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 131) 21451* MMIX assembler directive BYTE: MMIX-Pseudos. (line 97) 21452* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 131) 21453* MMIX assembler directive GREG: MMIX-Pseudos. (line 50) 21454* MMIX assembler directive IS: MMIX-Pseudos. (line 42) 21455* MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 21456* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 28) 21457* MMIX assembler directive OCTA: MMIX-Pseudos. (line 108) 21458* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 120) 21459* MMIX assembler directive TETRA: MMIX-Pseudos. (line 108) 21460* MMIX assembler directive WYDE: MMIX-Pseudos. (line 108) 21461* MMIX assembler directives: MMIX-Pseudos. (line 6) 21462* MMIX line comment characters: MMIX-Chars. (line 6) 21463* MMIX options: MMIX-Opts. (line 6) 21464* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 131) 21465* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 97) 21466* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 131) 21467* MMIX pseudo-op GREG: MMIX-Pseudos. (line 50) 21468* MMIX pseudo-op IS: MMIX-Pseudos. (line 42) 21469* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 21470* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 28) 21471* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 108) 21472* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 120) 21473* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 108) 21474* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 108) 21475* MMIX pseudo-ops: MMIX-Pseudos. (line 6) 21476* MMIX register names: MMIX-Regs. (line 6) 21477* MMIX support: MMIX-Dependent. (line 6) 21478* mmixal differences: MMIX-mmixal. (line 6) 21479* mmregs directive, TIC54X: TIC54X-Directives. (line 169) 21480* mmsg directive, TIC54X: TIC54X-Directives. (line 77) 21481* MMX, i386: i386-SIMD. (line 6) 21482* MMX, x86-64: i386-SIMD. (line 6) 21483* mnemonic compatibility, i386: i386-Mnemonics. (line 62) 21484* mnemonic suffixes, i386: i386-Syntax. (line 29) 21485* mnemonic suffixes, x86-64: i386-Syntax. (line 29) 21486* mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 21487* mnemonics, AVR: AVR Opcodes. (line 6) 21488* mnemonics, D10V: D10V-Opcodes. (line 6) 21489* mnemonics, D30V: D30V-Opcodes. (line 6) 21490* mnemonics, H8/300: H8/300 Opcodes. (line 6) 21491* mnemonics, LM32: LM32 Opcodes. (line 6) 21492* mnemonics, SH: SH Opcodes. (line 6) 21493* mnemonics, SH64: SH64 Opcodes. (line 6) 21494* mnemonics, Z8000: Z8000 Opcodes. (line 6) 21495* mnolist directive, TIC54X: TIC54X-Directives. (line 164) 21496* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 21497* MOVI instructions, relaxation: Xtensa Immediate Relaxation. 21498 (line 12) 21499* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 20) 21500* MRI compatibility mode: M. (line 6) 21501* mri directive: MRI. (line 6) 21502* MRI mode, temporarily: MRI. (line 6) 21503* MSP 430 floating point (IEEE): MSP430 Floating Point. 21504 (line 6) 21505* MSP 430 identifiers: MSP430-Chars. (line 8) 21506* MSP 430 line comment character: MSP430-Chars. (line 6) 21507* MSP 430 machine directives: MSP430 Directives. (line 6) 21508* MSP 430 macros: MSP430-Macros. (line 6) 21509* MSP 430 opcodes: MSP430 Opcodes. (line 6) 21510* MSP 430 options (none): MSP430 Options. (line 6) 21511* MSP 430 profiling capability: MSP430 Profiling Capability. 21512 (line 6) 21513* MSP 430 register names: MSP430-Regs. (line 6) 21514* MSP 430 support: MSP430-Dependent. (line 6) 21515* MSP430 Assembler Extensions: MSP430-Ext. (line 6) 21516* mul instruction, i386: i386-Notes. (line 6) 21517* mul instruction, x86-64: i386-Notes. (line 6) 21518* name: Z8000 Directives. (line 18) 21519* named section: Section. (line 6) 21520* named sections: Ld Sections. (line 8) 21521* names, symbol: Symbol Names. (line 6) 21522* naming object file: o. (line 6) 21523* new page, in listings: Eject. (line 6) 21524* newblock directive, TIC54X: TIC54X-Directives. (line 175) 21525* newline (\n): Strings. (line 21) 21526* newline, required at file end: Statements. (line 13) 21527* no-absolute-literals directive: Absolute Literals Directive. 21528 (line 6) 21529* no-longcalls directive: Longcalls Directive. (line 6) 21530* no-schedule directive: Schedule Directive. (line 6) 21531* no-transform directive: Transform Directive. (line 6) 21532* nolist directive: Nolist. (line 6) 21533* nolist directive, TIC54X: TIC54X-Directives. (line 131) 21534* NOP pseudo op, ARM: ARM Opcodes. (line 9) 21535* notes for Alpha: Alpha Notes. (line 6) 21536* null-terminated strings: Asciz. (line 6) 21537* number constants: Numbers. (line 6) 21538* number of macros executed: Macro. (line 143) 21539* numbered subsections: Sub-Sections. (line 6) 21540* numbers, 16-bit: hword. (line 6) 21541* numeric values: Expressions. (line 6) 21542* nword directive, SPARC: Sparc-Directives. (line 20) 21543* object attributes: Object Attributes. (line 6) 21544* object file: Object. (line 6) 21545* object file format: Object Formats. (line 6) 21546* object file name: o. (line 6) 21547* object file, after errors: Z. (line 6) 21548* obsolescent directives: Deprecated. (line 6) 21549* octa directive: Octa. (line 6) 21550* octal character code (\DDD): Strings. (line 30) 21551* octal integers: Integers. (line 9) 21552* offset directive, V850: V850 Directives. (line 6) 21553* opcode mnemonics, VAX: VAX-opcodes. (line 6) 21554* opcode names, Xtensa: Xtensa Opcodes. (line 6) 21555* opcode summary, AVR: AVR Opcodes. (line 6) 21556* opcode summary, D10V: D10V-Opcodes. (line 6) 21557* opcode summary, D30V: D30V-Opcodes. (line 6) 21558* opcode summary, H8/300: H8/300 Opcodes. (line 6) 21559* opcode summary, LM32: LM32 Opcodes. (line 6) 21560* opcode summary, SH: SH Opcodes. (line 6) 21561* opcode summary, SH64: SH64 Opcodes. (line 6) 21562* opcode summary, Z8000: Z8000 Opcodes. (line 6) 21563* opcodes for ARC: ARC Opcodes. (line 6) 21564* opcodes for ARM: ARM Opcodes. (line 6) 21565* opcodes for MSP 430: MSP430 Opcodes. (line 6) 21566* opcodes for V850: V850 Opcodes. (line 6) 21567* opcodes, i860: Opcodes for i860. (line 6) 21568* opcodes, i960: Opcodes for i960. (line 6) 21569* opcodes, M680x0: M68K-opcodes. (line 6) 21570* opcodes, M68HC11: M68HC11-opcodes. (line 6) 21571* operand delimiters, i386: i386-Syntax. (line 15) 21572* operand delimiters, x86-64: i386-Syntax. (line 15) 21573* operand notation, VAX: VAX-operands. (line 6) 21574* operands in expressions: Arguments. (line 6) 21575* operator precedence: Infix Ops. (line 11) 21576* operators, in expressions: Operators. (line 6) 21577* operators, permitted arguments: Infix Ops. (line 6) 21578* optimization, D10V: Overview. (line 472) 21579* optimization, D30V: Overview. (line 477) 21580* optimizations: Xtensa Optimizations. 21581 (line 6) 21582* option directive, ARC: ARC Directives. (line 162) 21583* option directive, TIC54X: TIC54X-Directives. (line 179) 21584* option summary: Overview. (line 6) 21585* options for Alpha: Alpha Options. (line 6) 21586* options for ARC (none): ARC Options. (line 6) 21587* options for ARM (none): ARM Options. (line 6) 21588* options for AVR (none): AVR Options. (line 6) 21589* options for Blackfin (none): Blackfin Options. (line 6) 21590* options for i386: i386-Options. (line 6) 21591* options for IA-64: IA-64 Options. (line 6) 21592* options for LM32 (none): LM32 Options. (line 6) 21593* options for MSP430 (none): MSP430 Options. (line 6) 21594* options for PDP-11: PDP-11-Options. (line 6) 21595* options for PowerPC: PowerPC-Opts. (line 6) 21596* options for s390: s390 Options. (line 6) 21597* options for SCORE: SCORE-Opts. (line 6) 21598* options for SPARC: Sparc-Opts. (line 6) 21599* options for TIC6X: TIC6X Options. (line 6) 21600* options for V850 (none): V850 Options. (line 6) 21601* options for VAX/VMS: VAX-Opts. (line 42) 21602* options for x86-64: i386-Options. (line 6) 21603* options for Z80: Z80 Options. (line 6) 21604* options, all versions of assembler: Invoking. (line 6) 21605* options, command line: Command Line. (line 13) 21606* options, CRIS: CRIS-Opts. (line 6) 21607* options, D10V: D10V-Opts. (line 6) 21608* options, D30V: D30V-Opts. (line 6) 21609* options, H8/300: H8/300 Options. (line 6) 21610* options, i960: Options-i960. (line 6) 21611* options, IP2K: IP2K-Opts. (line 6) 21612* options, M32C: M32C-Opts. (line 6) 21613* options, M32R: M32R-Opts. (line 6) 21614* options, M680x0: M68K-Opts. (line 6) 21615* options, M68HC11: M68HC11-Opts. (line 6) 21616* options, MMIX: MMIX-Opts. (line 6) 21617* options, PJ: PJ Options. (line 6) 21618* options, RX: RX-Opts. (line 6) 21619* options, SH: SH Options. (line 6) 21620* options, SH64: SH64 Options. (line 6) 21621* options, TIC54X: TIC54X-Opts. (line 6) 21622* options, Z8000: Z8000 Options. (line 6) 21623* org directive: Org. (line 6) 21624* other attribute, of a.out symbol: Symbol Other. (line 6) 21625* output file: Object. (line 6) 21626* p2align directive: P2align. (line 6) 21627* p2alignl directive: P2align. (line 28) 21628* p2alignw directive: P2align. (line 28) 21629* padding the location counter: Align. (line 6) 21630* padding the location counter given a power of two: P2align. (line 6) 21631* padding the location counter given number of bytes: Balign. (line 6) 21632* page, in listings: Eject. (line 6) 21633* paper size, for listings: Psize. (line 6) 21634* paths for .include: I. (line 6) 21635* patterns, writing in memory: Fill. (line 6) 21636* PDP-11 comments: PDP-11-Syntax. (line 16) 21637* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 21638* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 21639* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 21640* PDP-11 support: PDP-11-Dependent. (line 6) 21641* PDP-11 syntax: PDP-11-Syntax. (line 6) 21642* PIC code generation for ARM: ARM Options. (line 161) 21643* PIC code generation for M32R: M32R-Opts. (line 42) 21644* PIC selection, MIPS: MIPS Opts. (line 21) 21645* PJ endianness: Overview. (line 600) 21646* PJ options: PJ Options. (line 6) 21647* PJ support: PJ-Dependent. (line 6) 21648* plus, permitted arguments: Infix Ops. (line 44) 21649* popsection directive: PopSection. (line 6) 21650* Position-independent code, CRIS: CRIS-Opts. (line 27) 21651* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 21652* PowerPC architectures: PowerPC-Opts. (line 6) 21653* PowerPC directives: PowerPC-Pseudo. (line 6) 21654* PowerPC options: PowerPC-Opts. (line 6) 21655* PowerPC support: PPC-Dependent. (line 6) 21656* precedence of operators: Infix Ops. (line 11) 21657* precision, floating point: Flonums. (line 6) 21658* prefix operators: Prefix Ops. (line 6) 21659* prefixes, i386: i386-Prefixes. (line 6) 21660* preprocessing: Preprocessing. (line 6) 21661* preprocessing, turning on and off: Preprocessing. (line 27) 21662* previous directive: Previous. (line 6) 21663* primary attributes, COFF symbols: COFF Symbols. (line 13) 21664* print directive: Print. (line 6) 21665* proc directive, SPARC: Sparc-Directives. (line 25) 21666* profiler directive, MSP 430: MSP430 Directives. (line 22) 21667* profiling capability for MSP 430: MSP430 Profiling Capability. 21668 (line 6) 21669* protected directive: Protected. (line 6) 21670* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 45) 21671* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 21672* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 17) 21673* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 131) 21674* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 97) 21675* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 131) 21676* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 50) 21677* pseudo-op IS, MMIX: MMIX-Pseudos. (line 42) 21678* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 21679* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 28) 21680* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 108) 21681* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 120) 21682* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 108) 21683* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 108) 21684* pseudo-opcodes, M680x0: M68K-Branch. (line 6) 21685* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 21686* pseudo-ops for branch, VAX: VAX-branch. (line 6) 21687* pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 21688* pseudo-ops, machine independent: Pseudo Ops. (line 6) 21689* pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 21690* psize directive: Psize. (line 6) 21691* PSR bits: IA-64-Bits. (line 6) 21692* pstring directive, TIC54X: TIC54X-Directives. (line 208) 21693* psw register, V850: V850-Regs. (line 116) 21694* purgem directive: Purgem. (line 6) 21695* purpose of GNU assembler: GNU Assembler. (line 12) 21696* pushsection directive: PushSection. (line 6) 21697* quad directive: Quad. (line 6) 21698* quad directive, i386: i386-Float. (line 21) 21699* quad directive, x86-64: i386-Float. (line 21) 21700* real-mode code, i386: i386-16bit. (line 6) 21701* ref directive, TIC54X: TIC54X-Directives. (line 103) 21702* register directive, SPARC: Sparc-Directives. (line 29) 21703* register names, Alpha: Alpha-Regs. (line 6) 21704* register names, ARC: ARC-Regs. (line 6) 21705* register names, ARM: ARM-Regs. (line 6) 21706* register names, AVR: AVR-Regs. (line 6) 21707* register names, CRIS: CRIS-Regs. (line 6) 21708* register names, H8/300: H8/300-Regs. (line 6) 21709* register names, IA-64: IA-64-Regs. (line 6) 21710* register names, LM32: LM32-Regs. (line 6) 21711* register names, MMIX: MMIX-Regs. (line 6) 21712* register names, MSP 430: MSP430-Regs. (line 6) 21713* register names, Sparc: Sparc-Regs. (line 6) 21714* register names, V850: V850-Regs. (line 6) 21715* register names, VAX: VAX-operands. (line 17) 21716* register names, Xtensa: Xtensa Registers. (line 6) 21717* register names, Z80: Z80-Regs. (line 6) 21718* register naming, s390: s390 Register. (line 6) 21719* register operands, i386: i386-Syntax. (line 15) 21720* register operands, x86-64: i386-Syntax. (line 15) 21721* registers, D10V: D10V-Regs. (line 6) 21722* registers, D30V: D30V-Regs. (line 6) 21723* registers, i386: i386-Regs. (line 6) 21724* registers, SH: SH-Regs. (line 6) 21725* registers, SH64: SH64-Regs. (line 6) 21726* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 21727* registers, x86-64: i386-Regs. (line 6) 21728* registers, Z8000: Z8000-Regs. (line 6) 21729* relaxation: Xtensa Relaxation. (line 6) 21730* relaxation of ADDI instructions: Xtensa Immediate Relaxation. 21731 (line 43) 21732* relaxation of branch instructions: Xtensa Branch Relaxation. 21733 (line 6) 21734* relaxation of call instructions: Xtensa Call Relaxation. 21735 (line 6) 21736* relaxation of immediate fields: Xtensa Immediate Relaxation. 21737 (line 6) 21738* relaxation of L16SI instructions: Xtensa Immediate Relaxation. 21739 (line 23) 21740* relaxation of L16UI instructions: Xtensa Immediate Relaxation. 21741 (line 23) 21742* relaxation of L32I instructions: Xtensa Immediate Relaxation. 21743 (line 23) 21744* relaxation of L8UI instructions: Xtensa Immediate Relaxation. 21745 (line 23) 21746* relaxation of MOVI instructions: Xtensa Immediate Relaxation. 21747 (line 12) 21748* reloc directive: Reloc. (line 6) 21749* relocation: Sections. (line 6) 21750* relocation example: Ld Sections. (line 40) 21751* relocations, Alpha: Alpha-Relocs. (line 6) 21752* relocations, Sparc: Sparc-Relocs. (line 6) 21753* repeat prefixes, i386: i386-Prefixes. (line 44) 21754* reporting bugs in assembler: Reporting Bugs. (line 6) 21755* rept directive: Rept. (line 6) 21756* reserve directive, SPARC: Sparc-Directives. (line 39) 21757* return instructions, i386: i386-Syntax. (line 41) 21758* return instructions, x86-64: i386-Syntax. (line 41) 21759* REX prefixes, i386: i386-Prefixes. (line 46) 21760* rsect: Z8000 Directives. (line 52) 21761* RX assembler directive .3byte: RX-Directives. (line 9) 21762* RX assembler directives: RX-Directives. (line 6) 21763* RX floating point: RX-Float. (line 6) 21764* RX modifiers: RX-Modifiers. (line 6) 21765* RX options: RX-Opts. (line 6) 21766* RX support: RX-Dependent. (line 6) 21767* s390 floating point: s390 Floating Point. (line 6) 21768* s390 instruction aliases: s390 Aliases. (line 6) 21769* s390 instruction formats: s390 Formats. (line 6) 21770* s390 instruction marker: s390 Instruction Marker. 21771 (line 6) 21772* s390 instruction mnemonics: s390 Mnemonics. (line 6) 21773* s390 instruction operand modifier: s390 Operand Modifier. 21774 (line 6) 21775* s390 instruction operands: s390 Operands. (line 6) 21776* s390 instruction syntax: s390 Syntax. (line 6) 21777* s390 line comment character: s390 Characters. (line 6) 21778* s390 literal pool entries: s390 Literal Pool Entries. 21779 (line 6) 21780* s390 options: s390 Options. (line 6) 21781* s390 register naming: s390 Register. (line 6) 21782* s390 support: S/390-Dependent. (line 6) 21783* sblock directive, TIC54X: TIC54X-Directives. (line 182) 21784* sbttl directive: Sbttl. (line 6) 21785* schedule directive: Schedule Directive. (line 6) 21786* scl directive: Scl. (line 6) 21787* SCORE architectures: SCORE-Opts. (line 6) 21788* SCORE directives: SCORE-Pseudo. (line 6) 21789* SCORE options: SCORE-Opts. (line 6) 21790* SCORE processor: SCORE-Dependent. (line 6) 21791* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 21792* search path for .include: I. (line 6) 21793* sect directive, MSP 430: MSP430 Directives. (line 18) 21794* sect directive, TIC54X: TIC54X-Directives. (line 188) 21795* section directive (COFF version): Section. (line 16) 21796* section directive (ELF version): Section. (line 73) 21797* section directive, V850: V850 Directives. (line 9) 21798* section override prefixes, i386: i386-Prefixes. (line 23) 21799* Section Stack <1>: SubSection. (line 6) 21800* Section Stack <2>: PopSection. (line 6) 21801* Section Stack <3>: Section. (line 68) 21802* Section Stack <4>: Previous. (line 6) 21803* Section Stack: PushSection. (line 6) 21804* section-relative addressing: Secs Background. (line 68) 21805* sections: Sections. (line 6) 21806* sections in messages, internal: As Sections. (line 6) 21807* sections, i386: i386-Syntax. (line 47) 21808* sections, named: Ld Sections. (line 8) 21809* sections, x86-64: i386-Syntax. (line 47) 21810* seg directive, SPARC: Sparc-Directives. (line 44) 21811* segm: Z8000 Directives. (line 10) 21812* set directive: Set. (line 6) 21813* set directive, TIC54X: TIC54X-Directives. (line 191) 21814* SH addressing modes: SH-Addressing. (line 6) 21815* SH floating point (IEEE): SH Floating Point. (line 6) 21816* SH line comment character: SH-Chars. (line 6) 21817* SH line separator: SH-Chars. (line 8) 21818* SH machine directives: SH Directives. (line 6) 21819* SH opcode summary: SH Opcodes. (line 6) 21820* SH options: SH Options. (line 6) 21821* SH registers: SH-Regs. (line 6) 21822* SH support: SH-Dependent. (line 6) 21823* SH64 ABI options: SH64 Options. (line 29) 21824* SH64 addressing modes: SH64-Addressing. (line 6) 21825* SH64 ISA options: SH64 Options. (line 6) 21826* SH64 line comment character: SH64-Chars. (line 6) 21827* SH64 line separator: SH64-Chars. (line 8) 21828* SH64 machine directives: SH64 Directives. (line 9) 21829* SH64 opcode summary: SH64 Opcodes. (line 6) 21830* SH64 options: SH64 Options. (line 6) 21831* SH64 registers: SH64-Regs. (line 6) 21832* SH64 support: SH64-Dependent. (line 6) 21833* shigh directive, M32R: M32R-Directives. (line 26) 21834* short directive: Short. (line 6) 21835* short directive, ARC: ARC Directives. (line 171) 21836* short directive, TIC54X: TIC54X-Directives. (line 111) 21837* SIMD, i386: i386-SIMD. (line 6) 21838* SIMD, x86-64: i386-SIMD. (line 6) 21839* single character constant: Chars. (line 6) 21840* single directive: Single. (line 6) 21841* single directive, i386: i386-Float. (line 14) 21842* single directive, x86-64: i386-Float. (line 14) 21843* single quote, Z80: Z80-Chars. (line 13) 21844* sixteen bit integers: hword. (line 6) 21845* sixteen byte integer: Octa. (line 6) 21846* size directive (COFF version): Size. (line 11) 21847* size directive (ELF version): Size. (line 19) 21848* size modifiers, D10V: D10V-Size. (line 6) 21849* size modifiers, D30V: D30V-Size. (line 6) 21850* size modifiers, M680x0: M68K-Syntax. (line 8) 21851* size prefixes, i386: i386-Prefixes. (line 27) 21852* size suffixes, H8/300: H8/300 Opcodes. (line 163) 21853* size, translations, Sparc: Sparc-Size-Translations. 21854 (line 6) 21855* sizes operands, i386: i386-Syntax. (line 29) 21856* sizes operands, x86-64: i386-Syntax. (line 29) 21857* skip directive: Skip. (line 6) 21858* skip directive, M680x0: M68K-Directives. (line 19) 21859* skip directive, SPARC: Sparc-Directives. (line 48) 21860* sleb128 directive: Sleb128. (line 6) 21861* small objects, MIPS ECOFF: MIPS Object. (line 11) 21862* SmartMIPS instruction generation override: MIPS ASE instruction generation overrides. 21863 (line 11) 21864* SOM symbol attributes: SOM Symbols. (line 6) 21865* source program: Input Files. (line 6) 21866* source, destination operands; i386: i386-Syntax. (line 22) 21867* source, destination operands; x86-64: i386-Syntax. (line 22) 21868* sp register: Xtensa Registers. (line 6) 21869* sp register, V850: V850-Regs. (line 14) 21870* space directive: Space. (line 6) 21871* space directive, TIC54X: TIC54X-Directives. (line 196) 21872* space used, maximum for assembly: statistics. (line 6) 21873* SPARC architectures: Sparc-Opts. (line 6) 21874* Sparc constants: Sparc-Constants. (line 6) 21875* SPARC data alignment: Sparc-Aligned-Data. (line 6) 21876* SPARC floating point (IEEE): Sparc-Float. (line 6) 21877* Sparc line comment character: Sparc-Chars. (line 6) 21878* Sparc line separator: Sparc-Chars. (line 8) 21879* SPARC machine directives: Sparc-Directives. (line 6) 21880* SPARC options: Sparc-Opts. (line 6) 21881* Sparc registers: Sparc-Regs. (line 6) 21882* Sparc relocations: Sparc-Relocs. (line 6) 21883* Sparc size translations: Sparc-Size-Translations. 21884 (line 6) 21885* SPARC support: Sparc-Dependent. (line 6) 21886* SPARC syntax: Sparc-Aligned-Data. (line 21) 21887* special characters, ARC: ARC-Chars. (line 6) 21888* special characters, M680x0: M68K-Chars. (line 6) 21889* special purpose registers, MSP 430: MSP430-Regs. (line 11) 21890* sslist directive, TIC54X: TIC54X-Directives. (line 203) 21891* ssnolist directive, TIC54X: TIC54X-Directives. (line 203) 21892* stabd directive: Stab. (line 38) 21893* stabn directive: Stab. (line 48) 21894* stabs directive: Stab. (line 51) 21895* stabX directives: Stab. (line 6) 21896* standard assembler sections: Secs Background. (line 27) 21897* standard input, as input file: Command Line. (line 10) 21898* statement separator character: Statements. (line 6) 21899* statement separator, Alpha: Alpha-Chars. (line 8) 21900* statement separator, ARM: ARM-Chars. (line 10) 21901* statement separator, AVR: AVR-Chars. (line 10) 21902* statement separator, H8/300: H8/300-Chars. (line 8) 21903* statement separator, IA-64: IA-64-Chars. (line 8) 21904* statement separator, SH: SH-Chars. (line 8) 21905* statement separator, SH64: SH64-Chars. (line 8) 21906* statement separator, Sparc: Sparc-Chars. (line 8) 21907* statement separator, TIC6X: TIC6X Syntax. (line 10) 21908* statement separator, Z8000: Z8000-Chars. (line 8) 21909* statements, structure of: Statements. (line 6) 21910* statistics, about assembly: statistics. (line 6) 21911* stopping the assembly: Abort. (line 6) 21912* string constants: Strings. (line 6) 21913* string directive: String. (line 8) 21914* string directive on HPPA: HPPA Directives. (line 137) 21915* string directive, TIC54X: TIC54X-Directives. (line 208) 21916* string literals: Ascii. (line 6) 21917* string, copying to object file: String. (line 8) 21918* string16 directive: String. (line 8) 21919* string16, copying to object file: String. (line 8) 21920* string32 directive: String. (line 8) 21921* string32, copying to object file: String. (line 8) 21922* string64 directive: String. (line 8) 21923* string64, copying to object file: String. (line 8) 21924* string8 directive: String. (line 8) 21925* string8, copying to object file: String. (line 8) 21926* struct directive: Struct. (line 6) 21927* struct directive, TIC54X: TIC54X-Directives. (line 216) 21928* structure debugging, COFF: Tag. (line 6) 21929* sub-instruction ordering, D10V: D10V-Chars. (line 6) 21930* sub-instruction ordering, D30V: D30V-Chars. (line 6) 21931* sub-instructions, D10V: D10V-Subs. (line 6) 21932* sub-instructions, D30V: D30V-Subs. (line 6) 21933* subexpressions: Arguments. (line 24) 21934* subsection directive: SubSection. (line 6) 21935* subsym builtins, TIC54X: TIC54X-Macros. (line 16) 21936* subtitles for listings: Sbttl. (line 6) 21937* subtraction, permitted arguments: Infix Ops. (line 49) 21938* summary of options: Overview. (line 6) 21939* support: HPPA-Dependent. (line 6) 21940* supporting files, including: Include. (line 6) 21941* suppressing warnings: W. (line 11) 21942* sval: Z8000 Directives. (line 33) 21943* symbol attributes: Symbol Attributes. (line 6) 21944* symbol attributes, a.out: a.out Symbols. (line 6) 21945* symbol attributes, COFF: COFF Symbols. (line 6) 21946* symbol attributes, SOM: SOM Symbols. (line 6) 21947* symbol descriptor, COFF: Desc. (line 6) 21948* symbol modifiers <1>: AVR-Modifiers. (line 12) 21949* symbol modifiers <2>: M68HC11-Modifiers. (line 12) 21950* symbol modifiers <3>: M32C-Modifiers. (line 11) 21951* symbol modifiers <4>: LM32-Modifiers. (line 12) 21952* symbol modifiers: RX-Modifiers. (line 11) 21953* symbol names: Symbol Names. (line 6) 21954* symbol names, $ in <1>: D30V-Chars. (line 63) 21955* symbol names, $ in <2>: SH64-Chars. (line 10) 21956* symbol names, $ in <3>: SH-Chars. (line 10) 21957* symbol names, $ in: D10V-Chars. (line 46) 21958* symbol names, local: Symbol Names. (line 22) 21959* symbol names, temporary: Symbol Names. (line 35) 21960* symbol storage class (COFF): Scl. (line 6) 21961* symbol type: Symbol Type. (line 6) 21962* symbol type, COFF: Type. (line 11) 21963* symbol type, ELF: Type. (line 22) 21964* symbol value: Symbol Value. (line 6) 21965* symbol value, setting: Set. (line 6) 21966* symbol values, assigning: Setting Symbols. (line 6) 21967* symbol versioning: Symver. (line 6) 21968* symbol, common: Comm. (line 6) 21969* symbol, making visible to linker: Global. (line 6) 21970* symbolic debuggers, information for: Stab. (line 6) 21971* symbols: Symbols. (line 6) 21972* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 21973* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 21974* symbols, assigning values to: Equ. (line 6) 21975* Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 21976* Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 21977* symbols, local common: Lcomm. (line 6) 21978* symver directive: Symver. (line 6) 21979* syntax compatibility, i386: i386-Syntax. (line 6) 21980* syntax compatibility, x86-64: i386-Syntax. (line 6) 21981* syntax, AVR: AVR-Modifiers. (line 6) 21982* syntax, Blackfin: Blackfin Syntax. (line 6) 21983* syntax, D10V: D10V-Syntax. (line 6) 21984* syntax, D30V: D30V-Syntax. (line 6) 21985* syntax, LM32: LM32-Modifiers. (line 6) 21986* syntax, M32C: M32C-Modifiers. (line 6) 21987* syntax, M680x0: M68K-Syntax. (line 8) 21988* syntax, M68HC11 <1>: M68HC11-Syntax. (line 6) 21989* syntax, M68HC11: M68HC11-Modifiers. (line 6) 21990* syntax, machine-independent: Syntax. (line 6) 21991* syntax, RX: RX-Modifiers. (line 6) 21992* syntax, SPARC: Sparc-Aligned-Data. (line 21) 21993* syntax, Xtensa assembler: Xtensa Syntax. (line 6) 21994* sysproc directive, i960: Directives-i960. (line 37) 21995* tab (\t): Strings. (line 27) 21996* tab directive, TIC54X: TIC54X-Directives. (line 247) 21997* tag directive: Tag. (line 6) 21998* tag directive, TIC54X: TIC54X-Directives. (line 216) 21999* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 22000* temporary symbol names: Symbol Names. (line 35) 22001* text and data sections, joining: R. (line 6) 22002* text directive: Text. (line 6) 22003* text section: Ld Sections. (line 9) 22004* tfloat directive, i386: i386-Float. (line 14) 22005* tfloat directive, x86-64: i386-Float. (line 14) 22006* Thumb support: ARM-Dependent. (line 6) 22007* TIC54X builtin math functions: TIC54X-Builtins. (line 6) 22008* TIC54X machine directives: TIC54X-Directives. (line 6) 22009* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 22010* TIC54X options: TIC54X-Opts. (line 6) 22011* TIC54X subsym builtins: TIC54X-Macros. (line 16) 22012* TIC54X support: TIC54X-Dependent. (line 6) 22013* TIC54X-specific macros: TIC54X-Macros. (line 6) 22014* TIC6X big-endian output: TIC6X Options. (line 58) 22015* TIC6X line comment character: TIC6X Syntax. (line 6) 22016* TIC6X line separator: TIC6X Syntax. (line 10) 22017* TIC6X little-endian output: TIC6X Options. (line 58) 22018* TIC6X machine directives: TIC6X Directives. (line 6) 22019* TIC6X options: TIC6X Options. (line 6) 22020* TIC6X support: TIC6X-Dependent. (line 6) 22021* time, total for assembly: statistics. (line 6) 22022* title directive: Title. (line 6) 22023* TMS320C6X support: TIC6X-Dependent. (line 6) 22024* tp register, V850: V850-Regs. (line 20) 22025* transform directive: Transform Directive. (line 6) 22026* trusted compiler: f. (line 6) 22027* turning preprocessing on and off: Preprocessing. (line 27) 22028* type directive (COFF version): Type. (line 11) 22029* type directive (ELF version): Type. (line 22) 22030* type of a symbol: Symbol Type. (line 6) 22031* ualong directive, SH: SH Directives. (line 6) 22032* uaword directive, SH: SH Directives. (line 6) 22033* ubyte directive, TIC54X: TIC54X-Directives. (line 36) 22034* uchar directive, TIC54X: TIC54X-Directives. (line 36) 22035* uhalf directive, TIC54X: TIC54X-Directives. (line 111) 22036* uint directive, TIC54X: TIC54X-Directives. (line 111) 22037* uleb128 directive: Uleb128. (line 6) 22038* ulong directive, TIC54X: TIC54X-Directives. (line 135) 22039* undefined section: Ld Sections. (line 36) 22040* union directive, TIC54X: TIC54X-Directives. (line 250) 22041* unsegm: Z8000 Directives. (line 14) 22042* usect directive, TIC54X: TIC54X-Directives. (line 262) 22043* ushort directive, TIC54X: TIC54X-Directives. (line 111) 22044* uword directive, TIC54X: TIC54X-Directives. (line 111) 22045* V850 command line options: V850 Options. (line 9) 22046* V850 floating point (IEEE): V850 Floating Point. (line 6) 22047* V850 line comment character: V850-Chars. (line 6) 22048* V850 machine directives: V850 Directives. (line 6) 22049* V850 opcodes: V850 Opcodes. (line 6) 22050* V850 options (none): V850 Options. (line 6) 22051* V850 register names: V850-Regs. (line 6) 22052* V850 support: V850-Dependent. (line 6) 22053* val directive: Val. (line 6) 22054* value attribute, COFF: Val. (line 6) 22055* value of a symbol: Symbol Value. (line 6) 22056* var directive, TIC54X: TIC54X-Directives. (line 272) 22057* VAX bitfields not supported: VAX-no. (line 6) 22058* VAX branch improvement: VAX-branch. (line 6) 22059* VAX command-line options ignored: VAX-Opts. (line 6) 22060* VAX displacement sizing character: VAX-operands. (line 12) 22061* VAX floating point: VAX-float. (line 6) 22062* VAX immediate character: VAX-operands. (line 6) 22063* VAX indirect character: VAX-operands. (line 9) 22064* VAX machine directives: VAX-directives. (line 6) 22065* VAX opcode mnemonics: VAX-opcodes. (line 6) 22066* VAX operand notation: VAX-operands. (line 6) 22067* VAX register names: VAX-operands. (line 17) 22068* VAX support: Vax-Dependent. (line 6) 22069* Vax-11 C compatibility: VAX-Opts. (line 42) 22070* VAX/VMS options: VAX-Opts. (line 42) 22071* version directive: Version. (line 6) 22072* version directive, TIC54X: TIC54X-Directives. (line 276) 22073* version of assembler: v. (line 6) 22074* versions of symbols: Symver. (line 6) 22075* visibility <1>: Internal. (line 6) 22076* visibility <2>: Hidden. (line 6) 22077* visibility: Protected. (line 6) 22078* VMS (VAX) options: VAX-Opts. (line 42) 22079* vtable_entry directive: VTableEntry. (line 6) 22080* vtable_inherit directive: VTableInherit. (line 6) 22081* warning directive: Warning. (line 6) 22082* warning for altered difference tables: K. (line 6) 22083* warning messages: Errors. (line 6) 22084* warnings, causing error: W. (line 16) 22085* warnings, M32R: M32R-Warnings. (line 6) 22086* warnings, suppressing: W. (line 11) 22087* warnings, switching on: W. (line 19) 22088* weak directive: Weak. (line 6) 22089* weakref directive: Weakref. (line 6) 22090* whitespace: Whitespace. (line 6) 22091* whitespace, removed by preprocessor: Preprocessing. (line 7) 22092* wide floating point directives, VAX: VAX-directives. (line 10) 22093* width directive, TIC54X: TIC54X-Directives. (line 127) 22094* Width of continuation lines of disassembly output: listing. (line 21) 22095* Width of first line disassembly output: listing. (line 16) 22096* Width of source line output: listing. (line 28) 22097* wmsg directive, TIC54X: TIC54X-Directives. (line 77) 22098* word directive: Word. (line 6) 22099* word directive, ARC: ARC Directives. (line 174) 22100* word directive, H8/300: H8/300 Directives. (line 6) 22101* word directive, i386: i386-Float. (line 21) 22102* word directive, SPARC: Sparc-Directives. (line 51) 22103* word directive, TIC54X: TIC54X-Directives. (line 111) 22104* word directive, x86-64: i386-Float. (line 21) 22105* writing patterns in memory: Fill. (line 6) 22106* wval: Z8000 Directives. (line 24) 22107* x86 machine directives: i386-Directives. (line 6) 22108* x86-64 arch directive: i386-Arch. (line 6) 22109* x86-64 att_syntax pseudo op: i386-Syntax. (line 6) 22110* x86-64 conversion instructions: i386-Mnemonics. (line 37) 22111* x86-64 floating point: i386-Float. (line 6) 22112* x86-64 immediate operands: i386-Syntax. (line 15) 22113* x86-64 instruction naming: i386-Mnemonics. (line 6) 22114* x86-64 intel_syntax pseudo op: i386-Syntax. (line 6) 22115* x86-64 jump optimization: i386-Jumps. (line 6) 22116* x86-64 jump, call, return: i386-Syntax. (line 41) 22117* x86-64 jump/call operands: i386-Syntax. (line 15) 22118* x86-64 memory references: i386-Memory. (line 6) 22119* x86-64 options: i386-Options. (line 6) 22120* x86-64 register operands: i386-Syntax. (line 15) 22121* x86-64 registers: i386-Regs. (line 6) 22122* x86-64 sections: i386-Syntax. (line 47) 22123* x86-64 size suffixes: i386-Syntax. (line 29) 22124* x86-64 source, destination operands: i386-Syntax. (line 22) 22125* x86-64 support: i386-Dependent. (line 6) 22126* x86-64 syntax compatibility: i386-Syntax. (line 6) 22127* xfloat directive, TIC54X: TIC54X-Directives. (line 64) 22128* xlong directive, TIC54X: TIC54X-Directives. (line 135) 22129* Xtensa architecture: Xtensa-Dependent. (line 6) 22130* Xtensa assembler syntax: Xtensa Syntax. (line 6) 22131* Xtensa directives: Xtensa Directives. (line 6) 22132* Xtensa opcode names: Xtensa Opcodes. (line 6) 22133* Xtensa register names: Xtensa Registers. (line 6) 22134* xword directive, SPARC: Sparc-Directives. (line 55) 22135* Z80 $: Z80-Chars. (line 8) 22136* Z80 ': Z80-Chars. (line 13) 22137* Z80 floating point: Z80 Floating Point. (line 6) 22138* Z80 line comment character: Z80-Chars. (line 6) 22139* Z80 options: Z80 Options. (line 6) 22140* Z80 registers: Z80-Regs. (line 6) 22141* Z80 support: Z80-Dependent. (line 6) 22142* Z80 Syntax: Z80 Options. (line 47) 22143* Z80, \: Z80-Chars. (line 11) 22144* Z80, case sensitivity: Z80-Case. (line 6) 22145* Z80-only directives: Z80 Directives. (line 9) 22146* Z800 addressing modes: Z8000-Addressing. (line 6) 22147* Z8000 directives: Z8000 Directives. (line 6) 22148* Z8000 line comment character: Z8000-Chars. (line 6) 22149* Z8000 line separator: Z8000-Chars. (line 8) 22150* Z8000 opcode summary: Z8000 Opcodes. (line 6) 22151* Z8000 options: Z8000 Options. (line 6) 22152* Z8000 registers: Z8000-Regs. (line 6) 22153* Z8000 support: Z8000-Dependent. (line 6) 22154* zdaoff pseudo-op, V850: V850 Opcodes. (line 99) 22155* zero register, V850: V850-Regs. (line 7) 22156* zero-terminated strings: Asciz. (line 6) 22157 22158 22159 22160Tag Table: 22161Node: Top836 22162Node: Overview1824 22163Node: Manual35089 22164Node: GNU Assembler36033 22165Node: Object Formats37204 22166Node: Command Line37656 22167Node: Input Files38743 22168Node: Object40724 22169Node: Errors41620 22170Node: Invoking42815 22171Node: a44770 22172Node: alternate46681 22173Node: D46853 22174Node: f47086 22175Node: I47594 22176Node: K48138 22177Node: L48442 22178Node: listing49181 22179Node: M50840 22180Node: MD55241 22181Node: o55667 22182Node: R56122 22183Node: statistics57152 22184Node: traditional-format57559 22185Node: v58032 22186Node: W58307 22187Node: Z59214 22188Node: Syntax59736 22189Node: Preprocessing60327 22190Node: Whitespace61890 22191Node: Comments62286 22192Node: Symbol Intro64522 22193Node: Statements65212 22194Node: Constants67133 22195Node: Characters67764 22196Node: Strings68266 22197Node: Chars70432 22198Node: Numbers71186 22199Node: Integers71726 22200Node: Bignums72382 22201Node: Flonums72738 22202Node: Sections74485 22203Node: Secs Background74863 22204Node: Ld Sections79902 22205Node: As Sections82286 22206Node: Sub-Sections83196 22207Node: bss86341 22208Node: Symbols87291 22209Node: Labels87939 22210Node: Setting Symbols88670 22211Node: Symbol Names89224 22212Node: Dot94265 22213Node: Symbol Attributes94712 22214Node: Symbol Value95449 22215Node: Symbol Type96494 22216Node: a.out Symbols96882 22217Node: Symbol Desc97144 22218Node: Symbol Other97439 22219Node: COFF Symbols97608 22220Node: SOM Symbols98281 22221Node: Expressions98723 22222Node: Empty Exprs99472 22223Node: Integer Exprs99819 22224Node: Arguments100214 22225Node: Operators101320 22226Node: Prefix Ops101655 22227Node: Infix Ops101983 22228Node: Pseudo Ops104373 22229Node: Abort109874 22230Node: ABORT (COFF)110286 22231Node: Align110494 22232Node: Altmacro112776 22233Node: Ascii114105 22234Node: Asciz114414 22235Node: Balign114659 22236Node: Byte116522 22237Node: CFI directives116770 22238Node: Comm122397 22239Ref: Comm-Footnote-1123998 22240Node: Data124360 22241Node: Def124677 22242Node: Desc124909 22243Node: Dim125409 22244Node: Double125666 22245Node: Eject126004 22246Node: Else126179 22247Node: Elseif126479 22248Node: End126773 22249Node: Endef126988 22250Node: Endfunc127165 22251Node: Endif127340 22252Node: Equ127601 22253Node: Equiv128115 22254Node: Eqv128671 22255Node: Err129035 22256Node: Error129346 22257Node: Exitm129791 22258Node: Extern129960 22259Node: Fail130221 22260Node: File130666 22261Node: Fill131995 22262Node: Float132959 22263Node: Func133301 22264Node: Global133891 22265Node: Gnu_attribute134648 22266Node: Hidden134873 22267Node: hword135459 22268Node: Ident135787 22269Node: If136361 22270Node: Incbin139420 22271Node: Include140115 22272Node: Int140666 22273Node: Internal141047 22274Node: Irp141695 22275Node: Irpc142574 22276Node: Lcomm143491 22277Node: Lflags144239 22278Node: Line144433 22279Node: Linkonce145346 22280Node: List146575 22281Node: Ln147183 22282Node: Loc147333 22283Node: Loc_mark_labels148719 22284Node: Local149203 22285Node: Long149815 22286Node: Macro149993 22287Node: MRI155915 22288Node: Noaltmacro156253 22289Node: Nolist156422 22290Node: Octa156852 22291Node: Org157186 22292Node: P2align158469 22293Node: PopSection160397 22294Node: Previous160905 22295Node: Print162318 22296Node: Protected162547 22297Node: Psize163194 22298Node: Purgem163878 22299Node: PushSection164099 22300Node: Quad164842 22301Node: Reloc165298 22302Node: Rept166059 22303Node: Sbttl166473 22304Node: Scl166838 22305Node: Section167179 22306Node: Set173294 22307Node: Short173865 22308Node: Single174186 22309Node: Size174531 22310Node: Skip175205 22311Node: Sleb128175529 22312Node: Space175853 22313Node: Stab176494 22314Node: String178498 22315Node: Struct179492 22316Node: SubSection180217 22317Node: Symver180780 22318Node: Tag183173 22319Node: Text183555 22320Node: Title183876 22321Node: Type184257 22322Node: Uleb128186551 22323Node: Val186875 22324Node: Version187125 22325Node: VTableEntry187400 22326Node: VTableInherit187690 22327Node: Warning188140 22328Node: Weak188374 22329Node: Weakref189043 22330Node: Word190008 22331Node: Deprecated191854 22332Node: Object Attributes192089 22333Node: GNU Object Attributes193809 22334Node: Defining New Object Attributes196362 22335Node: Machine Dependencies197159 22336Node: Alpha-Dependent200404 22337Node: Alpha Notes200818 22338Node: Alpha Options201099 22339Node: Alpha Syntax203574 22340Node: Alpha-Chars204043 22341Node: Alpha-Regs204274 22342Node: Alpha-Relocs204661 22343Node: Alpha Floating Point210919 22344Node: Alpha Directives211141 22345Node: Alpha Opcodes216664 22346Node: ARC-Dependent216959 22347Node: ARC Options217342 22348Node: ARC Syntax218411 22349Node: ARC-Chars218643 22350Node: ARC-Regs218775 22351Node: ARC Floating Point218899 22352Node: ARC Directives219210 22353Node: ARC Opcodes225182 22354Node: ARM-Dependent225408 22355Node: ARM Options225873 22356Node: ARM Syntax234219 22357Node: ARM-Instruction-Set234587 22358Node: ARM-Chars235819 22359Node: ARM-Regs236371 22360Node: ARM-Neon-Alignment236580 22361Node: ARM Floating Point237044 22362Node: ARM-Relocations237243 22363Node: ARM Directives238235 22364Ref: arm_pad239552 22365Ref: arm_fnend242889 22366Ref: arm_fnstart243213 22367Ref: arm_save246223 22368Ref: arm_setfp246924 22369Node: ARM Opcodes250005 22370Node: ARM Mapping Symbols252093 22371Node: ARM Unwinding Tutorial252903 22372Node: AVR-Dependent259105 22373Node: AVR Options259395 22374Node: AVR Syntax262898 22375Node: AVR-Chars263185 22376Node: AVR-Regs263591 22377Node: AVR-Modifiers264170 22378Node: AVR Opcodes266230 22379Node: Blackfin-Dependent271476 22380Node: Blackfin Options271788 22381Node: Blackfin Syntax272762 22382Node: Blackfin Directives278495 22383Node: CR16-Dependent278914 22384Node: CR16 Operand Qualifiers279162 22385Node: CRIS-Dependent281803 22386Node: CRIS-Opts282149 22387Ref: march-option283767 22388Node: CRIS-Expand285584 22389Node: CRIS-Symbols286767 22390Node: CRIS-Syntax287936 22391Node: CRIS-Chars288272 22392Node: CRIS-Pic288823 22393Ref: crispic289019 22394Node: CRIS-Regs292559 22395Node: CRIS-Pseudos292976 22396Ref: crisnous293752 22397Node: D10V-Dependent295034 22398Node: D10V-Opts295385 22399Node: D10V-Syntax296347 22400Node: D10V-Size296876 22401Node: D10V-Subs297849 22402Node: D10V-Chars298884 22403Node: D10V-Regs300488 22404Node: D10V-Addressing301533 22405Node: D10V-Word302219 22406Node: D10V-Float302734 22407Node: D10V-Opcodes303045 22408Node: D30V-Dependent303438 22409Node: D30V-Opts303791 22410Node: D30V-Syntax304466 22411Node: D30V-Size304998 22412Node: D30V-Subs305969 22413Node: D30V-Chars307004 22414Node: D30V-Guarded309302 22415Node: D30V-Regs309982 22416Node: D30V-Addressing311121 22417Node: D30V-Float311789 22418Node: D30V-Opcodes312100 22419Node: H8/300-Dependent312493 22420Node: H8/300 Options312905 22421Node: H8/300 Syntax313172 22422Node: H8/300-Chars313473 22423Node: H8/300-Regs313772 22424Node: H8/300-Addressing314691 22425Node: H8/300 Floating Point315732 22426Node: H8/300 Directives316059 22427Node: H8/300 Opcodes317187 22428Node: HPPA-Dependent325509 22429Node: HPPA Notes325944 22430Node: HPPA Options326702 22431Node: HPPA Syntax326897 22432Node: HPPA Floating Point328167 22433Node: HPPA Directives328373 22434Node: HPPA Opcodes337059 22435Node: ESA/390-Dependent337318 22436Node: ESA/390 Notes337778 22437Node: ESA/390 Options338569 22438Node: ESA/390 Syntax338779 22439Node: ESA/390 Floating Point340952 22440Node: ESA/390 Directives341231 22441Node: ESA/390 Opcodes344520 22442Node: i386-Dependent344782 22443Node: i386-Options345979 22444Node: i386-Directives350345 22445Node: i386-Syntax351083 22446Node: i386-Mnemonics353647 22447Node: i386-Regs356940 22448Node: i386-Prefixes358985 22449Node: i386-Memory361745 22450Node: i386-Jumps364682 22451Node: i386-Float365803 22452Node: i386-SIMD367634 22453Node: i386-LWP368743 22454Node: i386-16bit369579 22455Node: i386-Bugs371650 22456Node: i386-Arch372404 22457Node: i386-Notes375065 22458Node: i860-Dependent375923 22459Node: Notes-i860376319 22460Node: Options-i860377224 22461Node: Directives-i860378587 22462Node: Opcodes for i860379656 22463Node: i960-Dependent381823 22464Node: Options-i960382226 22465Node: Floating Point-i960386111 22466Node: Directives-i960386379 22467Node: Opcodes for i960388413 22468Node: callj-i960389030 22469Node: Compare-and-branch-i960389519 22470Node: IA-64-Dependent391423 22471Node: IA-64 Options391724 22472Node: IA-64 Syntax394875 22473Node: IA-64-Chars395281 22474Node: IA-64-Regs395511 22475Node: IA-64-Bits396437 22476Node: IA-64-Relocs396967 22477Node: IA-64 Opcodes397439 22478Node: IP2K-Dependent397711 22479Node: IP2K-Opts397939 22480Node: LM32-Dependent398419 22481Node: LM32 Options398714 22482Node: LM32 Syntax399348 22483Node: LM32-Regs399595 22484Node: LM32-Modifiers400554 22485Node: LM32 Opcodes401910 22486Node: M32C-Dependent402214 22487Node: M32C-Opts402738 22488Node: M32C-Modifiers403161 22489Node: M32R-Dependent404948 22490Node: M32R-Opts405269 22491Node: M32R-Directives409436 22492Node: M32R-Warnings413411 22493Node: M68K-Dependent416417 22494Node: M68K-Opts416884 22495Node: M68K-Syntax424257 22496Node: M68K-Moto-Syntax426097 22497Node: M68K-Float428687 22498Node: M68K-Directives429207 22499Node: M68K-opcodes430535 22500Node: M68K-Branch430761 22501Node: M68K-Chars434959 22502Node: M68HC11-Dependent435372 22503Node: M68HC11-Opts435909 22504Node: M68HC11-Syntax439730 22505Node: M68HC11-Modifiers441944 22506Node: M68HC11-Directives443772 22507Node: M68HC11-Float445148 22508Node: M68HC11-opcodes445676 22509Node: M68HC11-Branch445858 22510Node: MicroBlaze-Dependent448307 22511Node: MicroBlaze Directives448937 22512Node: MIPS-Dependent450294 22513Node: MIPS Opts451457 22514Node: MIPS Object461969 22515Node: MIPS Stabs463535 22516Node: MIPS symbol sizes464257 22517Node: MIPS ISA465926 22518Node: MIPS autoextend467400 22519Node: MIPS insn468130 22520Node: MIPS option stack469400 22521Node: MIPS ASE instruction generation overrides470174 22522Node: MIPS floating-point471988 22523Node: MMIX-Dependent472874 22524Node: MMIX-Opts473254 22525Node: MMIX-Expand476858 22526Node: MMIX-Syntax478173 22527Ref: mmixsite478530 22528Node: MMIX-Chars479371 22529Node: MMIX-Symbols480025 22530Node: MMIX-Regs482093 22531Node: MMIX-Pseudos483118 22532Ref: MMIX-loc483259 22533Ref: MMIX-local484339 22534Ref: MMIX-is484871 22535Ref: MMIX-greg485142 22536Ref: GREG-base486061 22537Ref: MMIX-byte487378 22538Ref: MMIX-constants487849 22539Ref: MMIX-prefix488495 22540Ref: MMIX-spec488869 22541Node: MMIX-mmixal489203 22542Node: MSP430-Dependent492701 22543Node: MSP430 Options493167 22544Node: MSP430 Syntax493453 22545Node: MSP430-Macros493769 22546Node: MSP430-Chars494500 22547Node: MSP430-Regs494813 22548Node: MSP430-Ext495373 22549Node: MSP430 Floating Point497194 22550Node: MSP430 Directives497418 22551Node: MSP430 Opcodes498209 22552Node: MSP430 Profiling Capability498604 22553Node: PDP-11-Dependent500933 22554Node: PDP-11-Options501322 22555Node: PDP-11-Pseudos506393 22556Node: PDP-11-Syntax506738 22557Node: PDP-11-Mnemonics507490 22558Node: PDP-11-Synthetic507792 22559Node: PJ-Dependent508010 22560Node: PJ Options508235 22561Node: PPC-Dependent508512 22562Node: PowerPC-Opts508796 22563Node: PowerPC-Pseudo511925 22564Node: RX-Dependent512524 22565Node: RX-Opts512917 22566Node: RX-Modifiers514943 22567Node: RX-Directives515274 22568Node: RX-Float515590 22569Node: S/390-Dependent516213 22570Node: s390 Options516921 22571Node: s390 Characters518467 22572Node: s390 Syntax518660 22573Node: s390 Register519561 22574Node: s390 Mnemonics520374 22575Node: s390 Operands523394 22576Node: s390 Formats526013 22577Node: s390 Aliases533884 22578Node: s390 Operand Modifier537781 22579Node: s390 Instruction Marker541582 22580Node: s390 Literal Pool Entries542598 22581Node: s390 Directives544521 22582Node: s390 Floating Point548949 22583Node: SCORE-Dependent549395 22584Node: SCORE-Opts549669 22585Node: SCORE-Pseudo550957 22586Node: SH-Dependent553013 22587Node: SH Options553425 22588Node: SH Syntax554480 22589Node: SH-Chars554753 22590Node: SH-Regs555047 22591Node: SH-Addressing555661 22592Node: SH Floating Point556570 22593Node: SH Directives557664 22594Node: SH Opcodes558034 22595Node: SH64-Dependent562356 22596Node: SH64 Options562719 22597Node: SH64 Syntax564516 22598Node: SH64-Chars564799 22599Node: SH64-Regs565099 22600Node: SH64-Addressing566195 22601Node: SH64 Directives567378 22602Node: SH64 Opcodes568488 22603Node: Sparc-Dependent569204 22604Node: Sparc-Opts569616 22605Node: Sparc-Aligned-Data571873 22606Node: Sparc-Syntax572705 22607Node: Sparc-Chars573279 22608Node: Sparc-Regs573512 22609Node: Sparc-Constants578623 22610Node: Sparc-Relocs583383 22611Node: Sparc-Size-Translations588063 22612Node: Sparc-Float589712 22613Node: Sparc-Directives589907 22614Node: TIC54X-Dependent591867 22615Node: TIC54X-Opts592594 22616Node: TIC54X-Block593637 22617Node: TIC54X-Env593997 22618Node: TIC54X-Constants594345 22619Node: TIC54X-Subsyms594747 22620Node: TIC54X-Locals596656 22621Node: TIC54X-Builtins597400 22622Node: TIC54X-Ext599871 22623Node: TIC54X-Directives600442 22624Node: TIC54X-Macros611343 22625Node: TIC54X-MMRegs613454 22626Node: TIC6X-Dependent613670 22627Node: TIC6X Options613970 22628Node: TIC6X Syntax616588 22629Node: TIC6X Directives617512 22630Node: Z80-Dependent618581 22631Node: Z80 Options618969 22632Node: Z80 Syntax620392 22633Node: Z80-Chars621064 22634Node: Z80-Regs621598 22635Node: Z80-Case621950 22636Node: Z80 Floating Point622395 22637Node: Z80 Directives622589 22638Node: Z80 Opcodes624214 22639Node: Z8000-Dependent625558 22640Node: Z8000 Options626519 22641Node: Z8000 Syntax626736 22642Node: Z8000-Chars627026 22643Node: Z8000-Regs627259 22644Node: Z8000-Addressing628049 22645Node: Z8000 Directives629166 22646Node: Z8000 Opcodes630775 22647Node: Vax-Dependent640717 22648Node: VAX-Opts641234 22649Node: VAX-float644969 22650Node: VAX-directives645601 22651Node: VAX-opcodes646462 22652Node: VAX-branch646851 22653Node: VAX-operands649358 22654Node: VAX-no650121 22655Node: V850-Dependent650358 22656Node: V850 Options650755 22657Node: V850 Syntax653606 22658Node: V850-Chars653846 22659Node: V850-Regs654011 22660Node: V850 Floating Point655579 22661Node: V850 Directives655785 22662Node: V850 Opcodes657388 22663Node: Xtensa-Dependent663280 22664Node: Xtensa Options664009 22665Node: Xtensa Syntax666819 22666Node: Xtensa Opcodes668708 22667Node: Xtensa Registers670502 22668Node: Xtensa Optimizations671135 22669Node: Density Instructions671587 22670Node: Xtensa Automatic Alignment672689 22671Node: Xtensa Relaxation675136 22672Node: Xtensa Branch Relaxation676044 22673Node: Xtensa Call Relaxation677416 22674Node: Xtensa Immediate Relaxation679202 22675Node: Xtensa Directives681776 22676Node: Schedule Directive683485 22677Node: Longcalls Directive683825 22678Node: Transform Directive684369 22679Node: Literal Directive685111 22680Ref: Literal Directive-Footnote-1688650 22681Node: Literal Position Directive688792 22682Node: Literal Prefix Directive690491 22683Node: Absolute Literals Directive691389 22684Node: Reporting Bugs692696 22685Node: Bug Criteria693422 22686Node: Bug Reporting694189 22687Node: Acknowledgements700838 22688Ref: Acknowledgements-Footnote-1705804 22689Node: GNU Free Documentation License705830 22690Node: AS Index730999 22691 22692End Tag Table 22693