1 /* tc-xtensa.c -- Assemble Xtensa instructions. 2 Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 3 Free Software Foundation, Inc. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include <limits.h> 23 #include "as.h" 24 #include "sb.h" 25 #include "safe-ctype.h" 26 #include "tc-xtensa.h" 27 #include "subsegs.h" 28 #include "xtensa-relax.h" 29 #include "dwarf2dbg.h" 30 #include "xtensa-istack.h" 31 #include "struc-symbol.h" 32 #include "xtensa-config.h" 33 34 /* Provide default values for new configuration settings. */ 35 #ifndef XSHAL_ABI 36 #define XSHAL_ABI 0 37 #endif 38 39 #ifndef uint32 40 #define uint32 unsigned int 41 #endif 42 #ifndef int32 43 #define int32 signed int 44 #endif 45 46 /* Notes: 47 48 Naming conventions (used somewhat inconsistently): 49 The xtensa_ functions are exported 50 The xg_ functions are internal 51 52 We also have a couple of different extensibility mechanisms. 53 1) The idiom replacement: 54 This is used when a line is first parsed to 55 replace an instruction pattern with another instruction 56 It is currently limited to replacements of instructions 57 with constant operands. 58 2) The xtensa-relax.c mechanism that has stronger instruction 59 replacement patterns. When an instruction's immediate field 60 does not fit the next instruction sequence is attempted. 61 In addition, "narrow" opcodes are supported this way. */ 62 63 64 /* Define characters with special meanings to GAS. */ 65 const char comment_chars[] = "#"; 66 const char line_comment_chars[] = "#"; 67 const char line_separator_chars[] = ";"; 68 const char EXP_CHARS[] = "eE"; 69 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 70 71 72 /* Flags to indicate whether the hardware supports the density and 73 absolute literals options. */ 74 75 bfd_boolean density_supported = XCHAL_HAVE_DENSITY; 76 bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; 77 78 static vliw_insn cur_vinsn; 79 80 unsigned xtensa_num_pipe_stages; 81 unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; 82 83 static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; 84 85 /* Some functions are only valid in the front end. This variable 86 allows us to assert that we haven't crossed over into the 87 back end. */ 88 static bfd_boolean past_xtensa_end = FALSE; 89 90 /* Flags for properties of the last instruction in a segment. */ 91 #define FLAG_IS_A0_WRITER 0x1 92 #define FLAG_IS_BAD_LOOPEND 0x2 93 94 95 /* We define a special segment names ".literal" to place literals 96 into. The .fini and .init sections are special because they 97 contain code that is moved together by the linker. We give them 98 their own special .fini.literal and .init.literal sections. */ 99 100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") 101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") 102 #define INIT_SECTION_NAME xtensa_section_rename (".init") 103 #define FINI_SECTION_NAME xtensa_section_rename (".fini") 104 105 106 /* This type is used for the directive_stack to keep track of the 107 state of the literal collection pools. If lit_prefix is set, it is 108 used to determine the literal section names; otherwise, the literal 109 sections are determined based on the current text section. The 110 lit_seg and lit4_seg fields cache these literal sections, with the 111 current_text_seg field used a tag to indicate whether the cached 112 values are valid. */ 113 114 typedef struct lit_state_struct 115 { 116 char *lit_prefix; 117 segT current_text_seg; 118 segT lit_seg; 119 segT lit4_seg; 120 } lit_state; 121 122 static lit_state default_lit_sections; 123 124 125 /* We keep a list of literal segments. The seg_list type is the node 126 for this list. The literal_head pointer is the head of the list, 127 with the literal_head_h dummy node at the start. */ 128 129 typedef struct seg_list_struct 130 { 131 struct seg_list_struct *next; 132 segT seg; 133 } seg_list; 134 135 static seg_list literal_head_h; 136 static seg_list *literal_head = &literal_head_h; 137 138 139 /* Lists of symbols. We keep a list of symbols that label the current 140 instruction, so that we can adjust the symbols when inserting alignment 141 for various instructions. We also keep a list of all the symbols on 142 literals, so that we can fix up those symbols when the literals are 143 later moved into the text sections. */ 144 145 typedef struct sym_list_struct 146 { 147 struct sym_list_struct *next; 148 symbolS *sym; 149 } sym_list; 150 151 static sym_list *insn_labels = NULL; 152 static sym_list *free_insn_labels = NULL; 153 static sym_list *saved_insn_labels = NULL; 154 155 static sym_list *literal_syms; 156 157 158 /* Flags to determine whether to prefer const16 or l32r 159 if both options are available. */ 160 int prefer_const16 = 0; 161 int prefer_l32r = 0; 162 163 /* Global flag to indicate when we are emitting literals. */ 164 int generating_literals = 0; 165 166 /* The following PROPERTY table definitions are copied from 167 <elf/xtensa.h> and must be kept in sync with the code there. */ 168 169 /* Flags in the property tables to specify whether blocks of memory 170 are literals, instructions, data, or unreachable. For 171 instructions, blocks that begin loop targets and branch targets are 172 designated. Blocks that do not allow density, instruction 173 reordering or transformation are also specified. Finally, for 174 branch targets, branch target alignment priority is included. 175 Alignment of the next block is specified in the current block 176 and the size of the current block does not include any fill required 177 to align to the next block. */ 178 179 #define XTENSA_PROP_LITERAL 0x00000001 180 #define XTENSA_PROP_INSN 0x00000002 181 #define XTENSA_PROP_DATA 0x00000004 182 #define XTENSA_PROP_UNREACHABLE 0x00000008 183 /* Instruction only properties at beginning of code. */ 184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 186 /* Instruction only properties about code. */ 187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 189 /* Historically, NO_TRANSFORM was a property of instructions, 190 but it should apply to literals under certain circumstances. */ 191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100 192 193 /* Branch target alignment information. This transmits information 194 to the linker optimization about the priority of aligning a 195 particular block for branch target alignment: None, low priority, 196 high priority, or required. These only need to be checked in 197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. 198 Common usage is 199 200 switch (GET_XTENSA_PROP_BT_ALIGN (flags)) 201 case XTENSA_PROP_BT_ALIGN_NONE: 202 case XTENSA_PROP_BT_ALIGN_LOW: 203 case XTENSA_PROP_BT_ALIGN_HIGH: 204 case XTENSA_PROP_BT_ALIGN_REQUIRE: 205 */ 206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 207 208 /* No branch target alignment. */ 209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0 210 /* Low priority branch target alignment. */ 211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1 212 /* High priority branch target alignment. */ 213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 214 /* Required branch target alignment. */ 215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 216 217 #define GET_XTENSA_PROP_BT_ALIGN(flag) \ 218 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) 219 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ 220 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ 221 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) 222 223 224 /* Alignment is specified in the block BEFORE the one that needs 225 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to 226 get the required alignment specified as a power of 2. Use 227 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required 228 alignment. Be careful of side effects since the SET will evaluate 229 flags twice. Also, note that the SIZE of a block in the property 230 table does not include the alignment size, so the alignment fill 231 must be calculated to determine if two blocks are contiguous. 232 TEXT_ALIGN is not currently implemented but is a placeholder for a 233 possible future implementation. */ 234 235 #define XTENSA_PROP_ALIGN 0x00000800 236 237 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 238 239 #define GET_XTENSA_PROP_ALIGNMENT(flag) \ 240 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) 241 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ 242 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ 243 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) 244 245 #define XTENSA_PROP_INSN_ABSLIT 0x00020000 246 247 248 /* Structure for saving instruction and alignment per-fragment data 249 that will be written to the object file. This structure is 250 equivalent to the actual data that will be written out to the file 251 but is easier to use. We provide a conversion to file flags 252 in frag_flags_to_number. */ 253 254 typedef struct frag_flags_struct frag_flags; 255 256 struct frag_flags_struct 257 { 258 /* is_literal should only be used after xtensa_move_literals. 259 If you need to check if you are generating a literal fragment, 260 then use the generating_literals global. */ 261 262 unsigned is_literal : 1; 263 unsigned is_insn : 1; 264 unsigned is_data : 1; 265 unsigned is_unreachable : 1; 266 267 /* is_specific_opcode implies no_transform. */ 268 unsigned is_no_transform : 1; 269 270 struct 271 { 272 unsigned is_loop_target : 1; 273 unsigned is_branch_target : 1; /* Branch targets have a priority. */ 274 unsigned bt_align_priority : 2; 275 276 unsigned is_no_density : 1; 277 /* no_longcalls flag does not need to be placed in the object file. */ 278 279 unsigned is_no_reorder : 1; 280 281 /* Uses absolute literal addressing for l32r. */ 282 unsigned is_abslit : 1; 283 } insn; 284 unsigned is_align : 1; 285 unsigned alignment : 5; 286 }; 287 288 289 /* Structure for saving information about a block of property data 290 for frags that have the same flags. */ 291 struct xtensa_block_info_struct 292 { 293 segT sec; 294 bfd_vma offset; 295 size_t size; 296 frag_flags flags; 297 struct xtensa_block_info_struct *next; 298 }; 299 300 301 /* Structure for saving the current state before emitting literals. */ 302 typedef struct emit_state_struct 303 { 304 const char *name; 305 segT now_seg; 306 subsegT now_subseg; 307 int generating_literals; 308 } emit_state; 309 310 311 /* Opcode placement information */ 312 313 typedef unsigned long long bitfield; 314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) 315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) 316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) 317 318 #define MAX_FORMATS 32 319 320 typedef struct op_placement_info_struct 321 { 322 int num_formats; 323 /* A number describing how restrictive the issue is for this 324 opcode. For example, an opcode that fits lots of different 325 formats has a high freedom, as does an opcode that fits 326 only one format but many slots in that format. The most 327 restrictive is the opcode that fits only one slot in one 328 format. */ 329 int issuef; 330 xtensa_format narrowest; 331 char narrowest_size; 332 char narrowest_slot; 333 334 /* formats is a bitfield with the Nth bit set 335 if the opcode fits in the Nth xtensa_format. */ 336 bitfield formats; 337 338 /* slots[N]'s Mth bit is set if the op fits in the 339 Mth slot of the Nth xtensa_format. */ 340 bitfield slots[MAX_FORMATS]; 341 342 /* A count of the number of slots in a given format 343 an op can fit (i.e., the bitcount of the slot field above). */ 344 char slots_in_format[MAX_FORMATS]; 345 346 } op_placement_info, *op_placement_info_table; 347 348 op_placement_info_table op_placement_table; 349 350 351 /* Extra expression types. */ 352 353 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ 354 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ 355 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ 356 #define O_pcrel O_md4 /* value is a PC-relative offset */ 357 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */ 358 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */ 359 #define O_tlscall O_md7 /* TLS_CALL relocation */ 360 #define O_tpoff O_md8 /* TPOFF relocation */ 361 #define O_dtpoff O_md9 /* DTPOFF relocation */ 362 363 struct suffix_reloc_map 364 { 365 char *suffix; 366 int length; 367 bfd_reloc_code_real_type reloc; 368 unsigned char operator; 369 }; 370 371 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op } 372 373 static struct suffix_reloc_map suffix_relocs[] = 374 { 375 SUFFIX_MAP ("l", BFD_RELOC_LO16, O_lo16), 376 SUFFIX_MAP ("h", BFD_RELOC_HI16, O_hi16), 377 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT, O_pltrel), 378 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL, O_pcrel), 379 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC, O_tlsfunc), 380 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG, O_tlsarg), 381 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL, O_tlscall), 382 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF, O_tpoff), 383 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF, O_dtpoff), 384 { (char *) 0, 0, BFD_RELOC_UNUSED, 0 } 385 }; 386 387 388 /* Directives. */ 389 390 typedef enum 391 { 392 directive_none = 0, 393 directive_literal, 394 directive_density, 395 directive_transform, 396 directive_freeregs, 397 directive_longcalls, 398 directive_literal_prefix, 399 directive_schedule, 400 directive_absolute_literals, 401 directive_last_directive 402 } directiveE; 403 404 typedef struct 405 { 406 const char *name; 407 bfd_boolean can_be_negated; 408 } directive_infoS; 409 410 const directive_infoS directive_info[] = 411 { 412 { "none", FALSE }, 413 { "literal", FALSE }, 414 { "density", TRUE }, 415 { "transform", TRUE }, 416 { "freeregs", FALSE }, 417 { "longcalls", TRUE }, 418 { "literal_prefix", FALSE }, 419 { "schedule", TRUE }, 420 { "absolute-literals", TRUE } 421 }; 422 423 bfd_boolean directive_state[] = 424 { 425 FALSE, /* none */ 426 FALSE, /* literal */ 427 #if !XCHAL_HAVE_DENSITY 428 FALSE, /* density */ 429 #else 430 TRUE, /* density */ 431 #endif 432 TRUE, /* transform */ 433 FALSE, /* freeregs */ 434 FALSE, /* longcalls */ 435 FALSE, /* literal_prefix */ 436 FALSE, /* schedule */ 437 #if XSHAL_USE_ABSOLUTE_LITERALS 438 TRUE /* absolute_literals */ 439 #else 440 FALSE /* absolute_literals */ 441 #endif 442 }; 443 444 445 /* Directive functions. */ 446 447 static void xtensa_begin_directive (int); 448 static void xtensa_end_directive (int); 449 static void xtensa_literal_prefix (void); 450 static void xtensa_literal_position (int); 451 static void xtensa_literal_pseudo (int); 452 static void xtensa_frequency_pseudo (int); 453 static void xtensa_elf_cons (int); 454 static void xtensa_leb128 (int); 455 456 /* Parsing and Idiom Translation. */ 457 458 static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); 459 460 /* Various Other Internal Functions. */ 461 462 extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); 463 static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); 464 static void xtensa_mark_literal_pool_location (void); 465 static addressT get_expanded_loop_offset (xtensa_opcode); 466 static fragS *get_literal_pool_location (segT); 467 static void set_literal_pool_location (segT, fragS *); 468 static void xtensa_set_frag_assembly_state (fragS *); 469 static void finish_vinsn (vliw_insn *); 470 static bfd_boolean emit_single_op (TInsn *); 471 static int total_frag_text_expansion (fragS *); 472 473 /* Alignment Functions. */ 474 475 static int get_text_align_power (unsigned); 476 static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); 477 static int branch_align_power (segT); 478 479 /* Helpers for xtensa_relax_frag(). */ 480 481 static long relax_frag_add_nop (fragS *); 482 483 /* Accessors for additional per-subsegment information. */ 484 485 static unsigned get_last_insn_flags (segT, subsegT); 486 static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); 487 static float get_subseg_total_freq (segT, subsegT); 488 static float get_subseg_target_freq (segT, subsegT); 489 static void set_subseg_freq (segT, subsegT, float, float); 490 491 /* Segment list functions. */ 492 493 static void xtensa_move_literals (void); 494 static void xtensa_reorder_segments (void); 495 static void xtensa_switch_to_literal_fragment (emit_state *); 496 static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); 497 static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); 498 static void xtensa_restore_emit_state (emit_state *); 499 static segT cache_literal_section (bfd_boolean); 500 501 /* Import from elf32-xtensa.c in BFD library. */ 502 503 extern asection *xtensa_make_property_section (asection *, const char *); 504 505 /* op_placement_info functions. */ 506 507 static void init_op_placement_info_table (void); 508 extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); 509 static int xg_get_single_size (xtensa_opcode); 510 static xtensa_format xg_get_single_format (xtensa_opcode); 511 static int xg_get_single_slot (xtensa_opcode); 512 513 /* TInsn and IStack functions. */ 514 515 static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); 516 static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); 517 static bfd_boolean tinsn_has_complex_operands (const TInsn *); 518 static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); 519 static bfd_boolean tinsn_check_arguments (const TInsn *); 520 static void tinsn_from_chars (TInsn *, char *, int); 521 static void tinsn_immed_from_frag (TInsn *, fragS *, int); 522 static int get_num_stack_text_bytes (IStack *); 523 static int get_num_stack_literal_bytes (IStack *); 524 525 /* vliw_insn functions. */ 526 527 static void xg_init_vinsn (vliw_insn *); 528 static void xg_copy_vinsn (vliw_insn *, vliw_insn *); 529 static void xg_clear_vinsn (vliw_insn *); 530 static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); 531 static void xg_free_vinsn (vliw_insn *); 532 static bfd_boolean vinsn_to_insnbuf 533 (vliw_insn *, char *, fragS *, bfd_boolean); 534 static void vinsn_from_chars (vliw_insn *, char *); 535 536 /* Expression Utilities. */ 537 538 bfd_boolean expr_is_const (const expressionS *); 539 offsetT get_expr_const (const expressionS *); 540 void set_expr_const (expressionS *, offsetT); 541 bfd_boolean expr_is_register (const expressionS *); 542 offsetT get_expr_register (const expressionS *); 543 void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); 544 bfd_boolean expr_is_equal (expressionS *, expressionS *); 545 static void copy_expr (expressionS *, const expressionS *); 546 547 /* Section renaming. */ 548 549 static void build_section_rename (const char *); 550 551 552 /* ISA imported from bfd. */ 553 extern xtensa_isa xtensa_default_isa; 554 555 extern int target_big_endian; 556 557 static xtensa_opcode xtensa_addi_opcode; 558 static xtensa_opcode xtensa_addmi_opcode; 559 static xtensa_opcode xtensa_call0_opcode; 560 static xtensa_opcode xtensa_call4_opcode; 561 static xtensa_opcode xtensa_call8_opcode; 562 static xtensa_opcode xtensa_call12_opcode; 563 static xtensa_opcode xtensa_callx0_opcode; 564 static xtensa_opcode xtensa_callx4_opcode; 565 static xtensa_opcode xtensa_callx8_opcode; 566 static xtensa_opcode xtensa_callx12_opcode; 567 static xtensa_opcode xtensa_const16_opcode; 568 static xtensa_opcode xtensa_entry_opcode; 569 static xtensa_opcode xtensa_extui_opcode; 570 static xtensa_opcode xtensa_movi_opcode; 571 static xtensa_opcode xtensa_movi_n_opcode; 572 static xtensa_opcode xtensa_isync_opcode; 573 static xtensa_opcode xtensa_j_opcode; 574 static xtensa_opcode xtensa_jx_opcode; 575 static xtensa_opcode xtensa_l32r_opcode; 576 static xtensa_opcode xtensa_loop_opcode; 577 static xtensa_opcode xtensa_loopnez_opcode; 578 static xtensa_opcode xtensa_loopgtz_opcode; 579 static xtensa_opcode xtensa_nop_opcode; 580 static xtensa_opcode xtensa_nop_n_opcode; 581 static xtensa_opcode xtensa_or_opcode; 582 static xtensa_opcode xtensa_ret_opcode; 583 static xtensa_opcode xtensa_ret_n_opcode; 584 static xtensa_opcode xtensa_retw_opcode; 585 static xtensa_opcode xtensa_retw_n_opcode; 586 static xtensa_opcode xtensa_rsr_lcount_opcode; 587 static xtensa_opcode xtensa_waiti_opcode; 588 static int config_max_slots = 0; 589 590 591 /* Command-line Options. */ 592 593 bfd_boolean use_literal_section = TRUE; 594 enum flix_level produce_flix = FLIX_ALL; 595 static bfd_boolean align_targets = TRUE; 596 static bfd_boolean warn_unaligned_branch_targets = FALSE; 597 static bfd_boolean has_a0_b_retw = FALSE; 598 static bfd_boolean workaround_a0_b_retw = FALSE; 599 static bfd_boolean workaround_b_j_loop_end = FALSE; 600 static bfd_boolean workaround_short_loop = FALSE; 601 static bfd_boolean maybe_has_short_loop = FALSE; 602 static bfd_boolean workaround_close_loop_end = FALSE; 603 static bfd_boolean maybe_has_close_loop_end = FALSE; 604 static bfd_boolean enforce_three_byte_loop_align = FALSE; 605 606 /* When workaround_short_loops is TRUE, all loops with early exits must 607 have at least 3 instructions. workaround_all_short_loops is a modifier 608 to the workaround_short_loop flag. In addition to the 609 workaround_short_loop actions, all straightline loopgtz and loopnez 610 must have at least 3 instructions. */ 611 612 static bfd_boolean workaround_all_short_loops = FALSE; 613 614 615 static void 616 xtensa_setup_hw_workarounds (int earliest, int latest) 617 { 618 if (earliest > latest) 619 as_fatal (_("illegal range of target hardware versions")); 620 621 /* Enable all workarounds for pre-T1050.0 hardware. */ 622 if (earliest < 105000 || latest < 105000) 623 { 624 workaround_a0_b_retw |= TRUE; 625 workaround_b_j_loop_end |= TRUE; 626 workaround_short_loop |= TRUE; 627 workaround_close_loop_end |= TRUE; 628 workaround_all_short_loops |= TRUE; 629 enforce_three_byte_loop_align = TRUE; 630 } 631 } 632 633 634 enum 635 { 636 option_density = OPTION_MD_BASE, 637 option_no_density, 638 639 option_flix, 640 option_no_generate_flix, 641 option_no_flix, 642 643 option_relax, 644 option_no_relax, 645 646 option_link_relax, 647 option_no_link_relax, 648 649 option_generics, 650 option_no_generics, 651 652 option_transform, 653 option_no_transform, 654 655 option_text_section_literals, 656 option_no_text_section_literals, 657 658 option_absolute_literals, 659 option_no_absolute_literals, 660 661 option_align_targets, 662 option_no_align_targets, 663 664 option_warn_unaligned_targets, 665 666 option_longcalls, 667 option_no_longcalls, 668 669 option_workaround_a0_b_retw, 670 option_no_workaround_a0_b_retw, 671 672 option_workaround_b_j_loop_end, 673 option_no_workaround_b_j_loop_end, 674 675 option_workaround_short_loop, 676 option_no_workaround_short_loop, 677 678 option_workaround_all_short_loops, 679 option_no_workaround_all_short_loops, 680 681 option_workaround_close_loop_end, 682 option_no_workaround_close_loop_end, 683 684 option_no_workarounds, 685 686 option_rename_section_name, 687 688 option_prefer_l32r, 689 option_prefer_const16, 690 691 option_target_hardware 692 }; 693 694 const char *md_shortopts = ""; 695 696 struct option md_longopts[] = 697 { 698 { "density", no_argument, NULL, option_density }, 699 { "no-density", no_argument, NULL, option_no_density }, 700 701 { "flix", no_argument, NULL, option_flix }, 702 { "no-generate-flix", no_argument, NULL, option_no_generate_flix }, 703 { "no-allow-flix", no_argument, NULL, option_no_flix }, 704 705 /* Both "relax" and "generics" are deprecated and treated as equivalent 706 to the "transform" option. */ 707 { "relax", no_argument, NULL, option_relax }, 708 { "no-relax", no_argument, NULL, option_no_relax }, 709 { "generics", no_argument, NULL, option_generics }, 710 { "no-generics", no_argument, NULL, option_no_generics }, 711 712 { "transform", no_argument, NULL, option_transform }, 713 { "no-transform", no_argument, NULL, option_no_transform }, 714 { "text-section-literals", no_argument, NULL, option_text_section_literals }, 715 { "no-text-section-literals", no_argument, NULL, 716 option_no_text_section_literals }, 717 { "absolute-literals", no_argument, NULL, option_absolute_literals }, 718 { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, 719 /* This option was changed from -align-target to -target-align 720 because it conflicted with the "-al" option. */ 721 { "target-align", no_argument, NULL, option_align_targets }, 722 { "no-target-align", no_argument, NULL, option_no_align_targets }, 723 { "warn-unaligned-targets", no_argument, NULL, 724 option_warn_unaligned_targets }, 725 { "longcalls", no_argument, NULL, option_longcalls }, 726 { "no-longcalls", no_argument, NULL, option_no_longcalls }, 727 728 { "no-workaround-a0-b-retw", no_argument, NULL, 729 option_no_workaround_a0_b_retw }, 730 { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, 731 732 { "no-workaround-b-j-loop-end", no_argument, NULL, 733 option_no_workaround_b_j_loop_end }, 734 { "workaround-b-j-loop-end", no_argument, NULL, 735 option_workaround_b_j_loop_end }, 736 737 { "no-workaround-short-loops", no_argument, NULL, 738 option_no_workaround_short_loop }, 739 { "workaround-short-loops", no_argument, NULL, 740 option_workaround_short_loop }, 741 742 { "no-workaround-all-short-loops", no_argument, NULL, 743 option_no_workaround_all_short_loops }, 744 { "workaround-all-short-loop", no_argument, NULL, 745 option_workaround_all_short_loops }, 746 747 { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, 748 { "prefer-const16", no_argument, NULL, option_prefer_const16 }, 749 750 { "no-workarounds", no_argument, NULL, option_no_workarounds }, 751 752 { "no-workaround-close-loop-end", no_argument, NULL, 753 option_no_workaround_close_loop_end }, 754 { "workaround-close-loop-end", no_argument, NULL, 755 option_workaround_close_loop_end }, 756 757 { "rename-section", required_argument, NULL, option_rename_section_name }, 758 759 { "link-relax", no_argument, NULL, option_link_relax }, 760 { "no-link-relax", no_argument, NULL, option_no_link_relax }, 761 762 { "target-hardware", required_argument, NULL, option_target_hardware }, 763 764 { NULL, no_argument, NULL, 0 } 765 }; 766 767 size_t md_longopts_size = sizeof md_longopts; 768 769 770 int 771 md_parse_option (int c, char *arg) 772 { 773 switch (c) 774 { 775 case option_density: 776 as_warn (_("--density option is ignored")); 777 return 1; 778 case option_no_density: 779 as_warn (_("--no-density option is ignored")); 780 return 1; 781 case option_link_relax: 782 linkrelax = 1; 783 return 1; 784 case option_no_link_relax: 785 linkrelax = 0; 786 return 1; 787 case option_flix: 788 produce_flix = FLIX_ALL; 789 return 1; 790 case option_no_generate_flix: 791 produce_flix = FLIX_NO_GENERATE; 792 return 1; 793 case option_no_flix: 794 produce_flix = FLIX_NONE; 795 return 1; 796 case option_generics: 797 as_warn (_("--generics is deprecated; use --transform instead")); 798 return md_parse_option (option_transform, arg); 799 case option_no_generics: 800 as_warn (_("--no-generics is deprecated; use --no-transform instead")); 801 return md_parse_option (option_no_transform, arg); 802 case option_relax: 803 as_warn (_("--relax is deprecated; use --transform instead")); 804 return md_parse_option (option_transform, arg); 805 case option_no_relax: 806 as_warn (_("--no-relax is deprecated; use --no-transform instead")); 807 return md_parse_option (option_no_transform, arg); 808 case option_longcalls: 809 directive_state[directive_longcalls] = TRUE; 810 return 1; 811 case option_no_longcalls: 812 directive_state[directive_longcalls] = FALSE; 813 return 1; 814 case option_text_section_literals: 815 use_literal_section = FALSE; 816 return 1; 817 case option_no_text_section_literals: 818 use_literal_section = TRUE; 819 return 1; 820 case option_absolute_literals: 821 if (!absolute_literals_supported) 822 { 823 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); 824 return 0; 825 } 826 directive_state[directive_absolute_literals] = TRUE; 827 return 1; 828 case option_no_absolute_literals: 829 directive_state[directive_absolute_literals] = FALSE; 830 return 1; 831 832 case option_workaround_a0_b_retw: 833 workaround_a0_b_retw = TRUE; 834 return 1; 835 case option_no_workaround_a0_b_retw: 836 workaround_a0_b_retw = FALSE; 837 return 1; 838 case option_workaround_b_j_loop_end: 839 workaround_b_j_loop_end = TRUE; 840 return 1; 841 case option_no_workaround_b_j_loop_end: 842 workaround_b_j_loop_end = FALSE; 843 return 1; 844 845 case option_workaround_short_loop: 846 workaround_short_loop = TRUE; 847 return 1; 848 case option_no_workaround_short_loop: 849 workaround_short_loop = FALSE; 850 return 1; 851 852 case option_workaround_all_short_loops: 853 workaround_all_short_loops = TRUE; 854 return 1; 855 case option_no_workaround_all_short_loops: 856 workaround_all_short_loops = FALSE; 857 return 1; 858 859 case option_workaround_close_loop_end: 860 workaround_close_loop_end = TRUE; 861 return 1; 862 case option_no_workaround_close_loop_end: 863 workaround_close_loop_end = FALSE; 864 return 1; 865 866 case option_no_workarounds: 867 workaround_a0_b_retw = FALSE; 868 workaround_b_j_loop_end = FALSE; 869 workaround_short_loop = FALSE; 870 workaround_all_short_loops = FALSE; 871 workaround_close_loop_end = FALSE; 872 return 1; 873 874 case option_align_targets: 875 align_targets = TRUE; 876 return 1; 877 case option_no_align_targets: 878 align_targets = FALSE; 879 return 1; 880 881 case option_warn_unaligned_targets: 882 warn_unaligned_branch_targets = TRUE; 883 return 1; 884 885 case option_rename_section_name: 886 build_section_rename (arg); 887 return 1; 888 889 case 'Q': 890 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 891 should be emitted or not. FIXME: Not implemented. */ 892 return 1; 893 894 case option_prefer_l32r: 895 if (prefer_const16) 896 as_fatal (_("prefer-l32r conflicts with prefer-const16")); 897 prefer_l32r = 1; 898 return 1; 899 900 case option_prefer_const16: 901 if (prefer_l32r) 902 as_fatal (_("prefer-const16 conflicts with prefer-l32r")); 903 prefer_const16 = 1; 904 return 1; 905 906 case option_target_hardware: 907 { 908 int earliest, latest = 0; 909 if (*arg == 0 || *arg == '-') 910 as_fatal (_("invalid target hardware version")); 911 912 earliest = strtol (arg, &arg, 0); 913 914 if (*arg == 0) 915 latest = earliest; 916 else if (*arg == '-') 917 { 918 if (*++arg == 0) 919 as_fatal (_("invalid target hardware version")); 920 latest = strtol (arg, &arg, 0); 921 } 922 if (*arg != 0) 923 as_fatal (_("invalid target hardware version")); 924 925 xtensa_setup_hw_workarounds (earliest, latest); 926 return 1; 927 } 928 929 case option_transform: 930 /* This option has no affect other than to use the defaults, 931 which are already set. */ 932 return 1; 933 934 case option_no_transform: 935 /* This option turns off all transformations of any kind. 936 However, because we want to preserve the state of other 937 directives, we only change its own field. Thus, before 938 you perform any transformation, always check if transform 939 is available. If you use the functions we provide for this 940 purpose, you will be ok. */ 941 directive_state[directive_transform] = FALSE; 942 return 1; 943 944 default: 945 return 0; 946 } 947 } 948 949 950 void 951 md_show_usage (FILE *stream) 952 { 953 fputs ("\n\ 954 Xtensa options:\n\ 955 --[no-]text-section-literals\n\ 956 [Do not] put literals in the text section\n\ 957 --[no-]absolute-literals\n\ 958 [Do not] default to use non-PC-relative literals\n\ 959 --[no-]target-align [Do not] try to align branch targets\n\ 960 --[no-]longcalls [Do not] emit 32-bit call sequences\n\ 961 --[no-]transform [Do not] transform instructions\n\ 962 --flix both allow hand-written and generate flix bundles\n\ 963 --no-generate-flix allow hand-written but do not generate\n\ 964 flix bundles\n\ 965 --no-allow-flix neither allow hand-written nor generate\n\ 966 flix bundles\n\ 967 --rename-section old=new Rename section 'old' to 'new'\n", stream); 968 } 969 970 971 /* Functions related to the list of current label symbols. */ 972 973 static void 974 xtensa_add_insn_label (symbolS *sym) 975 { 976 sym_list *l; 977 978 if (!free_insn_labels) 979 l = (sym_list *) xmalloc (sizeof (sym_list)); 980 else 981 { 982 l = free_insn_labels; 983 free_insn_labels = l->next; 984 } 985 986 l->sym = sym; 987 l->next = insn_labels; 988 insn_labels = l; 989 } 990 991 992 static void 993 xtensa_clear_insn_labels (void) 994 { 995 sym_list **pl; 996 997 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) 998 ; 999 *pl = insn_labels; 1000 insn_labels = NULL; 1001 } 1002 1003 1004 static void 1005 xtensa_move_labels (fragS *new_frag, valueT new_offset) 1006 { 1007 sym_list *lit; 1008 1009 for (lit = insn_labels; lit; lit = lit->next) 1010 { 1011 symbolS *lit_sym = lit->sym; 1012 S_SET_VALUE (lit_sym, new_offset); 1013 symbol_set_frag (lit_sym, new_frag); 1014 } 1015 } 1016 1017 1018 /* Directive data and functions. */ 1019 1020 typedef struct state_stackS_struct 1021 { 1022 directiveE directive; 1023 bfd_boolean negated; 1024 bfd_boolean old_state; 1025 const char *file; 1026 unsigned int line; 1027 const void *datum; 1028 struct state_stackS_struct *prev; 1029 } state_stackS; 1030 1031 state_stackS *directive_state_stack; 1032 1033 const pseudo_typeS md_pseudo_table[] = 1034 { 1035 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ 1036 { "literal_position", xtensa_literal_position, 0 }, 1037 { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ 1038 { "long", xtensa_elf_cons, 4 }, 1039 { "word", xtensa_elf_cons, 4 }, 1040 { "4byte", xtensa_elf_cons, 4 }, 1041 { "short", xtensa_elf_cons, 2 }, 1042 { "2byte", xtensa_elf_cons, 2 }, 1043 { "sleb128", xtensa_leb128, 1}, 1044 { "uleb128", xtensa_leb128, 0}, 1045 { "begin", xtensa_begin_directive, 0 }, 1046 { "end", xtensa_end_directive, 0 }, 1047 { "literal", xtensa_literal_pseudo, 0 }, 1048 { "frequency", xtensa_frequency_pseudo, 0 }, 1049 { NULL, 0, 0 }, 1050 }; 1051 1052 1053 static bfd_boolean 1054 use_transform (void) 1055 { 1056 /* After md_end, you should be checking frag by frag, rather 1057 than state directives. */ 1058 gas_assert (!past_xtensa_end); 1059 return directive_state[directive_transform]; 1060 } 1061 1062 1063 static bfd_boolean 1064 do_align_targets (void) 1065 { 1066 /* Do not use this function after md_end; just look at align_targets 1067 instead. There is no target-align directive, so alignment is either 1068 enabled for all frags or not done at all. */ 1069 gas_assert (!past_xtensa_end); 1070 return align_targets && use_transform (); 1071 } 1072 1073 1074 static void 1075 directive_push (directiveE directive, bfd_boolean negated, const void *datum) 1076 { 1077 char *file; 1078 unsigned int line; 1079 state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); 1080 1081 as_where (&file, &line); 1082 1083 stack->directive = directive; 1084 stack->negated = negated; 1085 stack->old_state = directive_state[directive]; 1086 stack->file = file; 1087 stack->line = line; 1088 stack->datum = datum; 1089 stack->prev = directive_state_stack; 1090 directive_state_stack = stack; 1091 1092 directive_state[directive] = !negated; 1093 } 1094 1095 1096 static void 1097 directive_pop (directiveE *directive, 1098 bfd_boolean *negated, 1099 const char **file, 1100 unsigned int *line, 1101 const void **datum) 1102 { 1103 state_stackS *top = directive_state_stack; 1104 1105 if (!directive_state_stack) 1106 { 1107 as_bad (_("unmatched end directive")); 1108 *directive = directive_none; 1109 return; 1110 } 1111 1112 directive_state[directive_state_stack->directive] = top->old_state; 1113 *directive = top->directive; 1114 *negated = top->negated; 1115 *file = top->file; 1116 *line = top->line; 1117 *datum = top->datum; 1118 directive_state_stack = top->prev; 1119 free (top); 1120 } 1121 1122 1123 static void 1124 directive_balance (void) 1125 { 1126 while (directive_state_stack) 1127 { 1128 directiveE directive; 1129 bfd_boolean negated; 1130 const char *file; 1131 unsigned int line; 1132 const void *datum; 1133 1134 directive_pop (&directive, &negated, &file, &line, &datum); 1135 as_warn_where ((char *) file, line, 1136 _(".begin directive with no matching .end directive")); 1137 } 1138 } 1139 1140 1141 static bfd_boolean 1142 inside_directive (directiveE dir) 1143 { 1144 state_stackS *top = directive_state_stack; 1145 1146 while (top && top->directive != dir) 1147 top = top->prev; 1148 1149 return (top != NULL); 1150 } 1151 1152 1153 static void 1154 get_directive (directiveE *directive, bfd_boolean *negated) 1155 { 1156 int len; 1157 unsigned i; 1158 char *directive_string; 1159 1160 if (strncmp (input_line_pointer, "no-", 3) != 0) 1161 *negated = FALSE; 1162 else 1163 { 1164 *negated = TRUE; 1165 input_line_pointer += 3; 1166 } 1167 1168 len = strspn (input_line_pointer, 1169 "abcdefghijklmnopqrstuvwxyz_-/0123456789."); 1170 1171 /* This code is a hack to make .begin [no-][generics|relax] exactly 1172 equivalent to .begin [no-]transform. We should remove it when 1173 we stop accepting those options. */ 1174 1175 if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) 1176 { 1177 as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); 1178 directive_string = "transform"; 1179 } 1180 else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) 1181 { 1182 as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); 1183 directive_string = "transform"; 1184 } 1185 else 1186 directive_string = input_line_pointer; 1187 1188 for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) 1189 { 1190 if (strncmp (directive_string, directive_info[i].name, len) == 0) 1191 { 1192 input_line_pointer += len; 1193 *directive = (directiveE) i; 1194 if (*negated && !directive_info[i].can_be_negated) 1195 as_bad (_("directive %s cannot be negated"), 1196 directive_info[i].name); 1197 return; 1198 } 1199 } 1200 1201 as_bad (_("unknown directive")); 1202 *directive = (directiveE) XTENSA_UNDEFINED; 1203 } 1204 1205 1206 static void 1207 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) 1208 { 1209 directiveE directive; 1210 bfd_boolean negated; 1211 emit_state *state; 1212 lit_state *ls; 1213 1214 get_directive (&directive, &negated); 1215 if (directive == (directiveE) XTENSA_UNDEFINED) 1216 { 1217 discard_rest_of_line (); 1218 return; 1219 } 1220 1221 if (cur_vinsn.inside_bundle) 1222 as_bad (_("directives are not valid inside bundles")); 1223 1224 switch (directive) 1225 { 1226 case directive_literal: 1227 if (!inside_directive (directive_literal)) 1228 { 1229 /* Previous labels go with whatever follows this directive, not with 1230 the literal, so save them now. */ 1231 saved_insn_labels = insn_labels; 1232 insn_labels = NULL; 1233 } 1234 as_warn (_(".begin literal is deprecated; use .literal instead")); 1235 state = (emit_state *) xmalloc (sizeof (emit_state)); 1236 xtensa_switch_to_literal_fragment (state); 1237 directive_push (directive_literal, negated, state); 1238 break; 1239 1240 case directive_literal_prefix: 1241 /* Have to flush pending output because a movi relaxed to an l32r 1242 might produce a literal. */ 1243 md_flush_pending_output (); 1244 /* Check to see if the current fragment is a literal 1245 fragment. If it is, then this operation is not allowed. */ 1246 if (generating_literals) 1247 { 1248 as_bad (_("cannot set literal_prefix inside literal fragment")); 1249 return; 1250 } 1251 1252 /* Allocate the literal state for this section and push 1253 onto the directive stack. */ 1254 ls = xmalloc (sizeof (lit_state)); 1255 gas_assert (ls); 1256 1257 *ls = default_lit_sections; 1258 directive_push (directive_literal_prefix, negated, ls); 1259 1260 /* Process the new prefix. */ 1261 xtensa_literal_prefix (); 1262 break; 1263 1264 case directive_freeregs: 1265 /* This information is currently unused, but we'll accept the statement 1266 and just discard the rest of the line. This won't check the syntax, 1267 but it will accept every correct freeregs directive. */ 1268 input_line_pointer += strcspn (input_line_pointer, "\n"); 1269 directive_push (directive_freeregs, negated, 0); 1270 break; 1271 1272 case directive_schedule: 1273 md_flush_pending_output (); 1274 frag_var (rs_fill, 0, 0, frag_now->fr_subtype, 1275 frag_now->fr_symbol, frag_now->fr_offset, NULL); 1276 directive_push (directive_schedule, negated, 0); 1277 xtensa_set_frag_assembly_state (frag_now); 1278 break; 1279 1280 case directive_density: 1281 as_warn (_(".begin [no-]density is ignored")); 1282 break; 1283 1284 case directive_absolute_literals: 1285 md_flush_pending_output (); 1286 if (!absolute_literals_supported && !negated) 1287 { 1288 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1289 break; 1290 } 1291 xtensa_set_frag_assembly_state (frag_now); 1292 directive_push (directive, negated, 0); 1293 break; 1294 1295 default: 1296 md_flush_pending_output (); 1297 xtensa_set_frag_assembly_state (frag_now); 1298 directive_push (directive, negated, 0); 1299 break; 1300 } 1301 1302 demand_empty_rest_of_line (); 1303 } 1304 1305 1306 static void 1307 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) 1308 { 1309 directiveE begin_directive, end_directive; 1310 bfd_boolean begin_negated, end_negated; 1311 const char *file; 1312 unsigned int line; 1313 emit_state *state; 1314 emit_state **state_ptr; 1315 lit_state *s; 1316 1317 if (cur_vinsn.inside_bundle) 1318 as_bad (_("directives are not valid inside bundles")); 1319 1320 get_directive (&end_directive, &end_negated); 1321 1322 md_flush_pending_output (); 1323 1324 switch ((int) end_directive) 1325 { 1326 case XTENSA_UNDEFINED: 1327 discard_rest_of_line (); 1328 return; 1329 1330 case (int) directive_density: 1331 as_warn (_(".end [no-]density is ignored")); 1332 demand_empty_rest_of_line (); 1333 break; 1334 1335 case (int) directive_absolute_literals: 1336 if (!absolute_literals_supported && !end_negated) 1337 { 1338 as_warn (_("Xtensa absolute literals option not supported; ignored")); 1339 demand_empty_rest_of_line (); 1340 return; 1341 } 1342 break; 1343 1344 default: 1345 break; 1346 } 1347 1348 state_ptr = &state; /* use state_ptr to avoid type-punning warning */ 1349 directive_pop (&begin_directive, &begin_negated, &file, &line, 1350 (const void **) state_ptr); 1351 1352 if (begin_directive != directive_none) 1353 { 1354 if (begin_directive != end_directive || begin_negated != end_negated) 1355 { 1356 as_bad (_("does not match begin %s%s at %s:%d"), 1357 begin_negated ? "no-" : "", 1358 directive_info[begin_directive].name, file, line); 1359 } 1360 else 1361 { 1362 switch (end_directive) 1363 { 1364 case directive_literal: 1365 frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); 1366 xtensa_restore_emit_state (state); 1367 xtensa_set_frag_assembly_state (frag_now); 1368 free (state); 1369 if (!inside_directive (directive_literal)) 1370 { 1371 /* Restore the list of current labels. */ 1372 xtensa_clear_insn_labels (); 1373 insn_labels = saved_insn_labels; 1374 } 1375 break; 1376 1377 case directive_literal_prefix: 1378 /* Restore the default collection sections from saved state. */ 1379 s = (lit_state *) state; 1380 gas_assert (s); 1381 default_lit_sections = *s; 1382 1383 /* Free the state storage. */ 1384 free (s->lit_prefix); 1385 free (s); 1386 break; 1387 1388 case directive_schedule: 1389 case directive_freeregs: 1390 break; 1391 1392 default: 1393 xtensa_set_frag_assembly_state (frag_now); 1394 break; 1395 } 1396 } 1397 } 1398 1399 demand_empty_rest_of_line (); 1400 } 1401 1402 1403 /* Place an aligned literal fragment at the current location. */ 1404 1405 static void 1406 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) 1407 { 1408 md_flush_pending_output (); 1409 1410 if (inside_directive (directive_literal)) 1411 as_warn (_(".literal_position inside literal directive; ignoring")); 1412 xtensa_mark_literal_pool_location (); 1413 1414 demand_empty_rest_of_line (); 1415 xtensa_clear_insn_labels (); 1416 } 1417 1418 1419 /* Support .literal label, expr, ... */ 1420 1421 static void 1422 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) 1423 { 1424 emit_state state; 1425 char *p, *base_name; 1426 char c; 1427 segT dest_seg; 1428 1429 if (inside_directive (directive_literal)) 1430 { 1431 as_bad (_(".literal not allowed inside .begin literal region")); 1432 ignore_rest_of_line (); 1433 return; 1434 } 1435 1436 md_flush_pending_output (); 1437 1438 /* Previous labels go with whatever follows this directive, not with 1439 the literal, so save them now. */ 1440 saved_insn_labels = insn_labels; 1441 insn_labels = NULL; 1442 1443 /* If we are using text-section literals, then this is the right value... */ 1444 dest_seg = now_seg; 1445 1446 base_name = input_line_pointer; 1447 1448 xtensa_switch_to_literal_fragment (&state); 1449 1450 /* ...but if we aren't using text-section-literals, then we 1451 need to put them in the section we just switched to. */ 1452 if (use_literal_section || directive_state[directive_absolute_literals]) 1453 dest_seg = now_seg; 1454 1455 /* FIXME, despite the previous comments, dest_seg is unused... */ 1456 (void) dest_seg; 1457 1458 /* All literals are aligned to four-byte boundaries. */ 1459 frag_align (2, 0, 0); 1460 record_alignment (now_seg, 2); 1461 1462 c = get_symbol_end (); 1463 /* Just after name is now '\0'. */ 1464 p = input_line_pointer; 1465 *p = c; 1466 SKIP_WHITESPACE (); 1467 1468 if (*input_line_pointer != ',' && *input_line_pointer != ':') 1469 { 1470 as_bad (_("expected comma or colon after symbol name; " 1471 "rest of line ignored")); 1472 ignore_rest_of_line (); 1473 xtensa_restore_emit_state (&state); 1474 return; 1475 } 1476 *p = 0; 1477 1478 colon (base_name); 1479 1480 *p = c; 1481 input_line_pointer++; /* skip ',' or ':' */ 1482 1483 xtensa_elf_cons (4); 1484 1485 xtensa_restore_emit_state (&state); 1486 1487 /* Restore the list of current labels. */ 1488 xtensa_clear_insn_labels (); 1489 insn_labels = saved_insn_labels; 1490 } 1491 1492 1493 static void 1494 xtensa_literal_prefix (void) 1495 { 1496 char *name; 1497 int len; 1498 1499 /* Parse the new prefix from the input_line_pointer. */ 1500 SKIP_WHITESPACE (); 1501 len = strspn (input_line_pointer, 1502 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 1503 "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); 1504 1505 /* Get a null-terminated copy of the name. */ 1506 name = xmalloc (len + 1); 1507 gas_assert (name); 1508 strncpy (name, input_line_pointer, len); 1509 name[len] = 0; 1510 1511 /* Skip the name in the input line. */ 1512 input_line_pointer += len; 1513 1514 default_lit_sections.lit_prefix = name; 1515 1516 /* Clear cached literal sections, since the prefix has changed. */ 1517 default_lit_sections.lit_seg = NULL; 1518 default_lit_sections.lit4_seg = NULL; 1519 } 1520 1521 1522 /* Support ".frequency branch_target_frequency fall_through_frequency". */ 1523 1524 static void 1525 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) 1526 { 1527 float fall_through_f, target_f; 1528 1529 fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); 1530 if (fall_through_f < 0) 1531 { 1532 as_bad (_("fall through frequency must be greater than 0")); 1533 ignore_rest_of_line (); 1534 return; 1535 } 1536 1537 target_f = (float) strtod (input_line_pointer, &input_line_pointer); 1538 if (target_f < 0) 1539 { 1540 as_bad (_("branch target frequency must be greater than 0")); 1541 ignore_rest_of_line (); 1542 return; 1543 } 1544 1545 set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); 1546 1547 demand_empty_rest_of_line (); 1548 } 1549 1550 1551 /* Like normal .long/.short/.word, except support @plt, etc. 1552 Clobbers input_line_pointer, checks end-of-line. */ 1553 1554 static void 1555 xtensa_elf_cons (int nbytes) 1556 { 1557 expressionS exp; 1558 bfd_reloc_code_real_type reloc; 1559 1560 md_flush_pending_output (); 1561 1562 if (cur_vinsn.inside_bundle) 1563 as_bad (_("directives are not valid inside bundles")); 1564 1565 if (is_it_end_of_statement ()) 1566 { 1567 demand_empty_rest_of_line (); 1568 return; 1569 } 1570 1571 do 1572 { 1573 expression (&exp); 1574 if (exp.X_op == O_symbol 1575 && *input_line_pointer == '@' 1576 && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) 1577 != BFD_RELOC_NONE)) 1578 { 1579 reloc_howto_type *reloc_howto = 1580 bfd_reloc_type_lookup (stdoutput, reloc); 1581 1582 if (reloc == BFD_RELOC_UNUSED || !reloc_howto) 1583 as_bad (_("unsupported relocation")); 1584 else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP 1585 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 1586 || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 1587 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) 1588 as_bad (_("opcode-specific %s relocation used outside " 1589 "an instruction"), reloc_howto->name); 1590 else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) 1591 as_bad (_("%s relocations do not fit in %d bytes"), 1592 reloc_howto->name, nbytes); 1593 else if (reloc == BFD_RELOC_XTENSA_TLS_FUNC 1594 || reloc == BFD_RELOC_XTENSA_TLS_ARG 1595 || reloc == BFD_RELOC_XTENSA_TLS_CALL) 1596 as_bad (_("invalid use of %s relocation"), reloc_howto->name); 1597 else 1598 { 1599 char *p = frag_more ((int) nbytes); 1600 xtensa_set_frag_assembly_state (frag_now); 1601 fix_new_exp (frag_now, p - frag_now->fr_literal, 1602 nbytes, &exp, reloc_howto->pc_relative, reloc); 1603 } 1604 } 1605 else 1606 { 1607 xtensa_set_frag_assembly_state (frag_now); 1608 emit_expr (&exp, (unsigned int) nbytes); 1609 } 1610 } 1611 while (*input_line_pointer++ == ','); 1612 1613 input_line_pointer--; /* Put terminator back into stream. */ 1614 demand_empty_rest_of_line (); 1615 } 1616 1617 static bfd_boolean is_leb128_expr; 1618 1619 static void 1620 xtensa_leb128 (int sign) 1621 { 1622 is_leb128_expr = TRUE; 1623 s_leb128 (sign); 1624 is_leb128_expr = FALSE; 1625 } 1626 1627 1628 /* Parsing and Idiom Translation. */ 1629 1630 /* Parse @plt, etc. and return the desired relocation. */ 1631 static bfd_reloc_code_real_type 1632 xtensa_elf_suffix (char **str_p, expressionS *exp_p) 1633 { 1634 char ident[20]; 1635 char *str = *str_p; 1636 char *str2; 1637 int ch; 1638 int len; 1639 struct suffix_reloc_map *ptr; 1640 1641 if (*str++ != '@') 1642 return BFD_RELOC_NONE; 1643 1644 for (ch = *str, str2 = ident; 1645 (str2 < ident + sizeof (ident) - 1 1646 && (ISALNUM (ch) || ch == '@')); 1647 ch = *++str) 1648 { 1649 *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); 1650 } 1651 1652 *str2 = '\0'; 1653 len = str2 - ident; 1654 1655 ch = ident[0]; 1656 for (ptr = &suffix_relocs[0]; ptr->length > 0; ptr++) 1657 if (ch == ptr->suffix[0] 1658 && len == ptr->length 1659 && memcmp (ident, ptr->suffix, ptr->length) == 0) 1660 { 1661 /* Now check for "identifier@suffix+constant". */ 1662 if (*str == '-' || *str == '+') 1663 { 1664 char *orig_line = input_line_pointer; 1665 expressionS new_exp; 1666 1667 input_line_pointer = str; 1668 expression (&new_exp); 1669 if (new_exp.X_op == O_constant) 1670 { 1671 exp_p->X_add_number += new_exp.X_add_number; 1672 str = input_line_pointer; 1673 } 1674 1675 if (&input_line_pointer != str_p) 1676 input_line_pointer = orig_line; 1677 } 1678 1679 *str_p = str; 1680 return ptr->reloc; 1681 } 1682 1683 return BFD_RELOC_UNUSED; 1684 } 1685 1686 1687 /* Find the matching operator type. */ 1688 static unsigned char 1689 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc) 1690 { 1691 struct suffix_reloc_map *sfx; 1692 unsigned char operator = (unsigned char) -1; 1693 1694 for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) 1695 { 1696 if (sfx->reloc == reloc) 1697 { 1698 operator = sfx->operator; 1699 break; 1700 } 1701 } 1702 gas_assert (operator != (unsigned char) -1); 1703 return operator; 1704 } 1705 1706 1707 /* Find the matching reloc type. */ 1708 static bfd_reloc_code_real_type 1709 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal) 1710 { 1711 struct suffix_reloc_map *sfx; 1712 bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; 1713 1714 for (sfx = &suffix_relocs[0]; sfx->suffix; sfx++) 1715 { 1716 if (sfx->operator == operator) 1717 { 1718 reloc = sfx->reloc; 1719 break; 1720 } 1721 } 1722 1723 if (is_literal) 1724 { 1725 if (reloc == BFD_RELOC_XTENSA_TLS_FUNC) 1726 return BFD_RELOC_XTENSA_TLSDESC_FN; 1727 else if (reloc == BFD_RELOC_XTENSA_TLS_ARG) 1728 return BFD_RELOC_XTENSA_TLSDESC_ARG; 1729 } 1730 1731 if (reloc == BFD_RELOC_UNUSED) 1732 return BFD_RELOC_32; 1733 1734 return reloc; 1735 } 1736 1737 1738 static const char * 1739 expression_end (const char *name) 1740 { 1741 while (1) 1742 { 1743 switch (*name) 1744 { 1745 case '}': 1746 case ';': 1747 case '\0': 1748 case ',': 1749 case ':': 1750 return name; 1751 case ' ': 1752 case '\t': 1753 ++name; 1754 continue; 1755 default: 1756 return 0; 1757 } 1758 } 1759 } 1760 1761 1762 #define ERROR_REG_NUM ((unsigned) -1) 1763 1764 static unsigned 1765 tc_get_register (const char *prefix) 1766 { 1767 unsigned reg; 1768 const char *next_expr; 1769 const char *old_line_pointer; 1770 1771 SKIP_WHITESPACE (); 1772 old_line_pointer = input_line_pointer; 1773 1774 if (*input_line_pointer == '$') 1775 ++input_line_pointer; 1776 1777 /* Accept "sp" as a synonym for "a1". */ 1778 if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' 1779 && expression_end (input_line_pointer + 2)) 1780 { 1781 input_line_pointer += 2; 1782 return 1; /* AR[1] */ 1783 } 1784 1785 while (*input_line_pointer++ == *prefix++) 1786 ; 1787 --input_line_pointer; 1788 --prefix; 1789 1790 if (*prefix) 1791 { 1792 as_bad (_("bad register name: %s"), old_line_pointer); 1793 return ERROR_REG_NUM; 1794 } 1795 1796 if (!ISDIGIT ((unsigned char) *input_line_pointer)) 1797 { 1798 as_bad (_("bad register number: %s"), input_line_pointer); 1799 return ERROR_REG_NUM; 1800 } 1801 1802 reg = 0; 1803 1804 while (ISDIGIT ((int) *input_line_pointer)) 1805 reg = reg * 10 + *input_line_pointer++ - '0'; 1806 1807 if (!(next_expr = expression_end (input_line_pointer))) 1808 { 1809 as_bad (_("bad register name: %s"), old_line_pointer); 1810 return ERROR_REG_NUM; 1811 } 1812 1813 input_line_pointer = (char *) next_expr; 1814 1815 return reg; 1816 } 1817 1818 1819 static void 1820 expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) 1821 { 1822 xtensa_isa isa = xtensa_default_isa; 1823 1824 /* Check if this is an immediate operand. */ 1825 if (xtensa_operand_is_register (isa, opc, opnd) == 0) 1826 { 1827 bfd_reloc_code_real_type reloc; 1828 segT t = expression (tok); 1829 1830 if (t == absolute_section 1831 && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) 1832 { 1833 gas_assert (tok->X_op == O_constant); 1834 tok->X_op = O_symbol; 1835 tok->X_add_symbol = &abs_symbol; 1836 } 1837 1838 if ((tok->X_op == O_constant || tok->X_op == O_symbol) 1839 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) 1840 != BFD_RELOC_NONE)) 1841 { 1842 switch (reloc) 1843 { 1844 case BFD_RELOC_LO16: 1845 if (tok->X_op == O_constant) 1846 { 1847 tok->X_add_number &= 0xffff; 1848 return; 1849 } 1850 break; 1851 case BFD_RELOC_HI16: 1852 if (tok->X_op == O_constant) 1853 { 1854 tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; 1855 return; 1856 } 1857 break; 1858 case BFD_RELOC_UNUSED: 1859 as_bad (_("unsupported relocation")); 1860 return; 1861 case BFD_RELOC_32_PCREL: 1862 as_bad (_("pcrel relocation not allowed in an instruction")); 1863 return; 1864 default: 1865 break; 1866 } 1867 tok->X_op = map_suffix_reloc_to_operator (reloc); 1868 } 1869 } 1870 else 1871 { 1872 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); 1873 unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); 1874 1875 if (reg != ERROR_REG_NUM) /* Already errored */ 1876 { 1877 uint32 buf = reg; 1878 if (xtensa_operand_encode (isa, opc, opnd, &buf)) 1879 as_bad (_("register number out of range")); 1880 } 1881 1882 tok->X_op = O_register; 1883 tok->X_add_symbol = 0; 1884 tok->X_add_number = reg; 1885 } 1886 } 1887 1888 1889 /* Split up the arguments for an opcode or pseudo-op. */ 1890 1891 static int 1892 tokenize_arguments (char **args, char *str) 1893 { 1894 char *old_input_line_pointer; 1895 bfd_boolean saw_comma = FALSE; 1896 bfd_boolean saw_arg = FALSE; 1897 bfd_boolean saw_colon = FALSE; 1898 int num_args = 0; 1899 char *arg_end, *arg; 1900 int arg_len; 1901 1902 /* Save and restore input_line_pointer around this function. */ 1903 old_input_line_pointer = input_line_pointer; 1904 input_line_pointer = str; 1905 1906 while (*input_line_pointer) 1907 { 1908 SKIP_WHITESPACE (); 1909 switch (*input_line_pointer) 1910 { 1911 case '\0': 1912 case '}': 1913 goto fini; 1914 1915 case ':': 1916 input_line_pointer++; 1917 if (saw_comma || saw_colon || !saw_arg) 1918 goto err; 1919 saw_colon = TRUE; 1920 break; 1921 1922 case ',': 1923 input_line_pointer++; 1924 if (saw_comma || saw_colon || !saw_arg) 1925 goto err; 1926 saw_comma = TRUE; 1927 break; 1928 1929 default: 1930 if (!saw_comma && !saw_colon && saw_arg) 1931 goto err; 1932 1933 arg_end = input_line_pointer + 1; 1934 while (!expression_end (arg_end)) 1935 arg_end += 1; 1936 1937 arg_len = arg_end - input_line_pointer; 1938 arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); 1939 args[num_args] = arg; 1940 1941 if (saw_colon) 1942 *arg++ = ':'; 1943 strncpy (arg, input_line_pointer, arg_len); 1944 arg[arg_len] = '\0'; 1945 1946 input_line_pointer = arg_end; 1947 num_args += 1; 1948 saw_comma = FALSE; 1949 saw_colon = FALSE; 1950 saw_arg = TRUE; 1951 break; 1952 } 1953 } 1954 1955 fini: 1956 if (saw_comma || saw_colon) 1957 goto err; 1958 input_line_pointer = old_input_line_pointer; 1959 return num_args; 1960 1961 err: 1962 if (saw_comma) 1963 as_bad (_("extra comma")); 1964 else if (saw_colon) 1965 as_bad (_("extra colon")); 1966 else if (!saw_arg) 1967 as_bad (_("missing argument")); 1968 else 1969 as_bad (_("missing comma or colon")); 1970 input_line_pointer = old_input_line_pointer; 1971 return -1; 1972 } 1973 1974 1975 /* Parse the arguments to an opcode. Return TRUE on error. */ 1976 1977 static bfd_boolean 1978 parse_arguments (TInsn *insn, int num_args, char **arg_strings) 1979 { 1980 expressionS *tok, *last_tok; 1981 xtensa_opcode opcode = insn->opcode; 1982 bfd_boolean had_error = TRUE; 1983 xtensa_isa isa = xtensa_default_isa; 1984 int n, num_regs = 0; 1985 int opcode_operand_count; 1986 int opnd_cnt, last_opnd_cnt; 1987 unsigned int next_reg = 0; 1988 char *old_input_line_pointer; 1989 1990 if (insn->insn_type == ITYPE_LITERAL) 1991 opcode_operand_count = 1; 1992 else 1993 opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); 1994 1995 tok = insn->tok; 1996 memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); 1997 1998 /* Save and restore input_line_pointer around this function. */ 1999 old_input_line_pointer = input_line_pointer; 2000 2001 last_tok = 0; 2002 last_opnd_cnt = -1; 2003 opnd_cnt = 0; 2004 2005 /* Skip invisible operands. */ 2006 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) 2007 { 2008 opnd_cnt += 1; 2009 tok++; 2010 } 2011 2012 for (n = 0; n < num_args; n++) 2013 { 2014 input_line_pointer = arg_strings[n]; 2015 if (*input_line_pointer == ':') 2016 { 2017 xtensa_regfile opnd_rf; 2018 input_line_pointer++; 2019 if (num_regs == 0) 2020 goto err; 2021 gas_assert (opnd_cnt > 0); 2022 num_regs--; 2023 opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); 2024 if (next_reg 2025 != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) 2026 as_warn (_("incorrect register number, ignoring")); 2027 next_reg++; 2028 } 2029 else 2030 { 2031 if (opnd_cnt >= opcode_operand_count) 2032 { 2033 as_warn (_("too many arguments")); 2034 goto err; 2035 } 2036 gas_assert (opnd_cnt < MAX_INSN_ARGS); 2037 2038 expression_maybe_register (opcode, opnd_cnt, tok); 2039 next_reg = tok->X_add_number + 1; 2040 2041 if (tok->X_op == O_illegal || tok->X_op == O_absent) 2042 goto err; 2043 if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) 2044 { 2045 num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; 2046 /* minus 1 because we are seeing one right now */ 2047 } 2048 else 2049 num_regs = 0; 2050 2051 last_tok = tok; 2052 last_opnd_cnt = opnd_cnt; 2053 demand_empty_rest_of_line (); 2054 2055 do 2056 { 2057 opnd_cnt += 1; 2058 tok++; 2059 } 2060 while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); 2061 } 2062 } 2063 2064 if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) 2065 goto err; 2066 2067 insn->ntok = tok - insn->tok; 2068 had_error = FALSE; 2069 2070 err: 2071 input_line_pointer = old_input_line_pointer; 2072 return had_error; 2073 } 2074 2075 2076 static int 2077 get_invisible_operands (TInsn *insn) 2078 { 2079 xtensa_isa isa = xtensa_default_isa; 2080 static xtensa_insnbuf slotbuf = NULL; 2081 xtensa_format fmt; 2082 xtensa_opcode opc = insn->opcode; 2083 int slot, opnd, fmt_found; 2084 unsigned val; 2085 2086 if (!slotbuf) 2087 slotbuf = xtensa_insnbuf_alloc (isa); 2088 2089 /* Find format/slot where this can be encoded. */ 2090 fmt_found = 0; 2091 slot = 0; 2092 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 2093 { 2094 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 2095 { 2096 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) 2097 { 2098 fmt_found = 1; 2099 break; 2100 } 2101 } 2102 if (fmt_found) break; 2103 } 2104 2105 if (!fmt_found) 2106 { 2107 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); 2108 return -1; 2109 } 2110 2111 /* First encode all the visible operands 2112 (to deal with shared field operands). */ 2113 for (opnd = 0; opnd < insn->ntok; opnd++) 2114 { 2115 if (xtensa_operand_is_visible (isa, opc, opnd) == 1 2116 && (insn->tok[opnd].X_op == O_register 2117 || insn->tok[opnd].X_op == O_constant)) 2118 { 2119 val = insn->tok[opnd].X_add_number; 2120 xtensa_operand_encode (isa, opc, opnd, &val); 2121 xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); 2122 } 2123 } 2124 2125 /* Then pull out the values for the invisible ones. */ 2126 for (opnd = 0; opnd < insn->ntok; opnd++) 2127 { 2128 if (xtensa_operand_is_visible (isa, opc, opnd) == 0) 2129 { 2130 xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); 2131 xtensa_operand_decode (isa, opc, opnd, &val); 2132 insn->tok[opnd].X_add_number = val; 2133 if (xtensa_operand_is_register (isa, opc, opnd) == 1) 2134 insn->tok[opnd].X_op = O_register; 2135 else 2136 insn->tok[opnd].X_op = O_constant; 2137 } 2138 } 2139 2140 return 0; 2141 } 2142 2143 2144 static void 2145 xg_reverse_shift_count (char **cnt_argp) 2146 { 2147 char *cnt_arg, *new_arg; 2148 cnt_arg = *cnt_argp; 2149 2150 /* replace the argument with "31-(argument)" */ 2151 new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); 2152 sprintf (new_arg, "31-(%s)", cnt_arg); 2153 2154 free (cnt_arg); 2155 *cnt_argp = new_arg; 2156 } 2157 2158 2159 /* If "arg" is a constant expression, return non-zero with the value 2160 in *valp. */ 2161 2162 static int 2163 xg_arg_is_constant (char *arg, offsetT *valp) 2164 { 2165 expressionS exp; 2166 char *save_ptr = input_line_pointer; 2167 2168 input_line_pointer = arg; 2169 expression (&exp); 2170 input_line_pointer = save_ptr; 2171 2172 if (exp.X_op == O_constant) 2173 { 2174 *valp = exp.X_add_number; 2175 return 1; 2176 } 2177 2178 return 0; 2179 } 2180 2181 2182 static void 2183 xg_replace_opname (char **popname, char *newop) 2184 { 2185 free (*popname); 2186 *popname = (char *) xmalloc (strlen (newop) + 1); 2187 strcpy (*popname, newop); 2188 } 2189 2190 2191 static int 2192 xg_check_num_args (int *pnum_args, 2193 int expected_num, 2194 char *opname, 2195 char **arg_strings) 2196 { 2197 int num_args = *pnum_args; 2198 2199 if (num_args < expected_num) 2200 { 2201 as_bad (_("not enough operands (%d) for '%s'; expected %d"), 2202 num_args, opname, expected_num); 2203 return -1; 2204 } 2205 2206 if (num_args > expected_num) 2207 { 2208 as_warn (_("too many operands (%d) for '%s'; expected %d"), 2209 num_args, opname, expected_num); 2210 while (num_args-- > expected_num) 2211 { 2212 free (arg_strings[num_args]); 2213 arg_strings[num_args] = 0; 2214 } 2215 *pnum_args = expected_num; 2216 return -1; 2217 } 2218 2219 return 0; 2220 } 2221 2222 2223 /* If the register is not specified as part of the opcode, 2224 then get it from the operand and move it to the opcode. */ 2225 2226 static int 2227 xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) 2228 { 2229 xtensa_isa isa = xtensa_default_isa; 2230 xtensa_sysreg sr; 2231 char *opname, *new_opname; 2232 const char *sr_name; 2233 int is_user, is_write; 2234 2235 opname = *popname; 2236 if (*opname == '_') 2237 opname += 1; 2238 is_user = (opname[1] == 'u'); 2239 is_write = (opname[0] == 'w'); 2240 2241 /* Opname == [rw]ur or [rwx]sr... */ 2242 2243 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2244 return -1; 2245 2246 /* Check if the argument is a symbolic register name. */ 2247 sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); 2248 /* Handle WSR to "INTSET" as a special case. */ 2249 if (sr == XTENSA_UNDEFINED && is_write && !is_user 2250 && !strcasecmp (arg_strings[1], "intset")) 2251 sr = xtensa_sysreg_lookup_name (isa, "interrupt"); 2252 if (sr == XTENSA_UNDEFINED 2253 || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) 2254 { 2255 /* Maybe it's a register number.... */ 2256 offsetT val; 2257 if (!xg_arg_is_constant (arg_strings[1], &val)) 2258 { 2259 as_bad (_("invalid register '%s' for '%s' instruction"), 2260 arg_strings[1], opname); 2261 return -1; 2262 } 2263 sr = xtensa_sysreg_lookup (isa, val, is_user); 2264 if (sr == XTENSA_UNDEFINED) 2265 { 2266 as_bad (_("invalid register number (%ld) for '%s' instruction"), 2267 (long) val, opname); 2268 return -1; 2269 } 2270 } 2271 2272 /* Remove the last argument, which is now part of the opcode. */ 2273 free (arg_strings[1]); 2274 arg_strings[1] = 0; 2275 *pnum_args = 1; 2276 2277 /* Translate the opcode. */ 2278 sr_name = xtensa_sysreg_name (isa, sr); 2279 /* Another special case for "WSR.INTSET".... */ 2280 if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) 2281 sr_name = "intset"; 2282 new_opname = (char *) xmalloc (strlen (sr_name) + 6); 2283 sprintf (new_opname, "%s.%s", *popname, sr_name); 2284 free (*popname); 2285 *popname = new_opname; 2286 2287 return 0; 2288 } 2289 2290 2291 static int 2292 xtensa_translate_old_userreg_ops (char **popname) 2293 { 2294 xtensa_isa isa = xtensa_default_isa; 2295 xtensa_sysreg sr; 2296 char *opname, *new_opname; 2297 const char *sr_name; 2298 bfd_boolean has_underbar = FALSE; 2299 2300 opname = *popname; 2301 if (opname[0] == '_') 2302 { 2303 has_underbar = TRUE; 2304 opname += 1; 2305 } 2306 2307 sr = xtensa_sysreg_lookup_name (isa, opname + 1); 2308 if (sr != XTENSA_UNDEFINED) 2309 { 2310 /* The new default name ("nnn") is different from the old default 2311 name ("URnnn"). The old default is handled below, and we don't 2312 want to recognize [RW]nnn, so do nothing if the name is the (new) 2313 default. */ 2314 static char namebuf[10]; 2315 sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); 2316 if (strcmp (namebuf, opname + 1) == 0) 2317 return 0; 2318 } 2319 else 2320 { 2321 offsetT val; 2322 char *end; 2323 2324 /* Only continue if the reg name is "URnnn". */ 2325 if (opname[1] != 'u' || opname[2] != 'r') 2326 return 0; 2327 val = strtoul (opname + 3, &end, 10); 2328 if (*end != '\0') 2329 return 0; 2330 2331 sr = xtensa_sysreg_lookup (isa, val, 1); 2332 if (sr == XTENSA_UNDEFINED) 2333 { 2334 as_bad (_("invalid register number (%ld) for '%s'"), 2335 (long) val, opname); 2336 return -1; 2337 } 2338 } 2339 2340 /* Translate the opcode. */ 2341 sr_name = xtensa_sysreg_name (isa, sr); 2342 new_opname = (char *) xmalloc (strlen (sr_name) + 6); 2343 sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), 2344 opname[0], sr_name); 2345 free (*popname); 2346 *popname = new_opname; 2347 2348 return 0; 2349 } 2350 2351 2352 static int 2353 xtensa_translate_zero_immed (char *old_op, 2354 char *new_op, 2355 char **popname, 2356 int *pnum_args, 2357 char **arg_strings) 2358 { 2359 char *opname; 2360 offsetT val; 2361 2362 opname = *popname; 2363 gas_assert (opname[0] != '_'); 2364 2365 if (strcmp (opname, old_op) != 0) 2366 return 0; 2367 2368 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2369 return -1; 2370 if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) 2371 { 2372 xg_replace_opname (popname, new_op); 2373 free (arg_strings[1]); 2374 arg_strings[1] = arg_strings[2]; 2375 arg_strings[2] = 0; 2376 *pnum_args = 2; 2377 } 2378 2379 return 0; 2380 } 2381 2382 2383 /* If the instruction is an idiom (i.e., a built-in macro), translate it. 2384 Returns non-zero if an error was found. */ 2385 2386 static int 2387 xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) 2388 { 2389 char *opname = *popname; 2390 bfd_boolean has_underbar = FALSE; 2391 2392 if (*opname == '_') 2393 { 2394 has_underbar = TRUE; 2395 opname += 1; 2396 } 2397 2398 if (strcmp (opname, "mov") == 0) 2399 { 2400 if (use_transform () && !has_underbar && density_supported) 2401 xg_replace_opname (popname, "mov.n"); 2402 else 2403 { 2404 if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) 2405 return -1; 2406 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2407 arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); 2408 strcpy (arg_strings[2], arg_strings[1]); 2409 *pnum_args = 3; 2410 } 2411 return 0; 2412 } 2413 2414 if (strcmp (opname, "bbsi.l") == 0) 2415 { 2416 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2417 return -1; 2418 xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); 2419 if (target_big_endian) 2420 xg_reverse_shift_count (&arg_strings[1]); 2421 return 0; 2422 } 2423 2424 if (strcmp (opname, "bbci.l") == 0) 2425 { 2426 if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) 2427 return -1; 2428 xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); 2429 if (target_big_endian) 2430 xg_reverse_shift_count (&arg_strings[1]); 2431 return 0; 2432 } 2433 2434 /* Don't do anything special with NOPs inside FLIX instructions. They 2435 are handled elsewhere. Real NOP instructions are always available 2436 in configurations with FLIX, so this should never be an issue but 2437 check for it anyway. */ 2438 if (!cur_vinsn.inside_bundle && xtensa_nop_opcode == XTENSA_UNDEFINED 2439 && strcmp (opname, "nop") == 0) 2440 { 2441 if (use_transform () && !has_underbar && density_supported) 2442 xg_replace_opname (popname, "nop.n"); 2443 else 2444 { 2445 if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) 2446 return -1; 2447 xg_replace_opname (popname, (has_underbar ? "_or" : "or")); 2448 arg_strings[0] = (char *) xmalloc (3); 2449 arg_strings[1] = (char *) xmalloc (3); 2450 arg_strings[2] = (char *) xmalloc (3); 2451 strcpy (arg_strings[0], "a1"); 2452 strcpy (arg_strings[1], "a1"); 2453 strcpy (arg_strings[2], "a1"); 2454 *pnum_args = 3; 2455 } 2456 return 0; 2457 } 2458 2459 /* Recognize [RW]UR and [RWX]SR. */ 2460 if ((((opname[0] == 'r' || opname[0] == 'w') 2461 && (opname[1] == 'u' || opname[1] == 's')) 2462 || (opname[0] == 'x' && opname[1] == 's')) 2463 && opname[2] == 'r' 2464 && opname[3] == '\0') 2465 return xg_translate_sysreg_op (popname, pnum_args, arg_strings); 2466 2467 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and 2468 [RW]<name> if <name> is the non-default name of a user register. */ 2469 if ((opname[0] == 'r' || opname[0] == 'w') 2470 && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) 2471 return xtensa_translate_old_userreg_ops (popname); 2472 2473 /* Relax branches that don't allow comparisons against an immediate value 2474 of zero to the corresponding branches with implicit zero immediates. */ 2475 if (!has_underbar && use_transform ()) 2476 { 2477 if (xtensa_translate_zero_immed ("bnei", "bnez", popname, 2478 pnum_args, arg_strings)) 2479 return -1; 2480 2481 if (xtensa_translate_zero_immed ("beqi", "beqz", popname, 2482 pnum_args, arg_strings)) 2483 return -1; 2484 2485 if (xtensa_translate_zero_immed ("bgei", "bgez", popname, 2486 pnum_args, arg_strings)) 2487 return -1; 2488 2489 if (xtensa_translate_zero_immed ("blti", "bltz", popname, 2490 pnum_args, arg_strings)) 2491 return -1; 2492 } 2493 2494 return 0; 2495 } 2496 2497 2498 /* Functions for dealing with the Xtensa ISA. */ 2499 2500 /* Currently the assembler only allows us to use a single target per 2501 fragment. Because of this, only one operand for a given 2502 instruction may be symbolic. If there is a PC-relative operand, 2503 the last one is chosen. Otherwise, the result is the number of the 2504 last immediate operand, and if there are none of those, we fail and 2505 return -1. */ 2506 2507 static int 2508 get_relaxable_immed (xtensa_opcode opcode) 2509 { 2510 int last_immed = -1; 2511 int noperands, opi; 2512 2513 if (opcode == XTENSA_UNDEFINED) 2514 return -1; 2515 2516 noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); 2517 for (opi = noperands - 1; opi >= 0; opi--) 2518 { 2519 if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) 2520 continue; 2521 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) 2522 return opi; 2523 if (last_immed == -1 2524 && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) 2525 last_immed = opi; 2526 } 2527 return last_immed; 2528 } 2529 2530 2531 static xtensa_opcode 2532 get_opcode_from_buf (const char *buf, int slot) 2533 { 2534 static xtensa_insnbuf insnbuf = NULL; 2535 static xtensa_insnbuf slotbuf = NULL; 2536 xtensa_isa isa = xtensa_default_isa; 2537 xtensa_format fmt; 2538 2539 if (!insnbuf) 2540 { 2541 insnbuf = xtensa_insnbuf_alloc (isa); 2542 slotbuf = xtensa_insnbuf_alloc (isa); 2543 } 2544 2545 xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); 2546 fmt = xtensa_format_decode (isa, insnbuf); 2547 if (fmt == XTENSA_UNDEFINED) 2548 return XTENSA_UNDEFINED; 2549 2550 if (slot >= xtensa_format_num_slots (isa, fmt)) 2551 return XTENSA_UNDEFINED; 2552 2553 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 2554 return xtensa_opcode_decode (isa, fmt, slot, slotbuf); 2555 } 2556 2557 2558 #ifdef TENSILICA_DEBUG 2559 2560 /* For debugging, print out the mapping of opcode numbers to opcodes. */ 2561 2562 static void 2563 xtensa_print_insn_table (void) 2564 { 2565 int num_opcodes, num_operands; 2566 xtensa_opcode opcode; 2567 xtensa_isa isa = xtensa_default_isa; 2568 2569 num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); 2570 for (opcode = 0; opcode < num_opcodes; opcode++) 2571 { 2572 int opn; 2573 fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); 2574 num_operands = xtensa_opcode_num_operands (isa, opcode); 2575 for (opn = 0; opn < num_operands; opn++) 2576 { 2577 if (xtensa_operand_is_visible (isa, opcode, opn) == 0) 2578 continue; 2579 if (xtensa_operand_is_register (isa, opcode, opn) == 1) 2580 { 2581 xtensa_regfile opnd_rf = 2582 xtensa_operand_regfile (isa, opcode, opn); 2583 fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); 2584 } 2585 else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) 2586 fputs ("[lLr] ", stderr); 2587 else 2588 fputs ("i ", stderr); 2589 } 2590 fprintf (stderr, "\n"); 2591 } 2592 } 2593 2594 2595 static void 2596 print_vliw_insn (xtensa_insnbuf vbuf) 2597 { 2598 xtensa_isa isa = xtensa_default_isa; 2599 xtensa_format f = xtensa_format_decode (isa, vbuf); 2600 xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); 2601 int op; 2602 2603 fprintf (stderr, "format = %d\n", f); 2604 2605 for (op = 0; op < xtensa_format_num_slots (isa, f); op++) 2606 { 2607 xtensa_opcode opcode; 2608 const char *opname; 2609 int operands; 2610 2611 xtensa_format_get_slot (isa, f, op, vbuf, sbuf); 2612 opcode = xtensa_opcode_decode (isa, f, op, sbuf); 2613 opname = xtensa_opcode_name (isa, opcode); 2614 2615 fprintf (stderr, "op in slot %i is %s;\n", op, opname); 2616 fprintf (stderr, " operands = "); 2617 for (operands = 0; 2618 operands < xtensa_opcode_num_operands (isa, opcode); 2619 operands++) 2620 { 2621 unsigned int val; 2622 if (xtensa_operand_is_visible (isa, opcode, operands) == 0) 2623 continue; 2624 xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); 2625 xtensa_operand_decode (isa, opcode, operands, &val); 2626 fprintf (stderr, "%d ", val); 2627 } 2628 fprintf (stderr, "\n"); 2629 } 2630 xtensa_insnbuf_free (isa, sbuf); 2631 } 2632 2633 #endif /* TENSILICA_DEBUG */ 2634 2635 2636 static bfd_boolean 2637 is_direct_call_opcode (xtensa_opcode opcode) 2638 { 2639 xtensa_isa isa = xtensa_default_isa; 2640 int n, num_operands; 2641 2642 if (xtensa_opcode_is_call (isa, opcode) != 1) 2643 return FALSE; 2644 2645 num_operands = xtensa_opcode_num_operands (isa, opcode); 2646 for (n = 0; n < num_operands; n++) 2647 { 2648 if (xtensa_operand_is_register (isa, opcode, n) == 0 2649 && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) 2650 return TRUE; 2651 } 2652 return FALSE; 2653 } 2654 2655 2656 /* Convert from BFD relocation type code to slot and operand number. 2657 Returns non-zero on failure. */ 2658 2659 static int 2660 decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) 2661 { 2662 if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP 2663 && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) 2664 { 2665 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; 2666 *is_alt = FALSE; 2667 } 2668 else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT 2669 && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) 2670 { 2671 *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; 2672 *is_alt = TRUE; 2673 } 2674 else 2675 return -1; 2676 2677 return 0; 2678 } 2679 2680 2681 /* Convert from slot number to BFD relocation type code for the 2682 standard PC-relative relocations. Return BFD_RELOC_NONE on 2683 failure. */ 2684 2685 static bfd_reloc_code_real_type 2686 encode_reloc (int slot) 2687 { 2688 if (slot < 0 || slot > 14) 2689 return BFD_RELOC_NONE; 2690 2691 return BFD_RELOC_XTENSA_SLOT0_OP + slot; 2692 } 2693 2694 2695 /* Convert from slot numbers to BFD relocation type code for the 2696 "alternate" relocations. Return BFD_RELOC_NONE on failure. */ 2697 2698 static bfd_reloc_code_real_type 2699 encode_alt_reloc (int slot) 2700 { 2701 if (slot < 0 || slot > 14) 2702 return BFD_RELOC_NONE; 2703 2704 return BFD_RELOC_XTENSA_SLOT0_ALT + slot; 2705 } 2706 2707 2708 static void 2709 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, 2710 xtensa_format fmt, 2711 int slot, 2712 xtensa_opcode opcode, 2713 int operand, 2714 uint32 value, 2715 const char *file, 2716 unsigned int line) 2717 { 2718 uint32 valbuf = value; 2719 2720 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 2721 { 2722 if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) 2723 == 1) 2724 as_bad_where ((char *) file, line, 2725 _("operand %d of '%s' has out of range value '%u'"), 2726 operand + 1, 2727 xtensa_opcode_name (xtensa_default_isa, opcode), 2728 value); 2729 else 2730 as_bad_where ((char *) file, line, 2731 _("operand %d of '%s' has invalid value '%u'"), 2732 operand + 1, 2733 xtensa_opcode_name (xtensa_default_isa, opcode), 2734 value); 2735 return; 2736 } 2737 2738 xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, 2739 slotbuf, valbuf); 2740 } 2741 2742 2743 static uint32 2744 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, 2745 xtensa_format fmt, 2746 int slot, 2747 xtensa_opcode opcode, 2748 int opnum) 2749 { 2750 uint32 val = 0; 2751 (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, 2752 fmt, slot, slotbuf, &val); 2753 (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); 2754 return val; 2755 } 2756 2757 2758 /* Checks for rules from xtensa-relax tables. */ 2759 2760 /* The routine xg_instruction_matches_option_term must return TRUE 2761 when a given option term is true. The meaning of all of the option 2762 terms is given interpretation by this function. */ 2763 2764 static bfd_boolean 2765 xg_instruction_matches_option_term (TInsn *insn, const ReqOrOption *option) 2766 { 2767 if (strcmp (option->option_name, "realnop") == 0 2768 || strncmp (option->option_name, "IsaUse", 6) == 0) 2769 { 2770 /* These conditions were evaluated statically when building the 2771 relaxation table. There's no need to reevaluate them now. */ 2772 return TRUE; 2773 } 2774 else if (strcmp (option->option_name, "FREEREG") == 0) 2775 return insn->extra_arg.X_op == O_register; 2776 else 2777 { 2778 as_fatal (_("internal error: unknown option name '%s'"), 2779 option->option_name); 2780 } 2781 } 2782 2783 2784 static bfd_boolean 2785 xg_instruction_matches_or_options (TInsn *insn, 2786 const ReqOrOptionList *or_option) 2787 { 2788 const ReqOrOption *option; 2789 /* Must match each of the AND terms. */ 2790 for (option = or_option; option != NULL; option = option->next) 2791 { 2792 if (xg_instruction_matches_option_term (insn, option)) 2793 return TRUE; 2794 } 2795 return FALSE; 2796 } 2797 2798 2799 static bfd_boolean 2800 xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) 2801 { 2802 const ReqOption *req_options; 2803 /* Must match each of the AND terms. */ 2804 for (req_options = options; 2805 req_options != NULL; 2806 req_options = req_options->next) 2807 { 2808 /* Must match one of the OR clauses. */ 2809 if (!xg_instruction_matches_or_options (insn, 2810 req_options->or_option_terms)) 2811 return FALSE; 2812 } 2813 return TRUE; 2814 } 2815 2816 2817 /* Return the transition rule that matches or NULL if none matches. */ 2818 2819 static bfd_boolean 2820 xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) 2821 { 2822 PreconditionList *condition_l; 2823 2824 if (rule->opcode != insn->opcode) 2825 return FALSE; 2826 2827 for (condition_l = rule->conditions; 2828 condition_l != NULL; 2829 condition_l = condition_l->next) 2830 { 2831 expressionS *exp1; 2832 expressionS *exp2; 2833 Precondition *cond = condition_l->precond; 2834 2835 switch (cond->typ) 2836 { 2837 case OP_CONSTANT: 2838 /* The expression must be the constant. */ 2839 gas_assert (cond->op_num < insn->ntok); 2840 exp1 = &insn->tok[cond->op_num]; 2841 if (expr_is_const (exp1)) 2842 { 2843 switch (cond->cmp) 2844 { 2845 case OP_EQUAL: 2846 if (get_expr_const (exp1) != cond->op_data) 2847 return FALSE; 2848 break; 2849 case OP_NOTEQUAL: 2850 if (get_expr_const (exp1) == cond->op_data) 2851 return FALSE; 2852 break; 2853 default: 2854 return FALSE; 2855 } 2856 } 2857 else if (expr_is_register (exp1)) 2858 { 2859 switch (cond->cmp) 2860 { 2861 case OP_EQUAL: 2862 if (get_expr_register (exp1) != cond->op_data) 2863 return FALSE; 2864 break; 2865 case OP_NOTEQUAL: 2866 if (get_expr_register (exp1) == cond->op_data) 2867 return FALSE; 2868 break; 2869 default: 2870 return FALSE; 2871 } 2872 } 2873 else 2874 return FALSE; 2875 break; 2876 2877 case OP_OPERAND: 2878 gas_assert (cond->op_num < insn->ntok); 2879 gas_assert (cond->op_data < insn->ntok); 2880 exp1 = &insn->tok[cond->op_num]; 2881 exp2 = &insn->tok[cond->op_data]; 2882 2883 switch (cond->cmp) 2884 { 2885 case OP_EQUAL: 2886 if (!expr_is_equal (exp1, exp2)) 2887 return FALSE; 2888 break; 2889 case OP_NOTEQUAL: 2890 if (expr_is_equal (exp1, exp2)) 2891 return FALSE; 2892 break; 2893 } 2894 break; 2895 2896 case OP_LITERAL: 2897 case OP_LABEL: 2898 default: 2899 return FALSE; 2900 } 2901 } 2902 if (!xg_instruction_matches_options (insn, rule->options)) 2903 return FALSE; 2904 2905 return TRUE; 2906 } 2907 2908 2909 static int 2910 transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) 2911 { 2912 bfd_boolean a_greater = FALSE; 2913 bfd_boolean b_greater = FALSE; 2914 2915 ReqOptionList *l_a = a->options; 2916 ReqOptionList *l_b = b->options; 2917 2918 /* We only care if they both are the same except for 2919 a const16 vs. an l32r. */ 2920 2921 while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) 2922 { 2923 ReqOrOptionList *l_or_a = l_a->or_option_terms; 2924 ReqOrOptionList *l_or_b = l_b->or_option_terms; 2925 while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) 2926 { 2927 if (l_or_a->is_true != l_or_b->is_true) 2928 return 0; 2929 if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) 2930 { 2931 /* This is the case we care about. */ 2932 if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 2933 && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) 2934 { 2935 if (prefer_const16) 2936 a_greater = TRUE; 2937 else 2938 b_greater = TRUE; 2939 } 2940 else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 2941 && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) 2942 { 2943 if (prefer_const16) 2944 b_greater = TRUE; 2945 else 2946 a_greater = TRUE; 2947 } 2948 else 2949 return 0; 2950 } 2951 l_or_a = l_or_a->next; 2952 l_or_b = l_or_b->next; 2953 } 2954 if (l_or_a || l_or_b) 2955 return 0; 2956 2957 l_a = l_a->next; 2958 l_b = l_b->next; 2959 } 2960 if (l_a || l_b) 2961 return 0; 2962 2963 /* Incomparable if the substitution was used differently in two cases. */ 2964 if (a_greater && b_greater) 2965 return 0; 2966 2967 if (b_greater) 2968 return 1; 2969 if (a_greater) 2970 return -1; 2971 2972 return 0; 2973 } 2974 2975 2976 static TransitionRule * 2977 xg_instruction_match (TInsn *insn) 2978 { 2979 TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); 2980 TransitionList *l; 2981 gas_assert (insn->opcode < table->num_opcodes); 2982 2983 /* Walk through all of the possible transitions. */ 2984 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 2985 { 2986 TransitionRule *rule = l->rule; 2987 if (xg_instruction_matches_rule (insn, rule)) 2988 return rule; 2989 } 2990 return NULL; 2991 } 2992 2993 2994 /* Various Other Internal Functions. */ 2995 2996 static bfd_boolean 2997 is_unique_insn_expansion (TransitionRule *r) 2998 { 2999 if (!r->to_instr || r->to_instr->next != NULL) 3000 return FALSE; 3001 if (r->to_instr->typ != INSTR_INSTR) 3002 return FALSE; 3003 return TRUE; 3004 } 3005 3006 3007 /* Check if there is exactly one relaxation for INSN that converts it to 3008 another instruction of equal or larger size. If so, and if TARG is 3009 non-null, go ahead and generate the relaxed instruction into TARG. If 3010 NARROW_ONLY is true, then only consider relaxations that widen a narrow 3011 instruction, i.e., ignore relaxations that convert to an instruction of 3012 equal size. In some contexts where this function is used, only 3013 a single widening is allowed and the NARROW_ONLY argument is used to 3014 exclude cases like ADDI being "widened" to an ADDMI, which may 3015 later be relaxed to an ADDMI/ADDI pair. */ 3016 3017 bfd_boolean 3018 xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) 3019 { 3020 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3021 TransitionList *l; 3022 TransitionRule *match = 0; 3023 3024 gas_assert (insn->insn_type == ITYPE_INSN); 3025 gas_assert (insn->opcode < table->num_opcodes); 3026 3027 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3028 { 3029 TransitionRule *rule = l->rule; 3030 3031 if (xg_instruction_matches_rule (insn, rule) 3032 && is_unique_insn_expansion (rule) 3033 && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) 3034 <= xg_get_single_size (rule->to_instr->opcode))) 3035 { 3036 if (match) 3037 return FALSE; 3038 match = rule; 3039 } 3040 } 3041 if (!match) 3042 return FALSE; 3043 3044 if (targ) 3045 xg_build_to_insn (targ, insn, match->to_instr); 3046 return TRUE; 3047 } 3048 3049 3050 /* Return the maximum number of bytes this opcode can expand to. */ 3051 3052 static int 3053 xg_get_max_insn_widen_size (xtensa_opcode opcode) 3054 { 3055 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3056 TransitionList *l; 3057 int max_size = xg_get_single_size (opcode); 3058 3059 gas_assert (opcode < table->num_opcodes); 3060 3061 for (l = table->table[opcode]; l != NULL; l = l->next) 3062 { 3063 TransitionRule *rule = l->rule; 3064 BuildInstr *build_list; 3065 int this_size = 0; 3066 3067 if (!rule) 3068 continue; 3069 build_list = rule->to_instr; 3070 if (is_unique_insn_expansion (rule)) 3071 { 3072 gas_assert (build_list->typ == INSTR_INSTR); 3073 this_size = xg_get_max_insn_widen_size (build_list->opcode); 3074 } 3075 else 3076 for (; build_list != NULL; build_list = build_list->next) 3077 { 3078 switch (build_list->typ) 3079 { 3080 case INSTR_INSTR: 3081 this_size += xg_get_single_size (build_list->opcode); 3082 break; 3083 case INSTR_LITERAL_DEF: 3084 case INSTR_LABEL_DEF: 3085 default: 3086 break; 3087 } 3088 } 3089 if (this_size > max_size) 3090 max_size = this_size; 3091 } 3092 return max_size; 3093 } 3094 3095 3096 /* Return the maximum number of literal bytes this opcode can generate. */ 3097 3098 static int 3099 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) 3100 { 3101 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3102 TransitionList *l; 3103 int max_size = 0; 3104 3105 gas_assert (opcode < table->num_opcodes); 3106 3107 for (l = table->table[opcode]; l != NULL; l = l->next) 3108 { 3109 TransitionRule *rule = l->rule; 3110 BuildInstr *build_list; 3111 int this_size = 0; 3112 3113 if (!rule) 3114 continue; 3115 build_list = rule->to_instr; 3116 if (is_unique_insn_expansion (rule)) 3117 { 3118 gas_assert (build_list->typ == INSTR_INSTR); 3119 this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); 3120 } 3121 else 3122 for (; build_list != NULL; build_list = build_list->next) 3123 { 3124 switch (build_list->typ) 3125 { 3126 case INSTR_LITERAL_DEF: 3127 /* Hard-coded 4-byte literal. */ 3128 this_size += 4; 3129 break; 3130 case INSTR_INSTR: 3131 case INSTR_LABEL_DEF: 3132 default: 3133 break; 3134 } 3135 } 3136 if (this_size > max_size) 3137 max_size = this_size; 3138 } 3139 return max_size; 3140 } 3141 3142 3143 static bfd_boolean 3144 xg_is_relaxable_insn (TInsn *insn, int lateral_steps) 3145 { 3146 int steps_taken = 0; 3147 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3148 TransitionList *l; 3149 3150 gas_assert (insn->insn_type == ITYPE_INSN); 3151 gas_assert (insn->opcode < table->num_opcodes); 3152 3153 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3154 { 3155 TransitionRule *rule = l->rule; 3156 3157 if (xg_instruction_matches_rule (insn, rule)) 3158 { 3159 if (steps_taken == lateral_steps) 3160 return TRUE; 3161 steps_taken++; 3162 } 3163 } 3164 return FALSE; 3165 } 3166 3167 3168 static symbolS * 3169 get_special_literal_symbol (void) 3170 { 3171 static symbolS *sym = NULL; 3172 3173 if (sym == NULL) 3174 sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); 3175 return sym; 3176 } 3177 3178 3179 static symbolS * 3180 get_special_label_symbol (void) 3181 { 3182 static symbolS *sym = NULL; 3183 3184 if (sym == NULL) 3185 sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); 3186 return sym; 3187 } 3188 3189 3190 static bfd_boolean 3191 xg_valid_literal_expression (const expressionS *exp) 3192 { 3193 switch (exp->X_op) 3194 { 3195 case O_constant: 3196 case O_symbol: 3197 case O_big: 3198 case O_uminus: 3199 case O_subtract: 3200 case O_pltrel: 3201 case O_pcrel: 3202 case O_tlsfunc: 3203 case O_tlsarg: 3204 case O_tpoff: 3205 case O_dtpoff: 3206 return TRUE; 3207 default: 3208 return FALSE; 3209 } 3210 } 3211 3212 3213 /* This will check to see if the value can be converted into the 3214 operand type. It will return TRUE if it does not fit. */ 3215 3216 static bfd_boolean 3217 xg_check_operand (int32 value, xtensa_opcode opcode, int operand) 3218 { 3219 uint32 valbuf = value; 3220 if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) 3221 return TRUE; 3222 return FALSE; 3223 } 3224 3225 3226 /* Assumes: All immeds are constants. Check that all constants fit 3227 into their immeds; return FALSE if not. */ 3228 3229 static bfd_boolean 3230 xg_immeds_fit (const TInsn *insn) 3231 { 3232 xtensa_isa isa = xtensa_default_isa; 3233 int i; 3234 3235 int n = insn->ntok; 3236 gas_assert (insn->insn_type == ITYPE_INSN); 3237 for (i = 0; i < n; ++i) 3238 { 3239 const expressionS *exp = &insn->tok[i]; 3240 3241 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3242 continue; 3243 3244 switch (exp->X_op) 3245 { 3246 case O_register: 3247 case O_constant: 3248 if (xg_check_operand (exp->X_add_number, insn->opcode, i)) 3249 return FALSE; 3250 break; 3251 3252 default: 3253 /* The symbol should have a fixup associated with it. */ 3254 gas_assert (FALSE); 3255 break; 3256 } 3257 } 3258 return TRUE; 3259 } 3260 3261 3262 /* This should only be called after we have an initial 3263 estimate of the addresses. */ 3264 3265 static bfd_boolean 3266 xg_symbolic_immeds_fit (const TInsn *insn, 3267 segT pc_seg, 3268 fragS *pc_frag, 3269 offsetT pc_offset, 3270 long stretch) 3271 { 3272 xtensa_isa isa = xtensa_default_isa; 3273 symbolS *symbolP; 3274 fragS *sym_frag; 3275 offsetT target, pc; 3276 uint32 new_offset; 3277 int i; 3278 int n = insn->ntok; 3279 3280 gas_assert (insn->insn_type == ITYPE_INSN); 3281 3282 for (i = 0; i < n; ++i) 3283 { 3284 const expressionS *exp = &insn->tok[i]; 3285 3286 if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) 3287 continue; 3288 3289 switch (exp->X_op) 3290 { 3291 case O_register: 3292 case O_constant: 3293 if (xg_check_operand (exp->X_add_number, insn->opcode, i)) 3294 return FALSE; 3295 break; 3296 3297 case O_lo16: 3298 case O_hi16: 3299 /* Check for the worst case. */ 3300 if (xg_check_operand (0xffff, insn->opcode, i)) 3301 return FALSE; 3302 break; 3303 3304 case O_symbol: 3305 /* We only allow symbols for PC-relative references. 3306 If pc_frag == 0, then we don't have frag locations yet. */ 3307 if (pc_frag == 0 3308 || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) 3309 return FALSE; 3310 3311 /* If it is a weak symbol or a symbol in a different section, 3312 it cannot be known to fit at assembly time. */ 3313 if (S_IS_WEAK (exp->X_add_symbol) 3314 || S_GET_SEGMENT (exp->X_add_symbol) != pc_seg) 3315 { 3316 /* For a direct call with --no-longcalls, be optimistic and 3317 assume it will be in range. If the symbol is weak and 3318 undefined, it may remain undefined at link-time, in which 3319 case it will have a zero value and almost certainly be out 3320 of range for a direct call; thus, relax for undefined weak 3321 symbols even if longcalls is not enabled. */ 3322 if (is_direct_call_opcode (insn->opcode) 3323 && ! pc_frag->tc_frag_data.use_longcalls 3324 && (! S_IS_WEAK (exp->X_add_symbol) 3325 || S_IS_DEFINED (exp->X_add_symbol))) 3326 return TRUE; 3327 3328 return FALSE; 3329 } 3330 3331 symbolP = exp->X_add_symbol; 3332 sym_frag = symbol_get_frag (symbolP); 3333 target = S_GET_VALUE (symbolP) + exp->X_add_number; 3334 pc = pc_frag->fr_address + pc_offset; 3335 3336 /* If frag has yet to be reached on this pass, assume it 3337 will move by STRETCH just as we did. If this is not so, 3338 it will be because some frag between grows, and that will 3339 force another pass. Beware zero-length frags. There 3340 should be a faster way to do this. */ 3341 3342 if (stretch != 0 3343 && sym_frag->relax_marker != pc_frag->relax_marker 3344 && S_GET_SEGMENT (symbolP) == pc_seg) 3345 { 3346 target += stretch; 3347 } 3348 3349 new_offset = target; 3350 xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); 3351 if (xg_check_operand (new_offset, insn->opcode, i)) 3352 return FALSE; 3353 break; 3354 3355 default: 3356 /* The symbol should have a fixup associated with it. */ 3357 return FALSE; 3358 } 3359 } 3360 3361 return TRUE; 3362 } 3363 3364 3365 /* Return TRUE on success. */ 3366 3367 static bfd_boolean 3368 xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) 3369 { 3370 BuildOp *op; 3371 symbolS *sym; 3372 3373 tinsn_init (targ); 3374 targ->debug_line = insn->debug_line; 3375 targ->loc_directive_seen = insn->loc_directive_seen; 3376 switch (bi->typ) 3377 { 3378 case INSTR_INSTR: 3379 op = bi->ops; 3380 targ->opcode = bi->opcode; 3381 targ->insn_type = ITYPE_INSN; 3382 targ->is_specific_opcode = FALSE; 3383 3384 for (; op != NULL; op = op->next) 3385 { 3386 int op_num = op->op_num; 3387 int op_data = op->op_data; 3388 3389 gas_assert (op->op_num < MAX_INSN_ARGS); 3390 3391 if (targ->ntok <= op_num) 3392 targ->ntok = op_num + 1; 3393 3394 switch (op->typ) 3395 { 3396 case OP_CONSTANT: 3397 set_expr_const (&targ->tok[op_num], op_data); 3398 break; 3399 case OP_OPERAND: 3400 gas_assert (op_data < insn->ntok); 3401 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3402 break; 3403 case OP_FREEREG: 3404 if (insn->extra_arg.X_op != O_register) 3405 return FALSE; 3406 copy_expr (&targ->tok[op_num], &insn->extra_arg); 3407 break; 3408 case OP_LITERAL: 3409 sym = get_special_literal_symbol (); 3410 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3411 if (insn->tok[op_data].X_op == O_tlsfunc 3412 || insn->tok[op_data].X_op == O_tlsarg) 3413 copy_expr (&targ->extra_arg, &insn->tok[op_data]); 3414 break; 3415 case OP_LABEL: 3416 sym = get_special_label_symbol (); 3417 set_expr_symbol_offset (&targ->tok[op_num], sym, 0); 3418 break; 3419 case OP_OPERAND_HI16U: 3420 case OP_OPERAND_LOW16U: 3421 gas_assert (op_data < insn->ntok); 3422 if (expr_is_const (&insn->tok[op_data])) 3423 { 3424 long val; 3425 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3426 val = xg_apply_userdef_op_fn (op->typ, 3427 targ->tok[op_num]. 3428 X_add_number); 3429 targ->tok[op_num].X_add_number = val; 3430 } 3431 else 3432 { 3433 /* For const16 we can create relocations for these. */ 3434 if (targ->opcode == XTENSA_UNDEFINED 3435 || (targ->opcode != xtensa_const16_opcode)) 3436 return FALSE; 3437 gas_assert (op_data < insn->ntok); 3438 /* Need to build a O_lo16 or O_hi16. */ 3439 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3440 if (targ->tok[op_num].X_op == O_symbol) 3441 { 3442 if (op->typ == OP_OPERAND_HI16U) 3443 targ->tok[op_num].X_op = O_hi16; 3444 else if (op->typ == OP_OPERAND_LOW16U) 3445 targ->tok[op_num].X_op = O_lo16; 3446 else 3447 return FALSE; 3448 } 3449 } 3450 break; 3451 default: 3452 /* currently handles: 3453 OP_OPERAND_LOW8 3454 OP_OPERAND_HI24S 3455 OP_OPERAND_F32MINUS */ 3456 if (xg_has_userdef_op_fn (op->typ)) 3457 { 3458 gas_assert (op_data < insn->ntok); 3459 if (expr_is_const (&insn->tok[op_data])) 3460 { 3461 long val; 3462 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3463 val = xg_apply_userdef_op_fn (op->typ, 3464 targ->tok[op_num]. 3465 X_add_number); 3466 targ->tok[op_num].X_add_number = val; 3467 } 3468 else 3469 return FALSE; /* We cannot use a relocation for this. */ 3470 break; 3471 } 3472 gas_assert (0); 3473 break; 3474 } 3475 } 3476 break; 3477 3478 case INSTR_LITERAL_DEF: 3479 op = bi->ops; 3480 targ->opcode = XTENSA_UNDEFINED; 3481 targ->insn_type = ITYPE_LITERAL; 3482 targ->is_specific_opcode = FALSE; 3483 for (; op != NULL; op = op->next) 3484 { 3485 int op_num = op->op_num; 3486 int op_data = op->op_data; 3487 gas_assert (op->op_num < MAX_INSN_ARGS); 3488 3489 if (targ->ntok <= op_num) 3490 targ->ntok = op_num + 1; 3491 3492 switch (op->typ) 3493 { 3494 case OP_OPERAND: 3495 gas_assert (op_data < insn->ntok); 3496 /* We can only pass resolvable literals through. */ 3497 if (!xg_valid_literal_expression (&insn->tok[op_data])) 3498 return FALSE; 3499 copy_expr (&targ->tok[op_num], &insn->tok[op_data]); 3500 break; 3501 case OP_LITERAL: 3502 case OP_CONSTANT: 3503 case OP_LABEL: 3504 default: 3505 gas_assert (0); 3506 break; 3507 } 3508 } 3509 break; 3510 3511 case INSTR_LABEL_DEF: 3512 op = bi->ops; 3513 targ->opcode = XTENSA_UNDEFINED; 3514 targ->insn_type = ITYPE_LABEL; 3515 targ->is_specific_opcode = FALSE; 3516 /* Literal with no ops is a label? */ 3517 gas_assert (op == NULL); 3518 break; 3519 3520 default: 3521 gas_assert (0); 3522 } 3523 3524 return TRUE; 3525 } 3526 3527 3528 /* Return TRUE on success. */ 3529 3530 static bfd_boolean 3531 xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) 3532 { 3533 for (; bi != NULL; bi = bi->next) 3534 { 3535 TInsn *next_insn = istack_push_space (istack); 3536 3537 if (!xg_build_to_insn (next_insn, insn, bi)) 3538 return FALSE; 3539 } 3540 return TRUE; 3541 } 3542 3543 3544 /* Return TRUE on valid expansion. */ 3545 3546 static bfd_boolean 3547 xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) 3548 { 3549 int stack_size = istack->ninsn; 3550 int steps_taken = 0; 3551 TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); 3552 TransitionList *l; 3553 3554 gas_assert (insn->insn_type == ITYPE_INSN); 3555 gas_assert (insn->opcode < table->num_opcodes); 3556 3557 for (l = table->table[insn->opcode]; l != NULL; l = l->next) 3558 { 3559 TransitionRule *rule = l->rule; 3560 3561 if (xg_instruction_matches_rule (insn, rule)) 3562 { 3563 if (lateral_steps == steps_taken) 3564 { 3565 int i; 3566 3567 /* This is it. Expand the rule to the stack. */ 3568 if (!xg_build_to_stack (istack, insn, rule->to_instr)) 3569 return FALSE; 3570 3571 /* Check to see if it fits. */ 3572 for (i = stack_size; i < istack->ninsn; i++) 3573 { 3574 TInsn *tinsn = &istack->insn[i]; 3575 3576 if (tinsn->insn_type == ITYPE_INSN 3577 && !tinsn_has_symbolic_operands (tinsn) 3578 && !xg_immeds_fit (tinsn)) 3579 { 3580 istack->ninsn = stack_size; 3581 return FALSE; 3582 } 3583 } 3584 return TRUE; 3585 } 3586 steps_taken++; 3587 } 3588 } 3589 return FALSE; 3590 } 3591 3592 3593 /* Relax the assembly instruction at least "min_steps". 3594 Return the number of steps taken. 3595 3596 For relaxation to correctly terminate, every relaxation chain must 3597 terminate in one of two ways: 3598 3599 1. If the chain from one instruction to the next consists entirely of 3600 single instructions, then the chain *must* handle all possible 3601 immediates without failing. It must not ever fail because an 3602 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation 3603 chain is one example. L32R loads 32 bits, and there cannot be an 3604 immediate larger than 32 bits, so it satisfies this condition. 3605 Single instruction relaxation chains are as defined by 3606 xg_is_single_relaxable_instruction. 3607 3608 2. Otherwise, the chain must end in a multi-instruction expansion: e.g., 3609 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J 3610 3611 Strictly speaking, in most cases you can violate condition 1 and be OK 3612 -- in particular when the last two instructions have the same single 3613 size. But nevertheless, you should guarantee the above two conditions. 3614 3615 We could fix this so that single-instruction expansions correctly 3616 terminate when they can't handle the range, but the error messages are 3617 worse, and it actually turns out that in every case but one (18-bit wide 3618 branches), you need a multi-instruction expansion to get the full range 3619 anyway. And because 18-bit branches are handled identically to 15-bit 3620 branches, there isn't any point in changing it. */ 3621 3622 static int 3623 xg_assembly_relax (IStack *istack, 3624 TInsn *insn, 3625 segT pc_seg, 3626 fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ 3627 offsetT pc_offset, /* offset in fragment */ 3628 int min_steps, /* minimum conversion steps */ 3629 long stretch) /* number of bytes stretched so far */ 3630 { 3631 int steps_taken = 0; 3632 3633 /* Some of its immeds don't fit. Try to build a relaxed version. 3634 This may go through a couple of stages of single instruction 3635 transformations before we get there. */ 3636 3637 TInsn single_target; 3638 TInsn current_insn; 3639 int lateral_steps = 0; 3640 int istack_size = istack->ninsn; 3641 3642 if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) 3643 && steps_taken >= min_steps) 3644 { 3645 istack_push (istack, insn); 3646 return steps_taken; 3647 } 3648 current_insn = *insn; 3649 3650 /* Walk through all of the single instruction expansions. */ 3651 while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) 3652 { 3653 steps_taken++; 3654 if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, 3655 stretch)) 3656 { 3657 if (steps_taken >= min_steps) 3658 { 3659 istack_push (istack, &single_target); 3660 return steps_taken; 3661 } 3662 } 3663 current_insn = single_target; 3664 } 3665 3666 /* Now check for a multi-instruction expansion. */ 3667 while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) 3668 { 3669 if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, 3670 stretch)) 3671 { 3672 if (steps_taken >= min_steps) 3673 { 3674 istack_push (istack, ¤t_insn); 3675 return steps_taken; 3676 } 3677 } 3678 steps_taken++; 3679 if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) 3680 { 3681 if (steps_taken >= min_steps) 3682 return steps_taken; 3683 } 3684 lateral_steps++; 3685 istack->ninsn = istack_size; 3686 } 3687 3688 /* It's not going to work -- use the original. */ 3689 istack_push (istack, insn); 3690 return steps_taken; 3691 } 3692 3693 3694 static void 3695 xg_finish_frag (char *last_insn, 3696 enum xtensa_relax_statesE frag_state, 3697 enum xtensa_relax_statesE slot0_state, 3698 int max_growth, 3699 bfd_boolean is_insn) 3700 { 3701 /* Finish off this fragment so that it has at LEAST the desired 3702 max_growth. If it doesn't fit in this fragment, close this one 3703 and start a new one. In either case, return a pointer to the 3704 beginning of the growth area. */ 3705 3706 fragS *old_frag; 3707 3708 frag_grow (max_growth); 3709 old_frag = frag_now; 3710 3711 frag_now->fr_opcode = last_insn; 3712 if (is_insn) 3713 frag_now->tc_frag_data.is_insn = TRUE; 3714 3715 frag_var (rs_machine_dependent, max_growth, max_growth, 3716 frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); 3717 3718 old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; 3719 xtensa_set_frag_assembly_state (frag_now); 3720 3721 /* Just to make sure that we did not split it up. */ 3722 gas_assert (old_frag->fr_next == frag_now); 3723 } 3724 3725 3726 /* Return TRUE if the target frag is one of the next non-empty frags. */ 3727 3728 static bfd_boolean 3729 is_next_frag_target (const fragS *fragP, const fragS *target) 3730 { 3731 if (fragP == NULL) 3732 return FALSE; 3733 3734 for (; fragP; fragP = fragP->fr_next) 3735 { 3736 if (fragP == target) 3737 return TRUE; 3738 if (fragP->fr_fix != 0) 3739 return FALSE; 3740 if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) 3741 return FALSE; 3742 if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) 3743 && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) 3744 return FALSE; 3745 if (fragP->fr_type == rs_space) 3746 return FALSE; 3747 } 3748 return FALSE; 3749 } 3750 3751 3752 static bfd_boolean 3753 is_branch_jmp_to_next (TInsn *insn, fragS *fragP) 3754 { 3755 xtensa_isa isa = xtensa_default_isa; 3756 int i; 3757 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3758 int target_op = -1; 3759 symbolS *sym; 3760 fragS *target_frag; 3761 3762 if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 3763 && xtensa_opcode_is_jump (isa, insn->opcode) != 1) 3764 return FALSE; 3765 3766 for (i = 0; i < num_ops; i++) 3767 { 3768 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) 3769 { 3770 target_op = i; 3771 break; 3772 } 3773 } 3774 if (target_op == -1) 3775 return FALSE; 3776 3777 if (insn->ntok <= target_op) 3778 return FALSE; 3779 3780 if (insn->tok[target_op].X_op != O_symbol) 3781 return FALSE; 3782 3783 sym = insn->tok[target_op].X_add_symbol; 3784 if (sym == NULL) 3785 return FALSE; 3786 3787 if (insn->tok[target_op].X_add_number != 0) 3788 return FALSE; 3789 3790 target_frag = symbol_get_frag (sym); 3791 if (target_frag == NULL) 3792 return FALSE; 3793 3794 if (is_next_frag_target (fragP->fr_next, target_frag) 3795 && S_GET_VALUE (sym) == target_frag->fr_address) 3796 return TRUE; 3797 3798 return FALSE; 3799 } 3800 3801 3802 static void 3803 xg_add_branch_and_loop_targets (TInsn *insn) 3804 { 3805 xtensa_isa isa = xtensa_default_isa; 3806 int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 3807 3808 if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3809 { 3810 int i = 1; 3811 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3812 && insn->tok[i].X_op == O_symbol) 3813 symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; 3814 return; 3815 } 3816 3817 if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 3818 || xtensa_opcode_is_loop (isa, insn->opcode) == 1) 3819 { 3820 int i; 3821 3822 for (i = 0; i < insn->ntok && i < num_ops; i++) 3823 { 3824 if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 3825 && insn->tok[i].X_op == O_symbol) 3826 { 3827 symbolS *sym = insn->tok[i].X_add_symbol; 3828 symbol_get_tc (sym)->is_branch_target = TRUE; 3829 if (S_IS_DEFINED (sym)) 3830 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; 3831 } 3832 } 3833 } 3834 } 3835 3836 3837 /* Return FALSE if no error. */ 3838 3839 static bfd_boolean 3840 xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) 3841 { 3842 int num_ops = 0; 3843 BuildOp *b_op; 3844 3845 switch (instr_spec->typ) 3846 { 3847 case INSTR_INSTR: 3848 new_insn->insn_type = ITYPE_INSN; 3849 new_insn->opcode = instr_spec->opcode; 3850 break; 3851 case INSTR_LITERAL_DEF: 3852 new_insn->insn_type = ITYPE_LITERAL; 3853 new_insn->opcode = XTENSA_UNDEFINED; 3854 break; 3855 case INSTR_LABEL_DEF: 3856 abort (); 3857 } 3858 new_insn->is_specific_opcode = FALSE; 3859 new_insn->debug_line = old_insn->debug_line; 3860 new_insn->loc_directive_seen = old_insn->loc_directive_seen; 3861 3862 for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) 3863 { 3864 expressionS *exp; 3865 const expressionS *src_exp; 3866 3867 num_ops++; 3868 switch (b_op->typ) 3869 { 3870 case OP_CONSTANT: 3871 /* The expression must be the constant. */ 3872 gas_assert (b_op->op_num < MAX_INSN_ARGS); 3873 exp = &new_insn->tok[b_op->op_num]; 3874 set_expr_const (exp, b_op->op_data); 3875 break; 3876 3877 case OP_OPERAND: 3878 gas_assert (b_op->op_num < MAX_INSN_ARGS); 3879 gas_assert (b_op->op_data < (unsigned) old_insn->ntok); 3880 src_exp = &old_insn->tok[b_op->op_data]; 3881 exp = &new_insn->tok[b_op->op_num]; 3882 copy_expr (exp, src_exp); 3883 break; 3884 3885 case OP_LITERAL: 3886 case OP_LABEL: 3887 as_bad (_("can't handle generation of literal/labels yet")); 3888 gas_assert (0); 3889 3890 default: 3891 as_bad (_("can't handle undefined OP TYPE")); 3892 gas_assert (0); 3893 } 3894 } 3895 3896 new_insn->ntok = num_ops; 3897 return FALSE; 3898 } 3899 3900 3901 /* Return TRUE if it was simplified. */ 3902 3903 static bfd_boolean 3904 xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) 3905 { 3906 TransitionRule *rule; 3907 BuildInstr *insn_spec; 3908 3909 if (old_insn->is_specific_opcode || !density_supported) 3910 return FALSE; 3911 3912 rule = xg_instruction_match (old_insn); 3913 if (rule == NULL) 3914 return FALSE; 3915 3916 insn_spec = rule->to_instr; 3917 /* There should only be one. */ 3918 gas_assert (insn_spec != NULL); 3919 gas_assert (insn_spec->next == NULL); 3920 if (insn_spec->next != NULL) 3921 return FALSE; 3922 3923 xg_build_token_insn (insn_spec, old_insn, new_insn); 3924 3925 return TRUE; 3926 } 3927 3928 3929 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> 3930 l32i.n. (2) Check the number of operands. (3) Place the instruction 3931 tokens into the stack or relax it and place multiple 3932 instructions/literals onto the stack. Return FALSE if no error. */ 3933 3934 static bfd_boolean 3935 xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) 3936 { 3937 int noperands; 3938 TInsn new_insn; 3939 bfd_boolean do_expand; 3940 3941 tinsn_init (&new_insn); 3942 3943 /* Narrow it if we can. xg_simplify_insn now does all the 3944 appropriate checking (e.g., for the density option). */ 3945 if (xg_simplify_insn (orig_insn, &new_insn)) 3946 orig_insn = &new_insn; 3947 3948 noperands = xtensa_opcode_num_operands (xtensa_default_isa, 3949 orig_insn->opcode); 3950 if (orig_insn->ntok < noperands) 3951 { 3952 as_bad (_("found %d operands for '%s': Expected %d"), 3953 orig_insn->ntok, 3954 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 3955 noperands); 3956 return TRUE; 3957 } 3958 if (orig_insn->ntok > noperands) 3959 as_warn (_("found too many (%d) operands for '%s': Expected %d"), 3960 orig_insn->ntok, 3961 xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), 3962 noperands); 3963 3964 /* If there are not enough operands, we will assert above. If there 3965 are too many, just cut out the extras here. */ 3966 orig_insn->ntok = noperands; 3967 3968 if (tinsn_has_invalid_symbolic_operands (orig_insn)) 3969 return TRUE; 3970 3971 /* Special case for extui opcode which has constraints not handled 3972 by the ordinary operand encoding checks. The number of operands 3973 and related syntax issues have already been checked. */ 3974 if (orig_insn->opcode == xtensa_extui_opcode) 3975 { 3976 int shiftimm = orig_insn->tok[2].X_add_number; 3977 int maskimm = orig_insn->tok[3].X_add_number; 3978 if (shiftimm + maskimm > 32) 3979 { 3980 as_bad (_("immediate operands sum to greater than 32")); 3981 return TRUE; 3982 } 3983 } 3984 3985 /* If the instruction will definitely need to be relaxed, it is better 3986 to expand it now for better scheduling. Decide whether to expand 3987 now.... */ 3988 do_expand = (!orig_insn->is_specific_opcode && use_transform ()); 3989 3990 /* Calls should be expanded to longcalls only in the backend relaxation 3991 so that the assembly scheduler will keep the L32R/CALLX instructions 3992 adjacent. */ 3993 if (is_direct_call_opcode (orig_insn->opcode)) 3994 do_expand = FALSE; 3995 3996 if (tinsn_has_symbolic_operands (orig_insn)) 3997 { 3998 /* The values of symbolic operands are not known yet, so only expand 3999 now if an operand is "complex" (e.g., difference of symbols) and 4000 will have to be stored as a literal regardless of the value. */ 4001 if (!tinsn_has_complex_operands (orig_insn)) 4002 do_expand = FALSE; 4003 } 4004 else if (xg_immeds_fit (orig_insn)) 4005 do_expand = FALSE; 4006 4007 if (do_expand) 4008 xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); 4009 else 4010 istack_push (istack, orig_insn); 4011 4012 return FALSE; 4013 } 4014 4015 4016 /* Return TRUE if the section flags are marked linkonce 4017 or the name is .gnu.linkonce.*. */ 4018 4019 static int linkonce_len = sizeof (".gnu.linkonce.") - 1; 4020 4021 static bfd_boolean 4022 get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) 4023 { 4024 flagword flags, link_once_flags; 4025 4026 flags = bfd_get_section_flags (abfd, sec); 4027 link_once_flags = (flags & SEC_LINK_ONCE); 4028 4029 /* Flags might not be set yet. */ 4030 if (!link_once_flags 4031 && strncmp (segment_name (sec), ".gnu.linkonce.", linkonce_len) == 0) 4032 link_once_flags = SEC_LINK_ONCE; 4033 4034 return (link_once_flags != 0); 4035 } 4036 4037 4038 static void 4039 xtensa_add_literal_sym (symbolS *sym) 4040 { 4041 sym_list *l; 4042 4043 l = (sym_list *) xmalloc (sizeof (sym_list)); 4044 l->sym = sym; 4045 l->next = literal_syms; 4046 literal_syms = l; 4047 } 4048 4049 4050 static symbolS * 4051 xtensa_create_literal_symbol (segT sec, fragS *frag) 4052 { 4053 static int lit_num = 0; 4054 static char name[256]; 4055 symbolS *symbolP; 4056 4057 sprintf (name, ".L_lit_sym%d", lit_num); 4058 4059 /* Create a local symbol. If it is in a linkonce section, we have to 4060 be careful to make sure that if it is used in a relocation that the 4061 symbol will be in the output file. */ 4062 if (get_is_linkonce_section (stdoutput, sec)) 4063 { 4064 symbolP = symbol_new (name, sec, 0, frag); 4065 S_CLEAR_EXTERNAL (symbolP); 4066 /* symbolP->local = 1; */ 4067 } 4068 else 4069 symbolP = symbol_new (name, sec, 0, frag); 4070 4071 xtensa_add_literal_sym (symbolP); 4072 4073 lit_num++; 4074 return symbolP; 4075 } 4076 4077 4078 /* Currently all literals that are generated here are 32-bit L32R targets. */ 4079 4080 static symbolS * 4081 xg_assemble_literal (/* const */ TInsn *insn) 4082 { 4083 emit_state state; 4084 symbolS *lit_sym = NULL; 4085 bfd_reloc_code_real_type reloc; 4086 bfd_boolean pcrel = FALSE; 4087 char *p; 4088 4089 /* size = 4 for L32R. It could easily be larger when we move to 4090 larger constants. Add a parameter later. */ 4091 offsetT litsize = 4; 4092 offsetT litalign = 2; /* 2^2 = 4 */ 4093 expressionS saved_loc; 4094 expressionS * emit_val; 4095 4096 set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); 4097 4098 gas_assert (insn->insn_type == ITYPE_LITERAL); 4099 gas_assert (insn->ntok == 1); /* must be only one token here */ 4100 4101 xtensa_switch_to_literal_fragment (&state); 4102 4103 emit_val = &insn->tok[0]; 4104 if (emit_val->X_op == O_big) 4105 { 4106 int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; 4107 if (size > litsize) 4108 { 4109 /* This happens when someone writes a "movi a2, big_number". */ 4110 as_bad_where (frag_now->fr_file, frag_now->fr_line, 4111 _("invalid immediate")); 4112 xtensa_restore_emit_state (&state); 4113 return NULL; 4114 } 4115 } 4116 4117 /* Force a 4-byte align here. Note that this opens a new frag, so all 4118 literals done with this function have a frag to themselves. That's 4119 important for the way text section literals work. */ 4120 frag_align (litalign, 0, 0); 4121 record_alignment (now_seg, litalign); 4122 4123 switch (emit_val->X_op) 4124 { 4125 case O_pcrel: 4126 pcrel = TRUE; 4127 /* fall through */ 4128 case O_pltrel: 4129 case O_tlsfunc: 4130 case O_tlsarg: 4131 case O_tpoff: 4132 case O_dtpoff: 4133 p = frag_more (litsize); 4134 xtensa_set_frag_assembly_state (frag_now); 4135 reloc = map_operator_to_reloc (emit_val->X_op, TRUE); 4136 if (emit_val->X_add_symbol) 4137 emit_val->X_op = O_symbol; 4138 else 4139 emit_val->X_op = O_constant; 4140 fix_new_exp (frag_now, p - frag_now->fr_literal, 4141 litsize, emit_val, pcrel, reloc); 4142 break; 4143 4144 default: 4145 emit_expr (emit_val, litsize); 4146 break; 4147 } 4148 4149 gas_assert (frag_now->tc_frag_data.literal_frag == NULL); 4150 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4151 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4152 lit_sym = frag_now->fr_symbol; 4153 4154 /* Go back. */ 4155 xtensa_restore_emit_state (&state); 4156 return lit_sym; 4157 } 4158 4159 4160 static void 4161 xg_assemble_literal_space (/* const */ int size, int slot) 4162 { 4163 emit_state state; 4164 /* We might have to do something about this alignment. It only 4165 takes effect if something is placed here. */ 4166 offsetT litalign = 2; /* 2^2 = 4 */ 4167 fragS *lit_saved_frag; 4168 4169 gas_assert (size % 4 == 0); 4170 4171 xtensa_switch_to_literal_fragment (&state); 4172 4173 /* Force a 4-byte align here. */ 4174 frag_align (litalign, 0, 0); 4175 record_alignment (now_seg, litalign); 4176 4177 frag_grow (size); 4178 4179 lit_saved_frag = frag_now; 4180 frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); 4181 frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); 4182 xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); 4183 4184 /* Go back. */ 4185 xtensa_restore_emit_state (&state); 4186 frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; 4187 } 4188 4189 4190 /* Put in a fixup record based on the opcode. 4191 Return TRUE on success. */ 4192 4193 static bfd_boolean 4194 xg_add_opcode_fix (TInsn *tinsn, 4195 int opnum, 4196 xtensa_format fmt, 4197 int slot, 4198 expressionS *exp, 4199 fragS *fragP, 4200 offsetT offset) 4201 { 4202 xtensa_opcode opcode = tinsn->opcode; 4203 bfd_reloc_code_real_type reloc; 4204 reloc_howto_type *howto; 4205 int fmt_length; 4206 fixS *the_fix; 4207 4208 reloc = BFD_RELOC_NONE; 4209 4210 /* First try the special cases for "alternate" relocs. */ 4211 if (opcode == xtensa_l32r_opcode) 4212 { 4213 if (fragP->tc_frag_data.use_absolute_literals) 4214 reloc = encode_alt_reloc (slot); 4215 } 4216 else if (opcode == xtensa_const16_opcode) 4217 { 4218 if (exp->X_op == O_lo16) 4219 { 4220 reloc = encode_reloc (slot); 4221 exp->X_op = O_symbol; 4222 } 4223 else if (exp->X_op == O_hi16) 4224 { 4225 reloc = encode_alt_reloc (slot); 4226 exp->X_op = O_symbol; 4227 } 4228 } 4229 4230 if (opnum != get_relaxable_immed (opcode)) 4231 { 4232 as_bad (_("invalid relocation for operand %i of '%s'"), 4233 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4234 return FALSE; 4235 } 4236 4237 /* Handle erroneous "@h" and "@l" expressions here before they propagate 4238 into the symbol table where the generic portions of the assembler 4239 won't know what to do with them. */ 4240 if (exp->X_op == O_lo16 || exp->X_op == O_hi16) 4241 { 4242 as_bad (_("invalid expression for operand %i of '%s'"), 4243 opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); 4244 return FALSE; 4245 } 4246 4247 /* Next try the generic relocs. */ 4248 if (reloc == BFD_RELOC_NONE) 4249 reloc = encode_reloc (slot); 4250 if (reloc == BFD_RELOC_NONE) 4251 { 4252 as_bad (_("invalid relocation in instruction slot %i"), slot); 4253 return FALSE; 4254 } 4255 4256 howto = bfd_reloc_type_lookup (stdoutput, reloc); 4257 if (!howto) 4258 { 4259 as_bad (_("undefined symbol for opcode \"%s\""), 4260 xtensa_opcode_name (xtensa_default_isa, opcode)); 4261 return FALSE; 4262 } 4263 4264 fmt_length = xtensa_format_length (xtensa_default_isa, fmt); 4265 the_fix = fix_new_exp (fragP, offset, fmt_length, exp, 4266 howto->pc_relative, reloc); 4267 the_fix->fx_no_overflow = 1; 4268 the_fix->tc_fix_data.X_add_symbol = exp->X_add_symbol; 4269 the_fix->tc_fix_data.X_add_number = exp->X_add_number; 4270 the_fix->tc_fix_data.slot = slot; 4271 4272 return TRUE; 4273 } 4274 4275 4276 static bfd_boolean 4277 xg_emit_insn_to_buf (TInsn *tinsn, 4278 char *buf, 4279 fragS *fragP, 4280 offsetT offset, 4281 bfd_boolean build_fix) 4282 { 4283 static xtensa_insnbuf insnbuf = NULL; 4284 bfd_boolean has_symbolic_immed = FALSE; 4285 bfd_boolean ok = TRUE; 4286 4287 if (!insnbuf) 4288 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4289 4290 has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); 4291 if (has_symbolic_immed && build_fix) 4292 { 4293 /* Add a fixup. */ 4294 xtensa_format fmt = xg_get_single_format (tinsn->opcode); 4295 int slot = xg_get_single_slot (tinsn->opcode); 4296 int opnum = get_relaxable_immed (tinsn->opcode); 4297 expressionS *exp = &tinsn->tok[opnum]; 4298 4299 if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) 4300 ok = FALSE; 4301 } 4302 fragP->tc_frag_data.is_insn = TRUE; 4303 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4304 (unsigned char *) buf, 0); 4305 return ok; 4306 } 4307 4308 4309 static void 4310 xg_resolve_literals (TInsn *insn, symbolS *lit_sym) 4311 { 4312 symbolS *sym = get_special_literal_symbol (); 4313 int i; 4314 if (lit_sym == 0) 4315 return; 4316 gas_assert (insn->insn_type == ITYPE_INSN); 4317 for (i = 0; i < insn->ntok; i++) 4318 if (insn->tok[i].X_add_symbol == sym) 4319 insn->tok[i].X_add_symbol = lit_sym; 4320 4321 } 4322 4323 4324 static void 4325 xg_resolve_labels (TInsn *insn, symbolS *label_sym) 4326 { 4327 symbolS *sym = get_special_label_symbol (); 4328 int i; 4329 for (i = 0; i < insn->ntok; i++) 4330 if (insn->tok[i].X_add_symbol == sym) 4331 insn->tok[i].X_add_symbol = label_sym; 4332 4333 } 4334 4335 4336 /* Return TRUE if the instruction can write to the specified 4337 integer register. */ 4338 4339 static bfd_boolean 4340 is_register_writer (const TInsn *insn, const char *regset, int regnum) 4341 { 4342 int i; 4343 int num_ops; 4344 xtensa_isa isa = xtensa_default_isa; 4345 4346 num_ops = xtensa_opcode_num_operands (isa, insn->opcode); 4347 4348 for (i = 0; i < num_ops; i++) 4349 { 4350 char inout; 4351 inout = xtensa_operand_inout (isa, insn->opcode, i); 4352 if ((inout == 'o' || inout == 'm') 4353 && xtensa_operand_is_register (isa, insn->opcode, i) == 1) 4354 { 4355 xtensa_regfile opnd_rf = 4356 xtensa_operand_regfile (isa, insn->opcode, i); 4357 if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) 4358 { 4359 if ((insn->tok[i].X_op == O_register) 4360 && (insn->tok[i].X_add_number == regnum)) 4361 return TRUE; 4362 } 4363 } 4364 } 4365 return FALSE; 4366 } 4367 4368 4369 static bfd_boolean 4370 is_bad_loopend_opcode (const TInsn *tinsn) 4371 { 4372 xtensa_opcode opcode = tinsn->opcode; 4373 4374 if (opcode == XTENSA_UNDEFINED) 4375 return FALSE; 4376 4377 if (opcode == xtensa_call0_opcode 4378 || opcode == xtensa_callx0_opcode 4379 || opcode == xtensa_call4_opcode 4380 || opcode == xtensa_callx4_opcode 4381 || opcode == xtensa_call8_opcode 4382 || opcode == xtensa_callx8_opcode 4383 || opcode == xtensa_call12_opcode 4384 || opcode == xtensa_callx12_opcode 4385 || opcode == xtensa_isync_opcode 4386 || opcode == xtensa_ret_opcode 4387 || opcode == xtensa_ret_n_opcode 4388 || opcode == xtensa_retw_opcode 4389 || opcode == xtensa_retw_n_opcode 4390 || opcode == xtensa_waiti_opcode 4391 || opcode == xtensa_rsr_lcount_opcode) 4392 return TRUE; 4393 4394 return FALSE; 4395 } 4396 4397 4398 /* Labels that begin with ".Ln" or ".LM" are unaligned. 4399 This allows the debugger to add unaligned labels. 4400 Also, the assembler generates stabs labels that need 4401 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ 4402 4403 static bfd_boolean 4404 is_unaligned_label (symbolS *sym) 4405 { 4406 const char *name = S_GET_NAME (sym); 4407 static size_t fake_size = 0; 4408 4409 if (name 4410 && name[0] == '.' 4411 && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) 4412 return TRUE; 4413 4414 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ 4415 if (fake_size == 0) 4416 fake_size = strlen (FAKE_LABEL_NAME); 4417 4418 if (name 4419 && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 4420 && (name[fake_size] == 'F' 4421 || name[fake_size] == 'L' 4422 || (name[fake_size] == 'e' 4423 && strncmp ("endfunc", name+fake_size, 7) == 0))) 4424 return TRUE; 4425 4426 return FALSE; 4427 } 4428 4429 4430 static fragS * 4431 next_non_empty_frag (const fragS *fragP) 4432 { 4433 fragS *next_fragP = fragP->fr_next; 4434 4435 /* Sometimes an empty will end up here due storage allocation issues. 4436 So we have to skip until we find something legit. */ 4437 while (next_fragP && next_fragP->fr_fix == 0) 4438 next_fragP = next_fragP->fr_next; 4439 4440 if (next_fragP == NULL || next_fragP->fr_fix == 0) 4441 return NULL; 4442 4443 return next_fragP; 4444 } 4445 4446 4447 static bfd_boolean 4448 next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) 4449 { 4450 xtensa_opcode out_opcode; 4451 const fragS *next_fragP = next_non_empty_frag (fragP); 4452 4453 if (next_fragP == NULL) 4454 return FALSE; 4455 4456 out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); 4457 if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) 4458 { 4459 *opcode = out_opcode; 4460 return TRUE; 4461 } 4462 return FALSE; 4463 } 4464 4465 4466 static int 4467 frag_format_size (const fragS *fragP) 4468 { 4469 static xtensa_insnbuf insnbuf = NULL; 4470 xtensa_isa isa = xtensa_default_isa; 4471 xtensa_format fmt; 4472 int fmt_size; 4473 4474 if (!insnbuf) 4475 insnbuf = xtensa_insnbuf_alloc (isa); 4476 4477 if (fragP == NULL) 4478 return XTENSA_UNDEFINED; 4479 4480 xtensa_insnbuf_from_chars (isa, insnbuf, 4481 (unsigned char *) fragP->fr_literal, 0); 4482 4483 fmt = xtensa_format_decode (isa, insnbuf); 4484 if (fmt == XTENSA_UNDEFINED) 4485 return XTENSA_UNDEFINED; 4486 fmt_size = xtensa_format_length (isa, fmt); 4487 4488 /* If the next format won't be changing due to relaxation, just 4489 return the length of the first format. */ 4490 if (fragP->fr_opcode != fragP->fr_literal) 4491 return fmt_size; 4492 4493 /* If during relaxation we have to pull an instruction out of a 4494 multi-slot instruction, we will return the more conservative 4495 number. This works because alignment on bigger instructions 4496 is more restrictive than alignment on smaller instructions. 4497 This is more conservative than we would like, but it happens 4498 infrequently. */ 4499 4500 if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) 4501 return fmt_size; 4502 4503 /* If we aren't doing one of our own relaxations or it isn't 4504 slot-based, then the insn size won't change. */ 4505 if (fragP->fr_type != rs_machine_dependent) 4506 return fmt_size; 4507 if (fragP->fr_subtype != RELAX_SLOTS) 4508 return fmt_size; 4509 4510 /* If an instruction is about to grow, return the longer size. */ 4511 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 4512 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2 4513 || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP3) 4514 { 4515 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first 4516 instruction in the relaxed version is of length 3. (The case 4517 where we have to pull the instruction out of a FLIX bundle 4518 is handled conservatively above.) However, frags with opcodes 4519 that are expanding to wide branches end up having formats that 4520 are not determinable by the RELAX_IMMED_STEPX enumeration, and 4521 we can't tell directly what format the relaxer picked. This 4522 is a wart in the design of the relaxer that should someday be 4523 fixed, but would require major changes, or at least should 4524 be accompanied by major changes to make use of that data. 4525 4526 In any event, we can tell that we are expanding from a single-slot 4527 format to a wider one with the logic below. */ 4528 4529 int i; 4530 int relaxed_size = fmt_size + fragP->tc_frag_data.text_expansion[0]; 4531 4532 for (i = 0; i < xtensa_isa_num_formats (isa); i++) 4533 { 4534 if (relaxed_size == xtensa_format_length (isa, i)) 4535 return relaxed_size; 4536 } 4537 4538 return 3; 4539 } 4540 4541 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 4542 return 2 + fragP->tc_frag_data.text_expansion[0]; 4543 4544 return fmt_size; 4545 } 4546 4547 4548 static int 4549 next_frag_format_size (const fragS *fragP) 4550 { 4551 const fragS *next_fragP = next_non_empty_frag (fragP); 4552 return frag_format_size (next_fragP); 4553 } 4554 4555 4556 /* In early Xtensa Processors, for reasons that are unclear, the ISA 4557 required two-byte instructions to be treated as three-byte instructions 4558 for loop instruction alignment. This restriction was removed beginning 4559 with Xtensa LX. Now the only requirement on loop instruction alignment 4560 is that the first instruction of the loop must appear at an address that 4561 does not cross a fetch boundary. */ 4562 4563 static int 4564 get_loop_align_size (int insn_size) 4565 { 4566 if (insn_size == XTENSA_UNDEFINED) 4567 return xtensa_fetch_width; 4568 4569 if (enforce_three_byte_loop_align && insn_size == 2) 4570 return 3; 4571 4572 return insn_size; 4573 } 4574 4575 4576 /* If the next legit fragment is an end-of-loop marker, 4577 switch its state so it will instantiate a NOP. */ 4578 4579 static void 4580 update_next_frag_state (fragS *fragP) 4581 { 4582 fragS *next_fragP = fragP->fr_next; 4583 fragS *new_target = NULL; 4584 4585 if (align_targets) 4586 { 4587 /* We are guaranteed there will be one of these... */ 4588 while (!(next_fragP->fr_type == rs_machine_dependent 4589 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4590 || next_fragP->fr_subtype == RELAX_UNREACHABLE))) 4591 next_fragP = next_fragP->fr_next; 4592 4593 gas_assert (next_fragP->fr_type == rs_machine_dependent 4594 && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE 4595 || next_fragP->fr_subtype == RELAX_UNREACHABLE)); 4596 4597 /* ...and one of these. */ 4598 new_target = next_fragP->fr_next; 4599 while (!(new_target->fr_type == rs_machine_dependent 4600 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4601 || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) 4602 new_target = new_target->fr_next; 4603 4604 gas_assert (new_target->fr_type == rs_machine_dependent 4605 && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN 4606 || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); 4607 } 4608 4609 while (next_fragP && next_fragP->fr_fix == 0) 4610 { 4611 if (next_fragP->fr_type == rs_machine_dependent 4612 && next_fragP->fr_subtype == RELAX_LOOP_END) 4613 { 4614 next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; 4615 return; 4616 } 4617 4618 next_fragP = next_fragP->fr_next; 4619 } 4620 } 4621 4622 4623 static bfd_boolean 4624 next_frag_is_branch_target (const fragS *fragP) 4625 { 4626 /* Sometimes an empty will end up here due to storage allocation issues, 4627 so we have to skip until we find something legit. */ 4628 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4629 { 4630 if (fragP->tc_frag_data.is_branch_target) 4631 return TRUE; 4632 if (fragP->fr_fix != 0) 4633 break; 4634 } 4635 return FALSE; 4636 } 4637 4638 4639 static bfd_boolean 4640 next_frag_is_loop_target (const fragS *fragP) 4641 { 4642 /* Sometimes an empty will end up here due storage allocation issues. 4643 So we have to skip until we find something legit. */ 4644 for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) 4645 { 4646 if (fragP->tc_frag_data.is_loop_target) 4647 return TRUE; 4648 if (fragP->fr_fix != 0) 4649 break; 4650 } 4651 return FALSE; 4652 } 4653 4654 4655 /* As specified in the relaxation table, when a loop instruction is 4656 relaxed, there are 24 bytes between the loop instruction itself and 4657 the first instruction in the loop. */ 4658 4659 #define RELAXED_LOOP_INSN_BYTES 24 4660 4661 static addressT 4662 next_frag_pre_opcode_bytes (const fragS *fragp) 4663 { 4664 const fragS *next_fragp = fragp->fr_next; 4665 xtensa_opcode next_opcode; 4666 4667 if (!next_frag_opcode_is_loop (fragp, &next_opcode)) 4668 return 0; 4669 4670 /* Sometimes an empty will end up here due to storage allocation issues, 4671 so we have to skip until we find something legit. */ 4672 while (next_fragp->fr_fix == 0) 4673 next_fragp = next_fragp->fr_next; 4674 4675 if (next_fragp->fr_type != rs_machine_dependent) 4676 return 0; 4677 4678 /* There is some implicit knowledge encoded in here. 4679 The LOOP instructions that are NOT RELAX_IMMED have 4680 been relaxed. Note that we can assume that the LOOP 4681 instruction is in slot 0 because loops aren't bundleable. */ 4682 if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) 4683 return get_expanded_loop_offset (next_opcode) + RELAXED_LOOP_INSN_BYTES; 4684 4685 return 0; 4686 } 4687 4688 4689 /* Mark a location where we can later insert literal frags. Update 4690 the section's literal_pool_loc, so subsequent literals can be 4691 placed nearest to their use. */ 4692 4693 static void 4694 xtensa_mark_literal_pool_location (void) 4695 { 4696 /* Any labels pointing to the current location need 4697 to be adjusted to after the literal pool. */ 4698 emit_state s; 4699 fragS *pool_location; 4700 4701 if (use_literal_section) 4702 return; 4703 4704 /* We stash info in these frags so we can later move the literal's 4705 fixes into this frchain's fix list. */ 4706 pool_location = frag_now; 4707 frag_now->tc_frag_data.lit_frchain = frchain_now; 4708 frag_now->tc_frag_data.literal_frag = frag_now; 4709 frag_variant (rs_machine_dependent, 0, 0, 4710 RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); 4711 xtensa_set_frag_assembly_state (frag_now); 4712 frag_now->tc_frag_data.lit_seg = now_seg; 4713 frag_variant (rs_machine_dependent, 0, 0, 4714 RELAX_LITERAL_POOL_END, NULL, 0, NULL); 4715 xtensa_set_frag_assembly_state (frag_now); 4716 4717 /* Now put a frag into the literal pool that points to this location. */ 4718 set_literal_pool_location (now_seg, pool_location); 4719 xtensa_switch_to_non_abs_literal_fragment (&s); 4720 frag_align (2, 0, 0); 4721 record_alignment (now_seg, 2); 4722 4723 /* Close whatever frag is there. */ 4724 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 4725 xtensa_set_frag_assembly_state (frag_now); 4726 frag_now->tc_frag_data.literal_frag = pool_location; 4727 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 4728 xtensa_restore_emit_state (&s); 4729 xtensa_set_frag_assembly_state (frag_now); 4730 } 4731 4732 4733 /* Build a nop of the correct size into tinsn. */ 4734 4735 static void 4736 build_nop (TInsn *tinsn, int size) 4737 { 4738 tinsn_init (tinsn); 4739 switch (size) 4740 { 4741 case 2: 4742 tinsn->opcode = xtensa_nop_n_opcode; 4743 tinsn->ntok = 0; 4744 if (tinsn->opcode == XTENSA_UNDEFINED) 4745 as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); 4746 break; 4747 4748 case 3: 4749 if (xtensa_nop_opcode == XTENSA_UNDEFINED) 4750 { 4751 tinsn->opcode = xtensa_or_opcode; 4752 set_expr_const (&tinsn->tok[0], 1); 4753 set_expr_const (&tinsn->tok[1], 1); 4754 set_expr_const (&tinsn->tok[2], 1); 4755 tinsn->ntok = 3; 4756 } 4757 else 4758 tinsn->opcode = xtensa_nop_opcode; 4759 4760 gas_assert (tinsn->opcode != XTENSA_UNDEFINED); 4761 } 4762 } 4763 4764 4765 /* Assemble a NOP of the requested size in the buffer. User must have 4766 allocated "buf" with at least "size" bytes. */ 4767 4768 static void 4769 assemble_nop (int size, char *buf) 4770 { 4771 static xtensa_insnbuf insnbuf = NULL; 4772 TInsn tinsn; 4773 4774 build_nop (&tinsn, size); 4775 4776 if (!insnbuf) 4777 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 4778 4779 tinsn_to_insnbuf (&tinsn, insnbuf); 4780 xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, 4781 (unsigned char *) buf, 0); 4782 } 4783 4784 4785 /* Return the number of bytes for the offset of the expanded loop 4786 instruction. This should be incorporated into the relaxation 4787 specification but is hard-coded here. This is used to auto-align 4788 the loop instruction. It is invalid to call this function if the 4789 configuration does not have loops or if the opcode is not a loop 4790 opcode. */ 4791 4792 static addressT 4793 get_expanded_loop_offset (xtensa_opcode opcode) 4794 { 4795 /* This is the OFFSET of the loop instruction in the expanded loop. 4796 This MUST correspond directly to the specification of the loop 4797 expansion. It will be validated on fragment conversion. */ 4798 gas_assert (opcode != XTENSA_UNDEFINED); 4799 if (opcode == xtensa_loop_opcode) 4800 return 0; 4801 if (opcode == xtensa_loopnez_opcode) 4802 return 3; 4803 if (opcode == xtensa_loopgtz_opcode) 4804 return 6; 4805 as_fatal (_("get_expanded_loop_offset: invalid opcode")); 4806 return 0; 4807 } 4808 4809 4810 static fragS * 4811 get_literal_pool_location (segT seg) 4812 { 4813 return seg_info (seg)->tc_segment_info_data.literal_pool_loc; 4814 } 4815 4816 4817 static void 4818 set_literal_pool_location (segT seg, fragS *literal_pool_loc) 4819 { 4820 seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; 4821 } 4822 4823 4824 /* Set frag assembly state should be called when a new frag is 4825 opened and after a frag has been closed. */ 4826 4827 static void 4828 xtensa_set_frag_assembly_state (fragS *fragP) 4829 { 4830 if (!density_supported) 4831 fragP->tc_frag_data.is_no_density = TRUE; 4832 4833 /* This function is called from subsegs_finish, which is called 4834 after xtensa_end, so we can't use "use_transform" or 4835 "use_schedule" here. */ 4836 if (!directive_state[directive_transform]) 4837 fragP->tc_frag_data.is_no_transform = TRUE; 4838 if (directive_state[directive_longcalls]) 4839 fragP->tc_frag_data.use_longcalls = TRUE; 4840 fragP->tc_frag_data.use_absolute_literals = 4841 directive_state[directive_absolute_literals]; 4842 fragP->tc_frag_data.is_assembly_state_set = TRUE; 4843 } 4844 4845 4846 static bfd_boolean 4847 relaxable_section (asection *sec) 4848 { 4849 return ((sec->flags & SEC_DEBUGGING) == 0 4850 && strcmp (sec->name, ".eh_frame") != 0); 4851 } 4852 4853 4854 static void 4855 xtensa_mark_frags_for_org (void) 4856 { 4857 segT *seclist; 4858 4859 /* Walk over each fragment of all of the current segments. If we find 4860 a .org frag in any of the segments, mark all frags prior to it as 4861 "no transform", which will prevent linker optimizations from messing 4862 up the .org distance. This should be done after 4863 xtensa_find_unmarked_state_frags, because we don't want to worry here 4864 about that function trashing the data we save here. */ 4865 4866 for (seclist = &stdoutput->sections; 4867 seclist && *seclist; 4868 seclist = &(*seclist)->next) 4869 { 4870 segT sec = *seclist; 4871 segment_info_type *seginfo; 4872 fragS *fragP; 4873 flagword flags; 4874 flags = bfd_get_section_flags (stdoutput, sec); 4875 if (flags & SEC_DEBUGGING) 4876 continue; 4877 if (!(flags & SEC_ALLOC)) 4878 continue; 4879 4880 seginfo = seg_info (sec); 4881 if (seginfo && seginfo->frchainP) 4882 { 4883 fragS *last_fragP = seginfo->frchainP->frch_root; 4884 for (fragP = seginfo->frchainP->frch_root; fragP; 4885 fragP = fragP->fr_next) 4886 { 4887 /* cvt_frag_to_fill has changed the fr_type of org frags to 4888 rs_fill, so use the value as cached in rs_subtype here. */ 4889 if (fragP->fr_subtype == RELAX_ORG) 4890 { 4891 while (last_fragP != fragP->fr_next) 4892 { 4893 last_fragP->tc_frag_data.is_no_transform = TRUE; 4894 last_fragP = last_fragP->fr_next; 4895 } 4896 } 4897 } 4898 } 4899 } 4900 } 4901 4902 4903 static void 4904 xtensa_find_unmarked_state_frags (void) 4905 { 4906 segT *seclist; 4907 4908 /* Walk over each fragment of all of the current segments. For each 4909 unmarked fragment, mark it with the same info as the previous 4910 fragment. */ 4911 for (seclist = &stdoutput->sections; 4912 seclist && *seclist; 4913 seclist = &(*seclist)->next) 4914 { 4915 segT sec = *seclist; 4916 segment_info_type *seginfo; 4917 fragS *fragP; 4918 flagword flags; 4919 flags = bfd_get_section_flags (stdoutput, sec); 4920 if (flags & SEC_DEBUGGING) 4921 continue; 4922 if (!(flags & SEC_ALLOC)) 4923 continue; 4924 4925 seginfo = seg_info (sec); 4926 if (seginfo && seginfo->frchainP) 4927 { 4928 fragS *last_fragP = 0; 4929 for (fragP = seginfo->frchainP->frch_root; fragP; 4930 fragP = fragP->fr_next) 4931 { 4932 if (fragP->fr_fix != 0 4933 && !fragP->tc_frag_data.is_assembly_state_set) 4934 { 4935 if (last_fragP == 0) 4936 { 4937 as_warn_where (fragP->fr_file, fragP->fr_line, 4938 _("assembly state not set for first frag in section %s"), 4939 sec->name); 4940 } 4941 else 4942 { 4943 fragP->tc_frag_data.is_assembly_state_set = TRUE; 4944 fragP->tc_frag_data.is_no_density = 4945 last_fragP->tc_frag_data.is_no_density; 4946 fragP->tc_frag_data.is_no_transform = 4947 last_fragP->tc_frag_data.is_no_transform; 4948 fragP->tc_frag_data.use_longcalls = 4949 last_fragP->tc_frag_data.use_longcalls; 4950 fragP->tc_frag_data.use_absolute_literals = 4951 last_fragP->tc_frag_data.use_absolute_literals; 4952 } 4953 } 4954 if (fragP->tc_frag_data.is_assembly_state_set) 4955 last_fragP = fragP; 4956 } 4957 } 4958 } 4959 } 4960 4961 4962 static void 4963 xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, 4964 asection *sec, 4965 void *unused ATTRIBUTE_UNUSED) 4966 { 4967 flagword flags = bfd_get_section_flags (abfd, sec); 4968 segment_info_type *seginfo = seg_info (sec); 4969 fragS *frag = seginfo->frchainP->frch_root; 4970 4971 if (flags & SEC_CODE) 4972 { 4973 xtensa_isa isa = xtensa_default_isa; 4974 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 4975 while (frag != NULL) 4976 { 4977 if (frag->tc_frag_data.is_branch_target) 4978 { 4979 int op_size; 4980 addressT branch_align, frag_addr; 4981 xtensa_format fmt; 4982 4983 xtensa_insnbuf_from_chars 4984 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 4985 fmt = xtensa_format_decode (isa, insnbuf); 4986 op_size = xtensa_format_length (isa, fmt); 4987 branch_align = 1 << branch_align_power (sec); 4988 frag_addr = frag->fr_address % branch_align; 4989 if (frag_addr + op_size > branch_align) 4990 as_warn_where (frag->fr_file, frag->fr_line, 4991 _("unaligned branch target: %d bytes at 0x%lx"), 4992 op_size, (long) frag->fr_address); 4993 } 4994 frag = frag->fr_next; 4995 } 4996 xtensa_insnbuf_free (isa, insnbuf); 4997 } 4998 } 4999 5000 5001 static void 5002 xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, 5003 asection *sec, 5004 void *unused ATTRIBUTE_UNUSED) 5005 { 5006 flagword flags = bfd_get_section_flags (abfd, sec); 5007 segment_info_type *seginfo = seg_info (sec); 5008 fragS *frag = seginfo->frchainP->frch_root; 5009 xtensa_isa isa = xtensa_default_isa; 5010 5011 if (flags & SEC_CODE) 5012 { 5013 xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); 5014 while (frag != NULL) 5015 { 5016 if (frag->tc_frag_data.is_first_loop_insn) 5017 { 5018 int op_size; 5019 addressT frag_addr; 5020 xtensa_format fmt; 5021 5022 if (frag->fr_fix == 0) 5023 frag = next_non_empty_frag (frag); 5024 5025 if (frag) 5026 { 5027 xtensa_insnbuf_from_chars 5028 (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); 5029 fmt = xtensa_format_decode (isa, insnbuf); 5030 op_size = xtensa_format_length (isa, fmt); 5031 frag_addr = frag->fr_address % xtensa_fetch_width; 5032 5033 if (frag_addr + op_size > xtensa_fetch_width) 5034 as_warn_where (frag->fr_file, frag->fr_line, 5035 _("unaligned loop: %d bytes at 0x%lx"), 5036 op_size, (long) frag->fr_address); 5037 } 5038 } 5039 frag = frag->fr_next; 5040 } 5041 xtensa_insnbuf_free (isa, insnbuf); 5042 } 5043 } 5044 5045 5046 static int 5047 xg_apply_fix_value (fixS *fixP, valueT val) 5048 { 5049 xtensa_isa isa = xtensa_default_isa; 5050 static xtensa_insnbuf insnbuf = NULL; 5051 static xtensa_insnbuf slotbuf = NULL; 5052 xtensa_format fmt; 5053 int slot; 5054 bfd_boolean alt_reloc; 5055 xtensa_opcode opcode; 5056 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 5057 5058 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) 5059 || alt_reloc) 5060 as_fatal (_("unexpected fix")); 5061 5062 if (!insnbuf) 5063 { 5064 insnbuf = xtensa_insnbuf_alloc (isa); 5065 slotbuf = xtensa_insnbuf_alloc (isa); 5066 } 5067 5068 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 5069 fmt = xtensa_format_decode (isa, insnbuf); 5070 if (fmt == XTENSA_UNDEFINED) 5071 as_fatal (_("undecodable fix")); 5072 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 5073 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 5074 if (opcode == XTENSA_UNDEFINED) 5075 as_fatal (_("undecodable fix")); 5076 5077 /* CONST16 immediates are not PC-relative, despite the fact that we 5078 reuse the normal PC-relative operand relocations for the low part 5079 of a CONST16 operand. */ 5080 if (opcode == xtensa_const16_opcode) 5081 return 0; 5082 5083 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, 5084 get_relaxable_immed (opcode), val, 5085 fixP->fx_file, fixP->fx_line); 5086 5087 xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); 5088 xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); 5089 5090 return 1; 5091 } 5092 5093 5094 /* External Functions and Other GAS Hooks. */ 5095 5096 const char * 5097 xtensa_target_format (void) 5098 { 5099 return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); 5100 } 5101 5102 5103 void 5104 xtensa_file_arch_init (bfd *abfd) 5105 { 5106 bfd_set_private_flags (abfd, 0x100 | 0x200); 5107 } 5108 5109 5110 void 5111 md_number_to_chars (char *buf, valueT val, int n) 5112 { 5113 if (target_big_endian) 5114 number_to_chars_bigendian (buf, val, n); 5115 else 5116 number_to_chars_littleendian (buf, val, n); 5117 } 5118 5119 5120 /* This function is called once, at assembler startup time. It should 5121 set up all the tables, etc. that the MD part of the assembler will 5122 need. */ 5123 5124 void 5125 md_begin (void) 5126 { 5127 segT current_section = now_seg; 5128 int current_subsec = now_subseg; 5129 xtensa_isa isa; 5130 int i; 5131 5132 xtensa_default_isa = xtensa_isa_init (0, 0); 5133 isa = xtensa_default_isa; 5134 5135 linkrelax = 1; 5136 5137 /* Set up the literal sections. */ 5138 memset (&default_lit_sections, 0, sizeof (default_lit_sections)); 5139 5140 subseg_set (current_section, current_subsec); 5141 5142 xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); 5143 xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); 5144 xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); 5145 xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); 5146 xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); 5147 xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); 5148 xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); 5149 xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); 5150 xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); 5151 xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); 5152 xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); 5153 xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); 5154 xtensa_extui_opcode = xtensa_opcode_lookup (isa, "extui"); 5155 xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); 5156 xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); 5157 xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); 5158 xtensa_j_opcode = xtensa_opcode_lookup (isa, "j"); 5159 xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); 5160 xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); 5161 xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); 5162 xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); 5163 xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); 5164 xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); 5165 xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); 5166 xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); 5167 xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); 5168 xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); 5169 xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); 5170 xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); 5171 xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); 5172 xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); 5173 5174 for (i = 0; i < xtensa_isa_num_formats (isa); i++) 5175 { 5176 int format_slots = xtensa_format_num_slots (isa, i); 5177 if (format_slots > config_max_slots) 5178 config_max_slots = format_slots; 5179 } 5180 5181 xg_init_vinsn (&cur_vinsn); 5182 5183 xtensa_num_pipe_stages = xtensa_isa_num_pipe_stages (isa); 5184 5185 init_op_placement_info_table (); 5186 5187 /* Set up the assembly state. */ 5188 if (!frag_now->tc_frag_data.is_assembly_state_set) 5189 xtensa_set_frag_assembly_state (frag_now); 5190 } 5191 5192 5193 /* TC_INIT_FIX_DATA hook */ 5194 5195 void 5196 xtensa_init_fix_data (fixS *x) 5197 { 5198 x->tc_fix_data.slot = 0; 5199 x->tc_fix_data.X_add_symbol = NULL; 5200 x->tc_fix_data.X_add_number = 0; 5201 } 5202 5203 5204 /* tc_frob_label hook */ 5205 5206 void 5207 xtensa_frob_label (symbolS *sym) 5208 { 5209 float freq; 5210 5211 if (cur_vinsn.inside_bundle) 5212 { 5213 as_bad (_("labels are not valid inside bundles")); 5214 return; 5215 } 5216 5217 freq = get_subseg_target_freq (now_seg, now_subseg); 5218 5219 /* Since the label was already attached to a frag associated with the 5220 previous basic block, it now needs to be reset to the current frag. */ 5221 symbol_set_frag (sym, frag_now); 5222 S_SET_VALUE (sym, (valueT) frag_now_fix ()); 5223 5224 if (generating_literals) 5225 xtensa_add_literal_sym (sym); 5226 else 5227 xtensa_add_insn_label (sym); 5228 5229 if (symbol_get_tc (sym)->is_loop_target) 5230 { 5231 if ((get_last_insn_flags (now_seg, now_subseg) 5232 & FLAG_IS_BAD_LOOPEND) != 0) 5233 as_bad (_("invalid last instruction for a zero-overhead loop")); 5234 5235 xtensa_set_frag_assembly_state (frag_now); 5236 frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, 5237 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5238 5239 xtensa_set_frag_assembly_state (frag_now); 5240 xtensa_move_labels (frag_now, 0); 5241 } 5242 5243 /* No target aligning in the absolute section. */ 5244 if (now_seg != absolute_section 5245 && !is_unaligned_label (sym) 5246 && !generating_literals) 5247 { 5248 xtensa_set_frag_assembly_state (frag_now); 5249 5250 if (do_align_targets ()) 5251 frag_var (rs_machine_dependent, 0, (int) freq, 5252 RELAX_DESIRE_ALIGN_IF_TARGET, frag_now->fr_symbol, 5253 frag_now->fr_offset, NULL); 5254 else 5255 frag_var (rs_fill, 0, 0, frag_now->fr_subtype, 5256 frag_now->fr_symbol, frag_now->fr_offset, NULL); 5257 xtensa_set_frag_assembly_state (frag_now); 5258 xtensa_move_labels (frag_now, 0); 5259 } 5260 5261 /* We need to mark the following properties even if we aren't aligning. */ 5262 5263 /* If the label is already known to be a branch target, i.e., a 5264 forward branch, mark the frag accordingly. Backward branches 5265 are handled by xg_add_branch_and_loop_targets. */ 5266 if (symbol_get_tc (sym)->is_branch_target) 5267 symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; 5268 5269 /* Loops only go forward, so they can be identified here. */ 5270 if (symbol_get_tc (sym)->is_loop_target) 5271 symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; 5272 5273 dwarf2_emit_label (sym); 5274 } 5275 5276 5277 /* tc_unrecognized_line hook */ 5278 5279 int 5280 xtensa_unrecognized_line (int ch) 5281 { 5282 switch (ch) 5283 { 5284 case '{' : 5285 if (cur_vinsn.inside_bundle == 0) 5286 { 5287 /* PR8110: Cannot emit line number info inside a FLIX bundle 5288 when using --gstabs. Temporarily disable debug info. */ 5289 generate_lineno_debug (); 5290 if (debug_type == DEBUG_STABS) 5291 { 5292 xt_saved_debug_type = debug_type; 5293 debug_type = DEBUG_NONE; 5294 } 5295 5296 cur_vinsn.inside_bundle = 1; 5297 } 5298 else 5299 { 5300 as_bad (_("extra opening brace")); 5301 return 0; 5302 } 5303 break; 5304 5305 case '}' : 5306 if (cur_vinsn.inside_bundle) 5307 finish_vinsn (&cur_vinsn); 5308 else 5309 { 5310 as_bad (_("extra closing brace")); 5311 return 0; 5312 } 5313 break; 5314 default: 5315 as_bad (_("syntax error")); 5316 return 0; 5317 } 5318 return 1; 5319 } 5320 5321 5322 /* md_flush_pending_output hook */ 5323 5324 void 5325 xtensa_flush_pending_output (void) 5326 { 5327 /* This line fixes a bug where automatically generated gstabs info 5328 separates a function label from its entry instruction, ending up 5329 with the literal position between the function label and the entry 5330 instruction and crashing code. It only happens with --gstabs and 5331 --text-section-literals, and when several other obscure relaxation 5332 conditions are met. */ 5333 if (outputting_stabs_line_debug) 5334 return; 5335 5336 if (cur_vinsn.inside_bundle) 5337 as_bad (_("missing closing brace")); 5338 5339 /* If there is a non-zero instruction fragment, close it. */ 5340 if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) 5341 { 5342 frag_wane (frag_now); 5343 frag_new (0); 5344 xtensa_set_frag_assembly_state (frag_now); 5345 } 5346 frag_now->tc_frag_data.is_insn = FALSE; 5347 5348 xtensa_clear_insn_labels (); 5349 } 5350 5351 5352 /* We had an error while parsing an instruction. The string might look 5353 like this: "insn arg1, arg2 }". If so, we need to see the closing 5354 brace and reset some fields. Otherwise, the vinsn never gets closed 5355 and the num_slots field will grow past the end of the array of slots, 5356 and bad things happen. */ 5357 5358 static void 5359 error_reset_cur_vinsn (void) 5360 { 5361 if (cur_vinsn.inside_bundle) 5362 { 5363 if (*input_line_pointer == '}' 5364 || *(input_line_pointer - 1) == '}' 5365 || *(input_line_pointer - 2) == '}') 5366 xg_clear_vinsn (&cur_vinsn); 5367 } 5368 } 5369 5370 5371 void 5372 md_assemble (char *str) 5373 { 5374 xtensa_isa isa = xtensa_default_isa; 5375 char *opname; 5376 unsigned opnamelen; 5377 bfd_boolean has_underbar = FALSE; 5378 char *arg_strings[MAX_INSN_ARGS]; 5379 int num_args; 5380 TInsn orig_insn; /* Original instruction from the input. */ 5381 5382 tinsn_init (&orig_insn); 5383 5384 /* Split off the opcode. */ 5385 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); 5386 opname = xmalloc (opnamelen + 1); 5387 memcpy (opname, str, opnamelen); 5388 opname[opnamelen] = '\0'; 5389 5390 num_args = tokenize_arguments (arg_strings, str + opnamelen); 5391 if (num_args == -1) 5392 { 5393 as_bad (_("syntax error")); 5394 return; 5395 } 5396 5397 if (xg_translate_idioms (&opname, &num_args, arg_strings)) 5398 return; 5399 5400 /* Check for an underbar prefix. */ 5401 if (*opname == '_') 5402 { 5403 has_underbar = TRUE; 5404 opname += 1; 5405 } 5406 5407 orig_insn.insn_type = ITYPE_INSN; 5408 orig_insn.ntok = 0; 5409 orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); 5410 orig_insn.opcode = xtensa_opcode_lookup (isa, opname); 5411 5412 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its 5413 extra argument and set the opcode to "CALLXn". */ 5414 if (orig_insn.opcode == XTENSA_UNDEFINED 5415 && strncasecmp (opname, "callx", 5) == 0) 5416 { 5417 unsigned long window_size; 5418 char *suffix; 5419 5420 window_size = strtoul (opname + 5, &suffix, 10); 5421 if (suffix != opname + 5 5422 && (window_size == 0 5423 || window_size == 4 5424 || window_size == 8 5425 || window_size == 12) 5426 && strcasecmp (suffix, ".tls") == 0) 5427 { 5428 switch (window_size) 5429 { 5430 case 0: orig_insn.opcode = xtensa_callx0_opcode; break; 5431 case 4: orig_insn.opcode = xtensa_callx4_opcode; break; 5432 case 8: orig_insn.opcode = xtensa_callx8_opcode; break; 5433 case 12: orig_insn.opcode = xtensa_callx12_opcode; break; 5434 } 5435 5436 if (num_args != 2) 5437 as_bad (_("wrong number of operands for '%s'"), opname); 5438 else 5439 { 5440 bfd_reloc_code_real_type reloc; 5441 char *old_input_line_pointer; 5442 expressionS *tok = &orig_insn.extra_arg; 5443 5444 old_input_line_pointer = input_line_pointer; 5445 input_line_pointer = arg_strings[num_args - 1]; 5446 5447 expression (tok); 5448 if (tok->X_op == O_symbol 5449 && ((reloc = xtensa_elf_suffix (&input_line_pointer, tok)) 5450 == BFD_RELOC_XTENSA_TLS_CALL)) 5451 tok->X_op = map_suffix_reloc_to_operator (reloc); 5452 else 5453 as_bad (_("bad relocation expression for '%s'"), opname); 5454 5455 input_line_pointer = old_input_line_pointer; 5456 num_args -= 1; 5457 } 5458 } 5459 } 5460 5461 /* Special case: Check for "j.l" psuedo op. */ 5462 if (orig_insn.opcode == XTENSA_UNDEFINED 5463 && strncasecmp (opname, "j.l", 3) == 0) 5464 { 5465 if (num_args != 2) 5466 as_bad (_("wrong number of operands for '%s'"), opname); 5467 else 5468 { 5469 char *old_input_line_pointer; 5470 expressionS *tok = &orig_insn.extra_arg; 5471 5472 old_input_line_pointer = input_line_pointer; 5473 input_line_pointer = arg_strings[num_args - 1]; 5474 5475 expression_maybe_register (xtensa_jx_opcode, 0, tok); 5476 input_line_pointer = old_input_line_pointer; 5477 5478 num_args -= 1; 5479 orig_insn.opcode = xtensa_j_opcode; 5480 } 5481 } 5482 5483 if (orig_insn.opcode == XTENSA_UNDEFINED) 5484 { 5485 xtensa_format fmt = xtensa_format_lookup (isa, opname); 5486 if (fmt == XTENSA_UNDEFINED) 5487 { 5488 as_bad (_("unknown opcode or format name '%s'"), opname); 5489 error_reset_cur_vinsn (); 5490 return; 5491 } 5492 if (!cur_vinsn.inside_bundle) 5493 { 5494 as_bad (_("format names only valid inside bundles")); 5495 error_reset_cur_vinsn (); 5496 return; 5497 } 5498 if (cur_vinsn.format != XTENSA_UNDEFINED) 5499 as_warn (_("multiple formats specified for one bundle; using '%s'"), 5500 opname); 5501 cur_vinsn.format = fmt; 5502 free (has_underbar ? opname - 1 : opname); 5503 error_reset_cur_vinsn (); 5504 return; 5505 } 5506 5507 /* Parse the arguments. */ 5508 if (parse_arguments (&orig_insn, num_args, arg_strings)) 5509 { 5510 as_bad (_("syntax error")); 5511 error_reset_cur_vinsn (); 5512 return; 5513 } 5514 5515 /* Free the opcode and argument strings, now that they've been parsed. */ 5516 free (has_underbar ? opname - 1 : opname); 5517 opname = 0; 5518 while (num_args-- > 0) 5519 free (arg_strings[num_args]); 5520 5521 /* Get expressions for invisible operands. */ 5522 if (get_invisible_operands (&orig_insn)) 5523 { 5524 error_reset_cur_vinsn (); 5525 return; 5526 } 5527 5528 /* Check for the right number and type of arguments. */ 5529 if (tinsn_check_arguments (&orig_insn)) 5530 { 5531 error_reset_cur_vinsn (); 5532 return; 5533 } 5534 5535 /* Record the line number for each TInsn, because a FLIX bundle may be 5536 spread across multiple input lines and individual instructions may be 5537 moved around in some cases. */ 5538 orig_insn.loc_directive_seen = dwarf2_loc_directive_seen; 5539 dwarf2_where (&orig_insn.debug_line); 5540 dwarf2_consume_line_info (); 5541 5542 xg_add_branch_and_loop_targets (&orig_insn); 5543 5544 /* Check that immediate value for ENTRY is >= 16. */ 5545 if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) 5546 { 5547 expressionS *exp = &orig_insn.tok[2]; 5548 if (exp->X_op == O_constant && exp->X_add_number < 16) 5549 as_warn (_("entry instruction with stack decrement < 16")); 5550 } 5551 5552 /* Finish it off: 5553 assemble_tokens (opcode, tok, ntok); 5554 expand the tokens from the orig_insn into the 5555 stack of instructions that will not expand 5556 unless required at relaxation time. */ 5557 5558 if (!cur_vinsn.inside_bundle) 5559 emit_single_op (&orig_insn); 5560 else /* We are inside a bundle. */ 5561 { 5562 cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; 5563 cur_vinsn.num_slots++; 5564 if (*input_line_pointer == '}' 5565 || *(input_line_pointer - 1) == '}' 5566 || *(input_line_pointer - 2) == '}') 5567 finish_vinsn (&cur_vinsn); 5568 } 5569 5570 /* We've just emitted a new instruction so clear the list of labels. */ 5571 xtensa_clear_insn_labels (); 5572 } 5573 5574 5575 /* HANDLE_ALIGN hook */ 5576 5577 /* For a .align directive, we mark the previous block with the alignment 5578 information. This will be placed in the object file in the 5579 property section corresponding to this section. */ 5580 5581 void 5582 xtensa_handle_align (fragS *fragP) 5583 { 5584 if (linkrelax 5585 && ! fragP->tc_frag_data.is_literal 5586 && (fragP->fr_type == rs_align 5587 || fragP->fr_type == rs_align_code) 5588 && fragP->fr_address + fragP->fr_fix > 0 5589 && fragP->fr_offset > 0 5590 && now_seg != bss_section) 5591 { 5592 fragP->tc_frag_data.is_align = TRUE; 5593 fragP->tc_frag_data.alignment = fragP->fr_offset; 5594 } 5595 5596 if (fragP->fr_type == rs_align_test) 5597 { 5598 int count; 5599 count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; 5600 if (count != 0) 5601 as_bad_where (fragP->fr_file, fragP->fr_line, 5602 _("unaligned entry instruction")); 5603 } 5604 5605 if (linkrelax && fragP->fr_type == rs_org) 5606 fragP->fr_subtype = RELAX_ORG; 5607 } 5608 5609 5610 /* TC_FRAG_INIT hook */ 5611 5612 void 5613 xtensa_frag_init (fragS *frag) 5614 { 5615 xtensa_set_frag_assembly_state (frag); 5616 } 5617 5618 5619 symbolS * 5620 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 5621 { 5622 return NULL; 5623 } 5624 5625 5626 /* Round up a section size to the appropriate boundary. */ 5627 5628 valueT 5629 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 5630 { 5631 return size; /* Byte alignment is fine. */ 5632 } 5633 5634 5635 long 5636 md_pcrel_from (fixS *fixP) 5637 { 5638 char *insn_p; 5639 static xtensa_insnbuf insnbuf = NULL; 5640 static xtensa_insnbuf slotbuf = NULL; 5641 int opnum; 5642 uint32 opnd_value; 5643 xtensa_opcode opcode; 5644 xtensa_format fmt; 5645 int slot; 5646 xtensa_isa isa = xtensa_default_isa; 5647 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 5648 bfd_boolean alt_reloc; 5649 5650 if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) 5651 return 0; 5652 5653 if (fixP->fx_r_type == BFD_RELOC_32_PCREL) 5654 return addr; 5655 5656 if (!insnbuf) 5657 { 5658 insnbuf = xtensa_insnbuf_alloc (isa); 5659 slotbuf = xtensa_insnbuf_alloc (isa); 5660 } 5661 5662 insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; 5663 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); 5664 fmt = xtensa_format_decode (isa, insnbuf); 5665 5666 if (fmt == XTENSA_UNDEFINED) 5667 as_fatal (_("bad instruction format")); 5668 5669 if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) 5670 as_fatal (_("invalid relocation")); 5671 5672 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 5673 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 5674 5675 /* Check for "alternate" relocations (operand not specified). None 5676 of the current uses for these are really PC-relative. */ 5677 if (alt_reloc || opcode == xtensa_const16_opcode) 5678 { 5679 if (opcode != xtensa_l32r_opcode 5680 && opcode != xtensa_const16_opcode) 5681 as_fatal (_("invalid relocation for '%s' instruction"), 5682 xtensa_opcode_name (isa, opcode)); 5683 return 0; 5684 } 5685 5686 opnum = get_relaxable_immed (opcode); 5687 opnd_value = 0; 5688 if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 5689 || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) 5690 { 5691 as_bad_where (fixP->fx_file, 5692 fixP->fx_line, 5693 _("invalid relocation for operand %d of '%s'"), 5694 opnum, xtensa_opcode_name (isa, opcode)); 5695 return 0; 5696 } 5697 return 0 - opnd_value; 5698 } 5699 5700 5701 /* TC_FORCE_RELOCATION hook */ 5702 5703 int 5704 xtensa_force_relocation (fixS *fix) 5705 { 5706 switch (fix->fx_r_type) 5707 { 5708 case BFD_RELOC_XTENSA_ASM_EXPAND: 5709 case BFD_RELOC_XTENSA_SLOT0_ALT: 5710 case BFD_RELOC_XTENSA_SLOT1_ALT: 5711 case BFD_RELOC_XTENSA_SLOT2_ALT: 5712 case BFD_RELOC_XTENSA_SLOT3_ALT: 5713 case BFD_RELOC_XTENSA_SLOT4_ALT: 5714 case BFD_RELOC_XTENSA_SLOT5_ALT: 5715 case BFD_RELOC_XTENSA_SLOT6_ALT: 5716 case BFD_RELOC_XTENSA_SLOT7_ALT: 5717 case BFD_RELOC_XTENSA_SLOT8_ALT: 5718 case BFD_RELOC_XTENSA_SLOT9_ALT: 5719 case BFD_RELOC_XTENSA_SLOT10_ALT: 5720 case BFD_RELOC_XTENSA_SLOT11_ALT: 5721 case BFD_RELOC_XTENSA_SLOT12_ALT: 5722 case BFD_RELOC_XTENSA_SLOT13_ALT: 5723 case BFD_RELOC_XTENSA_SLOT14_ALT: 5724 return 1; 5725 default: 5726 break; 5727 } 5728 5729 if (linkrelax && fix->fx_addsy 5730 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) 5731 return 1; 5732 5733 return generic_force_reloc (fix); 5734 } 5735 5736 5737 /* TC_VALIDATE_FIX_SUB hook */ 5738 5739 int 5740 xtensa_validate_fix_sub (fixS *fix) 5741 { 5742 segT add_symbol_segment, sub_symbol_segment; 5743 5744 /* The difference of two symbols should be resolved by the assembler when 5745 linkrelax is not set. If the linker may relax the section containing 5746 the symbols, then an Xtensa DIFF relocation must be generated so that 5747 the linker knows to adjust the difference value. */ 5748 if (!linkrelax || fix->fx_addsy == NULL) 5749 return 0; 5750 5751 /* Make sure both symbols are in the same segment, and that segment is 5752 "normal" and relaxable. If the segment is not "normal", then the 5753 fix is not valid. If the segment is not "relaxable", then the fix 5754 should have been handled earlier. */ 5755 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); 5756 if (! SEG_NORMAL (add_symbol_segment) || 5757 ! relaxable_section (add_symbol_segment)) 5758 return 0; 5759 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); 5760 return (sub_symbol_segment == add_symbol_segment); 5761 } 5762 5763 5764 /* NO_PSEUDO_DOT hook */ 5765 5766 /* This function has nothing to do with pseudo dots, but this is the 5767 nearest macro to where the check needs to take place. FIXME: This 5768 seems wrong. */ 5769 5770 bfd_boolean 5771 xtensa_check_inside_bundle (void) 5772 { 5773 if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') 5774 as_bad (_("directives are not valid inside bundles")); 5775 5776 /* This function must always return FALSE because it is called via a 5777 macro that has nothing to do with bundling. */ 5778 return FALSE; 5779 } 5780 5781 5782 /* md_elf_section_change_hook */ 5783 5784 void 5785 xtensa_elf_section_change_hook (void) 5786 { 5787 /* Set up the assembly state. */ 5788 if (!frag_now->tc_frag_data.is_assembly_state_set) 5789 xtensa_set_frag_assembly_state (frag_now); 5790 } 5791 5792 5793 /* tc_fix_adjustable hook */ 5794 5795 bfd_boolean 5796 xtensa_fix_adjustable (fixS *fixP) 5797 { 5798 /* We need the symbol name for the VTABLE entries. */ 5799 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 5800 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 5801 return 0; 5802 5803 return 1; 5804 } 5805 5806 5807 /* tc_symbol_new_hook */ 5808 5809 symbolS *expr_symbols = NULL; 5810 5811 void 5812 xtensa_symbol_new_hook (symbolS *sym) 5813 { 5814 if (is_leb128_expr && S_GET_SEGMENT (sym) == expr_section) 5815 { 5816 symbol_get_tc (sym)->next_expr_symbol = expr_symbols; 5817 expr_symbols = sym; 5818 } 5819 } 5820 5821 5822 void 5823 md_apply_fix (fixS *fixP, valueT *valP, segT seg) 5824 { 5825 char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; 5826 valueT val = 0; 5827 5828 /* Subtracted symbols are only allowed for a few relocation types, and 5829 unless linkrelax is enabled, they should not make it to this point. */ 5830 if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 5831 || fixP->fx_r_type == BFD_RELOC_16 5832 || fixP->fx_r_type == BFD_RELOC_8))) 5833 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); 5834 5835 switch (fixP->fx_r_type) 5836 { 5837 case BFD_RELOC_32_PCREL: 5838 case BFD_RELOC_32: 5839 case BFD_RELOC_16: 5840 case BFD_RELOC_8: 5841 if (fixP->fx_subsy) 5842 { 5843 switch (fixP->fx_r_type) 5844 { 5845 case BFD_RELOC_8: 5846 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; 5847 break; 5848 case BFD_RELOC_16: 5849 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; 5850 break; 5851 case BFD_RELOC_32: 5852 fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; 5853 break; 5854 default: 5855 break; 5856 } 5857 5858 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 5859 - S_GET_VALUE (fixP->fx_subsy)); 5860 5861 /* The difference value gets written out, and the DIFF reloc 5862 identifies the address of the subtracted symbol (i.e., the one 5863 with the lowest address). */ 5864 *valP = val; 5865 fixP->fx_offset -= val; 5866 fixP->fx_subsy = NULL; 5867 } 5868 else if (! fixP->fx_addsy) 5869 { 5870 val = *valP; 5871 fixP->fx_done = 1; 5872 } 5873 /* fall through */ 5874 5875 case BFD_RELOC_XTENSA_PLT: 5876 md_number_to_chars (fixpos, val, fixP->fx_size); 5877 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ 5878 break; 5879 5880 case BFD_RELOC_XTENSA_TLSDESC_FN: 5881 case BFD_RELOC_XTENSA_TLSDESC_ARG: 5882 case BFD_RELOC_XTENSA_TLS_TPOFF: 5883 case BFD_RELOC_XTENSA_TLS_DTPOFF: 5884 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5885 md_number_to_chars (fixpos, 0, fixP->fx_size); 5886 fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ 5887 break; 5888 5889 case BFD_RELOC_XTENSA_SLOT0_OP: 5890 case BFD_RELOC_XTENSA_SLOT1_OP: 5891 case BFD_RELOC_XTENSA_SLOT2_OP: 5892 case BFD_RELOC_XTENSA_SLOT3_OP: 5893 case BFD_RELOC_XTENSA_SLOT4_OP: 5894 case BFD_RELOC_XTENSA_SLOT5_OP: 5895 case BFD_RELOC_XTENSA_SLOT6_OP: 5896 case BFD_RELOC_XTENSA_SLOT7_OP: 5897 case BFD_RELOC_XTENSA_SLOT8_OP: 5898 case BFD_RELOC_XTENSA_SLOT9_OP: 5899 case BFD_RELOC_XTENSA_SLOT10_OP: 5900 case BFD_RELOC_XTENSA_SLOT11_OP: 5901 case BFD_RELOC_XTENSA_SLOT12_OP: 5902 case BFD_RELOC_XTENSA_SLOT13_OP: 5903 case BFD_RELOC_XTENSA_SLOT14_OP: 5904 if (linkrelax) 5905 { 5906 /* Write the tentative value of a PC-relative relocation to a 5907 local symbol into the instruction. The value will be ignored 5908 by the linker, and it makes the object file disassembly 5909 readable when all branch targets are encoded in relocations. */ 5910 5911 gas_assert (fixP->fx_addsy); 5912 if (S_GET_SEGMENT (fixP->fx_addsy) == seg 5913 && !S_FORCE_RELOC (fixP->fx_addsy, 1)) 5914 { 5915 val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset 5916 - md_pcrel_from (fixP)); 5917 (void) xg_apply_fix_value (fixP, val); 5918 } 5919 } 5920 else if (! fixP->fx_addsy) 5921 { 5922 val = *valP; 5923 if (xg_apply_fix_value (fixP, val)) 5924 fixP->fx_done = 1; 5925 } 5926 break; 5927 5928 case BFD_RELOC_XTENSA_ASM_EXPAND: 5929 case BFD_RELOC_XTENSA_TLS_FUNC: 5930 case BFD_RELOC_XTENSA_TLS_ARG: 5931 case BFD_RELOC_XTENSA_TLS_CALL: 5932 case BFD_RELOC_XTENSA_SLOT0_ALT: 5933 case BFD_RELOC_XTENSA_SLOT1_ALT: 5934 case BFD_RELOC_XTENSA_SLOT2_ALT: 5935 case BFD_RELOC_XTENSA_SLOT3_ALT: 5936 case BFD_RELOC_XTENSA_SLOT4_ALT: 5937 case BFD_RELOC_XTENSA_SLOT5_ALT: 5938 case BFD_RELOC_XTENSA_SLOT6_ALT: 5939 case BFD_RELOC_XTENSA_SLOT7_ALT: 5940 case BFD_RELOC_XTENSA_SLOT8_ALT: 5941 case BFD_RELOC_XTENSA_SLOT9_ALT: 5942 case BFD_RELOC_XTENSA_SLOT10_ALT: 5943 case BFD_RELOC_XTENSA_SLOT11_ALT: 5944 case BFD_RELOC_XTENSA_SLOT12_ALT: 5945 case BFD_RELOC_XTENSA_SLOT13_ALT: 5946 case BFD_RELOC_XTENSA_SLOT14_ALT: 5947 /* These all need to be resolved at link-time. Do nothing now. */ 5948 break; 5949 5950 case BFD_RELOC_VTABLE_INHERIT: 5951 case BFD_RELOC_VTABLE_ENTRY: 5952 fixP->fx_done = 0; 5953 break; 5954 5955 default: 5956 as_bad (_("unhandled local relocation fix %s"), 5957 bfd_get_reloc_code_name (fixP->fx_r_type)); 5958 } 5959 } 5960 5961 5962 char * 5963 md_atof (int type, char *litP, int *sizeP) 5964 { 5965 return ieee_md_atof (type, litP, sizeP, target_big_endian); 5966 } 5967 5968 5969 int 5970 md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) 5971 { 5972 return total_frag_text_expansion (fragP); 5973 } 5974 5975 5976 /* Translate internal representation of relocation info to BFD target 5977 format. */ 5978 5979 arelent * 5980 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 5981 { 5982 arelent *reloc; 5983 5984 reloc = (arelent *) xmalloc (sizeof (arelent)); 5985 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 5986 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 5987 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 5988 5989 /* Make sure none of our internal relocations make it this far. 5990 They'd better have been fully resolved by this point. */ 5991 gas_assert ((int) fixp->fx_r_type > 0); 5992 5993 reloc->addend = fixp->fx_offset; 5994 5995 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 5996 if (reloc->howto == NULL) 5997 { 5998 as_bad_where (fixp->fx_file, fixp->fx_line, 5999 _("cannot represent `%s' relocation in object file"), 6000 bfd_get_reloc_code_name (fixp->fx_r_type)); 6001 free (reloc->sym_ptr_ptr); 6002 free (reloc); 6003 return NULL; 6004 } 6005 6006 if (!fixp->fx_pcrel != !reloc->howto->pc_relative) 6007 as_fatal (_("internal error; cannot generate `%s' relocation"), 6008 bfd_get_reloc_code_name (fixp->fx_r_type)); 6009 6010 return reloc; 6011 } 6012 6013 6014 /* Checks for resource conflicts between instructions. */ 6015 6016 /* The func unit stuff could be implemented as bit-vectors rather 6017 than the iterative approach here. If it ends up being too 6018 slow, we will switch it. */ 6019 6020 resource_table * 6021 new_resource_table (void *data, 6022 int cycles, 6023 int nu, 6024 unit_num_copies_func uncf, 6025 opcode_num_units_func onuf, 6026 opcode_funcUnit_use_unit_func ouuf, 6027 opcode_funcUnit_use_stage_func ousf) 6028 { 6029 int i; 6030 resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); 6031 rt->data = data; 6032 rt->cycles = cycles; 6033 rt->allocated_cycles = cycles; 6034 rt->num_units = nu; 6035 rt->unit_num_copies = uncf; 6036 rt->opcode_num_units = onuf; 6037 rt->opcode_unit_use = ouuf; 6038 rt->opcode_unit_stage = ousf; 6039 6040 rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); 6041 for (i = 0; i < cycles; i++) 6042 rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); 6043 6044 return rt; 6045 } 6046 6047 6048 void 6049 clear_resource_table (resource_table *rt) 6050 { 6051 int i, j; 6052 for (i = 0; i < rt->allocated_cycles; i++) 6053 for (j = 0; j < rt->num_units; j++) 6054 rt->units[i][j] = 0; 6055 } 6056 6057 6058 /* We never shrink it, just fake it into thinking so. */ 6059 6060 void 6061 resize_resource_table (resource_table *rt, int cycles) 6062 { 6063 int i, old_cycles; 6064 6065 rt->cycles = cycles; 6066 if (cycles <= rt->allocated_cycles) 6067 return; 6068 6069 old_cycles = rt->allocated_cycles; 6070 rt->allocated_cycles = cycles; 6071 6072 rt->units = xrealloc (rt->units, 6073 rt->allocated_cycles * sizeof (unsigned char *)); 6074 for (i = 0; i < old_cycles; i++) 6075 rt->units[i] = xrealloc (rt->units[i], 6076 rt->num_units * sizeof (unsigned char)); 6077 for (i = old_cycles; i < cycles; i++) 6078 rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); 6079 } 6080 6081 6082 bfd_boolean 6083 resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) 6084 { 6085 int i; 6086 int uses = (rt->opcode_num_units) (rt->data, opcode); 6087 6088 for (i = 0; i < uses; i++) 6089 { 6090 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6091 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6092 int copies_in_use = rt->units[stage + cycle][unit]; 6093 int copies = (rt->unit_num_copies) (rt->data, unit); 6094 if (copies_in_use >= copies) 6095 return FALSE; 6096 } 6097 return TRUE; 6098 } 6099 6100 6101 void 6102 reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 6103 { 6104 int i; 6105 int uses = (rt->opcode_num_units) (rt->data, opcode); 6106 6107 for (i = 0; i < uses; i++) 6108 { 6109 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6110 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6111 /* Note that this allows resources to be oversubscribed. That's 6112 essential to the way the optional scheduler works. 6113 resources_available reports when a resource is over-subscribed, 6114 so it's easy to tell. */ 6115 rt->units[stage + cycle][unit]++; 6116 } 6117 } 6118 6119 6120 void 6121 release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) 6122 { 6123 int i; 6124 int uses = (rt->opcode_num_units) (rt->data, opcode); 6125 6126 for (i = 0; i < uses; i++) 6127 { 6128 xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); 6129 int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); 6130 gas_assert (rt->units[stage + cycle][unit] > 0); 6131 rt->units[stage + cycle][unit]--; 6132 } 6133 } 6134 6135 6136 /* Wrapper functions make parameterized resource reservation 6137 more convenient. */ 6138 6139 int 6140 opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) 6141 { 6142 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 6143 return use->unit; 6144 } 6145 6146 6147 int 6148 opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) 6149 { 6150 xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); 6151 return use->stage; 6152 } 6153 6154 6155 /* Note that this function does not check issue constraints, but 6156 solely whether the hardware is available to execute the given 6157 instructions together. It also doesn't check if the tinsns 6158 write the same state, or access the same tieports. That is 6159 checked by check_t1_t2_reads_and_writes. */ 6160 6161 static bfd_boolean 6162 resources_conflict (vliw_insn *vinsn) 6163 { 6164 int i; 6165 static resource_table *rt = NULL; 6166 6167 /* This is the most common case by far. Optimize it. */ 6168 if (vinsn->num_slots == 1) 6169 return FALSE; 6170 6171 if (rt == NULL) 6172 { 6173 xtensa_isa isa = xtensa_default_isa; 6174 rt = new_resource_table 6175 (isa, xtensa_num_pipe_stages, 6176 xtensa_isa_num_funcUnits (isa), 6177 (unit_num_copies_func) xtensa_funcUnit_num_copies, 6178 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, 6179 opcode_funcUnit_use_unit, 6180 opcode_funcUnit_use_stage); 6181 } 6182 6183 clear_resource_table (rt); 6184 6185 for (i = 0; i < vinsn->num_slots; i++) 6186 { 6187 if (!resources_available (rt, vinsn->slots[i].opcode, 0)) 6188 return TRUE; 6189 reserve_resources (rt, vinsn->slots[i].opcode, 0); 6190 } 6191 6192 return FALSE; 6193 } 6194 6195 6196 /* finish_vinsn, emit_single_op and helper functions. */ 6197 6198 static bfd_boolean find_vinsn_conflicts (vliw_insn *); 6199 static xtensa_format xg_find_narrowest_format (vliw_insn *); 6200 static void xg_assemble_vliw_tokens (vliw_insn *); 6201 6202 6203 /* We have reached the end of a bundle; emit into the frag. */ 6204 6205 static void 6206 finish_vinsn (vliw_insn *vinsn) 6207 { 6208 IStack slotstack; 6209 int i; 6210 char *file_name; 6211 unsigned line; 6212 6213 if (find_vinsn_conflicts (vinsn)) 6214 { 6215 xg_clear_vinsn (vinsn); 6216 return; 6217 } 6218 6219 /* First, find a format that works. */ 6220 if (vinsn->format == XTENSA_UNDEFINED) 6221 vinsn->format = xg_find_narrowest_format (vinsn); 6222 6223 if (xtensa_format_num_slots (xtensa_default_isa, vinsn->format) > 1 6224 && produce_flix == FLIX_NONE) 6225 { 6226 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix.")); 6227 xg_clear_vinsn (vinsn); 6228 return; 6229 } 6230 6231 if (vinsn->format == XTENSA_UNDEFINED) 6232 { 6233 as_where (&file_name, &line); 6234 as_bad_where (file_name, line, 6235 _("couldn't find a valid instruction format")); 6236 fprintf (stderr, _(" ops were: ")); 6237 for (i = 0; i < vinsn->num_slots; i++) 6238 fprintf (stderr, _(" %s;"), 6239 xtensa_opcode_name (xtensa_default_isa, 6240 vinsn->slots[i].opcode)); 6241 fprintf (stderr, _("\n")); 6242 xg_clear_vinsn (vinsn); 6243 return; 6244 } 6245 6246 if (vinsn->num_slots 6247 != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) 6248 { 6249 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), 6250 xtensa_format_name (xtensa_default_isa, vinsn->format), 6251 xtensa_format_num_slots (xtensa_default_isa, vinsn->format), 6252 vinsn->num_slots); 6253 xg_clear_vinsn (vinsn); 6254 return; 6255 } 6256 6257 if (resources_conflict (vinsn)) 6258 { 6259 as_where (&file_name, &line); 6260 as_bad_where (file_name, line, _("illegal resource usage in bundle")); 6261 fprintf (stderr, " ops were: "); 6262 for (i = 0; i < vinsn->num_slots; i++) 6263 fprintf (stderr, " %s;", 6264 xtensa_opcode_name (xtensa_default_isa, 6265 vinsn->slots[i].opcode)); 6266 fprintf (stderr, "\n"); 6267 xg_clear_vinsn (vinsn); 6268 return; 6269 } 6270 6271 for (i = 0; i < vinsn->num_slots; i++) 6272 { 6273 if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) 6274 { 6275 symbolS *lit_sym = NULL; 6276 int j; 6277 bfd_boolean e = FALSE; 6278 bfd_boolean saved_density = density_supported; 6279 6280 /* We don't want to narrow ops inside multi-slot bundles. */ 6281 if (vinsn->num_slots > 1) 6282 density_supported = FALSE; 6283 6284 istack_init (&slotstack); 6285 if (vinsn->slots[i].opcode == xtensa_nop_opcode) 6286 { 6287 vinsn->slots[i].opcode = 6288 xtensa_format_slot_nop_opcode (xtensa_default_isa, 6289 vinsn->format, i); 6290 vinsn->slots[i].ntok = 0; 6291 } 6292 6293 if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) 6294 { 6295 e = TRUE; 6296 continue; 6297 } 6298 6299 density_supported = saved_density; 6300 6301 if (e) 6302 { 6303 xg_clear_vinsn (vinsn); 6304 return; 6305 } 6306 6307 for (j = 0; j < slotstack.ninsn; j++) 6308 { 6309 TInsn *insn = &slotstack.insn[j]; 6310 if (insn->insn_type == ITYPE_LITERAL) 6311 { 6312 gas_assert (lit_sym == NULL); 6313 lit_sym = xg_assemble_literal (insn); 6314 } 6315 else 6316 { 6317 gas_assert (insn->insn_type == ITYPE_INSN); 6318 if (lit_sym) 6319 xg_resolve_literals (insn, lit_sym); 6320 if (j != slotstack.ninsn - 1) 6321 emit_single_op (insn); 6322 } 6323 } 6324 6325 if (vinsn->num_slots > 1) 6326 { 6327 if (opcode_fits_format_slot 6328 (slotstack.insn[slotstack.ninsn - 1].opcode, 6329 vinsn->format, i)) 6330 { 6331 vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; 6332 } 6333 else 6334 { 6335 emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); 6336 if (vinsn->format == XTENSA_UNDEFINED) 6337 vinsn->slots[i].opcode = xtensa_nop_opcode; 6338 else 6339 vinsn->slots[i].opcode 6340 = xtensa_format_slot_nop_opcode (xtensa_default_isa, 6341 vinsn->format, i); 6342 6343 vinsn->slots[i].ntok = 0; 6344 } 6345 } 6346 else 6347 { 6348 vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; 6349 vinsn->format = XTENSA_UNDEFINED; 6350 } 6351 } 6352 } 6353 6354 /* Now check resource conflicts on the modified bundle. */ 6355 if (resources_conflict (vinsn)) 6356 { 6357 as_where (&file_name, &line); 6358 as_bad_where (file_name, line, _("illegal resource usage in bundle")); 6359 fprintf (stderr, " ops were: "); 6360 for (i = 0; i < vinsn->num_slots; i++) 6361 fprintf (stderr, " %s;", 6362 xtensa_opcode_name (xtensa_default_isa, 6363 vinsn->slots[i].opcode)); 6364 fprintf (stderr, "\n"); 6365 xg_clear_vinsn (vinsn); 6366 return; 6367 } 6368 6369 /* First, find a format that works. */ 6370 if (vinsn->format == XTENSA_UNDEFINED) 6371 vinsn->format = xg_find_narrowest_format (vinsn); 6372 6373 xg_assemble_vliw_tokens (vinsn); 6374 6375 xg_clear_vinsn (vinsn); 6376 } 6377 6378 6379 /* Given an vliw instruction, what conflicts are there in register 6380 usage and in writes to states and queues? 6381 6382 This function does two things: 6383 1. Reports an error when a vinsn contains illegal combinations 6384 of writes to registers states or queues. 6385 2. Marks individual tinsns as not relaxable if the combination 6386 contains antidependencies. 6387 6388 Job 2 handles things like swap semantics in instructions that need 6389 to be relaxed. For example, 6390 6391 addi a0, a1, 100000 6392 6393 normally would be relaxed to 6394 6395 l32r a0, some_label 6396 add a0, a1, a0 6397 6398 _but_, if the above instruction is bundled with an a0 reader, e.g., 6399 6400 { addi a0, a1, 10000 ; add a2, a0, a4 ; } 6401 6402 then we can't relax it into 6403 6404 l32r a0, some_label 6405 { add a0, a1, a0 ; add a2, a0, a4 ; } 6406 6407 because the value of a0 is trashed before the second add can read it. */ 6408 6409 static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); 6410 6411 static bfd_boolean 6412 find_vinsn_conflicts (vliw_insn *vinsn) 6413 { 6414 int i, j; 6415 int branches = 0; 6416 xtensa_isa isa = xtensa_default_isa; 6417 6418 gas_assert (!past_xtensa_end); 6419 6420 for (i = 0 ; i < vinsn->num_slots; i++) 6421 { 6422 TInsn *op1 = &vinsn->slots[i]; 6423 if (op1->is_specific_opcode) 6424 op1->keep_wide = TRUE; 6425 else 6426 op1->keep_wide = FALSE; 6427 } 6428 6429 for (i = 0 ; i < vinsn->num_slots; i++) 6430 { 6431 TInsn *op1 = &vinsn->slots[i]; 6432 6433 if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) 6434 branches++; 6435 6436 for (j = 0; j < vinsn->num_slots; j++) 6437 { 6438 if (i != j) 6439 { 6440 TInsn *op2 = &vinsn->slots[j]; 6441 char conflict_type = check_t1_t2_reads_and_writes (op1, op2); 6442 switch (conflict_type) 6443 { 6444 case 'c': 6445 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), 6446 xtensa_opcode_name (isa, op1->opcode), i, 6447 xtensa_opcode_name (isa, op2->opcode), j); 6448 return TRUE; 6449 case 'd': 6450 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), 6451 xtensa_opcode_name (isa, op1->opcode), i, 6452 xtensa_opcode_name (isa, op2->opcode), j); 6453 return TRUE; 6454 case 'e': 6455 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), 6456 xtensa_opcode_name (isa, op1->opcode), i, 6457 xtensa_opcode_name (isa, op2->opcode), j); 6458 return TRUE; 6459 case 'f': 6460 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), 6461 xtensa_opcode_name (isa, op1->opcode), i, 6462 xtensa_opcode_name (isa, op2->opcode), j); 6463 return TRUE; 6464 default: 6465 /* Everything is OK. */ 6466 break; 6467 } 6468 op2->is_specific_opcode = (op2->is_specific_opcode 6469 || conflict_type == 'a'); 6470 } 6471 } 6472 } 6473 6474 if (branches > 1) 6475 { 6476 as_bad (_("multiple branches or jumps in the same bundle")); 6477 return TRUE; 6478 } 6479 6480 return FALSE; 6481 } 6482 6483 6484 /* Check how the state used by t1 and t2 relate. 6485 Cases found are: 6486 6487 case A: t1 reads a register t2 writes (an antidependency within a bundle) 6488 case B: no relationship between what is read and written (both could 6489 read the same reg though) 6490 case C: t1 writes a register t2 writes (a register conflict within a 6491 bundle) 6492 case D: t1 writes a state that t2 also writes 6493 case E: t1 writes a tie queue that t2 also writes 6494 case F: two volatile queue accesses 6495 */ 6496 6497 static char 6498 check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) 6499 { 6500 xtensa_isa isa = xtensa_default_isa; 6501 xtensa_regfile t1_regfile, t2_regfile; 6502 int t1_reg, t2_reg; 6503 int t1_base_reg, t1_last_reg; 6504 int t2_base_reg, t2_last_reg; 6505 char t1_inout, t2_inout; 6506 int i, j; 6507 char conflict = 'b'; 6508 int t1_states; 6509 int t2_states; 6510 int t1_interfaces; 6511 int t2_interfaces; 6512 bfd_boolean t1_volatile = FALSE; 6513 bfd_boolean t2_volatile = FALSE; 6514 6515 /* Check registers. */ 6516 for (j = 0; j < t2->ntok; j++) 6517 { 6518 if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) 6519 continue; 6520 6521 t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); 6522 t2_base_reg = t2->tok[j].X_add_number; 6523 t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); 6524 6525 for (i = 0; i < t1->ntok; i++) 6526 { 6527 if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) 6528 continue; 6529 6530 t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); 6531 6532 if (t1_regfile != t2_regfile) 6533 continue; 6534 6535 t1_inout = xtensa_operand_inout (isa, t1->opcode, i); 6536 t2_inout = xtensa_operand_inout (isa, t2->opcode, j); 6537 6538 if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 6539 || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) 6540 { 6541 if (t1_inout == 'm' || t1_inout == 'o' 6542 || t2_inout == 'm' || t2_inout == 'o') 6543 { 6544 conflict = 'a'; 6545 continue; 6546 } 6547 } 6548 6549 t1_base_reg = t1->tok[i].X_add_number; 6550 t1_last_reg = (t1_base_reg 6551 + xtensa_operand_num_regs (isa, t1->opcode, i)); 6552 6553 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) 6554 { 6555 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) 6556 { 6557 if (t1_reg != t2_reg) 6558 continue; 6559 6560 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6561 { 6562 conflict = 'a'; 6563 continue; 6564 } 6565 6566 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6567 { 6568 conflict = 'a'; 6569 continue; 6570 } 6571 6572 if (t1_inout != 'i' && t2_inout != 'i') 6573 return 'c'; 6574 } 6575 } 6576 } 6577 } 6578 6579 /* Check states. */ 6580 t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); 6581 t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); 6582 for (j = 0; j < t2_states; j++) 6583 { 6584 xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); 6585 t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); 6586 for (i = 0; i < t1_states; i++) 6587 { 6588 xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); 6589 t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); 6590 if (t1_so != t2_so || xtensa_state_is_shared_or (isa, t1_so) == 1) 6591 continue; 6592 6593 if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) 6594 { 6595 conflict = 'a'; 6596 continue; 6597 } 6598 6599 if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) 6600 { 6601 conflict = 'a'; 6602 continue; 6603 } 6604 6605 if (t1_inout != 'i' && t2_inout != 'i') 6606 return 'd'; 6607 } 6608 } 6609 6610 /* Check tieports. */ 6611 t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); 6612 t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); 6613 for (j = 0; j < t2_interfaces; j++) 6614 { 6615 xtensa_interface t2_int 6616 = xtensa_interfaceOperand_interface (isa, t2->opcode, j); 6617 int t2_class = xtensa_interface_class_id (isa, t2_int); 6618 6619 t2_inout = xtensa_interface_inout (isa, t2_int); 6620 if (xtensa_interface_has_side_effect (isa, t2_int) == 1) 6621 t2_volatile = TRUE; 6622 6623 for (i = 0; i < t1_interfaces; i++) 6624 { 6625 xtensa_interface t1_int 6626 = xtensa_interfaceOperand_interface (isa, t1->opcode, j); 6627 int t1_class = xtensa_interface_class_id (isa, t1_int); 6628 6629 t1_inout = xtensa_interface_inout (isa, t1_int); 6630 if (xtensa_interface_has_side_effect (isa, t1_int) == 1) 6631 t1_volatile = TRUE; 6632 6633 if (t1_volatile && t2_volatile && (t1_class == t2_class)) 6634 return 'f'; 6635 6636 if (t1_int != t2_int) 6637 continue; 6638 6639 if (t2_inout == 'i' && t1_inout == 'o') 6640 { 6641 conflict = 'a'; 6642 continue; 6643 } 6644 6645 if (t1_inout == 'i' && t2_inout == 'o') 6646 { 6647 conflict = 'a'; 6648 continue; 6649 } 6650 6651 if (t1_inout != 'i' && t2_inout != 'i') 6652 return 'e'; 6653 } 6654 } 6655 6656 return conflict; 6657 } 6658 6659 6660 static xtensa_format 6661 xg_find_narrowest_format (vliw_insn *vinsn) 6662 { 6663 /* Right now we assume that the ops within the vinsn are properly 6664 ordered for the slots that the programmer wanted them in. In 6665 other words, we don't rearrange the ops in hopes of finding a 6666 better format. The scheduler handles that. */ 6667 6668 xtensa_isa isa = xtensa_default_isa; 6669 xtensa_format format; 6670 xtensa_opcode nop_opcode = xtensa_nop_opcode; 6671 6672 if (vinsn->num_slots == 1) 6673 return xg_get_single_format (vinsn->slots[0].opcode); 6674 6675 for (format = 0; format < xtensa_isa_num_formats (isa); format++) 6676 { 6677 vliw_insn v_copy; 6678 xg_copy_vinsn (&v_copy, vinsn); 6679 if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) 6680 { 6681 int slot; 6682 int fit = 0; 6683 for (slot = 0; slot < v_copy.num_slots; slot++) 6684 { 6685 if (v_copy.slots[slot].opcode == nop_opcode) 6686 { 6687 v_copy.slots[slot].opcode = 6688 xtensa_format_slot_nop_opcode (isa, format, slot); 6689 v_copy.slots[slot].ntok = 0; 6690 } 6691 6692 if (opcode_fits_format_slot (v_copy.slots[slot].opcode, 6693 format, slot)) 6694 fit++; 6695 else if (v_copy.num_slots > 1) 6696 { 6697 TInsn widened; 6698 /* Try the widened version. */ 6699 if (!v_copy.slots[slot].keep_wide 6700 && !v_copy.slots[slot].is_specific_opcode 6701 && xg_is_single_relaxable_insn (&v_copy.slots[slot], 6702 &widened, TRUE) 6703 && opcode_fits_format_slot (widened.opcode, 6704 format, slot)) 6705 { 6706 v_copy.slots[slot] = widened; 6707 fit++; 6708 } 6709 } 6710 } 6711 if (fit == v_copy.num_slots) 6712 { 6713 xg_copy_vinsn (vinsn, &v_copy); 6714 xtensa_format_encode (isa, format, vinsn->insnbuf); 6715 vinsn->format = format; 6716 break; 6717 } 6718 } 6719 } 6720 6721 if (format == xtensa_isa_num_formats (isa)) 6722 return XTENSA_UNDEFINED; 6723 6724 return format; 6725 } 6726 6727 6728 /* Return the additional space needed in a frag 6729 for possible relaxations of any ops in a VLIW insn. 6730 Also fill out the relaxations that might be required of 6731 each tinsn in the vinsn. */ 6732 6733 static int 6734 relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) 6735 { 6736 bfd_boolean finish_frag = FALSE; 6737 int extra_space = 0; 6738 int slot; 6739 6740 for (slot = 0; slot < vinsn->num_slots; slot++) 6741 { 6742 TInsn *tinsn = &vinsn->slots[slot]; 6743 if (!tinsn_has_symbolic_operands (tinsn)) 6744 { 6745 /* A narrow instruction could be widened later to help 6746 alignment issues. */ 6747 if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) 6748 && !tinsn->is_specific_opcode 6749 && vinsn->num_slots == 1) 6750 { 6751 /* Difference in bytes between narrow and wide insns... */ 6752 extra_space += 1; 6753 tinsn->subtype = RELAX_NARROW; 6754 } 6755 } 6756 else 6757 { 6758 if (workaround_b_j_loop_end 6759 && tinsn->opcode == xtensa_jx_opcode 6760 && use_transform ()) 6761 { 6762 /* Add 2 of these. */ 6763 extra_space += 3; /* for the nop size */ 6764 tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; 6765 } 6766 6767 /* Need to assemble it with space for the relocation. */ 6768 if (xg_is_relaxable_insn (tinsn, 0) 6769 && !tinsn->is_specific_opcode) 6770 { 6771 int max_size = xg_get_max_insn_widen_size (tinsn->opcode); 6772 int max_literal_size = 6773 xg_get_max_insn_widen_literal_size (tinsn->opcode); 6774 6775 tinsn->literal_space = max_literal_size; 6776 6777 tinsn->subtype = RELAX_IMMED; 6778 extra_space += max_size; 6779 } 6780 else 6781 { 6782 /* A fix record will be added for this instruction prior 6783 to relaxation, so make it end the frag. */ 6784 finish_frag = TRUE; 6785 } 6786 } 6787 } 6788 *pfinish_frag = finish_frag; 6789 return extra_space; 6790 } 6791 6792 6793 static void 6794 bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) 6795 { 6796 xtensa_isa isa = xtensa_default_isa; 6797 int slot, chosen_slot; 6798 6799 vinsn->format = xg_get_single_format (tinsn->opcode); 6800 gas_assert (vinsn->format != XTENSA_UNDEFINED); 6801 vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); 6802 6803 chosen_slot = xg_get_single_slot (tinsn->opcode); 6804 for (slot = 0; slot < vinsn->num_slots; slot++) 6805 { 6806 if (slot == chosen_slot) 6807 vinsn->slots[slot] = *tinsn; 6808 else 6809 { 6810 vinsn->slots[slot].opcode = 6811 xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); 6812 vinsn->slots[slot].ntok = 0; 6813 vinsn->slots[slot].insn_type = ITYPE_INSN; 6814 } 6815 } 6816 } 6817 6818 6819 static bfd_boolean 6820 emit_single_op (TInsn *orig_insn) 6821 { 6822 int i; 6823 IStack istack; /* put instructions into here */ 6824 symbolS *lit_sym = NULL; 6825 symbolS *label_sym = NULL; 6826 6827 istack_init (&istack); 6828 6829 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. 6830 Because the scheduling and bundling characteristics of movi and 6831 l32r or const16 are so different, we can do much better if we relax 6832 it prior to scheduling and bundling, rather than after. */ 6833 if ((orig_insn->opcode == xtensa_movi_opcode 6834 || orig_insn->opcode == xtensa_movi_n_opcode) 6835 && !cur_vinsn.inside_bundle 6836 && (orig_insn->tok[1].X_op == O_symbol 6837 || orig_insn->tok[1].X_op == O_pltrel 6838 || orig_insn->tok[1].X_op == O_tlsfunc 6839 || orig_insn->tok[1].X_op == O_tlsarg 6840 || orig_insn->tok[1].X_op == O_tpoff 6841 || orig_insn->tok[1].X_op == O_dtpoff) 6842 && !orig_insn->is_specific_opcode && use_transform ()) 6843 xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); 6844 else 6845 if (xg_expand_assembly_insn (&istack, orig_insn)) 6846 return TRUE; 6847 6848 for (i = 0; i < istack.ninsn; i++) 6849 { 6850 TInsn *insn = &istack.insn[i]; 6851 switch (insn->insn_type) 6852 { 6853 case ITYPE_LITERAL: 6854 gas_assert (lit_sym == NULL); 6855 lit_sym = xg_assemble_literal (insn); 6856 break; 6857 case ITYPE_LABEL: 6858 { 6859 static int relaxed_sym_idx = 0; 6860 char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); 6861 sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); 6862 colon (label); 6863 gas_assert (label_sym == NULL); 6864 label_sym = symbol_find_or_make (label); 6865 gas_assert (label_sym); 6866 free (label); 6867 } 6868 break; 6869 case ITYPE_INSN: 6870 { 6871 vliw_insn v; 6872 if (lit_sym) 6873 xg_resolve_literals (insn, lit_sym); 6874 if (label_sym) 6875 xg_resolve_labels (insn, label_sym); 6876 xg_init_vinsn (&v); 6877 bundle_tinsn (insn, &v); 6878 finish_vinsn (&v); 6879 xg_free_vinsn (&v); 6880 } 6881 break; 6882 default: 6883 gas_assert (0); 6884 break; 6885 } 6886 } 6887 return FALSE; 6888 } 6889 6890 6891 static int 6892 total_frag_text_expansion (fragS *fragP) 6893 { 6894 int slot; 6895 int total_expansion = 0; 6896 6897 for (slot = 0; slot < config_max_slots; slot++) 6898 total_expansion += fragP->tc_frag_data.text_expansion[slot]; 6899 6900 return total_expansion; 6901 } 6902 6903 6904 /* Emit a vliw instruction to the current fragment. */ 6905 6906 static void 6907 xg_assemble_vliw_tokens (vliw_insn *vinsn) 6908 { 6909 bfd_boolean finish_frag; 6910 bfd_boolean is_jump = FALSE; 6911 bfd_boolean is_branch = FALSE; 6912 xtensa_isa isa = xtensa_default_isa; 6913 int insn_size; 6914 int extra_space; 6915 char *f = NULL; 6916 int slot; 6917 struct dwarf2_line_info debug_line; 6918 bfd_boolean loc_directive_seen = FALSE; 6919 TInsn *tinsn; 6920 6921 memset (&debug_line, 0, sizeof (struct dwarf2_line_info)); 6922 6923 if (generating_literals) 6924 { 6925 static int reported = 0; 6926 if (reported < 4) 6927 as_bad_where (frag_now->fr_file, frag_now->fr_line, 6928 _("cannot assemble into a literal fragment")); 6929 if (reported == 3) 6930 as_bad (_("...")); 6931 reported++; 6932 return; 6933 } 6934 6935 if (frag_now_fix () != 0 6936 && (! frag_now->tc_frag_data.is_insn 6937 || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 6938 || !use_transform () != frag_now->tc_frag_data.is_no_transform 6939 || (directive_state[directive_longcalls] 6940 != frag_now->tc_frag_data.use_longcalls) 6941 || (directive_state[directive_absolute_literals] 6942 != frag_now->tc_frag_data.use_absolute_literals))) 6943 { 6944 frag_wane (frag_now); 6945 frag_new (0); 6946 xtensa_set_frag_assembly_state (frag_now); 6947 } 6948 6949 if (workaround_a0_b_retw 6950 && vinsn->num_slots == 1 6951 && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 6952 && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 6953 && use_transform ()) 6954 { 6955 has_a0_b_retw = TRUE; 6956 6957 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. 6958 After the first assembly pass we will check all of them and 6959 add a nop if needed. */ 6960 frag_now->tc_frag_data.is_insn = TRUE; 6961 frag_var (rs_machine_dependent, 4, 4, 6962 RELAX_ADD_NOP_IF_A0_B_RETW, 6963 frag_now->fr_symbol, 6964 frag_now->fr_offset, 6965 NULL); 6966 xtensa_set_frag_assembly_state (frag_now); 6967 frag_now->tc_frag_data.is_insn = TRUE; 6968 frag_var (rs_machine_dependent, 4, 4, 6969 RELAX_ADD_NOP_IF_A0_B_RETW, 6970 frag_now->fr_symbol, 6971 frag_now->fr_offset, 6972 NULL); 6973 xtensa_set_frag_assembly_state (frag_now); 6974 } 6975 6976 for (slot = 0; slot < vinsn->num_slots; slot++) 6977 { 6978 tinsn = &vinsn->slots[slot]; 6979 6980 /* See if the instruction implies an aligned section. */ 6981 if (xtensa_opcode_is_loop (isa, tinsn->opcode) == 1) 6982 record_alignment (now_seg, 2); 6983 6984 /* Determine the best line number for debug info. */ 6985 if ((tinsn->loc_directive_seen || !loc_directive_seen) 6986 && (tinsn->debug_line.filenum != debug_line.filenum 6987 || tinsn->debug_line.line < debug_line.line 6988 || tinsn->debug_line.column < debug_line.column)) 6989 debug_line = tinsn->debug_line; 6990 if (tinsn->loc_directive_seen) 6991 loc_directive_seen = TRUE; 6992 } 6993 6994 /* Special cases for instructions that force an alignment... */ 6995 /* None of these opcodes are bundle-able. */ 6996 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) 6997 { 6998 int max_fill; 6999 7000 /* Remember the symbol that marks the end of the loop in the frag 7001 that marks the start of the loop. This way we can easily find 7002 the end of the loop at the beginning, without adding special code 7003 to mark the loop instructions themselves. */ 7004 symbolS *target_sym = NULL; 7005 if (vinsn->slots[0].tok[1].X_op == O_symbol) 7006 target_sym = vinsn->slots[0].tok[1].X_add_symbol; 7007 7008 xtensa_set_frag_assembly_state (frag_now); 7009 frag_now->tc_frag_data.is_insn = TRUE; 7010 7011 max_fill = get_text_align_max_fill_size 7012 (get_text_align_power (xtensa_fetch_width), 7013 TRUE, frag_now->tc_frag_data.is_no_density); 7014 7015 if (use_transform ()) 7016 frag_var (rs_machine_dependent, max_fill, max_fill, 7017 RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 7018 else 7019 frag_var (rs_machine_dependent, 0, 0, 7020 RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); 7021 xtensa_set_frag_assembly_state (frag_now); 7022 } 7023 7024 if (vinsn->slots[0].opcode == xtensa_entry_opcode 7025 && !vinsn->slots[0].is_specific_opcode) 7026 { 7027 xtensa_mark_literal_pool_location (); 7028 xtensa_move_labels (frag_now, 0); 7029 frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); 7030 } 7031 7032 if (vinsn->num_slots == 1) 7033 { 7034 if (workaround_a0_b_retw && use_transform ()) 7035 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, 7036 is_register_writer (&vinsn->slots[0], "a", 0)); 7037 7038 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, 7039 is_bad_loopend_opcode (&vinsn->slots[0])); 7040 } 7041 else 7042 set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); 7043 7044 insn_size = xtensa_format_length (isa, vinsn->format); 7045 7046 extra_space = relaxation_requirements (vinsn, &finish_frag); 7047 7048 /* vinsn_to_insnbuf will produce the error. */ 7049 if (vinsn->format != XTENSA_UNDEFINED) 7050 { 7051 f = frag_more (insn_size + extra_space); 7052 xtensa_set_frag_assembly_state (frag_now); 7053 frag_now->tc_frag_data.is_insn = TRUE; 7054 } 7055 7056 vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); 7057 if (vinsn->format == XTENSA_UNDEFINED) 7058 return; 7059 7060 xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); 7061 7062 if (debug_type == DEBUG_DWARF2 || loc_directive_seen) 7063 dwarf2_gen_line_info (frag_now_fix () - (insn_size + extra_space), 7064 &debug_line); 7065 7066 for (slot = 0; slot < vinsn->num_slots; slot++) 7067 { 7068 tinsn = &vinsn->slots[slot]; 7069 frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; 7070 frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; 7071 frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; 7072 frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; 7073 if (tinsn->literal_space != 0) 7074 xg_assemble_literal_space (tinsn->literal_space, slot); 7075 frag_now->tc_frag_data.free_reg[slot] = tinsn->extra_arg; 7076 7077 if (tinsn->subtype == RELAX_NARROW) 7078 gas_assert (vinsn->num_slots == 1); 7079 if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) 7080 is_jump = TRUE; 7081 if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) 7082 is_branch = TRUE; 7083 7084 if (tinsn->subtype || tinsn->symbol || tinsn->offset 7085 || tinsn->literal_frag || is_jump || is_branch) 7086 finish_frag = TRUE; 7087 } 7088 7089 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 7090 frag_now->tc_frag_data.is_specific_opcode = TRUE; 7091 7092 if (finish_frag) 7093 { 7094 frag_variant (rs_machine_dependent, 7095 extra_space, extra_space, RELAX_SLOTS, 7096 frag_now->fr_symbol, frag_now->fr_offset, f); 7097 xtensa_set_frag_assembly_state (frag_now); 7098 } 7099 7100 /* Special cases for loops: 7101 close_loop_end should be inserted AFTER short_loop. 7102 Make sure that CLOSE loops are processed BEFORE short_loops 7103 when converting them. */ 7104 7105 /* "short_loop": Add a NOP if the loop is < 4 bytes. */ 7106 if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 7107 && !vinsn->slots[0].is_specific_opcode) 7108 { 7109 if (workaround_short_loop && use_transform ()) 7110 { 7111 maybe_has_short_loop = TRUE; 7112 frag_now->tc_frag_data.is_insn = TRUE; 7113 frag_var (rs_machine_dependent, 4, 4, 7114 RELAX_ADD_NOP_IF_SHORT_LOOP, 7115 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7116 frag_now->tc_frag_data.is_insn = TRUE; 7117 frag_var (rs_machine_dependent, 4, 4, 7118 RELAX_ADD_NOP_IF_SHORT_LOOP, 7119 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7120 } 7121 7122 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a 7123 loop at least 12 bytes away from another loop's end. */ 7124 if (workaround_close_loop_end && use_transform ()) 7125 { 7126 maybe_has_close_loop_end = TRUE; 7127 frag_now->tc_frag_data.is_insn = TRUE; 7128 frag_var (rs_machine_dependent, 12, 12, 7129 RELAX_ADD_NOP_IF_CLOSE_LOOP_END, 7130 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7131 } 7132 } 7133 7134 if (use_transform ()) 7135 { 7136 if (is_jump) 7137 { 7138 gas_assert (finish_frag); 7139 frag_var (rs_machine_dependent, 7140 xtensa_fetch_width, xtensa_fetch_width, 7141 RELAX_UNREACHABLE, 7142 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7143 xtensa_set_frag_assembly_state (frag_now); 7144 } 7145 else if (is_branch && do_align_targets ()) 7146 { 7147 gas_assert (finish_frag); 7148 frag_var (rs_machine_dependent, 7149 xtensa_fetch_width, xtensa_fetch_width, 7150 RELAX_MAYBE_UNREACHABLE, 7151 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7152 xtensa_set_frag_assembly_state (frag_now); 7153 frag_var (rs_machine_dependent, 7154 0, 0, 7155 RELAX_MAYBE_DESIRE_ALIGN, 7156 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7157 xtensa_set_frag_assembly_state (frag_now); 7158 } 7159 } 7160 7161 /* Now, if the original opcode was a call... */ 7162 if (do_align_targets () 7163 && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) 7164 { 7165 float freq = get_subseg_total_freq (now_seg, now_subseg); 7166 frag_now->tc_frag_data.is_insn = TRUE; 7167 frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, 7168 frag_now->fr_symbol, frag_now->fr_offset, NULL); 7169 xtensa_set_frag_assembly_state (frag_now); 7170 } 7171 7172 if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) 7173 { 7174 frag_wane (frag_now); 7175 frag_new (0); 7176 xtensa_set_frag_assembly_state (frag_now); 7177 } 7178 } 7179 7180 7181 /* xtensa_end and helper functions. */ 7182 7183 static void xtensa_cleanup_align_frags (void); 7184 static void xtensa_fix_target_frags (void); 7185 static void xtensa_mark_narrow_branches (void); 7186 static void xtensa_mark_zcl_first_insns (void); 7187 static void xtensa_mark_difference_of_two_symbols (void); 7188 static void xtensa_fix_a0_b_retw_frags (void); 7189 static void xtensa_fix_b_j_loop_end_frags (void); 7190 static void xtensa_fix_close_loop_end_frags (void); 7191 static void xtensa_fix_short_loop_frags (void); 7192 static void xtensa_sanity_check (void); 7193 static void xtensa_add_config_info (void); 7194 7195 void 7196 xtensa_end (void) 7197 { 7198 directive_balance (); 7199 xtensa_flush_pending_output (); 7200 7201 past_xtensa_end = TRUE; 7202 7203 xtensa_move_literals (); 7204 7205 xtensa_reorder_segments (); 7206 xtensa_cleanup_align_frags (); 7207 xtensa_fix_target_frags (); 7208 if (workaround_a0_b_retw && has_a0_b_retw) 7209 xtensa_fix_a0_b_retw_frags (); 7210 if (workaround_b_j_loop_end) 7211 xtensa_fix_b_j_loop_end_frags (); 7212 7213 /* "close_loop_end" should be processed BEFORE "short_loop". */ 7214 if (workaround_close_loop_end && maybe_has_close_loop_end) 7215 xtensa_fix_close_loop_end_frags (); 7216 7217 if (workaround_short_loop && maybe_has_short_loop) 7218 xtensa_fix_short_loop_frags (); 7219 if (align_targets) 7220 xtensa_mark_narrow_branches (); 7221 xtensa_mark_zcl_first_insns (); 7222 7223 xtensa_sanity_check (); 7224 7225 xtensa_add_config_info (); 7226 } 7227 7228 7229 static void 7230 xtensa_cleanup_align_frags (void) 7231 { 7232 frchainS *frchP; 7233 asection *s; 7234 7235 for (s = stdoutput->sections; s; s = s->next) 7236 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7237 { 7238 fragS *fragP; 7239 /* Walk over all of the fragments in a subsection. */ 7240 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7241 { 7242 if ((fragP->fr_type == rs_align 7243 || fragP->fr_type == rs_align_code 7244 || (fragP->fr_type == rs_machine_dependent 7245 && (fragP->fr_subtype == RELAX_DESIRE_ALIGN 7246 || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) 7247 && fragP->fr_fix == 0) 7248 { 7249 fragS *next = fragP->fr_next; 7250 7251 while (next 7252 && next->fr_fix == 0 7253 && next->fr_type == rs_machine_dependent 7254 && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 7255 { 7256 frag_wane (next); 7257 next = next->fr_next; 7258 } 7259 } 7260 /* If we don't widen branch targets, then they 7261 will be easier to align. */ 7262 if (fragP->tc_frag_data.is_branch_target 7263 && fragP->fr_opcode == fragP->fr_literal 7264 && fragP->fr_type == rs_machine_dependent 7265 && fragP->fr_subtype == RELAX_SLOTS 7266 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 7267 frag_wane (fragP); 7268 if (fragP->fr_type == rs_machine_dependent 7269 && fragP->fr_subtype == RELAX_UNREACHABLE) 7270 fragP->tc_frag_data.is_unreachable = TRUE; 7271 } 7272 } 7273 } 7274 7275 7276 /* Re-process all of the fragments looking to convert all of the 7277 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch 7278 target in the next fragment, convert this to RELAX_DESIRE_ALIGN. 7279 Otherwise, convert to a .fill 0. */ 7280 7281 static void 7282 xtensa_fix_target_frags (void) 7283 { 7284 frchainS *frchP; 7285 asection *s; 7286 7287 /* When this routine is called, all of the subsections are still intact 7288 so we walk over subsections instead of sections. */ 7289 for (s = stdoutput->sections; s; s = s->next) 7290 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7291 { 7292 fragS *fragP; 7293 7294 /* Walk over all of the fragments in a subsection. */ 7295 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7296 { 7297 if (fragP->fr_type == rs_machine_dependent 7298 && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 7299 { 7300 if (next_frag_is_branch_target (fragP)) 7301 fragP->fr_subtype = RELAX_DESIRE_ALIGN; 7302 else 7303 frag_wane (fragP); 7304 } 7305 } 7306 } 7307 } 7308 7309 7310 static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); 7311 7312 static void 7313 xtensa_mark_narrow_branches (void) 7314 { 7315 frchainS *frchP; 7316 asection *s; 7317 7318 for (s = stdoutput->sections; s; s = s->next) 7319 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7320 { 7321 fragS *fragP; 7322 /* Walk over all of the fragments in a subsection. */ 7323 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7324 { 7325 if (fragP->fr_type == rs_machine_dependent 7326 && fragP->fr_subtype == RELAX_SLOTS 7327 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) 7328 { 7329 vliw_insn vinsn; 7330 7331 vinsn_from_chars (&vinsn, fragP->fr_opcode); 7332 tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); 7333 7334 if (vinsn.num_slots == 1 7335 && xtensa_opcode_is_branch (xtensa_default_isa, 7336 vinsn.slots[0].opcode) == 1 7337 && xg_get_single_size (vinsn.slots[0].opcode) == 2 7338 && is_narrow_branch_guaranteed_in_range (fragP, 7339 &vinsn.slots[0])) 7340 { 7341 fragP->fr_subtype = RELAX_SLOTS; 7342 fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; 7343 fragP->tc_frag_data.is_aligning_branch = 1; 7344 } 7345 } 7346 } 7347 } 7348 } 7349 7350 7351 /* A branch is typically widened only when its target is out of 7352 range. However, we would like to widen them to align a subsequent 7353 branch target when possible. 7354 7355 Because the branch relaxation code is so convoluted, the optimal solution 7356 (combining the two cases) is difficult to get right in all circumstances. 7357 We therefore go with an "almost as good" solution, where we only 7358 use for alignment narrow branches that definitely will not expand to a 7359 jump and a branch. These functions find and mark these cases. */ 7360 7361 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded 7362 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. 7363 We start counting beginning with the frag after the 2-byte branch, so the 7364 maximum offset is (4 - 2) + 63 = 65. */ 7365 #define MAX_IMMED6 65 7366 7367 static offsetT unrelaxed_frag_max_size (fragS *); 7368 7369 static bfd_boolean 7370 is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) 7371 { 7372 const expressionS *exp = &tinsn->tok[1]; 7373 symbolS *symbolP = exp->X_add_symbol; 7374 offsetT max_distance = exp->X_add_number; 7375 fragS *target_frag; 7376 7377 if (exp->X_op != O_symbol) 7378 return FALSE; 7379 7380 target_frag = symbol_get_frag (symbolP); 7381 7382 max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); 7383 if (is_branch_jmp_to_next (tinsn, fragP)) 7384 return FALSE; 7385 7386 /* The branch doesn't branch over it's own frag, 7387 but over the subsequent ones. */ 7388 fragP = fragP->fr_next; 7389 while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) 7390 { 7391 max_distance += unrelaxed_frag_max_size (fragP); 7392 fragP = fragP->fr_next; 7393 } 7394 if (max_distance <= MAX_IMMED6 && fragP == target_frag) 7395 return TRUE; 7396 return FALSE; 7397 } 7398 7399 7400 static void 7401 xtensa_mark_zcl_first_insns (void) 7402 { 7403 frchainS *frchP; 7404 asection *s; 7405 7406 for (s = stdoutput->sections; s; s = s->next) 7407 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7408 { 7409 fragS *fragP; 7410 /* Walk over all of the fragments in a subsection. */ 7411 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7412 { 7413 if (fragP->fr_type == rs_machine_dependent 7414 && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE 7415 || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) 7416 { 7417 /* Find the loop frag. */ 7418 fragS *loop_frag = next_non_empty_frag (fragP); 7419 /* Find the first insn frag. */ 7420 fragS *targ_frag = next_non_empty_frag (loop_frag); 7421 7422 /* Handle a corner case that comes up in hardware 7423 diagnostics. The original assembly looks like this: 7424 7425 loop aX, LabelA 7426 <empty_frag>--not found by next_non_empty_frag 7427 loop aY, LabelB 7428 7429 Depending on the start address, the assembler may or 7430 may not change it to look something like this: 7431 7432 loop aX, LabelA 7433 nop--frag isn't empty anymore 7434 loop aY, LabelB 7435 7436 So set up to check the alignment of the nop if it 7437 exists */ 7438 while (loop_frag != targ_frag) 7439 { 7440 if (loop_frag->fr_type == rs_machine_dependent 7441 && (loop_frag->fr_subtype == RELAX_ALIGN_NEXT_OPCODE 7442 || loop_frag->fr_subtype 7443 == RELAX_CHECK_ALIGN_NEXT_OPCODE)) 7444 targ_frag = loop_frag; 7445 else 7446 loop_frag = loop_frag->fr_next; 7447 } 7448 7449 /* Of course, sometimes (mostly for toy test cases) a 7450 zero-cost loop instruction is the last in a section. */ 7451 if (targ_frag) 7452 { 7453 targ_frag->tc_frag_data.is_first_loop_insn = TRUE; 7454 /* Do not widen a frag that is the first instruction of a 7455 zero-cost loop. It makes that loop harder to align. */ 7456 if (targ_frag->fr_type == rs_machine_dependent 7457 && targ_frag->fr_subtype == RELAX_SLOTS 7458 && (targ_frag->tc_frag_data.slot_subtypes[0] 7459 == RELAX_NARROW)) 7460 { 7461 if (targ_frag->tc_frag_data.is_aligning_branch) 7462 targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 7463 else 7464 { 7465 frag_wane (targ_frag); 7466 targ_frag->tc_frag_data.slot_subtypes[0] = 0; 7467 } 7468 } 7469 } 7470 if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) 7471 frag_wane (fragP); 7472 } 7473 } 7474 } 7475 } 7476 7477 7478 /* When a difference-of-symbols expression is encoded as a uleb128 or 7479 sleb128 value, the linker is unable to adjust that value to account for 7480 link-time relaxation. Mark all the code between such symbols so that 7481 its size cannot be changed by linker relaxation. */ 7482 7483 static void 7484 xtensa_mark_difference_of_two_symbols (void) 7485 { 7486 symbolS *expr_sym; 7487 7488 for (expr_sym = expr_symbols; expr_sym; 7489 expr_sym = symbol_get_tc (expr_sym)->next_expr_symbol) 7490 { 7491 expressionS *exp = symbol_get_value_expression (expr_sym); 7492 7493 if (exp->X_op == O_subtract) 7494 { 7495 symbolS *left = exp->X_add_symbol; 7496 symbolS *right = exp->X_op_symbol; 7497 7498 /* Difference of two symbols not in the same section 7499 are handled with relocations in the linker. */ 7500 if (S_GET_SEGMENT (left) == S_GET_SEGMENT (right)) 7501 { 7502 fragS *start; 7503 fragS *end; 7504 fragS *walk; 7505 7506 if (symbol_get_frag (left)->fr_address 7507 <= symbol_get_frag (right)->fr_address) 7508 { 7509 start = symbol_get_frag (left); 7510 end = symbol_get_frag (right); 7511 } 7512 else 7513 { 7514 start = symbol_get_frag (right); 7515 end = symbol_get_frag (left); 7516 } 7517 7518 if (start->tc_frag_data.no_transform_end != NULL) 7519 walk = start->tc_frag_data.no_transform_end; 7520 else 7521 walk = start; 7522 do 7523 { 7524 walk->tc_frag_data.is_no_transform = 1; 7525 walk = walk->fr_next; 7526 } 7527 while (walk && walk->fr_address < end->fr_address); 7528 7529 start->tc_frag_data.no_transform_end = walk; 7530 } 7531 } 7532 } 7533 } 7534 7535 7536 /* Re-process all of the fragments looking to convert all of the 7537 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a 7538 conditional branch or a retw/retw.n, convert this frag to one that 7539 will generate a NOP. In any case close it off with a .fill 0. */ 7540 7541 static bfd_boolean next_instrs_are_b_retw (fragS *); 7542 7543 static void 7544 xtensa_fix_a0_b_retw_frags (void) 7545 { 7546 frchainS *frchP; 7547 asection *s; 7548 7549 /* When this routine is called, all of the subsections are still intact 7550 so we walk over subsections instead of sections. */ 7551 for (s = stdoutput->sections; s; s = s->next) 7552 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7553 { 7554 fragS *fragP; 7555 7556 /* Walk over all of the fragments in a subsection. */ 7557 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7558 { 7559 if (fragP->fr_type == rs_machine_dependent 7560 && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) 7561 { 7562 if (next_instrs_are_b_retw (fragP)) 7563 { 7564 if (fragP->tc_frag_data.is_no_transform) 7565 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); 7566 else 7567 relax_frag_add_nop (fragP); 7568 } 7569 frag_wane (fragP); 7570 } 7571 } 7572 } 7573 } 7574 7575 7576 static bfd_boolean 7577 next_instrs_are_b_retw (fragS *fragP) 7578 { 7579 xtensa_opcode opcode; 7580 xtensa_format fmt; 7581 const fragS *next_fragP = next_non_empty_frag (fragP); 7582 static xtensa_insnbuf insnbuf = NULL; 7583 static xtensa_insnbuf slotbuf = NULL; 7584 xtensa_isa isa = xtensa_default_isa; 7585 int offset = 0; 7586 int slot; 7587 bfd_boolean branch_seen = FALSE; 7588 7589 if (!insnbuf) 7590 { 7591 insnbuf = xtensa_insnbuf_alloc (isa); 7592 slotbuf = xtensa_insnbuf_alloc (isa); 7593 } 7594 7595 if (next_fragP == NULL) 7596 return FALSE; 7597 7598 /* Check for the conditional branch. */ 7599 xtensa_insnbuf_from_chars 7600 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 7601 fmt = xtensa_format_decode (isa, insnbuf); 7602 if (fmt == XTENSA_UNDEFINED) 7603 return FALSE; 7604 7605 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 7606 { 7607 xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); 7608 opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 7609 7610 branch_seen = (branch_seen 7611 || xtensa_opcode_is_branch (isa, opcode) == 1); 7612 } 7613 7614 if (!branch_seen) 7615 return FALSE; 7616 7617 offset += xtensa_format_length (isa, fmt); 7618 if (offset == next_fragP->fr_fix) 7619 { 7620 next_fragP = next_non_empty_frag (next_fragP); 7621 offset = 0; 7622 } 7623 7624 if (next_fragP == NULL) 7625 return FALSE; 7626 7627 /* Check for the retw/retw.n. */ 7628 xtensa_insnbuf_from_chars 7629 (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); 7630 fmt = xtensa_format_decode (isa, insnbuf); 7631 7632 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we 7633 have no problems. */ 7634 if (fmt == XTENSA_UNDEFINED 7635 || xtensa_format_num_slots (isa, fmt) != 1) 7636 return FALSE; 7637 7638 xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); 7639 opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); 7640 7641 if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) 7642 return TRUE; 7643 7644 return FALSE; 7645 } 7646 7647 7648 /* Re-process all of the fragments looking to convert all of the 7649 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a 7650 loop end label, convert this frag to one that will generate a NOP. 7651 In any case close it off with a .fill 0. */ 7652 7653 static bfd_boolean next_instr_is_loop_end (fragS *); 7654 7655 static void 7656 xtensa_fix_b_j_loop_end_frags (void) 7657 { 7658 frchainS *frchP; 7659 asection *s; 7660 7661 /* When this routine is called, all of the subsections are still intact 7662 so we walk over subsections instead of sections. */ 7663 for (s = stdoutput->sections; s; s = s->next) 7664 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7665 { 7666 fragS *fragP; 7667 7668 /* Walk over all of the fragments in a subsection. */ 7669 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7670 { 7671 if (fragP->fr_type == rs_machine_dependent 7672 && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) 7673 { 7674 if (next_instr_is_loop_end (fragP)) 7675 { 7676 if (fragP->tc_frag_data.is_no_transform) 7677 as_bad (_("branching or jumping to a loop end may trigger hardware errata")); 7678 else 7679 relax_frag_add_nop (fragP); 7680 } 7681 frag_wane (fragP); 7682 } 7683 } 7684 } 7685 } 7686 7687 7688 static bfd_boolean 7689 next_instr_is_loop_end (fragS *fragP) 7690 { 7691 const fragS *next_fragP; 7692 7693 if (next_frag_is_loop_target (fragP)) 7694 return FALSE; 7695 7696 next_fragP = next_non_empty_frag (fragP); 7697 if (next_fragP == NULL) 7698 return FALSE; 7699 7700 if (!next_frag_is_loop_target (next_fragP)) 7701 return FALSE; 7702 7703 /* If the size is >= 3 then there is more than one instruction here. 7704 The hardware bug will not fire. */ 7705 if (next_fragP->fr_fix > 3) 7706 return FALSE; 7707 7708 return TRUE; 7709 } 7710 7711 7712 /* Re-process all of the fragments looking to convert all of the 7713 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is 7714 not MY loop's loop end within 12 bytes, add enough nops here to 7715 make it at least 12 bytes away. In any case close it off with a 7716 .fill 0. */ 7717 7718 static offsetT min_bytes_to_other_loop_end 7719 (fragS *, fragS *, offsetT); 7720 7721 static void 7722 xtensa_fix_close_loop_end_frags (void) 7723 { 7724 frchainS *frchP; 7725 asection *s; 7726 7727 /* When this routine is called, all of the subsections are still intact 7728 so we walk over subsections instead of sections. */ 7729 for (s = stdoutput->sections; s; s = s->next) 7730 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7731 { 7732 fragS *fragP; 7733 7734 fragS *current_target = NULL; 7735 7736 /* Walk over all of the fragments in a subsection. */ 7737 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7738 { 7739 if (fragP->fr_type == rs_machine_dependent 7740 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 7741 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 7742 current_target = symbol_get_frag (fragP->fr_symbol); 7743 7744 if (current_target 7745 && fragP->fr_type == rs_machine_dependent 7746 && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) 7747 { 7748 offsetT min_bytes; 7749 int bytes_added = 0; 7750 7751 #define REQUIRED_LOOP_DIVIDING_BYTES 12 7752 /* Max out at 12. */ 7753 min_bytes = min_bytes_to_other_loop_end 7754 (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); 7755 7756 if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) 7757 { 7758 if (fragP->tc_frag_data.is_no_transform) 7759 as_bad (_("loop end too close to another loop end may trigger hardware errata")); 7760 else 7761 { 7762 while (min_bytes + bytes_added 7763 < REQUIRED_LOOP_DIVIDING_BYTES) 7764 { 7765 int length = 3; 7766 7767 if (fragP->fr_var < length) 7768 as_fatal (_("fr_var %lu < length %d"), 7769 (long) fragP->fr_var, length); 7770 else 7771 { 7772 assemble_nop (length, 7773 fragP->fr_literal + fragP->fr_fix); 7774 fragP->fr_fix += length; 7775 fragP->fr_var -= length; 7776 } 7777 bytes_added += length; 7778 } 7779 } 7780 } 7781 frag_wane (fragP); 7782 } 7783 gas_assert (fragP->fr_type != rs_machine_dependent 7784 || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); 7785 } 7786 } 7787 } 7788 7789 7790 static offsetT unrelaxed_frag_min_size (fragS *); 7791 7792 static offsetT 7793 min_bytes_to_other_loop_end (fragS *fragP, 7794 fragS *current_target, 7795 offsetT max_size) 7796 { 7797 offsetT offset = 0; 7798 fragS *current_fragP; 7799 7800 for (current_fragP = fragP; 7801 current_fragP; 7802 current_fragP = current_fragP->fr_next) 7803 { 7804 if (current_fragP->tc_frag_data.is_loop_target 7805 && current_fragP != current_target) 7806 return offset; 7807 7808 offset += unrelaxed_frag_min_size (current_fragP); 7809 7810 if (offset >= max_size) 7811 return max_size; 7812 } 7813 return max_size; 7814 } 7815 7816 7817 static offsetT 7818 unrelaxed_frag_min_size (fragS *fragP) 7819 { 7820 offsetT size = fragP->fr_fix; 7821 7822 /* Add fill size. */ 7823 if (fragP->fr_type == rs_fill) 7824 size += fragP->fr_offset; 7825 7826 return size; 7827 } 7828 7829 7830 static offsetT 7831 unrelaxed_frag_max_size (fragS *fragP) 7832 { 7833 offsetT size = fragP->fr_fix; 7834 switch (fragP->fr_type) 7835 { 7836 case 0: 7837 /* Empty frags created by the obstack allocation scheme 7838 end up with type 0. */ 7839 break; 7840 case rs_fill: 7841 case rs_org: 7842 case rs_space: 7843 size += fragP->fr_offset; 7844 break; 7845 case rs_align: 7846 case rs_align_code: 7847 case rs_align_test: 7848 case rs_leb128: 7849 case rs_cfa: 7850 case rs_dwarf2dbg: 7851 /* No further adjustments needed. */ 7852 break; 7853 case rs_machine_dependent: 7854 if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) 7855 size += fragP->fr_var; 7856 break; 7857 default: 7858 /* We had darn well better know how big it is. */ 7859 gas_assert (0); 7860 break; 7861 } 7862 7863 return size; 7864 } 7865 7866 7867 /* Re-process all of the fragments looking to convert all 7868 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: 7869 7870 A) 7871 1) the instruction size count to the loop end label 7872 is too short (<= 2 instructions), 7873 2) loop has a jump or branch in it 7874 7875 or B) 7876 1) workaround_all_short_loops is TRUE 7877 2) The generating loop was a 'loopgtz' or 'loopnez' 7878 3) the instruction size count to the loop end label is too short 7879 (<= 2 instructions) 7880 then convert this frag (and maybe the next one) to generate a NOP. 7881 In any case close it off with a .fill 0. */ 7882 7883 static int count_insns_to_loop_end (fragS *, bfd_boolean, int); 7884 static bfd_boolean branch_before_loop_end (fragS *); 7885 7886 static void 7887 xtensa_fix_short_loop_frags (void) 7888 { 7889 frchainS *frchP; 7890 asection *s; 7891 7892 /* When this routine is called, all of the subsections are still intact 7893 so we walk over subsections instead of sections. */ 7894 for (s = stdoutput->sections; s; s = s->next) 7895 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 7896 { 7897 fragS *fragP; 7898 xtensa_opcode current_opcode = XTENSA_UNDEFINED; 7899 7900 /* Walk over all of the fragments in a subsection. */ 7901 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 7902 { 7903 if (fragP->fr_type == rs_machine_dependent 7904 && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) 7905 || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) 7906 { 7907 TInsn t_insn; 7908 fragS *loop_frag = next_non_empty_frag (fragP); 7909 tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); 7910 current_opcode = t_insn.opcode; 7911 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa, 7912 current_opcode) == 1); 7913 } 7914 7915 if (fragP->fr_type == rs_machine_dependent 7916 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 7917 { 7918 if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 7919 && (branch_before_loop_end (fragP->fr_next) 7920 || (workaround_all_short_loops 7921 && current_opcode != XTENSA_UNDEFINED 7922 && current_opcode != xtensa_loop_opcode))) 7923 { 7924 if (fragP->tc_frag_data.is_no_transform) 7925 as_bad (_("loop containing less than three instructions may trigger hardware errata")); 7926 else 7927 relax_frag_add_nop (fragP); 7928 } 7929 frag_wane (fragP); 7930 } 7931 } 7932 } 7933 } 7934 7935 7936 static int unrelaxed_frag_min_insn_count (fragS *); 7937 7938 static int 7939 count_insns_to_loop_end (fragS *base_fragP, 7940 bfd_boolean count_relax_add, 7941 int max_count) 7942 { 7943 fragS *fragP = NULL; 7944 int insn_count = 0; 7945 7946 fragP = base_fragP; 7947 7948 for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) 7949 { 7950 insn_count += unrelaxed_frag_min_insn_count (fragP); 7951 if (insn_count >= max_count) 7952 return max_count; 7953 7954 if (count_relax_add) 7955 { 7956 if (fragP->fr_type == rs_machine_dependent 7957 && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) 7958 { 7959 /* In order to add the appropriate number of 7960 NOPs, we count an instruction for downstream 7961 occurrences. */ 7962 insn_count++; 7963 if (insn_count >= max_count) 7964 return max_count; 7965 } 7966 } 7967 } 7968 return insn_count; 7969 } 7970 7971 7972 static int 7973 unrelaxed_frag_min_insn_count (fragS *fragP) 7974 { 7975 xtensa_isa isa = xtensa_default_isa; 7976 static xtensa_insnbuf insnbuf = NULL; 7977 int insn_count = 0; 7978 int offset = 0; 7979 7980 if (!fragP->tc_frag_data.is_insn) 7981 return insn_count; 7982 7983 if (!insnbuf) 7984 insnbuf = xtensa_insnbuf_alloc (isa); 7985 7986 /* Decode the fixed instructions. */ 7987 while (offset < fragP->fr_fix) 7988 { 7989 xtensa_format fmt; 7990 7991 xtensa_insnbuf_from_chars 7992 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 7993 fmt = xtensa_format_decode (isa, insnbuf); 7994 7995 if (fmt == XTENSA_UNDEFINED) 7996 { 7997 as_fatal (_("undecodable instruction in instruction frag")); 7998 return insn_count; 7999 } 8000 offset += xtensa_format_length (isa, fmt); 8001 insn_count++; 8002 } 8003 8004 return insn_count; 8005 } 8006 8007 8008 static bfd_boolean unrelaxed_frag_has_b_j (fragS *); 8009 8010 static bfd_boolean 8011 branch_before_loop_end (fragS *base_fragP) 8012 { 8013 fragS *fragP; 8014 8015 for (fragP = base_fragP; 8016 fragP && !fragP->tc_frag_data.is_loop_target; 8017 fragP = fragP->fr_next) 8018 { 8019 if (unrelaxed_frag_has_b_j (fragP)) 8020 return TRUE; 8021 } 8022 return FALSE; 8023 } 8024 8025 8026 static bfd_boolean 8027 unrelaxed_frag_has_b_j (fragS *fragP) 8028 { 8029 static xtensa_insnbuf insnbuf = NULL; 8030 xtensa_isa isa = xtensa_default_isa; 8031 int offset = 0; 8032 8033 if (!fragP->tc_frag_data.is_insn) 8034 return FALSE; 8035 8036 if (!insnbuf) 8037 insnbuf = xtensa_insnbuf_alloc (isa); 8038 8039 /* Decode the fixed instructions. */ 8040 while (offset < fragP->fr_fix) 8041 { 8042 xtensa_format fmt; 8043 int slot; 8044 8045 xtensa_insnbuf_from_chars 8046 (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); 8047 fmt = xtensa_format_decode (isa, insnbuf); 8048 if (fmt == XTENSA_UNDEFINED) 8049 return FALSE; 8050 8051 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 8052 { 8053 xtensa_opcode opcode = 8054 get_opcode_from_buf (fragP->fr_literal + offset, slot); 8055 if (xtensa_opcode_is_branch (isa, opcode) == 1 8056 || xtensa_opcode_is_jump (isa, opcode) == 1) 8057 return TRUE; 8058 } 8059 offset += xtensa_format_length (isa, fmt); 8060 } 8061 return FALSE; 8062 } 8063 8064 8065 /* Checks to be made after initial assembly but before relaxation. */ 8066 8067 static bfd_boolean is_empty_loop (const TInsn *, fragS *); 8068 static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); 8069 8070 static void 8071 xtensa_sanity_check (void) 8072 { 8073 char *file_name; 8074 unsigned line; 8075 frchainS *frchP; 8076 asection *s; 8077 8078 as_where (&file_name, &line); 8079 for (s = stdoutput->sections; s; s = s->next) 8080 for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) 8081 { 8082 fragS *fragP; 8083 8084 /* Walk over all of the fragments in a subsection. */ 8085 for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) 8086 { 8087 if (fragP->fr_type == rs_machine_dependent 8088 && fragP->fr_subtype == RELAX_SLOTS 8089 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) 8090 { 8091 static xtensa_insnbuf insnbuf = NULL; 8092 TInsn t_insn; 8093 8094 if (fragP->fr_opcode != NULL) 8095 { 8096 if (!insnbuf) 8097 insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); 8098 tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); 8099 tinsn_immed_from_frag (&t_insn, fragP, 0); 8100 8101 if (xtensa_opcode_is_loop (xtensa_default_isa, 8102 t_insn.opcode) == 1) 8103 { 8104 if (is_empty_loop (&t_insn, fragP)) 8105 { 8106 new_logical_line (fragP->fr_file, fragP->fr_line); 8107 as_bad (_("invalid empty loop")); 8108 } 8109 if (!is_local_forward_loop (&t_insn, fragP)) 8110 { 8111 new_logical_line (fragP->fr_file, fragP->fr_line); 8112 as_bad (_("loop target does not follow " 8113 "loop instruction in section")); 8114 } 8115 } 8116 } 8117 } 8118 } 8119 } 8120 new_logical_line (file_name, line); 8121 } 8122 8123 8124 #define LOOP_IMMED_OPN 1 8125 8126 /* Return TRUE if the loop target is the next non-zero fragment. */ 8127 8128 static bfd_boolean 8129 is_empty_loop (const TInsn *insn, fragS *fragP) 8130 { 8131 const expressionS *exp; 8132 symbolS *symbolP; 8133 fragS *next_fragP; 8134 8135 if (insn->insn_type != ITYPE_INSN) 8136 return FALSE; 8137 8138 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) 8139 return FALSE; 8140 8141 if (insn->ntok <= LOOP_IMMED_OPN) 8142 return FALSE; 8143 8144 exp = &insn->tok[LOOP_IMMED_OPN]; 8145 8146 if (exp->X_op != O_symbol) 8147 return FALSE; 8148 8149 symbolP = exp->X_add_symbol; 8150 if (!symbolP) 8151 return FALSE; 8152 8153 if (symbol_get_frag (symbolP) == NULL) 8154 return FALSE; 8155 8156 if (S_GET_VALUE (symbolP) != 0) 8157 return FALSE; 8158 8159 /* Walk through the zero-size fragments from this one. If we find 8160 the target fragment, then this is a zero-size loop. */ 8161 8162 for (next_fragP = fragP->fr_next; 8163 next_fragP != NULL; 8164 next_fragP = next_fragP->fr_next) 8165 { 8166 if (next_fragP == symbol_get_frag (symbolP)) 8167 return TRUE; 8168 if (next_fragP->fr_fix != 0) 8169 return FALSE; 8170 } 8171 return FALSE; 8172 } 8173 8174 8175 static bfd_boolean 8176 is_local_forward_loop (const TInsn *insn, fragS *fragP) 8177 { 8178 const expressionS *exp; 8179 symbolS *symbolP; 8180 fragS *next_fragP; 8181 8182 if (insn->insn_type != ITYPE_INSN) 8183 return FALSE; 8184 8185 if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) 8186 return FALSE; 8187 8188 if (insn->ntok <= LOOP_IMMED_OPN) 8189 return FALSE; 8190 8191 exp = &insn->tok[LOOP_IMMED_OPN]; 8192 8193 if (exp->X_op != O_symbol) 8194 return FALSE; 8195 8196 symbolP = exp->X_add_symbol; 8197 if (!symbolP) 8198 return FALSE; 8199 8200 if (symbol_get_frag (symbolP) == NULL) 8201 return FALSE; 8202 8203 /* Walk through fragments until we find the target. 8204 If we do not find the target, then this is an invalid loop. */ 8205 8206 for (next_fragP = fragP->fr_next; 8207 next_fragP != NULL; 8208 next_fragP = next_fragP->fr_next) 8209 { 8210 if (next_fragP == symbol_get_frag (symbolP)) 8211 return TRUE; 8212 } 8213 8214 return FALSE; 8215 } 8216 8217 8218 #define XTINFO_NAME "Xtensa_Info" 8219 #define XTINFO_NAMESZ 12 8220 #define XTINFO_TYPE 1 8221 8222 static void 8223 xtensa_add_config_info (void) 8224 { 8225 asection *info_sec; 8226 char *data, *p; 8227 int sz; 8228 8229 info_sec = subseg_new (".xtensa.info", 0); 8230 bfd_set_section_flags (stdoutput, info_sec, SEC_HAS_CONTENTS | SEC_READONLY); 8231 8232 data = xmalloc (100); 8233 sprintf (data, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n", 8234 XSHAL_USE_ABSOLUTE_LITERALS, XSHAL_ABI); 8235 sz = strlen (data) + 1; 8236 8237 /* Add enough null terminators to pad to a word boundary. */ 8238 do 8239 data[sz++] = 0; 8240 while ((sz & 3) != 0); 8241 8242 /* Follow the standard note section layout: 8243 First write the length of the name string. */ 8244 p = frag_more (4); 8245 md_number_to_chars (p, (valueT) XTINFO_NAMESZ, 4); 8246 8247 /* Next comes the length of the "descriptor", i.e., the actual data. */ 8248 p = frag_more (4); 8249 md_number_to_chars (p, (valueT) sz, 4); 8250 8251 /* Write the note type. */ 8252 p = frag_more (4); 8253 md_number_to_chars (p, (valueT) XTINFO_TYPE, 4); 8254 8255 /* Write the name field. */ 8256 p = frag_more (XTINFO_NAMESZ); 8257 memcpy (p, XTINFO_NAME, XTINFO_NAMESZ); 8258 8259 /* Finally, write the descriptor. */ 8260 p = frag_more (sz); 8261 memcpy (p, data, sz); 8262 8263 free (data); 8264 } 8265 8266 8267 /* Alignment Functions. */ 8268 8269 static int 8270 get_text_align_power (unsigned target_size) 8271 { 8272 if (target_size <= 4) 8273 return 2; 8274 8275 if (target_size <= 8) 8276 return 3; 8277 8278 if (target_size <= 16) 8279 return 4; 8280 8281 if (target_size <= 32) 8282 return 5; 8283 8284 if (target_size <= 64) 8285 return 6; 8286 8287 if (target_size <= 128) 8288 return 7; 8289 8290 if (target_size <= 256) 8291 return 8; 8292 8293 if (target_size <= 512) 8294 return 9; 8295 8296 if (target_size <= 1024) 8297 return 10; 8298 8299 gas_assert (0); 8300 return 0; 8301 } 8302 8303 8304 static int 8305 get_text_align_max_fill_size (int align_pow, 8306 bfd_boolean use_nops, 8307 bfd_boolean use_no_density) 8308 { 8309 if (!use_nops) 8310 return (1 << align_pow); 8311 if (use_no_density) 8312 return 3 * (1 << align_pow); 8313 8314 return 1 + (1 << align_pow); 8315 } 8316 8317 8318 /* Calculate the minimum bytes of fill needed at "address" to align a 8319 target instruction of size "target_size" so that it does not cross a 8320 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, 8321 the fill can be an arbitrary number of bytes. Otherwise, the space must 8322 be filled by NOP instructions. */ 8323 8324 static int 8325 get_text_align_fill_size (addressT address, 8326 int align_pow, 8327 int target_size, 8328 bfd_boolean use_nops, 8329 bfd_boolean use_no_density) 8330 { 8331 addressT alignment, fill, fill_limit, fill_step; 8332 bfd_boolean skip_one = FALSE; 8333 8334 alignment = (1 << align_pow); 8335 gas_assert (target_size > 0 && alignment >= (addressT) target_size); 8336 8337 if (!use_nops) 8338 { 8339 fill_limit = alignment; 8340 fill_step = 1; 8341 } 8342 else if (!use_no_density) 8343 { 8344 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ 8345 fill_limit = alignment * 2; 8346 fill_step = 1; 8347 skip_one = TRUE; 8348 } 8349 else 8350 { 8351 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ 8352 fill_limit = alignment * 3; 8353 fill_step = 3; 8354 } 8355 8356 /* Try all fill sizes until finding one that works. */ 8357 for (fill = 0; fill < fill_limit; fill += fill_step) 8358 { 8359 if (skip_one && fill == 1) 8360 continue; 8361 if ((address + fill) >> align_pow 8362 == (address + fill + target_size - 1) >> align_pow) 8363 return fill; 8364 } 8365 gas_assert (0); 8366 return 0; 8367 } 8368 8369 8370 static int 8371 branch_align_power (segT sec) 8372 { 8373 /* If the Xtensa processor has a fetch width of X, and 8374 the section is aligned to at least that boundary, then a branch 8375 target need only fit within that aligned block of memory to avoid 8376 a stall. Otherwise, try to fit branch targets within 4-byte 8377 aligned blocks (which may be insufficient, e.g., if the section 8378 has no alignment, but it's good enough). */ 8379 int fetch_align = get_text_align_power(xtensa_fetch_width); 8380 int sec_align = get_recorded_alignment (sec); 8381 8382 if (sec_align >= fetch_align) 8383 return fetch_align; 8384 8385 return 2; 8386 } 8387 8388 8389 /* This will assert if it is not possible. */ 8390 8391 static int 8392 get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) 8393 { 8394 int count = 0; 8395 8396 if (use_no_density) 8397 { 8398 gas_assert (fill_size % 3 == 0); 8399 return (fill_size / 3); 8400 } 8401 8402 gas_assert (fill_size != 1); /* Bad argument. */ 8403 8404 while (fill_size > 1) 8405 { 8406 int insn_size = 3; 8407 if (fill_size == 2 || fill_size == 4) 8408 insn_size = 2; 8409 fill_size -= insn_size; 8410 count++; 8411 } 8412 gas_assert (fill_size != 1); /* Bad algorithm. */ 8413 return count; 8414 } 8415 8416 8417 static int 8418 get_text_align_nth_nop_size (offsetT fill_size, 8419 int n, 8420 bfd_boolean use_no_density) 8421 { 8422 int count = 0; 8423 8424 if (use_no_density) 8425 return 3; 8426 8427 gas_assert (fill_size != 1); /* Bad argument. */ 8428 8429 while (fill_size > 1) 8430 { 8431 int insn_size = 3; 8432 if (fill_size == 2 || fill_size == 4) 8433 insn_size = 2; 8434 fill_size -= insn_size; 8435 count++; 8436 if (n + 1 == count) 8437 return insn_size; 8438 } 8439 gas_assert (0); 8440 return 0; 8441 } 8442 8443 8444 /* For the given fragment, find the appropriate address 8445 for it to begin at if we are using NOPs to align it. */ 8446 8447 static addressT 8448 get_noop_aligned_address (fragS *fragP, addressT address) 8449 { 8450 /* The rule is: get next fragment's FIRST instruction. Find 8451 the smallest number of bytes that need to be added to 8452 ensure that the next fragment's FIRST instruction will fit 8453 in a single word. 8454 8455 E.G., 2 bytes : 0, 1, 2 mod 4 8456 3 bytes: 0, 1 mod 4 8457 8458 If the FIRST instruction MIGHT be relaxed, 8459 assume that it will become a 3-byte instruction. 8460 8461 Note again here that LOOP instructions are not bundleable, 8462 and this relaxation only applies to LOOP opcodes. */ 8463 8464 int fill_size = 0; 8465 int first_insn_size; 8466 int loop_insn_size; 8467 addressT pre_opcode_bytes; 8468 int align_power; 8469 fragS *first_insn; 8470 xtensa_opcode opcode; 8471 bfd_boolean is_loop; 8472 8473 gas_assert (fragP->fr_type == rs_machine_dependent); 8474 gas_assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); 8475 8476 /* Find the loop frag. */ 8477 first_insn = next_non_empty_frag (fragP); 8478 /* Now find the first insn frag. */ 8479 first_insn = next_non_empty_frag (first_insn); 8480 8481 is_loop = next_frag_opcode_is_loop (fragP, &opcode); 8482 gas_assert (is_loop); 8483 loop_insn_size = xg_get_single_size (opcode); 8484 8485 pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); 8486 pre_opcode_bytes += loop_insn_size; 8487 8488 /* For loops, the alignment depends on the size of the 8489 instruction following the loop, not the LOOP instruction. */ 8490 8491 if (first_insn == NULL) 8492 first_insn_size = xtensa_fetch_width; 8493 else 8494 first_insn_size = get_loop_align_size (frag_format_size (first_insn)); 8495 8496 /* If it was 8, then we'll need a larger alignment for the section. */ 8497 align_power = get_text_align_power (first_insn_size); 8498 record_alignment (now_seg, align_power); 8499 8500 fill_size = get_text_align_fill_size 8501 (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, 8502 fragP->tc_frag_data.is_no_density); 8503 8504 return address + fill_size; 8505 } 8506 8507 8508 /* 3 mechanisms for relaxing an alignment: 8509 8510 Align to a power of 2. 8511 Align so the next fragment's instruction does not cross a word boundary. 8512 Align the current instruction so that if the next instruction 8513 were 3 bytes, it would not cross a word boundary. 8514 8515 We can align with: 8516 8517 zeros - This is easy; always insert zeros. 8518 nops - 3-byte and 2-byte instructions 8519 2 - 2-byte nop 8520 3 - 3-byte nop 8521 4 - 2 2-byte nops 8522 >=5 : 3-byte instruction + fn (n-3) 8523 widening - widen previous instructions. */ 8524 8525 static offsetT 8526 get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) 8527 { 8528 addressT target_address, loop_insn_offset; 8529 int target_size; 8530 xtensa_opcode loop_opcode; 8531 bfd_boolean is_loop; 8532 int align_power; 8533 offsetT opt_diff; 8534 offsetT branch_align; 8535 fragS *loop_frag; 8536 8537 gas_assert (fragP->fr_type == rs_machine_dependent); 8538 switch (fragP->fr_subtype) 8539 { 8540 case RELAX_DESIRE_ALIGN: 8541 target_size = next_frag_format_size (fragP); 8542 if (target_size == XTENSA_UNDEFINED) 8543 target_size = 3; 8544 align_power = branch_align_power (now_seg); 8545 branch_align = 1 << align_power; 8546 /* Don't count on the section alignment being as large as the target. */ 8547 if (target_size > branch_align) 8548 target_size = branch_align; 8549 opt_diff = get_text_align_fill_size (address, align_power, 8550 target_size, FALSE, FALSE); 8551 8552 *max_diff = (opt_diff + branch_align 8553 - (target_size + ((address + opt_diff) % branch_align))); 8554 gas_assert (*max_diff >= opt_diff); 8555 return opt_diff; 8556 8557 case RELAX_ALIGN_NEXT_OPCODE: 8558 /* The next non-empty frag after this one holds the LOOP instruction 8559 that needs to be aligned. The required alignment depends on the 8560 size of the next non-empty frag after the loop frag, i.e., the 8561 first instruction in the loop. */ 8562 loop_frag = next_non_empty_frag (fragP); 8563 target_size = get_loop_align_size (next_frag_format_size (loop_frag)); 8564 loop_insn_offset = 0; 8565 is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); 8566 gas_assert (is_loop); 8567 8568 /* If the loop has been expanded then the LOOP instruction 8569 could be at an offset from this fragment. */ 8570 if (loop_frag->tc_frag_data.slot_subtypes[0] != RELAX_IMMED) 8571 loop_insn_offset = get_expanded_loop_offset (loop_opcode); 8572 8573 /* In an ideal world, which is what we are shooting for here, 8574 we wouldn't need to use any NOPs immediately prior to the 8575 LOOP instruction. If this approach fails, relax_frag_loop_align 8576 will call get_noop_aligned_address. */ 8577 target_address = 8578 address + loop_insn_offset + xg_get_single_size (loop_opcode); 8579 align_power = get_text_align_power (target_size); 8580 opt_diff = get_text_align_fill_size (target_address, align_power, 8581 target_size, FALSE, FALSE); 8582 8583 *max_diff = xtensa_fetch_width 8584 - ((target_address + opt_diff) % xtensa_fetch_width) 8585 - target_size + opt_diff; 8586 gas_assert (*max_diff >= opt_diff); 8587 return opt_diff; 8588 8589 default: 8590 break; 8591 } 8592 gas_assert (0); 8593 return 0; 8594 } 8595 8596 8597 /* md_relax_frag Hook and Helper Functions. */ 8598 8599 static long relax_frag_loop_align (fragS *, long); 8600 static long relax_frag_for_align (fragS *, long); 8601 static long relax_frag_immed 8602 (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); 8603 8604 8605 /* Return the number of bytes added to this fragment, given that the 8606 input has been stretched already by "stretch". */ 8607 8608 long 8609 xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) 8610 { 8611 xtensa_isa isa = xtensa_default_isa; 8612 int unreported = fragP->tc_frag_data.unreported_expansion; 8613 long new_stretch = 0; 8614 char *file_name; 8615 unsigned line; 8616 int lit_size; 8617 static xtensa_insnbuf vbuf = NULL; 8618 int slot, num_slots; 8619 xtensa_format fmt; 8620 8621 as_where (&file_name, &line); 8622 new_logical_line (fragP->fr_file, fragP->fr_line); 8623 8624 fragP->tc_frag_data.unreported_expansion = 0; 8625 8626 switch (fragP->fr_subtype) 8627 { 8628 case RELAX_ALIGN_NEXT_OPCODE: 8629 /* Always convert. */ 8630 if (fragP->tc_frag_data.relax_seen) 8631 new_stretch = relax_frag_loop_align (fragP, stretch); 8632 break; 8633 8634 case RELAX_LOOP_END: 8635 /* Do nothing. */ 8636 break; 8637 8638 case RELAX_LOOP_END_ADD_NOP: 8639 /* Add a NOP and switch to .fill 0. */ 8640 new_stretch = relax_frag_add_nop (fragP); 8641 frag_wane (fragP); 8642 break; 8643 8644 case RELAX_DESIRE_ALIGN: 8645 /* Do nothing. The narrowing before this frag will either align 8646 it or not. */ 8647 break; 8648 8649 case RELAX_LITERAL: 8650 case RELAX_LITERAL_FINAL: 8651 return 0; 8652 8653 case RELAX_LITERAL_NR: 8654 lit_size = 4; 8655 fragP->fr_subtype = RELAX_LITERAL_FINAL; 8656 gas_assert (unreported == lit_size); 8657 memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); 8658 fragP->fr_var -= lit_size; 8659 fragP->fr_fix += lit_size; 8660 new_stretch = 4; 8661 break; 8662 8663 case RELAX_SLOTS: 8664 if (vbuf == NULL) 8665 vbuf = xtensa_insnbuf_alloc (isa); 8666 8667 xtensa_insnbuf_from_chars 8668 (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); 8669 fmt = xtensa_format_decode (isa, vbuf); 8670 num_slots = xtensa_format_num_slots (isa, fmt); 8671 8672 for (slot = 0; slot < num_slots; slot++) 8673 { 8674 switch (fragP->tc_frag_data.slot_subtypes[slot]) 8675 { 8676 case RELAX_NARROW: 8677 if (fragP->tc_frag_data.relax_seen) 8678 new_stretch += relax_frag_for_align (fragP, stretch); 8679 break; 8680 8681 case RELAX_IMMED: 8682 case RELAX_IMMED_STEP1: 8683 case RELAX_IMMED_STEP2: 8684 case RELAX_IMMED_STEP3: 8685 /* Place the immediate. */ 8686 new_stretch += relax_frag_immed 8687 (now_seg, fragP, stretch, 8688 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 8689 fmt, slot, stretched_p, FALSE); 8690 break; 8691 8692 default: 8693 /* This is OK; see the note in xg_assemble_vliw_tokens. */ 8694 break; 8695 } 8696 } 8697 break; 8698 8699 case RELAX_LITERAL_POOL_BEGIN: 8700 case RELAX_LITERAL_POOL_END: 8701 case RELAX_MAYBE_UNREACHABLE: 8702 case RELAX_MAYBE_DESIRE_ALIGN: 8703 /* No relaxation required. */ 8704 break; 8705 8706 case RELAX_FILL_NOP: 8707 case RELAX_UNREACHABLE: 8708 if (fragP->tc_frag_data.relax_seen) 8709 new_stretch += relax_frag_for_align (fragP, stretch); 8710 break; 8711 8712 default: 8713 as_bad (_("bad relaxation state")); 8714 } 8715 8716 /* Tell gas we need another relaxation pass. */ 8717 if (! fragP->tc_frag_data.relax_seen) 8718 { 8719 fragP->tc_frag_data.relax_seen = TRUE; 8720 *stretched_p = 1; 8721 } 8722 8723 new_logical_line (file_name, line); 8724 return new_stretch; 8725 } 8726 8727 8728 static long 8729 relax_frag_loop_align (fragS *fragP, long stretch) 8730 { 8731 addressT old_address, old_next_address, old_size; 8732 addressT new_address, new_next_address, new_size; 8733 addressT growth; 8734 8735 /* All the frags with relax_frag_for_alignment prior to this one in the 8736 section have been done, hopefully eliminating the need for a NOP here. 8737 But, this will put it in if necessary. */ 8738 8739 /* Calculate the old address of this fragment and the next fragment. */ 8740 old_address = fragP->fr_address - stretch; 8741 old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + 8742 fragP->tc_frag_data.text_expansion[0]); 8743 old_size = old_next_address - old_address; 8744 8745 /* Calculate the new address of this fragment and the next fragment. */ 8746 new_address = fragP->fr_address; 8747 new_next_address = 8748 get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); 8749 new_size = new_next_address - new_address; 8750 8751 growth = new_size - old_size; 8752 8753 /* Fix up the text_expansion field and return the new growth. */ 8754 fragP->tc_frag_data.text_expansion[0] += growth; 8755 return growth; 8756 } 8757 8758 8759 /* Add a NOP instruction. */ 8760 8761 static long 8762 relax_frag_add_nop (fragS *fragP) 8763 { 8764 char *nop_buf = fragP->fr_literal + fragP->fr_fix; 8765 int length = fragP->tc_frag_data.is_no_density ? 3 : 2; 8766 assemble_nop (length, nop_buf); 8767 fragP->tc_frag_data.is_insn = TRUE; 8768 8769 if (fragP->fr_var < length) 8770 { 8771 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); 8772 return 0; 8773 } 8774 8775 fragP->fr_fix += length; 8776 fragP->fr_var -= length; 8777 return length; 8778 } 8779 8780 8781 static long future_alignment_required (fragS *, long); 8782 8783 static long 8784 relax_frag_for_align (fragS *fragP, long stretch) 8785 { 8786 /* Overview of the relaxation procedure for alignment: 8787 We can widen with NOPs or by widening instructions or by filling 8788 bytes after jump instructions. Find the opportune places and widen 8789 them if necessary. */ 8790 8791 long stretch_me; 8792 long diff; 8793 8794 gas_assert (fragP->fr_subtype == RELAX_FILL_NOP 8795 || fragP->fr_subtype == RELAX_UNREACHABLE 8796 || (fragP->fr_subtype == RELAX_SLOTS 8797 && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); 8798 8799 stretch_me = future_alignment_required (fragP, stretch); 8800 diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; 8801 if (diff == 0) 8802 return 0; 8803 8804 if (diff < 0) 8805 { 8806 /* We expanded on a previous pass. Can we shrink now? */ 8807 long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; 8808 if (shrink <= stretch && stretch > 0) 8809 { 8810 fragP->tc_frag_data.text_expansion[0] = stretch_me; 8811 return -shrink; 8812 } 8813 return 0; 8814 } 8815 8816 /* Below here, diff > 0. */ 8817 fragP->tc_frag_data.text_expansion[0] = stretch_me; 8818 8819 return diff; 8820 } 8821 8822 8823 /* Return the address of the next frag that should be aligned. 8824 8825 By "address" we mean the address it _would_ be at if there 8826 is no action taken to align it between here and the target frag. 8827 In other words, if no narrows and no fill nops are used between 8828 here and the frag to align, _even_if_ some of the frags we use 8829 to align targets have already expanded on a previous relaxation 8830 pass. 8831 8832 Also, count each frag that may be used to help align the target. 8833 8834 Return 0 if there are no frags left in the chain that need to be 8835 aligned. */ 8836 8837 static addressT 8838 find_address_of_next_align_frag (fragS **fragPP, 8839 int *wide_nops, 8840 int *narrow_nops, 8841 int *widens, 8842 bfd_boolean *paddable) 8843 { 8844 fragS *fragP = *fragPP; 8845 addressT address = fragP->fr_address; 8846 8847 /* Do not reset the counts to 0. */ 8848 8849 while (fragP) 8850 { 8851 /* Limit this to a small search. */ 8852 if (*widens >= (int) xtensa_fetch_width) 8853 { 8854 *fragPP = fragP; 8855 return 0; 8856 } 8857 address += fragP->fr_fix; 8858 8859 if (fragP->fr_type == rs_fill) 8860 address += fragP->fr_offset * fragP->fr_var; 8861 else if (fragP->fr_type == rs_machine_dependent) 8862 { 8863 switch (fragP->fr_subtype) 8864 { 8865 case RELAX_UNREACHABLE: 8866 *paddable = TRUE; 8867 break; 8868 8869 case RELAX_FILL_NOP: 8870 (*wide_nops)++; 8871 if (!fragP->tc_frag_data.is_no_density) 8872 (*narrow_nops)++; 8873 break; 8874 8875 case RELAX_SLOTS: 8876 if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 8877 { 8878 (*widens)++; 8879 break; 8880 } 8881 address += total_frag_text_expansion (fragP);; 8882 break; 8883 8884 case RELAX_IMMED: 8885 address += fragP->tc_frag_data.text_expansion[0]; 8886 break; 8887 8888 case RELAX_ALIGN_NEXT_OPCODE: 8889 case RELAX_DESIRE_ALIGN: 8890 *fragPP = fragP; 8891 return address; 8892 8893 case RELAX_MAYBE_UNREACHABLE: 8894 case RELAX_MAYBE_DESIRE_ALIGN: 8895 /* Do nothing. */ 8896 break; 8897 8898 default: 8899 /* Just punt if we don't know the type. */ 8900 *fragPP = fragP; 8901 return 0; 8902 } 8903 } 8904 else 8905 { 8906 /* Just punt if we don't know the type. */ 8907 *fragPP = fragP; 8908 return 0; 8909 } 8910 fragP = fragP->fr_next; 8911 } 8912 8913 *fragPP = fragP; 8914 return 0; 8915 } 8916 8917 8918 static long bytes_to_stretch (fragS *, int, int, int, int); 8919 8920 static long 8921 future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) 8922 { 8923 fragS *this_frag = fragP; 8924 long address; 8925 int num_widens = 0; 8926 int wide_nops = 0; 8927 int narrow_nops = 0; 8928 bfd_boolean paddable = FALSE; 8929 offsetT local_opt_diff; 8930 offsetT opt_diff; 8931 offsetT max_diff; 8932 int stretch_amount = 0; 8933 int local_stretch_amount; 8934 int global_stretch_amount; 8935 8936 address = find_address_of_next_align_frag 8937 (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); 8938 8939 if (!address) 8940 { 8941 if (this_frag->tc_frag_data.is_aligning_branch) 8942 this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; 8943 else 8944 frag_wane (this_frag); 8945 } 8946 else 8947 { 8948 local_opt_diff = get_aligned_diff (fragP, address, &max_diff); 8949 opt_diff = local_opt_diff; 8950 gas_assert (opt_diff >= 0); 8951 gas_assert (max_diff >= opt_diff); 8952 if (max_diff == 0) 8953 return 0; 8954 8955 if (fragP) 8956 fragP = fragP->fr_next; 8957 8958 while (fragP && opt_diff < max_diff && address) 8959 { 8960 /* We only use these to determine if we can exit early 8961 because there will be plenty of ways to align future 8962 align frags. */ 8963 int glob_widens = 0; 8964 int dnn = 0; 8965 int dw = 0; 8966 bfd_boolean glob_pad = 0; 8967 address = find_address_of_next_align_frag 8968 (&fragP, &glob_widens, &dnn, &dw, &glob_pad); 8969 /* If there is a padable portion, then skip. */ 8970 if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) 8971 address = 0; 8972 8973 if (address) 8974 { 8975 offsetT next_m_diff; 8976 offsetT next_o_diff; 8977 8978 /* Downrange frags haven't had stretch added to them yet. */ 8979 address += stretch; 8980 8981 /* The address also includes any text expansion from this 8982 frag in a previous pass, but we don't want that. */ 8983 address -= this_frag->tc_frag_data.text_expansion[0]; 8984 8985 /* Assume we are going to move at least opt_diff. In 8986 reality, we might not be able to, but assuming that 8987 we will helps catch cases where moving opt_diff pushes 8988 the next target from aligned to unaligned. */ 8989 address += opt_diff; 8990 8991 next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); 8992 8993 /* Now cleanup for the adjustments to address. */ 8994 next_o_diff += opt_diff; 8995 next_m_diff += opt_diff; 8996 if (next_o_diff <= max_diff && next_o_diff > opt_diff) 8997 opt_diff = next_o_diff; 8998 if (next_m_diff < max_diff) 8999 max_diff = next_m_diff; 9000 fragP = fragP->fr_next; 9001 } 9002 } 9003 9004 /* If there are enough wideners in between, do it. */ 9005 if (paddable) 9006 { 9007 if (this_frag->fr_subtype == RELAX_UNREACHABLE) 9008 { 9009 gas_assert (opt_diff <= (signed) xtensa_fetch_width); 9010 return opt_diff; 9011 } 9012 return 0; 9013 } 9014 local_stretch_amount 9015 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 9016 num_widens, local_opt_diff); 9017 global_stretch_amount 9018 = bytes_to_stretch (this_frag, wide_nops, narrow_nops, 9019 num_widens, opt_diff); 9020 /* If the condition below is true, then the frag couldn't 9021 stretch the correct amount for the global case, so we just 9022 optimize locally. We'll rely on the subsequent frags to get 9023 the correct alignment in the global case. */ 9024 if (global_stretch_amount < local_stretch_amount) 9025 stretch_amount = local_stretch_amount; 9026 else 9027 stretch_amount = global_stretch_amount; 9028 9029 if (this_frag->fr_subtype == RELAX_SLOTS 9030 && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) 9031 gas_assert (stretch_amount <= 1); 9032 else if (this_frag->fr_subtype == RELAX_FILL_NOP) 9033 { 9034 if (this_frag->tc_frag_data.is_no_density) 9035 gas_assert (stretch_amount == 3 || stretch_amount == 0); 9036 else 9037 gas_assert (stretch_amount <= 3); 9038 } 9039 } 9040 return stretch_amount; 9041 } 9042 9043 9044 /* The idea: widen everything you can to get a target or loop aligned, 9045 then start using NOPs. 9046 9047 wide_nops = the number of wide NOPs available for aligning 9048 narrow_nops = the number of narrow NOPs available for aligning 9049 (a subset of wide_nops) 9050 widens = the number of narrow instructions that should be widened 9051 9052 */ 9053 9054 static long 9055 bytes_to_stretch (fragS *this_frag, 9056 int wide_nops, 9057 int narrow_nops, 9058 int num_widens, 9059 int desired_diff) 9060 { 9061 int nops_needed; 9062 int nop_bytes; 9063 int extra_bytes; 9064 int bytes_short = desired_diff - num_widens; 9065 9066 gas_assert (desired_diff >= 0 9067 && desired_diff < (signed) xtensa_fetch_width); 9068 if (desired_diff == 0) 9069 return 0; 9070 9071 gas_assert (wide_nops > 0 || num_widens > 0); 9072 9073 /* Always prefer widening to NOP-filling. */ 9074 if (bytes_short < 0) 9075 { 9076 /* There are enough RELAX_NARROW frags after this one 9077 to align the target without widening this frag in any way. */ 9078 return 0; 9079 } 9080 9081 if (bytes_short == 0) 9082 { 9083 /* Widen every narrow between here and the align target 9084 and the align target will be properly aligned. */ 9085 if (this_frag->fr_subtype == RELAX_FILL_NOP) 9086 return 0; 9087 else 9088 return 1; 9089 } 9090 9091 /* From here we will need at least one NOP to get an alignment. 9092 However, we may not be able to align at all, in which case, 9093 don't widen. */ 9094 nops_needed = desired_diff / 3; 9095 9096 /* If there aren't enough nops, don't widen. */ 9097 if (nops_needed > wide_nops) 9098 return 0; 9099 9100 /* First try it with all wide nops. */ 9101 nop_bytes = nops_needed * 3; 9102 extra_bytes = desired_diff - nop_bytes; 9103 9104 if (nop_bytes + num_widens >= desired_diff) 9105 { 9106 if (this_frag->fr_subtype == RELAX_FILL_NOP) 9107 return 3; 9108 else if (num_widens == extra_bytes) 9109 return 1; 9110 return 0; 9111 } 9112 9113 /* Add a narrow nop. */ 9114 nops_needed++; 9115 nop_bytes += 2; 9116 extra_bytes -= 2; 9117 if (narrow_nops == 0 || nops_needed > wide_nops) 9118 return 0; 9119 9120 if (nop_bytes + num_widens >= desired_diff && extra_bytes >= 0) 9121 { 9122 if (this_frag->fr_subtype == RELAX_FILL_NOP) 9123 return !this_frag->tc_frag_data.is_no_density ? 2 : 3; 9124 else if (num_widens == extra_bytes) 9125 return 1; 9126 return 0; 9127 } 9128 9129 /* Replace a wide nop with a narrow nop--we can get here if 9130 extra_bytes was negative in the previous conditional. */ 9131 if (narrow_nops == 1) 9132 return 0; 9133 nop_bytes--; 9134 extra_bytes++; 9135 if (nop_bytes + num_widens >= desired_diff) 9136 { 9137 if (this_frag->fr_subtype == RELAX_FILL_NOP) 9138 return !this_frag->tc_frag_data.is_no_density ? 2 : 3; 9139 else if (num_widens == extra_bytes) 9140 return 1; 9141 return 0; 9142 } 9143 9144 /* If we can't satisfy any of the above cases, then we can't align 9145 using padding or fill nops. */ 9146 return 0; 9147 } 9148 9149 9150 static long 9151 relax_frag_immed (segT segP, 9152 fragS *fragP, 9153 long stretch, 9154 int min_steps, 9155 xtensa_format fmt, 9156 int slot, 9157 int *stretched_p, 9158 bfd_boolean estimate_only) 9159 { 9160 TInsn tinsn; 9161 int old_size; 9162 bfd_boolean negatable_branch = FALSE; 9163 bfd_boolean branch_jmp_to_next = FALSE; 9164 bfd_boolean from_wide_insn = FALSE; 9165 xtensa_isa isa = xtensa_default_isa; 9166 IStack istack; 9167 offsetT frag_offset; 9168 int num_steps; 9169 int num_text_bytes, num_literal_bytes; 9170 int literal_diff, total_text_diff, this_text_diff; 9171 9172 gas_assert (fragP->fr_opcode != NULL); 9173 9174 xg_clear_vinsn (&cur_vinsn); 9175 vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); 9176 if (cur_vinsn.num_slots > 1) 9177 from_wide_insn = TRUE; 9178 9179 tinsn = cur_vinsn.slots[slot]; 9180 tinsn_immed_from_frag (&tinsn, fragP, slot); 9181 9182 if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) 9183 return 0; 9184 9185 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 9186 branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); 9187 9188 negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); 9189 9190 old_size = xtensa_format_length (isa, fmt); 9191 9192 /* Special case: replace a branch to the next instruction with a NOP. 9193 This is required to work around a hardware bug in T1040.0 and also 9194 serves as an optimization. */ 9195 9196 if (branch_jmp_to_next 9197 && ((old_size == 2) || (old_size == 3)) 9198 && !next_frag_is_loop_target (fragP)) 9199 return 0; 9200 9201 /* Here is the fun stuff: Get the immediate field from this 9202 instruction. If it fits, we are done. If not, find the next 9203 instruction sequence that fits. */ 9204 9205 frag_offset = fragP->fr_opcode - fragP->fr_literal; 9206 istack_init (&istack); 9207 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, 9208 min_steps, stretch); 9209 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); 9210 9211 fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; 9212 9213 /* Figure out the number of bytes needed. */ 9214 num_literal_bytes = get_num_stack_literal_bytes (&istack); 9215 literal_diff 9216 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; 9217 num_text_bytes = get_num_stack_text_bytes (&istack); 9218 9219 if (from_wide_insn) 9220 { 9221 int first = 0; 9222 while (istack.insn[first].opcode == XTENSA_UNDEFINED) 9223 first++; 9224 9225 num_text_bytes += old_size; 9226 if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) 9227 num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); 9228 else 9229 { 9230 /* The first instruction in the relaxed sequence will go after 9231 the current wide instruction, and thus its symbolic immediates 9232 might not fit. */ 9233 9234 istack_init (&istack); 9235 num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, 9236 frag_offset + old_size, 9237 min_steps, stretch + old_size); 9238 gas_assert (num_steps >= min_steps && num_steps <= RELAX_IMMED_MAXSTEPS); 9239 9240 fragP->tc_frag_data.slot_subtypes[slot] 9241 = (int) RELAX_IMMED + num_steps; 9242 9243 num_literal_bytes = get_num_stack_literal_bytes (&istack); 9244 literal_diff 9245 = num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; 9246 9247 num_text_bytes = get_num_stack_text_bytes (&istack) + old_size; 9248 } 9249 } 9250 9251 total_text_diff = num_text_bytes - old_size; 9252 this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; 9253 9254 /* It MUST get larger. If not, we could get an infinite loop. */ 9255 gas_assert (num_text_bytes >= 0); 9256 gas_assert (literal_diff >= 0); 9257 gas_assert (total_text_diff >= 0); 9258 9259 fragP->tc_frag_data.text_expansion[slot] = total_text_diff; 9260 fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; 9261 gas_assert (fragP->tc_frag_data.text_expansion[slot] >= 0); 9262 gas_assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); 9263 9264 /* Find the associated expandable literal for this. */ 9265 if (literal_diff != 0) 9266 { 9267 fragS *lit_fragP = fragP->tc_frag_data.literal_frags[slot]; 9268 if (lit_fragP) 9269 { 9270 gas_assert (literal_diff == 4); 9271 lit_fragP->tc_frag_data.unreported_expansion += literal_diff; 9272 9273 /* We expect that the literal section state has NOT been 9274 modified yet. */ 9275 gas_assert (lit_fragP->fr_type == rs_machine_dependent 9276 && lit_fragP->fr_subtype == RELAX_LITERAL); 9277 lit_fragP->fr_subtype = RELAX_LITERAL_NR; 9278 9279 /* We need to mark this section for another iteration 9280 of relaxation. */ 9281 (*stretched_p)++; 9282 } 9283 } 9284 9285 if (negatable_branch && istack.ninsn > 1) 9286 update_next_frag_state (fragP); 9287 9288 return this_text_diff; 9289 } 9290 9291 9292 /* md_convert_frag Hook and Helper Functions. */ 9293 9294 static void convert_frag_align_next_opcode (fragS *); 9295 static void convert_frag_narrow (segT, fragS *, xtensa_format, int); 9296 static void convert_frag_fill_nop (fragS *); 9297 static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); 9298 9299 void 9300 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) 9301 { 9302 static xtensa_insnbuf vbuf = NULL; 9303 xtensa_isa isa = xtensa_default_isa; 9304 int slot; 9305 int num_slots; 9306 xtensa_format fmt; 9307 char *file_name; 9308 unsigned line; 9309 9310 as_where (&file_name, &line); 9311 new_logical_line (fragp->fr_file, fragp->fr_line); 9312 9313 switch (fragp->fr_subtype) 9314 { 9315 case RELAX_ALIGN_NEXT_OPCODE: 9316 /* Always convert. */ 9317 convert_frag_align_next_opcode (fragp); 9318 break; 9319 9320 case RELAX_DESIRE_ALIGN: 9321 /* Do nothing. If not aligned already, too bad. */ 9322 break; 9323 9324 case RELAX_LITERAL: 9325 case RELAX_LITERAL_FINAL: 9326 break; 9327 9328 case RELAX_SLOTS: 9329 if (vbuf == NULL) 9330 vbuf = xtensa_insnbuf_alloc (isa); 9331 9332 xtensa_insnbuf_from_chars 9333 (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); 9334 fmt = xtensa_format_decode (isa, vbuf); 9335 num_slots = xtensa_format_num_slots (isa, fmt); 9336 9337 for (slot = 0; slot < num_slots; slot++) 9338 { 9339 switch (fragp->tc_frag_data.slot_subtypes[slot]) 9340 { 9341 case RELAX_NARROW: 9342 convert_frag_narrow (sec, fragp, fmt, slot); 9343 break; 9344 9345 case RELAX_IMMED: 9346 case RELAX_IMMED_STEP1: 9347 case RELAX_IMMED_STEP2: 9348 case RELAX_IMMED_STEP3: 9349 /* Place the immediate. */ 9350 convert_frag_immed 9351 (sec, fragp, 9352 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, 9353 fmt, slot); 9354 break; 9355 9356 default: 9357 /* This is OK because some slots could have 9358 relaxations and others have none. */ 9359 break; 9360 } 9361 } 9362 break; 9363 9364 case RELAX_UNREACHABLE: 9365 memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); 9366 fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; 9367 fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; 9368 frag_wane (fragp); 9369 break; 9370 9371 case RELAX_MAYBE_UNREACHABLE: 9372 case RELAX_MAYBE_DESIRE_ALIGN: 9373 frag_wane (fragp); 9374 break; 9375 9376 case RELAX_FILL_NOP: 9377 convert_frag_fill_nop (fragp); 9378 break; 9379 9380 case RELAX_LITERAL_NR: 9381 if (use_literal_section) 9382 { 9383 /* This should have been handled during relaxation. When 9384 relaxing a code segment, literals sometimes need to be 9385 added to the corresponding literal segment. If that 9386 literal segment has already been relaxed, then we end up 9387 in this situation. Marking the literal segments as data 9388 would make this happen less often (since GAS always relaxes 9389 code before data), but we could still get into trouble if 9390 there are instructions in a segment that is not marked as 9391 containing code. Until we can implement a better solution, 9392 cheat and adjust the addresses of all the following frags. 9393 This could break subsequent alignments, but the linker's 9394 literal coalescing will do that anyway. */ 9395 9396 fragS *f; 9397 fragp->fr_subtype = RELAX_LITERAL_FINAL; 9398 gas_assert (fragp->tc_frag_data.unreported_expansion == 4); 9399 memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); 9400 fragp->fr_var -= 4; 9401 fragp->fr_fix += 4; 9402 for (f = fragp->fr_next; f; f = f->fr_next) 9403 f->fr_address += 4; 9404 } 9405 else 9406 as_bad (_("invalid relaxation fragment result")); 9407 break; 9408 } 9409 9410 fragp->fr_var = 0; 9411 new_logical_line (file_name, line); 9412 } 9413 9414 9415 static void 9416 convert_frag_align_next_opcode (fragS *fragp) 9417 { 9418 char *nop_buf; /* Location for Writing. */ 9419 bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; 9420 addressT aligned_address; 9421 offsetT fill_size; 9422 int nop, nop_count; 9423 9424 aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + 9425 fragp->fr_fix); 9426 fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); 9427 nop_count = get_text_align_nop_count (fill_size, use_no_density); 9428 nop_buf = fragp->fr_literal + fragp->fr_fix; 9429 9430 for (nop = 0; nop < nop_count; nop++) 9431 { 9432 int nop_size; 9433 nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); 9434 9435 assemble_nop (nop_size, nop_buf); 9436 nop_buf += nop_size; 9437 } 9438 9439 fragp->fr_fix += fill_size; 9440 fragp->fr_var -= fill_size; 9441 } 9442 9443 9444 static void 9445 convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) 9446 { 9447 TInsn tinsn, single_target; 9448 int size, old_size, diff; 9449 offsetT frag_offset; 9450 9451 gas_assert (slot == 0); 9452 tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); 9453 9454 if (fragP->tc_frag_data.is_aligning_branch == 1) 9455 { 9456 gas_assert (fragP->tc_frag_data.text_expansion[0] == 1 9457 || fragP->tc_frag_data.text_expansion[0] == 0); 9458 convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], 9459 fmt, slot); 9460 return; 9461 } 9462 9463 if (fragP->tc_frag_data.text_expansion[0] == 0) 9464 { 9465 /* No conversion. */ 9466 fragP->fr_var = 0; 9467 return; 9468 } 9469 9470 gas_assert (fragP->fr_opcode != NULL); 9471 9472 /* Frags in this relaxation state should only contain 9473 single instruction bundles. */ 9474 tinsn_immed_from_frag (&tinsn, fragP, 0); 9475 9476 /* Just convert it to a wide form.... */ 9477 size = 0; 9478 old_size = xg_get_single_size (tinsn.opcode); 9479 9480 tinsn_init (&single_target); 9481 frag_offset = fragP->fr_opcode - fragP->fr_literal; 9482 9483 if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) 9484 { 9485 as_bad (_("unable to widen instruction")); 9486 return; 9487 } 9488 9489 size = xg_get_single_size (single_target.opcode); 9490 xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, 9491 frag_offset, TRUE); 9492 9493 diff = size - old_size; 9494 gas_assert (diff >= 0); 9495 gas_assert (diff <= fragP->fr_var); 9496 fragP->fr_var -= diff; 9497 fragP->fr_fix += diff; 9498 9499 /* clean it up */ 9500 fragP->fr_var = 0; 9501 } 9502 9503 9504 static void 9505 convert_frag_fill_nop (fragS *fragP) 9506 { 9507 char *loc = &fragP->fr_literal[fragP->fr_fix]; 9508 int size = fragP->tc_frag_data.text_expansion[0]; 9509 gas_assert ((unsigned) size == (fragP->fr_next->fr_address 9510 - fragP->fr_address - fragP->fr_fix)); 9511 if (size == 0) 9512 { 9513 /* No conversion. */ 9514 fragP->fr_var = 0; 9515 return; 9516 } 9517 assemble_nop (size, loc); 9518 fragP->tc_frag_data.is_insn = TRUE; 9519 fragP->fr_var -= size; 9520 fragP->fr_fix += size; 9521 frag_wane (fragP); 9522 } 9523 9524 9525 static fixS *fix_new_exp_in_seg 9526 (segT, subsegT, fragS *, int, int, expressionS *, int, 9527 bfd_reloc_code_real_type); 9528 static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); 9529 9530 static void 9531 convert_frag_immed (segT segP, 9532 fragS *fragP, 9533 int min_steps, 9534 xtensa_format fmt, 9535 int slot) 9536 { 9537 char *immed_instr = fragP->fr_opcode; 9538 TInsn orig_tinsn; 9539 bfd_boolean expanded = FALSE; 9540 bfd_boolean branch_jmp_to_next = FALSE; 9541 char *fr_opcode = fragP->fr_opcode; 9542 xtensa_isa isa = xtensa_default_isa; 9543 bfd_boolean from_wide_insn = FALSE; 9544 int bytes; 9545 bfd_boolean is_loop; 9546 9547 gas_assert (fr_opcode != NULL); 9548 9549 xg_clear_vinsn (&cur_vinsn); 9550 9551 vinsn_from_chars (&cur_vinsn, fr_opcode); 9552 if (cur_vinsn.num_slots > 1) 9553 from_wide_insn = TRUE; 9554 9555 orig_tinsn = cur_vinsn.slots[slot]; 9556 tinsn_immed_from_frag (&orig_tinsn, fragP, slot); 9557 9558 is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; 9559 9560 if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) 9561 branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); 9562 9563 if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) 9564 { 9565 /* Conversion just inserts a NOP and marks the fix as completed. */ 9566 bytes = xtensa_format_length (isa, fmt); 9567 if (bytes >= 4) 9568 { 9569 cur_vinsn.slots[slot].opcode = 9570 xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); 9571 cur_vinsn.slots[slot].ntok = 0; 9572 } 9573 else 9574 { 9575 bytes += fragP->tc_frag_data.text_expansion[0]; 9576 gas_assert (bytes == 2 || bytes == 3); 9577 build_nop (&cur_vinsn.slots[0], bytes); 9578 fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; 9579 } 9580 vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); 9581 xtensa_insnbuf_to_chars 9582 (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); 9583 fragP->fr_var = 0; 9584 } 9585 else 9586 { 9587 /* Here is the fun stuff: Get the immediate field from this 9588 instruction. If it fits, we're done. If not, find the next 9589 instruction sequence that fits. */ 9590 9591 IStack istack; 9592 int i; 9593 symbolS *lit_sym = NULL; 9594 int total_size = 0; 9595 int target_offset = 0; 9596 int old_size; 9597 int diff; 9598 symbolS *gen_label = NULL; 9599 offsetT frag_offset; 9600 bfd_boolean first = TRUE; 9601 9602 /* It does not fit. Find something that does and 9603 convert immediately. */ 9604 frag_offset = fr_opcode - fragP->fr_literal; 9605 istack_init (&istack); 9606 xg_assembly_relax (&istack, &orig_tinsn, 9607 segP, fragP, frag_offset, min_steps, 0); 9608 9609 old_size = xtensa_format_length (isa, fmt); 9610 9611 /* Assemble this right inline. */ 9612 9613 /* First, create the mapping from a label name to the REAL label. */ 9614 target_offset = 0; 9615 for (i = 0; i < istack.ninsn; i++) 9616 { 9617 TInsn *tinsn = &istack.insn[i]; 9618 fragS *lit_frag; 9619 9620 switch (tinsn->insn_type) 9621 { 9622 case ITYPE_LITERAL: 9623 if (lit_sym != NULL) 9624 as_bad (_("multiple literals in expansion")); 9625 /* First find the appropriate space in the literal pool. */ 9626 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 9627 if (lit_frag == NULL) 9628 as_bad (_("no registered fragment for literal")); 9629 if (tinsn->ntok != 1) 9630 as_bad (_("number of literal tokens != 1")); 9631 9632 /* Set the literal symbol and add a fixup. */ 9633 lit_sym = lit_frag->fr_symbol; 9634 break; 9635 9636 case ITYPE_LABEL: 9637 if (align_targets && !is_loop) 9638 { 9639 fragS *unreach = fragP->fr_next; 9640 while (!(unreach->fr_type == rs_machine_dependent 9641 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 9642 || unreach->fr_subtype == RELAX_UNREACHABLE))) 9643 { 9644 unreach = unreach->fr_next; 9645 } 9646 9647 gas_assert (unreach->fr_type == rs_machine_dependent 9648 && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE 9649 || unreach->fr_subtype == RELAX_UNREACHABLE)); 9650 9651 target_offset += unreach->tc_frag_data.text_expansion[0]; 9652 } 9653 gas_assert (gen_label == NULL); 9654 gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, 9655 fr_opcode - fragP->fr_literal 9656 + target_offset, fragP); 9657 break; 9658 9659 case ITYPE_INSN: 9660 if (first && from_wide_insn) 9661 { 9662 target_offset += xtensa_format_length (isa, fmt); 9663 first = FALSE; 9664 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9665 target_offset += xg_get_single_size (tinsn->opcode); 9666 } 9667 else 9668 target_offset += xg_get_single_size (tinsn->opcode); 9669 break; 9670 } 9671 } 9672 9673 total_size = 0; 9674 first = TRUE; 9675 for (i = 0; i < istack.ninsn; i++) 9676 { 9677 TInsn *tinsn = &istack.insn[i]; 9678 fragS *lit_frag; 9679 int size; 9680 segT target_seg; 9681 bfd_reloc_code_real_type reloc_type; 9682 9683 switch (tinsn->insn_type) 9684 { 9685 case ITYPE_LITERAL: 9686 lit_frag = fragP->tc_frag_data.literal_frags[slot]; 9687 /* Already checked. */ 9688 gas_assert (lit_frag != NULL); 9689 gas_assert (lit_sym != NULL); 9690 gas_assert (tinsn->ntok == 1); 9691 /* Add a fixup. */ 9692 target_seg = S_GET_SEGMENT (lit_sym); 9693 gas_assert (target_seg); 9694 reloc_type = map_operator_to_reloc (tinsn->tok[0].X_op, TRUE); 9695 fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, 9696 &tinsn->tok[0], FALSE, reloc_type); 9697 break; 9698 9699 case ITYPE_LABEL: 9700 break; 9701 9702 case ITYPE_INSN: 9703 xg_resolve_labels (tinsn, gen_label); 9704 xg_resolve_literals (tinsn, lit_sym); 9705 if (from_wide_insn && first) 9706 { 9707 first = FALSE; 9708 if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9709 { 9710 cur_vinsn.slots[slot] = *tinsn; 9711 } 9712 else 9713 { 9714 cur_vinsn.slots[slot].opcode = 9715 xtensa_format_slot_nop_opcode (isa, fmt, slot); 9716 cur_vinsn.slots[slot].ntok = 0; 9717 } 9718 vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); 9719 xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, 9720 (unsigned char *) immed_instr, 0); 9721 fragP->tc_frag_data.is_insn = TRUE; 9722 size = xtensa_format_length (isa, fmt); 9723 if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) 9724 { 9725 xg_emit_insn_to_buf 9726 (tinsn, immed_instr + size, fragP, 9727 immed_instr - fragP->fr_literal + size, TRUE); 9728 size += xg_get_single_size (tinsn->opcode); 9729 } 9730 } 9731 else 9732 { 9733 size = xg_get_single_size (tinsn->opcode); 9734 xg_emit_insn_to_buf (tinsn, immed_instr, fragP, 9735 immed_instr - fragP->fr_literal, TRUE); 9736 } 9737 immed_instr += size; 9738 total_size += size; 9739 break; 9740 } 9741 } 9742 9743 diff = total_size - old_size; 9744 gas_assert (diff >= 0); 9745 if (diff != 0) 9746 expanded = TRUE; 9747 gas_assert (diff <= fragP->fr_var); 9748 fragP->fr_var -= diff; 9749 fragP->fr_fix += diff; 9750 } 9751 9752 /* Check for undefined immediates in LOOP instructions. */ 9753 if (is_loop) 9754 { 9755 symbolS *sym; 9756 sym = orig_tinsn.tok[1].X_add_symbol; 9757 if (sym != NULL && !S_IS_DEFINED (sym)) 9758 { 9759 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 9760 return; 9761 } 9762 sym = orig_tinsn.tok[1].X_op_symbol; 9763 if (sym != NULL && !S_IS_DEFINED (sym)) 9764 { 9765 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); 9766 return; 9767 } 9768 } 9769 9770 if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) 9771 convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); 9772 9773 if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) 9774 { 9775 /* Add an expansion note on the expanded instruction. */ 9776 fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, 9777 &orig_tinsn.tok[0], TRUE, 9778 BFD_RELOC_XTENSA_ASM_EXPAND); 9779 } 9780 } 9781 9782 9783 /* Add a new fix expression into the desired segment. We have to 9784 switch to that segment to do this. */ 9785 9786 static fixS * 9787 fix_new_exp_in_seg (segT new_seg, 9788 subsegT new_subseg, 9789 fragS *frag, 9790 int where, 9791 int size, 9792 expressionS *exp, 9793 int pcrel, 9794 bfd_reloc_code_real_type r_type) 9795 { 9796 fixS *new_fix; 9797 segT seg = now_seg; 9798 subsegT subseg = now_subseg; 9799 9800 gas_assert (new_seg != 0); 9801 subseg_set (new_seg, new_subseg); 9802 9803 new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); 9804 subseg_set (seg, subseg); 9805 return new_fix; 9806 } 9807 9808 9809 /* Relax a loop instruction so that it can span loop >256 bytes. 9810 9811 loop as, .L1 9812 .L0: 9813 rsr as, LEND 9814 wsr as, LBEG 9815 addi as, as, lo8 (label-.L1) 9816 addmi as, as, mid8 (label-.L1) 9817 wsr as, LEND 9818 isync 9819 rsr as, LCOUNT 9820 addi as, as, 1 9821 .L1: 9822 <<body>> 9823 label: 9824 */ 9825 9826 static void 9827 convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) 9828 { 9829 TInsn loop_insn; 9830 TInsn addi_insn; 9831 TInsn addmi_insn; 9832 unsigned long target; 9833 static xtensa_insnbuf insnbuf = NULL; 9834 unsigned int loop_length, loop_length_hi, loop_length_lo; 9835 xtensa_isa isa = xtensa_default_isa; 9836 addressT loop_offset; 9837 addressT addi_offset = 9; 9838 addressT addmi_offset = 12; 9839 fragS *next_fragP; 9840 int target_count; 9841 9842 if (!insnbuf) 9843 insnbuf = xtensa_insnbuf_alloc (isa); 9844 9845 /* Get the loop offset. */ 9846 loop_offset = get_expanded_loop_offset (tinsn->opcode); 9847 9848 /* Validate that there really is a LOOP at the loop_offset. Because 9849 loops are not bundleable, we can assume that the instruction will be 9850 in slot 0. */ 9851 tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); 9852 tinsn_immed_from_frag (&loop_insn, fragP, 0); 9853 9854 gas_assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); 9855 addi_offset += loop_offset; 9856 addmi_offset += loop_offset; 9857 9858 gas_assert (tinsn->ntok == 2); 9859 if (tinsn->tok[1].X_op == O_constant) 9860 target = tinsn->tok[1].X_add_number; 9861 else if (tinsn->tok[1].X_op == O_symbol) 9862 { 9863 /* Find the fragment. */ 9864 symbolS *sym = tinsn->tok[1].X_add_symbol; 9865 gas_assert (S_GET_SEGMENT (sym) == segP 9866 || S_GET_SEGMENT (sym) == absolute_section); 9867 target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); 9868 } 9869 else 9870 { 9871 as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); 9872 target = 0; 9873 } 9874 9875 loop_length = target - (fragP->fr_address + fragP->fr_fix); 9876 loop_length_hi = loop_length & ~0x0ff; 9877 loop_length_lo = loop_length & 0x0ff; 9878 if (loop_length_lo >= 128) 9879 { 9880 loop_length_lo -= 256; 9881 loop_length_hi += 256; 9882 } 9883 9884 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most 9885 32512. If the loop is larger than that, then we just fail. */ 9886 if (loop_length_hi > 32512) 9887 as_bad_where (fragP->fr_file, fragP->fr_line, 9888 _("loop too long for LOOP instruction")); 9889 9890 tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); 9891 gas_assert (addi_insn.opcode == xtensa_addi_opcode); 9892 9893 tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); 9894 gas_assert (addmi_insn.opcode == xtensa_addmi_opcode); 9895 9896 set_expr_const (&addi_insn.tok[2], loop_length_lo); 9897 tinsn_to_insnbuf (&addi_insn, insnbuf); 9898 9899 fragP->tc_frag_data.is_insn = TRUE; 9900 xtensa_insnbuf_to_chars 9901 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); 9902 9903 set_expr_const (&addmi_insn.tok[2], loop_length_hi); 9904 tinsn_to_insnbuf (&addmi_insn, insnbuf); 9905 xtensa_insnbuf_to_chars 9906 (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); 9907 9908 /* Walk through all of the frags from here to the loop end 9909 and mark them as no_transform to keep them from being modified 9910 by the linker. If we ever have a relocation for the 9911 addi/addmi of the difference of two symbols we can remove this. */ 9912 9913 target_count = 0; 9914 for (next_fragP = fragP; next_fragP != NULL; 9915 next_fragP = next_fragP->fr_next) 9916 { 9917 next_fragP->tc_frag_data.is_no_transform = TRUE; 9918 if (next_fragP->tc_frag_data.is_loop_target) 9919 target_count++; 9920 if (target_count == 2) 9921 break; 9922 } 9923 } 9924 9925 9926 /* A map that keeps information on a per-subsegment basis. This is 9927 maintained during initial assembly, but is invalid once the 9928 subsegments are smashed together. I.E., it cannot be used during 9929 the relaxation. */ 9930 9931 typedef struct subseg_map_struct 9932 { 9933 /* the key */ 9934 segT seg; 9935 subsegT subseg; 9936 9937 /* the data */ 9938 unsigned flags; 9939 float total_freq; /* fall-through + branch target frequency */ 9940 float target_freq; /* branch target frequency alone */ 9941 9942 struct subseg_map_struct *next; 9943 } subseg_map; 9944 9945 9946 static subseg_map *sseg_map = NULL; 9947 9948 static subseg_map * 9949 get_subseg_info (segT seg, subsegT subseg) 9950 { 9951 subseg_map *subseg_e; 9952 9953 for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) 9954 { 9955 if (seg == subseg_e->seg && subseg == subseg_e->subseg) 9956 break; 9957 } 9958 return subseg_e; 9959 } 9960 9961 9962 static subseg_map * 9963 add_subseg_info (segT seg, subsegT subseg) 9964 { 9965 subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); 9966 memset (subseg_e, 0, sizeof (subseg_map)); 9967 subseg_e->seg = seg; 9968 subseg_e->subseg = subseg; 9969 subseg_e->flags = 0; 9970 /* Start off considering every branch target very important. */ 9971 subseg_e->target_freq = 1.0; 9972 subseg_e->total_freq = 1.0; 9973 subseg_e->next = sseg_map; 9974 sseg_map = subseg_e; 9975 return subseg_e; 9976 } 9977 9978 9979 static unsigned 9980 get_last_insn_flags (segT seg, subsegT subseg) 9981 { 9982 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9983 if (subseg_e) 9984 return subseg_e->flags; 9985 return 0; 9986 } 9987 9988 9989 static void 9990 set_last_insn_flags (segT seg, 9991 subsegT subseg, 9992 unsigned fl, 9993 bfd_boolean val) 9994 { 9995 subseg_map *subseg_e = get_subseg_info (seg, subseg); 9996 if (! subseg_e) 9997 subseg_e = add_subseg_info (seg, subseg); 9998 if (val) 9999 subseg_e->flags |= fl; 10000 else 10001 subseg_e->flags &= ~fl; 10002 } 10003 10004 10005 static float 10006 get_subseg_total_freq (segT seg, subsegT subseg) 10007 { 10008 subseg_map *subseg_e = get_subseg_info (seg, subseg); 10009 if (subseg_e) 10010 return subseg_e->total_freq; 10011 return 1.0; 10012 } 10013 10014 10015 static float 10016 get_subseg_target_freq (segT seg, subsegT subseg) 10017 { 10018 subseg_map *subseg_e = get_subseg_info (seg, subseg); 10019 if (subseg_e) 10020 return subseg_e->target_freq; 10021 return 1.0; 10022 } 10023 10024 10025 static void 10026 set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) 10027 { 10028 subseg_map *subseg_e = get_subseg_info (seg, subseg); 10029 if (! subseg_e) 10030 subseg_e = add_subseg_info (seg, subseg); 10031 subseg_e->total_freq = total_f; 10032 subseg_e->target_freq = target_f; 10033 } 10034 10035 10036 /* Segment Lists and emit_state Stuff. */ 10037 10038 static void 10039 xtensa_move_seg_list_to_beginning (seg_list *head) 10040 { 10041 head = head->next; 10042 while (head) 10043 { 10044 segT literal_section = head->seg; 10045 10046 /* Move the literal section to the front of the section list. */ 10047 gas_assert (literal_section); 10048 if (literal_section != stdoutput->sections) 10049 { 10050 bfd_section_list_remove (stdoutput, literal_section); 10051 bfd_section_list_prepend (stdoutput, literal_section); 10052 } 10053 head = head->next; 10054 } 10055 } 10056 10057 10058 static void mark_literal_frags (seg_list *); 10059 10060 static void 10061 xtensa_move_literals (void) 10062 { 10063 seg_list *segment; 10064 frchainS *frchain_from, *frchain_to; 10065 fragS *search_frag, *next_frag, *literal_pool, *insert_after; 10066 fragS **frag_splice; 10067 emit_state state; 10068 segT dest_seg; 10069 fixS *fix, *next_fix, **fix_splice; 10070 sym_list *lit; 10071 10072 mark_literal_frags (literal_head->next); 10073 10074 if (use_literal_section) 10075 return; 10076 10077 for (segment = literal_head->next; segment; segment = segment->next) 10078 { 10079 /* Keep the literals for .init and .fini in separate sections. */ 10080 if (!strcmp (segment_name (segment->seg), INIT_SECTION_NAME) 10081 || !strcmp (segment_name (segment->seg), FINI_SECTION_NAME)) 10082 continue; 10083 10084 frchain_from = seg_info (segment->seg)->frchainP; 10085 search_frag = frchain_from->frch_root; 10086 literal_pool = NULL; 10087 frchain_to = NULL; 10088 frag_splice = &(frchain_from->frch_root); 10089 10090 while (!search_frag->tc_frag_data.literal_frag) 10091 { 10092 gas_assert (search_frag->fr_fix == 0 10093 || search_frag->fr_type == rs_align); 10094 search_frag = search_frag->fr_next; 10095 } 10096 10097 gas_assert (search_frag->tc_frag_data.literal_frag->fr_subtype 10098 == RELAX_LITERAL_POOL_BEGIN); 10099 xtensa_switch_section_emit_state (&state, segment->seg, 0); 10100 10101 /* Make sure that all the frags in this series are closed, and 10102 that there is at least one left over of zero-size. This 10103 prevents us from making a segment with an frchain without any 10104 frags in it. */ 10105 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10106 xtensa_set_frag_assembly_state (frag_now); 10107 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10108 xtensa_set_frag_assembly_state (frag_now); 10109 10110 while (search_frag != frag_now) 10111 { 10112 next_frag = search_frag->fr_next; 10113 10114 /* First, move the frag out of the literal section and 10115 to the appropriate place. */ 10116 if (search_frag->tc_frag_data.literal_frag) 10117 { 10118 literal_pool = search_frag->tc_frag_data.literal_frag; 10119 gas_assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); 10120 frchain_to = literal_pool->tc_frag_data.lit_frchain; 10121 gas_assert (frchain_to); 10122 } 10123 insert_after = literal_pool->tc_frag_data.literal_frag; 10124 dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; 10125 10126 *frag_splice = next_frag; 10127 search_frag->fr_next = insert_after->fr_next; 10128 insert_after->fr_next = search_frag; 10129 search_frag->tc_frag_data.lit_seg = dest_seg; 10130 literal_pool->tc_frag_data.literal_frag = search_frag; 10131 10132 /* Now move any fixups associated with this frag to the 10133 right section. */ 10134 fix = frchain_from->fix_root; 10135 fix_splice = &(frchain_from->fix_root); 10136 while (fix) 10137 { 10138 next_fix = fix->fx_next; 10139 if (fix->fx_frag == search_frag) 10140 { 10141 *fix_splice = next_fix; 10142 fix->fx_next = frchain_to->fix_root; 10143 frchain_to->fix_root = fix; 10144 if (frchain_to->fix_tail == NULL) 10145 frchain_to->fix_tail = fix; 10146 } 10147 else 10148 fix_splice = &(fix->fx_next); 10149 fix = next_fix; 10150 } 10151 search_frag = next_frag; 10152 } 10153 10154 if (frchain_from->fix_root != NULL) 10155 { 10156 frchain_from = seg_info (segment->seg)->frchainP; 10157 as_warn (_("fixes not all moved from %s"), segment->seg->name); 10158 10159 gas_assert (frchain_from->fix_root == NULL); 10160 } 10161 frchain_from->fix_tail = NULL; 10162 xtensa_restore_emit_state (&state); 10163 } 10164 10165 /* Now fix up the SEGMENT value for all the literal symbols. */ 10166 for (lit = literal_syms; lit; lit = lit->next) 10167 { 10168 symbolS *lit_sym = lit->sym; 10169 segT dseg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; 10170 if (dseg) 10171 S_SET_SEGMENT (lit_sym, dseg); 10172 } 10173 } 10174 10175 10176 /* Walk over all the frags for segments in a list and mark them as 10177 containing literals. As clunky as this is, we can't rely on frag_var 10178 and frag_variant to get called in all situations. */ 10179 10180 static void 10181 mark_literal_frags (seg_list *segment) 10182 { 10183 frchainS *frchain_from; 10184 fragS *search_frag; 10185 10186 while (segment) 10187 { 10188 frchain_from = seg_info (segment->seg)->frchainP; 10189 search_frag = frchain_from->frch_root; 10190 while (search_frag) 10191 { 10192 search_frag->tc_frag_data.is_literal = TRUE; 10193 search_frag = search_frag->fr_next; 10194 } 10195 segment = segment->next; 10196 } 10197 } 10198 10199 10200 static void 10201 xtensa_reorder_seg_list (seg_list *head, segT after) 10202 { 10203 /* Move all of the sections in the section list to come 10204 after "after" in the gnu segment list. */ 10205 10206 head = head->next; 10207 while (head) 10208 { 10209 segT literal_section = head->seg; 10210 10211 /* Move the literal section after "after". */ 10212 gas_assert (literal_section); 10213 if (literal_section != after) 10214 { 10215 bfd_section_list_remove (stdoutput, literal_section); 10216 bfd_section_list_insert_after (stdoutput, after, literal_section); 10217 } 10218 10219 head = head->next; 10220 } 10221 } 10222 10223 10224 /* Push all the literal segments to the end of the gnu list. */ 10225 10226 static void 10227 xtensa_reorder_segments (void) 10228 { 10229 segT sec; 10230 segT last_sec = 0; 10231 int old_count = 0; 10232 int new_count = 0; 10233 10234 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 10235 { 10236 last_sec = sec; 10237 old_count++; 10238 } 10239 10240 /* Now that we have the last section, push all the literal 10241 sections to the end. */ 10242 xtensa_reorder_seg_list (literal_head, last_sec); 10243 10244 /* Now perform the final error check. */ 10245 for (sec = stdoutput->sections; sec != NULL; sec = sec->next) 10246 new_count++; 10247 gas_assert (new_count == old_count); 10248 } 10249 10250 10251 /* Change the emit state (seg, subseg, and frag related stuff) to the 10252 correct location. Return a emit_state which can be passed to 10253 xtensa_restore_emit_state to return to current fragment. */ 10254 10255 static void 10256 xtensa_switch_to_literal_fragment (emit_state *result) 10257 { 10258 if (directive_state[directive_absolute_literals]) 10259 { 10260 segT lit4_seg = cache_literal_section (TRUE); 10261 xtensa_switch_section_emit_state (result, lit4_seg, 0); 10262 } 10263 else 10264 xtensa_switch_to_non_abs_literal_fragment (result); 10265 10266 /* Do a 4-byte align here. */ 10267 frag_align (2, 0, 0); 10268 record_alignment (now_seg, 2); 10269 } 10270 10271 10272 static void 10273 xtensa_switch_to_non_abs_literal_fragment (emit_state *result) 10274 { 10275 static bfd_boolean recursive = FALSE; 10276 fragS *pool_location = get_literal_pool_location (now_seg); 10277 segT lit_seg; 10278 bfd_boolean is_init = 10279 (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); 10280 bfd_boolean is_fini = 10281 (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); 10282 10283 if (pool_location == NULL 10284 && !use_literal_section 10285 && !recursive 10286 && !is_init && ! is_fini) 10287 { 10288 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); 10289 10290 /* When we mark a literal pool location, we want to put a frag in 10291 the literal pool that points to it. But to do that, we want to 10292 switch_to_literal_fragment. But literal sections don't have 10293 literal pools, so their location is always null, so we would 10294 recurse forever. This is kind of hacky, but it works. */ 10295 10296 recursive = TRUE; 10297 xtensa_mark_literal_pool_location (); 10298 recursive = FALSE; 10299 } 10300 10301 lit_seg = cache_literal_section (FALSE); 10302 xtensa_switch_section_emit_state (result, lit_seg, 0); 10303 10304 if (!use_literal_section 10305 && !is_init && !is_fini 10306 && get_literal_pool_location (now_seg) != pool_location) 10307 { 10308 /* Close whatever frag is there. */ 10309 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10310 xtensa_set_frag_assembly_state (frag_now); 10311 frag_now->tc_frag_data.literal_frag = pool_location; 10312 frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); 10313 xtensa_set_frag_assembly_state (frag_now); 10314 } 10315 } 10316 10317 10318 /* Call this function before emitting data into the literal section. 10319 This is a helper function for xtensa_switch_to_literal_fragment. 10320 This is similar to a .section new_now_seg subseg. */ 10321 10322 static void 10323 xtensa_switch_section_emit_state (emit_state *state, 10324 segT new_now_seg, 10325 subsegT new_now_subseg) 10326 { 10327 state->name = now_seg->name; 10328 state->now_seg = now_seg; 10329 state->now_subseg = now_subseg; 10330 state->generating_literals = generating_literals; 10331 generating_literals++; 10332 subseg_set (new_now_seg, new_now_subseg); 10333 } 10334 10335 10336 /* Use to restore the emitting into the normal place. */ 10337 10338 static void 10339 xtensa_restore_emit_state (emit_state *state) 10340 { 10341 generating_literals = state->generating_literals; 10342 subseg_set (state->now_seg, state->now_subseg); 10343 } 10344 10345 10346 /* Predicate function used to look up a section in a particular group. */ 10347 10348 static bfd_boolean 10349 match_section_group (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf) 10350 { 10351 const char *gname = inf; 10352 const char *group_name = elf_group_name (sec); 10353 10354 return (group_name == gname 10355 || (group_name != NULL 10356 && gname != NULL 10357 && strcmp (group_name, gname) == 0)); 10358 } 10359 10360 10361 /* Get the literal section to be used for the current text section. 10362 The result may be cached in the default_lit_sections structure. */ 10363 10364 static segT 10365 cache_literal_section (bfd_boolean use_abs_literals) 10366 { 10367 const char *text_name, *group_name = 0; 10368 char *base_name, *name, *suffix; 10369 segT *pcached; 10370 segT seg, current_section; 10371 int current_subsec; 10372 bfd_boolean linkonce = FALSE; 10373 10374 /* Save the current section/subsection. */ 10375 current_section = now_seg; 10376 current_subsec = now_subseg; 10377 10378 /* Clear the cached values if they are no longer valid. */ 10379 if (now_seg != default_lit_sections.current_text_seg) 10380 { 10381 default_lit_sections.current_text_seg = now_seg; 10382 default_lit_sections.lit_seg = NULL; 10383 default_lit_sections.lit4_seg = NULL; 10384 } 10385 10386 /* Check if the literal section is already cached. */ 10387 if (use_abs_literals) 10388 pcached = &default_lit_sections.lit4_seg; 10389 else 10390 pcached = &default_lit_sections.lit_seg; 10391 10392 if (*pcached) 10393 return *pcached; 10394 10395 text_name = default_lit_sections.lit_prefix; 10396 if (! text_name || ! *text_name) 10397 { 10398 text_name = segment_name (current_section); 10399 group_name = elf_group_name (current_section); 10400 linkonce = (current_section->flags & SEC_LINK_ONCE) != 0; 10401 } 10402 10403 base_name = use_abs_literals ? ".lit4" : ".literal"; 10404 if (group_name) 10405 { 10406 name = xmalloc (strlen (base_name) + strlen (group_name) + 2); 10407 sprintf (name, "%s.%s", base_name, group_name); 10408 } 10409 else if (strncmp (text_name, ".gnu.linkonce.", linkonce_len) == 0) 10410 { 10411 suffix = strchr (text_name + linkonce_len, '.'); 10412 10413 name = xmalloc (linkonce_len + strlen (base_name) + 1 10414 + (suffix ? strlen (suffix) : 0)); 10415 strcpy (name, ".gnu.linkonce"); 10416 strcat (name, base_name); 10417 if (suffix) 10418 strcat (name, suffix); 10419 linkonce = TRUE; 10420 } 10421 else 10422 { 10423 /* If the section name begins or ends with ".text", then replace 10424 that portion instead of appending an additional suffix. */ 10425 size_t len = strlen (text_name); 10426 if (len >= 5 10427 && (strcmp (text_name + len - 5, ".text") == 0 10428 || strncmp (text_name, ".text", 5) == 0)) 10429 len -= 5; 10430 10431 name = xmalloc (len + strlen (base_name) + 1); 10432 if (strncmp (text_name, ".text", 5) == 0) 10433 { 10434 strcpy (name, base_name); 10435 strcat (name, text_name + 5); 10436 } 10437 else 10438 { 10439 strcpy (name, text_name); 10440 strcpy (name + len, base_name); 10441 } 10442 } 10443 10444 /* Canonicalize section names to allow renaming literal sections. 10445 The group name, if any, came from the current text section and 10446 has already been canonicalized. */ 10447 name = tc_canonicalize_symbol_name (name); 10448 10449 seg = bfd_get_section_by_name_if (stdoutput, name, match_section_group, 10450 (void *) group_name); 10451 if (! seg) 10452 { 10453 flagword flags; 10454 10455 seg = subseg_force_new (name, 0); 10456 10457 if (! use_abs_literals) 10458 { 10459 /* Add the newly created literal segment to the list. */ 10460 seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); 10461 n->seg = seg; 10462 n->next = literal_head->next; 10463 literal_head->next = n; 10464 } 10465 10466 flags = (SEC_HAS_CONTENTS | SEC_READONLY | SEC_ALLOC | SEC_LOAD 10467 | (linkonce ? (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD) : 0) 10468 | (use_abs_literals ? SEC_DATA : SEC_CODE)); 10469 10470 elf_group_name (seg) = group_name; 10471 10472 bfd_set_section_flags (stdoutput, seg, flags); 10473 bfd_set_section_alignment (stdoutput, seg, 2); 10474 } 10475 10476 *pcached = seg; 10477 subseg_set (current_section, current_subsec); 10478 return seg; 10479 } 10480 10481 10482 /* Property Tables Stuff. */ 10483 10484 #define XTENSA_INSN_SEC_NAME ".xt.insn" 10485 #define XTENSA_LIT_SEC_NAME ".xt.lit" 10486 #define XTENSA_PROP_SEC_NAME ".xt.prop" 10487 10488 typedef bfd_boolean (*frag_predicate) (const fragS *); 10489 typedef void (*frag_flags_fn) (const fragS *, frag_flags *); 10490 10491 static bfd_boolean get_frag_is_literal (const fragS *); 10492 static void xtensa_create_property_segments 10493 (frag_predicate, frag_predicate, const char *, xt_section_type); 10494 static void xtensa_create_xproperty_segments 10495 (frag_flags_fn, const char *, xt_section_type); 10496 static bfd_boolean exclude_section_from_property_tables (segT); 10497 static bfd_boolean section_has_property (segT, frag_predicate); 10498 static bfd_boolean section_has_xproperty (segT, frag_flags_fn); 10499 static void add_xt_block_frags 10500 (segT, xtensa_block_info **, frag_predicate, frag_predicate); 10501 static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); 10502 static void xtensa_frag_flags_init (frag_flags *); 10503 static void get_frag_property_flags (const fragS *, frag_flags *); 10504 static flagword frag_flags_to_number (const frag_flags *); 10505 static void add_xt_prop_frags (segT, xtensa_block_info **, frag_flags_fn); 10506 10507 /* Set up property tables after relaxation. */ 10508 10509 void 10510 xtensa_post_relax_hook (void) 10511 { 10512 xtensa_move_seg_list_to_beginning (literal_head); 10513 10514 xtensa_find_unmarked_state_frags (); 10515 xtensa_mark_frags_for_org (); 10516 xtensa_mark_difference_of_two_symbols (); 10517 10518 xtensa_create_property_segments (get_frag_is_literal, 10519 NULL, 10520 XTENSA_LIT_SEC_NAME, 10521 xt_literal_sec); 10522 xtensa_create_xproperty_segments (get_frag_property_flags, 10523 XTENSA_PROP_SEC_NAME, 10524 xt_prop_sec); 10525 10526 if (warn_unaligned_branch_targets) 10527 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); 10528 bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); 10529 } 10530 10531 10532 /* This function is only meaningful after xtensa_move_literals. */ 10533 10534 static bfd_boolean 10535 get_frag_is_literal (const fragS *fragP) 10536 { 10537 gas_assert (fragP != NULL); 10538 return fragP->tc_frag_data.is_literal; 10539 } 10540 10541 10542 static void 10543 xtensa_create_property_segments (frag_predicate property_function, 10544 frag_predicate end_property_function, 10545 const char *section_name_base, 10546 xt_section_type sec_type) 10547 { 10548 segT *seclist; 10549 10550 /* Walk over all of the current segments. 10551 Walk over each fragment 10552 For each non-empty fragment, 10553 Build a property record (append where possible). */ 10554 10555 for (seclist = &stdoutput->sections; 10556 seclist && *seclist; 10557 seclist = &(*seclist)->next) 10558 { 10559 segT sec = *seclist; 10560 10561 if (exclude_section_from_property_tables (sec)) 10562 continue; 10563 10564 if (section_has_property (sec, property_function)) 10565 { 10566 segment_info_type *xt_seg_info; 10567 xtensa_block_info **xt_blocks; 10568 segT prop_sec = xtensa_make_property_section (sec, section_name_base); 10569 10570 prop_sec->output_section = prop_sec; 10571 subseg_set (prop_sec, 0); 10572 xt_seg_info = seg_info (prop_sec); 10573 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 10574 10575 /* Walk over all of the frchains here and add new sections. */ 10576 add_xt_block_frags (sec, xt_blocks, property_function, 10577 end_property_function); 10578 } 10579 } 10580 10581 /* Now we fill them out.... */ 10582 10583 for (seclist = &stdoutput->sections; 10584 seclist && *seclist; 10585 seclist = &(*seclist)->next) 10586 { 10587 segment_info_type *seginfo; 10588 xtensa_block_info *block; 10589 segT sec = *seclist; 10590 10591 seginfo = seg_info (sec); 10592 block = seginfo->tc_segment_info_data.blocks[sec_type]; 10593 10594 if (block) 10595 { 10596 xtensa_block_info *cur_block; 10597 int num_recs = 0; 10598 bfd_size_type rec_size; 10599 10600 for (cur_block = block; cur_block; cur_block = cur_block->next) 10601 num_recs++; 10602 10603 rec_size = num_recs * 8; 10604 bfd_set_section_size (stdoutput, sec, rec_size); 10605 10606 if (num_recs) 10607 { 10608 char *frag_data; 10609 int i; 10610 10611 subseg_set (sec, 0); 10612 frag_data = frag_more (rec_size); 10613 cur_block = block; 10614 for (i = 0; i < num_recs; i++) 10615 { 10616 fixS *fix; 10617 10618 /* Write the fixup. */ 10619 gas_assert (cur_block); 10620 fix = fix_new (frag_now, i * 8, 4, 10621 section_symbol (cur_block->sec), 10622 cur_block->offset, 10623 FALSE, BFD_RELOC_32); 10624 fix->fx_file = "<internal>"; 10625 fix->fx_line = 0; 10626 10627 /* Write the length. */ 10628 md_number_to_chars (&frag_data[4 + i * 8], 10629 cur_block->size, 4); 10630 cur_block = cur_block->next; 10631 } 10632 frag_wane (frag_now); 10633 frag_new (0); 10634 frag_wane (frag_now); 10635 } 10636 } 10637 } 10638 } 10639 10640 10641 static void 10642 xtensa_create_xproperty_segments (frag_flags_fn flag_fn, 10643 const char *section_name_base, 10644 xt_section_type sec_type) 10645 { 10646 segT *seclist; 10647 10648 /* Walk over all of the current segments. 10649 Walk over each fragment. 10650 For each fragment that has instructions, 10651 build an instruction record (append where possible). */ 10652 10653 for (seclist = &stdoutput->sections; 10654 seclist && *seclist; 10655 seclist = &(*seclist)->next) 10656 { 10657 segT sec = *seclist; 10658 10659 if (exclude_section_from_property_tables (sec)) 10660 continue; 10661 10662 if (section_has_xproperty (sec, flag_fn)) 10663 { 10664 segment_info_type *xt_seg_info; 10665 xtensa_block_info **xt_blocks; 10666 segT prop_sec = xtensa_make_property_section (sec, section_name_base); 10667 10668 prop_sec->output_section = prop_sec; 10669 subseg_set (prop_sec, 0); 10670 xt_seg_info = seg_info (prop_sec); 10671 xt_blocks = &xt_seg_info->tc_segment_info_data.blocks[sec_type]; 10672 10673 /* Walk over all of the frchains here and add new sections. */ 10674 add_xt_prop_frags (sec, xt_blocks, flag_fn); 10675 } 10676 } 10677 10678 /* Now we fill them out.... */ 10679 10680 for (seclist = &stdoutput->sections; 10681 seclist && *seclist; 10682 seclist = &(*seclist)->next) 10683 { 10684 segment_info_type *seginfo; 10685 xtensa_block_info *block; 10686 segT sec = *seclist; 10687 10688 seginfo = seg_info (sec); 10689 block = seginfo->tc_segment_info_data.blocks[sec_type]; 10690 10691 if (block) 10692 { 10693 xtensa_block_info *cur_block; 10694 int num_recs = 0; 10695 bfd_size_type rec_size; 10696 10697 for (cur_block = block; cur_block; cur_block = cur_block->next) 10698 num_recs++; 10699 10700 rec_size = num_recs * (8 + 4); 10701 bfd_set_section_size (stdoutput, sec, rec_size); 10702 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ 10703 10704 if (num_recs) 10705 { 10706 char *frag_data; 10707 int i; 10708 10709 subseg_set (sec, 0); 10710 frag_data = frag_more (rec_size); 10711 cur_block = block; 10712 for (i = 0; i < num_recs; i++) 10713 { 10714 fixS *fix; 10715 10716 /* Write the fixup. */ 10717 gas_assert (cur_block); 10718 fix = fix_new (frag_now, i * 12, 4, 10719 section_symbol (cur_block->sec), 10720 cur_block->offset, 10721 FALSE, BFD_RELOC_32); 10722 fix->fx_file = "<internal>"; 10723 fix->fx_line = 0; 10724 10725 /* Write the length. */ 10726 md_number_to_chars (&frag_data[4 + i * 12], 10727 cur_block->size, 4); 10728 md_number_to_chars (&frag_data[8 + i * 12], 10729 frag_flags_to_number (&cur_block->flags), 10730 sizeof (flagword)); 10731 cur_block = cur_block->next; 10732 } 10733 frag_wane (frag_now); 10734 frag_new (0); 10735 frag_wane (frag_now); 10736 } 10737 } 10738 } 10739 } 10740 10741 10742 static bfd_boolean 10743 exclude_section_from_property_tables (segT sec) 10744 { 10745 flagword flags = bfd_get_section_flags (stdoutput, sec); 10746 10747 /* Sections that don't contribute to the memory footprint are excluded. */ 10748 if ((flags & SEC_DEBUGGING) 10749 || !(flags & SEC_ALLOC) 10750 || (flags & SEC_MERGE)) 10751 return TRUE; 10752 10753 /* Linker cie and fde optimizations mess up property entries for 10754 eh_frame sections, but there is nothing inside them relevant to 10755 property tables anyway. */ 10756 if (strcmp (sec->name, ".eh_frame") == 0) 10757 return TRUE; 10758 10759 return FALSE; 10760 } 10761 10762 10763 static bfd_boolean 10764 section_has_property (segT sec, frag_predicate property_function) 10765 { 10766 segment_info_type *seginfo = seg_info (sec); 10767 fragS *fragP; 10768 10769 if (seginfo && seginfo->frchainP) 10770 { 10771 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 10772 { 10773 if (property_function (fragP) 10774 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 10775 return TRUE; 10776 } 10777 } 10778 return FALSE; 10779 } 10780 10781 10782 static bfd_boolean 10783 section_has_xproperty (segT sec, frag_flags_fn property_function) 10784 { 10785 segment_info_type *seginfo = seg_info (sec); 10786 fragS *fragP; 10787 10788 if (seginfo && seginfo->frchainP) 10789 { 10790 for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) 10791 { 10792 frag_flags prop_flags; 10793 property_function (fragP, &prop_flags); 10794 if (!xtensa_frag_flags_is_empty (&prop_flags)) 10795 return TRUE; 10796 } 10797 } 10798 return FALSE; 10799 } 10800 10801 10802 /* Two types of block sections exist right now: literal and insns. */ 10803 10804 static void 10805 add_xt_block_frags (segT sec, 10806 xtensa_block_info **xt_block, 10807 frag_predicate property_function, 10808 frag_predicate end_property_function) 10809 { 10810 fragS *fragP; 10811 10812 /* Build it if needed. */ 10813 while (*xt_block != NULL) 10814 xt_block = &(*xt_block)->next; 10815 /* We are either at NULL at the beginning or at the end. */ 10816 10817 /* Walk through the frags. */ 10818 if (seg_info (sec)->frchainP) 10819 { 10820 for (fragP = seg_info (sec)->frchainP->frch_root; 10821 fragP; 10822 fragP = fragP->fr_next) 10823 { 10824 if (property_function (fragP) 10825 && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) 10826 { 10827 if (*xt_block != NULL) 10828 { 10829 if ((*xt_block)->offset + (*xt_block)->size 10830 == fragP->fr_address) 10831 (*xt_block)->size += fragP->fr_fix; 10832 else 10833 xt_block = &((*xt_block)->next); 10834 } 10835 if (*xt_block == NULL) 10836 { 10837 xtensa_block_info *new_block = (xtensa_block_info *) 10838 xmalloc (sizeof (xtensa_block_info)); 10839 new_block->sec = sec; 10840 new_block->offset = fragP->fr_address; 10841 new_block->size = fragP->fr_fix; 10842 new_block->next = NULL; 10843 xtensa_frag_flags_init (&new_block->flags); 10844 *xt_block = new_block; 10845 } 10846 if (end_property_function 10847 && end_property_function (fragP)) 10848 { 10849 xt_block = &((*xt_block)->next); 10850 } 10851 } 10852 } 10853 } 10854 } 10855 10856 10857 /* Break the encapsulation of add_xt_prop_frags here. */ 10858 10859 static bfd_boolean 10860 xtensa_frag_flags_is_empty (const frag_flags *prop_flags) 10861 { 10862 if (prop_flags->is_literal 10863 || prop_flags->is_insn 10864 || prop_flags->is_data 10865 || prop_flags->is_unreachable) 10866 return FALSE; 10867 return TRUE; 10868 } 10869 10870 10871 static void 10872 xtensa_frag_flags_init (frag_flags *prop_flags) 10873 { 10874 memset (prop_flags, 0, sizeof (frag_flags)); 10875 } 10876 10877 10878 static void 10879 get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) 10880 { 10881 xtensa_frag_flags_init (prop_flags); 10882 if (fragP->tc_frag_data.is_literal) 10883 prop_flags->is_literal = TRUE; 10884 if (fragP->tc_frag_data.is_specific_opcode 10885 || fragP->tc_frag_data.is_no_transform) 10886 { 10887 prop_flags->is_no_transform = TRUE; 10888 if (xtensa_frag_flags_is_empty (prop_flags)) 10889 prop_flags->is_data = TRUE; 10890 } 10891 if (fragP->tc_frag_data.is_unreachable) 10892 prop_flags->is_unreachable = TRUE; 10893 else if (fragP->tc_frag_data.is_insn) 10894 { 10895 prop_flags->is_insn = TRUE; 10896 if (fragP->tc_frag_data.is_loop_target) 10897 prop_flags->insn.is_loop_target = TRUE; 10898 if (fragP->tc_frag_data.is_branch_target) 10899 prop_flags->insn.is_branch_target = TRUE; 10900 if (fragP->tc_frag_data.is_no_density) 10901 prop_flags->insn.is_no_density = TRUE; 10902 if (fragP->tc_frag_data.use_absolute_literals) 10903 prop_flags->insn.is_abslit = TRUE; 10904 } 10905 if (fragP->tc_frag_data.is_align) 10906 { 10907 prop_flags->is_align = TRUE; 10908 prop_flags->alignment = fragP->tc_frag_data.alignment; 10909 if (xtensa_frag_flags_is_empty (prop_flags)) 10910 prop_flags->is_data = TRUE; 10911 } 10912 } 10913 10914 10915 static flagword 10916 frag_flags_to_number (const frag_flags *prop_flags) 10917 { 10918 flagword num = 0; 10919 if (prop_flags->is_literal) 10920 num |= XTENSA_PROP_LITERAL; 10921 if (prop_flags->is_insn) 10922 num |= XTENSA_PROP_INSN; 10923 if (prop_flags->is_data) 10924 num |= XTENSA_PROP_DATA; 10925 if (prop_flags->is_unreachable) 10926 num |= XTENSA_PROP_UNREACHABLE; 10927 if (prop_flags->insn.is_loop_target) 10928 num |= XTENSA_PROP_INSN_LOOP_TARGET; 10929 if (prop_flags->insn.is_branch_target) 10930 { 10931 num |= XTENSA_PROP_INSN_BRANCH_TARGET; 10932 num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); 10933 } 10934 10935 if (prop_flags->insn.is_no_density) 10936 num |= XTENSA_PROP_INSN_NO_DENSITY; 10937 if (prop_flags->is_no_transform) 10938 num |= XTENSA_PROP_NO_TRANSFORM; 10939 if (prop_flags->insn.is_no_reorder) 10940 num |= XTENSA_PROP_INSN_NO_REORDER; 10941 if (prop_flags->insn.is_abslit) 10942 num |= XTENSA_PROP_INSN_ABSLIT; 10943 10944 if (prop_flags->is_align) 10945 { 10946 num |= XTENSA_PROP_ALIGN; 10947 num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); 10948 } 10949 10950 return num; 10951 } 10952 10953 10954 static bfd_boolean 10955 xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, 10956 const frag_flags *prop_flags_2) 10957 { 10958 /* Cannot combine with an end marker. */ 10959 10960 if (prop_flags_1->is_literal != prop_flags_2->is_literal) 10961 return FALSE; 10962 if (prop_flags_1->is_insn != prop_flags_2->is_insn) 10963 return FALSE; 10964 if (prop_flags_1->is_data != prop_flags_2->is_data) 10965 return FALSE; 10966 10967 if (prop_flags_1->is_insn) 10968 { 10969 /* Properties of the beginning of the frag. */ 10970 if (prop_flags_2->insn.is_loop_target) 10971 return FALSE; 10972 if (prop_flags_2->insn.is_branch_target) 10973 return FALSE; 10974 if (prop_flags_1->insn.is_no_density != 10975 prop_flags_2->insn.is_no_density) 10976 return FALSE; 10977 if (prop_flags_1->is_no_transform != 10978 prop_flags_2->is_no_transform) 10979 return FALSE; 10980 if (prop_flags_1->insn.is_no_reorder != 10981 prop_flags_2->insn.is_no_reorder) 10982 return FALSE; 10983 if (prop_flags_1->insn.is_abslit != 10984 prop_flags_2->insn.is_abslit) 10985 return FALSE; 10986 } 10987 10988 if (prop_flags_1->is_align) 10989 return FALSE; 10990 10991 return TRUE; 10992 } 10993 10994 10995 static bfd_vma 10996 xt_block_aligned_size (const xtensa_block_info *xt_block) 10997 { 10998 bfd_vma end_addr; 10999 unsigned align_bits; 11000 11001 if (!xt_block->flags.is_align) 11002 return xt_block->size; 11003 11004 end_addr = xt_block->offset + xt_block->size; 11005 align_bits = xt_block->flags.alignment; 11006 end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; 11007 return end_addr - xt_block->offset; 11008 } 11009 11010 11011 static bfd_boolean 11012 xtensa_xt_block_combine (xtensa_block_info *xt_block, 11013 const xtensa_block_info *xt_block_2) 11014 { 11015 if (xt_block->sec != xt_block_2->sec) 11016 return FALSE; 11017 if (xt_block->offset + xt_block_aligned_size (xt_block) 11018 != xt_block_2->offset) 11019 return FALSE; 11020 11021 if (xt_block_2->size == 0 11022 && (!xt_block_2->flags.is_unreachable 11023 || xt_block->flags.is_unreachable)) 11024 { 11025 if (xt_block_2->flags.is_align 11026 && xt_block->flags.is_align) 11027 { 11028 /* Nothing needed. */ 11029 if (xt_block->flags.alignment >= xt_block_2->flags.alignment) 11030 return TRUE; 11031 } 11032 else 11033 { 11034 if (xt_block_2->flags.is_align) 11035 { 11036 /* Push alignment to previous entry. */ 11037 xt_block->flags.is_align = xt_block_2->flags.is_align; 11038 xt_block->flags.alignment = xt_block_2->flags.alignment; 11039 } 11040 return TRUE; 11041 } 11042 } 11043 if (!xtensa_frag_flags_combinable (&xt_block->flags, 11044 &xt_block_2->flags)) 11045 return FALSE; 11046 11047 xt_block->size += xt_block_2->size; 11048 11049 if (xt_block_2->flags.is_align) 11050 { 11051 xt_block->flags.is_align = TRUE; 11052 xt_block->flags.alignment = xt_block_2->flags.alignment; 11053 } 11054 11055 return TRUE; 11056 } 11057 11058 11059 static void 11060 add_xt_prop_frags (segT sec, 11061 xtensa_block_info **xt_block, 11062 frag_flags_fn property_function) 11063 { 11064 fragS *fragP; 11065 11066 /* Build it if needed. */ 11067 while (*xt_block != NULL) 11068 { 11069 xt_block = &(*xt_block)->next; 11070 } 11071 /* We are either at NULL at the beginning or at the end. */ 11072 11073 /* Walk through the frags. */ 11074 if (seg_info (sec)->frchainP) 11075 { 11076 for (fragP = seg_info (sec)->frchainP->frch_root; fragP; 11077 fragP = fragP->fr_next) 11078 { 11079 xtensa_block_info tmp_block; 11080 tmp_block.sec = sec; 11081 tmp_block.offset = fragP->fr_address; 11082 tmp_block.size = fragP->fr_fix; 11083 tmp_block.next = NULL; 11084 property_function (fragP, &tmp_block.flags); 11085 11086 if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) 11087 /* && fragP->fr_fix != 0) */ 11088 { 11089 if ((*xt_block) == NULL 11090 || !xtensa_xt_block_combine (*xt_block, &tmp_block)) 11091 { 11092 xtensa_block_info *new_block; 11093 if ((*xt_block) != NULL) 11094 xt_block = &(*xt_block)->next; 11095 new_block = (xtensa_block_info *) 11096 xmalloc (sizeof (xtensa_block_info)); 11097 *new_block = tmp_block; 11098 *xt_block = new_block; 11099 } 11100 } 11101 } 11102 } 11103 } 11104 11105 11106 /* op_placement_info_table */ 11107 11108 /* op_placement_info makes it easier to determine which 11109 ops can go in which slots. */ 11110 11111 static void 11112 init_op_placement_info_table (void) 11113 { 11114 xtensa_isa isa = xtensa_default_isa; 11115 xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); 11116 xtensa_opcode opcode; 11117 xtensa_format fmt; 11118 int slot; 11119 int num_opcodes = xtensa_isa_num_opcodes (isa); 11120 11121 op_placement_table = (op_placement_info_table) 11122 xmalloc (sizeof (op_placement_info) * num_opcodes); 11123 gas_assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); 11124 11125 for (opcode = 0; opcode < num_opcodes; opcode++) 11126 { 11127 op_placement_info *opi = &op_placement_table[opcode]; 11128 /* FIXME: Make tinsn allocation dynamic. */ 11129 if (xtensa_opcode_num_operands (isa, opcode) > MAX_INSN_ARGS) 11130 as_fatal (_("too many operands in instruction")); 11131 opi->narrowest = XTENSA_UNDEFINED; 11132 opi->narrowest_size = 0x7F; 11133 opi->narrowest_slot = 0; 11134 opi->formats = 0; 11135 opi->num_formats = 0; 11136 opi->issuef = 0; 11137 for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) 11138 { 11139 opi->slots[fmt] = 0; 11140 for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) 11141 { 11142 if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) 11143 { 11144 int fmt_length = xtensa_format_length (isa, fmt); 11145 opi->issuef++; 11146 set_bit (fmt, opi->formats); 11147 set_bit (slot, opi->slots[fmt]); 11148 if (fmt_length < opi->narrowest_size 11149 || (fmt_length == opi->narrowest_size 11150 && (xtensa_format_num_slots (isa, fmt) 11151 < xtensa_format_num_slots (isa, 11152 opi->narrowest)))) 11153 { 11154 opi->narrowest = fmt; 11155 opi->narrowest_size = fmt_length; 11156 opi->narrowest_slot = slot; 11157 } 11158 } 11159 } 11160 if (opi->formats) 11161 opi->num_formats++; 11162 } 11163 } 11164 xtensa_insnbuf_free (isa, ibuf); 11165 } 11166 11167 11168 bfd_boolean 11169 opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) 11170 { 11171 return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); 11172 } 11173 11174 11175 /* If the opcode is available in a single slot format, return its size. */ 11176 11177 static int 11178 xg_get_single_size (xtensa_opcode opcode) 11179 { 11180 return op_placement_table[opcode].narrowest_size; 11181 } 11182 11183 11184 static xtensa_format 11185 xg_get_single_format (xtensa_opcode opcode) 11186 { 11187 return op_placement_table[opcode].narrowest; 11188 } 11189 11190 11191 static int 11192 xg_get_single_slot (xtensa_opcode opcode) 11193 { 11194 return op_placement_table[opcode].narrowest_slot; 11195 } 11196 11197 11198 /* Instruction Stack Functions (from "xtensa-istack.h"). */ 11199 11200 void 11201 istack_init (IStack *stack) 11202 { 11203 stack->ninsn = 0; 11204 } 11205 11206 11207 bfd_boolean 11208 istack_empty (IStack *stack) 11209 { 11210 return (stack->ninsn == 0); 11211 } 11212 11213 11214 bfd_boolean 11215 istack_full (IStack *stack) 11216 { 11217 return (stack->ninsn == MAX_ISTACK); 11218 } 11219 11220 11221 /* Return a pointer to the top IStack entry. 11222 It is an error to call this if istack_empty () is TRUE. */ 11223 11224 TInsn * 11225 istack_top (IStack *stack) 11226 { 11227 int rec = stack->ninsn - 1; 11228 gas_assert (!istack_empty (stack)); 11229 return &stack->insn[rec]; 11230 } 11231 11232 11233 /* Add a new TInsn to an IStack. 11234 It is an error to call this if istack_full () is TRUE. */ 11235 11236 void 11237 istack_push (IStack *stack, TInsn *insn) 11238 { 11239 int rec = stack->ninsn; 11240 gas_assert (!istack_full (stack)); 11241 stack->insn[rec] = *insn; 11242 stack->ninsn++; 11243 } 11244 11245 11246 /* Clear space for the next TInsn on the IStack and return a pointer 11247 to it. It is an error to call this if istack_full () is TRUE. */ 11248 11249 TInsn * 11250 istack_push_space (IStack *stack) 11251 { 11252 int rec = stack->ninsn; 11253 TInsn *insn; 11254 gas_assert (!istack_full (stack)); 11255 insn = &stack->insn[rec]; 11256 tinsn_init (insn); 11257 stack->ninsn++; 11258 return insn; 11259 } 11260 11261 11262 /* Remove the last pushed instruction. It is an error to call this if 11263 istack_empty () returns TRUE. */ 11264 11265 void 11266 istack_pop (IStack *stack) 11267 { 11268 int rec = stack->ninsn - 1; 11269 gas_assert (!istack_empty (stack)); 11270 stack->ninsn--; 11271 tinsn_init (&stack->insn[rec]); 11272 } 11273 11274 11275 /* TInsn functions. */ 11276 11277 void 11278 tinsn_init (TInsn *dst) 11279 { 11280 memset (dst, 0, sizeof (TInsn)); 11281 } 11282 11283 11284 /* Return TRUE if ANY of the operands in the insn are symbolic. */ 11285 11286 static bfd_boolean 11287 tinsn_has_symbolic_operands (const TInsn *insn) 11288 { 11289 int i; 11290 int n = insn->ntok; 11291 11292 gas_assert (insn->insn_type == ITYPE_INSN); 11293 11294 for (i = 0; i < n; ++i) 11295 { 11296 switch (insn->tok[i].X_op) 11297 { 11298 case O_register: 11299 case O_constant: 11300 break; 11301 default: 11302 return TRUE; 11303 } 11304 } 11305 return FALSE; 11306 } 11307 11308 11309 bfd_boolean 11310 tinsn_has_invalid_symbolic_operands (const TInsn *insn) 11311 { 11312 xtensa_isa isa = xtensa_default_isa; 11313 int i; 11314 int n = insn->ntok; 11315 11316 gas_assert (insn->insn_type == ITYPE_INSN); 11317 11318 for (i = 0; i < n; ++i) 11319 { 11320 switch (insn->tok[i].X_op) 11321 { 11322 case O_register: 11323 case O_constant: 11324 break; 11325 case O_big: 11326 case O_illegal: 11327 case O_absent: 11328 /* Errors for these types are caught later. */ 11329 break; 11330 case O_hi16: 11331 case O_lo16: 11332 default: 11333 /* Symbolic immediates are only allowed on the last immediate 11334 operand. At this time, CONST16 is the only opcode where we 11335 support non-PC-relative relocations. */ 11336 if (i != get_relaxable_immed (insn->opcode) 11337 || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 11338 && insn->opcode != xtensa_const16_opcode)) 11339 { 11340 as_bad (_("invalid symbolic operand")); 11341 return TRUE; 11342 } 11343 } 11344 } 11345 return FALSE; 11346 } 11347 11348 11349 /* For assembly code with complex expressions (e.g. subtraction), 11350 we have to build them in the literal pool so that 11351 their results are calculated correctly after relaxation. 11352 The relaxation only handles expressions that 11353 boil down to SYMBOL + OFFSET. */ 11354 11355 static bfd_boolean 11356 tinsn_has_complex_operands (const TInsn *insn) 11357 { 11358 int i; 11359 int n = insn->ntok; 11360 gas_assert (insn->insn_type == ITYPE_INSN); 11361 for (i = 0; i < n; ++i) 11362 { 11363 switch (insn->tok[i].X_op) 11364 { 11365 case O_register: 11366 case O_constant: 11367 case O_symbol: 11368 case O_lo16: 11369 case O_hi16: 11370 break; 11371 default: 11372 return TRUE; 11373 } 11374 } 11375 return FALSE; 11376 } 11377 11378 11379 /* Encode a TInsn opcode and its constant operands into slotbuf. 11380 Return TRUE if there is a symbol in the immediate field. This 11381 function assumes that: 11382 1) The number of operands are correct. 11383 2) The insn_type is ITYPE_INSN. 11384 3) The opcode can be encoded in the specified format and slot. 11385 4) Operands are either O_constant or O_symbol, and all constants fit. */ 11386 11387 static bfd_boolean 11388 tinsn_to_slotbuf (xtensa_format fmt, 11389 int slot, 11390 TInsn *tinsn, 11391 xtensa_insnbuf slotbuf) 11392 { 11393 xtensa_isa isa = xtensa_default_isa; 11394 xtensa_opcode opcode = tinsn->opcode; 11395 bfd_boolean has_fixup = FALSE; 11396 int noperands = xtensa_opcode_num_operands (isa, opcode); 11397 int i; 11398 11399 gas_assert (tinsn->insn_type == ITYPE_INSN); 11400 if (noperands != tinsn->ntok) 11401 as_fatal (_("operand number mismatch")); 11402 11403 if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) 11404 { 11405 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), 11406 xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); 11407 return FALSE; 11408 } 11409 11410 for (i = 0; i < noperands; i++) 11411 { 11412 expressionS *exp = &tinsn->tok[i]; 11413 int rc; 11414 unsigned line; 11415 char *file_name; 11416 uint32 opnd_value; 11417 11418 switch (exp->X_op) 11419 { 11420 case O_register: 11421 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 11422 break; 11423 /* The register number has already been checked in 11424 expression_maybe_register, so we don't need to check here. */ 11425 opnd_value = exp->X_add_number; 11426 (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); 11427 rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, 11428 opnd_value); 11429 if (rc != 0) 11430 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); 11431 break; 11432 11433 case O_constant: 11434 if (xtensa_operand_is_visible (isa, opcode, i) == 0) 11435 break; 11436 as_where (&file_name, &line); 11437 /* It is a constant and we called this function 11438 then we have to try to fit it. */ 11439 xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, 11440 exp->X_add_number, file_name, line); 11441 break; 11442 11443 default: 11444 has_fixup = TRUE; 11445 break; 11446 } 11447 } 11448 11449 return has_fixup; 11450 } 11451 11452 11453 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded 11454 into a multi-slot instruction, fill the other slots with NOPs. 11455 Return TRUE if there is a symbol in the immediate field. See also the 11456 assumptions listed for tinsn_to_slotbuf. */ 11457 11458 static bfd_boolean 11459 tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) 11460 { 11461 static xtensa_insnbuf slotbuf = 0; 11462 static vliw_insn vinsn; 11463 xtensa_isa isa = xtensa_default_isa; 11464 bfd_boolean has_fixup = FALSE; 11465 int i; 11466 11467 if (!slotbuf) 11468 { 11469 slotbuf = xtensa_insnbuf_alloc (isa); 11470 xg_init_vinsn (&vinsn); 11471 } 11472 11473 xg_clear_vinsn (&vinsn); 11474 11475 bundle_tinsn (tinsn, &vinsn); 11476 11477 xtensa_format_encode (isa, vinsn.format, insnbuf); 11478 11479 for (i = 0; i < vinsn.num_slots; i++) 11480 { 11481 /* Only one slot may have a fix-up because the rest contains NOPs. */ 11482 has_fixup |= 11483 tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); 11484 xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); 11485 } 11486 11487 return has_fixup; 11488 } 11489 11490 11491 /* Check the instruction arguments. Return TRUE on failure. */ 11492 11493 static bfd_boolean 11494 tinsn_check_arguments (const TInsn *insn) 11495 { 11496 xtensa_isa isa = xtensa_default_isa; 11497 xtensa_opcode opcode = insn->opcode; 11498 xtensa_regfile t1_regfile, t2_regfile; 11499 int t1_reg, t2_reg; 11500 int t1_base_reg, t1_last_reg; 11501 int t2_base_reg, t2_last_reg; 11502 char t1_inout, t2_inout; 11503 int i, j; 11504 11505 if (opcode == XTENSA_UNDEFINED) 11506 { 11507 as_bad (_("invalid opcode")); 11508 return TRUE; 11509 } 11510 11511 if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) 11512 { 11513 as_bad (_("too few operands")); 11514 return TRUE; 11515 } 11516 11517 if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) 11518 { 11519 as_bad (_("too many operands")); 11520 return TRUE; 11521 } 11522 11523 /* Check registers. */ 11524 for (j = 0; j < insn->ntok; j++) 11525 { 11526 if (xtensa_operand_is_register (isa, insn->opcode, j) != 1) 11527 continue; 11528 11529 t2_regfile = xtensa_operand_regfile (isa, insn->opcode, j); 11530 t2_base_reg = insn->tok[j].X_add_number; 11531 t2_last_reg 11532 = t2_base_reg + xtensa_operand_num_regs (isa, insn->opcode, j); 11533 11534 for (i = 0; i < insn->ntok; i++) 11535 { 11536 if (i == j) 11537 continue; 11538 11539 if (xtensa_operand_is_register (isa, insn->opcode, i) != 1) 11540 continue; 11541 11542 t1_regfile = xtensa_operand_regfile (isa, insn->opcode, i); 11543 11544 if (t1_regfile != t2_regfile) 11545 continue; 11546 11547 t1_inout = xtensa_operand_inout (isa, insn->opcode, i); 11548 t2_inout = xtensa_operand_inout (isa, insn->opcode, j); 11549 11550 t1_base_reg = insn->tok[i].X_add_number; 11551 t1_last_reg = (t1_base_reg 11552 + xtensa_operand_num_regs (isa, insn->opcode, i)); 11553 11554 for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) 11555 { 11556 for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) 11557 { 11558 if (t1_reg != t2_reg) 11559 continue; 11560 11561 if (t1_inout != 'i' && t2_inout != 'i') 11562 { 11563 as_bad (_("multiple writes to the same register")); 11564 return TRUE; 11565 } 11566 } 11567 } 11568 } 11569 } 11570 return FALSE; 11571 } 11572 11573 11574 /* Load an instruction from its encoded form. */ 11575 11576 static void 11577 tinsn_from_chars (TInsn *tinsn, char *f, int slot) 11578 { 11579 vliw_insn vinsn; 11580 11581 xg_init_vinsn (&vinsn); 11582 vinsn_from_chars (&vinsn, f); 11583 11584 *tinsn = vinsn.slots[slot]; 11585 xg_free_vinsn (&vinsn); 11586 } 11587 11588 11589 static void 11590 tinsn_from_insnbuf (TInsn *tinsn, 11591 xtensa_insnbuf slotbuf, 11592 xtensa_format fmt, 11593 int slot) 11594 { 11595 int i; 11596 xtensa_isa isa = xtensa_default_isa; 11597 11598 /* Find the immed. */ 11599 tinsn_init (tinsn); 11600 tinsn->insn_type = ITYPE_INSN; 11601 tinsn->is_specific_opcode = FALSE; /* must not be specific */ 11602 tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); 11603 tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); 11604 for (i = 0; i < tinsn->ntok; i++) 11605 { 11606 set_expr_const (&tinsn->tok[i], 11607 xtensa_insnbuf_get_operand (slotbuf, fmt, slot, 11608 tinsn->opcode, i)); 11609 } 11610 } 11611 11612 11613 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ 11614 11615 static void 11616 tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) 11617 { 11618 xtensa_opcode opcode = tinsn->opcode; 11619 int opnum; 11620 11621 if (fragP->tc_frag_data.slot_symbols[slot]) 11622 { 11623 opnum = get_relaxable_immed (opcode); 11624 gas_assert (opnum >= 0); 11625 set_expr_symbol_offset (&tinsn->tok[opnum], 11626 fragP->tc_frag_data.slot_symbols[slot], 11627 fragP->tc_frag_data.slot_offsets[slot]); 11628 } 11629 tinsn->extra_arg = fragP->tc_frag_data.free_reg[slot]; 11630 } 11631 11632 11633 static int 11634 get_num_stack_text_bytes (IStack *istack) 11635 { 11636 int i; 11637 int text_bytes = 0; 11638 11639 for (i = 0; i < istack->ninsn; i++) 11640 { 11641 TInsn *tinsn = &istack->insn[i]; 11642 if (tinsn->insn_type == ITYPE_INSN) 11643 text_bytes += xg_get_single_size (tinsn->opcode); 11644 } 11645 return text_bytes; 11646 } 11647 11648 11649 static int 11650 get_num_stack_literal_bytes (IStack *istack) 11651 { 11652 int i; 11653 int lit_bytes = 0; 11654 11655 for (i = 0; i < istack->ninsn; i++) 11656 { 11657 TInsn *tinsn = &istack->insn[i]; 11658 if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) 11659 lit_bytes += 4; 11660 } 11661 return lit_bytes; 11662 } 11663 11664 11665 /* vliw_insn functions. */ 11666 11667 static void 11668 xg_init_vinsn (vliw_insn *v) 11669 { 11670 int i; 11671 xtensa_isa isa = xtensa_default_isa; 11672 11673 xg_clear_vinsn (v); 11674 11675 v->insnbuf = xtensa_insnbuf_alloc (isa); 11676 if (v->insnbuf == NULL) 11677 as_fatal (_("out of memory")); 11678 11679 for (i = 0; i < config_max_slots; i++) 11680 { 11681 v->slotbuf[i] = xtensa_insnbuf_alloc (isa); 11682 if (v->slotbuf[i] == NULL) 11683 as_fatal (_("out of memory")); 11684 } 11685 } 11686 11687 11688 static void 11689 xg_clear_vinsn (vliw_insn *v) 11690 { 11691 int i; 11692 11693 memset (v, 0, offsetof (vliw_insn, slots) 11694 + sizeof(TInsn) * config_max_slots); 11695 11696 v->format = XTENSA_UNDEFINED; 11697 v->num_slots = 0; 11698 v->inside_bundle = FALSE; 11699 11700 if (xt_saved_debug_type != DEBUG_NONE) 11701 debug_type = xt_saved_debug_type; 11702 11703 for (i = 0; i < config_max_slots; i++) 11704 v->slots[i].opcode = XTENSA_UNDEFINED; 11705 } 11706 11707 11708 static void 11709 xg_copy_vinsn (vliw_insn *dst, vliw_insn *src) 11710 { 11711 memcpy (dst, src, 11712 offsetof(vliw_insn, slots) + src->num_slots * sizeof(TInsn)); 11713 dst->insnbuf = src->insnbuf; 11714 memcpy (dst->slotbuf, src->slotbuf, src->num_slots * sizeof(xtensa_insnbuf)); 11715 } 11716 11717 11718 static bfd_boolean 11719 vinsn_has_specific_opcodes (vliw_insn *v) 11720 { 11721 int i; 11722 11723 for (i = 0; i < v->num_slots; i++) 11724 { 11725 if (v->slots[i].is_specific_opcode) 11726 return TRUE; 11727 } 11728 return FALSE; 11729 } 11730 11731 11732 static void 11733 xg_free_vinsn (vliw_insn *v) 11734 { 11735 int i; 11736 xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); 11737 for (i = 0; i < config_max_slots; i++) 11738 xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); 11739 } 11740 11741 11742 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic 11743 operands. See also the assumptions listed for tinsn_to_slotbuf. */ 11744 11745 static bfd_boolean 11746 vinsn_to_insnbuf (vliw_insn *vinsn, 11747 char *frag_offset, 11748 fragS *fragP, 11749 bfd_boolean record_fixup) 11750 { 11751 xtensa_isa isa = xtensa_default_isa; 11752 xtensa_format fmt = vinsn->format; 11753 xtensa_insnbuf insnbuf = vinsn->insnbuf; 11754 int slot; 11755 bfd_boolean has_fixup = FALSE; 11756 11757 xtensa_format_encode (isa, fmt, insnbuf); 11758 11759 for (slot = 0; slot < vinsn->num_slots; slot++) 11760 { 11761 TInsn *tinsn = &vinsn->slots[slot]; 11762 expressionS *extra_arg = &tinsn->extra_arg; 11763 bfd_boolean tinsn_has_fixup = 11764 tinsn_to_slotbuf (vinsn->format, slot, tinsn, 11765 vinsn->slotbuf[slot]); 11766 11767 xtensa_format_set_slot (isa, fmt, slot, 11768 insnbuf, vinsn->slotbuf[slot]); 11769 if (extra_arg->X_op != O_illegal && extra_arg->X_op != O_register) 11770 { 11771 if (vinsn->num_slots != 1) 11772 as_bad (_("TLS relocation not allowed in FLIX bundle")); 11773 else if (record_fixup) 11774 /* Instructions that generate TLS relocations should always be 11775 relaxed in the front-end. If "record_fixup" is set, then this 11776 function is being called during back-end relaxation, so flag 11777 the unexpected behavior as an error. */ 11778 as_bad (_("unexpected TLS relocation")); 11779 else 11780 fix_new (fragP, frag_offset - fragP->fr_literal, 11781 xtensa_format_length (isa, fmt), 11782 extra_arg->X_add_symbol, extra_arg->X_add_number, 11783 FALSE, map_operator_to_reloc (extra_arg->X_op, FALSE)); 11784 } 11785 if (tinsn_has_fixup) 11786 { 11787 int i; 11788 xtensa_opcode opcode = tinsn->opcode; 11789 int noperands = xtensa_opcode_num_operands (isa, opcode); 11790 has_fixup = TRUE; 11791 11792 for (i = 0; i < noperands; i++) 11793 { 11794 expressionS* exp = &tinsn->tok[i]; 11795 switch (exp->X_op) 11796 { 11797 case O_symbol: 11798 case O_lo16: 11799 case O_hi16: 11800 if (get_relaxable_immed (opcode) == i) 11801 { 11802 /* Add a fix record for the instruction, except if this 11803 function is being called prior to relaxation, i.e., 11804 if record_fixup is false, and the instruction might 11805 be relaxed later. */ 11806 if (record_fixup 11807 || tinsn->is_specific_opcode 11808 || !xg_is_relaxable_insn (tinsn, 0)) 11809 { 11810 xg_add_opcode_fix (tinsn, i, fmt, slot, exp, fragP, 11811 frag_offset - fragP->fr_literal); 11812 } 11813 else 11814 { 11815 if (exp->X_op != O_symbol) 11816 as_bad (_("invalid operand")); 11817 tinsn->symbol = exp->X_add_symbol; 11818 tinsn->offset = exp->X_add_number; 11819 } 11820 } 11821 else 11822 as_bad (_("symbolic operand not allowed")); 11823 break; 11824 11825 case O_constant: 11826 case O_register: 11827 break; 11828 11829 default: 11830 as_bad (_("expression too complex")); 11831 break; 11832 } 11833 } 11834 } 11835 } 11836 11837 return has_fixup; 11838 } 11839 11840 11841 static void 11842 vinsn_from_chars (vliw_insn *vinsn, char *f) 11843 { 11844 static xtensa_insnbuf insnbuf = NULL; 11845 static xtensa_insnbuf slotbuf = NULL; 11846 int i; 11847 xtensa_format fmt; 11848 xtensa_isa isa = xtensa_default_isa; 11849 11850 if (!insnbuf) 11851 { 11852 insnbuf = xtensa_insnbuf_alloc (isa); 11853 slotbuf = xtensa_insnbuf_alloc (isa); 11854 } 11855 11856 xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); 11857 fmt = xtensa_format_decode (isa, insnbuf); 11858 if (fmt == XTENSA_UNDEFINED) 11859 as_fatal (_("cannot decode instruction format")); 11860 vinsn->format = fmt; 11861 vinsn->num_slots = xtensa_format_num_slots (isa, fmt); 11862 11863 for (i = 0; i < vinsn->num_slots; i++) 11864 { 11865 TInsn *tinsn = &vinsn->slots[i]; 11866 xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); 11867 tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); 11868 } 11869 } 11870 11871 11872 /* Expression utilities. */ 11873 11874 /* Return TRUE if the expression is an integer constant. */ 11875 11876 bfd_boolean 11877 expr_is_const (const expressionS *s) 11878 { 11879 return (s->X_op == O_constant); 11880 } 11881 11882 11883 /* Get the expression constant. 11884 Calling this is illegal if expr_is_const () returns TRUE. */ 11885 11886 offsetT 11887 get_expr_const (const expressionS *s) 11888 { 11889 gas_assert (expr_is_const (s)); 11890 return s->X_add_number; 11891 } 11892 11893 11894 /* Set the expression to a constant value. */ 11895 11896 void 11897 set_expr_const (expressionS *s, offsetT val) 11898 { 11899 s->X_op = O_constant; 11900 s->X_add_number = val; 11901 s->X_add_symbol = NULL; 11902 s->X_op_symbol = NULL; 11903 } 11904 11905 11906 bfd_boolean 11907 expr_is_register (const expressionS *s) 11908 { 11909 return (s->X_op == O_register); 11910 } 11911 11912 11913 /* Get the expression constant. 11914 Calling this is illegal if expr_is_const () returns TRUE. */ 11915 11916 offsetT 11917 get_expr_register (const expressionS *s) 11918 { 11919 gas_assert (expr_is_register (s)); 11920 return s->X_add_number; 11921 } 11922 11923 11924 /* Set the expression to a symbol + constant offset. */ 11925 11926 void 11927 set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) 11928 { 11929 s->X_op = O_symbol; 11930 s->X_add_symbol = sym; 11931 s->X_op_symbol = NULL; /* unused */ 11932 s->X_add_number = offset; 11933 } 11934 11935 11936 /* Return TRUE if the two expressions are equal. */ 11937 11938 bfd_boolean 11939 expr_is_equal (expressionS *s1, expressionS *s2) 11940 { 11941 if (s1->X_op != s2->X_op) 11942 return FALSE; 11943 if (s1->X_add_symbol != s2->X_add_symbol) 11944 return FALSE; 11945 if (s1->X_op_symbol != s2->X_op_symbol) 11946 return FALSE; 11947 if (s1->X_add_number != s2->X_add_number) 11948 return FALSE; 11949 return TRUE; 11950 } 11951 11952 11953 static void 11954 copy_expr (expressionS *dst, const expressionS *src) 11955 { 11956 memcpy (dst, src, sizeof (expressionS)); 11957 } 11958 11959 11960 /* Support for the "--rename-section" option. */ 11961 11962 struct rename_section_struct 11963 { 11964 char *old_name; 11965 char *new_name; 11966 struct rename_section_struct *next; 11967 }; 11968 11969 static struct rename_section_struct *section_rename; 11970 11971 11972 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add 11973 entries to the section_rename list. Note: Specifying multiple 11974 renamings separated by colons is not documented and is retained only 11975 for backward compatibility. */ 11976 11977 static void 11978 build_section_rename (const char *arg) 11979 { 11980 struct rename_section_struct *r; 11981 char *this_arg = NULL; 11982 char *next_arg = NULL; 11983 11984 for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) 11985 { 11986 char *old_name, *new_name; 11987 11988 if (this_arg) 11989 { 11990 next_arg = strchr (this_arg, ':'); 11991 if (next_arg) 11992 { 11993 *next_arg = '\0'; 11994 next_arg++; 11995 } 11996 } 11997 11998 old_name = this_arg; 11999 new_name = strchr (this_arg, '='); 12000 12001 if (*old_name == '\0') 12002 { 12003 as_warn (_("ignoring extra '-rename-section' delimiter ':'")); 12004 continue; 12005 } 12006 if (!new_name || new_name[1] == '\0') 12007 { 12008 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), 12009 old_name); 12010 continue; 12011 } 12012 *new_name = '\0'; 12013 new_name++; 12014 12015 /* Check for invalid section renaming. */ 12016 for (r = section_rename; r != NULL; r = r->next) 12017 { 12018 if (strcmp (r->old_name, old_name) == 0) 12019 as_bad (_("section %s renamed multiple times"), old_name); 12020 if (strcmp (r->new_name, new_name) == 0) 12021 as_bad (_("multiple sections remapped to output section %s"), 12022 new_name); 12023 } 12024 12025 /* Now add it. */ 12026 r = (struct rename_section_struct *) 12027 xmalloc (sizeof (struct rename_section_struct)); 12028 r->old_name = xstrdup (old_name); 12029 r->new_name = xstrdup (new_name); 12030 r->next = section_rename; 12031 section_rename = r; 12032 } 12033 } 12034 12035 12036 char * 12037 xtensa_section_rename (char *name) 12038 { 12039 struct rename_section_struct *r = section_rename; 12040 12041 for (r = section_rename; r != NULL; r = r->next) 12042 { 12043 if (strcmp (r->old_name, name) == 0) 12044 return r->new_name; 12045 } 12046 12047 return name; 12048 } 12049