1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright (C) 1989-2016 Free Software Foundation, Inc. 3 This file is part of GAS, the GNU Assembler. 4 5 GAS is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3, or (at your option) 8 any later version. 9 10 GAS is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public 16 License along with GAS; see the file COPYING. If not, write 17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 18 Boston, MA 02110-1301, USA. */ 19 20 #include "as.h" 21 #include "safe-ctype.h" 22 #include "subsegs.h" 23 24 #include "opcode/sparc.h" 25 #include "dw2gencfi.h" 26 27 #ifdef OBJ_ELF 28 #include "elf/sparc.h" 29 #include "dwarf2dbg.h" 30 #endif 31 32 /* Some ancient Sun C compilers would not take such hex constants as 33 unsigned, and would end up sign-extending them to form an offsetT, 34 so use these constants instead. */ 35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 37 38 static int sparc_ip (char *, const struct sparc_opcode **); 39 static int parse_keyword_arg (int (*) (const char *), char **, int *); 40 static int parse_const_expr_arg (char **, int *); 41 static int get_expression (char *); 42 43 /* Default architecture. */ 44 /* ??? The default value should be V8, but sparclite support was added 45 by making it the default. GCC now passes -Asparclite, so maybe sometime in 46 the future we can set this to V8. */ 47 #ifndef DEFAULT_ARCH 48 #define DEFAULT_ARCH "sparclite" 49 #endif 50 static const char *default_arch = DEFAULT_ARCH; 51 52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 53 have been set. */ 54 static int default_init_p; 55 56 /* Current architecture. We don't bump up unless necessary. */ 57 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 58 59 /* The maximum architecture level we can bump up to. 60 In a 32 bit environment, don't allow bumping up to v9 by default. 61 The native assembler works this way. The user is required to pass 62 an explicit argument before we'll create v9 object files. However, if 63 we don't see any v9 insns, a v8plus object file is not created. */ 64 static enum sparc_opcode_arch_val max_architecture; 65 66 /* Either 32 or 64, selects file format. */ 67 static int sparc_arch_size; 68 /* Initial (default) value, recorded separately in case a user option 69 changes the value before md_show_usage is called. */ 70 static int default_arch_size; 71 72 #ifdef OBJ_ELF 73 /* The currently selected v9 memory model. Currently only used for 74 ELF. */ 75 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 76 77 #ifndef TE_SOLARIS 78 /* Bitmask of instruction types seen so far, used to populate the 79 GNU attributes section with hwcap information. */ 80 static bfd_uint64_t hwcap_seen; 81 #endif 82 #endif 83 84 static bfd_uint64_t hwcap_allowed; 85 86 static int architecture_requested; 87 static int warn_on_bump; 88 89 /* If warn_on_bump and the needed architecture is higher than this 90 architecture, issue a warning. */ 91 static enum sparc_opcode_arch_val warn_after_architecture; 92 93 /* Non-zero if as should generate error if an undeclared g[23] register 94 has been used in -64. */ 95 static int no_undeclared_regs; 96 97 /* Non-zero if we should try to relax jumps and calls. */ 98 static int sparc_relax; 99 100 /* Non-zero if we are generating PIC code. */ 101 int sparc_pic_code; 102 103 /* Non-zero if we should give an error when misaligned data is seen. */ 104 static int enforce_aligned_data; 105 106 extern int target_big_endian; 107 108 static int target_little_endian_data; 109 110 /* Symbols for global registers on v9. */ 111 static symbolS *globals[8]; 112 113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 114 int sparc_cie_data_alignment; 115 116 /* V9 and 86x have big and little endian data, but instructions are always big 117 endian. The sparclet has bi-endian support but both data and insns have 118 the same endianness. Global `target_big_endian' is used for data. 119 The following macro is used for instructions. */ 120 #ifndef INSN_BIG_ENDIAN 121 #define INSN_BIG_ENDIAN (target_big_endian \ 122 || default_arch_type == sparc86x \ 123 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 124 #endif 125 126 /* Handle of the OPCODE hash table. */ 127 static struct hash_control *op_hash; 128 129 static void s_data1 (void); 130 static void s_seg (int); 131 static void s_proc (int); 132 static void s_reserve (int); 133 static void s_common (int); 134 static void s_empty (int); 135 static void s_uacons (int); 136 static void s_ncons (int); 137 #ifdef OBJ_ELF 138 static void s_register (int); 139 #endif 140 141 const pseudo_typeS md_pseudo_table[] = 142 { 143 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 144 {"common", s_common, 0}, 145 {"empty", s_empty, 0}, 146 {"global", s_globl, 0}, 147 {"half", cons, 2}, 148 {"nword", s_ncons, 0}, 149 {"optim", s_ignore, 0}, 150 {"proc", s_proc, 0}, 151 {"reserve", s_reserve, 0}, 152 {"seg", s_seg, 0}, 153 {"skip", s_space, 0}, 154 {"word", cons, 4}, 155 {"xword", cons, 8}, 156 {"uahalf", s_uacons, 2}, 157 {"uaword", s_uacons, 4}, 158 {"uaxword", s_uacons, 8}, 159 #ifdef OBJ_ELF 160 /* These are specific to sparc/svr4. */ 161 {"2byte", s_uacons, 2}, 162 {"4byte", s_uacons, 4}, 163 {"8byte", s_uacons, 8}, 164 {"register", s_register, 0}, 165 #endif 166 {NULL, 0, 0}, 167 }; 168 169 /* This array holds the chars that always start a comment. If the 170 pre-processor is disabled, these aren't very useful. */ 171 const char comment_chars[] = "!"; /* JF removed '|' from 172 comment_chars. */ 173 174 /* This array holds the chars that only start a comment at the beginning of 175 a line. If the line seems to have the form '# 123 filename' 176 .line and .file directives will appear in the pre-processed output. */ 177 /* Note that input_file.c hand checks for '#' at the beginning of the 178 first line of the input file. This is because the compiler outputs 179 #NO_APP at the beginning of its output. */ 180 /* Also note that comments started like this one will always 181 work if '/' isn't otherwise defined. */ 182 const char line_comment_chars[] = "#"; 183 184 const char line_separator_chars[] = ";"; 185 186 /* Chars that can be used to separate mant from exp in floating point 187 nums. */ 188 const char EXP_CHARS[] = "eE"; 189 190 /* Chars that mean this number is a floating point constant. 191 As in 0f12.456 192 or 0d1.2345e12 */ 193 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 194 195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 196 changed in read.c. Ideally it shouldn't have to know about it at all, 197 but nothing is ideal around here. */ 198 199 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 200 201 struct sparc_it 202 { 203 const char *error; 204 unsigned long opcode; 205 struct nlist *nlistp; 206 expressionS exp; 207 expressionS exp2; 208 int pcrel; 209 bfd_reloc_code_real_type reloc; 210 }; 211 212 struct sparc_it the_insn, set_insn; 213 214 static void output_insn (const struct sparc_opcode *, struct sparc_it *); 215 216 /* Table of arguments to -A. 217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 218 for this use. That table is for opcodes only. This table is for opcodes 219 and file formats. */ 220 221 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, 222 v8plusa, v9, v9a, v9b, v9_64}; 223 224 /* Hardware capability sets, used to keep sparc_arch_table easy to 225 read. */ 226 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD 227 #define HWS_V9 HWS_V8 | HWCAP_POPC 228 #define HWS_VA HWS_V9 | HWCAP_VIS 229 #define HWS_VB HWS_VA | HWCAP_VIS2 230 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT 231 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC 232 #define HWS_VE HWS_VD \ 233 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \ 234 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \ 235 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE 236 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA 237 #define HWS_VM HWS_VV 238 239 #define HWS2_VM \ 240 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \ 241 | HWCAP2_XMPMUL | HWCAP2_XMONT 242 243 static struct sparc_arch { 244 const char *name; 245 const char *opcode_arch; 246 enum sparc_arch_types arch_type; 247 /* Default word size, as specified during configuration. 248 A value of zero means can't be used to specify default architecture. */ 249 int default_arch_size; 250 /* Allowable arg to -A? */ 251 int user_option_p; 252 int hwcap_allowed; 253 int hwcap2_allowed; 254 } sparc_arch_table[] = { 255 { "v6", "v6", v6, 0, 1, 0, 0 }, 256 { "v7", "v7", v7, 0, 1, 0, 0 }, 257 { "v8", "v8", v8, 32, 1, HWS_V8, 0 }, 258 { "v8a", "v8", v8, 32, 1, HWS_V8, 0 }, 259 { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, 260 { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 }, 261 { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 }, 262 { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 }, 263 { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 }, 264 { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, 265 { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, 266 267 { "sparc4", "v9v", v9, 0, 1, HWS_VV, 0 }, 268 { "sparc5", "v9m", v9, 0, 1, HWS_VM, HWS2_VM }, 269 270 { "leon", "leon", leon, 32, 1, HWS_V8, 0 }, 271 { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 }, 272 { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 }, 273 { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 }, 274 275 { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, 276 { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 }, 277 { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 }, 278 { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 }, 279 { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 }, 280 { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 }, 281 { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 }, 282 { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 }, 283 284 { "v9", "v9", v9, 0, 1, HWS_V9, 0 }, 285 { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 }, 286 { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 }, 287 { "v9c", "v9c", v9, 0, 1, HWS_VC, 0 }, 288 { "v9d", "v9d", v9, 0, 1, HWS_VD, 0 }, 289 { "v9e", "v9e", v9, 0, 1, HWS_VE, 0 }, 290 { "v9v", "v9v", v9, 0, 1, HWS_VV, 0 }, 291 { "v9m", "v9m", v9, 0, 1, HWS_VM, HWS2_VM }, 292 293 /* This exists to allow configure.tgt to pass one 294 value to specify both the default machine and default word size. */ 295 { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 }, 296 { NULL, NULL, v8, 0, 0, 0, 0 } 297 }; 298 299 /* Variant of default_arch */ 300 static enum sparc_arch_types default_arch_type; 301 302 static struct sparc_arch * 303 lookup_arch (const char *name) 304 { 305 struct sparc_arch *sa; 306 307 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 308 if (strcmp (sa->name, name) == 0) 309 break; 310 if (sa->name == NULL) 311 return NULL; 312 return sa; 313 } 314 315 /* Initialize the default opcode arch and word size from the default 316 architecture name. */ 317 318 static void 319 init_default_arch (void) 320 { 321 struct sparc_arch *sa = lookup_arch (default_arch); 322 323 if (sa == NULL 324 || sa->default_arch_size == 0) 325 as_fatal (_("Invalid default architecture, broken assembler.")); 326 327 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 328 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 329 as_fatal (_("Bad opcode table, broken assembler.")); 330 default_arch_size = sparc_arch_size = sa->default_arch_size; 331 default_init_p = 1; 332 default_arch_type = sa->arch_type; 333 } 334 335 /* Called by TARGET_FORMAT. */ 336 337 const char * 338 sparc_target_format (void) 339 { 340 /* We don't get a chance to initialize anything before we're called, 341 so handle that now. */ 342 if (! default_init_p) 343 init_default_arch (); 344 345 #ifdef OBJ_AOUT 346 #ifdef TE_NetBSD 347 return "a.out-sparc-netbsd"; 348 #else 349 #ifdef TE_SPARCAOUT 350 if (target_big_endian) 351 return "a.out-sunos-big"; 352 else if (default_arch_type == sparc86x && target_little_endian_data) 353 return "a.out-sunos-big"; 354 else 355 return "a.out-sparc-little"; 356 #else 357 return "a.out-sunos-big"; 358 #endif 359 #endif 360 #endif 361 362 #ifdef OBJ_BOUT 363 return "b.out.big"; 364 #endif 365 366 #ifdef OBJ_COFF 367 #ifdef TE_LYNX 368 return "coff-sparc-lynx"; 369 #else 370 return "coff-sparc"; 371 #endif 372 #endif 373 374 #ifdef TE_VXWORKS 375 return "elf32-sparc-vxworks"; 376 #endif 377 378 #ifdef OBJ_ELF 379 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; 380 #endif 381 382 abort (); 383 } 384 385 /* md_parse_option 386 * Invocation line includes a switch not recognized by the base assembler. 387 * See if it's a processor-specific option. These are: 388 * 389 * -bump 390 * Warn on architecture bumps. See also -A. 391 * 392 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet 393 * Standard 32 bit architectures. 394 * -Av9, -Av9a, -Av9b 395 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 396 * This used to only mean 64 bits, but properly specifying it 397 * complicated gcc's ASM_SPECs, so now opcode selection is 398 * specified orthogonally to word size (except when specifying 399 * the default, but that is an internal implementation detail). 400 * -Av8plus, -Av8plusa, -Av8plusb 401 * Same as -Av9{,a,b}. 402 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 403 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 404 * assembler. 405 * -xarch=v9, -xarch=v9a, -xarch=v9b 406 * Same as -Av9{,a,b} -64, for compatibility with Sun's 407 * assembler. 408 * 409 * Select the architecture and possibly the file format. 410 * Instructions or features not supported by the selected 411 * architecture cause fatal errors. 412 * 413 * The default is to start at v6, and bump the architecture up 414 * whenever an instruction is seen at a higher level. In 32 bit 415 * environments, v9 is not bumped up to, the user must pass 416 * -Av8plus{,a,b}. 417 * 418 * If -bump is specified, a warning is printing when bumping to 419 * higher levels. 420 * 421 * If an architecture is specified, all instructions must match 422 * that architecture. Any higher level instructions are flagged 423 * as errors. Note that in the 32 bit environment specifying 424 * -Av8plus does not automatically create a v8plus object file, a 425 * v9 insn must be seen. 426 * 427 * If both an architecture and -bump are specified, the 428 * architecture starts at the specified level, but bumps are 429 * warnings. Note that we can't set `current_architecture' to 430 * the requested level in this case: in the 32 bit environment, 431 * we still must avoid creating v8plus object files unless v9 432 * insns are seen. 433 * 434 * Note: 435 * Bumping between incompatible architectures is always an 436 * error. For example, from sparclite to v9. 437 */ 438 439 #ifdef OBJ_ELF 440 const char *md_shortopts = "A:K:VQ:sq"; 441 #else 442 #ifdef OBJ_AOUT 443 const char *md_shortopts = "A:k"; 444 #else 445 const char *md_shortopts = "A:"; 446 #endif 447 #endif 448 struct option md_longopts[] = { 449 #define OPTION_BUMP (OPTION_MD_BASE) 450 {"bump", no_argument, NULL, OPTION_BUMP}, 451 #define OPTION_SPARC (OPTION_MD_BASE + 1) 452 {"sparc", no_argument, NULL, OPTION_SPARC}, 453 #define OPTION_XARCH (OPTION_MD_BASE + 2) 454 {"xarch", required_argument, NULL, OPTION_XARCH}, 455 #ifdef OBJ_ELF 456 #define OPTION_32 (OPTION_MD_BASE + 3) 457 {"32", no_argument, NULL, OPTION_32}, 458 #define OPTION_64 (OPTION_MD_BASE + 4) 459 {"64", no_argument, NULL, OPTION_64}, 460 #define OPTION_TSO (OPTION_MD_BASE + 5) 461 {"TSO", no_argument, NULL, OPTION_TSO}, 462 #define OPTION_PSO (OPTION_MD_BASE + 6) 463 {"PSO", no_argument, NULL, OPTION_PSO}, 464 #define OPTION_RMO (OPTION_MD_BASE + 7) 465 {"RMO", no_argument, NULL, OPTION_RMO}, 466 #endif 467 #ifdef SPARC_BIENDIAN 468 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 469 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 470 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 471 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 472 #endif 473 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 474 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 475 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 476 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 477 #ifdef OBJ_ELF 478 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 479 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 480 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 481 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 482 #endif 483 #define OPTION_RELAX (OPTION_MD_BASE + 14) 484 {"relax", no_argument, NULL, OPTION_RELAX}, 485 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 486 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 487 {NULL, no_argument, NULL, 0} 488 }; 489 490 size_t md_longopts_size = sizeof (md_longopts); 491 492 int 493 md_parse_option (int c, const char *arg) 494 { 495 /* We don't get a chance to initialize anything before we're called, 496 so handle that now. */ 497 if (! default_init_p) 498 init_default_arch (); 499 500 switch (c) 501 { 502 case OPTION_BUMP: 503 warn_on_bump = 1; 504 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 505 break; 506 507 case OPTION_XARCH: 508 #ifdef OBJ_ELF 509 if (!strncmp (arg, "v9", 2)) 510 md_parse_option (OPTION_64, NULL); 511 else 512 { 513 if (!strncmp (arg, "v8", 2) 514 || !strncmp (arg, "v7", 2) 515 || !strncmp (arg, "v6", 2) 516 || !strcmp (arg, "sparclet") 517 || !strcmp (arg, "sparclite") 518 || !strcmp (arg, "sparc86x")) 519 md_parse_option (OPTION_32, NULL); 520 } 521 #endif 522 /* Fall through. */ 523 524 case 'A': 525 { 526 struct sparc_arch *sa; 527 enum sparc_opcode_arch_val opcode_arch; 528 529 sa = lookup_arch (arg); 530 if (sa == NULL 531 || ! sa->user_option_p) 532 { 533 if (c == OPTION_XARCH) 534 as_bad (_("invalid architecture -xarch=%s"), arg); 535 else 536 as_bad (_("invalid architecture -A%s"), arg); 537 return 0; 538 } 539 540 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 541 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 542 as_fatal (_("Bad opcode table, broken assembler.")); 543 544 if (!architecture_requested 545 || opcode_arch > max_architecture) 546 max_architecture = opcode_arch; 547 hwcap_allowed 548 |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed; 549 architecture_requested = 1; 550 } 551 break; 552 553 case OPTION_SPARC: 554 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 555 break; 556 557 case OPTION_ENFORCE_ALIGNED_DATA: 558 enforce_aligned_data = 1; 559 break; 560 561 #ifdef SPARC_BIENDIAN 562 case OPTION_LITTLE_ENDIAN: 563 target_big_endian = 0; 564 if (default_arch_type != sparclet) 565 as_fatal ("This target does not support -EL"); 566 break; 567 case OPTION_LITTLE_ENDIAN_DATA: 568 target_little_endian_data = 1; 569 target_big_endian = 0; 570 if (default_arch_type != sparc86x 571 && default_arch_type != v9) 572 as_fatal ("This target does not support --little-endian-data"); 573 break; 574 case OPTION_BIG_ENDIAN: 575 target_big_endian = 1; 576 break; 577 #endif 578 579 #ifdef OBJ_AOUT 580 case 'k': 581 sparc_pic_code = 1; 582 break; 583 #endif 584 585 #ifdef OBJ_ELF 586 case OPTION_32: 587 case OPTION_64: 588 { 589 const char **list, **l; 590 591 sparc_arch_size = c == OPTION_32 ? 32 : 64; 592 list = bfd_target_list (); 593 for (l = list; *l != NULL; l++) 594 { 595 if (sparc_arch_size == 32) 596 { 597 if (CONST_STRNEQ (*l, "elf32-sparc")) 598 break; 599 } 600 else 601 { 602 if (CONST_STRNEQ (*l, "elf64-sparc")) 603 break; 604 } 605 } 606 if (*l == NULL) 607 as_fatal (_("No compiled in support for %d bit object file format"), 608 sparc_arch_size); 609 free (list); 610 611 if (sparc_arch_size == 64 612 && max_architecture < SPARC_OPCODE_ARCH_V9) 613 max_architecture = SPARC_OPCODE_ARCH_V9; 614 } 615 break; 616 617 case OPTION_TSO: 618 sparc_memory_model = MM_TSO; 619 break; 620 621 case OPTION_PSO: 622 sparc_memory_model = MM_PSO; 623 break; 624 625 case OPTION_RMO: 626 sparc_memory_model = MM_RMO; 627 break; 628 629 case 'V': 630 print_version_id (); 631 break; 632 633 case 'Q': 634 /* Qy - do emit .comment 635 Qn - do not emit .comment. */ 636 break; 637 638 case 's': 639 /* Use .stab instead of .stab.excl. */ 640 break; 641 642 case 'q': 643 /* quick -- Native assembler does fewer checks. */ 644 break; 645 646 case 'K': 647 if (strcmp (arg, "PIC") != 0) 648 as_warn (_("Unrecognized option following -K")); 649 else 650 sparc_pic_code = 1; 651 break; 652 653 case OPTION_NO_UNDECLARED_REGS: 654 no_undeclared_regs = 1; 655 break; 656 657 case OPTION_UNDECLARED_REGS: 658 no_undeclared_regs = 0; 659 break; 660 #endif 661 662 case OPTION_RELAX: 663 sparc_relax = 1; 664 break; 665 666 case OPTION_NO_RELAX: 667 sparc_relax = 0; 668 break; 669 670 default: 671 return 0; 672 } 673 674 return 1; 675 } 676 677 void 678 md_show_usage (FILE *stream) 679 { 680 const struct sparc_arch *arch; 681 int column; 682 683 /* We don't get a chance to initialize anything before we're called, 684 so handle that now. */ 685 if (! default_init_p) 686 init_default_arch (); 687 688 fprintf (stream, _("SPARC options:\n")); 689 column = 0; 690 for (arch = &sparc_arch_table[0]; arch->name; arch++) 691 { 692 if (!arch->user_option_p) 693 continue; 694 if (arch != &sparc_arch_table[0]) 695 fprintf (stream, " | "); 696 if (column + strlen (arch->name) > 70) 697 { 698 column = 0; 699 fputc ('\n', stream); 700 } 701 column += 5 + 2 + strlen (arch->name); 702 fprintf (stream, "-A%s", arch->name); 703 } 704 for (arch = &sparc_arch_table[0]; arch->name; arch++) 705 { 706 if (!arch->user_option_p) 707 continue; 708 fprintf (stream, " | "); 709 if (column + strlen (arch->name) > 65) 710 { 711 column = 0; 712 fputc ('\n', stream); 713 } 714 column += 5 + 7 + strlen (arch->name); 715 fprintf (stream, "-xarch=%s", arch->name); 716 } 717 fprintf (stream, _("\n\ 718 specify variant of SPARC architecture\n\ 719 -bump warn when assembler switches architectures\n\ 720 -sparc ignored\n\ 721 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 722 -relax relax jumps and branches (default)\n\ 723 -no-relax avoid changing any jumps and branches\n")); 724 #ifdef OBJ_AOUT 725 fprintf (stream, _("\ 726 -k generate PIC\n")); 727 #endif 728 #ifdef OBJ_ELF 729 fprintf (stream, _("\ 730 -32 create 32 bit object file\n\ 731 -64 create 64 bit object file\n")); 732 fprintf (stream, _("\ 733 [default is %d]\n"), default_arch_size); 734 fprintf (stream, _("\ 735 -TSO use Total Store Ordering\n\ 736 -PSO use Partial Store Ordering\n\ 737 -RMO use Relaxed Memory Ordering\n")); 738 fprintf (stream, _("\ 739 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 740 fprintf (stream, _("\ 741 -KPIC generate PIC\n\ 742 -V print assembler version number\n\ 743 -undeclared-regs ignore application global register usage without\n\ 744 appropriate .register directive (default)\n\ 745 -no-undeclared-regs force error on application global register usage\n\ 746 without appropriate .register directive\n\ 747 -q ignored\n\ 748 -Qy, -Qn ignored\n\ 749 -s ignored\n")); 750 #endif 751 #ifdef SPARC_BIENDIAN 752 fprintf (stream, _("\ 753 -EL generate code for a little endian machine\n\ 754 -EB generate code for a big endian machine\n\ 755 --little-endian-data generate code for a machine having big endian\n\ 756 instructions and little endian data.\n")); 757 #endif 758 } 759 760 /* Native operand size opcode translation. */ 761 static struct 762 { 763 const char *name; 764 const char *name32; 765 const char *name64; 766 } native_op_table[] = 767 { 768 {"ldn", "ld", "ldx"}, 769 {"ldna", "lda", "ldxa"}, 770 {"stn", "st", "stx"}, 771 {"stna", "sta", "stxa"}, 772 {"slln", "sll", "sllx"}, 773 {"srln", "srl", "srlx"}, 774 {"sran", "sra", "srax"}, 775 {"casn", "cas", "casx"}, 776 {"casna", "casa", "casxa"}, 777 {"clrn", "clr", "clrx"}, 778 {NULL, NULL, NULL}, 779 }; 780 781 /* sparc64 privileged and hyperprivileged registers. */ 782 783 struct priv_reg_entry 784 { 785 const char *name; 786 int regnum; 787 }; 788 789 struct priv_reg_entry priv_reg_table[] = 790 { 791 {"tpc", 0}, 792 {"tnpc", 1}, 793 {"tstate", 2}, 794 {"tt", 3}, 795 {"tick", 4}, 796 {"tba", 5}, 797 {"pstate", 6}, 798 {"tl", 7}, 799 {"pil", 8}, 800 {"cwp", 9}, 801 {"cansave", 10}, 802 {"canrestore", 11}, 803 {"cleanwin", 12}, 804 {"otherwin", 13}, 805 {"wstate", 14}, 806 {"fq", 15}, 807 {"gl", 16}, 808 {"pmcdper", 23}, 809 {"ver", 31}, 810 {NULL, -1}, /* End marker. */ 811 }; 812 813 struct priv_reg_entry hpriv_reg_table[] = 814 { 815 {"hpstate", 0}, 816 {"htstate", 1}, 817 {"hintp", 3}, 818 {"htba", 5}, 819 {"hver", 6}, 820 {"hmcdper", 23}, 821 {"hmcddfr", 24}, 822 {"hva_mask_nz", 27}, 823 {"hstick_offset", 28}, 824 {"hstick_enable", 29}, 825 {"hstick_cmpr", 31}, 826 {NULL, -1}, /* End marker. */ 827 }; 828 829 /* v9a or later specific ancillary state registers. */ 830 831 struct priv_reg_entry v9a_asr_table[] = 832 { 833 {"tick_cmpr", 23}, 834 {"sys_tick_cmpr", 25}, 835 {"sys_tick", 24}, 836 {"stick_cmpr", 25}, 837 {"stick", 24}, 838 {"softint_clear", 21}, 839 {"softint_set", 20}, 840 {"softint", 22}, 841 {"set_softint", 20}, 842 {"pause", 27}, 843 {"pic", 17}, 844 {"pcr", 16}, 845 {"mwait", 28}, 846 {"gsr", 19}, 847 {"dcr", 18}, 848 {"cfr", 26}, 849 {"clear_softint", 21}, 850 {NULL, -1}, /* End marker. */ 851 }; 852 853 static int 854 cmp_reg_entry (const void *parg, const void *qarg) 855 { 856 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 857 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 858 859 if (p->name == q->name) 860 return 0; 861 else if (p->name == NULL) 862 return 1; 863 else if (q->name == NULL) 864 return -1; 865 else 866 return strcmp (q->name, p->name); 867 } 868 869 /* sparc %-pseudo-operations. */ 870 871 872 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */ 873 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative 874 contexts. */ 875 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */ 876 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the 877 last operand of an 878 instruction. (Generally they can appear 879 anywhere an immediate operand is 880 expected. */ 881 struct pop_entry 882 { 883 /* The name as it appears in assembler. */ 884 const char *name; 885 /* The reloc this pseudo-op translates to. */ 886 int reloc; 887 /* Flags. See F_POP_* above. */ 888 int flags; 889 }; 890 891 struct pop_entry pop_table[] = 892 { 893 { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 }, 894 { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 }, 895 { "hi", BFD_RELOC_HI22, F_POP_PCREL }, 896 { "lo", BFD_RELOC_LO10, F_POP_PCREL }, 897 { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL }, 898 { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL }, 899 { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL }, 900 { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL }, 901 { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL }, 902 { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 }, 903 { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 }, 904 { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 }, 905 { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 }, 906 { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 }, 907 { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 }, 908 { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 }, 909 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 }, 910 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 }, 911 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 }, 912 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 }, 913 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 }, 914 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 }, 915 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 }, 916 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 }, 917 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 }, 918 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 }, 919 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 }, 920 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 }, 921 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX }, 922 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, 923 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX }, 924 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, 925 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX }, 926 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX }, 927 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX }, 928 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX }, 929 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX }, 930 { NULL, 0, 0 }, 931 }; 932 933 /* Table of %-names that can appear in a sparc assembly program. This 934 table is initialized in md_begin and contains entries for each 935 privileged/hyperprivileged/alternate register and %-pseudo-op. */ 936 937 enum perc_entry_type 938 { 939 perc_entry_none = 0, 940 perc_entry_reg, 941 perc_entry_post_pop, 942 perc_entry_imm_pop 943 }; 944 945 struct perc_entry 946 { 947 /* Entry type. */ 948 enum perc_entry_type type; 949 /* Name of the %-entity. */ 950 const char *name; 951 /* strlen (name). */ 952 int len; 953 /* Value. Either a pop or a reg depending on type.*/ 954 union 955 { 956 struct pop_entry *pop; 957 struct priv_reg_entry *reg; 958 }; 959 }; 960 961 #define NUM_PERC_ENTRIES \ 962 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \ 963 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \ 964 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \ 965 + ((sizeof (pop_table) / sizeof (pop_table[0])) - 1) \ 966 + 1) 967 968 struct perc_entry perc_table[NUM_PERC_ENTRIES]; 969 970 static int 971 cmp_perc_entry (const void *parg, const void *qarg) 972 { 973 const struct perc_entry *p = (const struct perc_entry *) parg; 974 const struct perc_entry *q = (const struct perc_entry *) qarg; 975 976 if (p->name == q->name) 977 return 0; 978 else if (p->name == NULL) 979 return 1; 980 else if (q->name == NULL) 981 return -1; 982 else 983 return strcmp (q->name, p->name); 984 } 985 986 /* This function is called once, at assembler startup time. It should 987 set up all the tables, etc. that the MD part of the assembler will 988 need. */ 989 990 void 991 md_begin (void) 992 { 993 const char *retval = NULL; 994 int lose = 0; 995 unsigned int i = 0; 996 997 /* We don't get a chance to initialize anything before md_parse_option 998 is called, and it may not be called, so handle default initialization 999 now if not already done. */ 1000 if (! default_init_p) 1001 init_default_arch (); 1002 1003 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 1004 op_hash = hash_new (); 1005 1006 while (i < (unsigned int) sparc_num_opcodes) 1007 { 1008 const char *name = sparc_opcodes[i].name; 1009 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); 1010 if (retval != NULL) 1011 { 1012 as_bad (_("Internal error: can't hash `%s': %s\n"), 1013 sparc_opcodes[i].name, retval); 1014 lose = 1; 1015 } 1016 do 1017 { 1018 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 1019 { 1020 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 1021 sparc_opcodes[i].name, sparc_opcodes[i].args); 1022 lose = 1; 1023 } 1024 ++i; 1025 } 1026 while (i < (unsigned int) sparc_num_opcodes 1027 && !strcmp (sparc_opcodes[i].name, name)); 1028 } 1029 1030 for (i = 0; native_op_table[i].name; i++) 1031 { 1032 const struct sparc_opcode *insn; 1033 const char *name = ((sparc_arch_size == 32) 1034 ? native_op_table[i].name32 1035 : native_op_table[i].name64); 1036 insn = (struct sparc_opcode *) hash_find (op_hash, name); 1037 if (insn == NULL) 1038 { 1039 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 1040 name, native_op_table[i].name); 1041 lose = 1; 1042 } 1043 else 1044 { 1045 retval = hash_insert (op_hash, native_op_table[i].name, 1046 (void *) insn); 1047 if (retval != NULL) 1048 { 1049 as_bad (_("Internal error: can't hash `%s': %s\n"), 1050 sparc_opcodes[i].name, retval); 1051 lose = 1; 1052 } 1053 } 1054 } 1055 1056 if (lose) 1057 as_fatal (_("Broken assembler. No assembly attempted.")); 1058 1059 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 1060 sizeof (priv_reg_table[0]), cmp_reg_entry); 1061 qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]), 1062 sizeof (hpriv_reg_table[0]), cmp_reg_entry); 1063 qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]), 1064 sizeof (v9a_asr_table[0]), cmp_reg_entry); 1065 1066 /* If -bump, record the architecture level at which we start issuing 1067 warnings. The behaviour is different depending upon whether an 1068 architecture was explicitly specified. If it wasn't, we issue warnings 1069 for all upwards bumps. If it was, we don't start issuing warnings until 1070 we need to bump beyond the requested architecture or when we bump between 1071 conflicting architectures. */ 1072 1073 if (warn_on_bump 1074 && architecture_requested) 1075 { 1076 /* `max_architecture' records the requested architecture. 1077 Issue warnings if we go above it. */ 1078 warn_after_architecture = max_architecture; 1079 } 1080 1081 /* Find the highest architecture level that doesn't conflict with 1082 the requested one. */ 1083 1084 if (warn_on_bump 1085 || !architecture_requested) 1086 { 1087 enum sparc_opcode_arch_val current_max_architecture 1088 = max_architecture; 1089 1090 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 1091 max_architecture > warn_after_architecture; 1092 --max_architecture) 1093 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 1094 current_max_architecture)) 1095 break; 1096 } 1097 1098 /* Prepare the tables of %-pseudo-ops. */ 1099 { 1100 struct priv_reg_entry *reg_tables[] 1101 = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL}; 1102 struct priv_reg_entry **reg_table; 1103 int entry = 0; 1104 1105 /* Add registers. */ 1106 for (reg_table = reg_tables; reg_table[0]; reg_table++) 1107 { 1108 struct priv_reg_entry *reg; 1109 for (reg = *reg_table; reg->name; reg++) 1110 { 1111 struct perc_entry *p = &perc_table[entry++]; 1112 p->type = perc_entry_reg; 1113 p->name = reg->name; 1114 p->len = strlen (reg->name); 1115 p->reg = reg; 1116 } 1117 } 1118 1119 /* Add %-pseudo-ops. */ 1120 { 1121 struct pop_entry *pop; 1122 1123 for (pop = pop_table; pop->name; pop++) 1124 { 1125 struct perc_entry *p = &perc_table[entry++]; 1126 p->type = (pop->flags & F_POP_POSTFIX 1127 ? perc_entry_post_pop : perc_entry_imm_pop); 1128 p->name = pop->name; 1129 p->len = strlen (pop->name); 1130 p->pop = pop; 1131 } 1132 } 1133 1134 /* Last entry is the centinel. */ 1135 perc_table[entry].type = perc_entry_none; 1136 1137 qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]), 1138 sizeof (perc_table[0]), cmp_perc_entry); 1139 1140 } 1141 } 1142 1143 /* Called after all assembly has been done. */ 1144 1145 void 1146 sparc_md_end (void) 1147 { 1148 unsigned long mach = bfd_mach_sparc; 1149 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 1150 int hwcaps, hwcaps2; 1151 #endif 1152 1153 if (sparc_arch_size == 64) 1154 switch (current_architecture) 1155 { 1156 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 1157 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 1158 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break; 1159 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break; 1160 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break; 1161 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break; 1162 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break; 1163 default: mach = bfd_mach_sparc_v9; break; 1164 } 1165 else 1166 switch (current_architecture) 1167 { 1168 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 1169 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 1170 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 1171 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 1172 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break; 1173 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break; 1174 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break; 1175 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break; 1176 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break; 1177 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 1178 be but for now it is (since that's the way it's always been 1179 treated). */ 1180 default: break; 1181 } 1182 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 1183 1184 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 1185 hwcaps = hwcap_seen & U0xffffffff; 1186 hwcaps2 = hwcap_seen >> 32; 1187 1188 if (hwcaps) 1189 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); 1190 if (hwcaps2) 1191 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); 1192 #endif 1193 } 1194 1195 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 1196 1197 static inline int 1198 in_signed_range (bfd_signed_vma val, bfd_signed_vma max) 1199 { 1200 if (max <= 0) 1201 abort (); 1202 /* Sign-extend the value from the architecture word size, so that 1203 0xffffffff is always considered -1 on sparc32. */ 1204 if (sparc_arch_size == 32) 1205 { 1206 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 1207 val = ((val & U0xffffffff) ^ sign) - sign; 1208 } 1209 if (val > max) 1210 return 0; 1211 if (val < ~max) 1212 return 0; 1213 return 1; 1214 } 1215 1216 /* Return non-zero if VAL is in the range 0 to MAX. */ 1217 1218 static inline int 1219 in_unsigned_range (bfd_vma val, bfd_vma max) 1220 { 1221 if (val > max) 1222 return 0; 1223 return 1; 1224 } 1225 1226 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 1227 (e.g. -15 to +31). */ 1228 1229 static inline int 1230 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) 1231 { 1232 if (max <= 0) 1233 abort (); 1234 if (val > max) 1235 return 0; 1236 if (val < ~(max >> 1)) 1237 return 0; 1238 return 1; 1239 } 1240 1241 static int 1242 sparc_ffs (unsigned int mask) 1243 { 1244 int i; 1245 1246 if (mask == 0) 1247 return -1; 1248 1249 for (i = 0; (mask & 1) == 0; ++i) 1250 mask >>= 1; 1251 return i; 1252 } 1253 1254 /* Implement big shift right. */ 1255 static bfd_vma 1256 BSR (bfd_vma val, int amount) 1257 { 1258 if (sizeof (bfd_vma) <= 4 && amount >= 32) 1259 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 1260 return val >> amount; 1261 } 1262 1263 /* For communication between sparc_ip and get_expression. */ 1264 static char *expr_end; 1265 1266 /* Values for `special_case'. 1267 Instructions that require wierd handling because they're longer than 1268 4 bytes. */ 1269 #define SPECIAL_CASE_NONE 0 1270 #define SPECIAL_CASE_SET 1 1271 #define SPECIAL_CASE_SETSW 2 1272 #define SPECIAL_CASE_SETX 3 1273 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1274 #define SPECIAL_CASE_FDIV 4 1275 1276 /* Bit masks of various insns. */ 1277 #define NOP_INSN 0x01000000 1278 #define OR_INSN 0x80100000 1279 #define XOR_INSN 0x80180000 1280 #define FMOVS_INSN 0x81A00020 1281 #define SETHI_INSN 0x01000000 1282 #define SLLX_INSN 0x81281000 1283 #define SRA_INSN 0x81380000 1284 1285 /* The last instruction to be assembled. */ 1286 static const struct sparc_opcode *last_insn; 1287 /* The assembled opcode of `last_insn'. */ 1288 static unsigned long last_opcode; 1289 1290 /* Handle the set and setuw synthetic instructions. */ 1291 1292 static void 1293 synthetize_setuw (const struct sparc_opcode *insn) 1294 { 1295 int need_hi22_p = 0; 1296 int rd = (the_insn.opcode & RD (~0)) >> 25; 1297 1298 if (the_insn.exp.X_op == O_constant) 1299 { 1300 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1301 { 1302 if (sizeof (offsetT) > 4 1303 && (the_insn.exp.X_add_number < 0 1304 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1305 as_warn (_("set: number not in 0..4294967295 range")); 1306 } 1307 else 1308 { 1309 if (sizeof (offsetT) > 4 1310 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1311 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1312 as_warn (_("set: number not in -2147483648..4294967295 range")); 1313 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1314 } 1315 } 1316 1317 /* See if operand is absolute and small; skip sethi if so. */ 1318 if (the_insn.exp.X_op != O_constant 1319 || the_insn.exp.X_add_number >= (1 << 12) 1320 || the_insn.exp.X_add_number < -(1 << 12)) 1321 { 1322 the_insn.opcode = (SETHI_INSN | RD (rd) 1323 | ((the_insn.exp.X_add_number >> 10) 1324 & (the_insn.exp.X_op == O_constant 1325 ? 0x3fffff : 0))); 1326 the_insn.reloc = (the_insn.exp.X_op != O_constant 1327 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1328 output_insn (insn, &the_insn); 1329 need_hi22_p = 1; 1330 } 1331 1332 /* See if operand has no low-order bits; skip OR if so. */ 1333 if (the_insn.exp.X_op != O_constant 1334 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1335 || ! need_hi22_p) 1336 { 1337 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1338 | RD (rd) | IMMED 1339 | (the_insn.exp.X_add_number 1340 & (the_insn.exp.X_op != O_constant 1341 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1342 the_insn.reloc = (the_insn.exp.X_op != O_constant 1343 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1344 output_insn (insn, &the_insn); 1345 } 1346 } 1347 1348 /* Handle the setsw synthetic instruction. */ 1349 1350 static void 1351 synthetize_setsw (const struct sparc_opcode *insn) 1352 { 1353 int low32, rd, opc; 1354 1355 rd = (the_insn.opcode & RD (~0)) >> 25; 1356 1357 if (the_insn.exp.X_op != O_constant) 1358 { 1359 synthetize_setuw (insn); 1360 1361 /* Need to sign extend it. */ 1362 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1363 the_insn.reloc = BFD_RELOC_NONE; 1364 output_insn (insn, &the_insn); 1365 return; 1366 } 1367 1368 if (sizeof (offsetT) > 4 1369 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1370 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1371 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1372 1373 low32 = the_insn.exp.X_add_number; 1374 1375 if (low32 >= 0) 1376 { 1377 synthetize_setuw (insn); 1378 return; 1379 } 1380 1381 opc = OR_INSN; 1382 1383 the_insn.reloc = BFD_RELOC_NONE; 1384 /* See if operand is absolute and small; skip sethi if so. */ 1385 if (low32 < -(1 << 12)) 1386 { 1387 the_insn.opcode = (SETHI_INSN | RD (rd) 1388 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1389 output_insn (insn, &the_insn); 1390 low32 = 0x1c00 | (low32 & 0x3ff); 1391 opc = RS1 (rd) | XOR_INSN; 1392 } 1393 1394 the_insn.opcode = (opc | RD (rd) | IMMED 1395 | (low32 & 0x1fff)); 1396 output_insn (insn, &the_insn); 1397 } 1398 1399 /* Handle the setx synthetic instruction. */ 1400 1401 static void 1402 synthetize_setx (const struct sparc_opcode *insn) 1403 { 1404 int upper32, lower32; 1405 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1406 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1407 int upper_dstreg; 1408 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1409 int need_xor10_p = 0; 1410 1411 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1412 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1413 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1414 #undef SIGNEXT32 1415 1416 upper_dstreg = tmpreg; 1417 /* The tmp reg should not be the dst reg. */ 1418 if (tmpreg == dstreg) 1419 as_warn (_("setx: temporary register same as destination register")); 1420 1421 /* ??? Obviously there are other optimizations we can do 1422 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1423 doing some of these. Later. If you do change things, try to 1424 change all of this to be table driven as well. */ 1425 /* What to output depends on the number if it's constant. 1426 Compute that first, then output what we've decided upon. */ 1427 if (the_insn.exp.X_op != O_constant) 1428 { 1429 if (sparc_arch_size == 32) 1430 { 1431 /* When arch size is 32, we want setx to be equivalent 1432 to setuw for anything but constants. */ 1433 the_insn.exp.X_add_number &= 0xffffffff; 1434 synthetize_setuw (insn); 1435 return; 1436 } 1437 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1438 lower32 = 0; 1439 upper32 = 0; 1440 } 1441 else 1442 { 1443 /* Reset X_add_number, we've extracted it as upper32/lower32. 1444 Otherwise fixup_segment will complain about not being able to 1445 write an 8 byte number in a 4 byte field. */ 1446 the_insn.exp.X_add_number = 0; 1447 1448 /* Only need hh22 if `or' insn can't handle constant. */ 1449 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1450 need_hh22_p = 1; 1451 1452 /* Does bottom part (after sethi) have bits? */ 1453 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1454 /* No hh22, but does upper32 still have bits we can't set 1455 from lower32? */ 1456 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1457 need_hm10_p = 1; 1458 1459 /* If the lower half is all zero, we build the upper half directly 1460 into the dst reg. */ 1461 if (lower32 != 0 1462 /* Need lower half if number is zero or 0xffffffff00000000. */ 1463 || (! need_hh22_p && ! need_hm10_p)) 1464 { 1465 /* No need for sethi if `or' insn can handle constant. */ 1466 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1467 /* Note that we can't use a negative constant in the `or' 1468 insn unless the upper 32 bits are all ones. */ 1469 || (lower32 < 0 && upper32 != -1) 1470 || (lower32 >= 0 && upper32 == -1)) 1471 need_hi22_p = 1; 1472 1473 if (need_hi22_p && upper32 == -1) 1474 need_xor10_p = 1; 1475 1476 /* Does bottom part (after sethi) have bits? */ 1477 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1478 /* No sethi. */ 1479 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1480 /* Need `or' if we didn't set anything else. */ 1481 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1482 need_lo10_p = 1; 1483 } 1484 else 1485 /* Output directly to dst reg if lower 32 bits are all zero. */ 1486 upper_dstreg = dstreg; 1487 } 1488 1489 if (!upper_dstreg && dstreg) 1490 as_warn (_("setx: illegal temporary register g0")); 1491 1492 if (need_hh22_p) 1493 { 1494 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1495 | ((upper32 >> 10) & 0x3fffff)); 1496 the_insn.reloc = (the_insn.exp.X_op != O_constant 1497 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1498 output_insn (insn, &the_insn); 1499 } 1500 1501 if (need_hi22_p) 1502 { 1503 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1504 | (((need_xor10_p ? ~lower32 : lower32) 1505 >> 10) & 0x3fffff)); 1506 the_insn.reloc = (the_insn.exp.X_op != O_constant 1507 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1508 output_insn (insn, &the_insn); 1509 } 1510 1511 if (need_hm10_p) 1512 { 1513 the_insn.opcode = (OR_INSN 1514 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1515 | RD (upper_dstreg) 1516 | IMMED 1517 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1518 the_insn.reloc = (the_insn.exp.X_op != O_constant 1519 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1520 output_insn (insn, &the_insn); 1521 } 1522 1523 if (need_lo10_p) 1524 { 1525 /* FIXME: One nice optimization to do here is to OR the low part 1526 with the highpart if hi22 isn't needed and the low part is 1527 positive. */ 1528 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1529 | RD (dstreg) 1530 | IMMED 1531 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1532 the_insn.reloc = (the_insn.exp.X_op != O_constant 1533 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1534 output_insn (insn, &the_insn); 1535 } 1536 1537 /* If we needed to build the upper part, shift it into place. */ 1538 if (need_hh22_p || need_hm10_p) 1539 { 1540 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1541 | IMMED | 32); 1542 the_insn.reloc = BFD_RELOC_NONE; 1543 output_insn (insn, &the_insn); 1544 } 1545 1546 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1547 if (need_xor10_p) 1548 { 1549 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1550 | 0x1c00 | (lower32 & 0x3ff)); 1551 the_insn.reloc = BFD_RELOC_NONE; 1552 output_insn (insn, &the_insn); 1553 } 1554 1555 /* If we needed to build both upper and lower parts, OR them together. */ 1556 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1557 { 1558 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1559 | RD (dstreg)); 1560 the_insn.reloc = BFD_RELOC_NONE; 1561 output_insn (insn, &the_insn); 1562 } 1563 } 1564 1565 /* Main entry point to assemble one instruction. */ 1566 1567 void 1568 md_assemble (char *str) 1569 { 1570 const struct sparc_opcode *insn; 1571 int special_case; 1572 1573 know (str); 1574 special_case = sparc_ip (str, &insn); 1575 if (insn == NULL) 1576 return; 1577 1578 /* We warn about attempts to put a floating point branch in a delay slot, 1579 unless the delay slot has been annulled. */ 1580 if (last_insn != NULL 1581 && (insn->flags & F_FBR) != 0 1582 && (last_insn->flags & F_DELAYED) != 0 1583 /* ??? This test isn't completely accurate. We assume anything with 1584 F_{UNBR,CONDBR,FBR} set is annullable. */ 1585 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1586 || (last_opcode & ANNUL) == 0)) 1587 as_warn (_("FP branch in delay slot")); 1588 1589 /* SPARC before v8 requires a nop instruction between a floating 1590 point instruction and a floating point branch. SPARCv8 requires 1591 a nop only immediately after FPop2 (fcmp*) instructions. 1592 We insert one automatically, with a warning. 1593 */ 1594 if (last_insn != NULL 1595 && (insn->flags & F_FBR) != 0 1596 && (last_insn->flags & F_FLOAT) != 0 1597 && (max_architecture < SPARC_OPCODE_ARCH_V8 || 1598 (max_architecture < SPARC_OPCODE_ARCH_V9 && 1599 strncmp(last_insn->name, "fcmp", 4) == 0))) 1600 { 1601 struct sparc_it nop_insn; 1602 1603 nop_insn.opcode = NOP_INSN; 1604 nop_insn.reloc = BFD_RELOC_NONE; 1605 output_insn (insn, &nop_insn); 1606 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1607 } 1608 1609 switch (special_case) 1610 { 1611 case SPECIAL_CASE_NONE: 1612 /* Normal insn. */ 1613 output_insn (insn, &the_insn); 1614 break; 1615 1616 case SPECIAL_CASE_SETSW: 1617 synthetize_setsw (insn); 1618 break; 1619 1620 case SPECIAL_CASE_SET: 1621 synthetize_setuw (insn); 1622 break; 1623 1624 case SPECIAL_CASE_SETX: 1625 synthetize_setx (insn); 1626 break; 1627 1628 case SPECIAL_CASE_FDIV: 1629 { 1630 int rd = (the_insn.opcode >> 25) & 0x1f; 1631 1632 output_insn (insn, &the_insn); 1633 1634 /* According to information leaked from Sun, the "fdiv" instructions 1635 on early SPARC machines would produce incorrect results sometimes. 1636 The workaround is to add an fmovs of the destination register to 1637 itself just after the instruction. This was true on machines 1638 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1639 gas_assert (the_insn.reloc == BFD_RELOC_NONE); 1640 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1641 output_insn (insn, &the_insn); 1642 return; 1643 } 1644 1645 default: 1646 as_fatal (_("failed special case insn sanity check")); 1647 } 1648 } 1649 1650 static const char * 1651 get_hwcap_name (bfd_uint64_t mask) 1652 { 1653 if (mask & HWCAP_MUL32) 1654 return "mul32"; 1655 if (mask & HWCAP_DIV32) 1656 return "div32"; 1657 if (mask & HWCAP_FSMULD) 1658 return "fsmuld"; 1659 if (mask & HWCAP_V8PLUS) 1660 return "v8plus"; 1661 if (mask & HWCAP_POPC) 1662 return "popc"; 1663 if (mask & HWCAP_VIS) 1664 return "vis"; 1665 if (mask & HWCAP_VIS2) 1666 return "vis2"; 1667 if (mask & HWCAP_ASI_BLK_INIT) 1668 return "ASIBlkInit"; 1669 if (mask & HWCAP_FMAF) 1670 return "fmaf"; 1671 if (mask & HWCAP_VIS3) 1672 return "vis3"; 1673 if (mask & HWCAP_HPC) 1674 return "hpc"; 1675 if (mask & HWCAP_RANDOM) 1676 return "random"; 1677 if (mask & HWCAP_TRANS) 1678 return "trans"; 1679 if (mask & HWCAP_FJFMAU) 1680 return "fjfmau"; 1681 if (mask & HWCAP_IMA) 1682 return "ima"; 1683 if (mask & HWCAP_ASI_CACHE_SPARING) 1684 return "cspare"; 1685 if (mask & HWCAP_AES) 1686 return "aes"; 1687 if (mask & HWCAP_DES) 1688 return "des"; 1689 if (mask & HWCAP_KASUMI) 1690 return "kasumi"; 1691 if (mask & HWCAP_CAMELLIA) 1692 return "camellia"; 1693 if (mask & HWCAP_MD5) 1694 return "md5"; 1695 if (mask & HWCAP_SHA1) 1696 return "sha1"; 1697 if (mask & HWCAP_SHA256) 1698 return "sha256"; 1699 if (mask & HWCAP_SHA512) 1700 return "sha512"; 1701 if (mask & HWCAP_MPMUL) 1702 return "mpmul"; 1703 if (mask & HWCAP_MONT) 1704 return "mont"; 1705 if (mask & HWCAP_PAUSE) 1706 return "pause"; 1707 if (mask & HWCAP_CBCOND) 1708 return "cbcond"; 1709 if (mask & HWCAP_CRC32C) 1710 return "crc32c"; 1711 1712 mask = mask >> 32; 1713 if (mask & HWCAP2_FJATHPLUS) 1714 return "fjathplus"; 1715 if (mask & HWCAP2_VIS3B) 1716 return "vis3b"; 1717 if (mask & HWCAP2_ADP) 1718 return "adp"; 1719 if (mask & HWCAP2_SPARC5) 1720 return "sparc5"; 1721 if (mask & HWCAP2_MWAIT) 1722 return "mwait"; 1723 if (mask & HWCAP2_XMPMUL) 1724 return "xmpmul"; 1725 if (mask & HWCAP2_XMONT) 1726 return "xmont"; 1727 if (mask & HWCAP2_NSEC) 1728 return "nsec"; 1729 1730 return "UNKNOWN"; 1731 } 1732 1733 /* Subroutine of md_assemble to do the actual parsing. */ 1734 1735 static int 1736 sparc_ip (char *str, const struct sparc_opcode **pinsn) 1737 { 1738 const char *error_message = ""; 1739 char *s; 1740 const char *args; 1741 char c; 1742 const struct sparc_opcode *insn; 1743 char *argsStart; 1744 unsigned long opcode; 1745 unsigned int mask = 0; 1746 int match = 0; 1747 int comma = 0; 1748 int v9_arg_p; 1749 int special_case = SPECIAL_CASE_NONE; 1750 1751 s = str; 1752 if (ISLOWER (*s)) 1753 { 1754 do 1755 ++s; 1756 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); 1757 } 1758 1759 switch (*s) 1760 { 1761 case '\0': 1762 break; 1763 1764 case ',': 1765 comma = 1; 1766 /* Fall through. */ 1767 1768 case ' ': 1769 *s++ = '\0'; 1770 break; 1771 1772 default: 1773 as_bad (_("Unknown opcode: `%s'"), str); 1774 *pinsn = NULL; 1775 return special_case; 1776 } 1777 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1778 *pinsn = insn; 1779 if (insn == NULL) 1780 { 1781 as_bad (_("Unknown opcode: `%s'"), str); 1782 return special_case; 1783 } 1784 if (comma) 1785 { 1786 *--s = ','; 1787 } 1788 1789 argsStart = s; 1790 for (;;) 1791 { 1792 opcode = insn->match; 1793 memset (&the_insn, '\0', sizeof (the_insn)); 1794 the_insn.reloc = BFD_RELOC_NONE; 1795 v9_arg_p = 0; 1796 1797 /* Build the opcode, checking as we go to make sure that the 1798 operands match. */ 1799 for (args = insn->args;; ++args) 1800 { 1801 switch (*args) 1802 { 1803 case 'K': 1804 { 1805 int kmask = 0; 1806 1807 /* Parse a series of masks. */ 1808 if (*s == '#') 1809 { 1810 while (*s == '#') 1811 { 1812 int jmask; 1813 1814 if (! parse_keyword_arg (sparc_encode_membar, &s, 1815 &jmask)) 1816 { 1817 error_message = _(": invalid membar mask name"); 1818 goto error; 1819 } 1820 kmask |= jmask; 1821 while (*s == ' ') 1822 ++s; 1823 if (*s == '|' || *s == '+') 1824 ++s; 1825 while (*s == ' ') 1826 ++s; 1827 } 1828 } 1829 else 1830 { 1831 if (! parse_const_expr_arg (&s, &kmask)) 1832 { 1833 error_message = _(": invalid membar mask expression"); 1834 goto error; 1835 } 1836 if (kmask < 0 || kmask > 127) 1837 { 1838 error_message = _(": invalid membar mask number"); 1839 goto error; 1840 } 1841 } 1842 1843 opcode |= MEMBAR (kmask); 1844 continue; 1845 } 1846 1847 case '3': 1848 { 1849 int smask = 0; 1850 1851 if (! parse_const_expr_arg (&s, &smask)) 1852 { 1853 error_message = _(": invalid siam mode expression"); 1854 goto error; 1855 } 1856 if (smask < 0 || smask > 7) 1857 { 1858 error_message = _(": invalid siam mode number"); 1859 goto error; 1860 } 1861 opcode |= smask; 1862 continue; 1863 } 1864 1865 case '*': 1866 { 1867 int fcn = 0; 1868 1869 /* Parse a prefetch function. */ 1870 if (*s == '#') 1871 { 1872 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1873 { 1874 error_message = _(": invalid prefetch function name"); 1875 goto error; 1876 } 1877 } 1878 else 1879 { 1880 if (! parse_const_expr_arg (&s, &fcn)) 1881 { 1882 error_message = _(": invalid prefetch function expression"); 1883 goto error; 1884 } 1885 if (fcn < 0 || fcn > 31) 1886 { 1887 error_message = _(": invalid prefetch function number"); 1888 goto error; 1889 } 1890 } 1891 opcode |= RD (fcn); 1892 continue; 1893 } 1894 1895 case '!': 1896 case '?': 1897 /* Parse a sparc64 privileged register. */ 1898 if (*s == '%') 1899 { 1900 struct priv_reg_entry *p; 1901 unsigned int len = 9999999; /* Init to make gcc happy. */ 1902 1903 s += 1; 1904 for (p = priv_reg_table; p->name; p++) 1905 if (p->name[0] == s[0]) 1906 { 1907 len = strlen (p->name); 1908 if (strncmp (p->name, s, len) == 0) 1909 break; 1910 } 1911 1912 if (!p->name) 1913 { 1914 error_message = _(": unrecognizable privileged register"); 1915 goto error; 1916 } 1917 1918 if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1919 { 1920 error_message = _(": unrecognizable privileged register"); 1921 goto error; 1922 } 1923 1924 s += len; 1925 continue; 1926 } 1927 else 1928 { 1929 error_message = _(": unrecognizable privileged register"); 1930 goto error; 1931 } 1932 1933 case '$': 1934 case '%': 1935 /* Parse a sparc64 hyperprivileged register. */ 1936 if (*s == '%') 1937 { 1938 struct priv_reg_entry *p; 1939 unsigned int len = 9999999; /* Init to make gcc happy. */ 1940 1941 s += 1; 1942 for (p = hpriv_reg_table; p->name; p++) 1943 if (p->name[0] == s[0]) 1944 { 1945 len = strlen (p->name); 1946 if (strncmp (p->name, s, len) == 0) 1947 break; 1948 } 1949 1950 if (!p->name) 1951 { 1952 error_message = _(": unrecognizable hyperprivileged register"); 1953 goto error; 1954 } 1955 1956 if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1957 { 1958 error_message = _(": unrecognizable hyperprivileged register"); 1959 goto error; 1960 } 1961 1962 s += len; 1963 continue; 1964 } 1965 else 1966 { 1967 error_message = _(": unrecognizable hyperprivileged register"); 1968 goto error; 1969 } 1970 1971 case '_': 1972 case '/': 1973 /* Parse a v9a or later ancillary state register. */ 1974 if (*s == '%') 1975 { 1976 struct priv_reg_entry *p; 1977 unsigned int len = 9999999; /* Init to make gcc happy. */ 1978 1979 s += 1; 1980 for (p = v9a_asr_table; p->name; p++) 1981 if (p->name[0] == s[0]) 1982 { 1983 len = strlen (p->name); 1984 if (strncmp (p->name, s, len) == 0) 1985 break; 1986 } 1987 1988 if (!p->name) 1989 { 1990 error_message = _(": unrecognizable ancillary state register"); 1991 goto error; 1992 } 1993 1994 if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1995 { 1996 error_message = _(": unrecognizable ancillary state register"); 1997 goto error; 1998 } 1999 2000 s += len; 2001 continue; 2002 } 2003 else 2004 { 2005 error_message = _(": unrecognizable ancillary state register"); 2006 goto error; 2007 } 2008 2009 case 'M': 2010 case 'm': 2011 if (strncmp (s, "%asr", 4) == 0) 2012 { 2013 s += 4; 2014 2015 if (ISDIGIT (*s)) 2016 { 2017 long num = 0; 2018 2019 while (ISDIGIT (*s)) 2020 { 2021 num = num * 10 + *s - '0'; 2022 ++s; 2023 } 2024 2025 /* We used to check here for the asr number to 2026 be between 16 and 31 in V9 and later, as 2027 mandated by the section C.1.1 "Register 2028 Names" in the SPARC spec. However, we 2029 decided to remove this restriction as a) it 2030 introduces problems when new V9 asr registers 2031 are introduced, b) the Solaris assembler 2032 doesn't implement this restriction and c) the 2033 restriction will go away in future revisions 2034 of the Oracle SPARC Architecture. */ 2035 2036 if (num < 0 || 31 < num) 2037 { 2038 error_message = _(": asr number must be between 0 and 31"); 2039 goto error; 2040 } 2041 2042 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 2043 continue; 2044 } 2045 else 2046 { 2047 error_message = _(": expecting %asrN"); 2048 goto error; 2049 } 2050 } /* if %asr */ 2051 break; 2052 2053 case 'I': 2054 the_insn.reloc = BFD_RELOC_SPARC_11; 2055 goto immediate; 2056 2057 case 'j': 2058 the_insn.reloc = BFD_RELOC_SPARC_10; 2059 goto immediate; 2060 2061 case ')': 2062 if (*s == ' ') 2063 s++; 2064 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) 2065 || ISDIGIT (*s)) 2066 { 2067 long num = 0; 2068 2069 if (s[0] == '0' && s[1] == 'x') 2070 { 2071 s += 2; 2072 while (ISXDIGIT (*s)) 2073 { 2074 num <<= 4; 2075 num |= hex_value (*s); 2076 ++s; 2077 } 2078 } 2079 else 2080 { 2081 while (ISDIGIT (*s)) 2082 { 2083 num = num * 10 + *s - '0'; 2084 ++s; 2085 } 2086 } 2087 if (num < 0 || num > 31) 2088 { 2089 error_message = _(": crypto immediate must be between 0 and 31"); 2090 goto error; 2091 } 2092 2093 opcode |= RS3 (num); 2094 continue; 2095 } 2096 else 2097 { 2098 error_message = _(": expecting crypto immediate"); 2099 goto error; 2100 } 2101 2102 case 'X': 2103 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 2104 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2105 the_insn.reloc = BFD_RELOC_SPARC_5; 2106 else 2107 the_insn.reloc = BFD_RELOC_SPARC13; 2108 /* These fields are unsigned, but for upward compatibility, 2109 allow negative values as well. */ 2110 goto immediate; 2111 2112 case 'Y': 2113 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 2114 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2115 the_insn.reloc = BFD_RELOC_SPARC_6; 2116 else 2117 the_insn.reloc = BFD_RELOC_SPARC13; 2118 /* These fields are unsigned, but for upward compatibility, 2119 allow negative values as well. */ 2120 goto immediate; 2121 2122 case 'k': 2123 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 2124 the_insn.pcrel = 1; 2125 goto immediate; 2126 2127 case '=': 2128 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; 2129 the_insn.pcrel = 1; 2130 goto immediate; 2131 2132 case 'G': 2133 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 2134 the_insn.pcrel = 1; 2135 goto immediate; 2136 2137 case 'N': 2138 if (*s == 'p' && s[1] == 'n') 2139 { 2140 s += 2; 2141 continue; 2142 } 2143 break; 2144 2145 case 'T': 2146 if (*s == 'p' && s[1] == 't') 2147 { 2148 s += 2; 2149 continue; 2150 } 2151 break; 2152 2153 case 'z': 2154 if (*s == ' ') 2155 { 2156 ++s; 2157 } 2158 if ((strncmp (s, "%icc", 4) == 0) 2159 || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) 2160 { 2161 s += 4; 2162 continue; 2163 } 2164 break; 2165 2166 case 'Z': 2167 if (*s == ' ') 2168 { 2169 ++s; 2170 } 2171 if ((strncmp (s, "%xcc", 4) == 0) 2172 || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) 2173 { 2174 s += 4; 2175 continue; 2176 } 2177 break; 2178 2179 case '6': 2180 if (*s == ' ') 2181 { 2182 ++s; 2183 } 2184 if (strncmp (s, "%fcc0", 5) == 0) 2185 { 2186 s += 5; 2187 continue; 2188 } 2189 break; 2190 2191 case '7': 2192 if (*s == ' ') 2193 { 2194 ++s; 2195 } 2196 if (strncmp (s, "%fcc1", 5) == 0) 2197 { 2198 s += 5; 2199 continue; 2200 } 2201 break; 2202 2203 case '8': 2204 if (*s == ' ') 2205 { 2206 ++s; 2207 } 2208 if (strncmp (s, "%fcc2", 5) == 0) 2209 { 2210 s += 5; 2211 continue; 2212 } 2213 break; 2214 2215 case '9': 2216 if (*s == ' ') 2217 { 2218 ++s; 2219 } 2220 if (strncmp (s, "%fcc3", 5) == 0) 2221 { 2222 s += 5; 2223 continue; 2224 } 2225 break; 2226 2227 case 'P': 2228 if (strncmp (s, "%pc", 3) == 0) 2229 { 2230 s += 3; 2231 continue; 2232 } 2233 break; 2234 2235 case 'W': 2236 if (strncmp (s, "%tick", 5) == 0) 2237 { 2238 s += 5; 2239 continue; 2240 } 2241 break; 2242 2243 case '\0': /* End of args. */ 2244 if (s[0] == ',' && s[1] == '%') 2245 { 2246 char *s1; 2247 int npar = 0; 2248 const struct perc_entry *p; 2249 2250 for (p = perc_table; p->type != perc_entry_none; p++) 2251 if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg) 2252 && strncmp (s + 2, p->name, p->len) == 0) 2253 break; 2254 if (p->type == perc_entry_none || p->type == perc_entry_reg) 2255 break; 2256 2257 if (s[p->len + 2] != '(') 2258 { 2259 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2260 return special_case; 2261 } 2262 2263 if (! (p->pop->flags & F_POP_TLS_CALL) 2264 && the_insn.reloc != BFD_RELOC_NONE) 2265 { 2266 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 2267 p->name); 2268 return special_case; 2269 } 2270 2271 if ((p->pop->flags & F_POP_TLS_CALL) 2272 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 2273 || the_insn.exp.X_add_number != 0 2274 || the_insn.exp.X_add_symbol 2275 != symbol_find_or_make ("__tls_get_addr"))) 2276 { 2277 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 2278 p->name); 2279 return special_case; 2280 } 2281 2282 the_insn.reloc = p->pop->reloc; 2283 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2284 s += p->len + 3; 2285 2286 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2287 if (*s1 == '(') 2288 npar++; 2289 else if (*s1 == ')') 2290 { 2291 if (!npar) 2292 break; 2293 npar--; 2294 } 2295 2296 if (*s1 != ')') 2297 { 2298 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2299 return special_case; 2300 } 2301 2302 *s1 = '\0'; 2303 (void) get_expression (s); 2304 *s1 = ')'; 2305 s = s1 + 1; 2306 } 2307 if (*s == '\0') 2308 match = 1; 2309 break; 2310 2311 case '+': 2312 if (*s == '+') 2313 { 2314 ++s; 2315 continue; 2316 } 2317 if (*s == '-') 2318 { 2319 continue; 2320 } 2321 break; 2322 2323 case '[': /* These must match exactly. */ 2324 case ']': 2325 case ',': 2326 case ' ': 2327 if (*s++ == *args) 2328 continue; 2329 break; 2330 2331 case '#': /* Must be at least one digit. */ 2332 if (ISDIGIT (*s++)) 2333 { 2334 while (ISDIGIT (*s)) 2335 { 2336 ++s; 2337 } 2338 continue; 2339 } 2340 break; 2341 2342 case 'C': /* Coprocessor state register. */ 2343 if (strncmp (s, "%csr", 4) == 0) 2344 { 2345 s += 4; 2346 continue; 2347 } 2348 break; 2349 2350 case 'b': /* Next operand is a coprocessor register. */ 2351 case 'c': 2352 case 'D': 2353 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 2354 { 2355 mask = *s++; 2356 if (ISDIGIT (*s)) 2357 { 2358 mask = 10 * (mask - '0') + (*s++ - '0'); 2359 if (mask >= 32) 2360 { 2361 break; 2362 } 2363 } 2364 else 2365 { 2366 mask -= '0'; 2367 } 2368 switch (*args) 2369 { 2370 2371 case 'b': 2372 opcode |= mask << 14; 2373 continue; 2374 2375 case 'c': 2376 opcode |= mask; 2377 continue; 2378 2379 case 'D': 2380 opcode |= mask << 25; 2381 continue; 2382 } 2383 } 2384 break; 2385 2386 case 'r': /* next operand must be a register */ 2387 case 'O': 2388 case '1': 2389 case '2': 2390 case 'd': 2391 if (*s++ == '%') 2392 { 2393 switch (c = *s++) 2394 { 2395 2396 case 'f': /* frame pointer */ 2397 if (*s++ == 'p') 2398 { 2399 mask = 0x1e; 2400 break; 2401 } 2402 goto error; 2403 2404 case 'g': /* global register */ 2405 c = *s++; 2406 if (isoctal (c)) 2407 { 2408 mask = c - '0'; 2409 break; 2410 } 2411 goto error; 2412 2413 case 'i': /* in register */ 2414 c = *s++; 2415 if (isoctal (c)) 2416 { 2417 mask = c - '0' + 24; 2418 break; 2419 } 2420 goto error; 2421 2422 case 'l': /* local register */ 2423 c = *s++; 2424 if (isoctal (c)) 2425 { 2426 mask = (c - '0' + 16); 2427 break; 2428 } 2429 goto error; 2430 2431 case 'o': /* out register */ 2432 c = *s++; 2433 if (isoctal (c)) 2434 { 2435 mask = (c - '0' + 8); 2436 break; 2437 } 2438 goto error; 2439 2440 case 's': /* stack pointer */ 2441 if (*s++ == 'p') 2442 { 2443 mask = 0xe; 2444 break; 2445 } 2446 goto error; 2447 2448 case 'r': /* any register */ 2449 if (!ISDIGIT ((c = *s++))) 2450 { 2451 goto error; 2452 } 2453 /* FALLTHROUGH */ 2454 case '0': 2455 case '1': 2456 case '2': 2457 case '3': 2458 case '4': 2459 case '5': 2460 case '6': 2461 case '7': 2462 case '8': 2463 case '9': 2464 if (ISDIGIT (*s)) 2465 { 2466 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2467 { 2468 goto error; 2469 } 2470 } 2471 else 2472 { 2473 c -= '0'; 2474 } 2475 mask = c; 2476 break; 2477 2478 default: 2479 goto error; 2480 } 2481 2482 if ((mask & ~1) == 2 && sparc_arch_size == 64 2483 && no_undeclared_regs && ! globals[mask]) 2484 as_bad (_("detected global register use not covered by .register pseudo-op")); 2485 2486 /* Got the register, now figure out where 2487 it goes in the opcode. */ 2488 switch (*args) 2489 { 2490 case '1': 2491 opcode |= mask << 14; 2492 continue; 2493 2494 case '2': 2495 opcode |= mask; 2496 continue; 2497 2498 case 'd': 2499 opcode |= mask << 25; 2500 continue; 2501 2502 case 'r': 2503 opcode |= (mask << 25) | (mask << 14); 2504 continue; 2505 2506 case 'O': 2507 opcode |= (mask << 25) | (mask << 0); 2508 continue; 2509 } 2510 } 2511 break; 2512 2513 case 'e': /* next operand is a floating point register */ 2514 case 'v': 2515 case 'V': 2516 2517 case 'f': 2518 case 'B': 2519 case 'R': 2520 2521 case '4': 2522 case '5': 2523 2524 case 'g': 2525 case 'H': 2526 case 'J': 2527 case '}': 2528 { 2529 char format; 2530 2531 if (*s++ == '%' 2532 && ((format = *s) == 'f' 2533 || format == 'd' 2534 || format == 'q') 2535 && ISDIGIT (*++s)) 2536 { 2537 for (mask = 0; ISDIGIT (*s); ++s) 2538 { 2539 mask = 10 * mask + (*s - '0'); 2540 } /* read the number */ 2541 2542 if ((*args == 'v' 2543 || *args == 'B' 2544 || *args == '5' 2545 || *args == 'H' 2546 || format == 'd') 2547 && (mask & 1)) 2548 { 2549 /* register must be even numbered */ 2550 break; 2551 } 2552 2553 if ((*args == 'V' 2554 || *args == 'R' 2555 || *args == 'J' 2556 || format == 'q') 2557 && (mask & 3)) 2558 { 2559 /* register must be multiple of 4 */ 2560 break; 2561 } 2562 2563 if (mask >= 64) 2564 { 2565 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2566 error_message = _(": There are only 64 f registers; [0-63]"); 2567 else 2568 error_message = _(": There are only 32 f registers; [0-31]"); 2569 goto error; 2570 } /* on error */ 2571 else if (mask >= 32) 2572 { 2573 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2574 { 2575 if (*args == 'e' || *args == 'f' || *args == 'g') 2576 { 2577 error_message 2578 = _(": There are only 32 single precision f registers; [0-31]"); 2579 goto error; 2580 } 2581 v9_arg_p = 1; 2582 mask -= 31; /* wrap high bit */ 2583 } 2584 else 2585 { 2586 error_message = _(": There are only 32 f registers; [0-31]"); 2587 goto error; 2588 } 2589 } 2590 } 2591 else 2592 { 2593 break; 2594 } /* if not an 'f' register. */ 2595 2596 if (*args == '}' && mask != RS2 (opcode)) 2597 { 2598 error_message 2599 = _(": Instruction requires frs2 and frsd must be the same register"); 2600 goto error; 2601 } 2602 2603 switch (*args) 2604 { 2605 case 'v': 2606 case 'V': 2607 case 'e': 2608 opcode |= RS1 (mask); 2609 continue; 2610 2611 case 'f': 2612 case 'B': 2613 case 'R': 2614 opcode |= RS2 (mask); 2615 continue; 2616 2617 case '4': 2618 case '5': 2619 opcode |= RS3 (mask); 2620 continue; 2621 2622 case 'g': 2623 case 'H': 2624 case 'J': 2625 case '}': 2626 opcode |= RD (mask); 2627 continue; 2628 } /* Pack it in. */ 2629 2630 know (0); 2631 break; 2632 } /* float arg */ 2633 2634 case 'F': 2635 if (strncmp (s, "%fsr", 4) == 0) 2636 { 2637 s += 4; 2638 continue; 2639 } 2640 break; 2641 2642 case '(': 2643 if (strncmp (s, "%efsr", 5) == 0) 2644 { 2645 s += 5; 2646 continue; 2647 } 2648 break; 2649 2650 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2651 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2652 goto immediate; 2653 2654 case 'l': /* 22 bit PC relative immediate */ 2655 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2656 the_insn.pcrel = 1; 2657 goto immediate; 2658 2659 case 'L': /* 30 bit immediate */ 2660 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2661 the_insn.pcrel = 1; 2662 goto immediate; 2663 2664 case 'h': 2665 case 'n': /* 22 bit immediate */ 2666 the_insn.reloc = BFD_RELOC_SPARC22; 2667 goto immediate; 2668 2669 case 'i': /* 13 bit immediate */ 2670 the_insn.reloc = BFD_RELOC_SPARC13; 2671 2672 /* fallthrough */ 2673 2674 immediate: 2675 if (*s == ' ') 2676 s++; 2677 2678 { 2679 char *s1; 2680 const char *op_arg = NULL; 2681 static expressionS op_exp; 2682 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2683 2684 /* Check for %hi, etc. */ 2685 if (*s == '%') 2686 { 2687 const struct perc_entry *p; 2688 2689 for (p = perc_table; p->type != perc_entry_none; p++) 2690 if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg) 2691 && strncmp (s + 1, p->name, p->len) == 0) 2692 break; 2693 if (p->type == perc_entry_none || p->type == perc_entry_reg) 2694 break; 2695 2696 if (s[p->len + 1] != '(') 2697 { 2698 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2699 return special_case; 2700 } 2701 2702 op_arg = p->name; 2703 the_insn.reloc = p->pop->reloc; 2704 s += p->len + 2; 2705 v9_arg_p = p->pop->flags & F_POP_V9; 2706 } 2707 2708 /* Note that if the get_expression() fails, we will still 2709 have created U entries in the symbol table for the 2710 'symbols' in the input string. Try not to create U 2711 symbols for registers, etc. */ 2712 2713 /* This stuff checks to see if the expression ends in 2714 +%reg. If it does, it removes the register from 2715 the expression, and re-sets 's' to point to the 2716 right place. */ 2717 2718 if (op_arg) 2719 { 2720 int npar = 0; 2721 2722 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2723 if (*s1 == '(') 2724 npar++; 2725 else if (*s1 == ')') 2726 { 2727 if (!npar) 2728 break; 2729 npar--; 2730 } 2731 2732 if (*s1 != ')') 2733 { 2734 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2735 return special_case; 2736 } 2737 2738 *s1 = '\0'; 2739 (void) get_expression (s); 2740 *s1 = ')'; 2741 if (expr_end != s1) 2742 { 2743 as_bad (_("Expression inside %%%s could not be parsed"), op_arg); 2744 return special_case; 2745 } 2746 s = s1 + 1; 2747 if (*s == ',' || *s == ']' || !*s) 2748 continue; 2749 if (*s != '+' && *s != '-') 2750 { 2751 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2752 return special_case; 2753 } 2754 *s1 = '0'; 2755 s = s1; 2756 op_exp = the_insn.exp; 2757 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2758 } 2759 2760 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2761 ; 2762 2763 if (s1 != s && ISDIGIT (s1[-1])) 2764 { 2765 if (s1[-2] == '%' && s1[-3] == '+') 2766 s1 -= 3; 2767 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2768 s1 -= 4; 2769 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') 2770 s1 -= 5; 2771 else 2772 s1 = NULL; 2773 if (s1) 2774 { 2775 *s1 = '\0'; 2776 if (op_arg && s1 == s + 1) 2777 the_insn.exp.X_op = O_absent; 2778 else 2779 (void) get_expression (s); 2780 *s1 = '+'; 2781 if (op_arg) 2782 *s = ')'; 2783 s = s1; 2784 } 2785 } 2786 else 2787 s1 = NULL; 2788 2789 if (!s1) 2790 { 2791 (void) get_expression (s); 2792 if (op_arg) 2793 *s = ')'; 2794 s = expr_end; 2795 } 2796 2797 if (op_arg) 2798 { 2799 the_insn.exp2 = the_insn.exp; 2800 the_insn.exp = op_exp; 2801 if (the_insn.exp2.X_op == O_absent) 2802 the_insn.exp2.X_op = O_illegal; 2803 else if (the_insn.exp.X_op == O_absent) 2804 { 2805 the_insn.exp = the_insn.exp2; 2806 the_insn.exp2.X_op = O_illegal; 2807 } 2808 else if (the_insn.exp.X_op == O_constant) 2809 { 2810 valueT val = the_insn.exp.X_add_number; 2811 switch (the_insn.reloc) 2812 { 2813 default: 2814 break; 2815 2816 case BFD_RELOC_SPARC_HH22: 2817 val = BSR (val, 32); 2818 /* Fall through. */ 2819 2820 case BFD_RELOC_SPARC_LM22: 2821 case BFD_RELOC_HI22: 2822 val = (val >> 10) & 0x3fffff; 2823 break; 2824 2825 case BFD_RELOC_SPARC_HM10: 2826 val = BSR (val, 32); 2827 /* Fall through. */ 2828 2829 case BFD_RELOC_LO10: 2830 val &= 0x3ff; 2831 break; 2832 2833 case BFD_RELOC_SPARC_H34: 2834 val >>= 12; 2835 val &= 0x3fffff; 2836 break; 2837 2838 case BFD_RELOC_SPARC_H44: 2839 val >>= 22; 2840 val &= 0x3fffff; 2841 break; 2842 2843 case BFD_RELOC_SPARC_M44: 2844 val >>= 12; 2845 val &= 0x3ff; 2846 break; 2847 2848 case BFD_RELOC_SPARC_L44: 2849 val &= 0xfff; 2850 break; 2851 2852 case BFD_RELOC_SPARC_HIX22: 2853 val = ~val; 2854 val = (val >> 10) & 0x3fffff; 2855 break; 2856 2857 case BFD_RELOC_SPARC_LOX10: 2858 val = (val & 0x3ff) | 0x1c00; 2859 break; 2860 } 2861 the_insn.exp = the_insn.exp2; 2862 the_insn.exp.X_add_number += val; 2863 the_insn.exp2.X_op = O_illegal; 2864 the_insn.reloc = old_reloc; 2865 } 2866 else if (the_insn.exp2.X_op != O_constant) 2867 { 2868 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2869 return special_case; 2870 } 2871 else 2872 { 2873 if (old_reloc != BFD_RELOC_SPARC13 2874 || the_insn.reloc != BFD_RELOC_LO10 2875 || sparc_arch_size != 64 2876 || sparc_pic_code) 2877 { 2878 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2879 return special_case; 2880 } 2881 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2882 } 2883 } 2884 } 2885 /* Check for constants that don't require emitting a reloc. */ 2886 if (the_insn.exp.X_op == O_constant 2887 && the_insn.exp.X_add_symbol == 0 2888 && the_insn.exp.X_op_symbol == 0) 2889 { 2890 /* For pc-relative call instructions, we reject 2891 constants to get better code. */ 2892 if (the_insn.pcrel 2893 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2894 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2895 { 2896 error_message = _(": PC-relative operand can't be a constant"); 2897 goto error; 2898 } 2899 2900 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2901 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2902 { 2903 error_message = _(": TLS operand can't be a constant"); 2904 goto error; 2905 } 2906 2907 /* Constants that won't fit are checked in md_apply_fix 2908 and bfd_install_relocation. 2909 ??? It would be preferable to install the constants 2910 into the insn here and save having to create a fixS 2911 for each one. There already exists code to handle 2912 all the various cases (e.g. in md_apply_fix and 2913 bfd_install_relocation) so duplicating all that code 2914 here isn't right. */ 2915 2916 /* This is a special case to handle cbcond instructions 2917 properly, which can need two relocations. The first 2918 one is for the 5-bit immediate field and the latter 2919 is going to be for the WDISP10 branch part. We 2920 handle the R_SPARC_5 immediate directly here so that 2921 we don't need to add support for multiple relocations 2922 in one instruction just yet. */ 2923 if (the_insn.reloc == BFD_RELOC_SPARC_5) 2924 { 2925 valueT val = the_insn.exp.X_add_number; 2926 2927 if (! in_bitfield_range (val, 0x1f)) 2928 { 2929 error_message = _(": Immediate value in cbcond is out of range."); 2930 goto error; 2931 } 2932 opcode |= val & 0x1f; 2933 the_insn.reloc = BFD_RELOC_NONE; 2934 } 2935 } 2936 2937 continue; 2938 2939 case 'a': 2940 if (*s++ == 'a') 2941 { 2942 opcode |= ANNUL; 2943 continue; 2944 } 2945 break; 2946 2947 case 'A': 2948 { 2949 int asi = 0; 2950 2951 /* Parse an asi. */ 2952 if (*s == '#') 2953 { 2954 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2955 { 2956 error_message = _(": invalid ASI name"); 2957 goto error; 2958 } 2959 } 2960 else 2961 { 2962 if (! parse_const_expr_arg (&s, &asi)) 2963 { 2964 error_message = _(": invalid ASI expression"); 2965 goto error; 2966 } 2967 if (asi < 0 || asi > 255) 2968 { 2969 error_message = _(": invalid ASI number"); 2970 goto error; 2971 } 2972 } 2973 opcode |= ASI (asi); 2974 continue; 2975 } /* Alternate space. */ 2976 2977 case 'p': 2978 if (strncmp (s, "%psr", 4) == 0) 2979 { 2980 s += 4; 2981 continue; 2982 } 2983 break; 2984 2985 case 'q': /* Floating point queue. */ 2986 if (strncmp (s, "%fq", 3) == 0) 2987 { 2988 s += 3; 2989 continue; 2990 } 2991 break; 2992 2993 case 'Q': /* Coprocessor queue. */ 2994 if (strncmp (s, "%cq", 3) == 0) 2995 { 2996 s += 3; 2997 continue; 2998 } 2999 break; 3000 3001 case 'S': 3002 if (strcmp (str, "set") == 0 3003 || strcmp (str, "setuw") == 0) 3004 { 3005 special_case = SPECIAL_CASE_SET; 3006 continue; 3007 } 3008 else if (strcmp (str, "setsw") == 0) 3009 { 3010 special_case = SPECIAL_CASE_SETSW; 3011 continue; 3012 } 3013 else if (strcmp (str, "setx") == 0) 3014 { 3015 special_case = SPECIAL_CASE_SETX; 3016 continue; 3017 } 3018 else if (strncmp (str, "fdiv", 4) == 0) 3019 { 3020 special_case = SPECIAL_CASE_FDIV; 3021 continue; 3022 } 3023 break; 3024 3025 case 'o': 3026 if (strncmp (s, "%asi", 4) != 0) 3027 break; 3028 s += 4; 3029 continue; 3030 3031 case 's': 3032 if (strncmp (s, "%fprs", 5) != 0) 3033 break; 3034 s += 5; 3035 continue; 3036 3037 case '{': 3038 if (strncmp (s, "%mcdper",7) != 0) 3039 break; 3040 s += 7; 3041 continue; 3042 3043 case 'E': 3044 if (strncmp (s, "%ccr", 4) != 0) 3045 break; 3046 s += 4; 3047 continue; 3048 3049 case 't': 3050 if (strncmp (s, "%tbr", 4) != 0) 3051 break; 3052 s += 4; 3053 continue; 3054 3055 case 'w': 3056 if (strncmp (s, "%wim", 4) != 0) 3057 break; 3058 s += 4; 3059 continue; 3060 3061 case 'x': 3062 { 3063 char *push = input_line_pointer; 3064 expressionS e; 3065 3066 input_line_pointer = s; 3067 expression (&e); 3068 if (e.X_op == O_constant) 3069 { 3070 int n = e.X_add_number; 3071 if (n != e.X_add_number || (n & ~0x1ff) != 0) 3072 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 3073 else 3074 opcode |= e.X_add_number << 5; 3075 } 3076 else 3077 as_bad (_("non-immediate OPF operand, ignored")); 3078 s = input_line_pointer; 3079 input_line_pointer = push; 3080 continue; 3081 } 3082 3083 case 'y': 3084 if (strncmp (s, "%y", 2) != 0) 3085 break; 3086 s += 2; 3087 continue; 3088 3089 case 'u': 3090 case 'U': 3091 { 3092 /* Parse a sparclet cpreg. */ 3093 int cpreg; 3094 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 3095 { 3096 error_message = _(": invalid cpreg name"); 3097 goto error; 3098 } 3099 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 3100 continue; 3101 } 3102 3103 default: 3104 as_fatal (_("failed sanity check.")); 3105 } /* switch on arg code. */ 3106 3107 /* Break out of for() loop. */ 3108 break; 3109 } /* For each arg that we expect. */ 3110 3111 error: 3112 if (match == 0) 3113 { 3114 /* Args don't match. */ 3115 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 3116 && (insn->name == insn[1].name 3117 || !strcmp (insn->name, insn[1].name))) 3118 { 3119 ++insn; 3120 s = argsStart; 3121 continue; 3122 } 3123 else 3124 { 3125 as_bad (_("Illegal operands%s"), error_message); 3126 return special_case; 3127 } 3128 } 3129 else 3130 { 3131 /* We have a match. Now see if the architecture is OK. */ 3132 int needed_arch_mask = insn->architecture; 3133 bfd_uint64_t hwcaps 3134 = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; 3135 3136 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 3137 if (hwcaps) 3138 hwcap_seen |= hwcaps; 3139 #endif 3140 if (v9_arg_p) 3141 { 3142 needed_arch_mask &= 3143 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 3144 if (! needed_arch_mask) 3145 needed_arch_mask = 3146 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 3147 } 3148 3149 if (needed_arch_mask 3150 & SPARC_OPCODE_SUPPORTED (current_architecture)) 3151 /* OK. */ 3152 ; 3153 /* Can we bump up the architecture? */ 3154 else if (needed_arch_mask 3155 & SPARC_OPCODE_SUPPORTED (max_architecture)) 3156 { 3157 enum sparc_opcode_arch_val needed_architecture = 3158 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 3159 & needed_arch_mask); 3160 3161 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 3162 if (warn_on_bump 3163 && needed_architecture > warn_after_architecture) 3164 { 3165 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 3166 sparc_opcode_archs[current_architecture].name, 3167 sparc_opcode_archs[needed_architecture].name, 3168 str); 3169 warn_after_architecture = needed_architecture; 3170 } 3171 current_architecture = needed_architecture; 3172 hwcap_allowed |= hwcaps; 3173 } 3174 /* Conflict. */ 3175 /* ??? This seems to be a bit fragile. What if the next entry in 3176 the opcode table is the one we want and it is supported? 3177 It is possible to arrange the table today so that this can't 3178 happen but what about tomorrow? */ 3179 else 3180 { 3181 int arch, printed_one_p = 0; 3182 char *p; 3183 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 3184 3185 /* Create a list of the architectures that support the insn. */ 3186 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 3187 p = required_archs; 3188 arch = sparc_ffs (needed_arch_mask); 3189 while ((1 << arch) <= needed_arch_mask) 3190 { 3191 if ((1 << arch) & needed_arch_mask) 3192 { 3193 if (printed_one_p) 3194 *p++ = '|'; 3195 strcpy (p, sparc_opcode_archs[arch].name); 3196 p += strlen (p); 3197 printed_one_p = 1; 3198 } 3199 ++arch; 3200 } 3201 3202 as_bad (_("Architecture mismatch on \"%s\"."), str); 3203 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 3204 required_archs, 3205 sparc_opcode_archs[max_architecture].name); 3206 return special_case; 3207 } 3208 3209 /* Make sure the hwcaps used by the instruction are 3210 currently enabled. */ 3211 if (hwcaps & ~hwcap_allowed) 3212 { 3213 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); 3214 3215 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), 3216 hwcap_name, str); 3217 return special_case; 3218 } 3219 } /* If no match. */ 3220 3221 break; 3222 } /* Forever looking for a match. */ 3223 3224 the_insn.opcode = opcode; 3225 return special_case; 3226 } 3227 3228 /* Parse an argument that can be expressed as a keyword. 3229 (eg: #StoreStore or %ccfr). 3230 The result is a boolean indicating success. 3231 If successful, INPUT_POINTER is updated. */ 3232 3233 static int 3234 parse_keyword_arg (int (*lookup_fn) (const char *), 3235 char **input_pointerP, 3236 int *valueP) 3237 { 3238 int value; 3239 char c, *p, *q; 3240 3241 p = *input_pointerP; 3242 for (q = p + (*p == '#' || *p == '%'); 3243 ISALNUM (*q) || *q == '_'; 3244 ++q) 3245 continue; 3246 c = *q; 3247 *q = 0; 3248 value = (*lookup_fn) (p); 3249 *q = c; 3250 if (value == -1) 3251 return 0; 3252 *valueP = value; 3253 *input_pointerP = q; 3254 return 1; 3255 } 3256 3257 /* Parse an argument that is a constant expression. 3258 The result is a boolean indicating success. */ 3259 3260 static int 3261 parse_const_expr_arg (char **input_pointerP, int *valueP) 3262 { 3263 char *save = input_line_pointer; 3264 expressionS exp; 3265 3266 input_line_pointer = *input_pointerP; 3267 /* The next expression may be something other than a constant 3268 (say if we're not processing the right variant of the insn). 3269 Don't call expression unless we're sure it will succeed as it will 3270 signal an error (which we want to defer until later). */ 3271 /* FIXME: It might be better to define md_operand and have it recognize 3272 things like %asi, etc. but continuing that route through to the end 3273 is a lot of work. */ 3274 if (*input_line_pointer == '%') 3275 { 3276 input_line_pointer = save; 3277 return 0; 3278 } 3279 expression (&exp); 3280 *input_pointerP = input_line_pointer; 3281 input_line_pointer = save; 3282 if (exp.X_op != O_constant) 3283 return 0; 3284 *valueP = exp.X_add_number; 3285 return 1; 3286 } 3287 3288 /* Subroutine of sparc_ip to parse an expression. */ 3289 3290 static int 3291 get_expression (char *str) 3292 { 3293 char *save_in; 3294 segT seg; 3295 3296 save_in = input_line_pointer; 3297 input_line_pointer = str; 3298 seg = expression (&the_insn.exp); 3299 if (seg != absolute_section 3300 && seg != text_section 3301 && seg != data_section 3302 && seg != bss_section 3303 && seg != undefined_section) 3304 { 3305 the_insn.error = _("bad segment"); 3306 expr_end = input_line_pointer; 3307 input_line_pointer = save_in; 3308 return 1; 3309 } 3310 expr_end = input_line_pointer; 3311 input_line_pointer = save_in; 3312 return 0; 3313 } 3314 3315 /* Subroutine of md_assemble to output one insn. */ 3316 3317 static void 3318 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) 3319 { 3320 char *toP = frag_more (4); 3321 3322 /* Put out the opcode. */ 3323 if (INSN_BIG_ENDIAN) 3324 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); 3325 else 3326 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); 3327 3328 /* Put out the symbol-dependent stuff. */ 3329 if (theinsn->reloc != BFD_RELOC_NONE) 3330 { 3331 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 3332 (toP - frag_now->fr_literal), /* Where. */ 3333 4, /* Size. */ 3334 &theinsn->exp, 3335 theinsn->pcrel, 3336 theinsn->reloc); 3337 /* Turn off overflow checking in fixup_segment. We'll do our 3338 own overflow checking in md_apply_fix. This is necessary because 3339 the insn size is 4 and fixup_segment will signal an overflow for 3340 large 8 byte quantities. */ 3341 fixP->fx_no_overflow = 1; 3342 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) 3343 fixP->tc_fix_data = theinsn->exp2.X_add_number; 3344 } 3345 3346 last_insn = insn; 3347 last_opcode = theinsn->opcode; 3348 3349 #ifdef OBJ_ELF 3350 dwarf2_emit_insn (4); 3351 #endif 3352 } 3353 3354 const char * 3355 md_atof (int type, char *litP, int *sizeP) 3356 { 3357 return ieee_md_atof (type, litP, sizeP, target_big_endian); 3358 } 3359 3360 /* Write a value out to the object file, using the appropriate 3361 endianness. */ 3362 3363 void 3364 md_number_to_chars (char *buf, valueT val, int n) 3365 { 3366 if (target_big_endian) 3367 number_to_chars_bigendian (buf, val, n); 3368 else if (target_little_endian_data 3369 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3370 /* Output debug words, which are not in allocated sections, as big 3371 endian. */ 3372 number_to_chars_bigendian (buf, val, n); 3373 else if (target_little_endian_data || ! target_big_endian) 3374 number_to_chars_littleendian (buf, val, n); 3375 } 3376 3377 /* Apply a fixS to the frags, now that we know the value it ought to 3378 hold. */ 3379 3380 void 3381 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) 3382 { 3383 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3384 offsetT val = * (offsetT *) valP; 3385 long insn; 3386 3387 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3388 3389 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3390 3391 #ifdef OBJ_ELF 3392 /* SPARC ELF relocations don't use an addend in the data field. */ 3393 if (fixP->fx_addsy != NULL) 3394 { 3395 switch (fixP->fx_r_type) 3396 { 3397 case BFD_RELOC_SPARC_TLS_GD_HI22: 3398 case BFD_RELOC_SPARC_TLS_GD_LO10: 3399 case BFD_RELOC_SPARC_TLS_GD_ADD: 3400 case BFD_RELOC_SPARC_TLS_GD_CALL: 3401 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3402 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3403 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3404 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3405 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3406 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3407 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3408 case BFD_RELOC_SPARC_TLS_IE_HI22: 3409 case BFD_RELOC_SPARC_TLS_IE_LO10: 3410 case BFD_RELOC_SPARC_TLS_IE_LD: 3411 case BFD_RELOC_SPARC_TLS_IE_LDX: 3412 case BFD_RELOC_SPARC_TLS_IE_ADD: 3413 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3414 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3415 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3416 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3417 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3418 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3419 case BFD_RELOC_SPARC_TLS_TPOFF32: 3420 case BFD_RELOC_SPARC_TLS_TPOFF64: 3421 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3422 3423 default: 3424 break; 3425 } 3426 3427 return; 3428 } 3429 #endif 3430 3431 /* This is a hack. There should be a better way to 3432 handle this. Probably in terms of howto fields, once 3433 we can look at these fixups in terms of howtos. */ 3434 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3435 val += fixP->fx_where + fixP->fx_frag->fr_address; 3436 3437 #ifdef OBJ_AOUT 3438 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3439 generate a reloc, then we just want to let the reloc addend set 3440 the value. We do not want to also stuff the addend into the 3441 object file. Including the addend in the object file works when 3442 doing a static link, because the linker will ignore the object 3443 file contents. However, the dynamic linker does not ignore the 3444 object file contents. */ 3445 if (fixP->fx_addsy != NULL 3446 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3447 val = 0; 3448 3449 /* When generating PIC code, we do not want an addend for a reloc 3450 against a local symbol. We adjust fx_addnumber to cancel out the 3451 value already included in val, and to also cancel out the 3452 adjustment which bfd_install_relocation will create. */ 3453 if (sparc_pic_code 3454 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3455 && fixP->fx_addsy != NULL 3456 && ! S_IS_COMMON (fixP->fx_addsy) 3457 && symbol_section_p (fixP->fx_addsy)) 3458 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3459 3460 /* When generating PIC code, we need to fiddle to get 3461 bfd_install_relocation to do the right thing for a PC relative 3462 reloc against a local symbol which we are going to keep. */ 3463 if (sparc_pic_code 3464 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3465 && fixP->fx_addsy != NULL 3466 && (S_IS_EXTERNAL (fixP->fx_addsy) 3467 || S_IS_WEAK (fixP->fx_addsy)) 3468 && S_IS_DEFINED (fixP->fx_addsy) 3469 && ! S_IS_COMMON (fixP->fx_addsy)) 3470 { 3471 val = 0; 3472 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3473 } 3474 #endif 3475 3476 /* If this is a data relocation, just output VAL. */ 3477 3478 if (fixP->fx_r_type == BFD_RELOC_8) 3479 { 3480 md_number_to_chars (buf, val, 1); 3481 } 3482 else if (fixP->fx_r_type == BFD_RELOC_16 3483 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3484 { 3485 md_number_to_chars (buf, val, 2); 3486 } 3487 else if (fixP->fx_r_type == BFD_RELOC_32 3488 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3489 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3490 { 3491 md_number_to_chars (buf, val, 4); 3492 } 3493 else if (fixP->fx_r_type == BFD_RELOC_64 3494 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3495 { 3496 md_number_to_chars (buf, val, 8); 3497 } 3498 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3499 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3500 { 3501 fixP->fx_done = 0; 3502 return; 3503 } 3504 else 3505 { 3506 /* It's a relocation against an instruction. */ 3507 3508 if (INSN_BIG_ENDIAN) 3509 insn = bfd_getb32 ((unsigned char *) buf); 3510 else 3511 insn = bfd_getl32 ((unsigned char *) buf); 3512 3513 switch (fixP->fx_r_type) 3514 { 3515 case BFD_RELOC_32_PCREL_S2: 3516 val = val >> 2; 3517 /* FIXME: This increment-by-one deserves a comment of why it's 3518 being done! */ 3519 if (! sparc_pic_code 3520 || fixP->fx_addsy == NULL 3521 || symbol_section_p (fixP->fx_addsy)) 3522 ++val; 3523 3524 insn |= val & 0x3fffffff; 3525 3526 /* See if we have a delay slot. */ 3527 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3528 { 3529 #define G0 0 3530 #define O7 15 3531 #define XCC (2 << 20) 3532 #define COND(x) (((x)&0xf)<<25) 3533 #define CONDA COND(0x8) 3534 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3535 #define INSN_BA (F2(0,2) | CONDA) 3536 #define INSN_OR F3(2, 0x2, 0) 3537 #define INSN_NOP F2(0,4) 3538 3539 long delay; 3540 3541 /* If the instruction is a call with either: 3542 restore 3543 arithmetic instruction with rd == %o7 3544 where rs1 != %o7 and rs2 if it is register != %o7 3545 then we can optimize if the call destination is near 3546 by changing the call into a branch always. */ 3547 if (INSN_BIG_ENDIAN) 3548 delay = bfd_getb32 ((unsigned char *) buf + 4); 3549 else 3550 delay = bfd_getl32 ((unsigned char *) buf + 4); 3551 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3552 break; 3553 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3554 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3555 || ((delay & RD (~0)) != RD (O7)))) 3556 break; 3557 if ((delay & RS1 (~0)) == RS1 (O7) 3558 || ((delay & F3I (~0)) == 0 3559 && (delay & RS2 (~0)) == RS2 (O7))) 3560 break; 3561 /* Ensure the branch will fit into simm22. */ 3562 if ((val & 0x3fe00000) 3563 && (val & 0x3fe00000) != 0x3fe00000) 3564 break; 3565 /* Check if the arch is v9 and branch will fit 3566 into simm19. */ 3567 if (((val & 0x3c0000) == 0 3568 || (val & 0x3c0000) == 0x3c0000) 3569 && (sparc_arch_size == 64 3570 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3571 /* ba,pt %xcc */ 3572 insn = INSN_BPA | (val & 0x7ffff); 3573 else 3574 /* ba */ 3575 insn = INSN_BA | (val & 0x3fffff); 3576 if (fixP->fx_where >= 4 3577 && ((delay & (0xffffffff ^ RS1 (~0))) 3578 == (INSN_OR | RD (O7) | RS2 (G0)))) 3579 { 3580 long setter; 3581 int reg; 3582 3583 if (INSN_BIG_ENDIAN) 3584 setter = bfd_getb32 ((unsigned char *) buf - 4); 3585 else 3586 setter = bfd_getl32 ((unsigned char *) buf - 4); 3587 if ((setter & (0xffffffff ^ RD (~0))) 3588 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3589 break; 3590 /* The sequence was 3591 or %o7, %g0, %rN 3592 call foo 3593 or %rN, %g0, %o7 3594 3595 If call foo was replaced with ba, replace 3596 or %rN, %g0, %o7 with nop. */ 3597 reg = (delay & RS1 (~0)) >> 14; 3598 if (reg != ((setter & RD (~0)) >> 25) 3599 || reg == G0 || reg == O7) 3600 break; 3601 3602 if (INSN_BIG_ENDIAN) 3603 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3604 else 3605 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3606 } 3607 } 3608 break; 3609 3610 case BFD_RELOC_SPARC_11: 3611 if (! in_signed_range (val, 0x7ff)) 3612 as_bad_where (fixP->fx_file, fixP->fx_line, 3613 _("relocation overflow")); 3614 insn |= val & 0x7ff; 3615 break; 3616 3617 case BFD_RELOC_SPARC_10: 3618 if (! in_signed_range (val, 0x3ff)) 3619 as_bad_where (fixP->fx_file, fixP->fx_line, 3620 _("relocation overflow")); 3621 insn |= val & 0x3ff; 3622 break; 3623 3624 case BFD_RELOC_SPARC_7: 3625 if (! in_bitfield_range (val, 0x7f)) 3626 as_bad_where (fixP->fx_file, fixP->fx_line, 3627 _("relocation overflow")); 3628 insn |= val & 0x7f; 3629 break; 3630 3631 case BFD_RELOC_SPARC_6: 3632 if (! in_bitfield_range (val, 0x3f)) 3633 as_bad_where (fixP->fx_file, fixP->fx_line, 3634 _("relocation overflow")); 3635 insn |= val & 0x3f; 3636 break; 3637 3638 case BFD_RELOC_SPARC_5: 3639 if (! in_bitfield_range (val, 0x1f)) 3640 as_bad_where (fixP->fx_file, fixP->fx_line, 3641 _("relocation overflow")); 3642 insn |= val & 0x1f; 3643 break; 3644 3645 case BFD_RELOC_SPARC_WDISP10: 3646 if ((val & 3) 3647 || val >= 0x007fc 3648 || val <= -(offsetT) 0x808) 3649 as_bad_where (fixP->fx_file, fixP->fx_line, 3650 _("relocation overflow")); 3651 /* FIXME: The +1 deserves a comment. */ 3652 val = (val >> 2) + 1; 3653 insn |= ((val & 0x300) << 11) 3654 | ((val & 0xff) << 5); 3655 break; 3656 3657 case BFD_RELOC_SPARC_WDISP16: 3658 if ((val & 3) 3659 || val >= 0x1fffc 3660 || val <= -(offsetT) 0x20008) 3661 as_bad_where (fixP->fx_file, fixP->fx_line, 3662 _("relocation overflow")); 3663 /* FIXME: The +1 deserves a comment. */ 3664 val = (val >> 2) + 1; 3665 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3666 break; 3667 3668 case BFD_RELOC_SPARC_WDISP19: 3669 if ((val & 3) 3670 || val >= 0xffffc 3671 || val <= -(offsetT) 0x100008) 3672 as_bad_where (fixP->fx_file, fixP->fx_line, 3673 _("relocation overflow")); 3674 /* FIXME: The +1 deserves a comment. */ 3675 val = (val >> 2) + 1; 3676 insn |= val & 0x7ffff; 3677 break; 3678 3679 case BFD_RELOC_SPARC_HH22: 3680 val = BSR (val, 32); 3681 /* Fall through. */ 3682 3683 case BFD_RELOC_SPARC_LM22: 3684 case BFD_RELOC_HI22: 3685 if (!fixP->fx_addsy) 3686 insn |= (val >> 10) & 0x3fffff; 3687 else 3688 /* FIXME: Need comment explaining why we do this. */ 3689 insn &= ~0xffff; 3690 break; 3691 3692 case BFD_RELOC_SPARC22: 3693 if (val & ~0x003fffff) 3694 as_bad_where (fixP->fx_file, fixP->fx_line, 3695 _("relocation overflow")); 3696 insn |= (val & 0x3fffff); 3697 break; 3698 3699 case BFD_RELOC_SPARC_HM10: 3700 val = BSR (val, 32); 3701 /* Fall through. */ 3702 3703 case BFD_RELOC_LO10: 3704 if (!fixP->fx_addsy) 3705 insn |= val & 0x3ff; 3706 else 3707 /* FIXME: Need comment explaining why we do this. */ 3708 insn &= ~0xff; 3709 break; 3710 3711 case BFD_RELOC_SPARC_OLO10: 3712 val &= 0x3ff; 3713 val += fixP->tc_fix_data; 3714 /* Fall through. */ 3715 3716 case BFD_RELOC_SPARC13: 3717 if (! in_signed_range (val, 0x1fff)) 3718 as_bad_where (fixP->fx_file, fixP->fx_line, 3719 _("relocation overflow")); 3720 insn |= val & 0x1fff; 3721 break; 3722 3723 case BFD_RELOC_SPARC_WDISP22: 3724 val = (val >> 2) + 1; 3725 /* Fall through. */ 3726 case BFD_RELOC_SPARC_BASE22: 3727 insn |= val & 0x3fffff; 3728 break; 3729 3730 case BFD_RELOC_SPARC_H34: 3731 if (!fixP->fx_addsy) 3732 { 3733 bfd_vma tval = val; 3734 tval >>= 12; 3735 insn |= tval & 0x3fffff; 3736 } 3737 break; 3738 3739 case BFD_RELOC_SPARC_H44: 3740 if (!fixP->fx_addsy) 3741 { 3742 bfd_vma tval = val; 3743 tval >>= 22; 3744 insn |= tval & 0x3fffff; 3745 } 3746 break; 3747 3748 case BFD_RELOC_SPARC_M44: 3749 if (!fixP->fx_addsy) 3750 insn |= (val >> 12) & 0x3ff; 3751 break; 3752 3753 case BFD_RELOC_SPARC_L44: 3754 if (!fixP->fx_addsy) 3755 insn |= val & 0xfff; 3756 break; 3757 3758 case BFD_RELOC_SPARC_HIX22: 3759 if (!fixP->fx_addsy) 3760 { 3761 val ^= ~(offsetT) 0; 3762 insn |= (val >> 10) & 0x3fffff; 3763 } 3764 break; 3765 3766 case BFD_RELOC_SPARC_LOX10: 3767 if (!fixP->fx_addsy) 3768 insn |= 0x1c00 | (val & 0x3ff); 3769 break; 3770 3771 case BFD_RELOC_NONE: 3772 default: 3773 as_bad_where (fixP->fx_file, fixP->fx_line, 3774 _("bad or unhandled relocation type: 0x%02x"), 3775 fixP->fx_r_type); 3776 break; 3777 } 3778 3779 if (INSN_BIG_ENDIAN) 3780 bfd_putb32 (insn, (unsigned char *) buf); 3781 else 3782 bfd_putl32 (insn, (unsigned char *) buf); 3783 } 3784 3785 /* Are we finished with this relocation now? */ 3786 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3787 fixP->fx_done = 1; 3788 } 3789 3790 /* Translate internal representation of relocation info to BFD target 3791 format. */ 3792 3793 arelent ** 3794 tc_gen_reloc (asection *section, fixS *fixp) 3795 { 3796 static arelent *relocs[3]; 3797 arelent *reloc; 3798 bfd_reloc_code_real_type code; 3799 3800 relocs[0] = reloc = XNEW (arelent); 3801 relocs[1] = NULL; 3802 3803 reloc->sym_ptr_ptr = XNEW (asymbol *); 3804 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3805 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3806 3807 switch (fixp->fx_r_type) 3808 { 3809 case BFD_RELOC_16: 3810 case BFD_RELOC_32: 3811 case BFD_RELOC_HI22: 3812 case BFD_RELOC_LO10: 3813 case BFD_RELOC_32_PCREL_S2: 3814 case BFD_RELOC_SPARC13: 3815 case BFD_RELOC_SPARC22: 3816 case BFD_RELOC_SPARC_PC22: 3817 case BFD_RELOC_SPARC_PC10: 3818 case BFD_RELOC_SPARC_BASE13: 3819 case BFD_RELOC_SPARC_WDISP10: 3820 case BFD_RELOC_SPARC_WDISP16: 3821 case BFD_RELOC_SPARC_WDISP19: 3822 case BFD_RELOC_SPARC_WDISP22: 3823 case BFD_RELOC_64: 3824 case BFD_RELOC_SPARC_5: 3825 case BFD_RELOC_SPARC_6: 3826 case BFD_RELOC_SPARC_7: 3827 case BFD_RELOC_SPARC_10: 3828 case BFD_RELOC_SPARC_11: 3829 case BFD_RELOC_SPARC_HH22: 3830 case BFD_RELOC_SPARC_HM10: 3831 case BFD_RELOC_SPARC_LM22: 3832 case BFD_RELOC_SPARC_PC_HH22: 3833 case BFD_RELOC_SPARC_PC_HM10: 3834 case BFD_RELOC_SPARC_PC_LM22: 3835 case BFD_RELOC_SPARC_H34: 3836 case BFD_RELOC_SPARC_H44: 3837 case BFD_RELOC_SPARC_M44: 3838 case BFD_RELOC_SPARC_L44: 3839 case BFD_RELOC_SPARC_HIX22: 3840 case BFD_RELOC_SPARC_LOX10: 3841 case BFD_RELOC_SPARC_REV32: 3842 case BFD_RELOC_SPARC_OLO10: 3843 case BFD_RELOC_SPARC_UA16: 3844 case BFD_RELOC_SPARC_UA32: 3845 case BFD_RELOC_SPARC_UA64: 3846 case BFD_RELOC_8_PCREL: 3847 case BFD_RELOC_16_PCREL: 3848 case BFD_RELOC_32_PCREL: 3849 case BFD_RELOC_64_PCREL: 3850 case BFD_RELOC_SPARC_PLT32: 3851 case BFD_RELOC_SPARC_PLT64: 3852 case BFD_RELOC_VTABLE_ENTRY: 3853 case BFD_RELOC_VTABLE_INHERIT: 3854 case BFD_RELOC_SPARC_TLS_GD_HI22: 3855 case BFD_RELOC_SPARC_TLS_GD_LO10: 3856 case BFD_RELOC_SPARC_TLS_GD_ADD: 3857 case BFD_RELOC_SPARC_TLS_GD_CALL: 3858 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3859 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3860 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3861 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3862 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3863 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3864 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3865 case BFD_RELOC_SPARC_TLS_IE_HI22: 3866 case BFD_RELOC_SPARC_TLS_IE_LO10: 3867 case BFD_RELOC_SPARC_TLS_IE_LD: 3868 case BFD_RELOC_SPARC_TLS_IE_LDX: 3869 case BFD_RELOC_SPARC_TLS_IE_ADD: 3870 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3871 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3872 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3873 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3874 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: 3875 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: 3876 case BFD_RELOC_SPARC_GOTDATA_OP: 3877 code = fixp->fx_r_type; 3878 break; 3879 default: 3880 abort (); 3881 return NULL; 3882 } 3883 3884 #if defined (OBJ_ELF) || defined (OBJ_AOUT) 3885 /* If we are generating PIC code, we need to generate a different 3886 set of relocs. */ 3887 3888 #ifdef OBJ_ELF 3889 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3890 #else 3891 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3892 #endif 3893 #ifdef TE_VXWORKS 3894 #define GOTT_BASE "__GOTT_BASE__" 3895 #define GOTT_INDEX "__GOTT_INDEX__" 3896 #endif 3897 3898 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3899 3900 if (sparc_pic_code) 3901 { 3902 switch (code) 3903 { 3904 case BFD_RELOC_32_PCREL_S2: 3905 if (generic_force_reloc (fixp)) 3906 code = BFD_RELOC_SPARC_WPLT30; 3907 break; 3908 case BFD_RELOC_HI22: 3909 code = BFD_RELOC_SPARC_GOT22; 3910 if (fixp->fx_addsy != NULL) 3911 { 3912 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3913 code = BFD_RELOC_SPARC_PC22; 3914 #ifdef TE_VXWORKS 3915 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3916 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3917 code = BFD_RELOC_HI22; /* Unchanged. */ 3918 #endif 3919 } 3920 break; 3921 case BFD_RELOC_LO10: 3922 code = BFD_RELOC_SPARC_GOT10; 3923 if (fixp->fx_addsy != NULL) 3924 { 3925 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3926 code = BFD_RELOC_SPARC_PC10; 3927 #ifdef TE_VXWORKS 3928 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3929 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3930 code = BFD_RELOC_LO10; /* Unchanged. */ 3931 #endif 3932 } 3933 break; 3934 case BFD_RELOC_SPARC13: 3935 code = BFD_RELOC_SPARC_GOT13; 3936 break; 3937 default: 3938 break; 3939 } 3940 } 3941 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3942 3943 /* Nothing is aligned in DWARF debugging sections. */ 3944 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) 3945 switch (code) 3946 { 3947 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; 3948 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; 3949 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; 3950 default: break; 3951 } 3952 3953 if (code == BFD_RELOC_SPARC_OLO10) 3954 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3955 else 3956 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3957 if (reloc->howto == 0) 3958 { 3959 as_bad_where (fixp->fx_file, fixp->fx_line, 3960 _("internal error: can't export reloc type %d (`%s')"), 3961 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3962 xfree (reloc); 3963 relocs[0] = NULL; 3964 return relocs; 3965 } 3966 3967 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3968 #ifdef OBJ_AOUT 3969 3970 if (reloc->howto->pc_relative == 0 3971 || code == BFD_RELOC_SPARC_PC10 3972 || code == BFD_RELOC_SPARC_PC22) 3973 reloc->addend = fixp->fx_addnumber; 3974 else if (sparc_pic_code 3975 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3976 && fixp->fx_addsy != NULL 3977 && (S_IS_EXTERNAL (fixp->fx_addsy) 3978 || S_IS_WEAK (fixp->fx_addsy)) 3979 && S_IS_DEFINED (fixp->fx_addsy) 3980 && ! S_IS_COMMON (fixp->fx_addsy)) 3981 reloc->addend = fixp->fx_addnumber; 3982 else 3983 reloc->addend = fixp->fx_offset - reloc->address; 3984 3985 #else /* elf or coff */ 3986 3987 if (code != BFD_RELOC_32_PCREL_S2 3988 && code != BFD_RELOC_SPARC_WDISP22 3989 && code != BFD_RELOC_SPARC_WDISP16 3990 && code != BFD_RELOC_SPARC_WDISP19 3991 && code != BFD_RELOC_SPARC_WDISP10 3992 && code != BFD_RELOC_SPARC_WPLT30 3993 && code != BFD_RELOC_SPARC_TLS_GD_CALL 3994 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 3995 reloc->addend = fixp->fx_addnumber; 3996 else if (symbol_section_p (fixp->fx_addsy)) 3997 reloc->addend = (section->vma 3998 + fixp->fx_addnumber 3999 + md_pcrel_from (fixp)); 4000 else 4001 reloc->addend = fixp->fx_offset; 4002 #endif 4003 4004 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 4005 on the same location. */ 4006 if (code == BFD_RELOC_SPARC_OLO10) 4007 { 4008 relocs[1] = reloc = XNEW (arelent); 4009 relocs[2] = NULL; 4010 4011 reloc->sym_ptr_ptr = XNEW (asymbol *); 4012 *reloc->sym_ptr_ptr 4013 = symbol_get_bfdsym (section_symbol (absolute_section)); 4014 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 4015 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 4016 reloc->addend = fixp->tc_fix_data; 4017 } 4018 4019 return relocs; 4020 } 4021 4022 /* We have no need to default values of symbols. */ 4023 4024 symbolS * 4025 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 4026 { 4027 return 0; 4028 } 4029 4030 /* Round up a section size to the appropriate boundary. */ 4031 4032 valueT 4033 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 4034 { 4035 #ifndef OBJ_ELF 4036 /* This is not right for ELF; a.out wants it, and COFF will force 4037 the alignment anyways. */ 4038 valueT align = ((valueT) 1 4039 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 4040 valueT newsize; 4041 4042 /* Turn alignment value into a mask. */ 4043 align--; 4044 newsize = (size + align) & ~align; 4045 return newsize; 4046 #else 4047 return size; 4048 #endif 4049 } 4050 4051 /* Exactly what point is a PC-relative offset relative TO? 4052 On the sparc, they're relative to the address of the offset, plus 4053 its size. This gets us to the following instruction. 4054 (??? Is this right? FIXME-SOON) */ 4055 long 4056 md_pcrel_from (fixS *fixP) 4057 { 4058 long ret; 4059 4060 ret = fixP->fx_where + fixP->fx_frag->fr_address; 4061 if (! sparc_pic_code 4062 || fixP->fx_addsy == NULL 4063 || symbol_section_p (fixP->fx_addsy)) 4064 ret += fixP->fx_size; 4065 return ret; 4066 } 4067 4068 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 4069 of two. */ 4070 4071 static int 4072 mylog2 (int value) 4073 { 4074 int shift; 4075 4076 if (value <= 0) 4077 return -1; 4078 4079 for (shift = 0; (value & 1) == 0; value >>= 1) 4080 ++shift; 4081 4082 return (value == 1) ? shift : -1; 4083 } 4084 4085 /* Sort of like s_lcomm. */ 4086 4087 #ifndef OBJ_ELF 4088 static int max_alignment = 15; 4089 #endif 4090 4091 static void 4092 s_reserve (int ignore ATTRIBUTE_UNUSED) 4093 { 4094 char *name; 4095 char *p; 4096 char c; 4097 int align; 4098 int size; 4099 int temp; 4100 symbolS *symbolP; 4101 4102 c = get_symbol_name (&name); 4103 p = input_line_pointer; 4104 *p = c; 4105 SKIP_WHITESPACE_AFTER_NAME (); 4106 4107 if (*input_line_pointer != ',') 4108 { 4109 as_bad (_("Expected comma after name")); 4110 ignore_rest_of_line (); 4111 return; 4112 } 4113 4114 ++input_line_pointer; 4115 4116 if ((size = get_absolute_expression ()) < 0) 4117 { 4118 as_bad (_("BSS length (%d.) <0! Ignored."), size); 4119 ignore_rest_of_line (); 4120 return; 4121 } /* Bad length. */ 4122 4123 *p = 0; 4124 symbolP = symbol_find_or_make (name); 4125 *p = c; 4126 4127 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 4128 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 4129 { 4130 as_bad (_("bad .reserve segment -- expected BSS segment")); 4131 return; 4132 } 4133 4134 if (input_line_pointer[2] == '.') 4135 input_line_pointer += 7; 4136 else 4137 input_line_pointer += 6; 4138 SKIP_WHITESPACE (); 4139 4140 if (*input_line_pointer == ',') 4141 { 4142 ++input_line_pointer; 4143 4144 SKIP_WHITESPACE (); 4145 if (*input_line_pointer == '\n') 4146 { 4147 as_bad (_("missing alignment")); 4148 ignore_rest_of_line (); 4149 return; 4150 } 4151 4152 align = (int) get_absolute_expression (); 4153 4154 #ifndef OBJ_ELF 4155 if (align > max_alignment) 4156 { 4157 align = max_alignment; 4158 as_warn (_("alignment too large; assuming %d"), align); 4159 } 4160 #endif 4161 4162 if (align < 0) 4163 { 4164 as_bad (_("negative alignment")); 4165 ignore_rest_of_line (); 4166 return; 4167 } 4168 4169 if (align != 0) 4170 { 4171 temp = mylog2 (align); 4172 if (temp < 0) 4173 { 4174 as_bad (_("alignment not a power of 2")); 4175 ignore_rest_of_line (); 4176 return; 4177 } 4178 4179 align = temp; 4180 } 4181 4182 record_alignment (bss_section, align); 4183 } 4184 else 4185 align = 0; 4186 4187 if (!S_IS_DEFINED (symbolP) 4188 #ifdef OBJ_AOUT 4189 && S_GET_OTHER (symbolP) == 0 4190 && S_GET_DESC (symbolP) == 0 4191 #endif 4192 ) 4193 { 4194 if (! need_pass_2) 4195 { 4196 char *pfrag; 4197 segT current_seg = now_seg; 4198 subsegT current_subseg = now_subseg; 4199 4200 /* Switch to bss. */ 4201 subseg_set (bss_section, 1); 4202 4203 if (align) 4204 /* Do alignment. */ 4205 frag_align (align, 0, 0); 4206 4207 /* Detach from old frag. */ 4208 if (S_GET_SEGMENT (symbolP) == bss_section) 4209 symbol_get_frag (symbolP)->fr_symbol = NULL; 4210 4211 symbol_set_frag (symbolP, frag_now); 4212 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4213 (offsetT) size, (char *) 0); 4214 *pfrag = 0; 4215 4216 S_SET_SEGMENT (symbolP, bss_section); 4217 4218 subseg_set (current_seg, current_subseg); 4219 4220 #ifdef OBJ_ELF 4221 S_SET_SIZE (symbolP, size); 4222 #endif 4223 } 4224 } 4225 else 4226 { 4227 as_warn (_("Ignoring attempt to re-define symbol %s"), 4228 S_GET_NAME (symbolP)); 4229 } 4230 4231 demand_empty_rest_of_line (); 4232 } 4233 4234 static void 4235 s_common (int ignore ATTRIBUTE_UNUSED) 4236 { 4237 char *name; 4238 char c; 4239 char *p; 4240 offsetT temp, size; 4241 symbolS *symbolP; 4242 4243 c = get_symbol_name (&name); 4244 /* Just after name is now '\0'. */ 4245 p = input_line_pointer; 4246 *p = c; 4247 SKIP_WHITESPACE_AFTER_NAME (); 4248 if (*input_line_pointer != ',') 4249 { 4250 as_bad (_("Expected comma after symbol-name")); 4251 ignore_rest_of_line (); 4252 return; 4253 } 4254 4255 /* Skip ','. */ 4256 input_line_pointer++; 4257 4258 if ((temp = get_absolute_expression ()) < 0) 4259 { 4260 as_bad (_(".COMMon length (%lu) out of range ignored"), 4261 (unsigned long) temp); 4262 ignore_rest_of_line (); 4263 return; 4264 } 4265 size = temp; 4266 *p = 0; 4267 symbolP = symbol_find_or_make (name); 4268 *p = c; 4269 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 4270 { 4271 as_bad (_("Ignoring attempt to re-define symbol")); 4272 ignore_rest_of_line (); 4273 return; 4274 } 4275 if (S_GET_VALUE (symbolP) != 0) 4276 { 4277 if (S_GET_VALUE (symbolP) != (valueT) size) 4278 { 4279 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 4280 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 4281 } 4282 } 4283 else 4284 { 4285 #ifndef OBJ_ELF 4286 S_SET_VALUE (symbolP, (valueT) size); 4287 S_SET_EXTERNAL (symbolP); 4288 #endif 4289 } 4290 know (symbol_get_frag (symbolP) == &zero_address_frag); 4291 if (*input_line_pointer != ',') 4292 { 4293 as_bad (_("Expected comma after common length")); 4294 ignore_rest_of_line (); 4295 return; 4296 } 4297 input_line_pointer++; 4298 SKIP_WHITESPACE (); 4299 if (*input_line_pointer != '"') 4300 { 4301 temp = get_absolute_expression (); 4302 4303 #ifndef OBJ_ELF 4304 if (temp > max_alignment) 4305 { 4306 temp = max_alignment; 4307 as_warn (_("alignment too large; assuming %ld"), (long) temp); 4308 } 4309 #endif 4310 4311 if (temp < 0) 4312 { 4313 as_bad (_("negative alignment")); 4314 ignore_rest_of_line (); 4315 return; 4316 } 4317 4318 #ifdef OBJ_ELF 4319 if (symbol_get_obj (symbolP)->local) 4320 { 4321 segT old_sec; 4322 int old_subsec; 4323 int align; 4324 4325 old_sec = now_seg; 4326 old_subsec = now_subseg; 4327 4328 if (temp == 0) 4329 align = 0; 4330 else 4331 align = mylog2 (temp); 4332 4333 if (align < 0) 4334 { 4335 as_bad (_("alignment not a power of 2")); 4336 ignore_rest_of_line (); 4337 return; 4338 } 4339 4340 record_alignment (bss_section, align); 4341 subseg_set (bss_section, 0); 4342 if (align) 4343 frag_align (align, 0, 0); 4344 if (S_GET_SEGMENT (symbolP) == bss_section) 4345 symbol_get_frag (symbolP)->fr_symbol = 0; 4346 symbol_set_frag (symbolP, frag_now); 4347 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4348 (offsetT) size, (char *) 0); 4349 *p = 0; 4350 S_SET_SEGMENT (symbolP, bss_section); 4351 S_CLEAR_EXTERNAL (symbolP); 4352 S_SET_SIZE (symbolP, size); 4353 subseg_set (old_sec, old_subsec); 4354 } 4355 else 4356 #endif /* OBJ_ELF */ 4357 { 4358 allocate_common: 4359 S_SET_VALUE (symbolP, (valueT) size); 4360 #ifdef OBJ_ELF 4361 S_SET_ALIGN (symbolP, temp); 4362 S_SET_SIZE (symbolP, size); 4363 #endif 4364 S_SET_EXTERNAL (symbolP); 4365 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 4366 } 4367 } 4368 else 4369 { 4370 input_line_pointer++; 4371 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4372 if (*input_line_pointer == '.') 4373 input_line_pointer++; 4374 /* @@ Some say data, some say bss. */ 4375 if (strncmp (input_line_pointer, "bss\"", 4) 4376 && strncmp (input_line_pointer, "data\"", 5)) 4377 { 4378 while (*--input_line_pointer != '"') 4379 ; 4380 input_line_pointer--; 4381 goto bad_common_segment; 4382 } 4383 while (*input_line_pointer++ != '"') 4384 ; 4385 goto allocate_common; 4386 } 4387 4388 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4389 4390 demand_empty_rest_of_line (); 4391 return; 4392 4393 { 4394 bad_common_segment: 4395 p = input_line_pointer; 4396 while (*p && *p != '\n') 4397 p++; 4398 c = *p; 4399 *p = '\0'; 4400 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4401 *p = c; 4402 input_line_pointer = p; 4403 ignore_rest_of_line (); 4404 return; 4405 } 4406 } 4407 4408 /* Handle the .empty pseudo-op. This suppresses the warnings about 4409 invalid delay slot usage. */ 4410 4411 static void 4412 s_empty (int ignore ATTRIBUTE_UNUSED) 4413 { 4414 /* The easy way to implement is to just forget about the last 4415 instruction. */ 4416 last_insn = NULL; 4417 } 4418 4419 static void 4420 s_seg (int ignore ATTRIBUTE_UNUSED) 4421 { 4422 4423 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4424 { 4425 input_line_pointer += 6; 4426 s_text (0); 4427 return; 4428 } 4429 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4430 { 4431 input_line_pointer += 6; 4432 s_data (0); 4433 return; 4434 } 4435 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4436 { 4437 input_line_pointer += 7; 4438 s_data1 (); 4439 return; 4440 } 4441 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4442 { 4443 input_line_pointer += 5; 4444 /* We only support 2 segments -- text and data -- for now, so 4445 things in the "bss segment" will have to go into data for now. 4446 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4447 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4448 return; 4449 } 4450 as_bad (_("Unknown segment type")); 4451 demand_empty_rest_of_line (); 4452 } 4453 4454 static void 4455 s_data1 (void) 4456 { 4457 subseg_set (data_section, 1); 4458 demand_empty_rest_of_line (); 4459 } 4460 4461 static void 4462 s_proc (int ignore ATTRIBUTE_UNUSED) 4463 { 4464 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4465 { 4466 ++input_line_pointer; 4467 } 4468 ++input_line_pointer; 4469 } 4470 4471 /* This static variable is set by s_uacons to tell sparc_cons_align 4472 that the expression does not need to be aligned. */ 4473 4474 static int sparc_no_align_cons = 0; 4475 4476 /* This handles the unaligned space allocation pseudo-ops, such as 4477 .uaword. .uaword is just like .word, but the value does not need 4478 to be aligned. */ 4479 4480 static void 4481 s_uacons (int bytes) 4482 { 4483 /* Tell sparc_cons_align not to align this value. */ 4484 sparc_no_align_cons = 1; 4485 cons (bytes); 4486 sparc_no_align_cons = 0; 4487 } 4488 4489 /* This handles the native word allocation pseudo-op .nword. 4490 For sparc_arch_size 32 it is equivalent to .word, for 4491 sparc_arch_size 64 it is equivalent to .xword. */ 4492 4493 static void 4494 s_ncons (int bytes ATTRIBUTE_UNUSED) 4495 { 4496 cons (sparc_arch_size == 32 ? 4 : 8); 4497 } 4498 4499 #ifdef OBJ_ELF 4500 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4501 global register. 4502 The syntax is: 4503 4504 .register %g[2367],{#scratch|symbolname|#ignore} 4505 */ 4506 4507 static void 4508 s_register (int ignore ATTRIBUTE_UNUSED) 4509 { 4510 char c; 4511 int reg; 4512 int flags; 4513 char *regname; 4514 4515 if (input_line_pointer[0] != '%' 4516 || input_line_pointer[1] != 'g' 4517 || ((input_line_pointer[2] & ~1) != '2' 4518 && (input_line_pointer[2] & ~1) != '6') 4519 || input_line_pointer[3] != ',') 4520 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4521 reg = input_line_pointer[2] - '0'; 4522 input_line_pointer += 4; 4523 4524 if (*input_line_pointer == '#') 4525 { 4526 ++input_line_pointer; 4527 c = get_symbol_name (®name); 4528 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4529 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4530 if (regname[0] == 'i') 4531 regname = NULL; 4532 else 4533 regname = (char *) ""; 4534 } 4535 else 4536 { 4537 c = get_symbol_name (®name); 4538 } 4539 4540 if (sparc_arch_size == 64) 4541 { 4542 if (globals[reg]) 4543 { 4544 if ((regname && globals[reg] != (symbolS *) 1 4545 && strcmp (S_GET_NAME (globals[reg]), regname)) 4546 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4547 as_bad (_("redefinition of global register")); 4548 } 4549 else 4550 { 4551 if (regname == NULL) 4552 globals[reg] = (symbolS *) 1; 4553 else 4554 { 4555 if (*regname) 4556 { 4557 if (symbol_find (regname)) 4558 as_bad (_("Register symbol %s already defined."), 4559 regname); 4560 } 4561 globals[reg] = symbol_make (regname); 4562 flags = symbol_get_bfdsym (globals[reg])->flags; 4563 if (! *regname) 4564 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4565 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4566 flags |= BSF_GLOBAL; 4567 symbol_get_bfdsym (globals[reg])->flags = flags; 4568 S_SET_VALUE (globals[reg], (valueT) reg); 4569 S_SET_ALIGN (globals[reg], reg); 4570 S_SET_SIZE (globals[reg], 0); 4571 /* Although we actually want undefined_section here, 4572 we have to use absolute_section, because otherwise 4573 generic as code will make it a COM section. 4574 We fix this up in sparc_adjust_symtab. */ 4575 S_SET_SEGMENT (globals[reg], absolute_section); 4576 S_SET_OTHER (globals[reg], 0); 4577 elf_symbol (symbol_get_bfdsym (globals[reg])) 4578 ->internal_elf_sym.st_info = 4579 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4580 elf_symbol (symbol_get_bfdsym (globals[reg])) 4581 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4582 } 4583 } 4584 } 4585 4586 (void) restore_line_pointer (c); 4587 4588 demand_empty_rest_of_line (); 4589 } 4590 4591 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4592 symbols which need it. */ 4593 4594 void 4595 sparc_adjust_symtab (void) 4596 { 4597 symbolS *sym; 4598 4599 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4600 { 4601 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4602 ->internal_elf_sym.st_info) != STT_REGISTER) 4603 continue; 4604 4605 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4606 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4607 continue; 4608 4609 S_SET_SEGMENT (sym, undefined_section); 4610 } 4611 } 4612 #endif 4613 4614 /* If the --enforce-aligned-data option is used, we require .word, 4615 et. al., to be aligned correctly. We do it by setting up an 4616 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4617 no unexpected alignment was introduced. 4618 4619 The SunOS and Solaris native assemblers enforce aligned data by 4620 default. We don't want to do that, because gcc can deliberately 4621 generate misaligned data if the packed attribute is used. Instead, 4622 we permit misaligned data by default, and permit the user to set an 4623 option to check for it. */ 4624 4625 void 4626 sparc_cons_align (int nbytes) 4627 { 4628 int nalign; 4629 4630 /* Only do this if we are enforcing aligned data. */ 4631 if (! enforce_aligned_data) 4632 return; 4633 4634 /* Don't align if this is an unaligned pseudo-op. */ 4635 if (sparc_no_align_cons) 4636 return; 4637 4638 nalign = mylog2 (nbytes); 4639 if (nalign == 0) 4640 return; 4641 4642 gas_assert (nalign > 0); 4643 4644 if (now_seg == absolute_section) 4645 { 4646 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4647 as_bad (_("misaligned data")); 4648 return; 4649 } 4650 4651 frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4652 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4653 4654 record_alignment (now_seg, nalign); 4655 } 4656 4657 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4658 4659 void 4660 sparc_handle_align (fragS *fragp) 4661 { 4662 int count, fix; 4663 char *p; 4664 4665 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4666 4667 switch (fragp->fr_type) 4668 { 4669 case rs_align_test: 4670 if (count != 0) 4671 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4672 break; 4673 4674 case rs_align_code: 4675 p = fragp->fr_literal + fragp->fr_fix; 4676 fix = 0; 4677 4678 if (count & 3) 4679 { 4680 fix = count & 3; 4681 memset (p, 0, fix); 4682 p += fix; 4683 count -= fix; 4684 } 4685 4686 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4687 { 4688 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4689 if (INSN_BIG_ENDIAN) 4690 number_to_chars_bigendian (p, wval, 4); 4691 else 4692 number_to_chars_littleendian (p, wval, 4); 4693 p += 4; 4694 count -= 4; 4695 fix += 4; 4696 } 4697 4698 if (INSN_BIG_ENDIAN) 4699 number_to_chars_bigendian (p, 0x01000000, 4); 4700 else 4701 number_to_chars_littleendian (p, 0x01000000, 4); 4702 4703 fragp->fr_fix += fix; 4704 fragp->fr_var = 4; 4705 break; 4706 4707 default: 4708 break; 4709 } 4710 } 4711 4712 #ifdef OBJ_ELF 4713 /* Some special processing for a Sparc ELF file. */ 4714 4715 void 4716 sparc_elf_final_processing (void) 4717 { 4718 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4719 sort of BFD interface for this. */ 4720 if (sparc_arch_size == 64) 4721 { 4722 switch (sparc_memory_model) 4723 { 4724 case MM_RMO: 4725 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4726 break; 4727 case MM_PSO: 4728 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4729 break; 4730 default: 4731 break; 4732 } 4733 } 4734 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4735 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4736 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4737 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4738 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4739 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4740 } 4741 4742 const char * 4743 sparc_cons (expressionS *exp, int size) 4744 { 4745 char *save; 4746 const char *sparc_cons_special_reloc = NULL; 4747 4748 SKIP_WHITESPACE (); 4749 save = input_line_pointer; 4750 if (input_line_pointer[0] == '%' 4751 && input_line_pointer[1] == 'r' 4752 && input_line_pointer[2] == '_') 4753 { 4754 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4755 { 4756 input_line_pointer += 7; 4757 sparc_cons_special_reloc = "disp"; 4758 } 4759 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4760 { 4761 if (size != 4 && size != 8) 4762 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4763 else 4764 { 4765 input_line_pointer += 6; 4766 sparc_cons_special_reloc = "plt"; 4767 } 4768 } 4769 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4770 { 4771 if (size != 4 && size != 8) 4772 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4773 else 4774 { 4775 input_line_pointer += 13; 4776 sparc_cons_special_reloc = "tls_dtpoff"; 4777 } 4778 } 4779 if (sparc_cons_special_reloc) 4780 { 4781 int bad = 0; 4782 4783 switch (size) 4784 { 4785 case 1: 4786 if (*input_line_pointer != '8') 4787 bad = 1; 4788 input_line_pointer--; 4789 break; 4790 case 2: 4791 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4792 bad = 1; 4793 break; 4794 case 4: 4795 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4796 bad = 1; 4797 break; 4798 case 8: 4799 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4800 bad = 1; 4801 break; 4802 default: 4803 bad = 1; 4804 break; 4805 } 4806 4807 if (bad) 4808 { 4809 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4810 sparc_cons_special_reloc, size * 8, size); 4811 } 4812 else 4813 { 4814 input_line_pointer += 2; 4815 if (*input_line_pointer != '(') 4816 { 4817 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4818 sparc_cons_special_reloc, size * 8); 4819 bad = 1; 4820 } 4821 } 4822 4823 if (bad) 4824 { 4825 input_line_pointer = save; 4826 sparc_cons_special_reloc = NULL; 4827 } 4828 else 4829 { 4830 int c; 4831 char *end = ++input_line_pointer; 4832 int npar = 0; 4833 4834 while (! is_end_of_line[(c = *end)]) 4835 { 4836 if (c == '(') 4837 npar++; 4838 else if (c == ')') 4839 { 4840 if (!npar) 4841 break; 4842 npar--; 4843 } 4844 end++; 4845 } 4846 4847 if (c != ')') 4848 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4849 sparc_cons_special_reloc, size * 8); 4850 else 4851 { 4852 *end = '\0'; 4853 expression (exp); 4854 *end = c; 4855 if (input_line_pointer != end) 4856 { 4857 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4858 sparc_cons_special_reloc, size * 8); 4859 } 4860 else 4861 { 4862 input_line_pointer++; 4863 SKIP_WHITESPACE (); 4864 c = *input_line_pointer; 4865 if (! is_end_of_line[c] && c != ',') 4866 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4867 sparc_cons_special_reloc, size * 8); 4868 } 4869 } 4870 } 4871 } 4872 } 4873 if (sparc_cons_special_reloc == NULL) 4874 expression (exp); 4875 return sparc_cons_special_reloc; 4876 } 4877 4878 #endif 4879 4880 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4881 reloc for a cons. We could use the definition there, except that 4882 we want to handle little endian relocs specially. */ 4883 4884 void 4885 cons_fix_new_sparc (fragS *frag, 4886 int where, 4887 unsigned int nbytes, 4888 expressionS *exp, 4889 const char *sparc_cons_special_reloc) 4890 { 4891 bfd_reloc_code_real_type r; 4892 4893 r = (nbytes == 1 ? BFD_RELOC_8 : 4894 (nbytes == 2 ? BFD_RELOC_16 : 4895 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4896 4897 if (target_little_endian_data 4898 && nbytes == 4 4899 && now_seg->flags & SEC_ALLOC) 4900 r = BFD_RELOC_SPARC_REV32; 4901 4902 if (sparc_cons_special_reloc) 4903 { 4904 if (*sparc_cons_special_reloc == 'd') 4905 switch (nbytes) 4906 { 4907 case 1: r = BFD_RELOC_8_PCREL; break; 4908 case 2: r = BFD_RELOC_16_PCREL; break; 4909 case 4: r = BFD_RELOC_32_PCREL; break; 4910 case 8: r = BFD_RELOC_64_PCREL; break; 4911 default: abort (); 4912 } 4913 else if (*sparc_cons_special_reloc == 'p') 4914 switch (nbytes) 4915 { 4916 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4917 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4918 } 4919 else 4920 switch (nbytes) 4921 { 4922 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4923 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4924 } 4925 } 4926 else if (sparc_no_align_cons) 4927 { 4928 switch (nbytes) 4929 { 4930 case 2: r = BFD_RELOC_SPARC_UA16; break; 4931 case 4: r = BFD_RELOC_SPARC_UA32; break; 4932 case 8: r = BFD_RELOC_SPARC_UA64; break; 4933 default: abort (); 4934 } 4935 } 4936 4937 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4938 } 4939 4940 void 4941 sparc_cfi_frame_initial_instructions (void) 4942 { 4943 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4944 } 4945 4946 int 4947 sparc_regname_to_dw2regnum (char *regname) 4948 { 4949 char *q; 4950 int i; 4951 4952 if (!regname[0]) 4953 return -1; 4954 4955 switch (regname[0]) 4956 { 4957 case 'g': i = 0; break; 4958 case 'o': i = 1; break; 4959 case 'l': i = 2; break; 4960 case 'i': i = 3; break; 4961 default: i = -1; break; 4962 } 4963 if (i != -1) 4964 { 4965 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4966 return -1; 4967 return i * 8 + regname[1] - '0'; 4968 } 4969 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4970 return 14; 4971 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4972 return 30; 4973 if (regname[0] == 'f' || regname[0] == 'r') 4974 { 4975 unsigned int regnum; 4976 4977 regnum = strtoul (regname + 1, &q, 10); 4978 if (q == NULL || *q) 4979 return -1; 4980 if (regnum >= ((regname[0] == 'f' 4981 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4982 ? 64 : 32)) 4983 return -1; 4984 if (regname[0] == 'f') 4985 { 4986 regnum += 32; 4987 if (regnum >= 64 && (regnum & 1)) 4988 return -1; 4989 } 4990 return regnum; 4991 } 4992 return -1; 4993 } 4994 4995 void 4996 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 4997 { 4998 sparc_no_align_cons = 1; 4999 emit_expr_with_reloc (exp, nbytes, "disp"); 5000 sparc_no_align_cons = 0; 5001 } 5002