1 /* tc-riscv.c -- RISC-V assembler 2 Copyright (C) 2011-2020 Free Software Foundation, Inc. 3 4 Contributed by Andrew Waterman (andrew@sifive.com). 5 Based on MIPS target. 6 7 This file is part of GAS. 8 9 GAS is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; see the file COPYING3. If not, 21 see <http://www.gnu.org/licenses/>. */ 22 23 #include "as.h" 24 #include "config.h" 25 #include "subsegs.h" 26 #include "safe-ctype.h" 27 28 #include "itbl-ops.h" 29 #include "dwarf2dbg.h" 30 #include "dw2gencfi.h" 31 32 #include "bfd/elfxx-riscv.h" 33 #include "elf/riscv.h" 34 #include "opcode/riscv.h" 35 36 #include <stdint.h> 37 38 /* Information about an instruction, including its format, operands 39 and fixups. */ 40 struct riscv_cl_insn 41 { 42 /* The opcode's entry in riscv_opcodes. */ 43 const struct riscv_opcode *insn_mo; 44 45 /* The encoded instruction bits. */ 46 insn_t insn_opcode; 47 48 /* The frag that contains the instruction. */ 49 struct frag *frag; 50 51 /* The offset into FRAG of the first instruction byte. */ 52 long where; 53 54 /* The relocs associated with the instruction, if any. */ 55 fixS *fixp; 56 }; 57 58 #ifndef DEFAULT_ARCH 59 #define DEFAULT_ARCH "riscv64" 60 #endif 61 62 #ifndef DEFAULT_RISCV_ATTR 63 #define DEFAULT_RISCV_ATTR 0 64 #endif 65 66 static const char default_arch[] = DEFAULT_ARCH; 67 68 static unsigned xlen = 0; /* width of an x-register */ 69 static unsigned abi_xlen = 0; /* width of a pointer in the ABI */ 70 static bfd_boolean rve_abi = FALSE; 71 72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") 73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") 74 75 static unsigned elf_flags = 0; 76 77 /* This is the set of options which the .option pseudo-op may modify. */ 78 79 struct riscv_set_options 80 { 81 int pic; /* Generate position-independent code. */ 82 int rvc; /* Generate RVC code. */ 83 int rve; /* Generate RVE code. */ 84 int relax; /* Emit relocs the linker is allowed to relax. */ 85 int arch_attr; /* Emit arch attribute. */ 86 }; 87 88 static struct riscv_set_options riscv_opts = 89 { 90 0, /* pic */ 91 0, /* rvc */ 92 0, /* rve */ 93 1, /* relax */ 94 DEFAULT_RISCV_ATTR, /* arch_attr */ 95 }; 96 97 static void 98 riscv_set_rvc (bfd_boolean rvc_value) 99 { 100 if (rvc_value) 101 elf_flags |= EF_RISCV_RVC; 102 103 riscv_opts.rvc = rvc_value; 104 } 105 106 static void 107 riscv_set_rve (bfd_boolean rve_value) 108 { 109 riscv_opts.rve = rve_value; 110 } 111 112 static riscv_subset_list_t riscv_subsets; 113 114 static bfd_boolean 115 riscv_subset_supports (const char *feature) 116 { 117 if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0)) 118 return TRUE; 119 120 return riscv_lookup_subset (&riscv_subsets, feature) != NULL; 121 } 122 123 static bfd_boolean 124 riscv_multi_subset_supports (enum riscv_insn_class insn_class) 125 { 126 switch (insn_class) 127 { 128 case INSN_CLASS_I: return riscv_subset_supports ("i"); 129 case INSN_CLASS_C: return riscv_subset_supports ("c"); 130 case INSN_CLASS_A: return riscv_subset_supports ("a"); 131 case INSN_CLASS_M: return riscv_subset_supports ("m"); 132 case INSN_CLASS_F: return riscv_subset_supports ("f"); 133 case INSN_CLASS_D: return riscv_subset_supports ("d"); 134 case INSN_CLASS_D_AND_C: 135 return riscv_subset_supports ("d") && riscv_subset_supports ("c"); 136 137 case INSN_CLASS_F_AND_C: 138 return riscv_subset_supports ("f") && riscv_subset_supports ("c"); 139 140 case INSN_CLASS_Q: return riscv_subset_supports ("q"); 141 142 default: 143 as_fatal ("Unreachable"); 144 return FALSE; 145 } 146 } 147 148 /* Set which ISA and extensions are available. */ 149 150 static void 151 riscv_set_arch (const char *s) 152 { 153 riscv_parse_subset_t rps; 154 rps.subset_list = &riscv_subsets; 155 rps.error_handler = as_fatal; 156 rps.xlen = &xlen; 157 158 riscv_release_subset_list (&riscv_subsets); 159 riscv_parse_subset (&rps, s); 160 } 161 162 /* Handle of the OPCODE hash table. */ 163 static struct hash_control *op_hash = NULL; 164 165 /* Handle of the type of .insn hash table. */ 166 static struct hash_control *insn_type_hash = NULL; 167 168 /* This array holds the chars that always start a comment. If the 169 pre-processor is disabled, these aren't very useful */ 170 const char comment_chars[] = "#"; 171 172 /* This array holds the chars that only start a comment at the beginning of 173 a line. If the line seems to have the form '# 123 filename' 174 .line and .file directives will appear in the pre-processed output */ 175 /* Note that input_file.c hand checks for '#' at the beginning of the 176 first line of the input file. This is because the compiler outputs 177 #NO_APP at the beginning of its output. */ 178 /* Also note that C style comments are always supported. */ 179 const char line_comment_chars[] = "#"; 180 181 /* This array holds machine specific line separator characters. */ 182 const char line_separator_chars[] = ";"; 183 184 /* Chars that can be used to separate mant from exp in floating point nums */ 185 const char EXP_CHARS[] = "eE"; 186 187 /* Chars that mean this number is a floating point constant */ 188 /* As in 0f12.456 */ 189 /* or 0d1.2345e12 */ 190 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 191 192 /* Indicate we are already assemble any instructions or not. */ 193 static bfd_boolean start_assemble = FALSE; 194 195 /* Indicate arch attribute is explictly set. */ 196 static bfd_boolean explicit_arch_attr = FALSE; 197 198 /* Macros for encoding relaxation state for RVC branches and far jumps. */ 199 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ 200 ((relax_substateT) \ 201 (0xc0000000 \ 202 | ((uncond) ? 1 : 0) \ 203 | ((rvc) ? 2 : 0) \ 204 | ((length) << 2))) 205 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) 206 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) 207 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) 208 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) 209 210 /* Is the given value a sign-extended 32-bit value? */ 211 #define IS_SEXT_32BIT_NUM(x) \ 212 (((x) &~ (offsetT) 0x7fffffff) == 0 \ 213 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) 214 215 /* Is the given value a zero-extended 32-bit value? Or a negated one? */ 216 #define IS_ZEXT_32BIT_NUM(x) \ 217 (((x) &~ (offsetT) 0xffffffff) == 0 \ 218 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) 219 220 /* Change INSN's opcode so that the operand given by FIELD has value VALUE. 221 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ 222 #define INSERT_OPERAND(FIELD, INSN, VALUE) \ 223 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) 224 225 /* Determine if an instruction matches an opcode. */ 226 #define OPCODE_MATCHES(OPCODE, OP) \ 227 (((OPCODE) & MASK_##OP) == MATCH_##OP) 228 229 static char *expr_end; 230 231 /* The default target format to use. */ 232 233 const char * 234 riscv_target_format (void) 235 { 236 return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; 237 } 238 239 /* Return the length of instruction INSN. */ 240 241 static inline unsigned int 242 insn_length (const struct riscv_cl_insn *insn) 243 { 244 return riscv_insn_length (insn->insn_opcode); 245 } 246 247 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ 248 249 static void 250 create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) 251 { 252 insn->insn_mo = mo; 253 insn->insn_opcode = mo->match; 254 insn->frag = NULL; 255 insn->where = 0; 256 insn->fixp = NULL; 257 } 258 259 /* Install INSN at the location specified by its "frag" and "where" fields. */ 260 261 static void 262 install_insn (const struct riscv_cl_insn *insn) 263 { 264 char *f = insn->frag->fr_literal + insn->where; 265 md_number_to_chars (f, insn->insn_opcode, insn_length (insn)); 266 } 267 268 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly 269 and install the opcode in the new location. */ 270 271 static void 272 move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) 273 { 274 insn->frag = frag; 275 insn->where = where; 276 if (insn->fixp != NULL) 277 { 278 insn->fixp->fx_frag = frag; 279 insn->fixp->fx_where = where; 280 } 281 install_insn (insn); 282 } 283 284 /* Add INSN to the end of the output. */ 285 286 static void 287 add_fixed_insn (struct riscv_cl_insn *insn) 288 { 289 char *f = frag_more (insn_length (insn)); 290 move_insn (insn, frag_now, f - frag_now->fr_literal); 291 } 292 293 static void 294 add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, 295 relax_substateT subtype, symbolS *symbol, offsetT offset) 296 { 297 frag_grow (max_chars); 298 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); 299 frag_var (rs_machine_dependent, max_chars, var, 300 subtype, symbol, offset, NULL); 301 } 302 303 /* Compute the length of a branch sequence, and adjust the stored length 304 accordingly. If FRAGP is NULL, the worst-case length is returned. */ 305 306 static unsigned 307 relaxed_branch_length (fragS *fragp, asection *sec, int update) 308 { 309 int jump, rvc, length = 8; 310 311 if (!fragp) 312 return length; 313 314 jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); 315 rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); 316 length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); 317 318 /* Assume jumps are in range; the linker will catch any that aren't. */ 319 length = jump ? 4 : 8; 320 321 if (fragp->fr_symbol != NULL 322 && S_IS_DEFINED (fragp->fr_symbol) 323 && !S_IS_WEAK (fragp->fr_symbol) 324 && sec == S_GET_SEGMENT (fragp->fr_symbol)) 325 { 326 offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; 327 bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; 328 val -= fragp->fr_address + fragp->fr_fix; 329 330 if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) 331 length = 2; 332 else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) 333 length = 4; 334 else if (!jump && rvc) 335 length = 6; 336 } 337 338 if (update) 339 fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); 340 341 return length; 342 } 343 344 /* Information about an opcode name, mnemonics and its value. */ 345 struct opcode_name_t 346 { 347 const char *name; 348 unsigned int val; 349 }; 350 351 /* List for all supported opcode name. */ 352 static const struct opcode_name_t opcode_name_list[] = 353 { 354 {"C0", 0x0}, 355 {"C1", 0x1}, 356 {"C2", 0x2}, 357 358 {"LOAD", 0x03}, 359 {"LOAD_FP", 0x07}, 360 {"CUSTOM_0", 0x0b}, 361 {"MISC_MEM", 0x0f}, 362 {"OP_IMM", 0x13}, 363 {"AUIPC", 0x17}, 364 {"OP_IMM_32", 0x1b}, 365 /* 48b 0x1f. */ 366 367 {"STORE", 0x23}, 368 {"STORE_FP", 0x27}, 369 {"CUSTOM_1", 0x2b}, 370 {"AMO", 0x2f}, 371 {"OP", 0x33}, 372 {"LUI", 0x37}, 373 {"OP_32", 0x3b}, 374 /* 64b 0x3f. */ 375 376 {"MADD", 0x43}, 377 {"MSUB", 0x47}, 378 {"NMADD", 0x4f}, 379 {"NMSUB", 0x4b}, 380 {"OP_FP", 0x53}, 381 /*reserved 0x57. */ 382 {"CUSTOM_2", 0x5b}, 383 /* 48b 0x5f. */ 384 385 {"BRANCH", 0x63}, 386 {"JALR", 0x67}, 387 /*reserved 0x5b. */ 388 {"JAL", 0x6f}, 389 {"SYSTEM", 0x73}, 390 /*reserved 0x77. */ 391 {"CUSTOM_3", 0x7b}, 392 /* >80b 0x7f. */ 393 394 {NULL, 0} 395 }; 396 397 /* Hash table for lookup opcode name. */ 398 static struct hash_control *opcode_names_hash = NULL; 399 400 /* Initialization for hash table of opcode name. */ 401 static void 402 init_opcode_names_hash (void) 403 { 404 const char *retval; 405 const struct opcode_name_t *opcode; 406 407 for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode) 408 { 409 retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode); 410 411 if (retval != NULL) 412 as_fatal (_("internal error: can't hash `%s': %s"), 413 opcode->name, retval); 414 } 415 } 416 417 /* Find `s` is a valid opcode name or not, 418 return the opcode name info if found. */ 419 static const struct opcode_name_t * 420 opcode_name_lookup (char **s) 421 { 422 char *e; 423 char save_c; 424 struct opcode_name_t *o; 425 426 /* Find end of name. */ 427 e = *s; 428 if (is_name_beginner (*e)) 429 ++e; 430 while (is_part_of_name (*e)) 431 ++e; 432 433 /* Terminate name. */ 434 save_c = *e; 435 *e = '\0'; 436 437 o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s); 438 439 /* Advance to next token if one was recognized. */ 440 if (o) 441 *s = e; 442 443 *e = save_c; 444 expr_end = e; 445 446 return o; 447 } 448 449 enum reg_class 450 { 451 RCLASS_GPR, 452 RCLASS_FPR, 453 RCLASS_CSR, 454 RCLASS_MAX 455 }; 456 457 static struct hash_control *reg_names_hash = NULL; 458 459 #define ENCODE_REG_HASH(cls, n) \ 460 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) 461 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) 462 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) 463 464 static void 465 hash_reg_name (enum reg_class class, const char *name, unsigned n) 466 { 467 void *hash = ENCODE_REG_HASH (class, n); 468 const char *retval = hash_insert (reg_names_hash, name, hash); 469 470 if (retval != NULL) 471 as_fatal (_("internal error: can't hash `%s': %s"), name, retval); 472 } 473 474 static void 475 hash_reg_names (enum reg_class class, const char * const names[], unsigned n) 476 { 477 unsigned i; 478 479 for (i = 0; i < n; i++) 480 hash_reg_name (class, names[i], i); 481 } 482 483 static unsigned int 484 reg_lookup_internal (const char *s, enum reg_class class) 485 { 486 void *r = hash_find (reg_names_hash, s); 487 488 if (r == NULL || DECODE_REG_CLASS (r) != class) 489 return -1; 490 491 if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15) 492 return -1; 493 494 return DECODE_REG_NUM (r); 495 } 496 497 static bfd_boolean 498 reg_lookup (char **s, enum reg_class class, unsigned int *regnop) 499 { 500 char *e; 501 char save_c; 502 int reg = -1; 503 504 /* Find end of name. */ 505 e = *s; 506 if (is_name_beginner (*e)) 507 ++e; 508 while (is_part_of_name (*e)) 509 ++e; 510 511 /* Terminate name. */ 512 save_c = *e; 513 *e = '\0'; 514 515 /* Look for the register. Advance to next token if one was recognized. */ 516 if ((reg = reg_lookup_internal (*s, class)) >= 0) 517 *s = e; 518 519 *e = save_c; 520 if (regnop) 521 *regnop = reg; 522 return reg >= 0; 523 } 524 525 static bfd_boolean 526 arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) 527 { 528 const char *p = strchr (*s, ','); 529 size_t i, len = p ? (size_t)(p - *s) : strlen (*s); 530 531 if (len == 0) 532 return FALSE; 533 534 for (i = 0; i < size; i++) 535 if (array[i] != NULL && strncmp (array[i], *s, len) == 0) 536 { 537 *regnop = i; 538 *s += len; 539 return TRUE; 540 } 541 542 return FALSE; 543 } 544 545 /* For consistency checking, verify that all bits are specified either 546 by the match/mask part of the instruction definition, or by the 547 operand list. 548 549 `length` could be 0, 4 or 8, 0 for auto detection. */ 550 static bfd_boolean 551 validate_riscv_insn (const struct riscv_opcode *opc, int length) 552 { 553 const char *p = opc->args; 554 char c; 555 insn_t used_bits = opc->mask; 556 int insn_width; 557 insn_t required_bits; 558 559 if (length == 0) 560 insn_width = 8 * riscv_insn_length (opc->match); 561 else 562 insn_width = 8 * length; 563 564 required_bits = ~0ULL >> (64 - insn_width); 565 566 if ((used_bits & opc->match) != (opc->match & required_bits)) 567 { 568 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), 569 opc->name, opc->args); 570 return FALSE; 571 } 572 573 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) 574 while (*p) 575 switch (c = *p++) 576 { 577 case 'C': /* RVC */ 578 switch (c = *p++) 579 { 580 case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break; 581 case 'c': break; /* RS1, constrained to equal sp */ 582 case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break; 583 case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break; 584 case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break; 585 case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break; 586 case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break; 587 case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break; 588 case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break; 589 case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break; 590 case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; 591 case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; 592 case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break; 593 case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break; 594 case 'w': break; /* RS1S, constrained to equal RD */ 595 case 'x': break; /* RS2S, constrained to equal RD */ 596 case 'z': break; /* RS2S, contrained to be x0 */ 597 case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break; 598 case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break; 599 case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break; 600 case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break; 601 case 'U': break; /* RS1, constrained to equal RD */ 602 case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; 603 case '<': used_bits |= ENCODE_RVC_IMM (-1U); break; 604 case '>': used_bits |= ENCODE_RVC_IMM (-1U); break; 605 case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break; 606 case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; 607 case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; 608 case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; 609 case 'F': /* funct */ 610 switch (c = *p++) 611 { 612 case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; 613 case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; 614 case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; 615 case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; 616 default: 617 as_bad (_("internal: bad RISC-V opcode" 618 " (unknown operand type `CF%c'): %s %s"), 619 c, opc->name, opc->args); 620 return FALSE; 621 } 622 break; 623 default: 624 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"), 625 c, opc->name, opc->args); 626 return FALSE; 627 } 628 break; 629 case ',': break; 630 case '(': break; 631 case ')': break; 632 case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; 633 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; 634 case 'A': break; 635 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 636 case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 637 case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; 638 case 'I': break; 639 case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; 640 case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 641 case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */ 642 case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; 643 case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; 644 case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; 645 case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; 646 case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; 647 case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; 648 case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; 649 case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; 650 case 'o': 651 case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; 652 case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break; 653 case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break; 654 case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; 655 case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; 656 case 'z': break; 657 case '[': break; 658 case ']': break; 659 case '0': break; 660 case '1': break; 661 case 'F': /* funct */ 662 switch (c = *p++) 663 { 664 case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; 665 case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; 666 case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; 667 default: 668 as_bad (_("internal: bad RISC-V opcode" 669 " (unknown operand type `F%c'): %s %s"), 670 c, opc->name, opc->args); 671 return FALSE; 672 } 673 break; 674 case 'O': /* opcode */ 675 switch (c = *p++) 676 { 677 case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; 678 case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; 679 default: 680 as_bad (_("internal: bad RISC-V opcode" 681 " (unknown operand type `F%c'): %s %s"), 682 c, opc->name, opc->args); 683 return FALSE; 684 } 685 break; 686 default: 687 as_bad (_("internal: bad RISC-V opcode " 688 "(unknown operand type `%c'): %s %s"), 689 c, opc->name, opc->args); 690 return FALSE; 691 } 692 #undef USE_BITS 693 if (used_bits != required_bits) 694 { 695 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"), 696 ~(unsigned long)(used_bits & required_bits), 697 opc->name, opc->args); 698 return FALSE; 699 } 700 return TRUE; 701 } 702 703 struct percent_op_match 704 { 705 const char *str; 706 bfd_reloc_code_real_type reloc; 707 }; 708 709 /* Common hash table initialization function for 710 instruction and .insn directive. */ 711 static struct hash_control * 712 init_opcode_hash (const struct riscv_opcode *opcodes, 713 bfd_boolean insn_directive_p) 714 { 715 int i = 0; 716 int length; 717 struct hash_control *hash = hash_new (); 718 while (opcodes[i].name) 719 { 720 const char *name = opcodes[i].name; 721 const char *hash_error = 722 hash_insert (hash, name, (void *) &opcodes[i]); 723 724 if (hash_error) 725 { 726 fprintf (stderr, _("internal error: can't hash `%s': %s\n"), 727 opcodes[i].name, hash_error); 728 /* Probably a memory allocation problem? Give up now. */ 729 as_fatal (_("Broken assembler. No assembly attempted.")); 730 } 731 732 do 733 { 734 if (opcodes[i].pinfo != INSN_MACRO) 735 { 736 if (insn_directive_p) 737 length = ((name[0] == 'c') ? 2 : 4); 738 else 739 length = 0; /* Let assembler determine the length. */ 740 if (!validate_riscv_insn (&opcodes[i], length)) 741 as_fatal (_("Broken assembler. No assembly attempted.")); 742 } 743 else 744 gas_assert (!insn_directive_p); 745 ++i; 746 } 747 while (opcodes[i].name && !strcmp (opcodes[i].name, name)); 748 } 749 750 return hash; 751 } 752 753 /* This function is called once, at assembler startup time. It should set up 754 all the tables, etc. that the MD part of the assembler will need. */ 755 756 void 757 md_begin (void) 758 { 759 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; 760 761 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) 762 as_warn (_("Could not set architecture and machine")); 763 764 op_hash = init_opcode_hash (riscv_opcodes, FALSE); 765 insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE); 766 767 reg_names_hash = hash_new (); 768 hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); 769 hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); 770 hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); 771 hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); 772 773 /* Add "fp" as an alias for "s0". */ 774 hash_reg_name (RCLASS_GPR, "fp", 8); 775 776 opcode_names_hash = hash_new (); 777 init_opcode_names_hash (); 778 779 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); 780 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num); 781 #include "opcode/riscv-opc.h" 782 #undef DECLARE_CSR 783 784 /* Set the default alignment for the text section. */ 785 record_alignment (text_section, riscv_opts.rvc ? 1 : 2); 786 } 787 788 static insn_t 789 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) 790 { 791 switch (reloc_type) 792 { 793 case BFD_RELOC_32: 794 return value; 795 796 case BFD_RELOC_RISCV_HI20: 797 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); 798 799 case BFD_RELOC_RISCV_LO12_S: 800 return ENCODE_STYPE_IMM (value); 801 802 case BFD_RELOC_RISCV_LO12_I: 803 return ENCODE_ITYPE_IMM (value); 804 805 default: 806 abort (); 807 } 808 } 809 810 /* Output an instruction. IP is the instruction information. 811 ADDRESS_EXPR is an operand of the instruction to be used with 812 RELOC_TYPE. */ 813 814 static void 815 append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, 816 bfd_reloc_code_real_type reloc_type) 817 { 818 dwarf2_emit_insn (0); 819 820 if (reloc_type != BFD_RELOC_UNUSED) 821 { 822 reloc_howto_type *howto; 823 824 gas_assert (address_expr); 825 if (reloc_type == BFD_RELOC_12_PCREL 826 || reloc_type == BFD_RELOC_RISCV_JMP) 827 { 828 int j = reloc_type == BFD_RELOC_RISCV_JMP; 829 int best_case = riscv_insn_length (ip->insn_opcode); 830 unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); 831 add_relaxed_insn (ip, worst_case, best_case, 832 RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), 833 address_expr->X_add_symbol, 834 address_expr->X_add_number); 835 return; 836 } 837 else 838 { 839 howto = bfd_reloc_type_lookup (stdoutput, reloc_type); 840 if (howto == NULL) 841 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type); 842 843 ip->fixp = fix_new_exp (ip->frag, ip->where, 844 bfd_get_reloc_size (howto), 845 address_expr, FALSE, reloc_type); 846 847 ip->fixp->fx_tcbit = riscv_opts.relax; 848 } 849 } 850 851 add_fixed_insn (ip); 852 install_insn (ip); 853 854 /* We need to start a new frag after any instruction that can be 855 optimized away or compressed by the linker during relaxation, to prevent 856 the assembler from computing static offsets across such an instruction. 857 This is necessary to get correct EH info. */ 858 if (reloc_type == BFD_RELOC_RISCV_CALL 859 || reloc_type == BFD_RELOC_RISCV_CALL_PLT 860 || reloc_type == BFD_RELOC_RISCV_HI20 861 || reloc_type == BFD_RELOC_RISCV_PCREL_HI20 862 || reloc_type == BFD_RELOC_RISCV_TPREL_HI20 863 || reloc_type == BFD_RELOC_RISCV_TPREL_ADD) 864 { 865 frag_wane (frag_now); 866 frag_new (0); 867 } 868 } 869 870 /* Build an instruction created by a macro expansion. This is passed 871 a pointer to the count of instructions created so far, an 872 expression, the name of the instruction to build, an operand format 873 string, and corresponding arguments. */ 874 875 static void 876 macro_build (expressionS *ep, const char *name, const char *fmt, ...) 877 { 878 const struct riscv_opcode *mo; 879 struct riscv_cl_insn insn; 880 bfd_reloc_code_real_type r; 881 va_list args; 882 883 va_start (args, fmt); 884 885 r = BFD_RELOC_UNUSED; 886 mo = (struct riscv_opcode *) hash_find (op_hash, name); 887 gas_assert (mo); 888 889 /* Find a non-RVC variant of the instruction. append_insn will compress 890 it if possible. */ 891 while (riscv_insn_length (mo->match) < 4) 892 mo++; 893 gas_assert (strcmp (name, mo->name) == 0); 894 895 create_insn (&insn, mo); 896 for (;;) 897 { 898 switch (*fmt++) 899 { 900 case 'd': 901 INSERT_OPERAND (RD, insn, va_arg (args, int)); 902 continue; 903 904 case 's': 905 INSERT_OPERAND (RS1, insn, va_arg (args, int)); 906 continue; 907 908 case 't': 909 INSERT_OPERAND (RS2, insn, va_arg (args, int)); 910 continue; 911 912 case '>': 913 INSERT_OPERAND (SHAMT, insn, va_arg (args, int)); 914 continue; 915 916 case 'j': 917 case 'u': 918 case 'q': 919 gas_assert (ep != NULL); 920 r = va_arg (args, int); 921 continue; 922 923 case '\0': 924 break; 925 case ',': 926 continue; 927 default: 928 as_fatal (_("internal error: invalid macro")); 929 } 930 break; 931 } 932 va_end (args); 933 gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); 934 935 append_insn (&insn, ep, r); 936 } 937 938 /* Build an instruction created by a macro expansion. Like md_assemble but 939 accept a printf-style format string and arguments. */ 940 941 static void 942 md_assemblef (const char *format, ...) 943 { 944 char *buf = NULL; 945 va_list ap; 946 int r; 947 948 va_start (ap, format); 949 950 r = vasprintf (&buf, format, ap); 951 952 if (r < 0) 953 as_fatal (_("internal error: vasprintf failed")); 954 955 md_assemble (buf); 956 free(buf); 957 958 va_end (ap); 959 } 960 961 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits 962 unset. */ 963 static void 964 normalize_constant_expr (expressionS *ex) 965 { 966 if (xlen > 32) 967 return; 968 if ((ex->X_op == O_constant || ex->X_op == O_symbol) 969 && IS_ZEXT_32BIT_NUM (ex->X_add_number)) 970 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) 971 - 0x80000000); 972 } 973 974 /* Fail if an expression EX is not a constant. IP is the instruction using EX. 975 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */ 976 977 static void 978 check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex, 979 bfd_boolean maybe_csr) 980 { 981 if (ex->X_op == O_big) 982 as_bad (_("unsupported large constant")); 983 else if (maybe_csr && ex->X_op == O_symbol) 984 as_bad (_("unknown CSR `%s'"), 985 S_GET_NAME (ex->X_add_symbol)); 986 else if (ex->X_op != O_constant) 987 as_bad (_("Instruction %s requires absolute expression"), 988 ip->insn_mo->name); 989 normalize_constant_expr (ex); 990 } 991 992 static symbolS * 993 make_internal_label (void) 994 { 995 return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, 996 (valueT) frag_now_fix (), frag_now); 997 } 998 999 /* Load an entry from the GOT. */ 1000 static void 1001 pcrel_access (int destreg, int tempreg, expressionS *ep, 1002 const char *lo_insn, const char *lo_pattern, 1003 bfd_reloc_code_real_type hi_reloc, 1004 bfd_reloc_code_real_type lo_reloc) 1005 { 1006 expressionS ep2; 1007 ep2.X_op = O_symbol; 1008 ep2.X_add_symbol = make_internal_label (); 1009 ep2.X_add_number = 0; 1010 1011 macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); 1012 macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); 1013 } 1014 1015 static void 1016 pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, 1017 bfd_reloc_code_real_type hi_reloc, 1018 bfd_reloc_code_real_type lo_reloc) 1019 { 1020 pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); 1021 } 1022 1023 static void 1024 pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, 1025 bfd_reloc_code_real_type hi_reloc, 1026 bfd_reloc_code_real_type lo_reloc) 1027 { 1028 pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); 1029 } 1030 1031 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ 1032 static void 1033 riscv_call (int destreg, int tempreg, expressionS *ep, 1034 bfd_reloc_code_real_type reloc) 1035 { 1036 macro_build (ep, "auipc", "d,u", tempreg, reloc); 1037 macro_build (NULL, "jalr", "d,s", destreg, tempreg); 1038 } 1039 1040 /* Load an integer constant into a register. */ 1041 1042 static void 1043 load_const (int reg, expressionS *ep) 1044 { 1045 int shift = RISCV_IMM_BITS; 1046 bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1); 1047 expressionS upper = *ep, lower = *ep; 1048 lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign; 1049 upper.X_add_number -= lower.X_add_number; 1050 1051 if (ep->X_op != O_constant) 1052 { 1053 as_bad (_("unsupported large constant")); 1054 return; 1055 } 1056 1057 if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) 1058 { 1059 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ 1060 while (((upper.X_add_number >> shift) & 1) == 0) 1061 shift++; 1062 1063 upper.X_add_number = (int64_t) upper.X_add_number >> shift; 1064 load_const (reg, &upper); 1065 1066 md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift); 1067 if (lower.X_add_number != 0) 1068 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT "d", reg, reg, 1069 lower.X_add_number); 1070 } 1071 else 1072 { 1073 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ 1074 int hi_reg = 0; 1075 1076 if (upper.X_add_number != 0) 1077 { 1078 /* Discard low part and zero-extend upper immediate. */ 1079 upper_imm = ((uint32_t)upper.X_add_number >> shift); 1080 1081 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT "x", reg, upper_imm); 1082 hi_reg = reg; 1083 } 1084 1085 if (lower.X_add_number != 0 || hi_reg == 0) 1086 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT "d", ADD32_INSN, reg, hi_reg, 1087 lower.X_add_number); 1088 } 1089 } 1090 1091 /* Expand RISC-V assembly macros into one or more instructions. */ 1092 static void 1093 macro (struct riscv_cl_insn *ip, expressionS *imm_expr, 1094 bfd_reloc_code_real_type *imm_reloc) 1095 { 1096 int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; 1097 int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; 1098 int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; 1099 int mask = ip->insn_mo->mask; 1100 1101 switch (mask) 1102 { 1103 case M_LI: 1104 load_const (rd, imm_expr); 1105 break; 1106 1107 case M_LA: 1108 case M_LLA: 1109 /* Load the address of a symbol into a register. */ 1110 if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) 1111 as_bad (_("offset too large")); 1112 1113 if (imm_expr->X_op == O_constant) 1114 load_const (rd, imm_expr); 1115 else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol */ 1116 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, 1117 BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1118 else /* Local PIC symbol, or any non-PIC symbol */ 1119 pcrel_load (rd, rd, imm_expr, "addi", 1120 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1121 break; 1122 1123 case M_LA_TLS_GD: 1124 pcrel_load (rd, rd, imm_expr, "addi", 1125 BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1126 break; 1127 1128 case M_LA_TLS_IE: 1129 pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, 1130 BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1131 break; 1132 1133 case M_LB: 1134 pcrel_load (rd, rd, imm_expr, "lb", 1135 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1136 break; 1137 1138 case M_LBU: 1139 pcrel_load (rd, rd, imm_expr, "lbu", 1140 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1141 break; 1142 1143 case M_LH: 1144 pcrel_load (rd, rd, imm_expr, "lh", 1145 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1146 break; 1147 1148 case M_LHU: 1149 pcrel_load (rd, rd, imm_expr, "lhu", 1150 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1151 break; 1152 1153 case M_LW: 1154 pcrel_load (rd, rd, imm_expr, "lw", 1155 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1156 break; 1157 1158 case M_LWU: 1159 pcrel_load (rd, rd, imm_expr, "lwu", 1160 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1161 break; 1162 1163 case M_LD: 1164 pcrel_load (rd, rd, imm_expr, "ld", 1165 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1166 break; 1167 1168 case M_FLW: 1169 pcrel_load (rd, rs1, imm_expr, "flw", 1170 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1171 break; 1172 1173 case M_FLD: 1174 pcrel_load (rd, rs1, imm_expr, "fld", 1175 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); 1176 break; 1177 1178 case M_SB: 1179 pcrel_store (rs2, rs1, imm_expr, "sb", 1180 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1181 break; 1182 1183 case M_SH: 1184 pcrel_store (rs2, rs1, imm_expr, "sh", 1185 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1186 break; 1187 1188 case M_SW: 1189 pcrel_store (rs2, rs1, imm_expr, "sw", 1190 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1191 break; 1192 1193 case M_SD: 1194 pcrel_store (rs2, rs1, imm_expr, "sd", 1195 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1196 break; 1197 1198 case M_FSW: 1199 pcrel_store (rs2, rs1, imm_expr, "fsw", 1200 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1201 break; 1202 1203 case M_FSD: 1204 pcrel_store (rs2, rs1, imm_expr, "fsd", 1205 BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); 1206 break; 1207 1208 case M_CALL: 1209 riscv_call (rd, rs1, imm_expr, *imm_reloc); 1210 break; 1211 1212 default: 1213 as_bad (_("Macro %s not implemented"), ip->insn_mo->name); 1214 break; 1215 } 1216 } 1217 1218 static const struct percent_op_match percent_op_utype[] = 1219 { 1220 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, 1221 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, 1222 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, 1223 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, 1224 {"%hi", BFD_RELOC_RISCV_HI20}, 1225 {0, 0} 1226 }; 1227 1228 static const struct percent_op_match percent_op_itype[] = 1229 { 1230 {"%lo", BFD_RELOC_RISCV_LO12_I}, 1231 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, 1232 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, 1233 {0, 0} 1234 }; 1235 1236 static const struct percent_op_match percent_op_stype[] = 1237 { 1238 {"%lo", BFD_RELOC_RISCV_LO12_S}, 1239 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, 1240 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, 1241 {0, 0} 1242 }; 1243 1244 static const struct percent_op_match percent_op_rtype[] = 1245 { 1246 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, 1247 {0, 0} 1248 }; 1249 1250 static const struct percent_op_match percent_op_null[] = 1251 { 1252 {0, 0} 1253 }; 1254 1255 /* Return true if *STR points to a relocation operator. When returning true, 1256 move *STR over the operator and store its relocation code in *RELOC. 1257 Leave both *STR and *RELOC alone when returning false. */ 1258 1259 static bfd_boolean 1260 parse_relocation (char **str, bfd_reloc_code_real_type *reloc, 1261 const struct percent_op_match *percent_op) 1262 { 1263 for ( ; percent_op->str; percent_op++) 1264 if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) 1265 { 1266 int len = strlen (percent_op->str); 1267 1268 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') 1269 continue; 1270 1271 *str += strlen (percent_op->str); 1272 *reloc = percent_op->reloc; 1273 1274 /* Check whether the output BFD supports this relocation. 1275 If not, issue an error and fall back on something safe. */ 1276 if (*reloc != BFD_RELOC_UNUSED 1277 && !bfd_reloc_type_lookup (stdoutput, *reloc)) 1278 { 1279 as_bad ("relocation %s isn't supported by the current ABI", 1280 percent_op->str); 1281 *reloc = BFD_RELOC_UNUSED; 1282 } 1283 return TRUE; 1284 } 1285 return FALSE; 1286 } 1287 1288 static void 1289 my_getExpression (expressionS *ep, char *str) 1290 { 1291 char *save_in; 1292 1293 save_in = input_line_pointer; 1294 input_line_pointer = str; 1295 expression (ep); 1296 expr_end = input_line_pointer; 1297 input_line_pointer = save_in; 1298 } 1299 1300 /* Parse string STR as a 16-bit relocatable operand. Store the 1301 expression in *EP and the relocation, if any, in RELOC. 1302 Return the number of relocation operators used (0 or 1). 1303 1304 On exit, EXPR_END points to the first character after the expression. */ 1305 1306 static size_t 1307 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 1308 char *str, const struct percent_op_match *percent_op) 1309 { 1310 size_t reloc_index; 1311 unsigned crux_depth, str_depth, regno; 1312 char *crux; 1313 1314 /* First, check for integer registers. No callers can accept a reg, but 1315 we need to avoid accidentally creating a useless undefined symbol below, 1316 if this is an instruction pattern that can't match. A glibc build fails 1317 if this is removed. */ 1318 if (reg_lookup (&str, RCLASS_GPR, ®no)) 1319 { 1320 ep->X_op = O_register; 1321 ep->X_add_number = regno; 1322 expr_end = str; 1323 return 0; 1324 } 1325 1326 /* Search for the start of the main expression. 1327 End the loop with CRUX pointing to the start 1328 of the main expression and with CRUX_DEPTH containing the number 1329 of open brackets at that point. */ 1330 reloc_index = -1; 1331 str_depth = 0; 1332 do 1333 { 1334 reloc_index++; 1335 crux = str; 1336 crux_depth = str_depth; 1337 1338 /* Skip over whitespace and brackets, keeping count of the number 1339 of brackets. */ 1340 while (*str == ' ' || *str == '\t' || *str == '(') 1341 if (*str++ == '(') 1342 str_depth++; 1343 } 1344 while (*str == '%' 1345 && reloc_index < 1 1346 && parse_relocation (&str, reloc, percent_op)); 1347 1348 my_getExpression (ep, crux); 1349 str = expr_end; 1350 1351 /* Match every open bracket. */ 1352 while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) 1353 if (*str++ == ')') 1354 crux_depth--; 1355 1356 if (crux_depth > 0) 1357 as_bad ("unclosed '('"); 1358 1359 expr_end = str; 1360 1361 return reloc_index; 1362 } 1363 1364 /* Parse opcode name, could be an mnemonics or number. */ 1365 static size_t 1366 my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, 1367 char *str, const struct percent_op_match *percent_op) 1368 { 1369 const struct opcode_name_t *o = opcode_name_lookup (&str); 1370 1371 if (o != NULL) 1372 { 1373 ep->X_op = O_constant; 1374 ep->X_add_number = o->val; 1375 return 0; 1376 } 1377 1378 return my_getSmallExpression (ep, reloc, str, percent_op); 1379 } 1380 1381 /* Detect and handle implicitly zero load-store offsets. For example, 1382 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such 1383 an implicit offset was detected. */ 1384 1385 static bfd_boolean 1386 riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) 1387 { 1388 /* Check whether there is only a single bracketed expression left. 1389 If so, it must be the base register and the constant must be zero. */ 1390 if (*s == '(' && strchr (s + 1, '(') == 0) 1391 { 1392 ep->X_op = O_constant; 1393 ep->X_add_number = 0; 1394 return TRUE; 1395 } 1396 1397 return FALSE; 1398 } 1399 1400 /* This routine assembles an instruction into its binary format. As a 1401 side effect, it sets the global variable imm_reloc to the type of 1402 relocation to do if one of the operands is an address expression. */ 1403 1404 static const char * 1405 riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, 1406 bfd_reloc_code_real_type *imm_reloc, struct hash_control *hash) 1407 { 1408 char *s; 1409 const char *args; 1410 char c = 0; 1411 struct riscv_opcode *insn; 1412 char *argsStart; 1413 unsigned int regno; 1414 char save_c = 0; 1415 int argnum; 1416 const struct percent_op_match *p; 1417 const char *error = "unrecognized opcode"; 1418 1419 /* Parse the name of the instruction. Terminate the string if whitespace 1420 is found so that hash_find only sees the name part of the string. */ 1421 for (s = str; *s != '\0'; ++s) 1422 if (ISSPACE (*s)) 1423 { 1424 save_c = *s; 1425 *s++ = '\0'; 1426 break; 1427 } 1428 1429 insn = (struct riscv_opcode *) hash_find (hash, str); 1430 1431 argsStart = s; 1432 for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) 1433 { 1434 if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement)) 1435 continue; 1436 1437 if (!riscv_multi_subset_supports (insn->insn_class)) 1438 continue; 1439 1440 create_insn (ip, insn); 1441 argnum = 1; 1442 1443 imm_expr->X_op = O_absent; 1444 *imm_reloc = BFD_RELOC_UNUSED; 1445 p = percent_op_itype; 1446 1447 for (args = insn->args;; ++args) 1448 { 1449 s += strspn (s, " \t"); 1450 switch (*args) 1451 { 1452 case '\0': /* End of args. */ 1453 if (insn->pinfo != INSN_MACRO) 1454 { 1455 if (!insn->match_func (insn, ip->insn_opcode)) 1456 break; 1457 1458 /* For .insn, insn->match and insn->mask are 0. */ 1459 if (riscv_insn_length ((insn->match == 0 && insn->mask == 0) 1460 ? ip->insn_opcode 1461 : insn->match) == 2 1462 && !riscv_opts.rvc) 1463 break; 1464 } 1465 if (*s != '\0') 1466 break; 1467 /* Successful assembly. */ 1468 error = NULL; 1469 goto out; 1470 1471 case 'C': /* RVC */ 1472 switch (*++args) 1473 { 1474 case 's': /* RS1 x8-x15 */ 1475 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1476 || !(regno >= 8 && regno <= 15)) 1477 break; 1478 INSERT_OPERAND (CRS1S, *ip, regno % 8); 1479 continue; 1480 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ 1481 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1482 || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) 1483 break; 1484 continue; 1485 case 't': /* RS2 x8-x15 */ 1486 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1487 || !(regno >= 8 && regno <= 15)) 1488 break; 1489 INSERT_OPERAND (CRS2S, *ip, regno % 8); 1490 continue; 1491 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ 1492 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1493 || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) 1494 break; 1495 continue; 1496 case 'U': /* RS1, constrained to equal RD. */ 1497 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1498 || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) 1499 break; 1500 continue; 1501 case 'V': /* RS2 */ 1502 if (!reg_lookup (&s, RCLASS_GPR, ®no)) 1503 break; 1504 INSERT_OPERAND (CRS2, *ip, regno); 1505 continue; 1506 case 'c': /* RS1, constrained to equal sp. */ 1507 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1508 || regno != X_SP) 1509 break; 1510 continue; 1511 case 'z': /* RS2, contrained to equal x0. */ 1512 if (!reg_lookup (&s, RCLASS_GPR, ®no) 1513 || regno != 0) 1514 break; 1515 continue; 1516 case '>': 1517 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1518 || imm_expr->X_op != O_constant 1519 || imm_expr->X_add_number <= 0 1520 || imm_expr->X_add_number >= 64) 1521 break; 1522 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1523 rvc_imm_done: 1524 s = expr_end; 1525 imm_expr->X_op = O_absent; 1526 continue; 1527 case '<': 1528 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1529 || imm_expr->X_op != O_constant 1530 || !VALID_RVC_IMM (imm_expr->X_add_number) 1531 || imm_expr->X_add_number <= 0 1532 || imm_expr->X_add_number >= 32) 1533 break; 1534 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1535 goto rvc_imm_done; 1536 case '8': 1537 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1538 || imm_expr->X_op != O_constant 1539 || !VALID_RVC_UIMM8 (imm_expr->X_add_number) 1540 || imm_expr->X_add_number < 0 1541 || imm_expr->X_add_number >= 256) 1542 break; 1543 ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number); 1544 goto rvc_imm_done; 1545 case 'i': 1546 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1547 || imm_expr->X_op != O_constant 1548 || imm_expr->X_add_number == 0 1549 || !VALID_RVC_SIMM3 (imm_expr->X_add_number)) 1550 break; 1551 ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number); 1552 goto rvc_imm_done; 1553 case 'j': 1554 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1555 || imm_expr->X_op != O_constant 1556 || imm_expr->X_add_number == 0 1557 || !VALID_RVC_IMM (imm_expr->X_add_number)) 1558 break; 1559 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1560 goto rvc_imm_done; 1561 case 'k': 1562 if (riscv_handle_implicit_zero_offset (imm_expr, s)) 1563 continue; 1564 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1565 || imm_expr->X_op != O_constant 1566 || !VALID_RVC_LW_IMM (imm_expr->X_add_number)) 1567 break; 1568 ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number); 1569 goto rvc_imm_done; 1570 case 'l': 1571 if (riscv_handle_implicit_zero_offset (imm_expr, s)) 1572 continue; 1573 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1574 || imm_expr->X_op != O_constant 1575 || !VALID_RVC_LD_IMM (imm_expr->X_add_number)) 1576 break; 1577 ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number); 1578 goto rvc_imm_done; 1579 case 'm': 1580 if (riscv_handle_implicit_zero_offset (imm_expr, s)) 1581 continue; 1582 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1583 || imm_expr->X_op != O_constant 1584 || !VALID_RVC_LWSP_IMM (imm_expr->X_add_number)) 1585 break; 1586 ip->insn_opcode |= 1587 ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number); 1588 goto rvc_imm_done; 1589 case 'n': 1590 if (riscv_handle_implicit_zero_offset (imm_expr, s)) 1591 continue; 1592 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1593 || imm_expr->X_op != O_constant 1594 || !VALID_RVC_LDSP_IMM (imm_expr->X_add_number)) 1595 break; 1596 ip->insn_opcode |= 1597 ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number); 1598 goto rvc_imm_done; 1599 case 'o': 1600 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1601 || imm_expr->X_op != O_constant 1602 /* C.addiw, c.li, and c.andi allow zero immediate. 1603 C.addi allows zero immediate as hint. Otherwise this 1604 is same as 'j'. */ 1605 || !VALID_RVC_IMM (imm_expr->X_add_number)) 1606 break; 1607 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1608 goto rvc_imm_done; 1609 case 'K': 1610 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1611 || imm_expr->X_op != O_constant 1612 || !VALID_RVC_ADDI4SPN_IMM (imm_expr->X_add_number) 1613 || imm_expr->X_add_number == 0) 1614 break; 1615 ip->insn_opcode |= 1616 ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number); 1617 goto rvc_imm_done; 1618 case 'L': 1619 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1620 || imm_expr->X_op != O_constant 1621 || !VALID_RVC_ADDI16SP_IMM (imm_expr->X_add_number) 1622 || imm_expr->X_add_number == 0) 1623 break; 1624 ip->insn_opcode |= 1625 ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number); 1626 goto rvc_imm_done; 1627 case 'M': 1628 if (riscv_handle_implicit_zero_offset (imm_expr, s)) 1629 continue; 1630 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1631 || imm_expr->X_op != O_constant 1632 || !VALID_RVC_SWSP_IMM (imm_expr->X_add_number)) 1633 break; 1634 ip->insn_opcode |= 1635 ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number); 1636 goto rvc_imm_done; 1637 case 'N': 1638 if (riscv_handle_implicit_zero_offset (imm_expr, s)) 1639 continue; 1640 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1641 || imm_expr->X_op != O_constant 1642 || !VALID_RVC_SDSP_IMM (imm_expr->X_add_number)) 1643 break; 1644 ip->insn_opcode |= 1645 ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number); 1646 goto rvc_imm_done; 1647 case 'u': 1648 p = percent_op_utype; 1649 if (my_getSmallExpression (imm_expr, imm_reloc, s, p)) 1650 break; 1651 rvc_lui: 1652 if (imm_expr->X_op != O_constant 1653 || imm_expr->X_add_number <= 0 1654 || imm_expr->X_add_number >= RISCV_BIGIMM_REACH 1655 || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 1656 && (imm_expr->X_add_number < 1657 RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) 1658 break; 1659 ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number); 1660 goto rvc_imm_done; 1661 case 'v': 1662 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1663 || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) 1664 || ((int32_t)imm_expr->X_add_number 1665 != imm_expr->X_add_number)) 1666 break; 1667 imm_expr->X_add_number = 1668 ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; 1669 goto rvc_lui; 1670 case 'p': 1671 goto branch; 1672 case 'a': 1673 goto jump; 1674 case 'S': /* Floating-point RS1 x8-x15. */ 1675 if (!reg_lookup (&s, RCLASS_FPR, ®no) 1676 || !(regno >= 8 && regno <= 15)) 1677 break; 1678 INSERT_OPERAND (CRS1S, *ip, regno % 8); 1679 continue; 1680 case 'D': /* Floating-point RS2 x8-x15. */ 1681 if (!reg_lookup (&s, RCLASS_FPR, ®no) 1682 || !(regno >= 8 && regno <= 15)) 1683 break; 1684 INSERT_OPERAND (CRS2S, *ip, regno % 8); 1685 continue; 1686 case 'T': /* Floating-point RS2. */ 1687 if (!reg_lookup (&s, RCLASS_FPR, ®no)) 1688 break; 1689 INSERT_OPERAND (CRS2, *ip, regno); 1690 continue; 1691 case 'F': 1692 switch (*++args) 1693 { 1694 case '6': 1695 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1696 || imm_expr->X_op != O_constant 1697 || imm_expr->X_add_number < 0 1698 || imm_expr->X_add_number >= 64) 1699 { 1700 as_bad (_("bad value for funct6 field, " 1701 "value must be 0...64")); 1702 break; 1703 } 1704 1705 INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number); 1706 imm_expr->X_op = O_absent; 1707 s = expr_end; 1708 continue; 1709 case '4': 1710 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1711 || imm_expr->X_op != O_constant 1712 || imm_expr->X_add_number < 0 1713 || imm_expr->X_add_number >= 16) 1714 { 1715 as_bad (_("bad value for funct4 field, " 1716 "value must be 0...15")); 1717 break; 1718 } 1719 1720 INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number); 1721 imm_expr->X_op = O_absent; 1722 s = expr_end; 1723 continue; 1724 case '3': 1725 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1726 || imm_expr->X_op != O_constant 1727 || imm_expr->X_add_number < 0 1728 || imm_expr->X_add_number >= 8) 1729 { 1730 as_bad (_("bad value for funct3 field, " 1731 "value must be 0...7")); 1732 break; 1733 } 1734 INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number); 1735 imm_expr->X_op = O_absent; 1736 s = expr_end; 1737 continue; 1738 case '2': 1739 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 1740 || imm_expr->X_op != O_constant 1741 || imm_expr->X_add_number < 0 1742 || imm_expr->X_add_number >= 4) 1743 { 1744 as_bad (_("bad value for funct2 field, " 1745 "value must be 0...3")); 1746 break; 1747 } 1748 INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number); 1749 imm_expr->X_op = O_absent; 1750 s = expr_end; 1751 continue; 1752 default: 1753 as_bad (_("bad compressed FUNCT field" 1754 " specifier 'CF%c'\n"), 1755 *args); 1756 } 1757 break; 1758 1759 default: 1760 as_bad (_("bad RVC field specifier 'C%c'\n"), *args); 1761 } 1762 break; 1763 1764 case ',': 1765 ++argnum; 1766 if (*s++ == *args) 1767 continue; 1768 s--; 1769 break; 1770 1771 case '(': 1772 case ')': 1773 case '[': 1774 case ']': 1775 if (*s++ == *args) 1776 continue; 1777 break; 1778 1779 case '<': /* Shift amount, 0 - 31. */ 1780 my_getExpression (imm_expr, s); 1781 check_absolute_expr (ip, imm_expr, FALSE); 1782 if ((unsigned long) imm_expr->X_add_number > 31) 1783 as_bad (_("Improper shift amount (%lu)"), 1784 (unsigned long) imm_expr->X_add_number); 1785 INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); 1786 imm_expr->X_op = O_absent; 1787 s = expr_end; 1788 continue; 1789 1790 case '>': /* Shift amount, 0 - (XLEN-1). */ 1791 my_getExpression (imm_expr, s); 1792 check_absolute_expr (ip, imm_expr, FALSE); 1793 if ((unsigned long) imm_expr->X_add_number >= xlen) 1794 as_bad (_("Improper shift amount (%lu)"), 1795 (unsigned long) imm_expr->X_add_number); 1796 INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); 1797 imm_expr->X_op = O_absent; 1798 s = expr_end; 1799 continue; 1800 1801 case 'Z': /* CSRRxI immediate. */ 1802 my_getExpression (imm_expr, s); 1803 check_absolute_expr (ip, imm_expr, FALSE); 1804 if ((unsigned long) imm_expr->X_add_number > 31) 1805 as_bad (_("Improper CSRxI immediate (%lu)"), 1806 (unsigned long) imm_expr->X_add_number); 1807 INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); 1808 imm_expr->X_op = O_absent; 1809 s = expr_end; 1810 continue; 1811 1812 case 'E': /* Control register. */ 1813 if (reg_lookup (&s, RCLASS_CSR, ®no)) 1814 INSERT_OPERAND (CSR, *ip, regno); 1815 else 1816 { 1817 my_getExpression (imm_expr, s); 1818 check_absolute_expr (ip, imm_expr, TRUE); 1819 if ((unsigned long) imm_expr->X_add_number > 0xfff) 1820 as_bad (_("Improper CSR address (%lu)"), 1821 (unsigned long) imm_expr->X_add_number); 1822 INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); 1823 imm_expr->X_op = O_absent; 1824 s = expr_end; 1825 } 1826 continue; 1827 1828 case 'm': /* Rounding mode. */ 1829 if (arg_lookup (&s, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) 1830 { 1831 INSERT_OPERAND (RM, *ip, regno); 1832 continue; 1833 } 1834 break; 1835 1836 case 'P': 1837 case 'Q': /* Fence predecessor/successor. */ 1838 if (arg_lookup (&s, riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ), 1839 ®no)) 1840 { 1841 if (*args == 'P') 1842 INSERT_OPERAND (PRED, *ip, regno); 1843 else 1844 INSERT_OPERAND (SUCC, *ip, regno); 1845 continue; 1846 } 1847 break; 1848 1849 case 'd': /* Destination register. */ 1850 case 's': /* Source register. */ 1851 case 't': /* Target register. */ 1852 case 'r': /* rs3. */ 1853 if (reg_lookup (&s, RCLASS_GPR, ®no)) 1854 { 1855 c = *args; 1856 if (*s == ' ') 1857 ++s; 1858 1859 /* Now that we have assembled one operand, we use the args 1860 string to figure out where it goes in the instruction. */ 1861 switch (c) 1862 { 1863 case 's': 1864 INSERT_OPERAND (RS1, *ip, regno); 1865 break; 1866 case 'd': 1867 INSERT_OPERAND (RD, *ip, regno); 1868 break; 1869 case 't': 1870 INSERT_OPERAND (RS2, *ip, regno); 1871 break; 1872 case 'r': 1873 INSERT_OPERAND (RS3, *ip, regno); 1874 break; 1875 } 1876 continue; 1877 } 1878 break; 1879 1880 case 'D': /* Floating point rd. */ 1881 case 'S': /* Floating point rs1. */ 1882 case 'T': /* Floating point rs2. */ 1883 case 'U': /* Floating point rs1 and rs2. */ 1884 case 'R': /* Floating point rs3. */ 1885 if (reg_lookup (&s, RCLASS_FPR, ®no)) 1886 { 1887 c = *args; 1888 if (*s == ' ') 1889 ++s; 1890 switch (c) 1891 { 1892 case 'D': 1893 INSERT_OPERAND (RD, *ip, regno); 1894 break; 1895 case 'S': 1896 INSERT_OPERAND (RS1, *ip, regno); 1897 break; 1898 case 'U': 1899 INSERT_OPERAND (RS1, *ip, regno); 1900 /* fallthru */ 1901 case 'T': 1902 INSERT_OPERAND (RS2, *ip, regno); 1903 break; 1904 case 'R': 1905 INSERT_OPERAND (RS3, *ip, regno); 1906 break; 1907 } 1908 continue; 1909 } 1910 1911 break; 1912 1913 case 'I': 1914 my_getExpression (imm_expr, s); 1915 if (imm_expr->X_op != O_big 1916 && imm_expr->X_op != O_constant) 1917 break; 1918 normalize_constant_expr (imm_expr); 1919 s = expr_end; 1920 continue; 1921 1922 case 'A': 1923 my_getExpression (imm_expr, s); 1924 normalize_constant_expr (imm_expr); 1925 /* The 'A' format specifier must be a symbol. */ 1926 if (imm_expr->X_op != O_symbol) 1927 break; 1928 *imm_reloc = BFD_RELOC_32; 1929 s = expr_end; 1930 continue; 1931 1932 case 'B': 1933 my_getExpression (imm_expr, s); 1934 normalize_constant_expr (imm_expr); 1935 /* The 'B' format specifier must be a symbol or a constant. */ 1936 if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant) 1937 break; 1938 if (imm_expr->X_op == O_symbol) 1939 *imm_reloc = BFD_RELOC_32; 1940 s = expr_end; 1941 continue; 1942 1943 case 'j': /* Sign-extended immediate. */ 1944 p = percent_op_itype; 1945 *imm_reloc = BFD_RELOC_RISCV_LO12_I; 1946 goto alu_op; 1947 case 'q': /* Store displacement. */ 1948 p = percent_op_stype; 1949 *imm_reloc = BFD_RELOC_RISCV_LO12_S; 1950 goto load_store; 1951 case 'o': /* Load displacement. */ 1952 p = percent_op_itype; 1953 *imm_reloc = BFD_RELOC_RISCV_LO12_I; 1954 goto load_store; 1955 case '1': /* 4-operand add, must be %tprel_add. */ 1956 p = percent_op_rtype; 1957 goto alu_op; 1958 case '0': /* AMO "displacement," which must be zero. */ 1959 p = percent_op_null; 1960 load_store: 1961 if (riscv_handle_implicit_zero_offset (imm_expr, s)) 1962 continue; 1963 alu_op: 1964 /* If this value won't fit into a 16 bit offset, then go 1965 find a macro that will generate the 32 bit offset 1966 code pattern. */ 1967 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) 1968 { 1969 normalize_constant_expr (imm_expr); 1970 if (imm_expr->X_op != O_constant 1971 || (*args == '0' && imm_expr->X_add_number != 0) 1972 || (*args == '1') 1973 || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 1974 || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) 1975 break; 1976 } 1977 1978 s = expr_end; 1979 continue; 1980 1981 case 'p': /* PC-relative offset. */ 1982 branch: 1983 *imm_reloc = BFD_RELOC_12_PCREL; 1984 my_getExpression (imm_expr, s); 1985 s = expr_end; 1986 continue; 1987 1988 case 'u': /* Upper 20 bits. */ 1989 p = percent_op_utype; 1990 if (!my_getSmallExpression (imm_expr, imm_reloc, s, p)) 1991 { 1992 if (imm_expr->X_op != O_constant) 1993 break; 1994 1995 if (imm_expr->X_add_number < 0 1996 || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) 1997 as_bad (_("lui expression not in range 0..1048575")); 1998 1999 *imm_reloc = BFD_RELOC_RISCV_HI20; 2000 imm_expr->X_add_number <<= RISCV_IMM_BITS; 2001 } 2002 s = expr_end; 2003 continue; 2004 2005 case 'a': /* 20-bit PC-relative offset. */ 2006 jump: 2007 my_getExpression (imm_expr, s); 2008 s = expr_end; 2009 *imm_reloc = BFD_RELOC_RISCV_JMP; 2010 continue; 2011 2012 case 'c': 2013 my_getExpression (imm_expr, s); 2014 s = expr_end; 2015 if (strcmp (s, "@plt") == 0) 2016 { 2017 *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; 2018 s += 4; 2019 } 2020 else 2021 *imm_reloc = BFD_RELOC_RISCV_CALL; 2022 continue; 2023 case 'O': 2024 switch (*++args) 2025 { 2026 case '4': 2027 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) 2028 || imm_expr->X_op != O_constant 2029 || imm_expr->X_add_number < 0 2030 || imm_expr->X_add_number >= 128 2031 || (imm_expr->X_add_number & 0x3) != 3) 2032 { 2033 as_bad (_("bad value for opcode field, " 2034 "value must be 0...127 and " 2035 "lower 2 bits must be 0x3")); 2036 break; 2037 } 2038 2039 INSERT_OPERAND (OP, *ip, imm_expr->X_add_number); 2040 imm_expr->X_op = O_absent; 2041 s = expr_end; 2042 continue; 2043 case '2': 2044 if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p) 2045 || imm_expr->X_op != O_constant 2046 || imm_expr->X_add_number < 0 2047 || imm_expr->X_add_number >= 3) 2048 { 2049 as_bad (_("bad value for opcode field, " 2050 "value must be 0...2")); 2051 break; 2052 } 2053 2054 INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number); 2055 imm_expr->X_op = O_absent; 2056 s = expr_end; 2057 continue; 2058 default: 2059 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args); 2060 } 2061 break; 2062 2063 case 'F': 2064 switch (*++args) 2065 { 2066 case '7': 2067 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 2068 || imm_expr->X_op != O_constant 2069 || imm_expr->X_add_number < 0 2070 || imm_expr->X_add_number >= 128) 2071 { 2072 as_bad (_("bad value for funct7 field, " 2073 "value must be 0...127")); 2074 break; 2075 } 2076 2077 INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); 2078 imm_expr->X_op = O_absent; 2079 s = expr_end; 2080 continue; 2081 case '3': 2082 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 2083 || imm_expr->X_op != O_constant 2084 || imm_expr->X_add_number < 0 2085 || imm_expr->X_add_number >= 8) 2086 { 2087 as_bad (_("bad value for funct3 field, " 2088 "value must be 0...7")); 2089 break; 2090 } 2091 2092 INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); 2093 imm_expr->X_op = O_absent; 2094 s = expr_end; 2095 continue; 2096 case '2': 2097 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 2098 || imm_expr->X_op != O_constant 2099 || imm_expr->X_add_number < 0 2100 || imm_expr->X_add_number >= 4) 2101 { 2102 as_bad (_("bad value for funct2 field, " 2103 "value must be 0...3")); 2104 break; 2105 } 2106 2107 INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number); 2108 imm_expr->X_op = O_absent; 2109 s = expr_end; 2110 continue; 2111 2112 default: 2113 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args); 2114 } 2115 break; 2116 2117 case 'z': 2118 if (my_getSmallExpression (imm_expr, imm_reloc, s, p) 2119 || imm_expr->X_op != O_constant 2120 || imm_expr->X_add_number != 0) 2121 break; 2122 s = expr_end; 2123 imm_expr->X_op = O_absent; 2124 continue; 2125 2126 default: 2127 as_fatal (_("internal error: bad argument type %c"), *args); 2128 } 2129 break; 2130 } 2131 s = argsStart; 2132 error = _("illegal operands"); 2133 } 2134 2135 out: 2136 /* Restore the character we might have clobbered above. */ 2137 if (save_c) 2138 *(argsStart - 1) = save_c; 2139 2140 return error; 2141 } 2142 2143 void 2144 md_assemble (char *str) 2145 { 2146 struct riscv_cl_insn insn; 2147 expressionS imm_expr; 2148 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; 2149 2150 const char *error = riscv_ip (str, &insn, &imm_expr, &imm_reloc, op_hash); 2151 2152 start_assemble = TRUE; 2153 2154 if (error) 2155 { 2156 as_bad ("%s `%s'", error, str); 2157 return; 2158 } 2159 2160 if (insn.insn_mo->pinfo == INSN_MACRO) 2161 macro (&insn, &imm_expr, &imm_reloc); 2162 else 2163 append_insn (&insn, &imm_expr, imm_reloc); 2164 } 2165 2166 const char * 2167 md_atof (int type, char *litP, int *sizeP) 2168 { 2169 return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); 2170 } 2171 2172 void 2173 md_number_to_chars (char *buf, valueT val, int n) 2174 { 2175 number_to_chars_littleendian (buf, val, n); 2176 } 2177 2178 const char *md_shortopts = "O::g::G:"; 2179 2180 enum options 2181 { 2182 OPTION_MARCH = OPTION_MD_BASE, 2183 OPTION_PIC, 2184 OPTION_NO_PIC, 2185 OPTION_MABI, 2186 OPTION_RELAX, 2187 OPTION_NO_RELAX, 2188 OPTION_ARCH_ATTR, 2189 OPTION_NO_ARCH_ATTR, 2190 OPTION_END_OF_ENUM 2191 }; 2192 2193 struct option md_longopts[] = 2194 { 2195 {"march", required_argument, NULL, OPTION_MARCH}, 2196 {"fPIC", no_argument, NULL, OPTION_PIC}, 2197 {"fpic", no_argument, NULL, OPTION_PIC}, 2198 {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, 2199 {"mabi", required_argument, NULL, OPTION_MABI}, 2200 {"mrelax", no_argument, NULL, OPTION_RELAX}, 2201 {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, 2202 {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR}, 2203 {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR}, 2204 2205 {NULL, no_argument, NULL, 0} 2206 }; 2207 size_t md_longopts_size = sizeof (md_longopts); 2208 2209 enum float_abi { 2210 FLOAT_ABI_DEFAULT = -1, 2211 FLOAT_ABI_SOFT, 2212 FLOAT_ABI_SINGLE, 2213 FLOAT_ABI_DOUBLE, 2214 FLOAT_ABI_QUAD 2215 }; 2216 static enum float_abi float_abi = FLOAT_ABI_DEFAULT; 2217 2218 static void 2219 riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bfd_boolean rve) 2220 { 2221 abi_xlen = new_xlen; 2222 float_abi = new_float_abi; 2223 rve_abi = rve; 2224 } 2225 2226 int 2227 md_parse_option (int c, const char *arg) 2228 { 2229 switch (c) 2230 { 2231 case OPTION_MARCH: 2232 riscv_set_arch (arg); 2233 break; 2234 2235 case OPTION_NO_PIC: 2236 riscv_opts.pic = FALSE; 2237 break; 2238 2239 case OPTION_PIC: 2240 riscv_opts.pic = TRUE; 2241 break; 2242 2243 case OPTION_MABI: 2244 if (strcmp (arg, "ilp32") == 0) 2245 riscv_set_abi (32, FLOAT_ABI_SOFT, FALSE); 2246 else if (strcmp (arg, "ilp32e") == 0) 2247 riscv_set_abi (32, FLOAT_ABI_SOFT, TRUE); 2248 else if (strcmp (arg, "ilp32f") == 0) 2249 riscv_set_abi (32, FLOAT_ABI_SINGLE, FALSE); 2250 else if (strcmp (arg, "ilp32d") == 0) 2251 riscv_set_abi (32, FLOAT_ABI_DOUBLE, FALSE); 2252 else if (strcmp (arg, "ilp32q") == 0) 2253 riscv_set_abi (32, FLOAT_ABI_QUAD, FALSE); 2254 else if (strcmp (arg, "lp64") == 0) 2255 riscv_set_abi (64, FLOAT_ABI_SOFT, FALSE); 2256 else if (strcmp (arg, "lp64f") == 0) 2257 riscv_set_abi (64, FLOAT_ABI_SINGLE, FALSE); 2258 else if (strcmp (arg, "lp64d") == 0) 2259 riscv_set_abi (64, FLOAT_ABI_DOUBLE, FALSE); 2260 else if (strcmp (arg, "lp64q") == 0) 2261 riscv_set_abi (64, FLOAT_ABI_QUAD, FALSE); 2262 else 2263 return 0; 2264 break; 2265 2266 case OPTION_RELAX: 2267 riscv_opts.relax = TRUE; 2268 break; 2269 2270 case OPTION_NO_RELAX: 2271 riscv_opts.relax = FALSE; 2272 break; 2273 2274 case OPTION_ARCH_ATTR: 2275 riscv_opts.arch_attr = TRUE; 2276 break; 2277 2278 case OPTION_NO_ARCH_ATTR: 2279 riscv_opts.arch_attr = FALSE; 2280 break; 2281 2282 default: 2283 return 0; 2284 } 2285 2286 return 1; 2287 } 2288 2289 void 2290 riscv_after_parse_args (void) 2291 { 2292 if (xlen == 0) 2293 { 2294 if (strcmp (default_arch, "riscv32") == 0) 2295 xlen = 32; 2296 else if (strcmp (default_arch, "riscv64") == 0) 2297 xlen = 64; 2298 else 2299 as_bad ("unknown default architecture `%s'", default_arch); 2300 } 2301 2302 if (riscv_subsets.head == NULL) 2303 riscv_set_arch (xlen == 64 ? "rv64g" : "rv32g"); 2304 2305 /* Add the RVC extension, regardless of -march, to support .option rvc. */ 2306 riscv_set_rvc (FALSE); 2307 if (riscv_subset_supports ("c")) 2308 riscv_set_rvc (TRUE); 2309 2310 /* Enable RVE if specified by the -march option. */ 2311 riscv_set_rve (FALSE); 2312 if (riscv_subset_supports ("e")) 2313 riscv_set_rve (TRUE); 2314 2315 /* Infer ABI from ISA if not specified on command line. */ 2316 if (abi_xlen == 0) 2317 abi_xlen = xlen; 2318 else if (abi_xlen > xlen) 2319 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); 2320 else if (abi_xlen < xlen) 2321 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); 2322 2323 if (float_abi == FLOAT_ABI_DEFAULT) 2324 { 2325 riscv_subset_t *subset; 2326 2327 /* Assume soft-float unless D extension is present. */ 2328 float_abi = FLOAT_ABI_SOFT; 2329 2330 for (subset = riscv_subsets.head; subset != NULL; subset = subset->next) 2331 { 2332 if (strcasecmp (subset->name, "D") == 0) 2333 float_abi = FLOAT_ABI_DOUBLE; 2334 if (strcasecmp (subset->name, "Q") == 0) 2335 float_abi = FLOAT_ABI_QUAD; 2336 } 2337 } 2338 2339 if (rve_abi) 2340 elf_flags |= EF_RISCV_RVE; 2341 2342 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */ 2343 elf_flags |= float_abi * (EF_RISCV_FLOAT_ABI & ~(EF_RISCV_FLOAT_ABI << 1)); 2344 2345 /* If the CIE to be produced has not been overridden on the command line, 2346 then produce version 3 by default. This allows us to use the full 2347 range of registers in a .cfi_return_column directive. */ 2348 if (flag_dwarf_cie_version == -1) 2349 flag_dwarf_cie_version = 3; 2350 } 2351 2352 long 2353 md_pcrel_from (fixS *fixP) 2354 { 2355 return fixP->fx_where + fixP->fx_frag->fr_address; 2356 } 2357 2358 /* Apply a fixup to the object file. */ 2359 2360 void 2361 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 2362 { 2363 unsigned int subtype; 2364 bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); 2365 bfd_boolean relaxable = FALSE; 2366 offsetT loc; 2367 segT sub_segment; 2368 2369 /* Remember value for tc_gen_reloc. */ 2370 fixP->fx_addnumber = *valP; 2371 2372 switch (fixP->fx_r_type) 2373 { 2374 case BFD_RELOC_RISCV_HI20: 2375 case BFD_RELOC_RISCV_LO12_I: 2376 case BFD_RELOC_RISCV_LO12_S: 2377 bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) 2378 | bfd_getl32 (buf), buf); 2379 if (fixP->fx_addsy == NULL) 2380 fixP->fx_done = TRUE; 2381 relaxable = TRUE; 2382 break; 2383 2384 case BFD_RELOC_RISCV_GOT_HI20: 2385 case BFD_RELOC_RISCV_ADD8: 2386 case BFD_RELOC_RISCV_ADD16: 2387 case BFD_RELOC_RISCV_ADD32: 2388 case BFD_RELOC_RISCV_ADD64: 2389 case BFD_RELOC_RISCV_SUB6: 2390 case BFD_RELOC_RISCV_SUB8: 2391 case BFD_RELOC_RISCV_SUB16: 2392 case BFD_RELOC_RISCV_SUB32: 2393 case BFD_RELOC_RISCV_SUB64: 2394 case BFD_RELOC_RISCV_RELAX: 2395 break; 2396 2397 case BFD_RELOC_RISCV_TPREL_HI20: 2398 case BFD_RELOC_RISCV_TPREL_LO12_I: 2399 case BFD_RELOC_RISCV_TPREL_LO12_S: 2400 case BFD_RELOC_RISCV_TPREL_ADD: 2401 relaxable = TRUE; 2402 /* Fall through. */ 2403 2404 case BFD_RELOC_RISCV_TLS_GOT_HI20: 2405 case BFD_RELOC_RISCV_TLS_GD_HI20: 2406 case BFD_RELOC_RISCV_TLS_DTPREL32: 2407 case BFD_RELOC_RISCV_TLS_DTPREL64: 2408 if (fixP->fx_addsy != NULL) 2409 S_SET_THREAD_LOCAL (fixP->fx_addsy); 2410 else 2411 as_bad_where (fixP->fx_file, fixP->fx_line, 2412 _("TLS relocation against a constant")); 2413 break; 2414 2415 case BFD_RELOC_32: 2416 /* Use pc-relative relocation for FDE initial location. 2417 The symbol address in .eh_frame may be adjusted in 2418 _bfd_elf_discard_section_eh_frame, and the content of 2419 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. 2420 Therefore, we cannot insert a relocation whose addend symbol is 2421 in .eh_frame. Othrewise, the value may be adjusted twice.*/ 2422 if (fixP->fx_addsy && fixP->fx_subsy 2423 && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) 2424 && strcmp (sub_segment->name, ".eh_frame") == 0 2425 && S_GET_VALUE (fixP->fx_subsy) 2426 == fixP->fx_frag->fr_address + fixP->fx_where) 2427 { 2428 fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL; 2429 fixP->fx_subsy = NULL; 2430 break; 2431 } 2432 /* Fall through. */ 2433 case BFD_RELOC_64: 2434 case BFD_RELOC_16: 2435 case BFD_RELOC_8: 2436 case BFD_RELOC_RISCV_CFA: 2437 if (fixP->fx_addsy && fixP->fx_subsy) 2438 { 2439 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); 2440 fixP->fx_next->fx_addsy = fixP->fx_subsy; 2441 fixP->fx_next->fx_subsy = NULL; 2442 fixP->fx_next->fx_offset = 0; 2443 fixP->fx_subsy = NULL; 2444 2445 switch (fixP->fx_r_type) 2446 { 2447 case BFD_RELOC_64: 2448 fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; 2449 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; 2450 break; 2451 2452 case BFD_RELOC_32: 2453 fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; 2454 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; 2455 break; 2456 2457 case BFD_RELOC_16: 2458 fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; 2459 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; 2460 break; 2461 2462 case BFD_RELOC_8: 2463 fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; 2464 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; 2465 break; 2466 2467 case BFD_RELOC_RISCV_CFA: 2468 /* Load the byte to get the subtype. */ 2469 subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); 2470 loc = fixP->fx_frag->fr_fix - (subtype & 7); 2471 switch (subtype) 2472 { 2473 case DW_CFA_advance_loc1: 2474 fixP->fx_where = loc + 1; 2475 fixP->fx_next->fx_where = loc + 1; 2476 fixP->fx_r_type = BFD_RELOC_RISCV_SET8; 2477 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; 2478 break; 2479 2480 case DW_CFA_advance_loc2: 2481 fixP->fx_size = 2; 2482 fixP->fx_next->fx_size = 2; 2483 fixP->fx_where = loc + 1; 2484 fixP->fx_next->fx_where = loc + 1; 2485 fixP->fx_r_type = BFD_RELOC_RISCV_SET16; 2486 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; 2487 break; 2488 2489 case DW_CFA_advance_loc4: 2490 fixP->fx_size = 4; 2491 fixP->fx_next->fx_size = 4; 2492 fixP->fx_where = loc; 2493 fixP->fx_next->fx_where = loc; 2494 fixP->fx_r_type = BFD_RELOC_RISCV_SET32; 2495 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; 2496 break; 2497 2498 default: 2499 if (subtype < 0x80 && (subtype & 0x40)) 2500 { 2501 /* DW_CFA_advance_loc */ 2502 fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; 2503 fixP->fx_next->fx_frag = fixP->fx_frag; 2504 fixP->fx_r_type = BFD_RELOC_RISCV_SET6; 2505 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; 2506 } 2507 else 2508 as_fatal (_("internal error: bad CFA value #%d"), subtype); 2509 break; 2510 } 2511 break; 2512 2513 default: 2514 /* This case is unreachable. */ 2515 abort (); 2516 } 2517 } 2518 /* Fall through. */ 2519 2520 case BFD_RELOC_RVA: 2521 /* If we are deleting this reloc entry, we must fill in the 2522 value now. This can happen if we have a .word which is not 2523 resolved when it appears but is later defined. */ 2524 if (fixP->fx_addsy == NULL) 2525 { 2526 gas_assert (fixP->fx_size <= sizeof (valueT)); 2527 md_number_to_chars ((char *) buf, *valP, fixP->fx_size); 2528 fixP->fx_done = 1; 2529 } 2530 break; 2531 2532 case BFD_RELOC_RISCV_JMP: 2533 if (fixP->fx_addsy) 2534 { 2535 /* Fill in a tentative value to improve objdump readability. */ 2536 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2537 bfd_vma delta = target - md_pcrel_from (fixP); 2538 bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf); 2539 } 2540 break; 2541 2542 case BFD_RELOC_12_PCREL: 2543 if (fixP->fx_addsy) 2544 { 2545 /* Fill in a tentative value to improve objdump readability. */ 2546 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2547 bfd_vma delta = target - md_pcrel_from (fixP); 2548 bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf); 2549 } 2550 break; 2551 2552 case BFD_RELOC_RISCV_RVC_BRANCH: 2553 if (fixP->fx_addsy) 2554 { 2555 /* Fill in a tentative value to improve objdump readability. */ 2556 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2557 bfd_vma delta = target - md_pcrel_from (fixP); 2558 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf); 2559 } 2560 break; 2561 2562 case BFD_RELOC_RISCV_RVC_JUMP: 2563 if (fixP->fx_addsy) 2564 { 2565 /* Fill in a tentative value to improve objdump readability. */ 2566 bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; 2567 bfd_vma delta = target - md_pcrel_from (fixP); 2568 bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf); 2569 } 2570 break; 2571 2572 case BFD_RELOC_RISCV_CALL: 2573 case BFD_RELOC_RISCV_CALL_PLT: 2574 relaxable = TRUE; 2575 break; 2576 2577 case BFD_RELOC_RISCV_PCREL_HI20: 2578 case BFD_RELOC_RISCV_PCREL_LO12_S: 2579 case BFD_RELOC_RISCV_PCREL_LO12_I: 2580 relaxable = riscv_opts.relax; 2581 break; 2582 2583 case BFD_RELOC_RISCV_ALIGN: 2584 break; 2585 2586 default: 2587 /* We ignore generic BFD relocations we don't know about. */ 2588 if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) 2589 as_fatal (_("internal error: bad relocation #%d"), fixP->fx_r_type); 2590 } 2591 2592 if (fixP->fx_subsy != NULL) 2593 as_bad_where (fixP->fx_file, fixP->fx_line, 2594 _("unsupported symbol subtraction")); 2595 2596 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ 2597 if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) 2598 { 2599 fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); 2600 fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; 2601 fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; 2602 } 2603 } 2604 2605 /* Because the value of .cfi_remember_state may changed after relaxation, 2606 we insert a fix to relocate it again in link-time. */ 2607 2608 void 2609 riscv_pre_output_hook (void) 2610 { 2611 const frchainS *frch; 2612 const asection *s; 2613 2614 for (s = stdoutput->sections; s; s = s->next) 2615 for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) 2616 { 2617 fragS *frag; 2618 2619 for (frag = frch->frch_root; frag; frag = frag->fr_next) 2620 { 2621 if (frag->fr_type == rs_cfa) 2622 { 2623 expressionS exp; 2624 expressionS *symval; 2625 2626 symval = symbol_get_value_expression (frag->fr_symbol); 2627 exp.X_op = O_subtract; 2628 exp.X_add_symbol = symval->X_add_symbol; 2629 exp.X_add_number = 0; 2630 exp.X_op_symbol = symval->X_op_symbol; 2631 2632 fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, 2633 BFD_RELOC_RISCV_CFA); 2634 } 2635 } 2636 } 2637 } 2638 2639 2640 /* This structure is used to hold a stack of .option values. */ 2641 2642 struct riscv_option_stack 2643 { 2644 struct riscv_option_stack *next; 2645 struct riscv_set_options options; 2646 }; 2647 2648 static struct riscv_option_stack *riscv_opts_stack; 2649 2650 /* Handle the .option pseudo-op. */ 2651 2652 static void 2653 s_riscv_option (int x ATTRIBUTE_UNUSED) 2654 { 2655 char *name = input_line_pointer, ch; 2656 2657 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 2658 ++input_line_pointer; 2659 ch = *input_line_pointer; 2660 *input_line_pointer = '\0'; 2661 2662 if (strcmp (name, "rvc") == 0) 2663 riscv_set_rvc (TRUE); 2664 else if (strcmp (name, "norvc") == 0) 2665 riscv_set_rvc (FALSE); 2666 else if (strcmp (name, "pic") == 0) 2667 riscv_opts.pic = TRUE; 2668 else if (strcmp (name, "nopic") == 0) 2669 riscv_opts.pic = FALSE; 2670 else if (strcmp (name, "relax") == 0) 2671 riscv_opts.relax = TRUE; 2672 else if (strcmp (name, "norelax") == 0) 2673 riscv_opts.relax = FALSE; 2674 else if (strcmp (name, "push") == 0) 2675 { 2676 struct riscv_option_stack *s; 2677 2678 s = (struct riscv_option_stack *) xmalloc (sizeof *s); 2679 s->next = riscv_opts_stack; 2680 s->options = riscv_opts; 2681 riscv_opts_stack = s; 2682 } 2683 else if (strcmp (name, "pop") == 0) 2684 { 2685 struct riscv_option_stack *s; 2686 2687 s = riscv_opts_stack; 2688 if (s == NULL) 2689 as_bad (_(".option pop with no .option push")); 2690 else 2691 { 2692 riscv_opts = s->options; 2693 riscv_opts_stack = s->next; 2694 free (s); 2695 } 2696 } 2697 else 2698 { 2699 as_warn (_("Unrecognized .option directive: %s\n"), name); 2700 } 2701 *input_line_pointer = ch; 2702 demand_empty_rest_of_line (); 2703 } 2704 2705 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate 2706 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for 2707 use in DWARF debug information. */ 2708 2709 static void 2710 s_dtprel (int bytes) 2711 { 2712 expressionS ex; 2713 char *p; 2714 2715 expression (&ex); 2716 2717 if (ex.X_op != O_symbol) 2718 { 2719 as_bad (_("Unsupported use of %s"), (bytes == 8 2720 ? ".dtpreldword" 2721 : ".dtprelword")); 2722 ignore_rest_of_line (); 2723 } 2724 2725 p = frag_more (bytes); 2726 md_number_to_chars (p, 0, bytes); 2727 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, 2728 (bytes == 8 2729 ? BFD_RELOC_RISCV_TLS_DTPREL64 2730 : BFD_RELOC_RISCV_TLS_DTPREL32)); 2731 2732 demand_empty_rest_of_line (); 2733 } 2734 2735 /* Handle the .bss pseudo-op. */ 2736 2737 static void 2738 s_bss (int ignore ATTRIBUTE_UNUSED) 2739 { 2740 subseg_set (bss_section, 0); 2741 demand_empty_rest_of_line (); 2742 } 2743 2744 static void 2745 riscv_make_nops (char *buf, bfd_vma bytes) 2746 { 2747 bfd_vma i = 0; 2748 2749 /* RISC-V instructions cannot begin or end on odd addresses, so this case 2750 means we are not within a valid instruction sequence. It is thus safe 2751 to use a zero byte, even though that is not a valid instruction. */ 2752 if (bytes % 2 == 1) 2753 buf[i++] = 0; 2754 2755 /* Use at most one 2-byte NOP. */ 2756 if ((bytes - i) % 4 == 2) 2757 { 2758 md_number_to_chars (buf + i, RVC_NOP, 2); 2759 i += 2; 2760 } 2761 2762 /* Fill the remainder with 4-byte NOPs. */ 2763 for ( ; i < bytes; i += 4) 2764 md_number_to_chars (buf + i, RISCV_NOP, 4); 2765 } 2766 2767 /* Called from md_do_align. Used to create an alignment frag in a 2768 code section by emitting a worst-case NOP sequence that the linker 2769 will later relax to the correct number of NOPs. We can't compute 2770 the correct alignment now because of other linker relaxations. */ 2771 2772 bfd_boolean 2773 riscv_frag_align_code (int n) 2774 { 2775 bfd_vma bytes = (bfd_vma) 1 << n; 2776 bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4; 2777 bfd_vma worst_case_bytes = bytes - insn_alignment; 2778 char *nops; 2779 expressionS ex; 2780 2781 /* If we are moving to a smaller alignment than the instruction size, then no 2782 alignment is required. */ 2783 if (bytes <= insn_alignment) 2784 return TRUE; 2785 2786 /* When not relaxing, riscv_handle_align handles code alignment. */ 2787 if (!riscv_opts.relax) 2788 return FALSE; 2789 2790 nops = frag_more (worst_case_bytes); 2791 2792 ex.X_op = O_constant; 2793 ex.X_add_number = worst_case_bytes; 2794 2795 riscv_make_nops (nops, worst_case_bytes); 2796 2797 fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, 2798 &ex, FALSE, BFD_RELOC_RISCV_ALIGN); 2799 2800 return TRUE; 2801 } 2802 2803 /* Implement HANDLE_ALIGN. */ 2804 2805 void 2806 riscv_handle_align (fragS *fragP) 2807 { 2808 switch (fragP->fr_type) 2809 { 2810 case rs_align_code: 2811 /* When relaxing, riscv_frag_align_code handles code alignment. */ 2812 if (!riscv_opts.relax) 2813 { 2814 bfd_signed_vma bytes = (fragP->fr_next->fr_address 2815 - fragP->fr_address - fragP->fr_fix); 2816 /* We have 4 byte uncompressed nops. */ 2817 bfd_signed_vma size = 4; 2818 bfd_signed_vma excess = bytes % size; 2819 char *p = fragP->fr_literal + fragP->fr_fix; 2820 2821 if (bytes <= 0) 2822 break; 2823 2824 /* Insert zeros or compressed nops to get 4 byte alignment. */ 2825 if (excess) 2826 { 2827 riscv_make_nops (p, excess); 2828 fragP->fr_fix += excess; 2829 p += excess; 2830 } 2831 2832 /* Insert variable number of 4 byte uncompressed nops. */ 2833 riscv_make_nops (p, size); 2834 fragP->fr_var = size; 2835 } 2836 break; 2837 2838 default: 2839 break; 2840 } 2841 } 2842 2843 int 2844 md_estimate_size_before_relax (fragS *fragp, asection *segtype) 2845 { 2846 return (fragp->fr_var = relaxed_branch_length (fragp, segtype, FALSE)); 2847 } 2848 2849 /* Translate internal representation of relocation info to BFD target 2850 format. */ 2851 2852 arelent * 2853 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 2854 { 2855 arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); 2856 2857 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 2858 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 2859 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 2860 reloc->addend = fixp->fx_addnumber; 2861 2862 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 2863 if (reloc->howto == NULL) 2864 { 2865 if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) 2866 && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) 2867 { 2868 /* We don't have R_RISCV_8/16, but for this special case, 2869 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ 2870 return reloc; 2871 } 2872 2873 as_bad_where (fixp->fx_file, fixp->fx_line, 2874 _("cannot represent %s relocation in object file"), 2875 bfd_get_reloc_code_name (fixp->fx_r_type)); 2876 return NULL; 2877 } 2878 2879 return reloc; 2880 } 2881 2882 int 2883 riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) 2884 { 2885 if (RELAX_BRANCH_P (fragp->fr_subtype)) 2886 { 2887 offsetT old_var = fragp->fr_var; 2888 fragp->fr_var = relaxed_branch_length (fragp, sec, TRUE); 2889 return fragp->fr_var - old_var; 2890 } 2891 2892 return 0; 2893 } 2894 2895 /* Expand far branches to multi-instruction sequences. */ 2896 2897 static void 2898 md_convert_frag_branch (fragS *fragp) 2899 { 2900 bfd_byte *buf; 2901 expressionS exp; 2902 fixS *fixp; 2903 insn_t insn; 2904 int rs1, reloc; 2905 2906 buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; 2907 2908 exp.X_op = O_symbol; 2909 exp.X_add_symbol = fragp->fr_symbol; 2910 exp.X_add_number = fragp->fr_offset; 2911 2912 gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); 2913 2914 if (RELAX_BRANCH_RVC (fragp->fr_subtype)) 2915 { 2916 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) 2917 { 2918 case 8: 2919 case 4: 2920 /* Expand the RVC branch into a RISC-V one. */ 2921 insn = bfd_getl16 (buf); 2922 rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); 2923 if ((insn & MASK_C_J) == MATCH_C_J) 2924 insn = MATCH_JAL; 2925 else if ((insn & MASK_C_JAL) == MATCH_C_JAL) 2926 insn = MATCH_JAL | (X_RA << OP_SH_RD); 2927 else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) 2928 insn = MATCH_BEQ | (rs1 << OP_SH_RS1); 2929 else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) 2930 insn = MATCH_BNE | (rs1 << OP_SH_RS1); 2931 else 2932 abort (); 2933 bfd_putl32 (insn, buf); 2934 break; 2935 2936 case 6: 2937 /* Invert the branch condition. Branch over the jump. */ 2938 insn = bfd_getl16 (buf); 2939 insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; 2940 insn |= ENCODE_RVC_B_IMM (6); 2941 bfd_putl16 (insn, buf); 2942 buf += 2; 2943 goto jump; 2944 2945 case 2: 2946 /* Just keep the RVC branch. */ 2947 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) 2948 ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; 2949 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 2950 2, &exp, FALSE, reloc); 2951 buf += 2; 2952 goto done; 2953 2954 default: 2955 abort (); 2956 } 2957 } 2958 2959 switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) 2960 { 2961 case 8: 2962 gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); 2963 2964 /* Invert the branch condition. Branch over the jump. */ 2965 insn = bfd_getl32 (buf); 2966 insn ^= MATCH_BEQ ^ MATCH_BNE; 2967 insn |= ENCODE_SBTYPE_IMM (8); 2968 md_number_to_chars ((char *) buf, insn, 4); 2969 buf += 4; 2970 2971 jump: 2972 /* Jump to the target. */ 2973 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 2974 4, &exp, FALSE, BFD_RELOC_RISCV_JMP); 2975 md_number_to_chars ((char *) buf, MATCH_JAL, 4); 2976 buf += 4; 2977 break; 2978 2979 case 4: 2980 reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) 2981 ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; 2982 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, 2983 4, &exp, FALSE, reloc); 2984 buf += 4; 2985 break; 2986 2987 default: 2988 abort (); 2989 } 2990 2991 done: 2992 fixp->fx_file = fragp->fr_file; 2993 fixp->fx_line = fragp->fr_line; 2994 2995 gas_assert (buf == (bfd_byte *)fragp->fr_literal 2996 + fragp->fr_fix + fragp->fr_var); 2997 2998 fragp->fr_fix += fragp->fr_var; 2999 } 3000 3001 /* Relax a machine dependent frag. This returns the amount by which 3002 the current size of the frag should change. */ 3003 3004 void 3005 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, 3006 fragS *fragp) 3007 { 3008 gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); 3009 md_convert_frag_branch (fragp); 3010 } 3011 3012 void 3013 md_show_usage (FILE *stream) 3014 { 3015 fprintf (stream, _("\ 3016 RISC-V options:\n\ 3017 -fpic generate position-independent code\n\ 3018 -fno-pic don't generate position-independent code (default)\n\ 3019 -march=ISA set the RISC-V architecture\n\ 3020 -mabi=ABI set the RISC-V ABI\n\ 3021 -mrelax enable relax (default)\n\ 3022 -mno-relax disable relax\n\ 3023 -march-attr generate RISC-V arch attribute\n\ 3024 -mno-arch-attr don't generate RISC-V arch attribute\n\ 3025 ")); 3026 } 3027 3028 /* Standard calling conventions leave the CFA at SP on entry. */ 3029 void 3030 riscv_cfi_frame_initial_instructions (void) 3031 { 3032 cfi_add_CFA_def_cfa_register (X_SP); 3033 } 3034 3035 int 3036 tc_riscv_regname_to_dw2regnum (char *regname) 3037 { 3038 int reg; 3039 3040 if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) 3041 return reg; 3042 3043 if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) 3044 return reg + 32; 3045 3046 /* CSRs are numbered 4096 -> 8191. */ 3047 if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0) 3048 return reg + 4096; 3049 3050 as_bad (_("unknown register `%s'"), regname); 3051 return -1; 3052 } 3053 3054 void 3055 riscv_elf_final_processing (void) 3056 { 3057 elf_elfheader (stdoutput)->e_flags |= elf_flags; 3058 } 3059 3060 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, 3061 since these directives break relaxation when used with symbol deltas. */ 3062 3063 static void 3064 s_riscv_leb128 (int sign) 3065 { 3066 expressionS exp; 3067 char *save_in = input_line_pointer; 3068 3069 expression (&exp); 3070 if (exp.X_op != O_constant) 3071 as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); 3072 demand_empty_rest_of_line (); 3073 3074 input_line_pointer = save_in; 3075 return s_leb128 (sign); 3076 } 3077 3078 /* Parse the .insn directive. */ 3079 3080 static void 3081 s_riscv_insn (int x ATTRIBUTE_UNUSED) 3082 { 3083 char *str = input_line_pointer; 3084 struct riscv_cl_insn insn; 3085 expressionS imm_expr; 3086 bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; 3087 char save_c; 3088 3089 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 3090 ++input_line_pointer; 3091 3092 save_c = *input_line_pointer; 3093 *input_line_pointer = '\0'; 3094 3095 const char *error = riscv_ip (str, &insn, &imm_expr, 3096 &imm_reloc, insn_type_hash); 3097 3098 if (error) 3099 { 3100 as_bad ("%s `%s'", error, str); 3101 } 3102 else 3103 { 3104 gas_assert (insn.insn_mo->pinfo != INSN_MACRO); 3105 append_insn (&insn, &imm_expr, imm_reloc); 3106 } 3107 3108 *input_line_pointer = save_c; 3109 demand_empty_rest_of_line (); 3110 } 3111 3112 /* Update arch attributes. */ 3113 3114 static void 3115 riscv_write_out_arch_attr (void) 3116 { 3117 const char *arch_str = riscv_arch_str (xlen, &riscv_subsets); 3118 3119 bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str); 3120 3121 xfree ((void *)arch_str); 3122 } 3123 3124 /* Add the default contents for the .riscv.attributes section. */ 3125 3126 static void 3127 riscv_set_public_attributes (void) 3128 { 3129 if (riscv_opts.arch_attr || explicit_arch_attr) 3130 /* Re-write arch attribute to normalize the arch string. */ 3131 riscv_write_out_arch_attr (); 3132 } 3133 3134 /* Called after all assembly has been done. */ 3135 3136 void 3137 riscv_md_end (void) 3138 { 3139 riscv_set_public_attributes (); 3140 } 3141 3142 /* Given a symbolic attribute NAME, return the proper integer value. 3143 Returns -1 if the attribute is not known. */ 3144 3145 int 3146 riscv_convert_symbolic_attribute (const char *name) 3147 { 3148 static const struct 3149 { 3150 const char * name; 3151 const int tag; 3152 } 3153 attribute_table[] = 3154 { 3155 /* When you modify this table you should 3156 also modify the list in doc/c-riscv.texi. */ 3157 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag} 3158 T(arch), 3159 T(priv_spec), 3160 T(priv_spec_minor), 3161 T(priv_spec_revision), 3162 T(unaligned_access), 3163 T(stack_align), 3164 #undef T 3165 }; 3166 3167 unsigned int i; 3168 3169 if (name == NULL) 3170 return -1; 3171 3172 for (i = 0; i < ARRAY_SIZE (attribute_table); i++) 3173 if (strcmp (name, attribute_table[i].name) == 0) 3174 return attribute_table[i].tag; 3175 3176 return -1; 3177 } 3178 3179 /* Parse a .attribute directive. */ 3180 3181 static void 3182 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) 3183 { 3184 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); 3185 3186 if (tag == Tag_RISCV_arch) 3187 { 3188 unsigned old_xlen = xlen; 3189 3190 explicit_arch_attr = TRUE; 3191 obj_attribute *attr; 3192 attr = elf_known_obj_attributes_proc (stdoutput); 3193 if (!start_assemble) 3194 riscv_set_arch (attr[Tag_RISCV_arch].s); 3195 else 3196 as_fatal (_(".attribute arch must set before any instructions")); 3197 3198 if (old_xlen != xlen) 3199 { 3200 /* We must re-init bfd again if xlen is changed. */ 3201 unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; 3202 bfd_find_target (riscv_target_format (), stdoutput); 3203 3204 if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) 3205 as_warn (_("Could not set architecture and machine")); 3206 } 3207 } 3208 } 3209 3210 /* Pseudo-op table. */ 3211 3212 static const pseudo_typeS riscv_pseudo_table[] = 3213 { 3214 /* RISC-V-specific pseudo-ops. */ 3215 {"option", s_riscv_option, 0}, 3216 {"half", cons, 2}, 3217 {"word", cons, 4}, 3218 {"dword", cons, 8}, 3219 {"dtprelword", s_dtprel, 4}, 3220 {"dtpreldword", s_dtprel, 8}, 3221 {"bss", s_bss, 0}, 3222 {"uleb128", s_riscv_leb128, 0}, 3223 {"sleb128", s_riscv_leb128, 1}, 3224 {"insn", s_riscv_insn, 0}, 3225 {"attribute", s_riscv_attribute, 0}, 3226 3227 { NULL, NULL, 0 }, 3228 }; 3229 3230 void 3231 riscv_pop_insert (void) 3232 { 3233 extern void pop_insert (const pseudo_typeS *); 3234 3235 pop_insert (riscv_pseudo_table); 3236 } 3237