1 /* tc-i386.c -- Assemble code for the Intel 80386 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 4 2012 5 Free Software Foundation, Inc. 6 7 This file is part of GAS, the GNU Assembler. 8 9 GAS is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GAS; see the file COPYING. If not, write to the Free 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 22 02110-1301, USA. */ 23 24 /* Intel 80386 machine specific gas. 25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu). 26 x86_64 support by Jan Hubicka (jh@suse.cz) 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz) 28 Bugs & suggestions are completely welcome. This is free software. 29 Please help us make it better. */ 30 31 #include "as.h" 32 #include "safe-ctype.h" 33 #include "subsegs.h" 34 #include "dwarf2dbg.h" 35 #include "dw2gencfi.h" 36 #include "elf/x86-64.h" 37 #include "opcodes/i386-init.h" 38 39 #ifndef REGISTER_WARNINGS 40 #define REGISTER_WARNINGS 1 41 #endif 42 43 #ifndef INFER_ADDR_PREFIX 44 #define INFER_ADDR_PREFIX 1 45 #endif 46 47 #ifndef DEFAULT_ARCH 48 #define DEFAULT_ARCH "i386" 49 #endif 50 51 #ifndef INLINE 52 #if __GNUC__ >= 2 53 #define INLINE __inline__ 54 #else 55 #define INLINE 56 #endif 57 #endif 58 59 /* Prefixes will be emitted in the order defined below. 60 WAIT_PREFIX must be the first prefix since FWAIT is really is an 61 instruction, and so must come before any prefixes. 62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ 64 #define WAIT_PREFIX 0 65 #define SEG_PREFIX 1 66 #define ADDR_PREFIX 2 67 #define DATA_PREFIX 3 68 #define REP_PREFIX 4 69 #define HLE_PREFIX REP_PREFIX 70 #define LOCK_PREFIX 5 71 #define REX_PREFIX 6 /* must come last. */ 72 #define MAX_PREFIXES 7 /* max prefixes per opcode */ 73 74 /* we define the syntax here (modulo base,index,scale syntax) */ 75 #define REGISTER_PREFIX '%' 76 #define IMMEDIATE_PREFIX '$' 77 #define ABSOLUTE_PREFIX '*' 78 79 /* these are the instruction mnemonic suffixes in AT&T syntax or 80 memory operand size in Intel syntax. */ 81 #define WORD_MNEM_SUFFIX 'w' 82 #define BYTE_MNEM_SUFFIX 'b' 83 #define SHORT_MNEM_SUFFIX 's' 84 #define LONG_MNEM_SUFFIX 'l' 85 #define QWORD_MNEM_SUFFIX 'q' 86 #define XMMWORD_MNEM_SUFFIX 'x' 87 #define YMMWORD_MNEM_SUFFIX 'y' 88 /* Intel Syntax. Use a non-ascii letter since since it never appears 89 in instructions. */ 90 #define LONG_DOUBLE_MNEM_SUFFIX '\1' 91 92 #define END_OF_INSN '\0' 93 94 /* 95 'templates' is for grouping together 'template' structures for opcodes 96 of the same name. This is only used for storing the insns in the grand 97 ole hash table of insns. 98 The templates themselves start at START and range up to (but not including) 99 END. 100 */ 101 typedef struct 102 { 103 const insn_template *start; 104 const insn_template *end; 105 } 106 templates; 107 108 /* 386 operand encoding bytes: see 386 book for details of this. */ 109 typedef struct 110 { 111 unsigned int regmem; /* codes register or memory operand */ 112 unsigned int reg; /* codes register operand (or extended opcode) */ 113 unsigned int mode; /* how to interpret regmem & reg */ 114 } 115 modrm_byte; 116 117 /* x86-64 extension prefix. */ 118 typedef int rex_byte; 119 120 /* 386 opcode byte to code indirect addressing. */ 121 typedef struct 122 { 123 unsigned base; 124 unsigned index; 125 unsigned scale; 126 } 127 sib_byte; 128 129 /* x86 arch names, types and features */ 130 typedef struct 131 { 132 const char *name; /* arch name */ 133 unsigned int len; /* arch string length */ 134 enum processor_type type; /* arch type */ 135 i386_cpu_flags flags; /* cpu feature flags */ 136 unsigned int skip; /* show_arch should skip this. */ 137 unsigned int negated; /* turn off indicated flags. */ 138 } 139 arch_entry; 140 141 static void update_code_flag (int, int); 142 static void set_code_flag (int); 143 static void set_16bit_gcc_code_flag (int); 144 static void set_intel_syntax (int); 145 static void set_intel_mnemonic (int); 146 static void set_allow_index_reg (int); 147 static void set_sse_check (int); 148 static void set_cpu_arch (int); 149 #ifdef TE_PE 150 static void pe_directive_secrel (int); 151 #endif 152 static void signed_cons (int); 153 static char *output_invalid (int c); 154 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, 155 const char *); 156 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, 157 const char *); 158 static int i386_att_operand (char *); 159 static int i386_intel_operand (char *, int); 160 static int i386_intel_simplify (expressionS *); 161 static int i386_intel_parse_name (const char *, expressionS *); 162 static const reg_entry *parse_register (char *, char **); 163 static char *parse_insn (char *, char *); 164 static char *parse_operands (char *, const char *); 165 static void swap_operands (void); 166 static void swap_2_operands (int, int); 167 static void optimize_imm (void); 168 static void optimize_disp (void); 169 static const insn_template *match_template (void); 170 static int check_string (void); 171 static int process_suffix (void); 172 static int check_byte_reg (void); 173 static int check_long_reg (void); 174 static int check_qword_reg (void); 175 static int check_word_reg (void); 176 static int finalize_imm (void); 177 static int process_operands (void); 178 static const seg_entry *build_modrm_byte (void); 179 static void output_insn (void); 180 static void output_imm (fragS *, offsetT); 181 static void output_disp (fragS *, offsetT); 182 #ifndef I386COFF 183 static void s_bss (int); 184 #endif 185 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 186 static void handle_large_common (int small ATTRIBUTE_UNUSED); 187 #endif 188 189 static const char *default_arch = DEFAULT_ARCH; 190 191 /* VEX prefix. */ 192 typedef struct 193 { 194 /* VEX prefix is either 2 byte or 3 byte. */ 195 unsigned char bytes[3]; 196 unsigned int length; 197 /* Destination or source register specifier. */ 198 const reg_entry *register_specifier; 199 } vex_prefix; 200 201 /* 'md_assemble ()' gathers together information and puts it into a 202 i386_insn. */ 203 204 union i386_op 205 { 206 expressionS *disps; 207 expressionS *imms; 208 const reg_entry *regs; 209 }; 210 211 enum i386_error 212 { 213 operand_size_mismatch, 214 operand_type_mismatch, 215 register_type_mismatch, 216 number_of_operands_mismatch, 217 invalid_instruction_suffix, 218 bad_imm4, 219 old_gcc_only, 220 unsupported_with_intel_mnemonic, 221 unsupported_syntax, 222 unsupported, 223 invalid_vsib_address, 224 unsupported_vector_index_register 225 }; 226 227 struct _i386_insn 228 { 229 /* TM holds the template for the insn were currently assembling. */ 230 insn_template tm; 231 232 /* SUFFIX holds the instruction size suffix for byte, word, dword 233 or qword, if given. */ 234 char suffix; 235 236 /* OPERANDS gives the number of given operands. */ 237 unsigned int operands; 238 239 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 240 of given register, displacement, memory operands and immediate 241 operands. */ 242 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 243 244 /* TYPES [i] is the type (see above #defines) which tells us how to 245 use OP[i] for the corresponding operand. */ 246 i386_operand_type types[MAX_OPERANDS]; 247 248 /* Displacement expression, immediate expression, or register for each 249 operand. */ 250 union i386_op op[MAX_OPERANDS]; 251 252 /* Flags for operands. */ 253 unsigned int flags[MAX_OPERANDS]; 254 #define Operand_PCrel 1 255 256 /* Relocation type for operand */ 257 enum bfd_reloc_code_real reloc[MAX_OPERANDS]; 258 259 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 260 the base index byte below. */ 261 const reg_entry *base_reg; 262 const reg_entry *index_reg; 263 unsigned int log2_scale_factor; 264 265 /* SEG gives the seg_entries of this insn. They are zero unless 266 explicit segment overrides are given. */ 267 const seg_entry *seg[2]; 268 269 /* PREFIX holds all the given prefix opcodes (usually null). 270 PREFIXES is the number of prefix opcodes. */ 271 unsigned int prefixes; 272 unsigned char prefix[MAX_PREFIXES]; 273 274 /* RM and SIB are the modrm byte and the sib byte where the 275 addressing modes of this insn are encoded. */ 276 modrm_byte rm; 277 rex_byte rex; 278 sib_byte sib; 279 vex_prefix vex; 280 281 /* Swap operand in encoding. */ 282 unsigned int swap_operand; 283 284 /* Prefer 8bit or 32bit displacement in encoding. */ 285 enum 286 { 287 disp_encoding_default = 0, 288 disp_encoding_8bit, 289 disp_encoding_32bit 290 } disp_encoding; 291 292 /* Have HLE prefix. */ 293 unsigned int have_hle; 294 295 /* Error message. */ 296 enum i386_error error; 297 }; 298 299 typedef struct _i386_insn i386_insn; 300 301 /* List of chars besides those in app.c:symbol_chars that can start an 302 operand. Used to prevent the scrubber eating vital white-space. */ 303 const char extra_symbol_chars[] = "*%-([" 304 #ifdef LEX_AT 305 "@" 306 #endif 307 #ifdef LEX_QM 308 "?" 309 #endif 310 ; 311 312 #if (defined (TE_I386AIX) \ 313 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ 314 && !defined (TE_GNU) \ 315 && !defined (TE_LINUX) \ 316 && !defined (TE_NACL) \ 317 && !defined (TE_NETWARE) \ 318 && !defined (TE_FreeBSD) \ 319 && !defined (TE_DragonFly) \ 320 && !defined (TE_NetBSD))) 321 /* This array holds the chars that always start a comment. If the 322 pre-processor is disabled, these aren't very useful. The option 323 --divide will remove '/' from this list. */ 324 const char *i386_comment_chars = "#/"; 325 #define SVR4_COMMENT_CHARS 1 326 #define PREFIX_SEPARATOR '\\' 327 328 #else 329 const char *i386_comment_chars = "#"; 330 #define PREFIX_SEPARATOR '/' 331 #endif 332 333 /* This array holds the chars that only start a comment at the beginning of 334 a line. If the line seems to have the form '# 123 filename' 335 .line and .file directives will appear in the pre-processed output. 336 Note that input_file.c hand checks for '#' at the beginning of the 337 first line of the input file. This is because the compiler outputs 338 #NO_APP at the beginning of its output. 339 Also note that comments started like this one will always work if 340 '/' isn't otherwise defined. */ 341 const char line_comment_chars[] = "#/"; 342 343 const char line_separator_chars[] = ";"; 344 345 /* Chars that can be used to separate mant from exp in floating point 346 nums. */ 347 const char EXP_CHARS[] = "eE"; 348 349 /* Chars that mean this number is a floating point constant 350 As in 0f12.456 351 or 0d1.2345e12. */ 352 const char FLT_CHARS[] = "fFdDxX"; 353 354 /* Tables for lexical analysis. */ 355 static char mnemonic_chars[256]; 356 static char register_chars[256]; 357 static char operand_chars[256]; 358 static char identifier_chars[256]; 359 static char digit_chars[256]; 360 361 /* Lexical macros. */ 362 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 363 #define is_operand_char(x) (operand_chars[(unsigned char) x]) 364 #define is_register_char(x) (register_chars[(unsigned char) x]) 365 #define is_space_char(x) ((x) == ' ') 366 #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 367 #define is_digit_char(x) (digit_chars[(unsigned char) x]) 368 369 /* All non-digit non-letter characters that may occur in an operand. */ 370 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 371 372 /* md_assemble() always leaves the strings it's passed unaltered. To 373 effect this we maintain a stack of saved characters that we've smashed 374 with '\0's (indicating end of strings for various sub-fields of the 375 assembler instruction). */ 376 static char save_stack[32]; 377 static char *save_stack_p; 378 #define END_STRING_AND_SAVE(s) \ 379 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 380 #define RESTORE_END_STRING(s) \ 381 do { *(s) = *--save_stack_p; } while (0) 382 383 /* The instruction we're assembling. */ 384 static i386_insn i; 385 386 /* Possible templates for current insn. */ 387 static const templates *current_templates; 388 389 /* Per instruction expressionS buffers: max displacements & immediates. */ 390 static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; 391 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; 392 393 /* Current operand we are working on. */ 394 static int this_operand = -1; 395 396 /* We support four different modes. FLAG_CODE variable is used to distinguish 397 these. */ 398 399 enum flag_code { 400 CODE_32BIT, 401 CODE_16BIT, 402 CODE_64BIT }; 403 404 static enum flag_code flag_code; 405 static unsigned int object_64bit; 406 static unsigned int disallow_64bit_reloc; 407 static int use_rela_relocations = 0; 408 409 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 410 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 411 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 412 413 /* The ELF ABI to use. */ 414 enum x86_elf_abi 415 { 416 I386_ABI, 417 X86_64_ABI, 418 X86_64_X32_ABI 419 }; 420 421 static enum x86_elf_abi x86_elf_abi = I386_ABI; 422 #endif 423 424 /* The names used to print error messages. */ 425 static const char *flag_code_names[] = 426 { 427 "32", 428 "16", 429 "64" 430 }; 431 432 /* 1 for intel syntax, 433 0 if att syntax. */ 434 static int intel_syntax = 0; 435 436 /* 1 for intel mnemonic, 437 0 if att mnemonic. */ 438 static int intel_mnemonic = !SYSV386_COMPAT; 439 440 /* 1 if support old (<= 2.8.1) versions of gcc. */ 441 static int old_gcc = OLDGCC_COMPAT; 442 443 /* 1 if pseudo registers are permitted. */ 444 static int allow_pseudo_reg = 0; 445 446 /* 1 if register prefix % not required. */ 447 static int allow_naked_reg = 0; 448 449 /* 1 if pseudo index register, eiz/riz, is allowed . */ 450 static int allow_index_reg = 0; 451 452 static enum 453 { 454 sse_check_none = 0, 455 sse_check_warning, 456 sse_check_error 457 } 458 sse_check; 459 460 /* Register prefix used for error message. */ 461 static const char *register_prefix = "%"; 462 463 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, 464 leave, push, and pop instructions so that gcc has the same stack 465 frame as in 32 bit mode. */ 466 static char stackop_size = '\0'; 467 468 /* Non-zero to optimize code alignment. */ 469 int optimize_align_code = 1; 470 471 /* Non-zero to quieten some warnings. */ 472 static int quiet_warnings = 0; 473 474 /* CPU name. */ 475 static const char *cpu_arch_name = NULL; 476 static char *cpu_sub_arch_name = NULL; 477 478 /* CPU feature flags. */ 479 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; 480 481 /* If we have selected a cpu we are generating instructions for. */ 482 static int cpu_arch_tune_set = 0; 483 484 /* Cpu we are generating instructions for. */ 485 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; 486 487 /* CPU feature flags of cpu we are generating instructions for. */ 488 static i386_cpu_flags cpu_arch_tune_flags; 489 490 /* CPU instruction set architecture used. */ 491 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; 492 493 /* CPU feature flags of instruction set architecture used. */ 494 i386_cpu_flags cpu_arch_isa_flags; 495 496 /* If set, conditional jumps are not automatically promoted to handle 497 larger than a byte offset. */ 498 static unsigned int no_cond_jump_promotion = 0; 499 500 /* Encode SSE instructions with VEX prefix. */ 501 static unsigned int sse2avx; 502 503 /* Encode scalar AVX instructions with specific vector length. */ 504 static enum 505 { 506 vex128 = 0, 507 vex256 508 } avxscalar; 509 510 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ 511 static symbolS *GOT_symbol; 512 513 /* The dwarf2 return column, adjusted for 32 or 64 bit. */ 514 unsigned int x86_dwarf2_return_column; 515 516 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 517 int x86_cie_data_alignment; 518 519 /* Interface to relax_segment. 520 There are 3 major relax states for 386 jump insns because the 521 different types of jumps add different sizes to frags when we're 522 figuring out what sort of jump to choose to reach a given label. */ 523 524 /* Types. */ 525 #define UNCOND_JUMP 0 526 #define COND_JUMP 1 527 #define COND_JUMP86 2 528 529 /* Sizes. */ 530 #define CODE16 1 531 #define SMALL 0 532 #define SMALL16 (SMALL | CODE16) 533 #define BIG 2 534 #define BIG16 (BIG | CODE16) 535 536 #ifndef INLINE 537 #ifdef __GNUC__ 538 #define INLINE __inline__ 539 #else 540 #define INLINE 541 #endif 542 #endif 543 544 #define ENCODE_RELAX_STATE(type, size) \ 545 ((relax_substateT) (((type) << 2) | (size))) 546 #define TYPE_FROM_RELAX_STATE(s) \ 547 ((s) >> 2) 548 #define DISP_SIZE_FROM_RELAX_STATE(s) \ 549 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) 550 551 /* This table is used by relax_frag to promote short jumps to long 552 ones where necessary. SMALL (short) jumps may be promoted to BIG 553 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 554 don't allow a short jump in a 32 bit code segment to be promoted to 555 a 16 bit offset jump because it's slower (requires data size 556 prefix), and doesn't work, unless the destination is in the bottom 557 64k of the code segment (The top 16 bits of eip are zeroed). */ 558 559 const relax_typeS md_relax_table[] = 560 { 561 /* The fields are: 562 1) most positive reach of this state, 563 2) most negative reach of this state, 564 3) how many bytes this mode will have in the variable part of the frag 565 4) which index into the table to try if we can't fit into this one. */ 566 567 /* UNCOND_JUMP states. */ 568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 570 /* dword jmp adds 4 bytes to frag: 571 0 extra opcode bytes, 4 displacement bytes. */ 572 {0, 0, 4, 0}, 573 /* word jmp adds 2 byte2 to frag: 574 0 extra opcode bytes, 2 displacement bytes. */ 575 {0, 0, 2, 0}, 576 577 /* COND_JUMP states. */ 578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 580 /* dword conditionals adds 5 bytes to frag: 581 1 extra opcode byte, 4 displacement bytes. */ 582 {0, 0, 5, 0}, 583 /* word conditionals add 3 bytes to frag: 584 1 extra opcode byte, 2 displacement bytes. */ 585 {0, 0, 3, 0}, 586 587 /* COND_JUMP86 states. */ 588 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, 589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, 590 /* dword conditionals adds 5 bytes to frag: 591 1 extra opcode byte, 4 displacement bytes. */ 592 {0, 0, 5, 0}, 593 /* word conditionals add 4 bytes to frag: 594 1 displacement byte and a 3 byte long branch insn. */ 595 {0, 0, 4, 0} 596 }; 597 598 static const arch_entry cpu_arch[] = 599 { 600 /* Do not replace the first two entries - i386_target_format() 601 relies on them being there in this order. */ 602 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, 603 CPU_GENERIC32_FLAGS, 0, 0 }, 604 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, 605 CPU_GENERIC64_FLAGS, 0, 0 }, 606 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, 607 CPU_NONE_FLAGS, 0, 0 }, 608 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, 609 CPU_I186_FLAGS, 0, 0 }, 610 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, 611 CPU_I286_FLAGS, 0, 0 }, 612 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, 613 CPU_I386_FLAGS, 0, 0 }, 614 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, 615 CPU_I486_FLAGS, 0, 0 }, 616 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, 617 CPU_I586_FLAGS, 0, 0 }, 618 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, 619 CPU_I686_FLAGS, 0, 0 }, 620 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, 621 CPU_I586_FLAGS, 0, 0 }, 622 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, 623 CPU_PENTIUMPRO_FLAGS, 0, 0 }, 624 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, 625 CPU_P2_FLAGS, 0, 0 }, 626 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, 627 CPU_P3_FLAGS, 0, 0 }, 628 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, 629 CPU_P4_FLAGS, 0, 0 }, 630 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, 631 CPU_CORE_FLAGS, 0, 0 }, 632 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, 633 CPU_NOCONA_FLAGS, 0, 0 }, 634 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, 635 CPU_CORE_FLAGS, 1, 0 }, 636 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, 637 CPU_CORE_FLAGS, 0, 0 }, 638 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, 639 CPU_CORE2_FLAGS, 1, 0 }, 640 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, 641 CPU_CORE2_FLAGS, 0, 0 }, 642 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, 643 CPU_COREI7_FLAGS, 0, 0 }, 644 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, 645 CPU_L1OM_FLAGS, 0, 0 }, 646 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, 647 CPU_K1OM_FLAGS, 0, 0 }, 648 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, 649 CPU_K6_FLAGS, 0, 0 }, 650 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, 651 CPU_K6_2_FLAGS, 0, 0 }, 652 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, 653 CPU_ATHLON_FLAGS, 0, 0 }, 654 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, 655 CPU_K8_FLAGS, 1, 0 }, 656 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, 657 CPU_K8_FLAGS, 0, 0 }, 658 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, 659 CPU_K8_FLAGS, 0, 0 }, 660 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, 661 CPU_AMDFAM10_FLAGS, 0, 0 }, 662 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, 663 CPU_BDVER1_FLAGS, 0, 0 }, 664 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, 665 CPU_BDVER2_FLAGS, 0, 0 }, 666 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, 667 CPU_BDVER3_FLAGS, 0, 0 }, 668 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, 669 CPU_BTVER1_FLAGS, 0, 0 }, 670 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, 671 CPU_BTVER2_FLAGS, 0, 0 }, 672 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, 673 CPU_8087_FLAGS, 0, 0 }, 674 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, 675 CPU_287_FLAGS, 0, 0 }, 676 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, 677 CPU_387_FLAGS, 0, 0 }, 678 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, 679 CPU_ANY87_FLAGS, 0, 1 }, 680 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, 681 CPU_MMX_FLAGS, 0, 0 }, 682 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, 683 CPU_3DNOWA_FLAGS, 0, 1 }, 684 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, 685 CPU_SSE_FLAGS, 0, 0 }, 686 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, 687 CPU_SSE2_FLAGS, 0, 0 }, 688 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, 689 CPU_SSE3_FLAGS, 0, 0 }, 690 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, 691 CPU_SSSE3_FLAGS, 0, 0 }, 692 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, 693 CPU_SSE4_1_FLAGS, 0, 0 }, 694 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, 695 CPU_SSE4_2_FLAGS, 0, 0 }, 696 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, 697 CPU_SSE4_2_FLAGS, 0, 0 }, 698 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, 699 CPU_ANY_SSE_FLAGS, 0, 1 }, 700 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, 701 CPU_AVX_FLAGS, 0, 0 }, 702 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, 703 CPU_AVX2_FLAGS, 0, 0 }, 704 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, 705 CPU_ANY_AVX_FLAGS, 0, 1 }, 706 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, 707 CPU_VMX_FLAGS, 0, 0 }, 708 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, 709 CPU_VMFUNC_FLAGS, 0, 0 }, 710 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, 711 CPU_SMX_FLAGS, 0, 0 }, 712 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, 713 CPU_XSAVE_FLAGS, 0, 0 }, 714 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, 715 CPU_XSAVEOPT_FLAGS, 0, 0 }, 716 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, 717 CPU_AES_FLAGS, 0, 0 }, 718 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, 719 CPU_PCLMUL_FLAGS, 0, 0 }, 720 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, 721 CPU_PCLMUL_FLAGS, 1, 0 }, 722 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, 723 CPU_FSGSBASE_FLAGS, 0, 0 }, 724 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, 725 CPU_RDRND_FLAGS, 0, 0 }, 726 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, 727 CPU_F16C_FLAGS, 0, 0 }, 728 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, 729 CPU_BMI2_FLAGS, 0, 0 }, 730 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, 731 CPU_FMA_FLAGS, 0, 0 }, 732 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, 733 CPU_FMA4_FLAGS, 0, 0 }, 734 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, 735 CPU_XOP_FLAGS, 0, 0 }, 736 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, 737 CPU_LWP_FLAGS, 0, 0 }, 738 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, 739 CPU_MOVBE_FLAGS, 0, 0 }, 740 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, 741 CPU_EPT_FLAGS, 0, 0 }, 742 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, 743 CPU_LZCNT_FLAGS, 0, 0 }, 744 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, 745 CPU_HLE_FLAGS, 0, 0 }, 746 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, 747 CPU_RTM_FLAGS, 0, 0 }, 748 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, 749 CPU_INVPCID_FLAGS, 0, 0 }, 750 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, 751 CPU_CLFLUSH_FLAGS, 0, 0 }, 752 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, 753 CPU_NOP_FLAGS, 0, 0 }, 754 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, 755 CPU_SYSCALL_FLAGS, 0, 0 }, 756 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, 757 CPU_RDTSCP_FLAGS, 0, 0 }, 758 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, 759 CPU_3DNOW_FLAGS, 0, 0 }, 760 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, 761 CPU_3DNOWA_FLAGS, 0, 0 }, 762 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, 763 CPU_PADLOCK_FLAGS, 0, 0 }, 764 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, 765 CPU_SVME_FLAGS, 1, 0 }, 766 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, 767 CPU_SVME_FLAGS, 0, 0 }, 768 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, 769 CPU_SSE4A_FLAGS, 0, 0 }, 770 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, 771 CPU_ABM_FLAGS, 0, 0 }, 772 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, 773 CPU_BMI_FLAGS, 0, 0 }, 774 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, 775 CPU_TBM_FLAGS, 0, 0 }, 776 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, 777 CPU_ADX_FLAGS, 0, 0 }, 778 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, 779 CPU_RDSEED_FLAGS, 0, 0 }, 780 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, 781 CPU_PRFCHW_FLAGS, 0, 0 }, 782 }; 783 784 #ifdef I386COFF 785 /* Like s_lcomm_internal in gas/read.c but the alignment string 786 is allowed to be optional. */ 787 788 static symbolS * 789 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) 790 { 791 addressT align = 0; 792 793 SKIP_WHITESPACE (); 794 795 if (needs_align 796 && *input_line_pointer == ',') 797 { 798 align = parse_align (needs_align - 1); 799 800 if (align == (addressT) -1) 801 return NULL; 802 } 803 else 804 { 805 if (size >= 8) 806 align = 3; 807 else if (size >= 4) 808 align = 2; 809 else if (size >= 2) 810 align = 1; 811 else 812 align = 0; 813 } 814 815 bss_alloc (symbolP, size, align); 816 return symbolP; 817 } 818 819 static void 820 pe_lcomm (int needs_align) 821 { 822 s_comm_internal (needs_align * 2, pe_lcomm_internal); 823 } 824 #endif 825 826 const pseudo_typeS md_pseudo_table[] = 827 { 828 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 829 {"align", s_align_bytes, 0}, 830 #else 831 {"align", s_align_ptwo, 0}, 832 #endif 833 {"arch", set_cpu_arch, 0}, 834 #ifndef I386COFF 835 {"bss", s_bss, 0}, 836 #else 837 {"lcomm", pe_lcomm, 1}, 838 #endif 839 {"ffloat", float_cons, 'f'}, 840 {"dfloat", float_cons, 'd'}, 841 {"tfloat", float_cons, 'x'}, 842 {"value", cons, 2}, 843 {"slong", signed_cons, 4}, 844 {"noopt", s_ignore, 0}, 845 {"optim", s_ignore, 0}, 846 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, 847 {"code16", set_code_flag, CODE_16BIT}, 848 {"code32", set_code_flag, CODE_32BIT}, 849 {"code64", set_code_flag, CODE_64BIT}, 850 {"intel_syntax", set_intel_syntax, 1}, 851 {"att_syntax", set_intel_syntax, 0}, 852 {"intel_mnemonic", set_intel_mnemonic, 1}, 853 {"att_mnemonic", set_intel_mnemonic, 0}, 854 {"allow_index_reg", set_allow_index_reg, 1}, 855 {"disallow_index_reg", set_allow_index_reg, 0}, 856 {"sse_check", set_sse_check, 0}, 857 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 858 {"largecomm", handle_large_common, 0}, 859 #else 860 {"file", (void (*) (int)) dwarf2_directive_file, 0}, 861 {"loc", dwarf2_directive_loc, 0}, 862 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, 863 #endif 864 #ifdef TE_PE 865 {"secrel32", pe_directive_secrel, 0}, 866 #endif 867 {0, 0, 0} 868 }; 869 870 /* For interface with expression (). */ 871 extern char *input_line_pointer; 872 873 /* Hash table for instruction mnemonic lookup. */ 874 static struct hash_control *op_hash; 875 876 /* Hash table for register lookup. */ 877 static struct hash_control *reg_hash; 878 879 void 880 i386_align_code (fragS *fragP, int count) 881 { 882 /* Various efficient no-op patterns for aligning code labels. 883 Note: Don't try to assemble the instructions in the comments. 884 0L and 0w are not legal. */ 885 static const char f32_1[] = 886 {0x90}; /* nop */ 887 static const char f32_2[] = 888 {0x66,0x90}; /* xchg %ax,%ax */ 889 static const char f32_3[] = 890 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 891 static const char f32_4[] = 892 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 893 static const char f32_5[] = 894 {0x90, /* nop */ 895 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 896 static const char f32_6[] = 897 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 898 static const char f32_7[] = 899 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 900 static const char f32_8[] = 901 {0x90, /* nop */ 902 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 903 static const char f32_9[] = 904 {0x89,0xf6, /* movl %esi,%esi */ 905 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 906 static const char f32_10[] = 907 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 908 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 909 static const char f32_11[] = 910 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 911 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 912 static const char f32_12[] = 913 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 914 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 915 static const char f32_13[] = 916 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 917 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 918 static const char f32_14[] = 919 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 920 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 921 static const char f16_3[] = 922 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 923 static const char f16_4[] = 924 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 925 static const char f16_5[] = 926 {0x90, /* nop */ 927 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 928 static const char f16_6[] = 929 {0x89,0xf6, /* mov %si,%si */ 930 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 931 static const char f16_7[] = 932 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 933 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 934 static const char f16_8[] = 935 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 936 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 937 static const char jump_31[] = 938 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ 939 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 940 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 941 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 942 static const char *const f32_patt[] = { 943 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 944 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 945 }; 946 static const char *const f16_patt[] = { 947 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 948 }; 949 /* nopl (%[re]ax) */ 950 static const char alt_3[] = 951 {0x0f,0x1f,0x00}; 952 /* nopl 0(%[re]ax) */ 953 static const char alt_4[] = 954 {0x0f,0x1f,0x40,0x00}; 955 /* nopl 0(%[re]ax,%[re]ax,1) */ 956 static const char alt_5[] = 957 {0x0f,0x1f,0x44,0x00,0x00}; 958 /* nopw 0(%[re]ax,%[re]ax,1) */ 959 static const char alt_6[] = 960 {0x66,0x0f,0x1f,0x44,0x00,0x00}; 961 /* nopl 0L(%[re]ax) */ 962 static const char alt_7[] = 963 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 964 /* nopl 0L(%[re]ax,%[re]ax,1) */ 965 static const char alt_8[] = 966 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 967 /* nopw 0L(%[re]ax,%[re]ax,1) */ 968 static const char alt_9[] = 969 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 970 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ 971 static const char alt_10[] = 972 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 973 /* data16 974 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 975 static const char alt_long_11[] = 976 {0x66, 977 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 978 /* data16 979 data16 980 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 981 static const char alt_long_12[] = 982 {0x66, 983 0x66, 984 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 985 /* data16 986 data16 987 data16 988 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 989 static const char alt_long_13[] = 990 {0x66, 991 0x66, 992 0x66, 993 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 994 /* data16 995 data16 996 data16 997 data16 998 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 999 static const char alt_long_14[] = 1000 {0x66, 1001 0x66, 1002 0x66, 1003 0x66, 1004 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1005 /* data16 1006 data16 1007 data16 1008 data16 1009 data16 1010 nopw %cs:0L(%[re]ax,%[re]ax,1) */ 1011 static const char alt_long_15[] = 1012 {0x66, 1013 0x66, 1014 0x66, 1015 0x66, 1016 0x66, 1017 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1018 /* nopl 0(%[re]ax,%[re]ax,1) 1019 nopw 0(%[re]ax,%[re]ax,1) */ 1020 static const char alt_short_11[] = 1021 {0x0f,0x1f,0x44,0x00,0x00, 1022 0x66,0x0f,0x1f,0x44,0x00,0x00}; 1023 /* nopw 0(%[re]ax,%[re]ax,1) 1024 nopw 0(%[re]ax,%[re]ax,1) */ 1025 static const char alt_short_12[] = 1026 {0x66,0x0f,0x1f,0x44,0x00,0x00, 1027 0x66,0x0f,0x1f,0x44,0x00,0x00}; 1028 /* nopw 0(%[re]ax,%[re]ax,1) 1029 nopl 0L(%[re]ax) */ 1030 static const char alt_short_13[] = 1031 {0x66,0x0f,0x1f,0x44,0x00,0x00, 1032 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 1033 /* nopl 0L(%[re]ax) 1034 nopl 0L(%[re]ax) */ 1035 static const char alt_short_14[] = 1036 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, 1037 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; 1038 /* nopl 0L(%[re]ax) 1039 nopl 0L(%[re]ax,%[re]ax,1) */ 1040 static const char alt_short_15[] = 1041 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, 1042 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; 1043 static const char *const alt_short_patt[] = { 1044 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, 1045 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, 1046 alt_short_14, alt_short_15 1047 }; 1048 static const char *const alt_long_patt[] = { 1049 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, 1050 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, 1051 alt_long_14, alt_long_15 1052 }; 1053 1054 /* Only align for at least a positive non-zero boundary. */ 1055 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) 1056 return; 1057 1058 /* We need to decide which NOP sequence to use for 32bit and 1059 64bit. When -mtune= is used: 1060 1061 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and 1062 PROCESSOR_GENERIC32, f32_patt will be used. 1063 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, 1064 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and 1065 PROCESSOR_GENERIC64, alt_long_patt will be used. 1066 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and 1067 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt 1068 will be used. 1069 1070 When -mtune= isn't used, alt_long_patt will be used if 1071 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will 1072 be used. 1073 1074 When -march= or .arch is used, we can't use anything beyond 1075 cpu_arch_isa_flags. */ 1076 1077 if (flag_code == CODE_16BIT) 1078 { 1079 if (count > 8) 1080 { 1081 memcpy (fragP->fr_literal + fragP->fr_fix, 1082 jump_31, count); 1083 /* Adjust jump offset. */ 1084 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 1085 } 1086 else 1087 memcpy (fragP->fr_literal + fragP->fr_fix, 1088 f16_patt[count - 1], count); 1089 } 1090 else 1091 { 1092 const char *const *patt = NULL; 1093 1094 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) 1095 { 1096 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ 1097 switch (cpu_arch_tune) 1098 { 1099 case PROCESSOR_UNKNOWN: 1100 /* We use cpu_arch_isa_flags to check if we SHOULD 1101 optimize with nops. */ 1102 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1103 patt = alt_long_patt; 1104 else 1105 patt = f32_patt; 1106 break; 1107 case PROCESSOR_PENTIUM4: 1108 case PROCESSOR_NOCONA: 1109 case PROCESSOR_CORE: 1110 case PROCESSOR_CORE2: 1111 case PROCESSOR_COREI7: 1112 case PROCESSOR_L1OM: 1113 case PROCESSOR_K1OM: 1114 case PROCESSOR_GENERIC64: 1115 patt = alt_long_patt; 1116 break; 1117 case PROCESSOR_K6: 1118 case PROCESSOR_ATHLON: 1119 case PROCESSOR_K8: 1120 case PROCESSOR_AMDFAM10: 1121 case PROCESSOR_BD: 1122 case PROCESSOR_BT: 1123 patt = alt_short_patt; 1124 break; 1125 case PROCESSOR_I386: 1126 case PROCESSOR_I486: 1127 case PROCESSOR_PENTIUM: 1128 case PROCESSOR_PENTIUMPRO: 1129 case PROCESSOR_GENERIC32: 1130 patt = f32_patt; 1131 break; 1132 } 1133 } 1134 else 1135 { 1136 switch (fragP->tc_frag_data.tune) 1137 { 1138 case PROCESSOR_UNKNOWN: 1139 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be 1140 PROCESSOR_UNKNOWN. */ 1141 abort (); 1142 break; 1143 1144 case PROCESSOR_I386: 1145 case PROCESSOR_I486: 1146 case PROCESSOR_PENTIUM: 1147 case PROCESSOR_K6: 1148 case PROCESSOR_ATHLON: 1149 case PROCESSOR_K8: 1150 case PROCESSOR_AMDFAM10: 1151 case PROCESSOR_BD: 1152 case PROCESSOR_BT: 1153 case PROCESSOR_GENERIC32: 1154 /* We use cpu_arch_isa_flags to check if we CAN optimize 1155 with nops. */ 1156 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1157 patt = alt_short_patt; 1158 else 1159 patt = f32_patt; 1160 break; 1161 case PROCESSOR_PENTIUMPRO: 1162 case PROCESSOR_PENTIUM4: 1163 case PROCESSOR_NOCONA: 1164 case PROCESSOR_CORE: 1165 case PROCESSOR_CORE2: 1166 case PROCESSOR_COREI7: 1167 case PROCESSOR_L1OM: 1168 case PROCESSOR_K1OM: 1169 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) 1170 patt = alt_long_patt; 1171 else 1172 patt = f32_patt; 1173 break; 1174 case PROCESSOR_GENERIC64: 1175 patt = alt_long_patt; 1176 break; 1177 } 1178 } 1179 1180 if (patt == f32_patt) 1181 { 1182 /* If the padding is less than 15 bytes, we use the normal 1183 ones. Otherwise, we use a jump instruction and adjust 1184 its offset. */ 1185 int limit; 1186 1187 /* For 64bit, the limit is 3 bytes. */ 1188 if (flag_code == CODE_64BIT 1189 && fragP->tc_frag_data.isa_flags.bitfield.cpulm) 1190 limit = 3; 1191 else 1192 limit = 15; 1193 if (count < limit) 1194 memcpy (fragP->fr_literal + fragP->fr_fix, 1195 patt[count - 1], count); 1196 else 1197 { 1198 memcpy (fragP->fr_literal + fragP->fr_fix, 1199 jump_31, count); 1200 /* Adjust jump offset. */ 1201 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 1202 } 1203 } 1204 else 1205 { 1206 /* Maximum length of an instruction is 15 byte. If the 1207 padding is greater than 15 bytes and we don't use jump, 1208 we have to break it into smaller pieces. */ 1209 int padding = count; 1210 while (padding > 15) 1211 { 1212 padding -= 15; 1213 memcpy (fragP->fr_literal + fragP->fr_fix + padding, 1214 patt [14], 15); 1215 } 1216 1217 if (padding) 1218 memcpy (fragP->fr_literal + fragP->fr_fix, 1219 patt [padding - 1], padding); 1220 } 1221 } 1222 fragP->fr_var = count; 1223 } 1224 1225 static INLINE int 1226 operand_type_all_zero (const union i386_operand_type *x) 1227 { 1228 switch (ARRAY_SIZE(x->array)) 1229 { 1230 case 3: 1231 if (x->array[2]) 1232 return 0; 1233 case 2: 1234 if (x->array[1]) 1235 return 0; 1236 case 1: 1237 return !x->array[0]; 1238 default: 1239 abort (); 1240 } 1241 } 1242 1243 static INLINE void 1244 operand_type_set (union i386_operand_type *x, unsigned int v) 1245 { 1246 switch (ARRAY_SIZE(x->array)) 1247 { 1248 case 3: 1249 x->array[2] = v; 1250 case 2: 1251 x->array[1] = v; 1252 case 1: 1253 x->array[0] = v; 1254 break; 1255 default: 1256 abort (); 1257 } 1258 } 1259 1260 static INLINE int 1261 operand_type_equal (const union i386_operand_type *x, 1262 const union i386_operand_type *y) 1263 { 1264 switch (ARRAY_SIZE(x->array)) 1265 { 1266 case 3: 1267 if (x->array[2] != y->array[2]) 1268 return 0; 1269 case 2: 1270 if (x->array[1] != y->array[1]) 1271 return 0; 1272 case 1: 1273 return x->array[0] == y->array[0]; 1274 break; 1275 default: 1276 abort (); 1277 } 1278 } 1279 1280 static INLINE int 1281 cpu_flags_all_zero (const union i386_cpu_flags *x) 1282 { 1283 switch (ARRAY_SIZE(x->array)) 1284 { 1285 case 3: 1286 if (x->array[2]) 1287 return 0; 1288 case 2: 1289 if (x->array[1]) 1290 return 0; 1291 case 1: 1292 return !x->array[0]; 1293 default: 1294 abort (); 1295 } 1296 } 1297 1298 static INLINE void 1299 cpu_flags_set (union i386_cpu_flags *x, unsigned int v) 1300 { 1301 switch (ARRAY_SIZE(x->array)) 1302 { 1303 case 3: 1304 x->array[2] = v; 1305 case 2: 1306 x->array[1] = v; 1307 case 1: 1308 x->array[0] = v; 1309 break; 1310 default: 1311 abort (); 1312 } 1313 } 1314 1315 static INLINE int 1316 cpu_flags_equal (const union i386_cpu_flags *x, 1317 const union i386_cpu_flags *y) 1318 { 1319 switch (ARRAY_SIZE(x->array)) 1320 { 1321 case 3: 1322 if (x->array[2] != y->array[2]) 1323 return 0; 1324 case 2: 1325 if (x->array[1] != y->array[1]) 1326 return 0; 1327 case 1: 1328 return x->array[0] == y->array[0]; 1329 break; 1330 default: 1331 abort (); 1332 } 1333 } 1334 1335 static INLINE int 1336 cpu_flags_check_cpu64 (i386_cpu_flags f) 1337 { 1338 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) 1339 || (flag_code != CODE_64BIT && f.bitfield.cpu64)); 1340 } 1341 1342 static INLINE i386_cpu_flags 1343 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) 1344 { 1345 switch (ARRAY_SIZE (x.array)) 1346 { 1347 case 3: 1348 x.array [2] &= y.array [2]; 1349 case 2: 1350 x.array [1] &= y.array [1]; 1351 case 1: 1352 x.array [0] &= y.array [0]; 1353 break; 1354 default: 1355 abort (); 1356 } 1357 return x; 1358 } 1359 1360 static INLINE i386_cpu_flags 1361 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) 1362 { 1363 switch (ARRAY_SIZE (x.array)) 1364 { 1365 case 3: 1366 x.array [2] |= y.array [2]; 1367 case 2: 1368 x.array [1] |= y.array [1]; 1369 case 1: 1370 x.array [0] |= y.array [0]; 1371 break; 1372 default: 1373 abort (); 1374 } 1375 return x; 1376 } 1377 1378 static INLINE i386_cpu_flags 1379 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) 1380 { 1381 switch (ARRAY_SIZE (x.array)) 1382 { 1383 case 3: 1384 x.array [2] &= ~y.array [2]; 1385 case 2: 1386 x.array [1] &= ~y.array [1]; 1387 case 1: 1388 x.array [0] &= ~y.array [0]; 1389 break; 1390 default: 1391 abort (); 1392 } 1393 return x; 1394 } 1395 1396 #define CPU_FLAGS_ARCH_MATCH 0x1 1397 #define CPU_FLAGS_64BIT_MATCH 0x2 1398 #define CPU_FLAGS_AES_MATCH 0x4 1399 #define CPU_FLAGS_PCLMUL_MATCH 0x8 1400 #define CPU_FLAGS_AVX_MATCH 0x10 1401 1402 #define CPU_FLAGS_32BIT_MATCH \ 1403 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ 1404 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) 1405 #define CPU_FLAGS_PERFECT_MATCH \ 1406 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) 1407 1408 /* Return CPU flags match bits. */ 1409 1410 static int 1411 cpu_flags_match (const insn_template *t) 1412 { 1413 i386_cpu_flags x = t->cpu_flags; 1414 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; 1415 1416 x.bitfield.cpu64 = 0; 1417 x.bitfield.cpuno64 = 0; 1418 1419 if (cpu_flags_all_zero (&x)) 1420 { 1421 /* This instruction is available on all archs. */ 1422 match |= CPU_FLAGS_32BIT_MATCH; 1423 } 1424 else 1425 { 1426 /* This instruction is available only on some archs. */ 1427 i386_cpu_flags cpu = cpu_arch_flags; 1428 1429 cpu.bitfield.cpu64 = 0; 1430 cpu.bitfield.cpuno64 = 0; 1431 cpu = cpu_flags_and (x, cpu); 1432 if (!cpu_flags_all_zero (&cpu)) 1433 { 1434 if (x.bitfield.cpuavx) 1435 { 1436 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ 1437 if (cpu.bitfield.cpuavx) 1438 { 1439 /* Check SSE2AVX. */ 1440 if (!t->opcode_modifier.sse2avx|| sse2avx) 1441 { 1442 match |= (CPU_FLAGS_ARCH_MATCH 1443 | CPU_FLAGS_AVX_MATCH); 1444 /* Check AES. */ 1445 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) 1446 match |= CPU_FLAGS_AES_MATCH; 1447 /* Check PCLMUL. */ 1448 if (!x.bitfield.cpupclmul 1449 || cpu.bitfield.cpupclmul) 1450 match |= CPU_FLAGS_PCLMUL_MATCH; 1451 } 1452 } 1453 else 1454 match |= CPU_FLAGS_ARCH_MATCH; 1455 } 1456 else 1457 match |= CPU_FLAGS_32BIT_MATCH; 1458 } 1459 } 1460 return match; 1461 } 1462 1463 static INLINE i386_operand_type 1464 operand_type_and (i386_operand_type x, i386_operand_type y) 1465 { 1466 switch (ARRAY_SIZE (x.array)) 1467 { 1468 case 3: 1469 x.array [2] &= y.array [2]; 1470 case 2: 1471 x.array [1] &= y.array [1]; 1472 case 1: 1473 x.array [0] &= y.array [0]; 1474 break; 1475 default: 1476 abort (); 1477 } 1478 return x; 1479 } 1480 1481 static INLINE i386_operand_type 1482 operand_type_or (i386_operand_type x, i386_operand_type y) 1483 { 1484 switch (ARRAY_SIZE (x.array)) 1485 { 1486 case 3: 1487 x.array [2] |= y.array [2]; 1488 case 2: 1489 x.array [1] |= y.array [1]; 1490 case 1: 1491 x.array [0] |= y.array [0]; 1492 break; 1493 default: 1494 abort (); 1495 } 1496 return x; 1497 } 1498 1499 static INLINE i386_operand_type 1500 operand_type_xor (i386_operand_type x, i386_operand_type y) 1501 { 1502 switch (ARRAY_SIZE (x.array)) 1503 { 1504 case 3: 1505 x.array [2] ^= y.array [2]; 1506 case 2: 1507 x.array [1] ^= y.array [1]; 1508 case 1: 1509 x.array [0] ^= y.array [0]; 1510 break; 1511 default: 1512 abort (); 1513 } 1514 return x; 1515 } 1516 1517 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; 1518 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; 1519 static const i386_operand_type control = OPERAND_TYPE_CONTROL; 1520 static const i386_operand_type inoutportreg 1521 = OPERAND_TYPE_INOUTPORTREG; 1522 static const i386_operand_type reg16_inoutportreg 1523 = OPERAND_TYPE_REG16_INOUTPORTREG; 1524 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; 1525 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; 1526 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; 1527 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; 1528 static const i386_operand_type anydisp 1529 = OPERAND_TYPE_ANYDISP; 1530 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; 1531 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; 1532 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; 1533 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; 1534 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; 1535 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; 1536 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; 1537 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; 1538 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; 1539 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; 1540 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; 1541 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; 1542 1543 enum operand_type 1544 { 1545 reg, 1546 imm, 1547 disp, 1548 anymem 1549 }; 1550 1551 static INLINE int 1552 operand_type_check (i386_operand_type t, enum operand_type c) 1553 { 1554 switch (c) 1555 { 1556 case reg: 1557 return (t.bitfield.reg8 1558 || t.bitfield.reg16 1559 || t.bitfield.reg32 1560 || t.bitfield.reg64); 1561 1562 case imm: 1563 return (t.bitfield.imm8 1564 || t.bitfield.imm8s 1565 || t.bitfield.imm16 1566 || t.bitfield.imm32 1567 || t.bitfield.imm32s 1568 || t.bitfield.imm64); 1569 1570 case disp: 1571 return (t.bitfield.disp8 1572 || t.bitfield.disp16 1573 || t.bitfield.disp32 1574 || t.bitfield.disp32s 1575 || t.bitfield.disp64); 1576 1577 case anymem: 1578 return (t.bitfield.disp8 1579 || t.bitfield.disp16 1580 || t.bitfield.disp32 1581 || t.bitfield.disp32s 1582 || t.bitfield.disp64 1583 || t.bitfield.baseindex); 1584 1585 default: 1586 abort (); 1587 } 1588 1589 return 0; 1590 } 1591 1592 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on 1593 operand J for instruction template T. */ 1594 1595 static INLINE int 1596 match_reg_size (const insn_template *t, unsigned int j) 1597 { 1598 return !((i.types[j].bitfield.byte 1599 && !t->operand_types[j].bitfield.byte) 1600 || (i.types[j].bitfield.word 1601 && !t->operand_types[j].bitfield.word) 1602 || (i.types[j].bitfield.dword 1603 && !t->operand_types[j].bitfield.dword) 1604 || (i.types[j].bitfield.qword 1605 && !t->operand_types[j].bitfield.qword)); 1606 } 1607 1608 /* Return 1 if there is no conflict in any size on operand J for 1609 instruction template T. */ 1610 1611 static INLINE int 1612 match_mem_size (const insn_template *t, unsigned int j) 1613 { 1614 return (match_reg_size (t, j) 1615 && !((i.types[j].bitfield.unspecified 1616 && !t->operand_types[j].bitfield.unspecified) 1617 || (i.types[j].bitfield.fword 1618 && !t->operand_types[j].bitfield.fword) 1619 || (i.types[j].bitfield.tbyte 1620 && !t->operand_types[j].bitfield.tbyte) 1621 || (i.types[j].bitfield.xmmword 1622 && !t->operand_types[j].bitfield.xmmword) 1623 || (i.types[j].bitfield.ymmword 1624 && !t->operand_types[j].bitfield.ymmword))); 1625 } 1626 1627 /* Return 1 if there is no size conflict on any operands for 1628 instruction template T. */ 1629 1630 static INLINE int 1631 operand_size_match (const insn_template *t) 1632 { 1633 unsigned int j; 1634 int match = 1; 1635 1636 /* Don't check jump instructions. */ 1637 if (t->opcode_modifier.jump 1638 || t->opcode_modifier.jumpbyte 1639 || t->opcode_modifier.jumpdword 1640 || t->opcode_modifier.jumpintersegment) 1641 return match; 1642 1643 /* Check memory and accumulator operand size. */ 1644 for (j = 0; j < i.operands; j++) 1645 { 1646 if (t->operand_types[j].bitfield.anysize) 1647 continue; 1648 1649 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) 1650 { 1651 match = 0; 1652 break; 1653 } 1654 1655 if (i.types[j].bitfield.mem && !match_mem_size (t, j)) 1656 { 1657 match = 0; 1658 break; 1659 } 1660 } 1661 1662 if (match) 1663 return match; 1664 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) 1665 { 1666 mismatch: 1667 i.error = operand_size_mismatch; 1668 return 0; 1669 } 1670 1671 /* Check reverse. */ 1672 gas_assert (i.operands == 2); 1673 1674 match = 1; 1675 for (j = 0; j < 2; j++) 1676 { 1677 if (t->operand_types[j].bitfield.acc 1678 && !match_reg_size (t, j ? 0 : 1)) 1679 goto mismatch; 1680 1681 if (i.types[j].bitfield.mem 1682 && !match_mem_size (t, j ? 0 : 1)) 1683 goto mismatch; 1684 } 1685 1686 return match; 1687 } 1688 1689 static INLINE int 1690 operand_type_match (i386_operand_type overlap, 1691 i386_operand_type given) 1692 { 1693 i386_operand_type temp = overlap; 1694 1695 temp.bitfield.jumpabsolute = 0; 1696 temp.bitfield.unspecified = 0; 1697 temp.bitfield.byte = 0; 1698 temp.bitfield.word = 0; 1699 temp.bitfield.dword = 0; 1700 temp.bitfield.fword = 0; 1701 temp.bitfield.qword = 0; 1702 temp.bitfield.tbyte = 0; 1703 temp.bitfield.xmmword = 0; 1704 temp.bitfield.ymmword = 0; 1705 if (operand_type_all_zero (&temp)) 1706 goto mismatch; 1707 1708 if (given.bitfield.baseindex == overlap.bitfield.baseindex 1709 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) 1710 return 1; 1711 1712 mismatch: 1713 i.error = operand_type_mismatch; 1714 return 0; 1715 } 1716 1717 /* If given types g0 and g1 are registers they must be of the same type 1718 unless the expected operand type register overlap is null. 1719 Note that Acc in a template matches every size of reg. */ 1720 1721 static INLINE int 1722 operand_type_register_match (i386_operand_type m0, 1723 i386_operand_type g0, 1724 i386_operand_type t0, 1725 i386_operand_type m1, 1726 i386_operand_type g1, 1727 i386_operand_type t1) 1728 { 1729 if (!operand_type_check (g0, reg)) 1730 return 1; 1731 1732 if (!operand_type_check (g1, reg)) 1733 return 1; 1734 1735 if (g0.bitfield.reg8 == g1.bitfield.reg8 1736 && g0.bitfield.reg16 == g1.bitfield.reg16 1737 && g0.bitfield.reg32 == g1.bitfield.reg32 1738 && g0.bitfield.reg64 == g1.bitfield.reg64) 1739 return 1; 1740 1741 if (m0.bitfield.acc) 1742 { 1743 t0.bitfield.reg8 = 1; 1744 t0.bitfield.reg16 = 1; 1745 t0.bitfield.reg32 = 1; 1746 t0.bitfield.reg64 = 1; 1747 } 1748 1749 if (m1.bitfield.acc) 1750 { 1751 t1.bitfield.reg8 = 1; 1752 t1.bitfield.reg16 = 1; 1753 t1.bitfield.reg32 = 1; 1754 t1.bitfield.reg64 = 1; 1755 } 1756 1757 if (!(t0.bitfield.reg8 & t1.bitfield.reg8) 1758 && !(t0.bitfield.reg16 & t1.bitfield.reg16) 1759 && !(t0.bitfield.reg32 & t1.bitfield.reg32) 1760 && !(t0.bitfield.reg64 & t1.bitfield.reg64)) 1761 return 1; 1762 1763 i.error = register_type_mismatch; 1764 1765 return 0; 1766 } 1767 1768 static INLINE unsigned int 1769 mode_from_disp_size (i386_operand_type t) 1770 { 1771 if (t.bitfield.disp8) 1772 return 1; 1773 else if (t.bitfield.disp16 1774 || t.bitfield.disp32 1775 || t.bitfield.disp32s) 1776 return 2; 1777 else 1778 return 0; 1779 } 1780 1781 static INLINE int 1782 fits_in_signed_byte (offsetT num) 1783 { 1784 return (num >= -128) && (num <= 127); 1785 } 1786 1787 static INLINE int 1788 fits_in_unsigned_byte (offsetT num) 1789 { 1790 return (num & 0xff) == num; 1791 } 1792 1793 static INLINE int 1794 fits_in_unsigned_word (offsetT num) 1795 { 1796 return (num & 0xffff) == num; 1797 } 1798 1799 static INLINE int 1800 fits_in_signed_word (offsetT num) 1801 { 1802 return (-32768 <= num) && (num <= 32767); 1803 } 1804 1805 static INLINE int 1806 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) 1807 { 1808 #ifndef BFD64 1809 return 1; 1810 #else 1811 return (!(((offsetT) -1 << 31) & num) 1812 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); 1813 #endif 1814 } /* fits_in_signed_long() */ 1815 1816 static INLINE int 1817 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) 1818 { 1819 #ifndef BFD64 1820 return 1; 1821 #else 1822 return (num & (((offsetT) 2 << 31) - 1)) == num; 1823 #endif 1824 } /* fits_in_unsigned_long() */ 1825 1826 static INLINE int 1827 fits_in_imm4 (offsetT num) 1828 { 1829 return (num & 0xf) == num; 1830 } 1831 1832 static i386_operand_type 1833 smallest_imm_type (offsetT num) 1834 { 1835 i386_operand_type t; 1836 1837 operand_type_set (&t, 0); 1838 t.bitfield.imm64 = 1; 1839 1840 if (cpu_arch_tune != PROCESSOR_I486 && num == 1) 1841 { 1842 /* This code is disabled on the 486 because all the Imm1 forms 1843 in the opcode table are slower on the i486. They're the 1844 versions with the implicitly specified single-position 1845 displacement, which has another syntax if you really want to 1846 use that form. */ 1847 t.bitfield.imm1 = 1; 1848 t.bitfield.imm8 = 1; 1849 t.bitfield.imm8s = 1; 1850 t.bitfield.imm16 = 1; 1851 t.bitfield.imm32 = 1; 1852 t.bitfield.imm32s = 1; 1853 } 1854 else if (fits_in_signed_byte (num)) 1855 { 1856 t.bitfield.imm8 = 1; 1857 t.bitfield.imm8s = 1; 1858 t.bitfield.imm16 = 1; 1859 t.bitfield.imm32 = 1; 1860 t.bitfield.imm32s = 1; 1861 } 1862 else if (fits_in_unsigned_byte (num)) 1863 { 1864 t.bitfield.imm8 = 1; 1865 t.bitfield.imm16 = 1; 1866 t.bitfield.imm32 = 1; 1867 t.bitfield.imm32s = 1; 1868 } 1869 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 1870 { 1871 t.bitfield.imm16 = 1; 1872 t.bitfield.imm32 = 1; 1873 t.bitfield.imm32s = 1; 1874 } 1875 else if (fits_in_signed_long (num)) 1876 { 1877 t.bitfield.imm32 = 1; 1878 t.bitfield.imm32s = 1; 1879 } 1880 else if (fits_in_unsigned_long (num)) 1881 t.bitfield.imm32 = 1; 1882 1883 return t; 1884 } 1885 1886 static offsetT 1887 offset_in_range (offsetT val, int size) 1888 { 1889 addressT mask; 1890 1891 switch (size) 1892 { 1893 case 1: mask = ((addressT) 1 << 8) - 1; break; 1894 case 2: mask = ((addressT) 1 << 16) - 1; break; 1895 case 4: mask = ((addressT) 2 << 31) - 1; break; 1896 #ifdef BFD64 1897 case 8: mask = ((addressT) 2 << 63) - 1; break; 1898 #endif 1899 default: abort (); 1900 } 1901 1902 #ifdef BFD64 1903 /* If BFD64, sign extend val for 32bit address mode. */ 1904 if (flag_code != CODE_64BIT 1905 || i.prefix[ADDR_PREFIX]) 1906 if ((val & ~(((addressT) 2 << 31) - 1)) == 0) 1907 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 1908 #endif 1909 1910 if ((val & ~mask) != 0 && (val & ~mask) != ~mask) 1911 { 1912 char buf1[40], buf2[40]; 1913 1914 sprint_value (buf1, val); 1915 sprint_value (buf2, val & mask); 1916 as_warn (_("%s shortened to %s"), buf1, buf2); 1917 } 1918 return val & mask; 1919 } 1920 1921 enum PREFIX_GROUP 1922 { 1923 PREFIX_EXIST = 0, 1924 PREFIX_LOCK, 1925 PREFIX_REP, 1926 PREFIX_OTHER 1927 }; 1928 1929 /* Returns 1930 a. PREFIX_EXIST if attempting to add a prefix where one from the 1931 same class already exists. 1932 b. PREFIX_LOCK if lock prefix is added. 1933 c. PREFIX_REP if rep/repne prefix is added. 1934 d. PREFIX_OTHER if other prefix is added. 1935 */ 1936 1937 static enum PREFIX_GROUP 1938 add_prefix (unsigned int prefix) 1939 { 1940 enum PREFIX_GROUP ret = PREFIX_OTHER; 1941 unsigned int q; 1942 1943 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 1944 && flag_code == CODE_64BIT) 1945 { 1946 if ((i.prefix[REX_PREFIX] & prefix & REX_W) 1947 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) 1948 && (prefix & (REX_R | REX_X | REX_B)))) 1949 ret = PREFIX_EXIST; 1950 q = REX_PREFIX; 1951 } 1952 else 1953 { 1954 switch (prefix) 1955 { 1956 default: 1957 abort (); 1958 1959 case CS_PREFIX_OPCODE: 1960 case DS_PREFIX_OPCODE: 1961 case ES_PREFIX_OPCODE: 1962 case FS_PREFIX_OPCODE: 1963 case GS_PREFIX_OPCODE: 1964 case SS_PREFIX_OPCODE: 1965 q = SEG_PREFIX; 1966 break; 1967 1968 case REPNE_PREFIX_OPCODE: 1969 case REPE_PREFIX_OPCODE: 1970 q = REP_PREFIX; 1971 ret = PREFIX_REP; 1972 break; 1973 1974 case LOCK_PREFIX_OPCODE: 1975 q = LOCK_PREFIX; 1976 ret = PREFIX_LOCK; 1977 break; 1978 1979 case FWAIT_OPCODE: 1980 q = WAIT_PREFIX; 1981 break; 1982 1983 case ADDR_PREFIX_OPCODE: 1984 q = ADDR_PREFIX; 1985 break; 1986 1987 case DATA_PREFIX_OPCODE: 1988 q = DATA_PREFIX; 1989 break; 1990 } 1991 if (i.prefix[q] != 0) 1992 ret = PREFIX_EXIST; 1993 } 1994 1995 if (ret) 1996 { 1997 if (!i.prefix[q]) 1998 ++i.prefixes; 1999 i.prefix[q] |= prefix; 2000 } 2001 else 2002 as_bad (_("same type of prefix used twice")); 2003 2004 return ret; 2005 } 2006 2007 static void 2008 update_code_flag (int value, int check) 2009 { 2010 PRINTF_LIKE ((*as_error)); 2011 2012 flag_code = (enum flag_code) value; 2013 if (flag_code == CODE_64BIT) 2014 { 2015 cpu_arch_flags.bitfield.cpu64 = 1; 2016 cpu_arch_flags.bitfield.cpuno64 = 0; 2017 } 2018 else 2019 { 2020 cpu_arch_flags.bitfield.cpu64 = 0; 2021 cpu_arch_flags.bitfield.cpuno64 = 1; 2022 } 2023 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) 2024 { 2025 if (check) 2026 as_error = as_fatal; 2027 else 2028 as_error = as_bad; 2029 (*as_error) (_("64bit mode not supported on `%s'."), 2030 cpu_arch_name ? cpu_arch_name : default_arch); 2031 } 2032 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) 2033 { 2034 if (check) 2035 as_error = as_fatal; 2036 else 2037 as_error = as_bad; 2038 (*as_error) (_("32bit mode not supported on `%s'."), 2039 cpu_arch_name ? cpu_arch_name : default_arch); 2040 } 2041 stackop_size = '\0'; 2042 } 2043 2044 static void 2045 set_code_flag (int value) 2046 { 2047 update_code_flag (value, 0); 2048 } 2049 2050 static void 2051 set_16bit_gcc_code_flag (int new_code_flag) 2052 { 2053 flag_code = (enum flag_code) new_code_flag; 2054 if (flag_code != CODE_16BIT) 2055 abort (); 2056 cpu_arch_flags.bitfield.cpu64 = 0; 2057 cpu_arch_flags.bitfield.cpuno64 = 1; 2058 stackop_size = LONG_MNEM_SUFFIX; 2059 } 2060 2061 static void 2062 set_intel_syntax (int syntax_flag) 2063 { 2064 /* Find out if register prefixing is specified. */ 2065 int ask_naked_reg = 0; 2066 2067 SKIP_WHITESPACE (); 2068 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2069 { 2070 char *string = input_line_pointer; 2071 int e = get_symbol_end (); 2072 2073 if (strcmp (string, "prefix") == 0) 2074 ask_naked_reg = 1; 2075 else if (strcmp (string, "noprefix") == 0) 2076 ask_naked_reg = -1; 2077 else 2078 as_bad (_("bad argument to syntax directive.")); 2079 *input_line_pointer = e; 2080 } 2081 demand_empty_rest_of_line (); 2082 2083 intel_syntax = syntax_flag; 2084 2085 if (ask_naked_reg == 0) 2086 allow_naked_reg = (intel_syntax 2087 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 2088 else 2089 allow_naked_reg = (ask_naked_reg < 0); 2090 2091 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); 2092 2093 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; 2094 identifier_chars['$'] = intel_syntax ? '$' : 0; 2095 register_prefix = allow_naked_reg ? "" : "%"; 2096 } 2097 2098 static void 2099 set_intel_mnemonic (int mnemonic_flag) 2100 { 2101 intel_mnemonic = mnemonic_flag; 2102 } 2103 2104 static void 2105 set_allow_index_reg (int flag) 2106 { 2107 allow_index_reg = flag; 2108 } 2109 2110 static void 2111 set_sse_check (int dummy ATTRIBUTE_UNUSED) 2112 { 2113 SKIP_WHITESPACE (); 2114 2115 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2116 { 2117 char *string = input_line_pointer; 2118 int e = get_symbol_end (); 2119 2120 if (strcmp (string, "none") == 0) 2121 sse_check = sse_check_none; 2122 else if (strcmp (string, "warning") == 0) 2123 sse_check = sse_check_warning; 2124 else if (strcmp (string, "error") == 0) 2125 sse_check = sse_check_error; 2126 else 2127 as_bad (_("bad argument to sse_check directive.")); 2128 *input_line_pointer = e; 2129 } 2130 else 2131 as_bad (_("missing argument for sse_check directive")); 2132 2133 demand_empty_rest_of_line (); 2134 } 2135 2136 static void 2137 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, 2138 i386_cpu_flags new_flag ATTRIBUTE_UNUSED) 2139 { 2140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2141 static const char *arch; 2142 2143 /* Intel LIOM is only supported on ELF. */ 2144 if (!IS_ELF) 2145 return; 2146 2147 if (!arch) 2148 { 2149 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise 2150 use default_arch. */ 2151 arch = cpu_arch_name; 2152 if (!arch) 2153 arch = default_arch; 2154 } 2155 2156 /* If we are targeting Intel L1OM, we must enable it. */ 2157 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM 2158 || new_flag.bitfield.cpul1om) 2159 return; 2160 2161 /* If we are targeting Intel K1OM, we must enable it. */ 2162 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM 2163 || new_flag.bitfield.cpuk1om) 2164 return; 2165 2166 as_bad (_("`%s' is not supported on `%s'"), name, arch); 2167 #endif 2168 } 2169 2170 static void 2171 set_cpu_arch (int dummy ATTRIBUTE_UNUSED) 2172 { 2173 SKIP_WHITESPACE (); 2174 2175 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 2176 { 2177 char *string = input_line_pointer; 2178 int e = get_symbol_end (); 2179 unsigned int j; 2180 i386_cpu_flags flags; 2181 2182 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 2183 { 2184 if (strcmp (string, cpu_arch[j].name) == 0) 2185 { 2186 check_cpu_arch_compatible (string, cpu_arch[j].flags); 2187 2188 if (*string != '.') 2189 { 2190 cpu_arch_name = cpu_arch[j].name; 2191 cpu_sub_arch_name = NULL; 2192 cpu_arch_flags = cpu_arch[j].flags; 2193 if (flag_code == CODE_64BIT) 2194 { 2195 cpu_arch_flags.bitfield.cpu64 = 1; 2196 cpu_arch_flags.bitfield.cpuno64 = 0; 2197 } 2198 else 2199 { 2200 cpu_arch_flags.bitfield.cpu64 = 0; 2201 cpu_arch_flags.bitfield.cpuno64 = 1; 2202 } 2203 cpu_arch_isa = cpu_arch[j].type; 2204 cpu_arch_isa_flags = cpu_arch[j].flags; 2205 if (!cpu_arch_tune_set) 2206 { 2207 cpu_arch_tune = cpu_arch_isa; 2208 cpu_arch_tune_flags = cpu_arch_isa_flags; 2209 } 2210 break; 2211 } 2212 2213 if (!cpu_arch[j].negated) 2214 flags = cpu_flags_or (cpu_arch_flags, 2215 cpu_arch[j].flags); 2216 else 2217 flags = cpu_flags_and_not (cpu_arch_flags, 2218 cpu_arch[j].flags); 2219 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 2220 { 2221 if (cpu_sub_arch_name) 2222 { 2223 char *name = cpu_sub_arch_name; 2224 cpu_sub_arch_name = concat (name, 2225 cpu_arch[j].name, 2226 (const char *) NULL); 2227 free (name); 2228 } 2229 else 2230 cpu_sub_arch_name = xstrdup (cpu_arch[j].name); 2231 cpu_arch_flags = flags; 2232 cpu_arch_isa_flags = flags; 2233 } 2234 *input_line_pointer = e; 2235 demand_empty_rest_of_line (); 2236 return; 2237 } 2238 } 2239 if (j >= ARRAY_SIZE (cpu_arch)) 2240 as_bad (_("no such architecture: `%s'"), string); 2241 2242 *input_line_pointer = e; 2243 } 2244 else 2245 as_bad (_("missing cpu architecture")); 2246 2247 no_cond_jump_promotion = 0; 2248 if (*input_line_pointer == ',' 2249 && !is_end_of_line[(unsigned char) input_line_pointer[1]]) 2250 { 2251 char *string = ++input_line_pointer; 2252 int e = get_symbol_end (); 2253 2254 if (strcmp (string, "nojumps") == 0) 2255 no_cond_jump_promotion = 1; 2256 else if (strcmp (string, "jumps") == 0) 2257 ; 2258 else 2259 as_bad (_("no such architecture modifier: `%s'"), string); 2260 2261 *input_line_pointer = e; 2262 } 2263 2264 demand_empty_rest_of_line (); 2265 } 2266 2267 enum bfd_architecture 2268 i386_arch (void) 2269 { 2270 if (cpu_arch_isa == PROCESSOR_L1OM) 2271 { 2272 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2273 || flag_code != CODE_64BIT) 2274 as_fatal (_("Intel L1OM is 64bit ELF only")); 2275 return bfd_arch_l1om; 2276 } 2277 else if (cpu_arch_isa == PROCESSOR_K1OM) 2278 { 2279 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2280 || flag_code != CODE_64BIT) 2281 as_fatal (_("Intel K1OM is 64bit ELF only")); 2282 return bfd_arch_k1om; 2283 } 2284 else 2285 return bfd_arch_i386; 2286 } 2287 2288 unsigned long 2289 i386_mach (void) 2290 { 2291 if (!strncmp (default_arch, "x86_64", 6)) 2292 { 2293 if (cpu_arch_isa == PROCESSOR_L1OM) 2294 { 2295 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2296 || default_arch[6] != '\0') 2297 as_fatal (_("Intel L1OM is 64bit ELF only")); 2298 return bfd_mach_l1om; 2299 } 2300 else if (cpu_arch_isa == PROCESSOR_K1OM) 2301 { 2302 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 2303 || default_arch[6] != '\0') 2304 as_fatal (_("Intel K1OM is 64bit ELF only")); 2305 return bfd_mach_k1om; 2306 } 2307 else if (default_arch[6] == '\0') 2308 return bfd_mach_x86_64; 2309 else 2310 return bfd_mach_x64_32; 2311 } 2312 else if (!strcmp (default_arch, "i386")) 2313 return bfd_mach_i386_i386; 2314 else 2315 as_fatal (_("unknown architecture")); 2316 } 2317 2318 void 2319 md_begin (void) 2320 { 2321 const char *hash_err; 2322 2323 /* Initialize op_hash hash table. */ 2324 op_hash = hash_new (); 2325 2326 { 2327 const insn_template *optab; 2328 templates *core_optab; 2329 2330 /* Setup for loop. */ 2331 optab = i386_optab; 2332 core_optab = (templates *) xmalloc (sizeof (templates)); 2333 core_optab->start = optab; 2334 2335 while (1) 2336 { 2337 ++optab; 2338 if (optab->name == NULL 2339 || strcmp (optab->name, (optab - 1)->name) != 0) 2340 { 2341 /* different name --> ship out current template list; 2342 add to hash table; & begin anew. */ 2343 core_optab->end = optab; 2344 hash_err = hash_insert (op_hash, 2345 (optab - 1)->name, 2346 (void *) core_optab); 2347 if (hash_err) 2348 { 2349 as_fatal (_("internal Error: Can't hash %s: %s"), 2350 (optab - 1)->name, 2351 hash_err); 2352 } 2353 if (optab->name == NULL) 2354 break; 2355 core_optab = (templates *) xmalloc (sizeof (templates)); 2356 core_optab->start = optab; 2357 } 2358 } 2359 } 2360 2361 /* Initialize reg_hash hash table. */ 2362 reg_hash = hash_new (); 2363 { 2364 const reg_entry *regtab; 2365 unsigned int regtab_size = i386_regtab_size; 2366 2367 for (regtab = i386_regtab; regtab_size--; regtab++) 2368 { 2369 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); 2370 if (hash_err) 2371 as_fatal (_("internal Error: Can't hash %s: %s"), 2372 regtab->reg_name, 2373 hash_err); 2374 } 2375 } 2376 2377 /* Fill in lexical tables: mnemonic_chars, operand_chars. */ 2378 { 2379 int c; 2380 char *p; 2381 2382 for (c = 0; c < 256; c++) 2383 { 2384 if (ISDIGIT (c)) 2385 { 2386 digit_chars[c] = c; 2387 mnemonic_chars[c] = c; 2388 register_chars[c] = c; 2389 operand_chars[c] = c; 2390 } 2391 else if (ISLOWER (c)) 2392 { 2393 mnemonic_chars[c] = c; 2394 register_chars[c] = c; 2395 operand_chars[c] = c; 2396 } 2397 else if (ISUPPER (c)) 2398 { 2399 mnemonic_chars[c] = TOLOWER (c); 2400 register_chars[c] = mnemonic_chars[c]; 2401 operand_chars[c] = c; 2402 } 2403 2404 if (ISALPHA (c) || ISDIGIT (c)) 2405 identifier_chars[c] = c; 2406 else if (c >= 128) 2407 { 2408 identifier_chars[c] = c; 2409 operand_chars[c] = c; 2410 } 2411 } 2412 2413 #ifdef LEX_AT 2414 identifier_chars['@'] = '@'; 2415 #endif 2416 #ifdef LEX_QM 2417 identifier_chars['?'] = '?'; 2418 operand_chars['?'] = '?'; 2419 #endif 2420 digit_chars['-'] = '-'; 2421 mnemonic_chars['_'] = '_'; 2422 mnemonic_chars['-'] = '-'; 2423 mnemonic_chars['.'] = '.'; 2424 identifier_chars['_'] = '_'; 2425 identifier_chars['.'] = '.'; 2426 2427 for (p = operand_special_chars; *p != '\0'; p++) 2428 operand_chars[(unsigned char) *p] = *p; 2429 } 2430 2431 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2432 if (IS_ELF) 2433 { 2434 record_alignment (text_section, 2); 2435 record_alignment (data_section, 2); 2436 record_alignment (bss_section, 2); 2437 } 2438 #endif 2439 2440 if (flag_code == CODE_64BIT) 2441 { 2442 #if defined (OBJ_COFF) && defined (TE_PE) 2443 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour 2444 ? 32 : 16); 2445 #else 2446 x86_dwarf2_return_column = 16; 2447 #endif 2448 x86_cie_data_alignment = -8; 2449 } 2450 else 2451 { 2452 x86_dwarf2_return_column = 8; 2453 x86_cie_data_alignment = -4; 2454 } 2455 } 2456 2457 void 2458 i386_print_statistics (FILE *file) 2459 { 2460 hash_print_statistics (file, "i386 opcode", op_hash); 2461 hash_print_statistics (file, "i386 register", reg_hash); 2462 } 2463 2464 #ifdef DEBUG386 2465 2466 /* Debugging routines for md_assemble. */ 2467 static void pte (insn_template *); 2468 static void pt (i386_operand_type); 2469 static void pe (expressionS *); 2470 static void ps (symbolS *); 2471 2472 static void 2473 pi (char *line, i386_insn *x) 2474 { 2475 unsigned int j; 2476 2477 fprintf (stdout, "%s: template ", line); 2478 pte (&x->tm); 2479 fprintf (stdout, " address: base %s index %s scale %x\n", 2480 x->base_reg ? x->base_reg->reg_name : "none", 2481 x->index_reg ? x->index_reg->reg_name : "none", 2482 x->log2_scale_factor); 2483 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", 2484 x->rm.mode, x->rm.reg, x->rm.regmem); 2485 fprintf (stdout, " sib: base %x index %x scale %x\n", 2486 x->sib.base, x->sib.index, x->sib.scale); 2487 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", 2488 (x->rex & REX_W) != 0, 2489 (x->rex & REX_R) != 0, 2490 (x->rex & REX_X) != 0, 2491 (x->rex & REX_B) != 0); 2492 for (j = 0; j < x->operands; j++) 2493 { 2494 fprintf (stdout, " #%d: ", j + 1); 2495 pt (x->types[j]); 2496 fprintf (stdout, "\n"); 2497 if (x->types[j].bitfield.reg8 2498 || x->types[j].bitfield.reg16 2499 || x->types[j].bitfield.reg32 2500 || x->types[j].bitfield.reg64 2501 || x->types[j].bitfield.regmmx 2502 || x->types[j].bitfield.regxmm 2503 || x->types[j].bitfield.regymm 2504 || x->types[j].bitfield.sreg2 2505 || x->types[j].bitfield.sreg3 2506 || x->types[j].bitfield.control 2507 || x->types[j].bitfield.debug 2508 || x->types[j].bitfield.test) 2509 fprintf (stdout, "%s\n", x->op[j].regs->reg_name); 2510 if (operand_type_check (x->types[j], imm)) 2511 pe (x->op[j].imms); 2512 if (operand_type_check (x->types[j], disp)) 2513 pe (x->op[j].disps); 2514 } 2515 } 2516 2517 static void 2518 pte (insn_template *t) 2519 { 2520 unsigned int j; 2521 fprintf (stdout, " %d operands ", t->operands); 2522 fprintf (stdout, "opcode %x ", t->base_opcode); 2523 if (t->extension_opcode != None) 2524 fprintf (stdout, "ext %x ", t->extension_opcode); 2525 if (t->opcode_modifier.d) 2526 fprintf (stdout, "D"); 2527 if (t->opcode_modifier.w) 2528 fprintf (stdout, "W"); 2529 fprintf (stdout, "\n"); 2530 for (j = 0; j < t->operands; j++) 2531 { 2532 fprintf (stdout, " #%d type ", j + 1); 2533 pt (t->operand_types[j]); 2534 fprintf (stdout, "\n"); 2535 } 2536 } 2537 2538 static void 2539 pe (expressionS *e) 2540 { 2541 fprintf (stdout, " operation %d\n", e->X_op); 2542 fprintf (stdout, " add_number %ld (%lx)\n", 2543 (long) e->X_add_number, (long) e->X_add_number); 2544 if (e->X_add_symbol) 2545 { 2546 fprintf (stdout, " add_symbol "); 2547 ps (e->X_add_symbol); 2548 fprintf (stdout, "\n"); 2549 } 2550 if (e->X_op_symbol) 2551 { 2552 fprintf (stdout, " op_symbol "); 2553 ps (e->X_op_symbol); 2554 fprintf (stdout, "\n"); 2555 } 2556 } 2557 2558 static void 2559 ps (symbolS *s) 2560 { 2561 fprintf (stdout, "%s type %s%s", 2562 S_GET_NAME (s), 2563 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 2564 segment_name (S_GET_SEGMENT (s))); 2565 } 2566 2567 static struct type_name 2568 { 2569 i386_operand_type mask; 2570 const char *name; 2571 } 2572 const type_names[] = 2573 { 2574 { OPERAND_TYPE_REG8, "r8" }, 2575 { OPERAND_TYPE_REG16, "r16" }, 2576 { OPERAND_TYPE_REG32, "r32" }, 2577 { OPERAND_TYPE_REG64, "r64" }, 2578 { OPERAND_TYPE_IMM8, "i8" }, 2579 { OPERAND_TYPE_IMM8, "i8s" }, 2580 { OPERAND_TYPE_IMM16, "i16" }, 2581 { OPERAND_TYPE_IMM32, "i32" }, 2582 { OPERAND_TYPE_IMM32S, "i32s" }, 2583 { OPERAND_TYPE_IMM64, "i64" }, 2584 { OPERAND_TYPE_IMM1, "i1" }, 2585 { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, 2586 { OPERAND_TYPE_DISP8, "d8" }, 2587 { OPERAND_TYPE_DISP16, "d16" }, 2588 { OPERAND_TYPE_DISP32, "d32" }, 2589 { OPERAND_TYPE_DISP32S, "d32s" }, 2590 { OPERAND_TYPE_DISP64, "d64" }, 2591 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, 2592 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, 2593 { OPERAND_TYPE_CONTROL, "control reg" }, 2594 { OPERAND_TYPE_TEST, "test reg" }, 2595 { OPERAND_TYPE_DEBUG, "debug reg" }, 2596 { OPERAND_TYPE_FLOATREG, "FReg" }, 2597 { OPERAND_TYPE_FLOATACC, "FAcc" }, 2598 { OPERAND_TYPE_SREG2, "SReg2" }, 2599 { OPERAND_TYPE_SREG3, "SReg3" }, 2600 { OPERAND_TYPE_ACC, "Acc" }, 2601 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, 2602 { OPERAND_TYPE_REGMMX, "rMMX" }, 2603 { OPERAND_TYPE_REGXMM, "rXMM" }, 2604 { OPERAND_TYPE_REGYMM, "rYMM" }, 2605 { OPERAND_TYPE_ESSEG, "es" }, 2606 }; 2607 2608 static void 2609 pt (i386_operand_type t) 2610 { 2611 unsigned int j; 2612 i386_operand_type a; 2613 2614 for (j = 0; j < ARRAY_SIZE (type_names); j++) 2615 { 2616 a = operand_type_and (t, type_names[j].mask); 2617 if (!operand_type_all_zero (&a)) 2618 fprintf (stdout, "%s, ", type_names[j].name); 2619 } 2620 fflush (stdout); 2621 } 2622 2623 #endif /* DEBUG386 */ 2624 2625 static bfd_reloc_code_real_type 2626 reloc (unsigned int size, 2627 int pcrel, 2628 int sign, 2629 bfd_reloc_code_real_type other) 2630 { 2631 if (other != NO_RELOC) 2632 { 2633 reloc_howto_type *rel; 2634 2635 if (size == 8) 2636 switch (other) 2637 { 2638 case BFD_RELOC_X86_64_GOT32: 2639 return BFD_RELOC_X86_64_GOT64; 2640 break; 2641 case BFD_RELOC_X86_64_PLTOFF64: 2642 return BFD_RELOC_X86_64_PLTOFF64; 2643 break; 2644 case BFD_RELOC_X86_64_GOTPC32: 2645 other = BFD_RELOC_X86_64_GOTPC64; 2646 break; 2647 case BFD_RELOC_X86_64_GOTPCREL: 2648 other = BFD_RELOC_X86_64_GOTPCREL64; 2649 break; 2650 case BFD_RELOC_X86_64_TPOFF32: 2651 other = BFD_RELOC_X86_64_TPOFF64; 2652 break; 2653 case BFD_RELOC_X86_64_DTPOFF32: 2654 other = BFD_RELOC_X86_64_DTPOFF64; 2655 break; 2656 default: 2657 break; 2658 } 2659 2660 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ 2661 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) 2662 sign = -1; 2663 2664 rel = bfd_reloc_type_lookup (stdoutput, other); 2665 if (!rel) 2666 as_bad (_("unknown relocation (%u)"), other); 2667 else if (size != bfd_get_reloc_size (rel)) 2668 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), 2669 bfd_get_reloc_size (rel), 2670 size); 2671 else if (pcrel && !rel->pc_relative) 2672 as_bad (_("non-pc-relative relocation for pc-relative field")); 2673 else if ((rel->complain_on_overflow == complain_overflow_signed 2674 && !sign) 2675 || (rel->complain_on_overflow == complain_overflow_unsigned 2676 && sign > 0)) 2677 as_bad (_("relocated field and relocation type differ in signedness")); 2678 else 2679 return other; 2680 return NO_RELOC; 2681 } 2682 2683 if (pcrel) 2684 { 2685 if (!sign) 2686 as_bad (_("there are no unsigned pc-relative relocations")); 2687 switch (size) 2688 { 2689 case 1: return BFD_RELOC_8_PCREL; 2690 case 2: return BFD_RELOC_16_PCREL; 2691 case 4: return BFD_RELOC_32_PCREL; 2692 case 8: return BFD_RELOC_64_PCREL; 2693 } 2694 as_bad (_("cannot do %u byte pc-relative relocation"), size); 2695 } 2696 else 2697 { 2698 if (sign > 0) 2699 switch (size) 2700 { 2701 case 4: return BFD_RELOC_X86_64_32S; 2702 } 2703 else 2704 switch (size) 2705 { 2706 case 1: return BFD_RELOC_8; 2707 case 2: return BFD_RELOC_16; 2708 case 4: return BFD_RELOC_32; 2709 case 8: return BFD_RELOC_64; 2710 } 2711 as_bad (_("cannot do %s %u byte relocation"), 2712 sign > 0 ? "signed" : "unsigned", size); 2713 } 2714 2715 return NO_RELOC; 2716 } 2717 2718 /* Here we decide which fixups can be adjusted to make them relative to 2719 the beginning of the section instead of the symbol. Basically we need 2720 to make sure that the dynamic relocations are done correctly, so in 2721 some cases we force the original symbol to be used. */ 2722 2723 int 2724 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) 2725 { 2726 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 2727 if (!IS_ELF) 2728 return 1; 2729 2730 /* Don't adjust pc-relative references to merge sections in 64-bit 2731 mode. */ 2732 if (use_rela_relocations 2733 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 2734 && fixP->fx_pcrel) 2735 return 0; 2736 2737 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations 2738 and changed later by validate_fix. */ 2739 if (GOT_symbol && fixP->fx_subsy == GOT_symbol 2740 && fixP->fx_r_type == BFD_RELOC_32_PCREL) 2741 return 0; 2742 2743 /* adjust_reloc_syms doesn't know about the GOT. */ 2744 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF 2745 || fixP->fx_r_type == BFD_RELOC_386_PLT32 2746 || fixP->fx_r_type == BFD_RELOC_386_GOT32 2747 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD 2748 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM 2749 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 2750 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 2751 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE 2752 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE 2753 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 2754 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE 2755 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC 2756 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL 2757 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 2758 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 2759 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL 2760 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD 2761 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD 2762 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 2763 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 2764 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF 2765 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 2766 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 2767 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 2768 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC 2769 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL 2770 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 2771 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 2772 return 0; 2773 #endif 2774 return 1; 2775 } 2776 2777 static int 2778 intel_float_operand (const char *mnemonic) 2779 { 2780 /* Note that the value returned is meaningful only for opcodes with (memory) 2781 operands, hence the code here is free to improperly handle opcodes that 2782 have no operands (for better performance and smaller code). */ 2783 2784 if (mnemonic[0] != 'f') 2785 return 0; /* non-math */ 2786 2787 switch (mnemonic[1]) 2788 { 2789 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and 2790 the fs segment override prefix not currently handled because no 2791 call path can make opcodes without operands get here */ 2792 case 'i': 2793 return 2 /* integer op */; 2794 case 'l': 2795 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) 2796 return 3; /* fldcw/fldenv */ 2797 break; 2798 case 'n': 2799 if (mnemonic[2] != 'o' /* fnop */) 2800 return 3; /* non-waiting control op */ 2801 break; 2802 case 'r': 2803 if (mnemonic[2] == 's') 2804 return 3; /* frstor/frstpm */ 2805 break; 2806 case 's': 2807 if (mnemonic[2] == 'a') 2808 return 3; /* fsave */ 2809 if (mnemonic[2] == 't') 2810 { 2811 switch (mnemonic[3]) 2812 { 2813 case 'c': /* fstcw */ 2814 case 'd': /* fstdw */ 2815 case 'e': /* fstenv */ 2816 case 's': /* fsts[gw] */ 2817 return 3; 2818 } 2819 } 2820 break; 2821 case 'x': 2822 if (mnemonic[2] == 'r' || mnemonic[2] == 's') 2823 return 0; /* fxsave/fxrstor are not really math ops */ 2824 break; 2825 } 2826 2827 return 1; 2828 } 2829 2830 /* Build the VEX prefix. */ 2831 2832 static void 2833 build_vex_prefix (const insn_template *t) 2834 { 2835 unsigned int register_specifier; 2836 unsigned int implied_prefix; 2837 unsigned int vector_length; 2838 2839 /* Check register specifier. */ 2840 if (i.vex.register_specifier) 2841 { 2842 register_specifier = i.vex.register_specifier->reg_num; 2843 if ((i.vex.register_specifier->reg_flags & RegRex)) 2844 register_specifier += 8; 2845 register_specifier = ~register_specifier & 0xf; 2846 } 2847 else 2848 register_specifier = 0xf; 2849 2850 /* Use 2-byte VEX prefix by swappping destination and source 2851 operand. */ 2852 if (!i.swap_operand 2853 && i.operands == i.reg_operands 2854 && i.tm.opcode_modifier.vexopcode == VEX0F 2855 && i.tm.opcode_modifier.s 2856 && i.rex == REX_B) 2857 { 2858 unsigned int xchg = i.operands - 1; 2859 union i386_op temp_op; 2860 i386_operand_type temp_type; 2861 2862 temp_type = i.types[xchg]; 2863 i.types[xchg] = i.types[0]; 2864 i.types[0] = temp_type; 2865 temp_op = i.op[xchg]; 2866 i.op[xchg] = i.op[0]; 2867 i.op[0] = temp_op; 2868 2869 gas_assert (i.rm.mode == 3); 2870 2871 i.rex = REX_R; 2872 xchg = i.rm.regmem; 2873 i.rm.regmem = i.rm.reg; 2874 i.rm.reg = xchg; 2875 2876 /* Use the next insn. */ 2877 i.tm = t[1]; 2878 } 2879 2880 if (i.tm.opcode_modifier.vex == VEXScalar) 2881 vector_length = avxscalar; 2882 else 2883 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; 2884 2885 switch ((i.tm.base_opcode >> 8) & 0xff) 2886 { 2887 case 0: 2888 implied_prefix = 0; 2889 break; 2890 case DATA_PREFIX_OPCODE: 2891 implied_prefix = 1; 2892 break; 2893 case REPE_PREFIX_OPCODE: 2894 implied_prefix = 2; 2895 break; 2896 case REPNE_PREFIX_OPCODE: 2897 implied_prefix = 3; 2898 break; 2899 default: 2900 abort (); 2901 } 2902 2903 /* Use 2-byte VEX prefix if possible. */ 2904 if (i.tm.opcode_modifier.vexopcode == VEX0F 2905 && i.tm.opcode_modifier.vexw != VEXW1 2906 && (i.rex & (REX_W | REX_X | REX_B)) == 0) 2907 { 2908 /* 2-byte VEX prefix. */ 2909 unsigned int r; 2910 2911 i.vex.length = 2; 2912 i.vex.bytes[0] = 0xc5; 2913 2914 /* Check the REX.R bit. */ 2915 r = (i.rex & REX_R) ? 0 : 1; 2916 i.vex.bytes[1] = (r << 7 2917 | register_specifier << 3 2918 | vector_length << 2 2919 | implied_prefix); 2920 } 2921 else 2922 { 2923 /* 3-byte VEX prefix. */ 2924 unsigned int m, w; 2925 2926 i.vex.length = 3; 2927 2928 switch (i.tm.opcode_modifier.vexopcode) 2929 { 2930 case VEX0F: 2931 m = 0x1; 2932 i.vex.bytes[0] = 0xc4; 2933 break; 2934 case VEX0F38: 2935 m = 0x2; 2936 i.vex.bytes[0] = 0xc4; 2937 break; 2938 case VEX0F3A: 2939 m = 0x3; 2940 i.vex.bytes[0] = 0xc4; 2941 break; 2942 case XOP08: 2943 m = 0x8; 2944 i.vex.bytes[0] = 0x8f; 2945 break; 2946 case XOP09: 2947 m = 0x9; 2948 i.vex.bytes[0] = 0x8f; 2949 break; 2950 case XOP0A: 2951 m = 0xa; 2952 i.vex.bytes[0] = 0x8f; 2953 break; 2954 default: 2955 abort (); 2956 } 2957 2958 /* The high 3 bits of the second VEX byte are 1's compliment 2959 of RXB bits from REX. */ 2960 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; 2961 2962 /* Check the REX.W bit. */ 2963 w = (i.rex & REX_W) ? 1 : 0; 2964 if (i.tm.opcode_modifier.vexw) 2965 { 2966 if (w) 2967 abort (); 2968 2969 if (i.tm.opcode_modifier.vexw == VEXW1) 2970 w = 1; 2971 } 2972 2973 i.vex.bytes[2] = (w << 7 2974 | register_specifier << 3 2975 | vector_length << 2 2976 | implied_prefix); 2977 } 2978 } 2979 2980 static void 2981 process_immext (void) 2982 { 2983 expressionS *exp; 2984 2985 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) 2986 { 2987 /* SSE3 Instructions have the fixed operands with an opcode 2988 suffix which is coded in the same place as an 8-bit immediate 2989 field would be. Here we check those operands and remove them 2990 afterwards. */ 2991 unsigned int x; 2992 2993 for (x = 0; x < i.operands; x++) 2994 if (i.op[x].regs->reg_num != x) 2995 as_bad (_("can't use register '%s%s' as operand %d in '%s'."), 2996 register_prefix, i.op[x].regs->reg_name, x + 1, 2997 i.tm.name); 2998 2999 i.operands = 0; 3000 } 3001 3002 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix 3003 which is coded in the same place as an 8-bit immediate field 3004 would be. Here we fake an 8-bit immediate operand from the 3005 opcode suffix stored in tm.extension_opcode. 3006 3007 AVX instructions also use this encoding, for some of 3008 3 argument instructions. */ 3009 3010 gas_assert (i.imm_operands == 0 3011 && (i.operands <= 2 3012 || (i.tm.opcode_modifier.vex 3013 && i.operands <= 4))); 3014 3015 exp = &im_expressions[i.imm_operands++]; 3016 i.op[i.operands].imms = exp; 3017 i.types[i.operands] = imm8; 3018 i.operands++; 3019 exp->X_op = O_constant; 3020 exp->X_add_number = i.tm.extension_opcode; 3021 i.tm.extension_opcode = None; 3022 } 3023 3024 3025 static int 3026 check_hle (void) 3027 { 3028 switch (i.tm.opcode_modifier.hleprefixok) 3029 { 3030 default: 3031 abort (); 3032 case HLEPrefixNone: 3033 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE) 3034 as_bad (_("invalid instruction `%s' after `xacquire'"), 3035 i.tm.name); 3036 else 3037 as_bad (_("invalid instruction `%s' after `xrelease'"), 3038 i.tm.name); 3039 return 0; 3040 case HLEPrefixLock: 3041 if (i.prefix[LOCK_PREFIX]) 3042 return 1; 3043 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE) 3044 as_bad (_("missing `lock' with `xacquire'")); 3045 else 3046 as_bad (_("missing `lock' with `xrelease'")); 3047 return 0; 3048 case HLEPrefixAny: 3049 return 1; 3050 case HLEPrefixRelease: 3051 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) 3052 { 3053 as_bad (_("instruction `%s' after `xacquire' not allowed"), 3054 i.tm.name); 3055 return 0; 3056 } 3057 if (i.mem_operands == 0 3058 || !operand_type_check (i.types[i.operands - 1], anymem)) 3059 { 3060 as_bad (_("memory destination needed for instruction `%s'" 3061 " after `xrelease'"), i.tm.name); 3062 return 0; 3063 } 3064 return 1; 3065 } 3066 } 3067 3068 /* This is the guts of the machine-dependent assembler. LINE points to a 3069 machine dependent instruction. This function is supposed to emit 3070 the frags/bytes it assembles to. */ 3071 3072 void 3073 md_assemble (char *line) 3074 { 3075 unsigned int j; 3076 char mnemonic[MAX_MNEM_SIZE]; 3077 const insn_template *t; 3078 3079 /* Initialize globals. */ 3080 memset (&i, '\0', sizeof (i)); 3081 for (j = 0; j < MAX_OPERANDS; j++) 3082 i.reloc[j] = NO_RELOC; 3083 memset (disp_expressions, '\0', sizeof (disp_expressions)); 3084 memset (im_expressions, '\0', sizeof (im_expressions)); 3085 save_stack_p = save_stack; 3086 3087 /* First parse an instruction mnemonic & call i386_operand for the operands. 3088 We assume that the scrubber has arranged it so that line[0] is the valid 3089 start of a (possibly prefixed) mnemonic. */ 3090 3091 line = parse_insn (line, mnemonic); 3092 if (line == NULL) 3093 return; 3094 3095 line = parse_operands (line, mnemonic); 3096 this_operand = -1; 3097 if (line == NULL) 3098 return; 3099 3100 /* Now we've parsed the mnemonic into a set of templates, and have the 3101 operands at hand. */ 3102 3103 /* All intel opcodes have reversed operands except for "bound" and 3104 "enter". We also don't reverse intersegment "jmp" and "call" 3105 instructions with 2 immediate operands so that the immediate segment 3106 precedes the offset, as it does when in AT&T mode. */ 3107 if (intel_syntax 3108 && i.operands > 1 3109 && (strcmp (mnemonic, "bound") != 0) 3110 && (strcmp (mnemonic, "invlpga") != 0) 3111 && !(operand_type_check (i.types[0], imm) 3112 && operand_type_check (i.types[1], imm))) 3113 swap_operands (); 3114 3115 /* The order of the immediates should be reversed 3116 for 2 immediates extrq and insertq instructions */ 3117 if (i.imm_operands == 2 3118 && (strcmp (mnemonic, "extrq") == 0 3119 || strcmp (mnemonic, "insertq") == 0)) 3120 swap_2_operands (0, 1); 3121 3122 if (i.imm_operands) 3123 optimize_imm (); 3124 3125 /* Don't optimize displacement for movabs since it only takes 64bit 3126 displacement. */ 3127 if (i.disp_operands 3128 && i.disp_encoding != disp_encoding_32bit 3129 && (flag_code != CODE_64BIT 3130 || strcmp (mnemonic, "movabs") != 0)) 3131 optimize_disp (); 3132 3133 /* Next, we find a template that matches the given insn, 3134 making sure the overlap of the given operands types is consistent 3135 with the template operand types. */ 3136 3137 if (!(t = match_template ())) 3138 return; 3139 3140 if (sse_check != sse_check_none 3141 && !i.tm.opcode_modifier.noavx 3142 && (i.tm.cpu_flags.bitfield.cpusse 3143 || i.tm.cpu_flags.bitfield.cpusse2 3144 || i.tm.cpu_flags.bitfield.cpusse3 3145 || i.tm.cpu_flags.bitfield.cpussse3 3146 || i.tm.cpu_flags.bitfield.cpusse4_1 3147 || i.tm.cpu_flags.bitfield.cpusse4_2)) 3148 { 3149 (sse_check == sse_check_warning 3150 ? as_warn 3151 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); 3152 } 3153 3154 /* Zap movzx and movsx suffix. The suffix has been set from 3155 "word ptr" or "byte ptr" on the source operand in Intel syntax 3156 or extracted from mnemonic in AT&T syntax. But we'll use 3157 the destination register to choose the suffix for encoding. */ 3158 if ((i.tm.base_opcode & ~9) == 0x0fb6) 3159 { 3160 /* In Intel syntax, there must be a suffix. In AT&T syntax, if 3161 there is no suffix, the default will be byte extension. */ 3162 if (i.reg_operands != 2 3163 && !i.suffix 3164 && intel_syntax) 3165 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 3166 3167 i.suffix = 0; 3168 } 3169 3170 if (i.tm.opcode_modifier.fwait) 3171 if (!add_prefix (FWAIT_OPCODE)) 3172 return; 3173 3174 /* Check for lock without a lockable instruction. Destination operand 3175 must be memory unless it is xchg (0x86). */ 3176 if (i.prefix[LOCK_PREFIX] 3177 && (!i.tm.opcode_modifier.islockable 3178 || i.mem_operands == 0 3179 || (i.tm.base_opcode != 0x86 3180 && !operand_type_check (i.types[i.operands - 1], anymem)))) 3181 { 3182 as_bad (_("expecting lockable instruction after `lock'")); 3183 return; 3184 } 3185 3186 /* Check if HLE prefix is OK. */ 3187 if (i.have_hle && !check_hle ()) 3188 return; 3189 3190 /* Check string instruction segment overrides. */ 3191 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) 3192 { 3193 if (!check_string ()) 3194 return; 3195 i.disp_operands = 0; 3196 } 3197 3198 if (!process_suffix ()) 3199 return; 3200 3201 /* Update operand types. */ 3202 for (j = 0; j < i.operands; j++) 3203 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); 3204 3205 /* Make still unresolved immediate matches conform to size of immediate 3206 given in i.suffix. */ 3207 if (!finalize_imm ()) 3208 return; 3209 3210 if (i.types[0].bitfield.imm1) 3211 i.imm_operands = 0; /* kludge for shift insns. */ 3212 3213 /* We only need to check those implicit registers for instructions 3214 with 3 operands or less. */ 3215 if (i.operands <= 3) 3216 for (j = 0; j < i.operands; j++) 3217 if (i.types[j].bitfield.inoutportreg 3218 || i.types[j].bitfield.shiftcount 3219 || i.types[j].bitfield.acc 3220 || i.types[j].bitfield.floatacc) 3221 i.reg_operands--; 3222 3223 /* ImmExt should be processed after SSE2AVX. */ 3224 if (!i.tm.opcode_modifier.sse2avx 3225 && i.tm.opcode_modifier.immext) 3226 process_immext (); 3227 3228 /* For insns with operands there are more diddles to do to the opcode. */ 3229 if (i.operands) 3230 { 3231 if (!process_operands ()) 3232 return; 3233 } 3234 else if (!quiet_warnings && i.tm.opcode_modifier.ugh) 3235 { 3236 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 3237 as_warn (_("translating to `%sp'"), i.tm.name); 3238 } 3239 3240 if (i.tm.opcode_modifier.vex) 3241 build_vex_prefix (t); 3242 3243 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 3244 instructions may define INT_OPCODE as well, so avoid this corner 3245 case for those instructions that use MODRM. */ 3246 if (i.tm.base_opcode == INT_OPCODE 3247 && !i.tm.opcode_modifier.modrm 3248 && i.op[0].imms->X_add_number == 3) 3249 { 3250 i.tm.base_opcode = INT3_OPCODE; 3251 i.imm_operands = 0; 3252 } 3253 3254 if ((i.tm.opcode_modifier.jump 3255 || i.tm.opcode_modifier.jumpbyte 3256 || i.tm.opcode_modifier.jumpdword) 3257 && i.op[0].disps->X_op == O_constant) 3258 { 3259 /* Convert "jmp constant" (and "call constant") to a jump (call) to 3260 the absolute address given by the constant. Since ix86 jumps and 3261 calls are pc relative, we need to generate a reloc. */ 3262 i.op[0].disps->X_add_symbol = &abs_symbol; 3263 i.op[0].disps->X_op = O_symbol; 3264 } 3265 3266 if (i.tm.opcode_modifier.rex64) 3267 i.rex |= REX_W; 3268 3269 /* For 8 bit registers we need an empty rex prefix. Also if the 3270 instruction already has a prefix, we need to convert old 3271 registers to new ones. */ 3272 3273 if ((i.types[0].bitfield.reg8 3274 && (i.op[0].regs->reg_flags & RegRex64) != 0) 3275 || (i.types[1].bitfield.reg8 3276 && (i.op[1].regs->reg_flags & RegRex64) != 0) 3277 || ((i.types[0].bitfield.reg8 3278 || i.types[1].bitfield.reg8) 3279 && i.rex != 0)) 3280 { 3281 int x; 3282 3283 i.rex |= REX_OPCODE; 3284 for (x = 0; x < 2; x++) 3285 { 3286 /* Look for 8 bit operand that uses old registers. */ 3287 if (i.types[x].bitfield.reg8 3288 && (i.op[x].regs->reg_flags & RegRex64) == 0) 3289 { 3290 /* In case it is "hi" register, give up. */ 3291 if (i.op[x].regs->reg_num > 3) 3292 as_bad (_("can't encode register '%s%s' in an " 3293 "instruction requiring REX prefix."), 3294 register_prefix, i.op[x].regs->reg_name); 3295 3296 /* Otherwise it is equivalent to the extended register. 3297 Since the encoding doesn't change this is merely 3298 cosmetic cleanup for debug output. */ 3299 3300 i.op[x].regs = i.op[x].regs + 8; 3301 } 3302 } 3303 } 3304 3305 if (i.rex != 0) 3306 add_prefix (REX_OPCODE | i.rex); 3307 3308 /* We are ready to output the insn. */ 3309 output_insn (); 3310 } 3311 3312 static char * 3313 parse_insn (char *line, char *mnemonic) 3314 { 3315 char *l = line; 3316 char *token_start = l; 3317 char *mnem_p; 3318 int supported; 3319 const insn_template *t; 3320 char *dot_p = NULL; 3321 3322 /* Non-zero if we found a prefix only acceptable with string insns. */ 3323 const char *expecting_string_instruction = NULL; 3324 3325 while (1) 3326 { 3327 mnem_p = mnemonic; 3328 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 3329 { 3330 if (*mnem_p == '.') 3331 dot_p = mnem_p; 3332 mnem_p++; 3333 if (mnem_p >= mnemonic + MAX_MNEM_SIZE) 3334 { 3335 as_bad (_("no such instruction: `%s'"), token_start); 3336 return NULL; 3337 } 3338 l++; 3339 } 3340 if (!is_space_char (*l) 3341 && *l != END_OF_INSN 3342 && (intel_syntax 3343 || (*l != PREFIX_SEPARATOR 3344 && *l != ','))) 3345 { 3346 as_bad (_("invalid character %s in mnemonic"), 3347 output_invalid (*l)); 3348 return NULL; 3349 } 3350 if (token_start == l) 3351 { 3352 if (!intel_syntax && *l == PREFIX_SEPARATOR) 3353 as_bad (_("expecting prefix; got nothing")); 3354 else 3355 as_bad (_("expecting mnemonic; got nothing")); 3356 return NULL; 3357 } 3358 3359 /* Look up instruction (or prefix) via hash table. */ 3360 current_templates = (const templates *) hash_find (op_hash, mnemonic); 3361 3362 if (*l != END_OF_INSN 3363 && (!is_space_char (*l) || l[1] != END_OF_INSN) 3364 && current_templates 3365 && current_templates->start->opcode_modifier.isprefix) 3366 { 3367 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) 3368 { 3369 as_bad ((flag_code != CODE_64BIT 3370 ? _("`%s' is only supported in 64-bit mode") 3371 : _("`%s' is not supported in 64-bit mode")), 3372 current_templates->start->name); 3373 return NULL; 3374 } 3375 /* If we are in 16-bit mode, do not allow addr16 or data16. 3376 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 3377 if ((current_templates->start->opcode_modifier.size16 3378 || current_templates->start->opcode_modifier.size32) 3379 && flag_code != CODE_64BIT 3380 && (current_templates->start->opcode_modifier.size32 3381 ^ (flag_code == CODE_16BIT))) 3382 { 3383 as_bad (_("redundant %s prefix"), 3384 current_templates->start->name); 3385 return NULL; 3386 } 3387 /* Add prefix, checking for repeated prefixes. */ 3388 switch (add_prefix (current_templates->start->base_opcode)) 3389 { 3390 case PREFIX_EXIST: 3391 return NULL; 3392 case PREFIX_REP: 3393 if (current_templates->start->cpu_flags.bitfield.cpuhle) 3394 i.have_hle = 1; 3395 else 3396 expecting_string_instruction = current_templates->start->name; 3397 break; 3398 default: 3399 break; 3400 } 3401 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 3402 token_start = ++l; 3403 } 3404 else 3405 break; 3406 } 3407 3408 if (!current_templates) 3409 { 3410 /* Check if we should swap operand or force 32bit displacement in 3411 encoding. */ 3412 if (mnem_p - 2 == dot_p && dot_p[1] == 's') 3413 i.swap_operand = 1; 3414 else if (mnem_p - 3 == dot_p 3415 && dot_p[1] == 'd' 3416 && dot_p[2] == '8') 3417 i.disp_encoding = disp_encoding_8bit; 3418 else if (mnem_p - 4 == dot_p 3419 && dot_p[1] == 'd' 3420 && dot_p[2] == '3' 3421 && dot_p[3] == '2') 3422 i.disp_encoding = disp_encoding_32bit; 3423 else 3424 goto check_suffix; 3425 mnem_p = dot_p; 3426 *dot_p = '\0'; 3427 current_templates = (const templates *) hash_find (op_hash, mnemonic); 3428 } 3429 3430 if (!current_templates) 3431 { 3432 check_suffix: 3433 /* See if we can get a match by trimming off a suffix. */ 3434 switch (mnem_p[-1]) 3435 { 3436 case WORD_MNEM_SUFFIX: 3437 if (intel_syntax && (intel_float_operand (mnemonic) & 2)) 3438 i.suffix = SHORT_MNEM_SUFFIX; 3439 else 3440 case BYTE_MNEM_SUFFIX: 3441 case QWORD_MNEM_SUFFIX: 3442 i.suffix = mnem_p[-1]; 3443 mnem_p[-1] = '\0'; 3444 current_templates = (const templates *) hash_find (op_hash, 3445 mnemonic); 3446 break; 3447 case SHORT_MNEM_SUFFIX: 3448 case LONG_MNEM_SUFFIX: 3449 if (!intel_syntax) 3450 { 3451 i.suffix = mnem_p[-1]; 3452 mnem_p[-1] = '\0'; 3453 current_templates = (const templates *) hash_find (op_hash, 3454 mnemonic); 3455 } 3456 break; 3457 3458 /* Intel Syntax. */ 3459 case 'd': 3460 if (intel_syntax) 3461 { 3462 if (intel_float_operand (mnemonic) == 1) 3463 i.suffix = SHORT_MNEM_SUFFIX; 3464 else 3465 i.suffix = LONG_MNEM_SUFFIX; 3466 mnem_p[-1] = '\0'; 3467 current_templates = (const templates *) hash_find (op_hash, 3468 mnemonic); 3469 } 3470 break; 3471 } 3472 if (!current_templates) 3473 { 3474 as_bad (_("no such instruction: `%s'"), token_start); 3475 return NULL; 3476 } 3477 } 3478 3479 if (current_templates->start->opcode_modifier.jump 3480 || current_templates->start->opcode_modifier.jumpbyte) 3481 { 3482 /* Check for a branch hint. We allow ",pt" and ",pn" for 3483 predict taken and predict not taken respectively. 3484 I'm not sure that branch hints actually do anything on loop 3485 and jcxz insns (JumpByte) for current Pentium4 chips. They 3486 may work in the future and it doesn't hurt to accept them 3487 now. */ 3488 if (l[0] == ',' && l[1] == 'p') 3489 { 3490 if (l[2] == 't') 3491 { 3492 if (!add_prefix (DS_PREFIX_OPCODE)) 3493 return NULL; 3494 l += 3; 3495 } 3496 else if (l[2] == 'n') 3497 { 3498 if (!add_prefix (CS_PREFIX_OPCODE)) 3499 return NULL; 3500 l += 3; 3501 } 3502 } 3503 } 3504 /* Any other comma loses. */ 3505 if (*l == ',') 3506 { 3507 as_bad (_("invalid character %s in mnemonic"), 3508 output_invalid (*l)); 3509 return NULL; 3510 } 3511 3512 /* Check if instruction is supported on specified architecture. */ 3513 supported = 0; 3514 for (t = current_templates->start; t < current_templates->end; ++t) 3515 { 3516 supported |= cpu_flags_match (t); 3517 if (supported == CPU_FLAGS_PERFECT_MATCH) 3518 goto skip; 3519 } 3520 3521 if (!(supported & CPU_FLAGS_64BIT_MATCH)) 3522 { 3523 as_bad (flag_code == CODE_64BIT 3524 ? _("`%s' is not supported in 64-bit mode") 3525 : _("`%s' is only supported in 64-bit mode"), 3526 current_templates->start->name); 3527 return NULL; 3528 } 3529 if (supported != CPU_FLAGS_PERFECT_MATCH) 3530 { 3531 as_bad (_("`%s' is not supported on `%s%s'"), 3532 current_templates->start->name, 3533 cpu_arch_name ? cpu_arch_name : default_arch, 3534 cpu_sub_arch_name ? cpu_sub_arch_name : ""); 3535 return NULL; 3536 } 3537 3538 skip: 3539 if (!cpu_arch_flags.bitfield.cpui386 3540 && (flag_code != CODE_16BIT)) 3541 { 3542 as_warn (_("use .code16 to ensure correct addressing mode")); 3543 } 3544 3545 /* Check for rep/repne without a string (or other allowed) instruction. */ 3546 if (expecting_string_instruction) 3547 { 3548 static templates override; 3549 3550 for (t = current_templates->start; t < current_templates->end; ++t) 3551 if (t->opcode_modifier.repprefixok) 3552 break; 3553 if (t >= current_templates->end) 3554 { 3555 as_bad (_("expecting string instruction after `%s'"), 3556 expecting_string_instruction); 3557 return NULL; 3558 } 3559 for (override.start = t; t < current_templates->end; ++t) 3560 if (!t->opcode_modifier.repprefixok) 3561 break; 3562 override.end = t; 3563 current_templates = &override; 3564 } 3565 3566 return l; 3567 } 3568 3569 static char * 3570 parse_operands (char *l, const char *mnemonic) 3571 { 3572 char *token_start; 3573 3574 /* 1 if operand is pending after ','. */ 3575 unsigned int expecting_operand = 0; 3576 3577 /* Non-zero if operand parens not balanced. */ 3578 unsigned int paren_not_balanced; 3579 3580 while (*l != END_OF_INSN) 3581 { 3582 /* Skip optional white space before operand. */ 3583 if (is_space_char (*l)) 3584 ++l; 3585 if (!is_operand_char (*l) && *l != END_OF_INSN) 3586 { 3587 as_bad (_("invalid character %s before operand %d"), 3588 output_invalid (*l), 3589 i.operands + 1); 3590 return NULL; 3591 } 3592 token_start = l; /* after white space */ 3593 paren_not_balanced = 0; 3594 while (paren_not_balanced || *l != ',') 3595 { 3596 if (*l == END_OF_INSN) 3597 { 3598 if (paren_not_balanced) 3599 { 3600 if (!intel_syntax) 3601 as_bad (_("unbalanced parenthesis in operand %d."), 3602 i.operands + 1); 3603 else 3604 as_bad (_("unbalanced brackets in operand %d."), 3605 i.operands + 1); 3606 return NULL; 3607 } 3608 else 3609 break; /* we are done */ 3610 } 3611 else if (!is_operand_char (*l) && !is_space_char (*l)) 3612 { 3613 as_bad (_("invalid character %s in operand %d"), 3614 output_invalid (*l), 3615 i.operands + 1); 3616 return NULL; 3617 } 3618 if (!intel_syntax) 3619 { 3620 if (*l == '(') 3621 ++paren_not_balanced; 3622 if (*l == ')') 3623 --paren_not_balanced; 3624 } 3625 else 3626 { 3627 if (*l == '[') 3628 ++paren_not_balanced; 3629 if (*l == ']') 3630 --paren_not_balanced; 3631 } 3632 l++; 3633 } 3634 if (l != token_start) 3635 { /* Yes, we've read in another operand. */ 3636 unsigned int operand_ok; 3637 this_operand = i.operands++; 3638 i.types[this_operand].bitfield.unspecified = 1; 3639 if (i.operands > MAX_OPERANDS) 3640 { 3641 as_bad (_("spurious operands; (%d operands/instruction max)"), 3642 MAX_OPERANDS); 3643 return NULL; 3644 } 3645 /* Now parse operand adding info to 'i' as we go along. */ 3646 END_STRING_AND_SAVE (l); 3647 3648 if (intel_syntax) 3649 operand_ok = 3650 i386_intel_operand (token_start, 3651 intel_float_operand (mnemonic)); 3652 else 3653 operand_ok = i386_att_operand (token_start); 3654 3655 RESTORE_END_STRING (l); 3656 if (!operand_ok) 3657 return NULL; 3658 } 3659 else 3660 { 3661 if (expecting_operand) 3662 { 3663 expecting_operand_after_comma: 3664 as_bad (_("expecting operand after ','; got nothing")); 3665 return NULL; 3666 } 3667 if (*l == ',') 3668 { 3669 as_bad (_("expecting operand before ','; got nothing")); 3670 return NULL; 3671 } 3672 } 3673 3674 /* Now *l must be either ',' or END_OF_INSN. */ 3675 if (*l == ',') 3676 { 3677 if (*++l == END_OF_INSN) 3678 { 3679 /* Just skip it, if it's \n complain. */ 3680 goto expecting_operand_after_comma; 3681 } 3682 expecting_operand = 1; 3683 } 3684 } 3685 return l; 3686 } 3687 3688 static void 3689 swap_2_operands (int xchg1, int xchg2) 3690 { 3691 union i386_op temp_op; 3692 i386_operand_type temp_type; 3693 enum bfd_reloc_code_real temp_reloc; 3694 3695 temp_type = i.types[xchg2]; 3696 i.types[xchg2] = i.types[xchg1]; 3697 i.types[xchg1] = temp_type; 3698 temp_op = i.op[xchg2]; 3699 i.op[xchg2] = i.op[xchg1]; 3700 i.op[xchg1] = temp_op; 3701 temp_reloc = i.reloc[xchg2]; 3702 i.reloc[xchg2] = i.reloc[xchg1]; 3703 i.reloc[xchg1] = temp_reloc; 3704 } 3705 3706 static void 3707 swap_operands (void) 3708 { 3709 switch (i.operands) 3710 { 3711 case 5: 3712 case 4: 3713 swap_2_operands (1, i.operands - 2); 3714 case 3: 3715 case 2: 3716 swap_2_operands (0, i.operands - 1); 3717 break; 3718 default: 3719 abort (); 3720 } 3721 3722 if (i.mem_operands == 2) 3723 { 3724 const seg_entry *temp_seg; 3725 temp_seg = i.seg[0]; 3726 i.seg[0] = i.seg[1]; 3727 i.seg[1] = temp_seg; 3728 } 3729 } 3730 3731 /* Try to ensure constant immediates are represented in the smallest 3732 opcode possible. */ 3733 static void 3734 optimize_imm (void) 3735 { 3736 char guess_suffix = 0; 3737 int op; 3738 3739 if (i.suffix) 3740 guess_suffix = i.suffix; 3741 else if (i.reg_operands) 3742 { 3743 /* Figure out a suffix from the last register operand specified. 3744 We can't do this properly yet, ie. excluding InOutPortReg, 3745 but the following works for instructions with immediates. 3746 In any case, we can't set i.suffix yet. */ 3747 for (op = i.operands; --op >= 0;) 3748 if (i.types[op].bitfield.reg8) 3749 { 3750 guess_suffix = BYTE_MNEM_SUFFIX; 3751 break; 3752 } 3753 else if (i.types[op].bitfield.reg16) 3754 { 3755 guess_suffix = WORD_MNEM_SUFFIX; 3756 break; 3757 } 3758 else if (i.types[op].bitfield.reg32) 3759 { 3760 guess_suffix = LONG_MNEM_SUFFIX; 3761 break; 3762 } 3763 else if (i.types[op].bitfield.reg64) 3764 { 3765 guess_suffix = QWORD_MNEM_SUFFIX; 3766 break; 3767 } 3768 } 3769 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 3770 guess_suffix = WORD_MNEM_SUFFIX; 3771 3772 for (op = i.operands; --op >= 0;) 3773 if (operand_type_check (i.types[op], imm)) 3774 { 3775 switch (i.op[op].imms->X_op) 3776 { 3777 case O_constant: 3778 /* If a suffix is given, this operand may be shortened. */ 3779 switch (guess_suffix) 3780 { 3781 case LONG_MNEM_SUFFIX: 3782 i.types[op].bitfield.imm32 = 1; 3783 i.types[op].bitfield.imm64 = 1; 3784 break; 3785 case WORD_MNEM_SUFFIX: 3786 i.types[op].bitfield.imm16 = 1; 3787 i.types[op].bitfield.imm32 = 1; 3788 i.types[op].bitfield.imm32s = 1; 3789 i.types[op].bitfield.imm64 = 1; 3790 break; 3791 case BYTE_MNEM_SUFFIX: 3792 i.types[op].bitfield.imm8 = 1; 3793 i.types[op].bitfield.imm8s = 1; 3794 i.types[op].bitfield.imm16 = 1; 3795 i.types[op].bitfield.imm32 = 1; 3796 i.types[op].bitfield.imm32s = 1; 3797 i.types[op].bitfield.imm64 = 1; 3798 break; 3799 } 3800 3801 /* If this operand is at most 16 bits, convert it 3802 to a signed 16 bit number before trying to see 3803 whether it will fit in an even smaller size. 3804 This allows a 16-bit operand such as $0xffe0 to 3805 be recognised as within Imm8S range. */ 3806 if ((i.types[op].bitfield.imm16) 3807 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) 3808 { 3809 i.op[op].imms->X_add_number = 3810 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 3811 } 3812 if ((i.types[op].bitfield.imm32) 3813 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) 3814 == 0)) 3815 { 3816 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number 3817 ^ ((offsetT) 1 << 31)) 3818 - ((offsetT) 1 << 31)); 3819 } 3820 i.types[op] 3821 = operand_type_or (i.types[op], 3822 smallest_imm_type (i.op[op].imms->X_add_number)); 3823 3824 /* We must avoid matching of Imm32 templates when 64bit 3825 only immediate is available. */ 3826 if (guess_suffix == QWORD_MNEM_SUFFIX) 3827 i.types[op].bitfield.imm32 = 0; 3828 break; 3829 3830 case O_absent: 3831 case O_register: 3832 abort (); 3833 3834 /* Symbols and expressions. */ 3835 default: 3836 /* Convert symbolic operand to proper sizes for matching, but don't 3837 prevent matching a set of insns that only supports sizes other 3838 than those matching the insn suffix. */ 3839 { 3840 i386_operand_type mask, allowed; 3841 const insn_template *t; 3842 3843 operand_type_set (&mask, 0); 3844 operand_type_set (&allowed, 0); 3845 3846 for (t = current_templates->start; 3847 t < current_templates->end; 3848 ++t) 3849 allowed = operand_type_or (allowed, 3850 t->operand_types[op]); 3851 switch (guess_suffix) 3852 { 3853 case QWORD_MNEM_SUFFIX: 3854 mask.bitfield.imm64 = 1; 3855 mask.bitfield.imm32s = 1; 3856 break; 3857 case LONG_MNEM_SUFFIX: 3858 mask.bitfield.imm32 = 1; 3859 break; 3860 case WORD_MNEM_SUFFIX: 3861 mask.bitfield.imm16 = 1; 3862 break; 3863 case BYTE_MNEM_SUFFIX: 3864 mask.bitfield.imm8 = 1; 3865 break; 3866 default: 3867 break; 3868 } 3869 allowed = operand_type_and (mask, allowed); 3870 if (!operand_type_all_zero (&allowed)) 3871 i.types[op] = operand_type_and (i.types[op], mask); 3872 } 3873 break; 3874 } 3875 } 3876 } 3877 3878 /* Try to use the smallest displacement type too. */ 3879 static void 3880 optimize_disp (void) 3881 { 3882 int op; 3883 3884 for (op = i.operands; --op >= 0;) 3885 if (operand_type_check (i.types[op], disp)) 3886 { 3887 if (i.op[op].disps->X_op == O_constant) 3888 { 3889 offsetT op_disp = i.op[op].disps->X_add_number; 3890 3891 if (i.types[op].bitfield.disp16 3892 && (op_disp & ~(offsetT) 0xffff) == 0) 3893 { 3894 /* If this operand is at most 16 bits, convert 3895 to a signed 16 bit number and don't use 64bit 3896 displacement. */ 3897 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); 3898 i.types[op].bitfield.disp64 = 0; 3899 } 3900 if (i.types[op].bitfield.disp32 3901 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) 3902 { 3903 /* If this operand is at most 32 bits, convert 3904 to a signed 32 bit number and don't use 64bit 3905 displacement. */ 3906 op_disp &= (((offsetT) 2 << 31) - 1); 3907 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); 3908 i.types[op].bitfield.disp64 = 0; 3909 } 3910 if (!op_disp && i.types[op].bitfield.baseindex) 3911 { 3912 i.types[op].bitfield.disp8 = 0; 3913 i.types[op].bitfield.disp16 = 0; 3914 i.types[op].bitfield.disp32 = 0; 3915 i.types[op].bitfield.disp32s = 0; 3916 i.types[op].bitfield.disp64 = 0; 3917 i.op[op].disps = 0; 3918 i.disp_operands--; 3919 } 3920 else if (flag_code == CODE_64BIT) 3921 { 3922 if (fits_in_signed_long (op_disp)) 3923 { 3924 i.types[op].bitfield.disp64 = 0; 3925 i.types[op].bitfield.disp32s = 1; 3926 } 3927 if (i.prefix[ADDR_PREFIX] 3928 && fits_in_unsigned_long (op_disp)) 3929 i.types[op].bitfield.disp32 = 1; 3930 } 3931 if ((i.types[op].bitfield.disp32 3932 || i.types[op].bitfield.disp32s 3933 || i.types[op].bitfield.disp16) 3934 && fits_in_signed_byte (op_disp)) 3935 i.types[op].bitfield.disp8 = 1; 3936 } 3937 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 3938 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) 3939 { 3940 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, 3941 i.op[op].disps, 0, i.reloc[op]); 3942 i.types[op].bitfield.disp8 = 0; 3943 i.types[op].bitfield.disp16 = 0; 3944 i.types[op].bitfield.disp32 = 0; 3945 i.types[op].bitfield.disp32s = 0; 3946 i.types[op].bitfield.disp64 = 0; 3947 } 3948 else 3949 /* We only support 64bit displacement on constants. */ 3950 i.types[op].bitfield.disp64 = 0; 3951 } 3952 } 3953 3954 /* Check if operands are valid for the instruction. */ 3955 3956 static int 3957 check_VecOperands (const insn_template *t) 3958 { 3959 /* Without VSIB byte, we can't have a vector register for index. */ 3960 if (!t->opcode_modifier.vecsib 3961 && i.index_reg 3962 && (i.index_reg->reg_type.bitfield.regxmm 3963 || i.index_reg->reg_type.bitfield.regymm)) 3964 { 3965 i.error = unsupported_vector_index_register; 3966 return 1; 3967 } 3968 3969 /* For VSIB byte, we need a vector register for index and no PC 3970 relative addressing is allowed. */ 3971 if (t->opcode_modifier.vecsib 3972 && (!i.index_reg 3973 || !((t->opcode_modifier.vecsib == VecSIB128 3974 && i.index_reg->reg_type.bitfield.regxmm) 3975 || (t->opcode_modifier.vecsib == VecSIB256 3976 && i.index_reg->reg_type.bitfield.regymm)) 3977 || (i.base_reg && i.base_reg->reg_num == RegRip))) 3978 { 3979 i.error = invalid_vsib_address; 3980 return 1; 3981 } 3982 3983 return 0; 3984 } 3985 3986 /* Check if operands are valid for the instruction. Update VEX 3987 operand types. */ 3988 3989 static int 3990 VEX_check_operands (const insn_template *t) 3991 { 3992 if (!t->opcode_modifier.vex) 3993 return 0; 3994 3995 /* Only check VEX_Imm4, which must be the first operand. */ 3996 if (t->operand_types[0].bitfield.vec_imm4) 3997 { 3998 if (i.op[0].imms->X_op != O_constant 3999 || !fits_in_imm4 (i.op[0].imms->X_add_number)) 4000 { 4001 i.error = bad_imm4; 4002 return 1; 4003 } 4004 4005 /* Turn off Imm8 so that update_imm won't complain. */ 4006 i.types[0] = vec_imm4; 4007 } 4008 4009 return 0; 4010 } 4011 4012 static const insn_template * 4013 match_template (void) 4014 { 4015 /* Points to template once we've found it. */ 4016 const insn_template *t; 4017 i386_operand_type overlap0, overlap1, overlap2, overlap3; 4018 i386_operand_type overlap4; 4019 unsigned int found_reverse_match; 4020 i386_opcode_modifier suffix_check; 4021 i386_operand_type operand_types [MAX_OPERANDS]; 4022 int addr_prefix_disp; 4023 unsigned int j; 4024 unsigned int found_cpu_match; 4025 unsigned int check_register; 4026 4027 #if MAX_OPERANDS != 5 4028 # error "MAX_OPERANDS must be 5." 4029 #endif 4030 4031 found_reverse_match = 0; 4032 addr_prefix_disp = -1; 4033 4034 memset (&suffix_check, 0, sizeof (suffix_check)); 4035 if (i.suffix == BYTE_MNEM_SUFFIX) 4036 suffix_check.no_bsuf = 1; 4037 else if (i.suffix == WORD_MNEM_SUFFIX) 4038 suffix_check.no_wsuf = 1; 4039 else if (i.suffix == SHORT_MNEM_SUFFIX) 4040 suffix_check.no_ssuf = 1; 4041 else if (i.suffix == LONG_MNEM_SUFFIX) 4042 suffix_check.no_lsuf = 1; 4043 else if (i.suffix == QWORD_MNEM_SUFFIX) 4044 suffix_check.no_qsuf = 1; 4045 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) 4046 suffix_check.no_ldsuf = 1; 4047 4048 /* Must have right number of operands. */ 4049 i.error = number_of_operands_mismatch; 4050 4051 for (t = current_templates->start; t < current_templates->end; t++) 4052 { 4053 addr_prefix_disp = -1; 4054 4055 if (i.operands != t->operands) 4056 continue; 4057 4058 /* Check processor support. */ 4059 i.error = unsupported; 4060 found_cpu_match = (cpu_flags_match (t) 4061 == CPU_FLAGS_PERFECT_MATCH); 4062 if (!found_cpu_match) 4063 continue; 4064 4065 /* Check old gcc support. */ 4066 i.error = old_gcc_only; 4067 if (!old_gcc && t->opcode_modifier.oldgcc) 4068 continue; 4069 4070 /* Check AT&T mnemonic. */ 4071 i.error = unsupported_with_intel_mnemonic; 4072 if (intel_mnemonic && t->opcode_modifier.attmnemonic) 4073 continue; 4074 4075 /* Check AT&T/Intel syntax. */ 4076 i.error = unsupported_syntax; 4077 if ((intel_syntax && t->opcode_modifier.attsyntax) 4078 || (!intel_syntax && t->opcode_modifier.intelsyntax)) 4079 continue; 4080 4081 /* Check the suffix, except for some instructions in intel mode. */ 4082 i.error = invalid_instruction_suffix; 4083 if ((!intel_syntax || !t->opcode_modifier.ignoresize) 4084 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) 4085 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) 4086 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) 4087 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) 4088 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) 4089 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) 4090 continue; 4091 4092 if (!operand_size_match (t)) 4093 continue; 4094 4095 for (j = 0; j < MAX_OPERANDS; j++) 4096 operand_types[j] = t->operand_types[j]; 4097 4098 /* In general, don't allow 64-bit operands in 32-bit mode. */ 4099 if (i.suffix == QWORD_MNEM_SUFFIX 4100 && flag_code != CODE_64BIT 4101 && (intel_syntax 4102 ? (!t->opcode_modifier.ignoresize 4103 && !intel_float_operand (t->name)) 4104 : intel_float_operand (t->name) != 2) 4105 && ((!operand_types[0].bitfield.regmmx 4106 && !operand_types[0].bitfield.regxmm 4107 && !operand_types[0].bitfield.regymm) 4108 || (!operand_types[t->operands > 1].bitfield.regmmx 4109 && !!operand_types[t->operands > 1].bitfield.regxmm 4110 && !!operand_types[t->operands > 1].bitfield.regymm)) 4111 && (t->base_opcode != 0x0fc7 4112 || t->extension_opcode != 1 /* cmpxchg8b */)) 4113 continue; 4114 4115 /* In general, don't allow 32-bit operands on pre-386. */ 4116 else if (i.suffix == LONG_MNEM_SUFFIX 4117 && !cpu_arch_flags.bitfield.cpui386 4118 && (intel_syntax 4119 ? (!t->opcode_modifier.ignoresize 4120 && !intel_float_operand (t->name)) 4121 : intel_float_operand (t->name) != 2) 4122 && ((!operand_types[0].bitfield.regmmx 4123 && !operand_types[0].bitfield.regxmm) 4124 || (!operand_types[t->operands > 1].bitfield.regmmx 4125 && !!operand_types[t->operands > 1].bitfield.regxmm))) 4126 continue; 4127 4128 /* Do not verify operands when there are none. */ 4129 else 4130 { 4131 if (!t->operands) 4132 /* We've found a match; break out of loop. */ 4133 break; 4134 } 4135 4136 /* Address size prefix will turn Disp64/Disp32/Disp16 operand 4137 into Disp32/Disp16/Disp32 operand. */ 4138 if (i.prefix[ADDR_PREFIX] != 0) 4139 { 4140 /* There should be only one Disp operand. */ 4141 switch (flag_code) 4142 { 4143 case CODE_16BIT: 4144 for (j = 0; j < MAX_OPERANDS; j++) 4145 { 4146 if (operand_types[j].bitfield.disp16) 4147 { 4148 addr_prefix_disp = j; 4149 operand_types[j].bitfield.disp32 = 1; 4150 operand_types[j].bitfield.disp16 = 0; 4151 break; 4152 } 4153 } 4154 break; 4155 case CODE_32BIT: 4156 for (j = 0; j < MAX_OPERANDS; j++) 4157 { 4158 if (operand_types[j].bitfield.disp32) 4159 { 4160 addr_prefix_disp = j; 4161 operand_types[j].bitfield.disp32 = 0; 4162 operand_types[j].bitfield.disp16 = 1; 4163 break; 4164 } 4165 } 4166 break; 4167 case CODE_64BIT: 4168 for (j = 0; j < MAX_OPERANDS; j++) 4169 { 4170 if (operand_types[j].bitfield.disp64) 4171 { 4172 addr_prefix_disp = j; 4173 operand_types[j].bitfield.disp64 = 0; 4174 operand_types[j].bitfield.disp32 = 1; 4175 break; 4176 } 4177 } 4178 break; 4179 } 4180 } 4181 4182 /* We check register size if needed. */ 4183 check_register = t->opcode_modifier.checkregsize; 4184 overlap0 = operand_type_and (i.types[0], operand_types[0]); 4185 switch (t->operands) 4186 { 4187 case 1: 4188 if (!operand_type_match (overlap0, i.types[0])) 4189 continue; 4190 break; 4191 case 2: 4192 /* xchg %eax, %eax is a special case. It is an aliase for nop 4193 only in 32bit mode and we can use opcode 0x90. In 64bit 4194 mode, we can't use 0x90 for xchg %eax, %eax since it should 4195 zero-extend %eax to %rax. */ 4196 if (flag_code == CODE_64BIT 4197 && t->base_opcode == 0x90 4198 && operand_type_equal (&i.types [0], &acc32) 4199 && operand_type_equal (&i.types [1], &acc32)) 4200 continue; 4201 if (i.swap_operand) 4202 { 4203 /* If we swap operand in encoding, we either match 4204 the next one or reverse direction of operands. */ 4205 if (t->opcode_modifier.s) 4206 continue; 4207 else if (t->opcode_modifier.d) 4208 goto check_reverse; 4209 } 4210 4211 case 3: 4212 /* If we swap operand in encoding, we match the next one. */ 4213 if (i.swap_operand && t->opcode_modifier.s) 4214 continue; 4215 case 4: 4216 case 5: 4217 overlap1 = operand_type_and (i.types[1], operand_types[1]); 4218 if (!operand_type_match (overlap0, i.types[0]) 4219 || !operand_type_match (overlap1, i.types[1]) 4220 || (check_register 4221 && !operand_type_register_match (overlap0, i.types[0], 4222 operand_types[0], 4223 overlap1, i.types[1], 4224 operand_types[1]))) 4225 { 4226 /* Check if other direction is valid ... */ 4227 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) 4228 continue; 4229 4230 check_reverse: 4231 /* Try reversing direction of operands. */ 4232 overlap0 = operand_type_and (i.types[0], operand_types[1]); 4233 overlap1 = operand_type_and (i.types[1], operand_types[0]); 4234 if (!operand_type_match (overlap0, i.types[0]) 4235 || !operand_type_match (overlap1, i.types[1]) 4236 || (check_register 4237 && !operand_type_register_match (overlap0, 4238 i.types[0], 4239 operand_types[1], 4240 overlap1, 4241 i.types[1], 4242 operand_types[0]))) 4243 { 4244 /* Does not match either direction. */ 4245 continue; 4246 } 4247 /* found_reverse_match holds which of D or FloatDR 4248 we've found. */ 4249 if (t->opcode_modifier.d) 4250 found_reverse_match = Opcode_D; 4251 else if (t->opcode_modifier.floatd) 4252 found_reverse_match = Opcode_FloatD; 4253 else 4254 found_reverse_match = 0; 4255 if (t->opcode_modifier.floatr) 4256 found_reverse_match |= Opcode_FloatR; 4257 } 4258 else 4259 { 4260 /* Found a forward 2 operand match here. */ 4261 switch (t->operands) 4262 { 4263 case 5: 4264 overlap4 = operand_type_and (i.types[4], 4265 operand_types[4]); 4266 case 4: 4267 overlap3 = operand_type_and (i.types[3], 4268 operand_types[3]); 4269 case 3: 4270 overlap2 = operand_type_and (i.types[2], 4271 operand_types[2]); 4272 break; 4273 } 4274 4275 switch (t->operands) 4276 { 4277 case 5: 4278 if (!operand_type_match (overlap4, i.types[4]) 4279 || !operand_type_register_match (overlap3, 4280 i.types[3], 4281 operand_types[3], 4282 overlap4, 4283 i.types[4], 4284 operand_types[4])) 4285 continue; 4286 case 4: 4287 if (!operand_type_match (overlap3, i.types[3]) 4288 || (check_register 4289 && !operand_type_register_match (overlap2, 4290 i.types[2], 4291 operand_types[2], 4292 overlap3, 4293 i.types[3], 4294 operand_types[3]))) 4295 continue; 4296 case 3: 4297 /* Here we make use of the fact that there are no 4298 reverse match 3 operand instructions, and all 3 4299 operand instructions only need to be checked for 4300 register consistency between operands 2 and 3. */ 4301 if (!operand_type_match (overlap2, i.types[2]) 4302 || (check_register 4303 && !operand_type_register_match (overlap1, 4304 i.types[1], 4305 operand_types[1], 4306 overlap2, 4307 i.types[2], 4308 operand_types[2]))) 4309 continue; 4310 break; 4311 } 4312 } 4313 /* Found either forward/reverse 2, 3 or 4 operand match here: 4314 slip through to break. */ 4315 } 4316 if (!found_cpu_match) 4317 { 4318 found_reverse_match = 0; 4319 continue; 4320 } 4321 4322 /* Check if vector operands are valid. */ 4323 if (check_VecOperands (t)) 4324 continue; 4325 4326 /* Check if VEX operands are valid. */ 4327 if (VEX_check_operands (t)) 4328 continue; 4329 4330 /* We've found a match; break out of loop. */ 4331 break; 4332 } 4333 4334 if (t == current_templates->end) 4335 { 4336 /* We found no match. */ 4337 const char *err_msg; 4338 switch (i.error) 4339 { 4340 default: 4341 abort (); 4342 case operand_size_mismatch: 4343 err_msg = _("operand size mismatch"); 4344 break; 4345 case operand_type_mismatch: 4346 err_msg = _("operand type mismatch"); 4347 break; 4348 case register_type_mismatch: 4349 err_msg = _("register type mismatch"); 4350 break; 4351 case number_of_operands_mismatch: 4352 err_msg = _("number of operands mismatch"); 4353 break; 4354 case invalid_instruction_suffix: 4355 err_msg = _("invalid instruction suffix"); 4356 break; 4357 case bad_imm4: 4358 err_msg = _("Imm4 isn't the first operand"); 4359 break; 4360 case old_gcc_only: 4361 err_msg = _("only supported with old gcc"); 4362 break; 4363 case unsupported_with_intel_mnemonic: 4364 err_msg = _("unsupported with Intel mnemonic"); 4365 break; 4366 case unsupported_syntax: 4367 err_msg = _("unsupported syntax"); 4368 break; 4369 case unsupported: 4370 as_bad (_("unsupported instruction `%s'"), 4371 current_templates->start->name); 4372 return NULL; 4373 case invalid_vsib_address: 4374 err_msg = _("invalid VSIB address"); 4375 break; 4376 case unsupported_vector_index_register: 4377 err_msg = _("unsupported vector index register"); 4378 break; 4379 } 4380 as_bad (_("%s for `%s'"), err_msg, 4381 current_templates->start->name); 4382 return NULL; 4383 } 4384 4385 if (!quiet_warnings) 4386 { 4387 if (!intel_syntax 4388 && (i.types[0].bitfield.jumpabsolute 4389 != operand_types[0].bitfield.jumpabsolute)) 4390 { 4391 as_warn (_("indirect %s without `*'"), t->name); 4392 } 4393 4394 if (t->opcode_modifier.isprefix 4395 && t->opcode_modifier.ignoresize) 4396 { 4397 /* Warn them that a data or address size prefix doesn't 4398 affect assembly of the next line of code. */ 4399 as_warn (_("stand-alone `%s' prefix"), t->name); 4400 } 4401 } 4402 4403 /* Copy the template we found. */ 4404 i.tm = *t; 4405 4406 if (addr_prefix_disp != -1) 4407 i.tm.operand_types[addr_prefix_disp] 4408 = operand_types[addr_prefix_disp]; 4409 4410 if (found_reverse_match) 4411 { 4412 /* If we found a reverse match we must alter the opcode 4413 direction bit. found_reverse_match holds bits to change 4414 (different for int & float insns). */ 4415 4416 i.tm.base_opcode ^= found_reverse_match; 4417 4418 i.tm.operand_types[0] = operand_types[1]; 4419 i.tm.operand_types[1] = operand_types[0]; 4420 } 4421 4422 return t; 4423 } 4424 4425 static int 4426 check_string (void) 4427 { 4428 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; 4429 if (i.tm.operand_types[mem_op].bitfield.esseg) 4430 { 4431 if (i.seg[0] != NULL && i.seg[0] != &es) 4432 { 4433 as_bad (_("`%s' operand %d must use `%ses' segment"), 4434 i.tm.name, 4435 mem_op + 1, 4436 register_prefix); 4437 return 0; 4438 } 4439 /* There's only ever one segment override allowed per instruction. 4440 This instruction possibly has a legal segment override on the 4441 second operand, so copy the segment to where non-string 4442 instructions store it, allowing common code. */ 4443 i.seg[0] = i.seg[1]; 4444 } 4445 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) 4446 { 4447 if (i.seg[1] != NULL && i.seg[1] != &es) 4448 { 4449 as_bad (_("`%s' operand %d must use `%ses' segment"), 4450 i.tm.name, 4451 mem_op + 2, 4452 register_prefix); 4453 return 0; 4454 } 4455 } 4456 return 1; 4457 } 4458 4459 static int 4460 process_suffix (void) 4461 { 4462 /* If matched instruction specifies an explicit instruction mnemonic 4463 suffix, use it. */ 4464 if (i.tm.opcode_modifier.size16) 4465 i.suffix = WORD_MNEM_SUFFIX; 4466 else if (i.tm.opcode_modifier.size32) 4467 i.suffix = LONG_MNEM_SUFFIX; 4468 else if (i.tm.opcode_modifier.size64) 4469 i.suffix = QWORD_MNEM_SUFFIX; 4470 else if (i.reg_operands) 4471 { 4472 /* If there's no instruction mnemonic suffix we try to invent one 4473 based on register operands. */ 4474 if (!i.suffix) 4475 { 4476 /* We take i.suffix from the last register operand specified, 4477 Destination register type is more significant than source 4478 register type. crc32 in SSE4.2 prefers source register 4479 type. */ 4480 if (i.tm.base_opcode == 0xf20f38f1) 4481 { 4482 if (i.types[0].bitfield.reg16) 4483 i.suffix = WORD_MNEM_SUFFIX; 4484 else if (i.types[0].bitfield.reg32) 4485 i.suffix = LONG_MNEM_SUFFIX; 4486 else if (i.types[0].bitfield.reg64) 4487 i.suffix = QWORD_MNEM_SUFFIX; 4488 } 4489 else if (i.tm.base_opcode == 0xf20f38f0) 4490 { 4491 if (i.types[0].bitfield.reg8) 4492 i.suffix = BYTE_MNEM_SUFFIX; 4493 } 4494 4495 if (!i.suffix) 4496 { 4497 int op; 4498 4499 if (i.tm.base_opcode == 0xf20f38f1 4500 || i.tm.base_opcode == 0xf20f38f0) 4501 { 4502 /* We have to know the operand size for crc32. */ 4503 as_bad (_("ambiguous memory operand size for `%s`"), 4504 i.tm.name); 4505 return 0; 4506 } 4507 4508 for (op = i.operands; --op >= 0;) 4509 if (!i.tm.operand_types[op].bitfield.inoutportreg) 4510 { 4511 if (i.types[op].bitfield.reg8) 4512 { 4513 i.suffix = BYTE_MNEM_SUFFIX; 4514 break; 4515 } 4516 else if (i.types[op].bitfield.reg16) 4517 { 4518 i.suffix = WORD_MNEM_SUFFIX; 4519 break; 4520 } 4521 else if (i.types[op].bitfield.reg32) 4522 { 4523 i.suffix = LONG_MNEM_SUFFIX; 4524 break; 4525 } 4526 else if (i.types[op].bitfield.reg64) 4527 { 4528 i.suffix = QWORD_MNEM_SUFFIX; 4529 break; 4530 } 4531 } 4532 } 4533 } 4534 else if (i.suffix == BYTE_MNEM_SUFFIX) 4535 { 4536 if (intel_syntax 4537 && i.tm.opcode_modifier.ignoresize 4538 && i.tm.opcode_modifier.no_bsuf) 4539 i.suffix = 0; 4540 else if (!check_byte_reg ()) 4541 return 0; 4542 } 4543 else if (i.suffix == LONG_MNEM_SUFFIX) 4544 { 4545 if (intel_syntax 4546 && i.tm.opcode_modifier.ignoresize 4547 && i.tm.opcode_modifier.no_lsuf) 4548 i.suffix = 0; 4549 else if (!check_long_reg ()) 4550 return 0; 4551 } 4552 else if (i.suffix == QWORD_MNEM_SUFFIX) 4553 { 4554 if (intel_syntax 4555 && i.tm.opcode_modifier.ignoresize 4556 && i.tm.opcode_modifier.no_qsuf) 4557 i.suffix = 0; 4558 else if (!check_qword_reg ()) 4559 return 0; 4560 } 4561 else if (i.suffix == WORD_MNEM_SUFFIX) 4562 { 4563 if (intel_syntax 4564 && i.tm.opcode_modifier.ignoresize 4565 && i.tm.opcode_modifier.no_wsuf) 4566 i.suffix = 0; 4567 else if (!check_word_reg ()) 4568 return 0; 4569 } 4570 else if (i.suffix == XMMWORD_MNEM_SUFFIX 4571 || i.suffix == YMMWORD_MNEM_SUFFIX) 4572 { 4573 /* Skip if the instruction has x/y suffix. match_template 4574 should check if it is a valid suffix. */ 4575 } 4576 else if (intel_syntax && i.tm.opcode_modifier.ignoresize) 4577 /* Do nothing if the instruction is going to ignore the prefix. */ 4578 ; 4579 else 4580 abort (); 4581 } 4582 else if (i.tm.opcode_modifier.defaultsize 4583 && !i.suffix 4584 /* exclude fldenv/frstor/fsave/fstenv */ 4585 && i.tm.opcode_modifier.no_ssuf) 4586 { 4587 i.suffix = stackop_size; 4588 } 4589 else if (intel_syntax 4590 && !i.suffix 4591 && (i.tm.operand_types[0].bitfield.jumpabsolute 4592 || i.tm.opcode_modifier.jumpbyte 4593 || i.tm.opcode_modifier.jumpintersegment 4594 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ 4595 && i.tm.extension_opcode <= 3))) 4596 { 4597 switch (flag_code) 4598 { 4599 case CODE_64BIT: 4600 if (!i.tm.opcode_modifier.no_qsuf) 4601 { 4602 i.suffix = QWORD_MNEM_SUFFIX; 4603 break; 4604 } 4605 case CODE_32BIT: 4606 if (!i.tm.opcode_modifier.no_lsuf) 4607 i.suffix = LONG_MNEM_SUFFIX; 4608 break; 4609 case CODE_16BIT: 4610 if (!i.tm.opcode_modifier.no_wsuf) 4611 i.suffix = WORD_MNEM_SUFFIX; 4612 break; 4613 } 4614 } 4615 4616 if (!i.suffix) 4617 { 4618 if (!intel_syntax) 4619 { 4620 if (i.tm.opcode_modifier.w) 4621 { 4622 as_bad (_("no instruction mnemonic suffix given and " 4623 "no register operands; can't size instruction")); 4624 return 0; 4625 } 4626 } 4627 else 4628 { 4629 unsigned int suffixes; 4630 4631 suffixes = !i.tm.opcode_modifier.no_bsuf; 4632 if (!i.tm.opcode_modifier.no_wsuf) 4633 suffixes |= 1 << 1; 4634 if (!i.tm.opcode_modifier.no_lsuf) 4635 suffixes |= 1 << 2; 4636 if (!i.tm.opcode_modifier.no_ldsuf) 4637 suffixes |= 1 << 3; 4638 if (!i.tm.opcode_modifier.no_ssuf) 4639 suffixes |= 1 << 4; 4640 if (!i.tm.opcode_modifier.no_qsuf) 4641 suffixes |= 1 << 5; 4642 4643 /* There are more than suffix matches. */ 4644 if (i.tm.opcode_modifier.w 4645 || ((suffixes & (suffixes - 1)) 4646 && !i.tm.opcode_modifier.defaultsize 4647 && !i.tm.opcode_modifier.ignoresize)) 4648 { 4649 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 4650 return 0; 4651 } 4652 } 4653 } 4654 4655 /* Change the opcode based on the operand size given by i.suffix; 4656 We don't need to change things for byte insns. */ 4657 4658 if (i.suffix 4659 && i.suffix != BYTE_MNEM_SUFFIX 4660 && i.suffix != XMMWORD_MNEM_SUFFIX 4661 && i.suffix != YMMWORD_MNEM_SUFFIX) 4662 { 4663 /* It's not a byte, select word/dword operation. */ 4664 if (i.tm.opcode_modifier.w) 4665 { 4666 if (i.tm.opcode_modifier.shortform) 4667 i.tm.base_opcode |= 8; 4668 else 4669 i.tm.base_opcode |= 1; 4670 } 4671 4672 /* Now select between word & dword operations via the operand 4673 size prefix, except for instructions that will ignore this 4674 prefix anyway. */ 4675 if (i.tm.opcode_modifier.addrprefixop0) 4676 { 4677 /* The address size override prefix changes the size of the 4678 first operand. */ 4679 if ((flag_code == CODE_32BIT 4680 && i.op->regs[0].reg_type.bitfield.reg16) 4681 || (flag_code != CODE_32BIT 4682 && i.op->regs[0].reg_type.bitfield.reg32)) 4683 if (!add_prefix (ADDR_PREFIX_OPCODE)) 4684 return 0; 4685 } 4686 else if (i.suffix != QWORD_MNEM_SUFFIX 4687 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX 4688 && !i.tm.opcode_modifier.ignoresize 4689 && !i.tm.opcode_modifier.floatmf 4690 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) 4691 || (flag_code == CODE_64BIT 4692 && i.tm.opcode_modifier.jumpbyte))) 4693 { 4694 unsigned int prefix = DATA_PREFIX_OPCODE; 4695 4696 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ 4697 prefix = ADDR_PREFIX_OPCODE; 4698 4699 if (!add_prefix (prefix)) 4700 return 0; 4701 } 4702 4703 /* Set mode64 for an operand. */ 4704 if (i.suffix == QWORD_MNEM_SUFFIX 4705 && flag_code == CODE_64BIT 4706 && !i.tm.opcode_modifier.norex64) 4707 { 4708 /* Special case for xchg %rax,%rax. It is NOP and doesn't 4709 need rex64. cmpxchg8b is also a special case. */ 4710 if (! (i.operands == 2 4711 && i.tm.base_opcode == 0x90 4712 && i.tm.extension_opcode == None 4713 && operand_type_equal (&i.types [0], &acc64) 4714 && operand_type_equal (&i.types [1], &acc64)) 4715 && ! (i.operands == 1 4716 && i.tm.base_opcode == 0xfc7 4717 && i.tm.extension_opcode == 1 4718 && !operand_type_check (i.types [0], reg) 4719 && operand_type_check (i.types [0], anymem))) 4720 i.rex |= REX_W; 4721 } 4722 4723 /* Size floating point instruction. */ 4724 if (i.suffix == LONG_MNEM_SUFFIX) 4725 if (i.tm.opcode_modifier.floatmf) 4726 i.tm.base_opcode ^= 4; 4727 } 4728 4729 return 1; 4730 } 4731 4732 static int 4733 check_byte_reg (void) 4734 { 4735 int op; 4736 4737 for (op = i.operands; --op >= 0;) 4738 { 4739 /* If this is an eight bit register, it's OK. If it's the 16 or 4740 32 bit version of an eight bit register, we will just use the 4741 low portion, and that's OK too. */ 4742 if (i.types[op].bitfield.reg8) 4743 continue; 4744 4745 /* crc32 doesn't generate this warning. */ 4746 if (i.tm.base_opcode == 0xf20f38f0) 4747 continue; 4748 4749 if ((i.types[op].bitfield.reg16 4750 || i.types[op].bitfield.reg32 4751 || i.types[op].bitfield.reg64) 4752 && i.op[op].regs->reg_num < 4) 4753 { 4754 /* Prohibit these changes in the 64bit mode, since the 4755 lowering is more complicated. */ 4756 if (flag_code == CODE_64BIT 4757 && !i.tm.operand_types[op].bitfield.inoutportreg) 4758 { 4759 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 4760 register_prefix, i.op[op].regs->reg_name, 4761 i.suffix); 4762 return 0; 4763 } 4764 #if REGISTER_WARNINGS 4765 if (!quiet_warnings 4766 && !i.tm.operand_types[op].bitfield.inoutportreg) 4767 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 4768 register_prefix, 4769 (i.op[op].regs + (i.types[op].bitfield.reg16 4770 ? REGNAM_AL - REGNAM_AX 4771 : REGNAM_AL - REGNAM_EAX))->reg_name, 4772 register_prefix, 4773 i.op[op].regs->reg_name, 4774 i.suffix); 4775 #endif 4776 continue; 4777 } 4778 /* Any other register is bad. */ 4779 if (i.types[op].bitfield.reg16 4780 || i.types[op].bitfield.reg32 4781 || i.types[op].bitfield.reg64 4782 || i.types[op].bitfield.regmmx 4783 || i.types[op].bitfield.regxmm 4784 || i.types[op].bitfield.regymm 4785 || i.types[op].bitfield.sreg2 4786 || i.types[op].bitfield.sreg3 4787 || i.types[op].bitfield.control 4788 || i.types[op].bitfield.debug 4789 || i.types[op].bitfield.test 4790 || i.types[op].bitfield.floatreg 4791 || i.types[op].bitfield.floatacc) 4792 { 4793 as_bad (_("`%s%s' not allowed with `%s%c'"), 4794 register_prefix, 4795 i.op[op].regs->reg_name, 4796 i.tm.name, 4797 i.suffix); 4798 return 0; 4799 } 4800 } 4801 return 1; 4802 } 4803 4804 static int 4805 check_long_reg (void) 4806 { 4807 int op; 4808 4809 for (op = i.operands; --op >= 0;) 4810 /* Reject eight bit registers, except where the template requires 4811 them. (eg. movzb) */ 4812 if (i.types[op].bitfield.reg8 4813 && (i.tm.operand_types[op].bitfield.reg16 4814 || i.tm.operand_types[op].bitfield.reg32 4815 || i.tm.operand_types[op].bitfield.acc)) 4816 { 4817 as_bad (_("`%s%s' not allowed with `%s%c'"), 4818 register_prefix, 4819 i.op[op].regs->reg_name, 4820 i.tm.name, 4821 i.suffix); 4822 return 0; 4823 } 4824 /* Warn if the e prefix on a general reg is missing. */ 4825 else if ((!quiet_warnings || flag_code == CODE_64BIT) 4826 && i.types[op].bitfield.reg16 4827 && (i.tm.operand_types[op].bitfield.reg32 4828 || i.tm.operand_types[op].bitfield.acc)) 4829 { 4830 /* Prohibit these changes in the 64bit mode, since the 4831 lowering is more complicated. */ 4832 if (flag_code == CODE_64BIT) 4833 { 4834 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 4835 register_prefix, i.op[op].regs->reg_name, 4836 i.suffix); 4837 return 0; 4838 } 4839 #if REGISTER_WARNINGS 4840 else 4841 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 4842 register_prefix, 4843 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, 4844 register_prefix, 4845 i.op[op].regs->reg_name, 4846 i.suffix); 4847 #endif 4848 } 4849 /* Warn if the r prefix on a general reg is missing. */ 4850 else if (i.types[op].bitfield.reg64 4851 && (i.tm.operand_types[op].bitfield.reg32 4852 || i.tm.operand_types[op].bitfield.acc)) 4853 { 4854 if (intel_syntax 4855 && i.tm.opcode_modifier.toqword 4856 && !i.types[0].bitfield.regxmm) 4857 { 4858 /* Convert to QWORD. We want REX byte. */ 4859 i.suffix = QWORD_MNEM_SUFFIX; 4860 } 4861 else 4862 { 4863 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 4864 register_prefix, i.op[op].regs->reg_name, 4865 i.suffix); 4866 return 0; 4867 } 4868 } 4869 return 1; 4870 } 4871 4872 static int 4873 check_qword_reg (void) 4874 { 4875 int op; 4876 4877 for (op = i.operands; --op >= 0; ) 4878 /* Reject eight bit registers, except where the template requires 4879 them. (eg. movzb) */ 4880 if (i.types[op].bitfield.reg8 4881 && (i.tm.operand_types[op].bitfield.reg16 4882 || i.tm.operand_types[op].bitfield.reg32 4883 || i.tm.operand_types[op].bitfield.acc)) 4884 { 4885 as_bad (_("`%s%s' not allowed with `%s%c'"), 4886 register_prefix, 4887 i.op[op].regs->reg_name, 4888 i.tm.name, 4889 i.suffix); 4890 return 0; 4891 } 4892 /* Warn if the e prefix on a general reg is missing. */ 4893 else if ((i.types[op].bitfield.reg16 4894 || i.types[op].bitfield.reg32) 4895 && (i.tm.operand_types[op].bitfield.reg32 4896 || i.tm.operand_types[op].bitfield.acc)) 4897 { 4898 /* Prohibit these changes in the 64bit mode, since the 4899 lowering is more complicated. */ 4900 if (intel_syntax 4901 && i.tm.opcode_modifier.todword 4902 && !i.types[0].bitfield.regxmm) 4903 { 4904 /* Convert to DWORD. We don't want REX byte. */ 4905 i.suffix = LONG_MNEM_SUFFIX; 4906 } 4907 else 4908 { 4909 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 4910 register_prefix, i.op[op].regs->reg_name, 4911 i.suffix); 4912 return 0; 4913 } 4914 } 4915 return 1; 4916 } 4917 4918 static int 4919 check_word_reg (void) 4920 { 4921 int op; 4922 for (op = i.operands; --op >= 0;) 4923 /* Reject eight bit registers, except where the template requires 4924 them. (eg. movzb) */ 4925 if (i.types[op].bitfield.reg8 4926 && (i.tm.operand_types[op].bitfield.reg16 4927 || i.tm.operand_types[op].bitfield.reg32 4928 || i.tm.operand_types[op].bitfield.acc)) 4929 { 4930 as_bad (_("`%s%s' not allowed with `%s%c'"), 4931 register_prefix, 4932 i.op[op].regs->reg_name, 4933 i.tm.name, 4934 i.suffix); 4935 return 0; 4936 } 4937 /* Warn if the e prefix on a general reg is present. */ 4938 else if ((!quiet_warnings || flag_code == CODE_64BIT) 4939 && i.types[op].bitfield.reg32 4940 && (i.tm.operand_types[op].bitfield.reg16 4941 || i.tm.operand_types[op].bitfield.acc)) 4942 { 4943 /* Prohibit these changes in the 64bit mode, since the 4944 lowering is more complicated. */ 4945 if (flag_code == CODE_64BIT) 4946 { 4947 as_bad (_("incorrect register `%s%s' used with `%c' suffix"), 4948 register_prefix, i.op[op].regs->reg_name, 4949 i.suffix); 4950 return 0; 4951 } 4952 else 4953 #if REGISTER_WARNINGS 4954 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), 4955 register_prefix, 4956 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, 4957 register_prefix, 4958 i.op[op].regs->reg_name, 4959 i.suffix); 4960 #endif 4961 } 4962 return 1; 4963 } 4964 4965 static int 4966 update_imm (unsigned int j) 4967 { 4968 i386_operand_type overlap = i.types[j]; 4969 if ((overlap.bitfield.imm8 4970 || overlap.bitfield.imm8s 4971 || overlap.bitfield.imm16 4972 || overlap.bitfield.imm32 4973 || overlap.bitfield.imm32s 4974 || overlap.bitfield.imm64) 4975 && !operand_type_equal (&overlap, &imm8) 4976 && !operand_type_equal (&overlap, &imm8s) 4977 && !operand_type_equal (&overlap, &imm16) 4978 && !operand_type_equal (&overlap, &imm32) 4979 && !operand_type_equal (&overlap, &imm32s) 4980 && !operand_type_equal (&overlap, &imm64)) 4981 { 4982 if (i.suffix) 4983 { 4984 i386_operand_type temp; 4985 4986 operand_type_set (&temp, 0); 4987 if (i.suffix == BYTE_MNEM_SUFFIX) 4988 { 4989 temp.bitfield.imm8 = overlap.bitfield.imm8; 4990 temp.bitfield.imm8s = overlap.bitfield.imm8s; 4991 } 4992 else if (i.suffix == WORD_MNEM_SUFFIX) 4993 temp.bitfield.imm16 = overlap.bitfield.imm16; 4994 else if (i.suffix == QWORD_MNEM_SUFFIX) 4995 { 4996 temp.bitfield.imm64 = overlap.bitfield.imm64; 4997 temp.bitfield.imm32s = overlap.bitfield.imm32s; 4998 } 4999 else 5000 temp.bitfield.imm32 = overlap.bitfield.imm32; 5001 overlap = temp; 5002 } 5003 else if (operand_type_equal (&overlap, &imm16_32_32s) 5004 || operand_type_equal (&overlap, &imm16_32) 5005 || operand_type_equal (&overlap, &imm16_32s)) 5006 { 5007 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 5008 overlap = imm16; 5009 else 5010 overlap = imm32s; 5011 } 5012 if (!operand_type_equal (&overlap, &imm8) 5013 && !operand_type_equal (&overlap, &imm8s) 5014 && !operand_type_equal (&overlap, &imm16) 5015 && !operand_type_equal (&overlap, &imm32) 5016 && !operand_type_equal (&overlap, &imm32s) 5017 && !operand_type_equal (&overlap, &imm64)) 5018 { 5019 as_bad (_("no instruction mnemonic suffix given; " 5020 "can't determine immediate size")); 5021 return 0; 5022 } 5023 } 5024 i.types[j] = overlap; 5025 5026 return 1; 5027 } 5028 5029 static int 5030 finalize_imm (void) 5031 { 5032 unsigned int j, n; 5033 5034 /* Update the first 2 immediate operands. */ 5035 n = i.operands > 2 ? 2 : i.operands; 5036 if (n) 5037 { 5038 for (j = 0; j < n; j++) 5039 if (update_imm (j) == 0) 5040 return 0; 5041 5042 /* The 3rd operand can't be immediate operand. */ 5043 gas_assert (operand_type_check (i.types[2], imm) == 0); 5044 } 5045 5046 return 1; 5047 } 5048 5049 static int 5050 bad_implicit_operand (int xmm) 5051 { 5052 const char *ireg = xmm ? "xmm0" : "ymm0"; 5053 5054 if (intel_syntax) 5055 as_bad (_("the last operand of `%s' must be `%s%s'"), 5056 i.tm.name, register_prefix, ireg); 5057 else 5058 as_bad (_("the first operand of `%s' must be `%s%s'"), 5059 i.tm.name, register_prefix, ireg); 5060 return 0; 5061 } 5062 5063 static int 5064 process_operands (void) 5065 { 5066 /* Default segment register this instruction will use for memory 5067 accesses. 0 means unknown. This is only for optimizing out 5068 unnecessary segment overrides. */ 5069 const seg_entry *default_seg = 0; 5070 5071 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) 5072 { 5073 unsigned int dupl = i.operands; 5074 unsigned int dest = dupl - 1; 5075 unsigned int j; 5076 5077 /* The destination must be an xmm register. */ 5078 gas_assert (i.reg_operands 5079 && MAX_OPERANDS > dupl 5080 && operand_type_equal (&i.types[dest], ®xmm)); 5081 5082 if (i.tm.opcode_modifier.firstxmm0) 5083 { 5084 /* The first operand is implicit and must be xmm0. */ 5085 gas_assert (operand_type_equal (&i.types[0], ®xmm)); 5086 if (i.op[0].regs->reg_num != 0) 5087 return bad_implicit_operand (1); 5088 5089 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) 5090 { 5091 /* Keep xmm0 for instructions with VEX prefix and 3 5092 sources. */ 5093 goto duplicate; 5094 } 5095 else 5096 { 5097 /* We remove the first xmm0 and keep the number of 5098 operands unchanged, which in fact duplicates the 5099 destination. */ 5100 for (j = 1; j < i.operands; j++) 5101 { 5102 i.op[j - 1] = i.op[j]; 5103 i.types[j - 1] = i.types[j]; 5104 i.tm.operand_types[j - 1] = i.tm.operand_types[j]; 5105 } 5106 } 5107 } 5108 else if (i.tm.opcode_modifier.implicit1stxmm0) 5109 { 5110 gas_assert ((MAX_OPERANDS - 1) > dupl 5111 && (i.tm.opcode_modifier.vexsources 5112 == VEX3SOURCES)); 5113 5114 /* Add the implicit xmm0 for instructions with VEX prefix 5115 and 3 sources. */ 5116 for (j = i.operands; j > 0; j--) 5117 { 5118 i.op[j] = i.op[j - 1]; 5119 i.types[j] = i.types[j - 1]; 5120 i.tm.operand_types[j] = i.tm.operand_types[j - 1]; 5121 } 5122 i.op[0].regs 5123 = (const reg_entry *) hash_find (reg_hash, "xmm0"); 5124 i.types[0] = regxmm; 5125 i.tm.operand_types[0] = regxmm; 5126 5127 i.operands += 2; 5128 i.reg_operands += 2; 5129 i.tm.operands += 2; 5130 5131 dupl++; 5132 dest++; 5133 i.op[dupl] = i.op[dest]; 5134 i.types[dupl] = i.types[dest]; 5135 i.tm.operand_types[dupl] = i.tm.operand_types[dest]; 5136 } 5137 else 5138 { 5139 duplicate: 5140 i.operands++; 5141 i.reg_operands++; 5142 i.tm.operands++; 5143 5144 i.op[dupl] = i.op[dest]; 5145 i.types[dupl] = i.types[dest]; 5146 i.tm.operand_types[dupl] = i.tm.operand_types[dest]; 5147 } 5148 5149 if (i.tm.opcode_modifier.immext) 5150 process_immext (); 5151 } 5152 else if (i.tm.opcode_modifier.firstxmm0) 5153 { 5154 unsigned int j; 5155 5156 /* The first operand is implicit and must be xmm0/ymm0. */ 5157 gas_assert (i.reg_operands 5158 && (operand_type_equal (&i.types[0], ®xmm) 5159 || operand_type_equal (&i.types[0], ®ymm))); 5160 if (i.op[0].regs->reg_num != 0) 5161 return bad_implicit_operand (i.types[0].bitfield.regxmm); 5162 5163 for (j = 1; j < i.operands; j++) 5164 { 5165 i.op[j - 1] = i.op[j]; 5166 i.types[j - 1] = i.types[j]; 5167 5168 /* We need to adjust fields in i.tm since they are used by 5169 build_modrm_byte. */ 5170 i.tm.operand_types [j - 1] = i.tm.operand_types [j]; 5171 } 5172 5173 i.operands--; 5174 i.reg_operands--; 5175 i.tm.operands--; 5176 } 5177 else if (i.tm.opcode_modifier.regkludge) 5178 { 5179 /* The imul $imm, %reg instruction is converted into 5180 imul $imm, %reg, %reg, and the clr %reg instruction 5181 is converted into xor %reg, %reg. */ 5182 5183 unsigned int first_reg_op; 5184 5185 if (operand_type_check (i.types[0], reg)) 5186 first_reg_op = 0; 5187 else 5188 first_reg_op = 1; 5189 /* Pretend we saw the extra register operand. */ 5190 gas_assert (i.reg_operands == 1 5191 && i.op[first_reg_op + 1].regs == 0); 5192 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; 5193 i.types[first_reg_op + 1] = i.types[first_reg_op]; 5194 i.operands++; 5195 i.reg_operands++; 5196 } 5197 5198 if (i.tm.opcode_modifier.shortform) 5199 { 5200 if (i.types[0].bitfield.sreg2 5201 || i.types[0].bitfield.sreg3) 5202 { 5203 if (i.tm.base_opcode == POP_SEG_SHORT 5204 && i.op[0].regs->reg_num == 1) 5205 { 5206 as_bad (_("you can't `pop %scs'"), register_prefix); 5207 return 0; 5208 } 5209 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 5210 if ((i.op[0].regs->reg_flags & RegRex) != 0) 5211 i.rex |= REX_B; 5212 } 5213 else 5214 { 5215 /* The register or float register operand is in operand 5216 0 or 1. */ 5217 unsigned int op; 5218 5219 if (i.types[0].bitfield.floatreg 5220 || operand_type_check (i.types[0], reg)) 5221 op = 0; 5222 else 5223 op = 1; 5224 /* Register goes in low 3 bits of opcode. */ 5225 i.tm.base_opcode |= i.op[op].regs->reg_num; 5226 if ((i.op[op].regs->reg_flags & RegRex) != 0) 5227 i.rex |= REX_B; 5228 if (!quiet_warnings && i.tm.opcode_modifier.ugh) 5229 { 5230 /* Warn about some common errors, but press on regardless. 5231 The first case can be generated by gcc (<= 2.8.1). */ 5232 if (i.operands == 2) 5233 { 5234 /* Reversed arguments on faddp, fsubp, etc. */ 5235 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, 5236 register_prefix, i.op[!intel_syntax].regs->reg_name, 5237 register_prefix, i.op[intel_syntax].regs->reg_name); 5238 } 5239 else 5240 { 5241 /* Extraneous `l' suffix on fp insn. */ 5242 as_warn (_("translating to `%s %s%s'"), i.tm.name, 5243 register_prefix, i.op[0].regs->reg_name); 5244 } 5245 } 5246 } 5247 } 5248 else if (i.tm.opcode_modifier.modrm) 5249 { 5250 /* The opcode is completed (modulo i.tm.extension_opcode which 5251 must be put into the modrm byte). Now, we make the modrm and 5252 index base bytes based on all the info we've collected. */ 5253 5254 default_seg = build_modrm_byte (); 5255 } 5256 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) 5257 { 5258 default_seg = &ds; 5259 } 5260 else if (i.tm.opcode_modifier.isstring) 5261 { 5262 /* For the string instructions that allow a segment override 5263 on one of their operands, the default segment is ds. */ 5264 default_seg = &ds; 5265 } 5266 5267 if (i.tm.base_opcode == 0x8d /* lea */ 5268 && i.seg[0] 5269 && !quiet_warnings) 5270 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); 5271 5272 /* If a segment was explicitly specified, and the specified segment 5273 is not the default, use an opcode prefix to select it. If we 5274 never figured out what the default segment is, then default_seg 5275 will be zero at this point, and the specified segment prefix will 5276 always be used. */ 5277 if ((i.seg[0]) && (i.seg[0] != default_seg)) 5278 { 5279 if (!add_prefix (i.seg[0]->seg_prefix)) 5280 return 0; 5281 } 5282 return 1; 5283 } 5284 5285 static const seg_entry * 5286 build_modrm_byte (void) 5287 { 5288 const seg_entry *default_seg = 0; 5289 unsigned int source, dest; 5290 int vex_3_sources; 5291 5292 /* The first operand of instructions with VEX prefix and 3 sources 5293 must be VEX_Imm4. */ 5294 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; 5295 if (vex_3_sources) 5296 { 5297 unsigned int nds, reg_slot; 5298 expressionS *exp; 5299 5300 if (i.tm.opcode_modifier.veximmext 5301 && i.tm.opcode_modifier.immext) 5302 { 5303 dest = i.operands - 2; 5304 gas_assert (dest == 3); 5305 } 5306 else 5307 dest = i.operands - 1; 5308 nds = dest - 1; 5309 5310 /* There are 2 kinds of instructions: 5311 1. 5 operands: 4 register operands or 3 register operands 5312 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and 5313 VexW0 or VexW1. The destination must be either XMM or YMM 5314 register. 5315 2. 4 operands: 4 register operands or 3 register operands 5316 plus 1 memory operand, VexXDS, and VexImmExt */ 5317 gas_assert ((i.reg_operands == 4 5318 || (i.reg_operands == 3 && i.mem_operands == 1)) 5319 && i.tm.opcode_modifier.vexvvvv == VEXXDS 5320 && (i.tm.opcode_modifier.veximmext 5321 || (i.imm_operands == 1 5322 && i.types[0].bitfield.vec_imm4 5323 && (i.tm.opcode_modifier.vexw == VEXW0 5324 || i.tm.opcode_modifier.vexw == VEXW1) 5325 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) 5326 || operand_type_equal (&i.tm.operand_types[dest], ®ymm))))); 5327 5328 if (i.imm_operands == 0) 5329 { 5330 /* When there is no immediate operand, generate an 8bit 5331 immediate operand to encode the first operand. */ 5332 exp = &im_expressions[i.imm_operands++]; 5333 i.op[i.operands].imms = exp; 5334 i.types[i.operands] = imm8; 5335 i.operands++; 5336 /* If VexW1 is set, the first operand is the source and 5337 the second operand is encoded in the immediate operand. */ 5338 if (i.tm.opcode_modifier.vexw == VEXW1) 5339 { 5340 source = 0; 5341 reg_slot = 1; 5342 } 5343 else 5344 { 5345 source = 1; 5346 reg_slot = 0; 5347 } 5348 5349 /* FMA swaps REG and NDS. */ 5350 if (i.tm.cpu_flags.bitfield.cpufma) 5351 { 5352 unsigned int tmp; 5353 tmp = reg_slot; 5354 reg_slot = nds; 5355 nds = tmp; 5356 } 5357 5358 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], 5359 ®xmm) 5360 || operand_type_equal (&i.tm.operand_types[reg_slot], 5361 ®ymm)); 5362 exp->X_op = O_constant; 5363 exp->X_add_number 5364 = ((i.op[reg_slot].regs->reg_num 5365 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) 5366 << 4); 5367 } 5368 else 5369 { 5370 unsigned int imm_slot; 5371 5372 if (i.tm.opcode_modifier.vexw == VEXW0) 5373 { 5374 /* If VexW0 is set, the third operand is the source and 5375 the second operand is encoded in the immediate 5376 operand. */ 5377 source = 2; 5378 reg_slot = 1; 5379 } 5380 else 5381 { 5382 /* VexW1 is set, the second operand is the source and 5383 the third operand is encoded in the immediate 5384 operand. */ 5385 source = 1; 5386 reg_slot = 2; 5387 } 5388 5389 if (i.tm.opcode_modifier.immext) 5390 { 5391 /* When ImmExt is set, the immdiate byte is the last 5392 operand. */ 5393 imm_slot = i.operands - 1; 5394 source--; 5395 reg_slot--; 5396 } 5397 else 5398 { 5399 imm_slot = 0; 5400 5401 /* Turn on Imm8 so that output_imm will generate it. */ 5402 i.types[imm_slot].bitfield.imm8 = 1; 5403 } 5404 5405 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], 5406 ®xmm) 5407 || operand_type_equal (&i.tm.operand_types[reg_slot], 5408 ®ymm)); 5409 i.op[imm_slot].imms->X_add_number 5410 |= ((i.op[reg_slot].regs->reg_num 5411 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) 5412 << 4); 5413 } 5414 5415 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) 5416 || operand_type_equal (&i.tm.operand_types[nds], 5417 ®ymm)); 5418 i.vex.register_specifier = i.op[nds].regs; 5419 } 5420 else 5421 source = dest = 0; 5422 5423 /* i.reg_operands MUST be the number of real register operands; 5424 implicit registers do not count. If there are 3 register 5425 operands, it must be a instruction with VexNDS. For a 5426 instruction with VexNDD, the destination register is encoded 5427 in VEX prefix. If there are 4 register operands, it must be 5428 a instruction with VEX prefix and 3 sources. */ 5429 if (i.mem_operands == 0 5430 && ((i.reg_operands == 2 5431 && i.tm.opcode_modifier.vexvvvv <= VEXXDS) 5432 || (i.reg_operands == 3 5433 && i.tm.opcode_modifier.vexvvvv == VEXXDS) 5434 || (i.reg_operands == 4 && vex_3_sources))) 5435 { 5436 switch (i.operands) 5437 { 5438 case 2: 5439 source = 0; 5440 break; 5441 case 3: 5442 /* When there are 3 operands, one of them may be immediate, 5443 which may be the first or the last operand. Otherwise, 5444 the first operand must be shift count register (cl) or it 5445 is an instruction with VexNDS. */ 5446 gas_assert (i.imm_operands == 1 5447 || (i.imm_operands == 0 5448 && (i.tm.opcode_modifier.vexvvvv == VEXXDS 5449 || i.types[0].bitfield.shiftcount))); 5450 if (operand_type_check (i.types[0], imm) 5451 || i.types[0].bitfield.shiftcount) 5452 source = 1; 5453 else 5454 source = 0; 5455 break; 5456 case 4: 5457 /* When there are 4 operands, the first two must be 8bit 5458 immediate operands. The source operand will be the 3rd 5459 one. 5460 5461 For instructions with VexNDS, if the first operand 5462 an imm8, the source operand is the 2nd one. If the last 5463 operand is imm8, the source operand is the first one. */ 5464 gas_assert ((i.imm_operands == 2 5465 && i.types[0].bitfield.imm8 5466 && i.types[1].bitfield.imm8) 5467 || (i.tm.opcode_modifier.vexvvvv == VEXXDS 5468 && i.imm_operands == 1 5469 && (i.types[0].bitfield.imm8 5470 || i.types[i.operands - 1].bitfield.imm8))); 5471 if (i.imm_operands == 2) 5472 source = 2; 5473 else 5474 { 5475 if (i.types[0].bitfield.imm8) 5476 source = 1; 5477 else 5478 source = 0; 5479 } 5480 break; 5481 case 5: 5482 break; 5483 default: 5484 abort (); 5485 } 5486 5487 if (!vex_3_sources) 5488 { 5489 dest = source + 1; 5490 5491 if (i.tm.opcode_modifier.vexvvvv == VEXXDS) 5492 { 5493 /* For instructions with VexNDS, the register-only 5494 source operand must be 32/64bit integer, XMM or 5495 YMM register. It is encoded in VEX prefix. We 5496 need to clear RegMem bit before calling 5497 operand_type_equal. */ 5498 5499 i386_operand_type op; 5500 unsigned int vvvv; 5501 5502 /* Check register-only source operand when two source 5503 operands are swapped. */ 5504 if (!i.tm.operand_types[source].bitfield.baseindex 5505 && i.tm.operand_types[dest].bitfield.baseindex) 5506 { 5507 vvvv = source; 5508 source = dest; 5509 } 5510 else 5511 vvvv = dest; 5512 5513 op = i.tm.operand_types[vvvv]; 5514 op.bitfield.regmem = 0; 5515 if ((dest + 1) >= i.operands 5516 || (op.bitfield.reg32 != 1 5517 && !op.bitfield.reg64 != 1 5518 && !operand_type_equal (&op, ®xmm) 5519 && !operand_type_equal (&op, ®ymm))) 5520 abort (); 5521 i.vex.register_specifier = i.op[vvvv].regs; 5522 dest++; 5523 } 5524 } 5525 5526 i.rm.mode = 3; 5527 /* One of the register operands will be encoded in the i.tm.reg 5528 field, the other in the combined i.tm.mode and i.tm.regmem 5529 fields. If no form of this instruction supports a memory 5530 destination operand, then we assume the source operand may 5531 sometimes be a memory operand and so we need to store the 5532 destination in the i.rm.reg field. */ 5533 if (!i.tm.operand_types[dest].bitfield.regmem 5534 && operand_type_check (i.tm.operand_types[dest], anymem) == 0) 5535 { 5536 i.rm.reg = i.op[dest].regs->reg_num; 5537 i.rm.regmem = i.op[source].regs->reg_num; 5538 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 5539 i.rex |= REX_R; 5540 if ((i.op[source].regs->reg_flags & RegRex) != 0) 5541 i.rex |= REX_B; 5542 } 5543 else 5544 { 5545 i.rm.reg = i.op[source].regs->reg_num; 5546 i.rm.regmem = i.op[dest].regs->reg_num; 5547 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 5548 i.rex |= REX_B; 5549 if ((i.op[source].regs->reg_flags & RegRex) != 0) 5550 i.rex |= REX_R; 5551 } 5552 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) 5553 { 5554 if (!i.types[0].bitfield.control 5555 && !i.types[1].bitfield.control) 5556 abort (); 5557 i.rex &= ~(REX_R | REX_B); 5558 add_prefix (LOCK_PREFIX_OPCODE); 5559 } 5560 } 5561 else 5562 { /* If it's not 2 reg operands... */ 5563 unsigned int mem; 5564 5565 if (i.mem_operands) 5566 { 5567 unsigned int fake_zero_displacement = 0; 5568 unsigned int op; 5569 5570 for (op = 0; op < i.operands; op++) 5571 if (operand_type_check (i.types[op], anymem)) 5572 break; 5573 gas_assert (op < i.operands); 5574 5575 if (i.tm.opcode_modifier.vecsib) 5576 { 5577 if (i.index_reg->reg_num == RegEiz 5578 || i.index_reg->reg_num == RegRiz) 5579 abort (); 5580 5581 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 5582 if (!i.base_reg) 5583 { 5584 i.sib.base = NO_BASE_REGISTER; 5585 i.sib.scale = i.log2_scale_factor; 5586 i.types[op].bitfield.disp8 = 0; 5587 i.types[op].bitfield.disp16 = 0; 5588 i.types[op].bitfield.disp64 = 0; 5589 if (flag_code != CODE_64BIT) 5590 { 5591 /* Must be 32 bit */ 5592 i.types[op].bitfield.disp32 = 1; 5593 i.types[op].bitfield.disp32s = 0; 5594 } 5595 else 5596 { 5597 i.types[op].bitfield.disp32 = 0; 5598 i.types[op].bitfield.disp32s = 1; 5599 } 5600 } 5601 i.sib.index = i.index_reg->reg_num; 5602 if ((i.index_reg->reg_flags & RegRex) != 0) 5603 i.rex |= REX_X; 5604 } 5605 5606 default_seg = &ds; 5607 5608 if (i.base_reg == 0) 5609 { 5610 i.rm.mode = 0; 5611 if (!i.disp_operands) 5612 { 5613 fake_zero_displacement = 1; 5614 /* Instructions with VSIB byte need 32bit displacement 5615 if there is no base register. */ 5616 if (i.tm.opcode_modifier.vecsib) 5617 i.types[op].bitfield.disp32 = 1; 5618 } 5619 if (i.index_reg == 0) 5620 { 5621 gas_assert (!i.tm.opcode_modifier.vecsib); 5622 /* Operand is just <disp> */ 5623 if (flag_code == CODE_64BIT) 5624 { 5625 /* 64bit mode overwrites the 32bit absolute 5626 addressing by RIP relative addressing and 5627 absolute addressing is encoded by one of the 5628 redundant SIB forms. */ 5629 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 5630 i.sib.base = NO_BASE_REGISTER; 5631 i.sib.index = NO_INDEX_REGISTER; 5632 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) 5633 ? disp32s : disp32); 5634 } 5635 else if ((flag_code == CODE_16BIT) 5636 ^ (i.prefix[ADDR_PREFIX] != 0)) 5637 { 5638 i.rm.regmem = NO_BASE_REGISTER_16; 5639 i.types[op] = disp16; 5640 } 5641 else 5642 { 5643 i.rm.regmem = NO_BASE_REGISTER; 5644 i.types[op] = disp32; 5645 } 5646 } 5647 else if (!i.tm.opcode_modifier.vecsib) 5648 { 5649 /* !i.base_reg && i.index_reg */ 5650 if (i.index_reg->reg_num == RegEiz 5651 || i.index_reg->reg_num == RegRiz) 5652 i.sib.index = NO_INDEX_REGISTER; 5653 else 5654 i.sib.index = i.index_reg->reg_num; 5655 i.sib.base = NO_BASE_REGISTER; 5656 i.sib.scale = i.log2_scale_factor; 5657 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 5658 i.types[op].bitfield.disp8 = 0; 5659 i.types[op].bitfield.disp16 = 0; 5660 i.types[op].bitfield.disp64 = 0; 5661 if (flag_code != CODE_64BIT) 5662 { 5663 /* Must be 32 bit */ 5664 i.types[op].bitfield.disp32 = 1; 5665 i.types[op].bitfield.disp32s = 0; 5666 } 5667 else 5668 { 5669 i.types[op].bitfield.disp32 = 0; 5670 i.types[op].bitfield.disp32s = 1; 5671 } 5672 if ((i.index_reg->reg_flags & RegRex) != 0) 5673 i.rex |= REX_X; 5674 } 5675 } 5676 /* RIP addressing for 64bit mode. */ 5677 else if (i.base_reg->reg_num == RegRip || 5678 i.base_reg->reg_num == RegEip) 5679 { 5680 gas_assert (!i.tm.opcode_modifier.vecsib); 5681 i.rm.regmem = NO_BASE_REGISTER; 5682 i.types[op].bitfield.disp8 = 0; 5683 i.types[op].bitfield.disp16 = 0; 5684 i.types[op].bitfield.disp32 = 0; 5685 i.types[op].bitfield.disp32s = 1; 5686 i.types[op].bitfield.disp64 = 0; 5687 i.flags[op] |= Operand_PCrel; 5688 if (! i.disp_operands) 5689 fake_zero_displacement = 1; 5690 } 5691 else if (i.base_reg->reg_type.bitfield.reg16) 5692 { 5693 gas_assert (!i.tm.opcode_modifier.vecsib); 5694 switch (i.base_reg->reg_num) 5695 { 5696 case 3: /* (%bx) */ 5697 if (i.index_reg == 0) 5698 i.rm.regmem = 7; 5699 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 5700 i.rm.regmem = i.index_reg->reg_num - 6; 5701 break; 5702 case 5: /* (%bp) */ 5703 default_seg = &ss; 5704 if (i.index_reg == 0) 5705 { 5706 i.rm.regmem = 6; 5707 if (operand_type_check (i.types[op], disp) == 0) 5708 { 5709 /* fake (%bp) into 0(%bp) */ 5710 i.types[op].bitfield.disp8 = 1; 5711 fake_zero_displacement = 1; 5712 } 5713 } 5714 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 5715 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 5716 break; 5717 default: /* (%si) -> 4 or (%di) -> 5 */ 5718 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 5719 } 5720 i.rm.mode = mode_from_disp_size (i.types[op]); 5721 } 5722 else /* i.base_reg and 32/64 bit mode */ 5723 { 5724 if (flag_code == CODE_64BIT 5725 && operand_type_check (i.types[op], disp)) 5726 { 5727 i386_operand_type temp; 5728 operand_type_set (&temp, 0); 5729 temp.bitfield.disp8 = i.types[op].bitfield.disp8; 5730 i.types[op] = temp; 5731 if (i.prefix[ADDR_PREFIX] == 0) 5732 i.types[op].bitfield.disp32s = 1; 5733 else 5734 i.types[op].bitfield.disp32 = 1; 5735 } 5736 5737 if (!i.tm.opcode_modifier.vecsib) 5738 i.rm.regmem = i.base_reg->reg_num; 5739 if ((i.base_reg->reg_flags & RegRex) != 0) 5740 i.rex |= REX_B; 5741 i.sib.base = i.base_reg->reg_num; 5742 /* x86-64 ignores REX prefix bit here to avoid decoder 5743 complications. */ 5744 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) 5745 { 5746 default_seg = &ss; 5747 if (i.disp_operands == 0) 5748 { 5749 fake_zero_displacement = 1; 5750 i.types[op].bitfield.disp8 = 1; 5751 } 5752 } 5753 else if (i.base_reg->reg_num == ESP_REG_NUM) 5754 { 5755 default_seg = &ss; 5756 } 5757 i.sib.scale = i.log2_scale_factor; 5758 if (i.index_reg == 0) 5759 { 5760 gas_assert (!i.tm.opcode_modifier.vecsib); 5761 /* <disp>(%esp) becomes two byte modrm with no index 5762 register. We've already stored the code for esp 5763 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. 5764 Any base register besides %esp will not use the 5765 extra modrm byte. */ 5766 i.sib.index = NO_INDEX_REGISTER; 5767 } 5768 else if (!i.tm.opcode_modifier.vecsib) 5769 { 5770 if (i.index_reg->reg_num == RegEiz 5771 || i.index_reg->reg_num == RegRiz) 5772 i.sib.index = NO_INDEX_REGISTER; 5773 else 5774 i.sib.index = i.index_reg->reg_num; 5775 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 5776 if ((i.index_reg->reg_flags & RegRex) != 0) 5777 i.rex |= REX_X; 5778 } 5779 5780 if (i.disp_operands 5781 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 5782 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) 5783 i.rm.mode = 0; 5784 else 5785 { 5786 if (!fake_zero_displacement 5787 && !i.disp_operands 5788 && i.disp_encoding) 5789 { 5790 fake_zero_displacement = 1; 5791 if (i.disp_encoding == disp_encoding_8bit) 5792 i.types[op].bitfield.disp8 = 1; 5793 else 5794 i.types[op].bitfield.disp32 = 1; 5795 } 5796 i.rm.mode = mode_from_disp_size (i.types[op]); 5797 } 5798 } 5799 5800 if (fake_zero_displacement) 5801 { 5802 /* Fakes a zero displacement assuming that i.types[op] 5803 holds the correct displacement size. */ 5804 expressionS *exp; 5805 5806 gas_assert (i.op[op].disps == 0); 5807 exp = &disp_expressions[i.disp_operands++]; 5808 i.op[op].disps = exp; 5809 exp->X_op = O_constant; 5810 exp->X_add_number = 0; 5811 exp->X_add_symbol = (symbolS *) 0; 5812 exp->X_op_symbol = (symbolS *) 0; 5813 } 5814 5815 mem = op; 5816 } 5817 else 5818 mem = ~0; 5819 5820 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) 5821 { 5822 if (operand_type_check (i.types[0], imm)) 5823 i.vex.register_specifier = NULL; 5824 else 5825 { 5826 /* VEX.vvvv encodes one of the sources when the first 5827 operand is not an immediate. */ 5828 if (i.tm.opcode_modifier.vexw == VEXW0) 5829 i.vex.register_specifier = i.op[0].regs; 5830 else 5831 i.vex.register_specifier = i.op[1].regs; 5832 } 5833 5834 /* Destination is a XMM register encoded in the ModRM.reg 5835 and VEX.R bit. */ 5836 i.rm.reg = i.op[2].regs->reg_num; 5837 if ((i.op[2].regs->reg_flags & RegRex) != 0) 5838 i.rex |= REX_R; 5839 5840 /* ModRM.rm and VEX.B encodes the other source. */ 5841 if (!i.mem_operands) 5842 { 5843 i.rm.mode = 3; 5844 5845 if (i.tm.opcode_modifier.vexw == VEXW0) 5846 i.rm.regmem = i.op[1].regs->reg_num; 5847 else 5848 i.rm.regmem = i.op[0].regs->reg_num; 5849 5850 if ((i.op[1].regs->reg_flags & RegRex) != 0) 5851 i.rex |= REX_B; 5852 } 5853 } 5854 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) 5855 { 5856 i.vex.register_specifier = i.op[2].regs; 5857 if (!i.mem_operands) 5858 { 5859 i.rm.mode = 3; 5860 i.rm.regmem = i.op[1].regs->reg_num; 5861 if ((i.op[1].regs->reg_flags & RegRex) != 0) 5862 i.rex |= REX_B; 5863 } 5864 } 5865 /* Fill in i.rm.reg or i.rm.regmem field with register operand 5866 (if any) based on i.tm.extension_opcode. Again, we must be 5867 careful to make sure that segment/control/debug/test/MMX 5868 registers are coded into the i.rm.reg field. */ 5869 else if (i.reg_operands) 5870 { 5871 unsigned int op; 5872 unsigned int vex_reg = ~0; 5873 5874 for (op = 0; op < i.operands; op++) 5875 if (i.types[op].bitfield.reg8 5876 || i.types[op].bitfield.reg16 5877 || i.types[op].bitfield.reg32 5878 || i.types[op].bitfield.reg64 5879 || i.types[op].bitfield.regmmx 5880 || i.types[op].bitfield.regxmm 5881 || i.types[op].bitfield.regymm 5882 || i.types[op].bitfield.sreg2 5883 || i.types[op].bitfield.sreg3 5884 || i.types[op].bitfield.control 5885 || i.types[op].bitfield.debug 5886 || i.types[op].bitfield.test) 5887 break; 5888 5889 if (vex_3_sources) 5890 op = dest; 5891 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) 5892 { 5893 /* For instructions with VexNDS, the register-only 5894 source operand is encoded in VEX prefix. */ 5895 gas_assert (mem != (unsigned int) ~0); 5896 5897 if (op > mem) 5898 { 5899 vex_reg = op++; 5900 gas_assert (op < i.operands); 5901 } 5902 else 5903 { 5904 /* Check register-only source operand when two source 5905 operands are swapped. */ 5906 if (!i.tm.operand_types[op].bitfield.baseindex 5907 && i.tm.operand_types[op + 1].bitfield.baseindex) 5908 { 5909 vex_reg = op; 5910 op += 2; 5911 gas_assert (mem == (vex_reg + 1) 5912 && op < i.operands); 5913 } 5914 else 5915 { 5916 vex_reg = op + 1; 5917 gas_assert (vex_reg < i.operands); 5918 } 5919 } 5920 } 5921 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) 5922 { 5923 /* For instructions with VexNDD, the register destination 5924 is encoded in VEX prefix. */ 5925 if (i.mem_operands == 0) 5926 { 5927 /* There is no memory operand. */ 5928 gas_assert ((op + 2) == i.operands); 5929 vex_reg = op + 1; 5930 } 5931 else 5932 { 5933 /* There are only 2 operands. */ 5934 gas_assert (op < 2 && i.operands == 2); 5935 vex_reg = 1; 5936 } 5937 } 5938 else 5939 gas_assert (op < i.operands); 5940 5941 if (vex_reg != (unsigned int) ~0) 5942 { 5943 i386_operand_type *type = &i.tm.operand_types[vex_reg]; 5944 5945 if (type->bitfield.reg32 != 1 5946 && type->bitfield.reg64 != 1 5947 && !operand_type_equal (type, ®xmm) 5948 && !operand_type_equal (type, ®ymm)) 5949 abort (); 5950 5951 i.vex.register_specifier = i.op[vex_reg].regs; 5952 } 5953 5954 /* Don't set OP operand twice. */ 5955 if (vex_reg != op) 5956 { 5957 /* If there is an extension opcode to put here, the 5958 register number must be put into the regmem field. */ 5959 if (i.tm.extension_opcode != None) 5960 { 5961 i.rm.regmem = i.op[op].regs->reg_num; 5962 if ((i.op[op].regs->reg_flags & RegRex) != 0) 5963 i.rex |= REX_B; 5964 } 5965 else 5966 { 5967 i.rm.reg = i.op[op].regs->reg_num; 5968 if ((i.op[op].regs->reg_flags & RegRex) != 0) 5969 i.rex |= REX_R; 5970 } 5971 } 5972 5973 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we 5974 must set it to 3 to indicate this is a register operand 5975 in the regmem field. */ 5976 if (!i.mem_operands) 5977 i.rm.mode = 3; 5978 } 5979 5980 /* Fill in i.rm.reg field with extension opcode (if any). */ 5981 if (i.tm.extension_opcode != None) 5982 i.rm.reg = i.tm.extension_opcode; 5983 } 5984 return default_seg; 5985 } 5986 5987 static void 5988 output_branch (void) 5989 { 5990 char *p; 5991 int size; 5992 int code16; 5993 int prefix; 5994 relax_substateT subtype; 5995 symbolS *sym; 5996 offsetT off; 5997 5998 code16 = flag_code == CODE_16BIT ? CODE16 : 0; 5999 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; 6000 6001 prefix = 0; 6002 if (i.prefix[DATA_PREFIX] != 0) 6003 { 6004 prefix = 1; 6005 i.prefixes -= 1; 6006 code16 ^= CODE16; 6007 } 6008 /* Pentium4 branch hints. */ 6009 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 6010 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 6011 { 6012 prefix++; 6013 i.prefixes--; 6014 } 6015 if (i.prefix[REX_PREFIX] != 0) 6016 { 6017 prefix++; 6018 i.prefixes--; 6019 } 6020 6021 if (i.prefixes != 0 && !intel_syntax) 6022 as_warn (_("skipping prefixes on this instruction")); 6023 6024 /* It's always a symbol; End frag & setup for relax. 6025 Make sure there is enough room in this frag for the largest 6026 instruction we may generate in md_convert_frag. This is 2 6027 bytes for the opcode and room for the prefix and largest 6028 displacement. */ 6029 frag_grow (prefix + 2 + 4); 6030 /* Prefix and 1 opcode byte go in fr_fix. */ 6031 p = frag_more (prefix + 1); 6032 if (i.prefix[DATA_PREFIX] != 0) 6033 *p++ = DATA_PREFIX_OPCODE; 6034 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE 6035 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) 6036 *p++ = i.prefix[SEG_PREFIX]; 6037 if (i.prefix[REX_PREFIX] != 0) 6038 *p++ = i.prefix[REX_PREFIX]; 6039 *p = i.tm.base_opcode; 6040 6041 if ((unsigned char) *p == JUMP_PC_RELATIVE) 6042 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); 6043 else if (cpu_arch_flags.bitfield.cpui386) 6044 subtype = ENCODE_RELAX_STATE (COND_JUMP, size); 6045 else 6046 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); 6047 subtype |= code16; 6048 6049 sym = i.op[0].disps->X_add_symbol; 6050 off = i.op[0].disps->X_add_number; 6051 6052 if (i.op[0].disps->X_op != O_constant 6053 && i.op[0].disps->X_op != O_symbol) 6054 { 6055 /* Handle complex expressions. */ 6056 sym = make_expr_symbol (i.op[0].disps); 6057 off = 0; 6058 } 6059 6060 /* 1 possible extra opcode + 4 byte displacement go in var part. 6061 Pass reloc in fr_var. */ 6062 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); 6063 } 6064 6065 static void 6066 output_jump (void) 6067 { 6068 char *p; 6069 int size; 6070 fixS *fixP; 6071 6072 if (i.tm.opcode_modifier.jumpbyte) 6073 { 6074 /* This is a loop or jecxz type instruction. */ 6075 size = 1; 6076 if (i.prefix[ADDR_PREFIX] != 0) 6077 { 6078 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 6079 i.prefixes -= 1; 6080 } 6081 /* Pentium4 branch hints. */ 6082 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 6083 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 6084 { 6085 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); 6086 i.prefixes--; 6087 } 6088 } 6089 else 6090 { 6091 int code16; 6092 6093 code16 = 0; 6094 if (flag_code == CODE_16BIT) 6095 code16 = CODE16; 6096 6097 if (i.prefix[DATA_PREFIX] != 0) 6098 { 6099 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 6100 i.prefixes -= 1; 6101 code16 ^= CODE16; 6102 } 6103 6104 size = 4; 6105 if (code16) 6106 size = 2; 6107 } 6108 6109 if (i.prefix[REX_PREFIX] != 0) 6110 { 6111 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); 6112 i.prefixes -= 1; 6113 } 6114 6115 if (i.prefixes != 0 && !intel_syntax) 6116 as_warn (_("skipping prefixes on this instruction")); 6117 6118 p = frag_more (i.tm.opcode_length + size); 6119 switch (i.tm.opcode_length) 6120 { 6121 case 2: 6122 *p++ = i.tm.base_opcode >> 8; 6123 case 1: 6124 *p++ = i.tm.base_opcode; 6125 break; 6126 default: 6127 abort (); 6128 } 6129 6130 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, 6131 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); 6132 6133 /* All jumps handled here are signed, but don't use a signed limit 6134 check for 32 and 16 bit jumps as we want to allow wrap around at 6135 4G and 64k respectively. */ 6136 if (size == 1) 6137 fixP->fx_signed = 1; 6138 } 6139 6140 static void 6141 output_interseg_jump (void) 6142 { 6143 char *p; 6144 int size; 6145 int prefix; 6146 int code16; 6147 6148 code16 = 0; 6149 if (flag_code == CODE_16BIT) 6150 code16 = CODE16; 6151 6152 prefix = 0; 6153 if (i.prefix[DATA_PREFIX] != 0) 6154 { 6155 prefix = 1; 6156 i.prefixes -= 1; 6157 code16 ^= CODE16; 6158 } 6159 if (i.prefix[REX_PREFIX] != 0) 6160 { 6161 prefix++; 6162 i.prefixes -= 1; 6163 } 6164 6165 size = 4; 6166 if (code16) 6167 size = 2; 6168 6169 if (i.prefixes != 0 && !intel_syntax) 6170 as_warn (_("skipping prefixes on this instruction")); 6171 6172 /* 1 opcode; 2 segment; offset */ 6173 p = frag_more (prefix + 1 + 2 + size); 6174 6175 if (i.prefix[DATA_PREFIX] != 0) 6176 *p++ = DATA_PREFIX_OPCODE; 6177 6178 if (i.prefix[REX_PREFIX] != 0) 6179 *p++ = i.prefix[REX_PREFIX]; 6180 6181 *p++ = i.tm.base_opcode; 6182 if (i.op[1].imms->X_op == O_constant) 6183 { 6184 offsetT n = i.op[1].imms->X_add_number; 6185 6186 if (size == 2 6187 && !fits_in_unsigned_word (n) 6188 && !fits_in_signed_word (n)) 6189 { 6190 as_bad (_("16-bit jump out of range")); 6191 return; 6192 } 6193 md_number_to_chars (p, n, size); 6194 } 6195 else 6196 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 6197 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); 6198 if (i.op[0].imms->X_op != O_constant) 6199 as_bad (_("can't handle non absolute segment in `%s'"), 6200 i.tm.name); 6201 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 6202 } 6203 6204 static void 6205 output_insn (void) 6206 { 6207 fragS *insn_start_frag; 6208 offsetT insn_start_off; 6209 6210 /* Tie dwarf2 debug info to the address at the start of the insn. 6211 We can't do this after the insn has been output as the current 6212 frag may have been closed off. eg. by frag_var. */ 6213 dwarf2_emit_insn (0); 6214 6215 insn_start_frag = frag_now; 6216 insn_start_off = frag_now_fix (); 6217 6218 /* Output jumps. */ 6219 if (i.tm.opcode_modifier.jump) 6220 output_branch (); 6221 else if (i.tm.opcode_modifier.jumpbyte 6222 || i.tm.opcode_modifier.jumpdword) 6223 output_jump (); 6224 else if (i.tm.opcode_modifier.jumpintersegment) 6225 output_interseg_jump (); 6226 else 6227 { 6228 /* Output normal instructions here. */ 6229 char *p; 6230 unsigned char *q; 6231 unsigned int j; 6232 unsigned int prefix; 6233 6234 /* Since the VEX prefix contains the implicit prefix, we don't 6235 need the explicit prefix. */ 6236 if (!i.tm.opcode_modifier.vex) 6237 { 6238 switch (i.tm.opcode_length) 6239 { 6240 case 3: 6241 if (i.tm.base_opcode & 0xff000000) 6242 { 6243 prefix = (i.tm.base_opcode >> 24) & 0xff; 6244 goto check_prefix; 6245 } 6246 break; 6247 case 2: 6248 if ((i.tm.base_opcode & 0xff0000) != 0) 6249 { 6250 prefix = (i.tm.base_opcode >> 16) & 0xff; 6251 if (i.tm.cpu_flags.bitfield.cpupadlock) 6252 { 6253 check_prefix: 6254 if (prefix != REPE_PREFIX_OPCODE 6255 || (i.prefix[REP_PREFIX] 6256 != REPE_PREFIX_OPCODE)) 6257 add_prefix (prefix); 6258 } 6259 else 6260 add_prefix (prefix); 6261 } 6262 break; 6263 case 1: 6264 break; 6265 default: 6266 abort (); 6267 } 6268 6269 /* The prefix bytes. */ 6270 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) 6271 if (*q) 6272 FRAG_APPEND_1_CHAR (*q); 6273 } 6274 else 6275 { 6276 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) 6277 if (*q) 6278 switch (j) 6279 { 6280 case REX_PREFIX: 6281 /* REX byte is encoded in VEX prefix. */ 6282 break; 6283 case SEG_PREFIX: 6284 case ADDR_PREFIX: 6285 FRAG_APPEND_1_CHAR (*q); 6286 break; 6287 default: 6288 /* There should be no other prefixes for instructions 6289 with VEX prefix. */ 6290 abort (); 6291 } 6292 6293 /* Now the VEX prefix. */ 6294 p = frag_more (i.vex.length); 6295 for (j = 0; j < i.vex.length; j++) 6296 p[j] = i.vex.bytes[j]; 6297 } 6298 6299 /* Now the opcode; be careful about word order here! */ 6300 if (i.tm.opcode_length == 1) 6301 { 6302 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 6303 } 6304 else 6305 { 6306 switch (i.tm.opcode_length) 6307 { 6308 case 3: 6309 p = frag_more (3); 6310 *p++ = (i.tm.base_opcode >> 16) & 0xff; 6311 break; 6312 case 2: 6313 p = frag_more (2); 6314 break; 6315 default: 6316 abort (); 6317 break; 6318 } 6319 6320 /* Put out high byte first: can't use md_number_to_chars! */ 6321 *p++ = (i.tm.base_opcode >> 8) & 0xff; 6322 *p = i.tm.base_opcode & 0xff; 6323 } 6324 6325 /* Now the modrm byte and sib byte (if present). */ 6326 if (i.tm.opcode_modifier.modrm) 6327 { 6328 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 6329 | i.rm.reg << 3 6330 | i.rm.mode << 6)); 6331 /* If i.rm.regmem == ESP (4) 6332 && i.rm.mode != (Register mode) 6333 && not 16 bit 6334 ==> need second modrm byte. */ 6335 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 6336 && i.rm.mode != 3 6337 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) 6338 FRAG_APPEND_1_CHAR ((i.sib.base << 0 6339 | i.sib.index << 3 6340 | i.sib.scale << 6)); 6341 } 6342 6343 if (i.disp_operands) 6344 output_disp (insn_start_frag, insn_start_off); 6345 6346 if (i.imm_operands) 6347 output_imm (insn_start_frag, insn_start_off); 6348 } 6349 6350 #ifdef DEBUG386 6351 if (flag_debug) 6352 { 6353 pi ("" /*line*/, &i); 6354 } 6355 #endif /* DEBUG386 */ 6356 } 6357 6358 /* Return the size of the displacement operand N. */ 6359 6360 static int 6361 disp_size (unsigned int n) 6362 { 6363 int size = 4; 6364 if (i.types[n].bitfield.disp64) 6365 size = 8; 6366 else if (i.types[n].bitfield.disp8) 6367 size = 1; 6368 else if (i.types[n].bitfield.disp16) 6369 size = 2; 6370 return size; 6371 } 6372 6373 /* Return the size of the immediate operand N. */ 6374 6375 static int 6376 imm_size (unsigned int n) 6377 { 6378 int size = 4; 6379 if (i.types[n].bitfield.imm64) 6380 size = 8; 6381 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) 6382 size = 1; 6383 else if (i.types[n].bitfield.imm16) 6384 size = 2; 6385 return size; 6386 } 6387 6388 static void 6389 output_disp (fragS *insn_start_frag, offsetT insn_start_off) 6390 { 6391 char *p; 6392 unsigned int n; 6393 6394 for (n = 0; n < i.operands; n++) 6395 { 6396 if (operand_type_check (i.types[n], disp)) 6397 { 6398 if (i.op[n].disps->X_op == O_constant) 6399 { 6400 int size = disp_size (n); 6401 offsetT val; 6402 6403 val = offset_in_range (i.op[n].disps->X_add_number, 6404 size); 6405 p = frag_more (size); 6406 md_number_to_chars (p, val, size); 6407 } 6408 else 6409 { 6410 enum bfd_reloc_code_real reloc_type; 6411 int size = disp_size (n); 6412 int sign = i.types[n].bitfield.disp32s; 6413 int pcrel = (i.flags[n] & Operand_PCrel) != 0; 6414 6415 /* We can't have 8 bit displacement here. */ 6416 gas_assert (!i.types[n].bitfield.disp8); 6417 6418 /* The PC relative address is computed relative 6419 to the instruction boundary, so in case immediate 6420 fields follows, we need to adjust the value. */ 6421 if (pcrel && i.imm_operands) 6422 { 6423 unsigned int n1; 6424 int sz = 0; 6425 6426 for (n1 = 0; n1 < i.operands; n1++) 6427 if (operand_type_check (i.types[n1], imm)) 6428 { 6429 /* Only one immediate is allowed for PC 6430 relative address. */ 6431 gas_assert (sz == 0); 6432 sz = imm_size (n1); 6433 i.op[n].disps->X_add_number -= sz; 6434 } 6435 /* We should find the immediate. */ 6436 gas_assert (sz != 0); 6437 } 6438 6439 p = frag_more (size); 6440 reloc_type = reloc (size, pcrel, sign, i.reloc[n]); 6441 if (GOT_symbol 6442 && GOT_symbol == i.op[n].disps->X_add_symbol 6443 && (((reloc_type == BFD_RELOC_32 6444 || reloc_type == BFD_RELOC_X86_64_32S 6445 || (reloc_type == BFD_RELOC_64 6446 && object_64bit)) 6447 && (i.op[n].disps->X_op == O_symbol 6448 || (i.op[n].disps->X_op == O_add 6449 && ((symbol_get_value_expression 6450 (i.op[n].disps->X_op_symbol)->X_op) 6451 == O_subtract)))) 6452 || reloc_type == BFD_RELOC_32_PCREL)) 6453 { 6454 offsetT add; 6455 6456 if (insn_start_frag == frag_now) 6457 add = (p - frag_now->fr_literal) - insn_start_off; 6458 else 6459 { 6460 fragS *fr; 6461 6462 add = insn_start_frag->fr_fix - insn_start_off; 6463 for (fr = insn_start_frag->fr_next; 6464 fr && fr != frag_now; fr = fr->fr_next) 6465 add += fr->fr_fix; 6466 add += p - frag_now->fr_literal; 6467 } 6468 6469 if (!object_64bit) 6470 { 6471 reloc_type = BFD_RELOC_386_GOTPC; 6472 i.op[n].imms->X_add_number += add; 6473 } 6474 else if (reloc_type == BFD_RELOC_64) 6475 reloc_type = BFD_RELOC_X86_64_GOTPC64; 6476 else 6477 /* Don't do the adjustment for x86-64, as there 6478 the pcrel addressing is relative to the _next_ 6479 insn, and that is taken care of in other code. */ 6480 reloc_type = BFD_RELOC_X86_64_GOTPC32; 6481 } 6482 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 6483 i.op[n].disps, pcrel, reloc_type); 6484 } 6485 } 6486 } 6487 } 6488 6489 static void 6490 output_imm (fragS *insn_start_frag, offsetT insn_start_off) 6491 { 6492 char *p; 6493 unsigned int n; 6494 6495 for (n = 0; n < i.operands; n++) 6496 { 6497 if (operand_type_check (i.types[n], imm)) 6498 { 6499 if (i.op[n].imms->X_op == O_constant) 6500 { 6501 int size = imm_size (n); 6502 offsetT val; 6503 6504 val = offset_in_range (i.op[n].imms->X_add_number, 6505 size); 6506 p = frag_more (size); 6507 md_number_to_chars (p, val, size); 6508 } 6509 else 6510 { 6511 /* Not absolute_section. 6512 Need a 32-bit fixup (don't support 8bit 6513 non-absolute imms). Try to support other 6514 sizes ... */ 6515 enum bfd_reloc_code_real reloc_type; 6516 int size = imm_size (n); 6517 int sign; 6518 6519 if (i.types[n].bitfield.imm32s 6520 && (i.suffix == QWORD_MNEM_SUFFIX 6521 || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) 6522 sign = 1; 6523 else 6524 sign = 0; 6525 6526 p = frag_more (size); 6527 reloc_type = reloc (size, 0, sign, i.reloc[n]); 6528 6529 /* This is tough to explain. We end up with this one if we 6530 * have operands that look like 6531 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to 6532 * obtain the absolute address of the GOT, and it is strongly 6533 * preferable from a performance point of view to avoid using 6534 * a runtime relocation for this. The actual sequence of 6535 * instructions often look something like: 6536 * 6537 * call .L66 6538 * .L66: 6539 * popl %ebx 6540 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 6541 * 6542 * The call and pop essentially return the absolute address 6543 * of the label .L66 and store it in %ebx. The linker itself 6544 * will ultimately change the first operand of the addl so 6545 * that %ebx points to the GOT, but to keep things simple, the 6546 * .o file must have this operand set so that it generates not 6547 * the absolute address of .L66, but the absolute address of 6548 * itself. This allows the linker itself simply treat a GOTPC 6549 * relocation as asking for a pcrel offset to the GOT to be 6550 * added in, and the addend of the relocation is stored in the 6551 * operand field for the instruction itself. 6552 * 6553 * Our job here is to fix the operand so that it would add 6554 * the correct offset so that %ebx would point to itself. The 6555 * thing that is tricky is that .-.L66 will point to the 6556 * beginning of the instruction, so we need to further modify 6557 * the operand so that it will point to itself. There are 6558 * other cases where you have something like: 6559 * 6560 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 6561 * 6562 * and here no correction would be required. Internally in 6563 * the assembler we treat operands of this form as not being 6564 * pcrel since the '.' is explicitly mentioned, and I wonder 6565 * whether it would simplify matters to do it this way. Who 6566 * knows. In earlier versions of the PIC patches, the 6567 * pcrel_adjust field was used to store the correction, but 6568 * since the expression is not pcrel, I felt it would be 6569 * confusing to do it this way. */ 6570 6571 if ((reloc_type == BFD_RELOC_32 6572 || reloc_type == BFD_RELOC_X86_64_32S 6573 || reloc_type == BFD_RELOC_64) 6574 && GOT_symbol 6575 && GOT_symbol == i.op[n].imms->X_add_symbol 6576 && (i.op[n].imms->X_op == O_symbol 6577 || (i.op[n].imms->X_op == O_add 6578 && ((symbol_get_value_expression 6579 (i.op[n].imms->X_op_symbol)->X_op) 6580 == O_subtract)))) 6581 { 6582 offsetT add; 6583 6584 if (insn_start_frag == frag_now) 6585 add = (p - frag_now->fr_literal) - insn_start_off; 6586 else 6587 { 6588 fragS *fr; 6589 6590 add = insn_start_frag->fr_fix - insn_start_off; 6591 for (fr = insn_start_frag->fr_next; 6592 fr && fr != frag_now; fr = fr->fr_next) 6593 add += fr->fr_fix; 6594 add += p - frag_now->fr_literal; 6595 } 6596 6597 if (!object_64bit) 6598 reloc_type = BFD_RELOC_386_GOTPC; 6599 else if (size == 4) 6600 reloc_type = BFD_RELOC_X86_64_GOTPC32; 6601 else if (size == 8) 6602 reloc_type = BFD_RELOC_X86_64_GOTPC64; 6603 i.op[n].imms->X_add_number += add; 6604 } 6605 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 6606 i.op[n].imms, 0, reloc_type); 6607 } 6608 } 6609 } 6610 } 6611 6612 /* x86_cons_fix_new is called via the expression parsing code when a 6613 reloc is needed. We use this hook to get the correct .got reloc. */ 6614 static enum bfd_reloc_code_real got_reloc = NO_RELOC; 6615 static int cons_sign = -1; 6616 6617 void 6618 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, 6619 expressionS *exp) 6620 { 6621 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); 6622 6623 got_reloc = NO_RELOC; 6624 6625 #ifdef TE_PE 6626 if (exp->X_op == O_secrel) 6627 { 6628 exp->X_op = O_symbol; 6629 r = BFD_RELOC_32_SECREL; 6630 } 6631 #endif 6632 6633 fix_new_exp (frag, off, len, exp, 0, r); 6634 } 6635 6636 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the 6637 purpose of the `.dc.a' internal pseudo-op. */ 6638 6639 int 6640 x86_address_bytes (void) 6641 { 6642 if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) 6643 return 4; 6644 return stdoutput->arch_info->bits_per_address / 8; 6645 } 6646 6647 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ 6648 || defined (LEX_AT) 6649 # define lex_got(reloc, adjust, types) NULL 6650 #else 6651 /* Parse operands of the form 6652 <symbol>@GOTOFF+<nnn> 6653 and similar .plt or .got references. 6654 6655 If we find one, set up the correct relocation in RELOC and copy the 6656 input string, minus the `@GOTOFF' into a malloc'd buffer for 6657 parsing by the calling routine. Return this buffer, and if ADJUST 6658 is non-null set it to the length of the string we removed from the 6659 input line. Otherwise return NULL. */ 6660 static char * 6661 lex_got (enum bfd_reloc_code_real *rel, 6662 int *adjust, 6663 i386_operand_type *types) 6664 { 6665 /* Some of the relocations depend on the size of what field is to 6666 be relocated. But in our callers i386_immediate and i386_displacement 6667 we don't yet know the operand size (this will be set by insn 6668 matching). Hence we record the word32 relocation here, 6669 and adjust the reloc according to the real size in reloc(). */ 6670 static const struct { 6671 const char *str; 6672 int len; 6673 const enum bfd_reloc_code_real rel[2]; 6674 const i386_operand_type types64; 6675 } gotrel[] = { 6676 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, 6677 BFD_RELOC_X86_64_PLTOFF64 }, 6678 OPERAND_TYPE_IMM64 }, 6679 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, 6680 BFD_RELOC_X86_64_PLT32 }, 6681 OPERAND_TYPE_IMM32_32S_DISP32 }, 6682 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, 6683 BFD_RELOC_X86_64_GOTPLT64 }, 6684 OPERAND_TYPE_IMM64_DISP64 }, 6685 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, 6686 BFD_RELOC_X86_64_GOTOFF64 }, 6687 OPERAND_TYPE_IMM64_DISP64 }, 6688 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, 6689 BFD_RELOC_X86_64_GOTPCREL }, 6690 OPERAND_TYPE_IMM32_32S_DISP32 }, 6691 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, 6692 BFD_RELOC_X86_64_TLSGD }, 6693 OPERAND_TYPE_IMM32_32S_DISP32 }, 6694 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, 6695 _dummy_first_bfd_reloc_code_real }, 6696 OPERAND_TYPE_NONE }, 6697 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, 6698 BFD_RELOC_X86_64_TLSLD }, 6699 OPERAND_TYPE_IMM32_32S_DISP32 }, 6700 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, 6701 BFD_RELOC_X86_64_GOTTPOFF }, 6702 OPERAND_TYPE_IMM32_32S_DISP32 }, 6703 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, 6704 BFD_RELOC_X86_64_TPOFF32 }, 6705 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 6706 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, 6707 _dummy_first_bfd_reloc_code_real }, 6708 OPERAND_TYPE_NONE }, 6709 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, 6710 BFD_RELOC_X86_64_DTPOFF32 }, 6711 OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, 6712 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, 6713 _dummy_first_bfd_reloc_code_real }, 6714 OPERAND_TYPE_NONE }, 6715 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, 6716 _dummy_first_bfd_reloc_code_real }, 6717 OPERAND_TYPE_NONE }, 6718 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, 6719 BFD_RELOC_X86_64_GOT32 }, 6720 OPERAND_TYPE_IMM32_32S_64_DISP32 }, 6721 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, 6722 BFD_RELOC_X86_64_GOTPC32_TLSDESC }, 6723 OPERAND_TYPE_IMM32_32S_DISP32 }, 6724 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, 6725 BFD_RELOC_X86_64_TLSDESC_CALL }, 6726 OPERAND_TYPE_IMM32_32S_DISP32 }, 6727 }; 6728 char *cp; 6729 unsigned int j; 6730 6731 #if defined (OBJ_MAYBE_ELF) 6732 if (!IS_ELF) 6733 return NULL; 6734 #endif 6735 6736 for (cp = input_line_pointer; *cp != '@'; cp++) 6737 if (is_end_of_line[(unsigned char) *cp] || *cp == ',') 6738 return NULL; 6739 6740 for (j = 0; j < ARRAY_SIZE (gotrel); j++) 6741 { 6742 int len = gotrel[j].len; 6743 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 6744 { 6745 if (gotrel[j].rel[object_64bit] != 0) 6746 { 6747 int first, second; 6748 char *tmpbuf, *past_reloc; 6749 6750 *rel = gotrel[j].rel[object_64bit]; 6751 if (adjust) 6752 *adjust = len; 6753 6754 if (types) 6755 { 6756 if (flag_code != CODE_64BIT) 6757 { 6758 types->bitfield.imm32 = 1; 6759 types->bitfield.disp32 = 1; 6760 } 6761 else 6762 *types = gotrel[j].types64; 6763 } 6764 6765 if (GOT_symbol == NULL) 6766 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 6767 6768 /* The length of the first part of our input line. */ 6769 first = cp - input_line_pointer; 6770 6771 /* The second part goes from after the reloc token until 6772 (and including) an end_of_line char or comma. */ 6773 past_reloc = cp + 1 + len; 6774 cp = past_reloc; 6775 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') 6776 ++cp; 6777 second = cp + 1 - past_reloc; 6778 6779 /* Allocate and copy string. The trailing NUL shouldn't 6780 be necessary, but be safe. */ 6781 tmpbuf = (char *) xmalloc (first + second + 2); 6782 memcpy (tmpbuf, input_line_pointer, first); 6783 if (second != 0 && *past_reloc != ' ') 6784 /* Replace the relocation token with ' ', so that 6785 errors like foo@GOTOFF1 will be detected. */ 6786 tmpbuf[first++] = ' '; 6787 memcpy (tmpbuf + first, past_reloc, second); 6788 tmpbuf[first + second] = '\0'; 6789 return tmpbuf; 6790 } 6791 6792 as_bad (_("@%s reloc is not supported with %d-bit output format"), 6793 gotrel[j].str, 1 << (5 + object_64bit)); 6794 return NULL; 6795 } 6796 } 6797 6798 /* Might be a symbol version string. Don't as_bad here. */ 6799 return NULL; 6800 } 6801 #endif 6802 6803 void 6804 x86_cons (expressionS *exp, int size) 6805 { 6806 intel_syntax = -intel_syntax; 6807 6808 exp->X_md = 0; 6809 if (size == 4 || (object_64bit && size == 8)) 6810 { 6811 /* Handle @GOTOFF and the like in an expression. */ 6812 char *save; 6813 char *gotfree_input_line; 6814 int adjust = 0; 6815 6816 save = input_line_pointer; 6817 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); 6818 if (gotfree_input_line) 6819 input_line_pointer = gotfree_input_line; 6820 6821 expression (exp); 6822 6823 if (gotfree_input_line) 6824 { 6825 /* expression () has merrily parsed up to the end of line, 6826 or a comma - in the wrong buffer. Transfer how far 6827 input_line_pointer has moved to the right buffer. */ 6828 input_line_pointer = (save 6829 + (input_line_pointer - gotfree_input_line) 6830 + adjust); 6831 free (gotfree_input_line); 6832 if (exp->X_op == O_constant 6833 || exp->X_op == O_absent 6834 || exp->X_op == O_illegal 6835 || exp->X_op == O_register 6836 || exp->X_op == O_big) 6837 { 6838 char c = *input_line_pointer; 6839 *input_line_pointer = 0; 6840 as_bad (_("missing or invalid expression `%s'"), save); 6841 *input_line_pointer = c; 6842 } 6843 } 6844 } 6845 else 6846 expression (exp); 6847 6848 intel_syntax = -intel_syntax; 6849 6850 if (intel_syntax) 6851 i386_intel_simplify (exp); 6852 } 6853 6854 static void 6855 signed_cons (int size) 6856 { 6857 if (flag_code == CODE_64BIT) 6858 cons_sign = 1; 6859 cons (size); 6860 cons_sign = -1; 6861 } 6862 6863 #ifdef TE_PE 6864 static void 6865 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 6866 { 6867 expressionS exp; 6868 6869 do 6870 { 6871 expression (&exp); 6872 if (exp.X_op == O_symbol) 6873 exp.X_op = O_secrel; 6874 6875 emit_expr (&exp, 4); 6876 } 6877 while (*input_line_pointer++ == ','); 6878 6879 input_line_pointer--; 6880 demand_empty_rest_of_line (); 6881 } 6882 #endif 6883 6884 static int 6885 i386_immediate (char *imm_start) 6886 { 6887 char *save_input_line_pointer; 6888 char *gotfree_input_line; 6889 segT exp_seg = 0; 6890 expressionS *exp; 6891 i386_operand_type types; 6892 6893 operand_type_set (&types, ~0); 6894 6895 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 6896 { 6897 as_bad (_("at most %d immediate operands are allowed"), 6898 MAX_IMMEDIATE_OPERANDS); 6899 return 0; 6900 } 6901 6902 exp = &im_expressions[i.imm_operands++]; 6903 i.op[this_operand].imms = exp; 6904 6905 if (is_space_char (*imm_start)) 6906 ++imm_start; 6907 6908 save_input_line_pointer = input_line_pointer; 6909 input_line_pointer = imm_start; 6910 6911 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 6912 if (gotfree_input_line) 6913 input_line_pointer = gotfree_input_line; 6914 6915 exp_seg = expression (exp); 6916 6917 SKIP_WHITESPACE (); 6918 if (*input_line_pointer) 6919 as_bad (_("junk `%s' after expression"), input_line_pointer); 6920 6921 input_line_pointer = save_input_line_pointer; 6922 if (gotfree_input_line) 6923 { 6924 free (gotfree_input_line); 6925 6926 if (exp->X_op == O_constant || exp->X_op == O_register) 6927 exp->X_op = O_illegal; 6928 } 6929 6930 return i386_finalize_immediate (exp_seg, exp, types, imm_start); 6931 } 6932 6933 static int 6934 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, 6935 i386_operand_type types, const char *imm_start) 6936 { 6937 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) 6938 { 6939 if (imm_start) 6940 as_bad (_("missing or invalid immediate expression `%s'"), 6941 imm_start); 6942 return 0; 6943 } 6944 else if (exp->X_op == O_constant) 6945 { 6946 /* Size it properly later. */ 6947 i.types[this_operand].bitfield.imm64 = 1; 6948 /* If not 64bit, sign extend val. */ 6949 if (flag_code != CODE_64BIT 6950 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) 6951 exp->X_add_number 6952 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 6953 } 6954 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 6955 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour 6956 && exp_seg != absolute_section 6957 && exp_seg != text_section 6958 && exp_seg != data_section 6959 && exp_seg != bss_section 6960 && exp_seg != undefined_section 6961 && !bfd_is_com_section (exp_seg)) 6962 { 6963 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 6964 return 0; 6965 } 6966 #endif 6967 else if (!intel_syntax && exp->X_op == O_register) 6968 { 6969 if (imm_start) 6970 as_bad (_("illegal immediate register operand %s"), imm_start); 6971 return 0; 6972 } 6973 else 6974 { 6975 /* This is an address. The size of the address will be 6976 determined later, depending on destination register, 6977 suffix, or the default for the section. */ 6978 i.types[this_operand].bitfield.imm8 = 1; 6979 i.types[this_operand].bitfield.imm16 = 1; 6980 i.types[this_operand].bitfield.imm32 = 1; 6981 i.types[this_operand].bitfield.imm32s = 1; 6982 i.types[this_operand].bitfield.imm64 = 1; 6983 i.types[this_operand] = operand_type_and (i.types[this_operand], 6984 types); 6985 } 6986 6987 return 1; 6988 } 6989 6990 static char * 6991 i386_scale (char *scale) 6992 { 6993 offsetT val; 6994 char *save = input_line_pointer; 6995 6996 input_line_pointer = scale; 6997 val = get_absolute_expression (); 6998 6999 switch (val) 7000 { 7001 case 1: 7002 i.log2_scale_factor = 0; 7003 break; 7004 case 2: 7005 i.log2_scale_factor = 1; 7006 break; 7007 case 4: 7008 i.log2_scale_factor = 2; 7009 break; 7010 case 8: 7011 i.log2_scale_factor = 3; 7012 break; 7013 default: 7014 { 7015 char sep = *input_line_pointer; 7016 7017 *input_line_pointer = '\0'; 7018 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 7019 scale); 7020 *input_line_pointer = sep; 7021 input_line_pointer = save; 7022 return NULL; 7023 } 7024 } 7025 if (i.log2_scale_factor != 0 && i.index_reg == 0) 7026 { 7027 as_warn (_("scale factor of %d without an index register"), 7028 1 << i.log2_scale_factor); 7029 i.log2_scale_factor = 0; 7030 } 7031 scale = input_line_pointer; 7032 input_line_pointer = save; 7033 return scale; 7034 } 7035 7036 static int 7037 i386_displacement (char *disp_start, char *disp_end) 7038 { 7039 expressionS *exp; 7040 segT exp_seg = 0; 7041 char *save_input_line_pointer; 7042 char *gotfree_input_line; 7043 int override; 7044 i386_operand_type bigdisp, types = anydisp; 7045 int ret; 7046 7047 if (i.disp_operands == MAX_MEMORY_OPERANDS) 7048 { 7049 as_bad (_("at most %d displacement operands are allowed"), 7050 MAX_MEMORY_OPERANDS); 7051 return 0; 7052 } 7053 7054 operand_type_set (&bigdisp, 0); 7055 if ((i.types[this_operand].bitfield.jumpabsolute) 7056 || (!current_templates->start->opcode_modifier.jump 7057 && !current_templates->start->opcode_modifier.jumpdword)) 7058 { 7059 bigdisp.bitfield.disp32 = 1; 7060 override = (i.prefix[ADDR_PREFIX] != 0); 7061 if (flag_code == CODE_64BIT) 7062 { 7063 if (!override) 7064 { 7065 bigdisp.bitfield.disp32s = 1; 7066 bigdisp.bitfield.disp64 = 1; 7067 } 7068 } 7069 else if ((flag_code == CODE_16BIT) ^ override) 7070 { 7071 bigdisp.bitfield.disp32 = 0; 7072 bigdisp.bitfield.disp16 = 1; 7073 } 7074 } 7075 else 7076 { 7077 /* For PC-relative branches, the width of the displacement 7078 is dependent upon data size, not address size. */ 7079 override = (i.prefix[DATA_PREFIX] != 0); 7080 if (flag_code == CODE_64BIT) 7081 { 7082 if (override || i.suffix == WORD_MNEM_SUFFIX) 7083 bigdisp.bitfield.disp16 = 1; 7084 else 7085 { 7086 bigdisp.bitfield.disp32 = 1; 7087 bigdisp.bitfield.disp32s = 1; 7088 } 7089 } 7090 else 7091 { 7092 if (!override) 7093 override = (i.suffix == (flag_code != CODE_16BIT 7094 ? WORD_MNEM_SUFFIX 7095 : LONG_MNEM_SUFFIX)); 7096 bigdisp.bitfield.disp32 = 1; 7097 if ((flag_code == CODE_16BIT) ^ override) 7098 { 7099 bigdisp.bitfield.disp32 = 0; 7100 bigdisp.bitfield.disp16 = 1; 7101 } 7102 } 7103 } 7104 i.types[this_operand] = operand_type_or (i.types[this_operand], 7105 bigdisp); 7106 7107 exp = &disp_expressions[i.disp_operands]; 7108 i.op[this_operand].disps = exp; 7109 i.disp_operands++; 7110 save_input_line_pointer = input_line_pointer; 7111 input_line_pointer = disp_start; 7112 END_STRING_AND_SAVE (disp_end); 7113 7114 #ifndef GCC_ASM_O_HACK 7115 #define GCC_ASM_O_HACK 0 7116 #endif 7117 #if GCC_ASM_O_HACK 7118 END_STRING_AND_SAVE (disp_end + 1); 7119 if (i.types[this_operand].bitfield.baseIndex 7120 && displacement_string_end[-1] == '+') 7121 { 7122 /* This hack is to avoid a warning when using the "o" 7123 constraint within gcc asm statements. 7124 For instance: 7125 7126 #define _set_tssldt_desc(n,addr,limit,type) \ 7127 __asm__ __volatile__ ( \ 7128 "movw %w2,%0\n\t" \ 7129 "movw %w1,2+%0\n\t" \ 7130 "rorl $16,%1\n\t" \ 7131 "movb %b1,4+%0\n\t" \ 7132 "movb %4,5+%0\n\t" \ 7133 "movb $0,6+%0\n\t" \ 7134 "movb %h1,7+%0\n\t" \ 7135 "rorl $16,%1" \ 7136 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 7137 7138 This works great except that the output assembler ends 7139 up looking a bit weird if it turns out that there is 7140 no offset. You end up producing code that looks like: 7141 7142 #APP 7143 movw $235,(%eax) 7144 movw %dx,2+(%eax) 7145 rorl $16,%edx 7146 movb %dl,4+(%eax) 7147 movb $137,5+(%eax) 7148 movb $0,6+(%eax) 7149 movb %dh,7+(%eax) 7150 rorl $16,%edx 7151 #NO_APP 7152 7153 So here we provide the missing zero. */ 7154 7155 *displacement_string_end = '0'; 7156 } 7157 #endif 7158 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 7159 if (gotfree_input_line) 7160 input_line_pointer = gotfree_input_line; 7161 7162 exp_seg = expression (exp); 7163 7164 SKIP_WHITESPACE (); 7165 if (*input_line_pointer) 7166 as_bad (_("junk `%s' after expression"), input_line_pointer); 7167 #if GCC_ASM_O_HACK 7168 RESTORE_END_STRING (disp_end + 1); 7169 #endif 7170 input_line_pointer = save_input_line_pointer; 7171 if (gotfree_input_line) 7172 { 7173 free (gotfree_input_line); 7174 7175 if (exp->X_op == O_constant || exp->X_op == O_register) 7176 exp->X_op = O_illegal; 7177 } 7178 7179 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); 7180 7181 RESTORE_END_STRING (disp_end); 7182 7183 return ret; 7184 } 7185 7186 static int 7187 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, 7188 i386_operand_type types, const char *disp_start) 7189 { 7190 i386_operand_type bigdisp; 7191 int ret = 1; 7192 7193 /* We do this to make sure that the section symbol is in 7194 the symbol table. We will ultimately change the relocation 7195 to be relative to the beginning of the section. */ 7196 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF 7197 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 7198 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 7199 { 7200 if (exp->X_op != O_symbol) 7201 goto inv_disp; 7202 7203 if (S_IS_LOCAL (exp->X_add_symbol) 7204 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section 7205 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) 7206 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 7207 exp->X_op = O_subtract; 7208 exp->X_op_symbol = GOT_symbol; 7209 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 7210 i.reloc[this_operand] = BFD_RELOC_32_PCREL; 7211 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 7212 i.reloc[this_operand] = BFD_RELOC_64; 7213 else 7214 i.reloc[this_operand] = BFD_RELOC_32; 7215 } 7216 7217 else if (exp->X_op == O_absent 7218 || exp->X_op == O_illegal 7219 || exp->X_op == O_big) 7220 { 7221 inv_disp: 7222 as_bad (_("missing or invalid displacement expression `%s'"), 7223 disp_start); 7224 ret = 0; 7225 } 7226 7227 else if (flag_code == CODE_64BIT 7228 && !i.prefix[ADDR_PREFIX] 7229 && exp->X_op == O_constant) 7230 { 7231 /* Since displacement is signed extended to 64bit, don't allow 7232 disp32 and turn off disp32s if they are out of range. */ 7233 i.types[this_operand].bitfield.disp32 = 0; 7234 if (!fits_in_signed_long (exp->X_add_number)) 7235 { 7236 i.types[this_operand].bitfield.disp32s = 0; 7237 if (i.types[this_operand].bitfield.baseindex) 7238 { 7239 as_bad (_("0x%lx out range of signed 32bit displacement"), 7240 (long) exp->X_add_number); 7241 ret = 0; 7242 } 7243 } 7244 } 7245 7246 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 7247 else if (exp->X_op != O_constant 7248 && OUTPUT_FLAVOR == bfd_target_aout_flavour 7249 && exp_seg != absolute_section 7250 && exp_seg != text_section 7251 && exp_seg != data_section 7252 && exp_seg != bss_section 7253 && exp_seg != undefined_section 7254 && !bfd_is_com_section (exp_seg)) 7255 { 7256 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 7257 ret = 0; 7258 } 7259 #endif 7260 7261 /* Check if this is a displacement only operand. */ 7262 bigdisp = i.types[this_operand]; 7263 bigdisp.bitfield.disp8 = 0; 7264 bigdisp.bitfield.disp16 = 0; 7265 bigdisp.bitfield.disp32 = 0; 7266 bigdisp.bitfield.disp32s = 0; 7267 bigdisp.bitfield.disp64 = 0; 7268 if (operand_type_all_zero (&bigdisp)) 7269 i.types[this_operand] = operand_type_and (i.types[this_operand], 7270 types); 7271 7272 return ret; 7273 } 7274 7275 /* Make sure the memory operand we've been dealt is valid. 7276 Return 1 on success, 0 on a failure. */ 7277 7278 static int 7279 i386_index_check (const char *operand_string) 7280 { 7281 int ok; 7282 const char *kind = "base/index"; 7283 #if INFER_ADDR_PREFIX 7284 int fudged = 0; 7285 7286 tryprefix: 7287 #endif 7288 ok = 1; 7289 if (current_templates->start->opcode_modifier.isstring 7290 && !current_templates->start->opcode_modifier.immext 7291 && (current_templates->end[-1].opcode_modifier.isstring 7292 || i.mem_operands)) 7293 { 7294 /* Memory operands of string insns are special in that they only allow 7295 a single register (rDI, rSI, or rBX) as their memory address. */ 7296 unsigned int expected; 7297 7298 kind = "string address"; 7299 7300 if (current_templates->start->opcode_modifier.w) 7301 { 7302 i386_operand_type type = current_templates->end[-1].operand_types[0]; 7303 7304 if (!type.bitfield.baseindex 7305 || ((!i.mem_operands != !intel_syntax) 7306 && current_templates->end[-1].operand_types[1] 7307 .bitfield.baseindex)) 7308 type = current_templates->end[-1].operand_types[1]; 7309 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; 7310 } 7311 else 7312 expected = 3 /* rBX */; 7313 7314 if (!i.base_reg || i.index_reg 7315 || operand_type_check (i.types[this_operand], disp)) 7316 ok = -1; 7317 else if (!(flag_code == CODE_64BIT 7318 ? i.prefix[ADDR_PREFIX] 7319 ? i.base_reg->reg_type.bitfield.reg32 7320 : i.base_reg->reg_type.bitfield.reg64 7321 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] 7322 ? i.base_reg->reg_type.bitfield.reg32 7323 : i.base_reg->reg_type.bitfield.reg16)) 7324 ok = 0; 7325 else if (i.base_reg->reg_num != expected) 7326 ok = -1; 7327 7328 if (ok < 0) 7329 { 7330 unsigned int j; 7331 7332 for (j = 0; j < i386_regtab_size; ++j) 7333 if ((flag_code == CODE_64BIT 7334 ? i.prefix[ADDR_PREFIX] 7335 ? i386_regtab[j].reg_type.bitfield.reg32 7336 : i386_regtab[j].reg_type.bitfield.reg64 7337 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] 7338 ? i386_regtab[j].reg_type.bitfield.reg32 7339 : i386_regtab[j].reg_type.bitfield.reg16) 7340 && i386_regtab[j].reg_num == expected) 7341 break; 7342 gas_assert (j < i386_regtab_size); 7343 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), 7344 operand_string, 7345 intel_syntax ? '[' : '(', 7346 register_prefix, 7347 i386_regtab[j].reg_name, 7348 intel_syntax ? ']' : ')'); 7349 ok = 1; 7350 } 7351 } 7352 else if (flag_code == CODE_64BIT) 7353 { 7354 if ((i.base_reg 7355 && ((i.prefix[ADDR_PREFIX] == 0 7356 && !i.base_reg->reg_type.bitfield.reg64) 7357 || (i.prefix[ADDR_PREFIX] 7358 && !i.base_reg->reg_type.bitfield.reg32)) 7359 && (i.index_reg 7360 || i.base_reg->reg_num != 7361 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) 7362 || (i.index_reg 7363 && !(i.index_reg->reg_type.bitfield.regxmm 7364 || i.index_reg->reg_type.bitfield.regymm) 7365 && (!i.index_reg->reg_type.bitfield.baseindex 7366 || (i.prefix[ADDR_PREFIX] == 0 7367 && i.index_reg->reg_num != RegRiz 7368 && !i.index_reg->reg_type.bitfield.reg64 7369 ) 7370 || (i.prefix[ADDR_PREFIX] 7371 && i.index_reg->reg_num != RegEiz 7372 && !i.index_reg->reg_type.bitfield.reg32)))) 7373 ok = 0; 7374 } 7375 else 7376 { 7377 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 7378 { 7379 /* 16bit checks. */ 7380 if ((i.base_reg 7381 && (!i.base_reg->reg_type.bitfield.reg16 7382 || !i.base_reg->reg_type.bitfield.baseindex)) 7383 || (i.index_reg 7384 && (!i.index_reg->reg_type.bitfield.reg16 7385 || !i.index_reg->reg_type.bitfield.baseindex 7386 || !(i.base_reg 7387 && i.base_reg->reg_num < 6 7388 && i.index_reg->reg_num >= 6 7389 && i.log2_scale_factor == 0)))) 7390 ok = 0; 7391 } 7392 else 7393 { 7394 /* 32bit checks. */ 7395 if ((i.base_reg 7396 && !i.base_reg->reg_type.bitfield.reg32) 7397 || (i.index_reg 7398 && !i.index_reg->reg_type.bitfield.regxmm 7399 && !i.index_reg->reg_type.bitfield.regymm 7400 && ((!i.index_reg->reg_type.bitfield.reg32 7401 && i.index_reg->reg_num != RegEiz) 7402 || !i.index_reg->reg_type.bitfield.baseindex))) 7403 ok = 0; 7404 } 7405 } 7406 if (!ok) 7407 { 7408 #if INFER_ADDR_PREFIX 7409 if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) 7410 { 7411 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 7412 i.prefixes += 1; 7413 /* Change the size of any displacement too. At most one of 7414 Disp16 or Disp32 is set. 7415 FIXME. There doesn't seem to be any real need for separate 7416 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. 7417 Removing them would probably clean up the code quite a lot. */ 7418 if (flag_code != CODE_64BIT 7419 && (i.types[this_operand].bitfield.disp16 7420 || i.types[this_operand].bitfield.disp32)) 7421 i.types[this_operand] 7422 = operand_type_xor (i.types[this_operand], disp16_32); 7423 fudged = 1; 7424 goto tryprefix; 7425 } 7426 if (fudged) 7427 as_bad (_("`%s' is not a valid %s expression"), 7428 operand_string, 7429 kind); 7430 else 7431 #endif 7432 as_bad (_("`%s' is not a valid %s-bit %s expression"), 7433 operand_string, 7434 flag_code_names[i.prefix[ADDR_PREFIX] 7435 ? flag_code == CODE_32BIT 7436 ? CODE_16BIT 7437 : CODE_32BIT 7438 : flag_code], 7439 kind); 7440 } 7441 return ok; 7442 } 7443 7444 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero 7445 on error. */ 7446 7447 static int 7448 i386_att_operand (char *operand_string) 7449 { 7450 const reg_entry *r; 7451 char *end_op; 7452 char *op_string = operand_string; 7453 7454 if (is_space_char (*op_string)) 7455 ++op_string; 7456 7457 /* We check for an absolute prefix (differentiating, 7458 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 7459 if (*op_string == ABSOLUTE_PREFIX) 7460 { 7461 ++op_string; 7462 if (is_space_char (*op_string)) 7463 ++op_string; 7464 i.types[this_operand].bitfield.jumpabsolute = 1; 7465 } 7466 7467 /* Check if operand is a register. */ 7468 if ((r = parse_register (op_string, &end_op)) != NULL) 7469 { 7470 i386_operand_type temp; 7471 7472 /* Check for a segment override by searching for ':' after a 7473 segment register. */ 7474 op_string = end_op; 7475 if (is_space_char (*op_string)) 7476 ++op_string; 7477 if (*op_string == ':' 7478 && (r->reg_type.bitfield.sreg2 7479 || r->reg_type.bitfield.sreg3)) 7480 { 7481 switch (r->reg_num) 7482 { 7483 case 0: 7484 i.seg[i.mem_operands] = &es; 7485 break; 7486 case 1: 7487 i.seg[i.mem_operands] = &cs; 7488 break; 7489 case 2: 7490 i.seg[i.mem_operands] = &ss; 7491 break; 7492 case 3: 7493 i.seg[i.mem_operands] = &ds; 7494 break; 7495 case 4: 7496 i.seg[i.mem_operands] = &fs; 7497 break; 7498 case 5: 7499 i.seg[i.mem_operands] = &gs; 7500 break; 7501 } 7502 7503 /* Skip the ':' and whitespace. */ 7504 ++op_string; 7505 if (is_space_char (*op_string)) 7506 ++op_string; 7507 7508 if (!is_digit_char (*op_string) 7509 && !is_identifier_char (*op_string) 7510 && *op_string != '(' 7511 && *op_string != ABSOLUTE_PREFIX) 7512 { 7513 as_bad (_("bad memory operand `%s'"), op_string); 7514 return 0; 7515 } 7516 /* Handle case of %es:*foo. */ 7517 if (*op_string == ABSOLUTE_PREFIX) 7518 { 7519 ++op_string; 7520 if (is_space_char (*op_string)) 7521 ++op_string; 7522 i.types[this_operand].bitfield.jumpabsolute = 1; 7523 } 7524 goto do_memory_reference; 7525 } 7526 if (*op_string) 7527 { 7528 as_bad (_("junk `%s' after register"), op_string); 7529 return 0; 7530 } 7531 temp = r->reg_type; 7532 temp.bitfield.baseindex = 0; 7533 i.types[this_operand] = operand_type_or (i.types[this_operand], 7534 temp); 7535 i.types[this_operand].bitfield.unspecified = 0; 7536 i.op[this_operand].regs = r; 7537 i.reg_operands++; 7538 } 7539 else if (*op_string == REGISTER_PREFIX) 7540 { 7541 as_bad (_("bad register name `%s'"), op_string); 7542 return 0; 7543 } 7544 else if (*op_string == IMMEDIATE_PREFIX) 7545 { 7546 ++op_string; 7547 if (i.types[this_operand].bitfield.jumpabsolute) 7548 { 7549 as_bad (_("immediate operand illegal with absolute jump")); 7550 return 0; 7551 } 7552 if (!i386_immediate (op_string)) 7553 return 0; 7554 } 7555 else if (is_digit_char (*op_string) 7556 || is_identifier_char (*op_string) 7557 || *op_string == '(') 7558 { 7559 /* This is a memory reference of some sort. */ 7560 char *base_string; 7561 7562 /* Start and end of displacement string expression (if found). */ 7563 char *displacement_string_start; 7564 char *displacement_string_end; 7565 7566 do_memory_reference: 7567 if ((i.mem_operands == 1 7568 && !current_templates->start->opcode_modifier.isstring) 7569 || i.mem_operands == 2) 7570 { 7571 as_bad (_("too many memory references for `%s'"), 7572 current_templates->start->name); 7573 return 0; 7574 } 7575 7576 /* Check for base index form. We detect the base index form by 7577 looking for an ')' at the end of the operand, searching 7578 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 7579 after the '('. */ 7580 base_string = op_string + strlen (op_string); 7581 7582 --base_string; 7583 if (is_space_char (*base_string)) 7584 --base_string; 7585 7586 /* If we only have a displacement, set-up for it to be parsed later. */ 7587 displacement_string_start = op_string; 7588 displacement_string_end = base_string + 1; 7589 7590 if (*base_string == ')') 7591 { 7592 char *temp_string; 7593 unsigned int parens_balanced = 1; 7594 /* We've already checked that the number of left & right ()'s are 7595 equal, so this loop will not be infinite. */ 7596 do 7597 { 7598 base_string--; 7599 if (*base_string == ')') 7600 parens_balanced++; 7601 if (*base_string == '(') 7602 parens_balanced--; 7603 } 7604 while (parens_balanced); 7605 7606 temp_string = base_string; 7607 7608 /* Skip past '(' and whitespace. */ 7609 ++base_string; 7610 if (is_space_char (*base_string)) 7611 ++base_string; 7612 7613 if (*base_string == ',' 7614 || ((i.base_reg = parse_register (base_string, &end_op)) 7615 != NULL)) 7616 { 7617 displacement_string_end = temp_string; 7618 7619 i.types[this_operand].bitfield.baseindex = 1; 7620 7621 if (i.base_reg) 7622 { 7623 base_string = end_op; 7624 if (is_space_char (*base_string)) 7625 ++base_string; 7626 } 7627 7628 /* There may be an index reg or scale factor here. */ 7629 if (*base_string == ',') 7630 { 7631 ++base_string; 7632 if (is_space_char (*base_string)) 7633 ++base_string; 7634 7635 if ((i.index_reg = parse_register (base_string, &end_op)) 7636 != NULL) 7637 { 7638 base_string = end_op; 7639 if (is_space_char (*base_string)) 7640 ++base_string; 7641 if (*base_string == ',') 7642 { 7643 ++base_string; 7644 if (is_space_char (*base_string)) 7645 ++base_string; 7646 } 7647 else if (*base_string != ')') 7648 { 7649 as_bad (_("expecting `,' or `)' " 7650 "after index register in `%s'"), 7651 operand_string); 7652 return 0; 7653 } 7654 } 7655 else if (*base_string == REGISTER_PREFIX) 7656 { 7657 as_bad (_("bad register name `%s'"), base_string); 7658 return 0; 7659 } 7660 7661 /* Check for scale factor. */ 7662 if (*base_string != ')') 7663 { 7664 char *end_scale = i386_scale (base_string); 7665 7666 if (!end_scale) 7667 return 0; 7668 7669 base_string = end_scale; 7670 if (is_space_char (*base_string)) 7671 ++base_string; 7672 if (*base_string != ')') 7673 { 7674 as_bad (_("expecting `)' " 7675 "after scale factor in `%s'"), 7676 operand_string); 7677 return 0; 7678 } 7679 } 7680 else if (!i.index_reg) 7681 { 7682 as_bad (_("expecting index register or scale factor " 7683 "after `,'; got '%c'"), 7684 *base_string); 7685 return 0; 7686 } 7687 } 7688 else if (*base_string != ')') 7689 { 7690 as_bad (_("expecting `,' or `)' " 7691 "after base register in `%s'"), 7692 operand_string); 7693 return 0; 7694 } 7695 } 7696 else if (*base_string == REGISTER_PREFIX) 7697 { 7698 as_bad (_("bad register name `%s'"), base_string); 7699 return 0; 7700 } 7701 } 7702 7703 /* If there's an expression beginning the operand, parse it, 7704 assuming displacement_string_start and 7705 displacement_string_end are meaningful. */ 7706 if (displacement_string_start != displacement_string_end) 7707 { 7708 if (!i386_displacement (displacement_string_start, 7709 displacement_string_end)) 7710 return 0; 7711 } 7712 7713 /* Special case for (%dx) while doing input/output op. */ 7714 if (i.base_reg 7715 && operand_type_equal (&i.base_reg->reg_type, 7716 ®16_inoutportreg) 7717 && i.index_reg == 0 7718 && i.log2_scale_factor == 0 7719 && i.seg[i.mem_operands] == 0 7720 && !operand_type_check (i.types[this_operand], disp)) 7721 { 7722 i.types[this_operand] = inoutportreg; 7723 return 1; 7724 } 7725 7726 if (i386_index_check (operand_string) == 0) 7727 return 0; 7728 i.types[this_operand].bitfield.mem = 1; 7729 i.mem_operands++; 7730 } 7731 else 7732 { 7733 /* It's not a memory operand; argh! */ 7734 as_bad (_("invalid char %s beginning operand %d `%s'"), 7735 output_invalid (*op_string), 7736 this_operand + 1, 7737 op_string); 7738 return 0; 7739 } 7740 return 1; /* Normal return. */ 7741 } 7742 7743 /* Calculate the maximum variable size (i.e., excluding fr_fix) 7744 that an rs_machine_dependent frag may reach. */ 7745 7746 unsigned int 7747 i386_frag_max_var (fragS *frag) 7748 { 7749 /* The only relaxable frags are for jumps. 7750 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ 7751 gas_assert (frag->fr_type == rs_machine_dependent); 7752 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; 7753 } 7754 7755 /* md_estimate_size_before_relax() 7756 7757 Called just before relax() for rs_machine_dependent frags. The x86 7758 assembler uses these frags to handle variable size jump 7759 instructions. 7760 7761 Any symbol that is now undefined will not become defined. 7762 Return the correct fr_subtype in the frag. 7763 Return the initial "guess for variable size of frag" to caller. 7764 The guess is actually the growth beyond the fixed part. Whatever 7765 we do to grow the fixed or variable part contributes to our 7766 returned value. */ 7767 7768 int 7769 md_estimate_size_before_relax (fragS *fragP, segT segment) 7770 { 7771 /* We've already got fragP->fr_subtype right; all we have to do is 7772 check for un-relaxable symbols. On an ELF system, we can't relax 7773 an externally visible symbol, because it may be overridden by a 7774 shared library. */ 7775 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 7776 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 7777 || (IS_ELF 7778 && (S_IS_EXTERNAL (fragP->fr_symbol) 7779 || S_IS_WEAK (fragP->fr_symbol) 7780 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags 7781 & BSF_GNU_INDIRECT_FUNCTION)))) 7782 #endif 7783 #if defined (OBJ_COFF) && defined (TE_PE) 7784 || (OUTPUT_FLAVOR == bfd_target_coff_flavour 7785 && S_IS_WEAK (fragP->fr_symbol)) 7786 #endif 7787 ) 7788 { 7789 /* Symbol is undefined in this segment, or we need to keep a 7790 reloc so that weak symbols can be overridden. */ 7791 int size = (fragP->fr_subtype & CODE16) ? 2 : 4; 7792 enum bfd_reloc_code_real reloc_type; 7793 unsigned char *opcode; 7794 int old_fr_fix; 7795 7796 if (fragP->fr_var != NO_RELOC) 7797 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; 7798 else if (size == 2) 7799 reloc_type = BFD_RELOC_16_PCREL; 7800 else 7801 reloc_type = BFD_RELOC_32_PCREL; 7802 7803 old_fr_fix = fragP->fr_fix; 7804 opcode = (unsigned char *) fragP->fr_opcode; 7805 7806 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) 7807 { 7808 case UNCOND_JUMP: 7809 /* Make jmp (0xeb) a (d)word displacement jump. */ 7810 opcode[0] = 0xe9; 7811 fragP->fr_fix += size; 7812 fix_new (fragP, old_fr_fix, size, 7813 fragP->fr_symbol, 7814 fragP->fr_offset, 1, 7815 reloc_type); 7816 break; 7817 7818 case COND_JUMP86: 7819 if (size == 2 7820 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) 7821 { 7822 /* Negate the condition, and branch past an 7823 unconditional jump. */ 7824 opcode[0] ^= 1; 7825 opcode[1] = 3; 7826 /* Insert an unconditional jump. */ 7827 opcode[2] = 0xe9; 7828 /* We added two extra opcode bytes, and have a two byte 7829 offset. */ 7830 fragP->fr_fix += 2 + 2; 7831 fix_new (fragP, old_fr_fix + 2, 2, 7832 fragP->fr_symbol, 7833 fragP->fr_offset, 1, 7834 reloc_type); 7835 break; 7836 } 7837 /* Fall through. */ 7838 7839 case COND_JUMP: 7840 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) 7841 { 7842 fixS *fixP; 7843 7844 fragP->fr_fix += 1; 7845 fixP = fix_new (fragP, old_fr_fix, 1, 7846 fragP->fr_symbol, 7847 fragP->fr_offset, 1, 7848 BFD_RELOC_8_PCREL); 7849 fixP->fx_signed = 1; 7850 break; 7851 } 7852 7853 /* This changes the byte-displacement jump 0x7N 7854 to the (d)word-displacement jump 0x0f,0x8N. */ 7855 opcode[1] = opcode[0] + 0x10; 7856 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 7857 /* We've added an opcode byte. */ 7858 fragP->fr_fix += 1 + size; 7859 fix_new (fragP, old_fr_fix + 1, size, 7860 fragP->fr_symbol, 7861 fragP->fr_offset, 1, 7862 reloc_type); 7863 break; 7864 7865 default: 7866 BAD_CASE (fragP->fr_subtype); 7867 break; 7868 } 7869 frag_wane (fragP); 7870 return fragP->fr_fix - old_fr_fix; 7871 } 7872 7873 /* Guess size depending on current relax state. Initially the relax 7874 state will correspond to a short jump and we return 1, because 7875 the variable part of the frag (the branch offset) is one byte 7876 long. However, we can relax a section more than once and in that 7877 case we must either set fr_subtype back to the unrelaxed state, 7878 or return the value for the appropriate branch. */ 7879 return md_relax_table[fragP->fr_subtype].rlx_length; 7880 } 7881 7882 /* Called after relax() is finished. 7883 7884 In: Address of frag. 7885 fr_type == rs_machine_dependent. 7886 fr_subtype is what the address relaxed to. 7887 7888 Out: Any fixSs and constants are set up. 7889 Caller will turn frag into a ".space 0". */ 7890 7891 void 7892 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, 7893 fragS *fragP) 7894 { 7895 unsigned char *opcode; 7896 unsigned char *where_to_put_displacement = NULL; 7897 offsetT target_address; 7898 offsetT opcode_address; 7899 unsigned int extension = 0; 7900 offsetT displacement_from_opcode_start; 7901 7902 opcode = (unsigned char *) fragP->fr_opcode; 7903 7904 /* Address we want to reach in file space. */ 7905 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 7906 7907 /* Address opcode resides at in file space. */ 7908 opcode_address = fragP->fr_address + fragP->fr_fix; 7909 7910 /* Displacement from opcode start to fill into instruction. */ 7911 displacement_from_opcode_start = target_address - opcode_address; 7912 7913 if ((fragP->fr_subtype & BIG) == 0) 7914 { 7915 /* Don't have to change opcode. */ 7916 extension = 1; /* 1 opcode + 1 displacement */ 7917 where_to_put_displacement = &opcode[1]; 7918 } 7919 else 7920 { 7921 if (no_cond_jump_promotion 7922 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) 7923 as_warn_where (fragP->fr_file, fragP->fr_line, 7924 _("long jump required")); 7925 7926 switch (fragP->fr_subtype) 7927 { 7928 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 7929 extension = 4; /* 1 opcode + 4 displacement */ 7930 opcode[0] = 0xe9; 7931 where_to_put_displacement = &opcode[1]; 7932 break; 7933 7934 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 7935 extension = 2; /* 1 opcode + 2 displacement */ 7936 opcode[0] = 0xe9; 7937 where_to_put_displacement = &opcode[1]; 7938 break; 7939 7940 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 7941 case ENCODE_RELAX_STATE (COND_JUMP86, BIG): 7942 extension = 5; /* 2 opcode + 4 displacement */ 7943 opcode[1] = opcode[0] + 0x10; 7944 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 7945 where_to_put_displacement = &opcode[2]; 7946 break; 7947 7948 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 7949 extension = 3; /* 2 opcode + 2 displacement */ 7950 opcode[1] = opcode[0] + 0x10; 7951 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 7952 where_to_put_displacement = &opcode[2]; 7953 break; 7954 7955 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): 7956 extension = 4; 7957 opcode[0] ^= 1; 7958 opcode[1] = 3; 7959 opcode[2] = 0xe9; 7960 where_to_put_displacement = &opcode[3]; 7961 break; 7962 7963 default: 7964 BAD_CASE (fragP->fr_subtype); 7965 break; 7966 } 7967 } 7968 7969 /* If size if less then four we are sure that the operand fits, 7970 but if it's 4, then it could be that the displacement is larger 7971 then -/+ 2GB. */ 7972 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 7973 && object_64bit 7974 && ((addressT) (displacement_from_opcode_start - extension 7975 + ((addressT) 1 << 31)) 7976 > (((addressT) 2 << 31) - 1))) 7977 { 7978 as_bad_where (fragP->fr_file, fragP->fr_line, 7979 _("jump target out of range")); 7980 /* Make us emit 0. */ 7981 displacement_from_opcode_start = extension; 7982 } 7983 /* Now put displacement after opcode. */ 7984 md_number_to_chars ((char *) where_to_put_displacement, 7985 (valueT) (displacement_from_opcode_start - extension), 7986 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 7987 fragP->fr_fix += extension; 7988 } 7989 7990 /* Apply a fixup (fixP) to segment data, once it has been determined 7991 by our caller that we have all the info we need to fix it up. 7992 7993 Parameter valP is the pointer to the value of the bits. 7994 7995 On the 386, immediates, displacements, and data pointers are all in 7996 the same (little-endian) format, so we don't need to care about which 7997 we are handling. */ 7998 7999 void 8000 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 8001 { 8002 char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 8003 valueT value = *valP; 8004 8005 #if !defined (TE_Mach) 8006 if (fixP->fx_pcrel) 8007 { 8008 switch (fixP->fx_r_type) 8009 { 8010 default: 8011 break; 8012 8013 case BFD_RELOC_64: 8014 fixP->fx_r_type = BFD_RELOC_64_PCREL; 8015 break; 8016 case BFD_RELOC_32: 8017 case BFD_RELOC_X86_64_32S: 8018 fixP->fx_r_type = BFD_RELOC_32_PCREL; 8019 break; 8020 case BFD_RELOC_16: 8021 fixP->fx_r_type = BFD_RELOC_16_PCREL; 8022 break; 8023 case BFD_RELOC_8: 8024 fixP->fx_r_type = BFD_RELOC_8_PCREL; 8025 break; 8026 } 8027 } 8028 8029 if (fixP->fx_addsy != NULL 8030 && (fixP->fx_r_type == BFD_RELOC_32_PCREL 8031 || fixP->fx_r_type == BFD_RELOC_64_PCREL 8032 || fixP->fx_r_type == BFD_RELOC_16_PCREL 8033 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 8034 && !use_rela_relocations) 8035 { 8036 /* This is a hack. There should be a better way to handle this. 8037 This covers for the fact that bfd_install_relocation will 8038 subtract the current location (for partial_inplace, PC relative 8039 relocations); see more below. */ 8040 #ifndef OBJ_AOUT 8041 if (IS_ELF 8042 #ifdef TE_PE 8043 || OUTPUT_FLAVOR == bfd_target_coff_flavour 8044 #endif 8045 ) 8046 value += fixP->fx_where + fixP->fx_frag->fr_address; 8047 #endif 8048 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8049 if (IS_ELF) 8050 { 8051 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); 8052 8053 if ((sym_seg == seg 8054 || (symbol_section_p (fixP->fx_addsy) 8055 && sym_seg != absolute_section)) 8056 && !generic_force_reloc (fixP)) 8057 { 8058 /* Yes, we add the values in twice. This is because 8059 bfd_install_relocation subtracts them out again. I think 8060 bfd_install_relocation is broken, but I don't dare change 8061 it. FIXME. */ 8062 value += fixP->fx_where + fixP->fx_frag->fr_address; 8063 } 8064 } 8065 #endif 8066 #if defined (OBJ_COFF) && defined (TE_PE) 8067 /* For some reason, the PE format does not store a 8068 section address offset for a PC relative symbol. */ 8069 if (S_GET_SEGMENT (fixP->fx_addsy) != seg 8070 || S_IS_WEAK (fixP->fx_addsy)) 8071 value += md_pcrel_from (fixP); 8072 #endif 8073 } 8074 #if defined (OBJ_COFF) && defined (TE_PE) 8075 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) 8076 { 8077 value -= S_GET_VALUE (fixP->fx_addsy); 8078 } 8079 #endif 8080 8081 /* Fix a few things - the dynamic linker expects certain values here, 8082 and we must not disappoint it. */ 8083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8084 if (IS_ELF && fixP->fx_addsy) 8085 switch (fixP->fx_r_type) 8086 { 8087 case BFD_RELOC_386_PLT32: 8088 case BFD_RELOC_X86_64_PLT32: 8089 /* Make the jump instruction point to the address of the operand. At 8090 runtime we merely add the offset to the actual PLT entry. */ 8091 value = -4; 8092 break; 8093 8094 case BFD_RELOC_386_TLS_GD: 8095 case BFD_RELOC_386_TLS_LDM: 8096 case BFD_RELOC_386_TLS_IE_32: 8097 case BFD_RELOC_386_TLS_IE: 8098 case BFD_RELOC_386_TLS_GOTIE: 8099 case BFD_RELOC_386_TLS_GOTDESC: 8100 case BFD_RELOC_X86_64_TLSGD: 8101 case BFD_RELOC_X86_64_TLSLD: 8102 case BFD_RELOC_X86_64_GOTTPOFF: 8103 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 8104 value = 0; /* Fully resolved at runtime. No addend. */ 8105 /* Fallthrough */ 8106 case BFD_RELOC_386_TLS_LE: 8107 case BFD_RELOC_386_TLS_LDO_32: 8108 case BFD_RELOC_386_TLS_LE_32: 8109 case BFD_RELOC_X86_64_DTPOFF32: 8110 case BFD_RELOC_X86_64_DTPOFF64: 8111 case BFD_RELOC_X86_64_TPOFF32: 8112 case BFD_RELOC_X86_64_TPOFF64: 8113 S_SET_THREAD_LOCAL (fixP->fx_addsy); 8114 break; 8115 8116 case BFD_RELOC_386_TLS_DESC_CALL: 8117 case BFD_RELOC_X86_64_TLSDESC_CALL: 8118 value = 0; /* Fully resolved at runtime. No addend. */ 8119 S_SET_THREAD_LOCAL (fixP->fx_addsy); 8120 fixP->fx_done = 0; 8121 return; 8122 8123 case BFD_RELOC_386_GOT32: 8124 case BFD_RELOC_X86_64_GOT32: 8125 value = 0; /* Fully resolved at runtime. No addend. */ 8126 break; 8127 8128 case BFD_RELOC_VTABLE_INHERIT: 8129 case BFD_RELOC_VTABLE_ENTRY: 8130 fixP->fx_done = 0; 8131 return; 8132 8133 default: 8134 break; 8135 } 8136 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 8137 *valP = value; 8138 #endif /* !defined (TE_Mach) */ 8139 8140 /* Are we finished with this relocation now? */ 8141 if (fixP->fx_addsy == NULL) 8142 fixP->fx_done = 1; 8143 #if defined (OBJ_COFF) && defined (TE_PE) 8144 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) 8145 { 8146 fixP->fx_done = 0; 8147 /* Remember value for tc_gen_reloc. */ 8148 fixP->fx_addnumber = value; 8149 /* Clear out the frag for now. */ 8150 value = 0; 8151 } 8152 #endif 8153 else if (use_rela_relocations) 8154 { 8155 fixP->fx_no_overflow = 1; 8156 /* Remember value for tc_gen_reloc. */ 8157 fixP->fx_addnumber = value; 8158 value = 0; 8159 } 8160 8161 md_number_to_chars (p, value, fixP->fx_size); 8162 } 8163 8164 char * 8165 md_atof (int type, char *litP, int *sizeP) 8166 { 8167 /* This outputs the LITTLENUMs in REVERSE order; 8168 in accord with the bigendian 386. */ 8169 return ieee_md_atof (type, litP, sizeP, FALSE); 8170 } 8171 8172 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; 8173 8174 static char * 8175 output_invalid (int c) 8176 { 8177 if (ISPRINT (c)) 8178 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 8179 "'%c'", c); 8180 else 8181 snprintf (output_invalid_buf, sizeof (output_invalid_buf), 8182 "(0x%x)", (unsigned char) c); 8183 return output_invalid_buf; 8184 } 8185 8186 /* REG_STRING starts *before* REGISTER_PREFIX. */ 8187 8188 static const reg_entry * 8189 parse_real_register (char *reg_string, char **end_op) 8190 { 8191 char *s = reg_string; 8192 char *p; 8193 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 8194 const reg_entry *r; 8195 8196 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 8197 if (*s == REGISTER_PREFIX) 8198 ++s; 8199 8200 if (is_space_char (*s)) 8201 ++s; 8202 8203 p = reg_name_given; 8204 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 8205 { 8206 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 8207 return (const reg_entry *) NULL; 8208 s++; 8209 } 8210 8211 /* For naked regs, make sure that we are not dealing with an identifier. 8212 This prevents confusing an identifier like `eax_var' with register 8213 `eax'. */ 8214 if (allow_naked_reg && identifier_chars[(unsigned char) *s]) 8215 return (const reg_entry *) NULL; 8216 8217 *end_op = s; 8218 8219 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 8220 8221 /* Handle floating point regs, allowing spaces in the (i) part. */ 8222 if (r == i386_regtab /* %st is first entry of table */) 8223 { 8224 if (is_space_char (*s)) 8225 ++s; 8226 if (*s == '(') 8227 { 8228 ++s; 8229 if (is_space_char (*s)) 8230 ++s; 8231 if (*s >= '0' && *s <= '7') 8232 { 8233 int fpr = *s - '0'; 8234 ++s; 8235 if (is_space_char (*s)) 8236 ++s; 8237 if (*s == ')') 8238 { 8239 *end_op = s + 1; 8240 r = (const reg_entry *) hash_find (reg_hash, "st(0)"); 8241 know (r); 8242 return r + fpr; 8243 } 8244 } 8245 /* We have "%st(" then garbage. */ 8246 return (const reg_entry *) NULL; 8247 } 8248 } 8249 8250 if (r == NULL || allow_pseudo_reg) 8251 return r; 8252 8253 if (operand_type_all_zero (&r->reg_type)) 8254 return (const reg_entry *) NULL; 8255 8256 if ((r->reg_type.bitfield.reg32 8257 || r->reg_type.bitfield.sreg3 8258 || r->reg_type.bitfield.control 8259 || r->reg_type.bitfield.debug 8260 || r->reg_type.bitfield.test) 8261 && !cpu_arch_flags.bitfield.cpui386) 8262 return (const reg_entry *) NULL; 8263 8264 if (r->reg_type.bitfield.floatreg 8265 && !cpu_arch_flags.bitfield.cpu8087 8266 && !cpu_arch_flags.bitfield.cpu287 8267 && !cpu_arch_flags.bitfield.cpu387) 8268 return (const reg_entry *) NULL; 8269 8270 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) 8271 return (const reg_entry *) NULL; 8272 8273 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) 8274 return (const reg_entry *) NULL; 8275 8276 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) 8277 return (const reg_entry *) NULL; 8278 8279 /* Don't allow fake index register unless allow_index_reg isn't 0. */ 8280 if (!allow_index_reg 8281 && (r->reg_num == RegEiz || r->reg_num == RegRiz)) 8282 return (const reg_entry *) NULL; 8283 8284 if (((r->reg_flags & (RegRex64 | RegRex)) 8285 || r->reg_type.bitfield.reg64) 8286 && (!cpu_arch_flags.bitfield.cpulm 8287 || !operand_type_equal (&r->reg_type, &control)) 8288 && flag_code != CODE_64BIT) 8289 return (const reg_entry *) NULL; 8290 8291 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) 8292 return (const reg_entry *) NULL; 8293 8294 return r; 8295 } 8296 8297 /* REG_STRING starts *before* REGISTER_PREFIX. */ 8298 8299 static const reg_entry * 8300 parse_register (char *reg_string, char **end_op) 8301 { 8302 const reg_entry *r; 8303 8304 if (*reg_string == REGISTER_PREFIX || allow_naked_reg) 8305 r = parse_real_register (reg_string, end_op); 8306 else 8307 r = NULL; 8308 if (!r) 8309 { 8310 char *save = input_line_pointer; 8311 char c; 8312 symbolS *symbolP; 8313 8314 input_line_pointer = reg_string; 8315 c = get_symbol_end (); 8316 symbolP = symbol_find (reg_string); 8317 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) 8318 { 8319 const expressionS *e = symbol_get_value_expression (symbolP); 8320 8321 know (e->X_op == O_register); 8322 know (e->X_add_number >= 0 8323 && (valueT) e->X_add_number < i386_regtab_size); 8324 r = i386_regtab + e->X_add_number; 8325 *end_op = input_line_pointer; 8326 } 8327 *input_line_pointer = c; 8328 input_line_pointer = save; 8329 } 8330 return r; 8331 } 8332 8333 int 8334 i386_parse_name (char *name, expressionS *e, char *nextcharP) 8335 { 8336 const reg_entry *r; 8337 char *end = input_line_pointer; 8338 8339 *end = *nextcharP; 8340 r = parse_register (name, &input_line_pointer); 8341 if (r && end <= input_line_pointer) 8342 { 8343 *nextcharP = *input_line_pointer; 8344 *input_line_pointer = 0; 8345 e->X_op = O_register; 8346 e->X_add_number = r - i386_regtab; 8347 return 1; 8348 } 8349 input_line_pointer = end; 8350 *end = 0; 8351 return intel_syntax ? i386_intel_parse_name (name, e) : 0; 8352 } 8353 8354 void 8355 md_operand (expressionS *e) 8356 { 8357 char *end; 8358 const reg_entry *r; 8359 8360 switch (*input_line_pointer) 8361 { 8362 case REGISTER_PREFIX: 8363 r = parse_real_register (input_line_pointer, &end); 8364 if (r) 8365 { 8366 e->X_op = O_register; 8367 e->X_add_number = r - i386_regtab; 8368 input_line_pointer = end; 8369 } 8370 break; 8371 8372 case '[': 8373 gas_assert (intel_syntax); 8374 end = input_line_pointer++; 8375 expression (e); 8376 if (*input_line_pointer == ']') 8377 { 8378 ++input_line_pointer; 8379 e->X_op_symbol = make_expr_symbol (e); 8380 e->X_add_symbol = NULL; 8381 e->X_add_number = 0; 8382 e->X_op = O_index; 8383 } 8384 else 8385 { 8386 e->X_op = O_absent; 8387 input_line_pointer = end; 8388 } 8389 break; 8390 } 8391 } 8392 8393 8394 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8395 const char *md_shortopts = "kVQ:sqn"; 8396 #else 8397 const char *md_shortopts = "qn"; 8398 #endif 8399 8400 #define OPTION_32 (OPTION_MD_BASE + 0) 8401 #define OPTION_64 (OPTION_MD_BASE + 1) 8402 #define OPTION_DIVIDE (OPTION_MD_BASE + 2) 8403 #define OPTION_MARCH (OPTION_MD_BASE + 3) 8404 #define OPTION_MTUNE (OPTION_MD_BASE + 4) 8405 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) 8406 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) 8407 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) 8408 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) 8409 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) 8410 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) 8411 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) 8412 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12) 8413 #define OPTION_X32 (OPTION_MD_BASE + 13) 8414 8415 struct option md_longopts[] = 8416 { 8417 {"32", no_argument, NULL, OPTION_32}, 8418 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 8419 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 8420 {"64", no_argument, NULL, OPTION_64}, 8421 #endif 8422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8423 {"x32", no_argument, NULL, OPTION_X32}, 8424 #endif 8425 {"divide", no_argument, NULL, OPTION_DIVIDE}, 8426 {"march", required_argument, NULL, OPTION_MARCH}, 8427 {"mtune", required_argument, NULL, OPTION_MTUNE}, 8428 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, 8429 {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, 8430 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, 8431 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, 8432 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, 8433 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, 8434 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, 8435 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, 8436 {NULL, no_argument, NULL, 0} 8437 }; 8438 size_t md_longopts_size = sizeof (md_longopts); 8439 8440 int 8441 md_parse_option (int c, char *arg) 8442 { 8443 unsigned int j; 8444 char *arch, *next; 8445 8446 switch (c) 8447 { 8448 case 'n': 8449 optimize_align_code = 0; 8450 break; 8451 8452 case 'q': 8453 quiet_warnings = 1; 8454 break; 8455 8456 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8457 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 8458 should be emitted or not. FIXME: Not implemented. */ 8459 case 'Q': 8460 break; 8461 8462 /* -V: SVR4 argument to print version ID. */ 8463 case 'V': 8464 print_version_id (); 8465 break; 8466 8467 /* -k: Ignore for FreeBSD compatibility. */ 8468 case 'k': 8469 break; 8470 8471 case 's': 8472 /* -s: On i386 Solaris, this tells the native assembler to use 8473 .stab instead of .stab.excl. We always use .stab anyhow. */ 8474 break; 8475 #endif 8476 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 8477 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 8478 case OPTION_64: 8479 { 8480 const char **list, **l; 8481 8482 list = bfd_target_list (); 8483 for (l = list; *l != NULL; l++) 8484 if (CONST_STRNEQ (*l, "elf64-x86-64") 8485 || strcmp (*l, "coff-x86-64") == 0 8486 || strcmp (*l, "pe-x86-64") == 0 8487 || strcmp (*l, "pei-x86-64") == 0 8488 || strcmp (*l, "mach-o-x86-64") == 0) 8489 { 8490 default_arch = "x86_64"; 8491 break; 8492 } 8493 if (*l == NULL) 8494 as_fatal (_("no compiled in support for x86_64")); 8495 free (list); 8496 } 8497 break; 8498 #endif 8499 8500 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8501 case OPTION_X32: 8502 if (IS_ELF) 8503 { 8504 const char **list, **l; 8505 8506 list = bfd_target_list (); 8507 for (l = list; *l != NULL; l++) 8508 if (CONST_STRNEQ (*l, "elf32-x86-64")) 8509 { 8510 default_arch = "x86_64:32"; 8511 break; 8512 } 8513 if (*l == NULL) 8514 as_fatal (_("no compiled in support for 32bit x86_64")); 8515 free (list); 8516 } 8517 else 8518 as_fatal (_("32bit x86_64 is only supported for ELF")); 8519 break; 8520 #endif 8521 8522 case OPTION_32: 8523 default_arch = "i386"; 8524 break; 8525 8526 case OPTION_DIVIDE: 8527 #ifdef SVR4_COMMENT_CHARS 8528 { 8529 char *n, *t; 8530 const char *s; 8531 8532 n = (char *) xmalloc (strlen (i386_comment_chars) + 1); 8533 t = n; 8534 for (s = i386_comment_chars; *s != '\0'; s++) 8535 if (*s != '/') 8536 *t++ = *s; 8537 *t = '\0'; 8538 i386_comment_chars = n; 8539 } 8540 #endif 8541 break; 8542 8543 case OPTION_MARCH: 8544 arch = xstrdup (arg); 8545 do 8546 { 8547 if (*arch == '.') 8548 as_fatal (_("invalid -march= option: `%s'"), arg); 8549 next = strchr (arch, '+'); 8550 if (next) 8551 *next++ = '\0'; 8552 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 8553 { 8554 if (strcmp (arch, cpu_arch [j].name) == 0) 8555 { 8556 /* Processor. */ 8557 if (! cpu_arch[j].flags.bitfield.cpui386) 8558 continue; 8559 8560 cpu_arch_name = cpu_arch[j].name; 8561 cpu_sub_arch_name = NULL; 8562 cpu_arch_flags = cpu_arch[j].flags; 8563 cpu_arch_isa = cpu_arch[j].type; 8564 cpu_arch_isa_flags = cpu_arch[j].flags; 8565 if (!cpu_arch_tune_set) 8566 { 8567 cpu_arch_tune = cpu_arch_isa; 8568 cpu_arch_tune_flags = cpu_arch_isa_flags; 8569 } 8570 break; 8571 } 8572 else if (*cpu_arch [j].name == '.' 8573 && strcmp (arch, cpu_arch [j].name + 1) == 0) 8574 { 8575 /* ISA entension. */ 8576 i386_cpu_flags flags; 8577 8578 if (!cpu_arch[j].negated) 8579 flags = cpu_flags_or (cpu_arch_flags, 8580 cpu_arch[j].flags); 8581 else 8582 flags = cpu_flags_and_not (cpu_arch_flags, 8583 cpu_arch[j].flags); 8584 if (!cpu_flags_equal (&flags, &cpu_arch_flags)) 8585 { 8586 if (cpu_sub_arch_name) 8587 { 8588 char *name = cpu_sub_arch_name; 8589 cpu_sub_arch_name = concat (name, 8590 cpu_arch[j].name, 8591 (const char *) NULL); 8592 free (name); 8593 } 8594 else 8595 cpu_sub_arch_name = xstrdup (cpu_arch[j].name); 8596 cpu_arch_flags = flags; 8597 cpu_arch_isa_flags = flags; 8598 } 8599 break; 8600 } 8601 } 8602 8603 if (j >= ARRAY_SIZE (cpu_arch)) 8604 as_fatal (_("invalid -march= option: `%s'"), arg); 8605 8606 arch = next; 8607 } 8608 while (next != NULL ); 8609 break; 8610 8611 case OPTION_MTUNE: 8612 if (*arg == '.') 8613 as_fatal (_("invalid -mtune= option: `%s'"), arg); 8614 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 8615 { 8616 if (strcmp (arg, cpu_arch [j].name) == 0) 8617 { 8618 cpu_arch_tune_set = 1; 8619 cpu_arch_tune = cpu_arch [j].type; 8620 cpu_arch_tune_flags = cpu_arch[j].flags; 8621 break; 8622 } 8623 } 8624 if (j >= ARRAY_SIZE (cpu_arch)) 8625 as_fatal (_("invalid -mtune= option: `%s'"), arg); 8626 break; 8627 8628 case OPTION_MMNEMONIC: 8629 if (strcasecmp (arg, "att") == 0) 8630 intel_mnemonic = 0; 8631 else if (strcasecmp (arg, "intel") == 0) 8632 intel_mnemonic = 1; 8633 else 8634 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); 8635 break; 8636 8637 case OPTION_MSYNTAX: 8638 if (strcasecmp (arg, "att") == 0) 8639 intel_syntax = 0; 8640 else if (strcasecmp (arg, "intel") == 0) 8641 intel_syntax = 1; 8642 else 8643 as_fatal (_("invalid -msyntax= option: `%s'"), arg); 8644 break; 8645 8646 case OPTION_MINDEX_REG: 8647 allow_index_reg = 1; 8648 break; 8649 8650 case OPTION_MNAKED_REG: 8651 allow_naked_reg = 1; 8652 break; 8653 8654 case OPTION_MOLD_GCC: 8655 old_gcc = 1; 8656 break; 8657 8658 case OPTION_MSSE2AVX: 8659 sse2avx = 1; 8660 break; 8661 8662 case OPTION_MSSE_CHECK: 8663 if (strcasecmp (arg, "error") == 0) 8664 sse_check = sse_check_error; 8665 else if (strcasecmp (arg, "warning") == 0) 8666 sse_check = sse_check_warning; 8667 else if (strcasecmp (arg, "none") == 0) 8668 sse_check = sse_check_none; 8669 else 8670 as_fatal (_("invalid -msse-check= option: `%s'"), arg); 8671 break; 8672 8673 case OPTION_MAVXSCALAR: 8674 if (strcasecmp (arg, "128") == 0) 8675 avxscalar = vex128; 8676 else if (strcasecmp (arg, "256") == 0) 8677 avxscalar = vex256; 8678 else 8679 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); 8680 break; 8681 8682 default: 8683 return 0; 8684 } 8685 return 1; 8686 } 8687 8688 #define MESSAGE_TEMPLATE \ 8689 " " 8690 8691 static void 8692 show_arch (FILE *stream, int ext, int check) 8693 { 8694 static char message[] = MESSAGE_TEMPLATE; 8695 char *start = message + 27; 8696 char *p; 8697 int size = sizeof (MESSAGE_TEMPLATE); 8698 int left; 8699 const char *name; 8700 int len; 8701 unsigned int j; 8702 8703 p = start; 8704 left = size - (start - message); 8705 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) 8706 { 8707 /* Should it be skipped? */ 8708 if (cpu_arch [j].skip) 8709 continue; 8710 8711 name = cpu_arch [j].name; 8712 len = cpu_arch [j].len; 8713 if (*name == '.') 8714 { 8715 /* It is an extension. Skip if we aren't asked to show it. */ 8716 if (ext) 8717 { 8718 name++; 8719 len--; 8720 } 8721 else 8722 continue; 8723 } 8724 else if (ext) 8725 { 8726 /* It is an processor. Skip if we show only extension. */ 8727 continue; 8728 } 8729 else if (check && ! cpu_arch[j].flags.bitfield.cpui386) 8730 { 8731 /* It is an impossible processor - skip. */ 8732 continue; 8733 } 8734 8735 /* Reserve 2 spaces for ", " or ",\0" */ 8736 left -= len + 2; 8737 8738 /* Check if there is any room. */ 8739 if (left >= 0) 8740 { 8741 if (p != start) 8742 { 8743 *p++ = ','; 8744 *p++ = ' '; 8745 } 8746 p = mempcpy (p, name, len); 8747 } 8748 else 8749 { 8750 /* Output the current message now and start a new one. */ 8751 *p++ = ','; 8752 *p = '\0'; 8753 fprintf (stream, "%s\n", message); 8754 p = start; 8755 left = size - (start - message) - len - 2; 8756 8757 gas_assert (left >= 0); 8758 8759 p = mempcpy (p, name, len); 8760 } 8761 } 8762 8763 *p = '\0'; 8764 fprintf (stream, "%s\n", message); 8765 } 8766 8767 void 8768 md_show_usage (FILE *stream) 8769 { 8770 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8771 fprintf (stream, _("\ 8772 -Q ignored\n\ 8773 -V print assembler version number\n\ 8774 -k ignored\n")); 8775 #endif 8776 fprintf (stream, _("\ 8777 -n Do not optimize code alignment\n\ 8778 -q quieten some warnings\n")); 8779 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 8780 fprintf (stream, _("\ 8781 -s ignored\n")); 8782 #endif 8783 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 8784 || defined (TE_PE) || defined (TE_PEP)) 8785 fprintf (stream, _("\ 8786 --32/--64/--x32 generate 32bit/64bit/x32 code\n")); 8787 #endif 8788 #ifdef SVR4_COMMENT_CHARS 8789 fprintf (stream, _("\ 8790 --divide do not treat `/' as a comment character\n")); 8791 #else 8792 fprintf (stream, _("\ 8793 --divide ignored\n")); 8794 #endif 8795 fprintf (stream, _("\ 8796 -march=CPU[,+EXTENSION...]\n\ 8797 generate code for CPU and EXTENSION, CPU is one of:\n")); 8798 show_arch (stream, 0, 1); 8799 fprintf (stream, _("\ 8800 EXTENSION is combination of:\n")); 8801 show_arch (stream, 1, 0); 8802 fprintf (stream, _("\ 8803 -mtune=CPU optimize for CPU, CPU is one of:\n")); 8804 show_arch (stream, 0, 0); 8805 fprintf (stream, _("\ 8806 -msse2avx encode SSE instructions with VEX prefix\n")); 8807 fprintf (stream, _("\ 8808 -msse-check=[none|error|warning]\n\ 8809 check SSE instructions\n")); 8810 fprintf (stream, _("\ 8811 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ 8812 length\n")); 8813 fprintf (stream, _("\ 8814 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); 8815 fprintf (stream, _("\ 8816 -msyntax=[att|intel] use AT&T/Intel syntax\n")); 8817 fprintf (stream, _("\ 8818 -mindex-reg support pseudo index registers\n")); 8819 fprintf (stream, _("\ 8820 -mnaked-reg don't require `%%' prefix for registers\n")); 8821 fprintf (stream, _("\ 8822 -mold-gcc support old (<= 2.8.1) versions of gcc\n")); 8823 } 8824 8825 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 8826 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ 8827 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) 8828 8829 /* Pick the target format to use. */ 8830 8831 const char * 8832 i386_target_format (void) 8833 { 8834 if (!strncmp (default_arch, "x86_64", 6)) 8835 { 8836 update_code_flag (CODE_64BIT, 1); 8837 if (default_arch[6] == '\0') 8838 x86_elf_abi = X86_64_ABI; 8839 else 8840 x86_elf_abi = X86_64_X32_ABI; 8841 } 8842 else if (!strcmp (default_arch, "i386")) 8843 update_code_flag (CODE_32BIT, 1); 8844 else 8845 as_fatal (_("unknown architecture")); 8846 8847 if (cpu_flags_all_zero (&cpu_arch_isa_flags)) 8848 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; 8849 if (cpu_flags_all_zero (&cpu_arch_tune_flags)) 8850 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; 8851 8852 switch (OUTPUT_FLAVOR) 8853 { 8854 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) 8855 case bfd_target_aout_flavour: 8856 return AOUT_TARGET_FORMAT; 8857 #endif 8858 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) 8859 # if defined (TE_PE) || defined (TE_PEP) 8860 case bfd_target_coff_flavour: 8861 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386"; 8862 # elif defined (TE_GO32) 8863 case bfd_target_coff_flavour: 8864 return "coff-go32"; 8865 # else 8866 case bfd_target_coff_flavour: 8867 return "coff-i386"; 8868 # endif 8869 #endif 8870 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 8871 case bfd_target_elf_flavour: 8872 { 8873 const char *format; 8874 8875 switch (x86_elf_abi) 8876 { 8877 default: 8878 format = ELF_TARGET_FORMAT; 8879 break; 8880 case X86_64_ABI: 8881 use_rela_relocations = 1; 8882 object_64bit = 1; 8883 format = ELF_TARGET_FORMAT64; 8884 break; 8885 case X86_64_X32_ABI: 8886 use_rela_relocations = 1; 8887 object_64bit = 1; 8888 disallow_64bit_reloc = 1; 8889 format = ELF_TARGET_FORMAT32; 8890 break; 8891 } 8892 if (cpu_arch_isa == PROCESSOR_L1OM) 8893 { 8894 if (x86_elf_abi != X86_64_ABI) 8895 as_fatal (_("Intel L1OM is 64bit only")); 8896 return ELF_TARGET_L1OM_FORMAT; 8897 } 8898 if (cpu_arch_isa == PROCESSOR_K1OM) 8899 { 8900 if (x86_elf_abi != X86_64_ABI) 8901 as_fatal (_("Intel K1OM is 64bit only")); 8902 return ELF_TARGET_K1OM_FORMAT; 8903 } 8904 else 8905 return format; 8906 } 8907 #endif 8908 #if defined (OBJ_MACH_O) 8909 case bfd_target_mach_o_flavour: 8910 if (flag_code == CODE_64BIT) 8911 { 8912 use_rela_relocations = 1; 8913 object_64bit = 1; 8914 return "mach-o-x86-64"; 8915 } 8916 else 8917 return "mach-o-i386"; 8918 #endif 8919 default: 8920 abort (); 8921 return NULL; 8922 } 8923 } 8924 8925 #endif /* OBJ_MAYBE_ more than one */ 8926 8927 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 8928 void 8929 i386_elf_emit_arch_note (void) 8930 { 8931 if (IS_ELF && cpu_arch_name != NULL) 8932 { 8933 char *p; 8934 asection *seg = now_seg; 8935 subsegT subseg = now_subseg; 8936 Elf_Internal_Note i_note; 8937 Elf_External_Note e_note; 8938 asection *note_secp; 8939 int len; 8940 8941 /* Create the .note section. */ 8942 note_secp = subseg_new (".note", 0); 8943 bfd_set_section_flags (stdoutput, 8944 note_secp, 8945 SEC_HAS_CONTENTS | SEC_READONLY); 8946 8947 /* Process the arch string. */ 8948 len = strlen (cpu_arch_name); 8949 8950 i_note.namesz = len + 1; 8951 i_note.descsz = 0; 8952 i_note.type = NT_ARCH; 8953 p = frag_more (sizeof (e_note.namesz)); 8954 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); 8955 p = frag_more (sizeof (e_note.descsz)); 8956 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); 8957 p = frag_more (sizeof (e_note.type)); 8958 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); 8959 p = frag_more (len + 1); 8960 strcpy (p, cpu_arch_name); 8961 8962 frag_align (2, 0, 0); 8963 8964 subseg_set (seg, subseg); 8965 } 8966 } 8967 #endif 8968 8969 symbolS * 8970 md_undefined_symbol (char *name) 8971 { 8972 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 8973 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 8974 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 8975 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 8976 { 8977 if (!GOT_symbol) 8978 { 8979 if (symbol_find (name)) 8980 as_bad (_("GOT already in symbol table")); 8981 GOT_symbol = symbol_new (name, undefined_section, 8982 (valueT) 0, &zero_address_frag); 8983 }; 8984 return GOT_symbol; 8985 } 8986 return 0; 8987 } 8988 8989 /* Round up a section size to the appropriate boundary. */ 8990 8991 valueT 8992 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 8993 { 8994 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 8995 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 8996 { 8997 /* For a.out, force the section size to be aligned. If we don't do 8998 this, BFD will align it for us, but it will not write out the 8999 final bytes of the section. This may be a bug in BFD, but it is 9000 easier to fix it here since that is how the other a.out targets 9001 work. */ 9002 int align; 9003 9004 align = bfd_get_section_alignment (stdoutput, segment); 9005 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 9006 } 9007 #endif 9008 9009 return size; 9010 } 9011 9012 /* On the i386, PC-relative offsets are relative to the start of the 9013 next instruction. That is, the address of the offset, plus its 9014 size, since the offset is always the last part of the insn. */ 9015 9016 long 9017 md_pcrel_from (fixS *fixP) 9018 { 9019 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 9020 } 9021 9022 #ifndef I386COFF 9023 9024 static void 9025 s_bss (int ignore ATTRIBUTE_UNUSED) 9026 { 9027 int temp; 9028 9029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9030 if (IS_ELF) 9031 obj_elf_section_change_hook (); 9032 #endif 9033 temp = get_absolute_expression (); 9034 subseg_set (bss_section, (subsegT) temp); 9035 demand_empty_rest_of_line (); 9036 } 9037 9038 #endif 9039 9040 void 9041 i386_validate_fix (fixS *fixp) 9042 { 9043 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) 9044 { 9045 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 9046 { 9047 if (!object_64bit) 9048 abort (); 9049 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; 9050 } 9051 else 9052 { 9053 if (!object_64bit) 9054 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 9055 else 9056 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; 9057 } 9058 fixp->fx_subsy = 0; 9059 } 9060 } 9061 9062 arelent * 9063 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 9064 { 9065 arelent *rel; 9066 bfd_reloc_code_real_type code; 9067 9068 switch (fixp->fx_r_type) 9069 { 9070 case BFD_RELOC_X86_64_PLT32: 9071 case BFD_RELOC_X86_64_GOT32: 9072 case BFD_RELOC_X86_64_GOTPCREL: 9073 case BFD_RELOC_386_PLT32: 9074 case BFD_RELOC_386_GOT32: 9075 case BFD_RELOC_386_GOTOFF: 9076 case BFD_RELOC_386_GOTPC: 9077 case BFD_RELOC_386_TLS_GD: 9078 case BFD_RELOC_386_TLS_LDM: 9079 case BFD_RELOC_386_TLS_LDO_32: 9080 case BFD_RELOC_386_TLS_IE_32: 9081 case BFD_RELOC_386_TLS_IE: 9082 case BFD_RELOC_386_TLS_GOTIE: 9083 case BFD_RELOC_386_TLS_LE_32: 9084 case BFD_RELOC_386_TLS_LE: 9085 case BFD_RELOC_386_TLS_GOTDESC: 9086 case BFD_RELOC_386_TLS_DESC_CALL: 9087 case BFD_RELOC_X86_64_TLSGD: 9088 case BFD_RELOC_X86_64_TLSLD: 9089 case BFD_RELOC_X86_64_DTPOFF32: 9090 case BFD_RELOC_X86_64_DTPOFF64: 9091 case BFD_RELOC_X86_64_GOTTPOFF: 9092 case BFD_RELOC_X86_64_TPOFF32: 9093 case BFD_RELOC_X86_64_TPOFF64: 9094 case BFD_RELOC_X86_64_GOTOFF64: 9095 case BFD_RELOC_X86_64_GOTPC32: 9096 case BFD_RELOC_X86_64_GOT64: 9097 case BFD_RELOC_X86_64_GOTPCREL64: 9098 case BFD_RELOC_X86_64_GOTPC64: 9099 case BFD_RELOC_X86_64_GOTPLT64: 9100 case BFD_RELOC_X86_64_PLTOFF64: 9101 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 9102 case BFD_RELOC_X86_64_TLSDESC_CALL: 9103 case BFD_RELOC_RVA: 9104 case BFD_RELOC_VTABLE_ENTRY: 9105 case BFD_RELOC_VTABLE_INHERIT: 9106 #ifdef TE_PE 9107 case BFD_RELOC_32_SECREL: 9108 #endif 9109 code = fixp->fx_r_type; 9110 break; 9111 case BFD_RELOC_X86_64_32S: 9112 if (!fixp->fx_pcrel) 9113 { 9114 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ 9115 code = fixp->fx_r_type; 9116 break; 9117 } 9118 default: 9119 if (fixp->fx_pcrel) 9120 { 9121 switch (fixp->fx_size) 9122 { 9123 default: 9124 as_bad_where (fixp->fx_file, fixp->fx_line, 9125 _("can not do %d byte pc-relative relocation"), 9126 fixp->fx_size); 9127 code = BFD_RELOC_32_PCREL; 9128 break; 9129 case 1: code = BFD_RELOC_8_PCREL; break; 9130 case 2: code = BFD_RELOC_16_PCREL; break; 9131 case 4: code = BFD_RELOC_32_PCREL; break; 9132 #ifdef BFD64 9133 case 8: code = BFD_RELOC_64_PCREL; break; 9134 #endif 9135 } 9136 } 9137 else 9138 { 9139 switch (fixp->fx_size) 9140 { 9141 default: 9142 as_bad_where (fixp->fx_file, fixp->fx_line, 9143 _("can not do %d byte relocation"), 9144 fixp->fx_size); 9145 code = BFD_RELOC_32; 9146 break; 9147 case 1: code = BFD_RELOC_8; break; 9148 case 2: code = BFD_RELOC_16; break; 9149 case 4: code = BFD_RELOC_32; break; 9150 #ifdef BFD64 9151 case 8: code = BFD_RELOC_64; break; 9152 #endif 9153 } 9154 } 9155 break; 9156 } 9157 9158 if ((code == BFD_RELOC_32 9159 || code == BFD_RELOC_32_PCREL 9160 || code == BFD_RELOC_X86_64_32S) 9161 && GOT_symbol 9162 && fixp->fx_addsy == GOT_symbol) 9163 { 9164 if (!object_64bit) 9165 code = BFD_RELOC_386_GOTPC; 9166 else 9167 code = BFD_RELOC_X86_64_GOTPC32; 9168 } 9169 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) 9170 && GOT_symbol 9171 && fixp->fx_addsy == GOT_symbol) 9172 { 9173 code = BFD_RELOC_X86_64_GOTPC64; 9174 } 9175 9176 rel = (arelent *) xmalloc (sizeof (arelent)); 9177 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 9178 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 9179 9180 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 9181 9182 if (!use_rela_relocations) 9183 { 9184 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 9185 vtable entry to be used in the relocation's section offset. */ 9186 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 9187 rel->address = fixp->fx_offset; 9188 #if defined (OBJ_COFF) && defined (TE_PE) 9189 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) 9190 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); 9191 else 9192 #endif 9193 rel->addend = 0; 9194 } 9195 /* Use the rela in 64bit mode. */ 9196 else 9197 { 9198 if (disallow_64bit_reloc) 9199 switch (code) 9200 { 9201 case BFD_RELOC_X86_64_DTPOFF64: 9202 case BFD_RELOC_X86_64_TPOFF64: 9203 case BFD_RELOC_64_PCREL: 9204 case BFD_RELOC_X86_64_GOTOFF64: 9205 case BFD_RELOC_X86_64_GOT64: 9206 case BFD_RELOC_X86_64_GOTPCREL64: 9207 case BFD_RELOC_X86_64_GOTPC64: 9208 case BFD_RELOC_X86_64_GOTPLT64: 9209 case BFD_RELOC_X86_64_PLTOFF64: 9210 as_bad_where (fixp->fx_file, fixp->fx_line, 9211 _("cannot represent relocation type %s in x32 mode"), 9212 bfd_get_reloc_code_name (code)); 9213 break; 9214 default: 9215 break; 9216 } 9217 9218 if (!fixp->fx_pcrel) 9219 rel->addend = fixp->fx_offset; 9220 else 9221 switch (code) 9222 { 9223 case BFD_RELOC_X86_64_PLT32: 9224 case BFD_RELOC_X86_64_GOT32: 9225 case BFD_RELOC_X86_64_GOTPCREL: 9226 case BFD_RELOC_X86_64_TLSGD: 9227 case BFD_RELOC_X86_64_TLSLD: 9228 case BFD_RELOC_X86_64_GOTTPOFF: 9229 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 9230 case BFD_RELOC_X86_64_TLSDESC_CALL: 9231 rel->addend = fixp->fx_offset - fixp->fx_size; 9232 break; 9233 default: 9234 rel->addend = (section->vma 9235 - fixp->fx_size 9236 + fixp->fx_addnumber 9237 + md_pcrel_from (fixp)); 9238 break; 9239 } 9240 } 9241 9242 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 9243 if (rel->howto == NULL) 9244 { 9245 as_bad_where (fixp->fx_file, fixp->fx_line, 9246 _("cannot represent relocation type %s"), 9247 bfd_get_reloc_code_name (code)); 9248 /* Set howto to a garbage value so that we can keep going. */ 9249 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 9250 gas_assert (rel->howto != NULL); 9251 } 9252 9253 return rel; 9254 } 9255 9256 #include "tc-i386-intel.c" 9257 9258 void 9259 tc_x86_parse_to_dw2regnum (expressionS *exp) 9260 { 9261 int saved_naked_reg; 9262 char saved_register_dot; 9263 9264 saved_naked_reg = allow_naked_reg; 9265 allow_naked_reg = 1; 9266 saved_register_dot = register_chars['.']; 9267 register_chars['.'] = '.'; 9268 allow_pseudo_reg = 1; 9269 expression_and_evaluate (exp); 9270 allow_pseudo_reg = 0; 9271 register_chars['.'] = saved_register_dot; 9272 allow_naked_reg = saved_naked_reg; 9273 9274 if (exp->X_op == O_register && exp->X_add_number >= 0) 9275 { 9276 if ((addressT) exp->X_add_number < i386_regtab_size) 9277 { 9278 exp->X_op = O_constant; 9279 exp->X_add_number = i386_regtab[exp->X_add_number] 9280 .dw2_regnum[flag_code >> 1]; 9281 } 9282 else 9283 exp->X_op = O_illegal; 9284 } 9285 } 9286 9287 void 9288 tc_x86_frame_initial_instructions (void) 9289 { 9290 static unsigned int sp_regno[2]; 9291 9292 if (!sp_regno[flag_code >> 1]) 9293 { 9294 char *saved_input = input_line_pointer; 9295 char sp[][4] = {"esp", "rsp"}; 9296 expressionS exp; 9297 9298 input_line_pointer = sp[flag_code >> 1]; 9299 tc_x86_parse_to_dw2regnum (&exp); 9300 gas_assert (exp.X_op == O_constant); 9301 sp_regno[flag_code >> 1] = exp.X_add_number; 9302 input_line_pointer = saved_input; 9303 } 9304 9305 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); 9306 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); 9307 } 9308 9309 int 9310 x86_dwarf2_addr_size (void) 9311 { 9312 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 9313 if (x86_elf_abi == X86_64_X32_ABI) 9314 return 4; 9315 #endif 9316 return bfd_arch_bits_per_address (stdoutput) / 8; 9317 } 9318 9319 int 9320 i386_elf_section_type (const char *str, size_t len) 9321 { 9322 if (flag_code == CODE_64BIT 9323 && len == sizeof ("unwind") - 1 9324 && strncmp (str, "unwind", 6) == 0) 9325 return SHT_X86_64_UNWIND; 9326 9327 return -1; 9328 } 9329 9330 #ifdef TE_SOLARIS 9331 void 9332 i386_solaris_fix_up_eh_frame (segT sec) 9333 { 9334 if (flag_code == CODE_64BIT) 9335 elf_section_type (sec) = SHT_X86_64_UNWIND; 9336 } 9337 #endif 9338 9339 #ifdef TE_PE 9340 void 9341 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 9342 { 9343 expressionS exp; 9344 9345 exp.X_op = O_secrel; 9346 exp.X_add_symbol = symbol; 9347 exp.X_add_number = 0; 9348 emit_expr (&exp, size); 9349 } 9350 #endif 9351 9352 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 9353 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ 9354 9355 bfd_vma 9356 x86_64_section_letter (int letter, char **ptr_msg) 9357 { 9358 if (flag_code == CODE_64BIT) 9359 { 9360 if (letter == 'l') 9361 return SHF_X86_64_LARGE; 9362 9363 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); 9364 } 9365 else 9366 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); 9367 return -1; 9368 } 9369 9370 bfd_vma 9371 x86_64_section_word (char *str, size_t len) 9372 { 9373 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) 9374 return SHF_X86_64_LARGE; 9375 9376 return -1; 9377 } 9378 9379 static void 9380 handle_large_common (int small ATTRIBUTE_UNUSED) 9381 { 9382 if (flag_code != CODE_64BIT) 9383 { 9384 s_comm_internal (0, elf_common_parse); 9385 as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); 9386 } 9387 else 9388 { 9389 static segT lbss_section; 9390 asection *saved_com_section_ptr = elf_com_section_ptr; 9391 asection *saved_bss_section = bss_section; 9392 9393 if (lbss_section == NULL) 9394 { 9395 flagword applicable; 9396 segT seg = now_seg; 9397 subsegT subseg = now_subseg; 9398 9399 /* The .lbss section is for local .largecomm symbols. */ 9400 lbss_section = subseg_new (".lbss", 0); 9401 applicable = bfd_applicable_section_flags (stdoutput); 9402 bfd_set_section_flags (stdoutput, lbss_section, 9403 applicable & SEC_ALLOC); 9404 seg_info (lbss_section)->bss = 1; 9405 9406 subseg_set (seg, subseg); 9407 } 9408 9409 elf_com_section_ptr = &_bfd_elf_large_com_section; 9410 bss_section = lbss_section; 9411 9412 s_comm_internal (0, elf_common_parse); 9413 9414 elf_com_section_ptr = saved_com_section_ptr; 9415 bss_section = saved_bss_section; 9416 } 9417 } 9418 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 9419