1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V 2 Copyright (C) 1997-2024 Free Software Foundation, Inc. 3 4 This file is part of GAS, the GNU Assembler. 5 6 GAS is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GAS is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to 18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 19 Boston, MA 02110-1301, USA. */ 20 21 #include "as.h" 22 #include "safe-ctype.h" 23 #include "subsegs.h" 24 #include "opcode/d30v.h" 25 #include "dwarf2dbg.h" 26 27 const char comment_chars[] = ";"; 28 const char line_comment_chars[] = "#"; 29 const char line_separator_chars[] = ""; 30 const char *md_shortopts = "OnNcC"; 31 const char EXP_CHARS[] = "eE"; 32 const char FLT_CHARS[] = "dD"; 33 34 #include <limits.h> 35 #ifndef CHAR_BIT 36 #define CHAR_BIT 8 37 #endif 38 39 #define NOP_MULTIPLY 1 40 #define NOP_ALL 2 41 static int warn_nops = 0; 42 static int Optimizing = 0; 43 static int warn_register_name_conflicts = 1; 44 45 #define FORCE_SHORT 1 46 #define FORCE_LONG 2 47 48 /* EXEC types. */ 49 typedef enum _exec_type 50 { 51 EXEC_UNKNOWN, /* No order specified. */ 52 EXEC_PARALLEL, /* Done in parallel (FM=00). */ 53 EXEC_SEQ, /* Sequential (FM=01). */ 54 EXEC_REVSEQ /* Reverse sequential (FM=10). */ 55 } exec_type_enum; 56 57 /* Fixups. */ 58 #define MAX_INSN_FIXUPS 5 59 60 struct d30v_fixup 61 { 62 expressionS exp; 63 int operand; 64 int pcrel; 65 int size; 66 bfd_reloc_code_real_type reloc; 67 }; 68 69 typedef struct _fixups 70 { 71 int fc; 72 struct d30v_fixup fix[MAX_INSN_FIXUPS]; 73 struct _fixups *next; 74 } Fixups; 75 76 static Fixups FixUps[2]; 77 static Fixups *fixups; 78 79 /* Whether current and previous instruction are word multiply insns. */ 80 static int cur_mul32_p = 0; 81 static int prev_mul32_p = 0; 82 83 /* The flag_explicitly_parallel is true iff the instruction being assembled 84 has been explicitly written as a parallel short-instruction pair by the 85 human programmer. It is used in parallel_ok () to distinguish between 86 those dangerous parallelizations attempted by the human, which are to be 87 allowed, and those attempted by the assembler, which are not. It is set 88 from md_assemble (). */ 89 static int flag_explicitly_parallel = 0; 90 static int flag_xp_state = 0; 91 92 /* Whether current and previous left sub-instruction disables 93 execution of right sub-instruction. */ 94 static int cur_left_kills_right_p = 0; 95 static int prev_left_kills_right_p = 0; 96 97 /* The known current alignment of the current section. */ 98 static int d30v_current_align; 99 static segT d30v_current_align_seg; 100 101 /* The last seen label in the current section. This is used to auto-align 102 labels preceding instructions. */ 103 static symbolS *d30v_last_label; 104 105 /* Two nops. */ 106 #define NOP_LEFT ((long long) NOP << 32) 107 #define NOP_RIGHT ((long long) NOP) 108 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT) 109 110 struct option md_longopts[] = 111 { 112 {NULL, no_argument, NULL, 0} 113 }; 114 115 size_t md_longopts_size = sizeof (md_longopts); 116 117 /* Opcode hash table. */ 118 static htab_t d30v_hash; 119 120 /* Do a binary search of the pre_defined_registers array to see if 121 NAME is a valid register name. Return the register number from the 122 array on success, or -1 on failure. */ 123 124 static int 125 reg_name_search (char *name) 126 { 127 int middle, low, high; 128 int cmp; 129 130 low = 0; 131 high = reg_name_cnt () - 1; 132 133 do 134 { 135 middle = (low + high) / 2; 136 cmp = strcasecmp (name, pre_defined_registers[middle].name); 137 if (cmp < 0) 138 high = middle - 1; 139 else if (cmp > 0) 140 low = middle + 1; 141 else 142 { 143 if (symbol_find (name) != NULL) 144 { 145 if (warn_register_name_conflicts) 146 as_warn (_("Register name %s conflicts with symbol of the same name"), 147 name); 148 } 149 150 return pre_defined_registers[middle].value; 151 } 152 } 153 while (low <= high); 154 155 return -1; 156 } 157 158 /* Check the string at input_line_pointer to see if it is a valid 159 register name. */ 160 161 static int 162 register_name (expressionS *expressionP) 163 { 164 int reg_number; 165 char c, *p = input_line_pointer; 166 167 while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') 168 p++; 169 170 c = *p; 171 if (c) 172 *p++ = 0; 173 174 /* Look to see if it's in the register table. */ 175 reg_number = reg_name_search (input_line_pointer); 176 if (reg_number >= 0) 177 { 178 expressionP->X_op = O_register; 179 /* Temporarily store a pointer to the string here. */ 180 expressionP->X_op_symbol = (symbolS *) input_line_pointer; 181 expressionP->X_add_number = reg_number; 182 input_line_pointer = p; 183 return 1; 184 } 185 if (c) 186 *(p - 1) = c; 187 return 0; 188 } 189 190 static int 191 check_range (unsigned long num, int bits, int flags) 192 { 193 long min, max; 194 195 /* Don't bother checking 32-bit values. */ 196 if (bits == 32) 197 { 198 if (sizeof (unsigned long) * CHAR_BIT == 32) 199 return 0; 200 201 /* We don't record signed or unsigned for 32-bit quantities. 202 Allow either. */ 203 min = -((unsigned long) 1 << (bits - 1)); 204 max = ((unsigned long) 1 << bits) - 1; 205 return (long) num < min || (long) num > max; 206 } 207 208 if (flags & OPERAND_SHIFT) 209 { 210 /* We know that all shifts are right by three bits. */ 211 num >>= 3; 212 213 if (flags & OPERAND_SIGNED) 214 { 215 unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1; 216 num = (num ^ sign_bit) - sign_bit; 217 } 218 } 219 220 if (flags & OPERAND_SIGNED) 221 { 222 max = ((unsigned long) 1 << (bits - 1)) - 1; 223 min = - ((unsigned long) 1 << (bits - 1)); 224 return (long) num > max || (long) num < min; 225 } 226 else 227 { 228 max = ((unsigned long) 1 << bits) - 1; 229 return num > (unsigned long) max; 230 } 231 } 232 233 void 234 md_show_usage (FILE *stream) 235 { 236 fprintf (stream, _("\nD30V options:\n\ 237 -O Make adjacent short instructions parallel if possible.\n\ 238 -n Warn about all NOPs inserted by the assembler.\n\ 239 -N Warn about NOPs inserted after word multiplies.\n\ 240 -c Warn about symbols whose names match register names.\n\ 241 -C Opposite of -C. -c is the default.\n")); 242 } 243 244 int 245 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) 246 { 247 switch (c) 248 { 249 /* Optimize. Will attempt to parallelize operations. */ 250 case 'O': 251 Optimizing = 1; 252 break; 253 254 /* Warn about all NOPS that the assembler inserts. */ 255 case 'n': 256 warn_nops = NOP_ALL; 257 break; 258 259 /* Warn about the NOPS that the assembler inserts because of the 260 multiply hazard. */ 261 case 'N': 262 warn_nops = NOP_MULTIPLY; 263 break; 264 265 case 'c': 266 warn_register_name_conflicts = 1; 267 break; 268 269 case 'C': 270 warn_register_name_conflicts = 0; 271 break; 272 273 default: 274 return 0; 275 } 276 return 1; 277 } 278 279 symbolS * 280 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 281 { 282 return 0; 283 } 284 285 const char * 286 md_atof (int type, char *litP, int *sizeP) 287 { 288 return ieee_md_atof (type, litP, sizeP, true); 289 } 290 291 void 292 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 293 asection *sec ATTRIBUTE_UNUSED, 294 fragS *fragP ATTRIBUTE_UNUSED) 295 { 296 abort (); 297 } 298 299 valueT 300 md_section_align (asection *seg, valueT addr) 301 { 302 int align = bfd_section_alignment (seg); 303 return ((addr + (1 << align) - 1) & -(1 << align)); 304 } 305 306 void 307 md_begin (void) 308 { 309 struct d30v_opcode *opcode; 310 d30v_hash = str_htab_create (); 311 312 /* Insert opcode names into a hash table. */ 313 for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++) 314 str_hash_insert (d30v_hash, opcode->name, opcode, 0); 315 316 fixups = &FixUps[0]; 317 FixUps[0].next = &FixUps[1]; 318 FixUps[1].next = &FixUps[0]; 319 320 d30v_current_align_seg = now_seg; 321 } 322 323 /* Remove the postincrement or postdecrement operator ( '+' or '-' ) 324 from an expression. */ 325 326 static int 327 postfix (char *p) 328 { 329 while (*p != '-' && *p != '+') 330 { 331 if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',') 332 break; 333 p++; 334 } 335 336 if (*p == '-') 337 { 338 *p = ' '; 339 return -1; 340 } 341 342 if (*p == '+') 343 { 344 *p = ' '; 345 return 1; 346 } 347 348 return 0; 349 } 350 351 static bfd_reloc_code_real_type 352 get_reloc (const struct d30v_operand *op, int rel_flag) 353 { 354 switch (op->bits) 355 { 356 case 6: 357 if (op->flags & OPERAND_SHIFT) 358 return BFD_RELOC_D30V_9_PCREL; 359 else 360 return BFD_RELOC_D30V_6; 361 break; 362 case 12: 363 if (!(op->flags & OPERAND_SHIFT)) 364 as_warn (_("unexpected 12-bit reloc type")); 365 if (rel_flag == RELOC_PCREL) 366 return BFD_RELOC_D30V_15_PCREL; 367 else 368 return BFD_RELOC_D30V_15; 369 case 18: 370 if (!(op->flags & OPERAND_SHIFT)) 371 as_warn (_("unexpected 18-bit reloc type")); 372 if (rel_flag == RELOC_PCREL) 373 return BFD_RELOC_D30V_21_PCREL; 374 else 375 return BFD_RELOC_D30V_21; 376 case 32: 377 if (rel_flag == RELOC_PCREL) 378 return BFD_RELOC_D30V_32_PCREL; 379 else 380 return BFD_RELOC_D30V_32; 381 default: 382 return 0; 383 } 384 } 385 386 /* Parse a string of operands and return an array of expressions. */ 387 388 static int 389 get_operands (expressionS exp[], int cmp_hack) 390 { 391 char *p = input_line_pointer; 392 int numops = 0; 393 int post = 0; 394 395 if (cmp_hack) 396 { 397 exp[numops].X_op = O_absent; 398 exp[numops++].X_add_number = cmp_hack - 1; 399 } 400 401 while (*p) 402 { 403 while (*p == ' ' || *p == '\t' || *p == ',') 404 p++; 405 406 if (*p == 0 || *p == '\n' || *p == '\r') 407 break; 408 409 if (*p == '@') 410 { 411 p++; 412 exp[numops].X_op = O_absent; 413 if (*p == '(') 414 { 415 p++; 416 exp[numops].X_add_number = OPERAND_ATPAR; 417 post = postfix (p); 418 } 419 else if (*p == '-') 420 { 421 p++; 422 exp[numops].X_add_number = OPERAND_ATMINUS; 423 } 424 else 425 { 426 exp[numops].X_add_number = OPERAND_ATSIGN; 427 post = postfix (p); 428 } 429 numops++; 430 continue; 431 } 432 433 if (*p == ')') 434 { 435 /* Just skip the trailing paren. */ 436 p++; 437 continue; 438 } 439 440 input_line_pointer = p; 441 442 /* Check to see if it might be a register name. */ 443 if (!register_name (&exp[numops])) 444 { 445 /* Parse as an expression. */ 446 expression (&exp[numops]); 447 } 448 449 if (exp[numops].X_op == O_illegal) 450 as_bad (_("illegal operand")); 451 else if (exp[numops].X_op == O_absent) 452 as_bad (_("missing operand")); 453 454 numops++; 455 p = input_line_pointer; 456 457 switch (post) 458 { 459 case -1: 460 /* Postdecrement mode. */ 461 exp[numops].X_op = O_absent; 462 exp[numops++].X_add_number = OPERAND_MINUS; 463 break; 464 case 1: 465 /* Postincrement mode. */ 466 exp[numops].X_op = O_absent; 467 exp[numops++].X_add_number = OPERAND_PLUS; 468 break; 469 } 470 post = 0; 471 } 472 473 exp[numops].X_op = 0; 474 475 return numops; 476 } 477 478 /* Generate the instruction. 479 It does everything but write the FM bits. */ 480 481 static long long 482 build_insn (struct d30v_insn *opcode, expressionS *opers) 483 { 484 int i, bits, shift, flags; 485 unsigned long number, id = 0; 486 long long insn; 487 struct d30v_opcode *op = opcode->op; 488 struct d30v_format *form = opcode->form; 489 490 insn = 491 opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18; 492 493 for (i = 0; form->operands[i]; i++) 494 { 495 flags = d30v_operand_table[form->operands[i]].flags; 496 497 /* Must be a register or number. */ 498 if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) 499 && !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL)) 500 continue; 501 502 bits = d30v_operand_table[form->operands[i]].bits; 503 if (flags & OPERAND_SHIFT) 504 bits += 3; 505 506 shift = 12 - d30v_operand_table[form->operands[i]].position; 507 if (opers[i].X_op != O_symbol) 508 number = opers[i].X_add_number; 509 else 510 number = 0; 511 if (flags & OPERAND_REG) 512 { 513 /* Check for mvfsys or mvtsys control registers. */ 514 if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG) 515 { 516 /* PSWL or PSWH. */ 517 id = (number & 0x7f) - MAX_CONTROL_REG; 518 number = 0; 519 } 520 else if (number & OPERAND_FLAG) 521 /* NUMBER is a flag register. */ 522 id = 3; 523 524 number &= 0x7F; 525 } 526 else if (flags & OPERAND_SPECIAL) 527 number = id; 528 529 if (opers[i].X_op != O_register && opers[i].X_op != O_constant 530 && !(flags & OPERAND_NAME)) 531 { 532 /* Now create a fixup. */ 533 if (fixups->fc >= MAX_INSN_FIXUPS) 534 as_fatal (_("too many fixups")); 535 536 fixups->fix[fixups->fc].reloc = 537 get_reloc (d30v_operand_table + form->operands[i], op->reloc_flag); 538 fixups->fix[fixups->fc].size = 4; 539 fixups->fix[fixups->fc].exp = opers[i]; 540 fixups->fix[fixups->fc].operand = form->operands[i]; 541 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL) 542 fixups->fix[fixups->fc].pcrel = RELOC_PCREL; 543 else 544 fixups->fix[fixups->fc].pcrel = op->reloc_flag; 545 (fixups->fc)++; 546 } 547 548 /* Truncate to the proper number of bits. */ 549 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) 550 as_bad (_("operand out of range: %ld"), number); 551 if (bits < 31) 552 number &= 0x7FFFFFFF >> (31 - bits); 553 if (flags & OPERAND_SHIFT) 554 number >>= 3; 555 if (bits == 32) 556 { 557 /* It's a LONG instruction. */ 558 insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */ 559 insn <<= 32; /* Shift the first word over. */ 560 insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */ 561 insn |= number & 0x0003FFFF; /* Bottom 18 bits. */ 562 } 563 else 564 insn |= number << shift; 565 } 566 567 return insn; 568 } 569 570 static void 571 d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */ 572 long long value, /* The value of the bits. */ 573 int n) /* Number of bytes in the output. */ 574 { 575 while (n--) 576 { 577 buf[n] = value & 0xff; 578 value >>= 8; 579 } 580 } 581 582 /* Write out a long form instruction. */ 583 584 static void 585 write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED, 586 long long insn, 587 Fixups *fx) 588 { 589 int i, where; 590 char *f = frag_more (8); 591 592 dwarf2_emit_insn (8); 593 insn |= FM11; 594 d30v_number_to_chars (f, insn, 8); 595 596 for (i = 0; i < fx->fc; i++) 597 { 598 if (fx->fix[i].reloc) 599 { 600 where = f - frag_now->fr_literal; 601 fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp), 602 fx->fix[i].pcrel, fx->fix[i].reloc); 603 } 604 } 605 606 fx->fc = 0; 607 } 608 609 /* Write out a short form instruction by itself. */ 610 611 static void 612 write_1_short (struct d30v_insn *opcode, 613 long long insn, 614 Fixups *fx, 615 int use_sequential) 616 { 617 char *f = frag_more (8); 618 int i, where; 619 620 dwarf2_emit_insn (8); 621 if (warn_nops == NOP_ALL) 622 as_warn (_("%s NOP inserted"), use_sequential ? 623 _("sequential") : _("parallel")); 624 625 /* The other container needs to be NOP. */ 626 if (use_sequential) 627 { 628 /* Use a sequential NOP rather than a parallel one, 629 as the current instruction is a FLAG_MUL32 type one 630 and the next instruction is a load. */ 631 632 /* According to 4.3.1: for FM=01, sub-instructions performed 633 only by IU cannot be encoded in L-container. */ 634 if (opcode->op->unit == IU) 635 /* Right then left. */ 636 insn |= FM10 | NOP_LEFT; 637 else 638 /* Left then right. */ 639 insn = FM01 | (insn << 32) | NOP_RIGHT; 640 } 641 else 642 { 643 /* According to 4.3.1: for FM=00, sub-instructions performed 644 only by IU cannot be encoded in L-container. */ 645 if (opcode->op->unit == IU) 646 /* Right container. */ 647 insn |= FM00 | NOP_LEFT; 648 else 649 /* Left container. */ 650 insn = FM00 | (insn << 32) | NOP_RIGHT; 651 } 652 653 d30v_number_to_chars (f, insn, 8); 654 655 for (i = 0; i < fx->fc; i++) 656 { 657 if (fx->fix[i].reloc) 658 { 659 where = f - frag_now->fr_literal; 660 fix_new_exp (frag_now, 661 where, 662 fx->fix[i].size, 663 &(fx->fix[i].exp), 664 fx->fix[i].pcrel, 665 fx->fix[i].reloc); 666 } 667 } 668 669 fx->fc = 0; 670 } 671 672 /* Check 2 instructions and determine if they can be safely 673 executed in parallel. Return 1 if they can be. */ 674 675 static int 676 parallel_ok (struct d30v_insn *op1, 677 unsigned long insn1, 678 struct d30v_insn *op2, 679 unsigned long insn2, 680 exec_type_enum exec_type) 681 { 682 int i, j, shift, regno, bits, ecc; 683 unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2; 684 unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2]; 685 struct d30v_format *f; 686 struct d30v_opcode *op; 687 688 /* Section 4.3: Both instructions must not be IU or MU only. */ 689 if ((op1->op->unit == IU && op2->op->unit == IU) 690 || (op1->op->unit == MU && op2->op->unit == MU)) 691 return 0; 692 693 /* First instruction must not be a jump to safely optimize, unless this 694 is an explicit parallel operation. */ 695 if (exec_type != EXEC_PARALLEL 696 && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))) 697 return 0; 698 699 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively, 700 then it is safe to allow the two to be done as parallel ops, since only 701 one will ever be executed at a time. */ 702 if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX) 703 || (op1->ecc == ECC_FX && op2->ecc == ECC_TX) 704 || (op1->ecc == ECC_XT && op2->ecc == ECC_XF) 705 || (op1->ecc == ECC_XF && op2->ecc == ECC_XT)) 706 return 1; 707 708 /* [0] r0-r31 709 [1] r32-r63 710 [2] a0, a1, flag registers. */ 711 for (j = 0; j < 2; j++) 712 { 713 if (j == 0) 714 { 715 f = op1->form; 716 op = op1->op; 717 ecc = op1->ecc; 718 ins = insn1; 719 } 720 else 721 { 722 f = op2->form; 723 op = op2->op; 724 ecc = op2->ecc; 725 ins = insn2; 726 } 727 728 flag_reg[j] = 0; 729 mod_reg[j][0] = mod_reg[j][1] = 0; 730 used_reg[j][0] = used_reg[j][1] = 0; 731 732 if (flag_explicitly_parallel) 733 { 734 /* For human specified parallel instructions we have been asked 735 to ignore the possibility that both instructions could modify 736 bits in the PSW, so we initialise the mod & used arrays to 0. 737 We have been asked, however, to refuse to allow parallel 738 instructions which explicitly set the same flag register, 739 eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test 740 for the use of a flag register and set a bit in the mod or used 741 array appropriately. */ 742 mod_reg[j][2] = 0; 743 used_reg[j][2] = 0; 744 } 745 else 746 { 747 mod_reg[j][2] = (op->flags_set & FLAG_ALL); 748 used_reg[j][2] = (op->flags_used & FLAG_ALL); 749 } 750 751 /* BSR/JSR always sets R62. */ 752 if (op->flags_used & FLAG_JSR) 753 mod_reg[j][1] = (1L << (62 - 32)); 754 755 /* Conditional execution affects the flags_used. */ 756 switch (ecc) 757 { 758 case ECC_TX: 759 case ECC_FX: 760 used_reg[j][2] |= flag_reg[j] = FLAG_0; 761 break; 762 763 case ECC_XT: 764 case ECC_XF: 765 used_reg[j][2] |= flag_reg[j] = FLAG_1; 766 break; 767 768 case ECC_TT: 769 case ECC_TF: 770 used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1); 771 break; 772 } 773 774 for (i = 0; f->operands[i]; i++) 775 { 776 flags = d30v_operand_table[f->operands[i]].flags; 777 shift = 12 - d30v_operand_table[f->operands[i]].position; 778 bits = d30v_operand_table[f->operands[i]].bits; 779 if (bits == 32) 780 mask = 0xffffffff; 781 else 782 mask = 0x7FFFFFFF >> (31 - bits); 783 784 if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS)) 785 { 786 /* This is a post-increment or post-decrement. 787 The previous register needs to be marked as modified. */ 788 shift = 12 - d30v_operand_table[f->operands[i - 1]].position; 789 regno = (ins >> shift) & 0x3f; 790 if (regno >= 32) 791 mod_reg[j][1] |= 1L << (regno - 32); 792 else 793 mod_reg[j][0] |= 1L << regno; 794 } 795 else if (flags & OPERAND_REG) 796 { 797 regno = (ins >> shift) & mask; 798 /* The memory write functions don't have a destination 799 register. */ 800 if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM)) 801 { 802 /* MODIFIED registers and flags. */ 803 if (flags & OPERAND_ACC) 804 { 805 if (regno == 0) 806 mod_reg[j][2] |= FLAG_A0; 807 else if (regno == 1) 808 mod_reg[j][2] |= FLAG_A1; 809 else 810 abort (); 811 } 812 else if (flags & OPERAND_FLAG) 813 mod_reg[j][2] |= 1L << regno; 814 else if (!(flags & OPERAND_CONTROL)) 815 { 816 int r, z; 817 818 /* Need to check if there are two destination 819 registers, for example ld2w. */ 820 if (flags & OPERAND_2REG) 821 z = 1; 822 else 823 z = 0; 824 825 for (r = regno; r <= regno + z; r++) 826 { 827 if (r >= 32) 828 mod_reg[j][1] |= 1L << (r - 32); 829 else 830 mod_reg[j][0] |= 1L << r; 831 } 832 } 833 } 834 else 835 { 836 /* USED, but not modified registers and flags. */ 837 if (flags & OPERAND_ACC) 838 { 839 if (regno == 0) 840 used_reg[j][2] |= FLAG_A0; 841 else if (regno == 1) 842 used_reg[j][2] |= FLAG_A1; 843 else 844 abort (); 845 } 846 else if (flags & OPERAND_FLAG) 847 used_reg[j][2] |= 1L << regno; 848 else if (!(flags & OPERAND_CONTROL)) 849 { 850 int r, z; 851 852 /* Need to check if there are two source 853 registers, for example st2w. */ 854 if (flags & OPERAND_2REG) 855 z = 1; 856 else 857 z = 0; 858 859 for (r = regno; r <= regno + z; r++) 860 { 861 if (r >= 32) 862 used_reg[j][1] |= 1UL << (r - 32); 863 else 864 used_reg[j][0] |= 1UL << r; 865 } 866 } 867 } 868 } 869 } 870 } 871 872 flags_set1 = op1->op->flags_set; 873 flags_set2 = op2->op->flags_set; 874 flags_used1 = op1->op->flags_used; 875 flags_used2 = op2->op->flags_used; 876 877 /* Check for illegal combinations with ADDppp/SUBppp. */ 878 if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0 879 && (flags_used2 & FLAG_ADDSUBppp) != 0) 880 || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0 881 && (flags_used1 & FLAG_ADDSUBppp) != 0)) 882 return 0; 883 884 /* Load instruction combined with half-word multiply is illegal. */ 885 if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16)) 886 || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16))) 887 return 0; 888 889 /* Specifically allow add || add by removing carry, overflow bits dependency. 890 This is safe, even if an addc follows since the IU takes the argument in 891 the right container, and it writes its results last. 892 However, don't paralellize add followed by addc or sub followed by 893 subb. */ 894 if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA 895 && (used_reg[0][2] & ~flag_reg[0]) == 0 896 && (used_reg[1][2] & ~flag_reg[1]) == 0 897 && op1->op->unit == EITHER && op2->op->unit == EITHER) 898 { 899 mod_reg[0][2] = mod_reg[1][2] = 0; 900 } 901 902 for (j = 0; j < 3; j++) 903 { 904 /* If the second instruction depends on the first, we obviously 905 cannot parallelize. Note, the mod flag implies use, so 906 check that as well. */ 907 /* If flag_explicitly_parallel is set, then the case of the 908 second instruction using a register the first instruction 909 modifies is assumed to be okay; we trust the human. We 910 don't trust the human if both instructions modify the same 911 register but we do trust the human if they modify the same 912 flags. */ 913 /* We have now been requested not to trust the human if the 914 instructions modify the same flag registers either. */ 915 if (flag_explicitly_parallel) 916 { 917 if ((mod_reg[0][j] & mod_reg[1][j]) != 0) 918 return 0; 919 } 920 else 921 if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0) 922 return 0; 923 } 924 925 return 1; 926 } 927 928 /* Write out a short form instruction if possible. 929 Return number of instructions not written out. */ 930 931 static int 932 write_2_short (struct d30v_insn *opcode1, 933 long long insn1, 934 struct d30v_insn *opcode2, 935 long long insn2, 936 exec_type_enum exec_type, 937 Fixups *fx) 938 { 939 long long insn = NOP2; 940 char *f; 941 int i, j, where; 942 943 if (exec_type == EXEC_SEQ 944 && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)) 945 && ((opcode1->op->flags_used & FLAG_DELAY) == 0) 946 && ((opcode1->ecc == ECC_AL) || ! Optimizing)) 947 { 948 /* Unconditional, non-delayed branches kill instructions in 949 the right bin. Conditional branches don't always but if 950 we are not optimizing, then we have been asked to produce 951 an error about such constructs. For the purposes of this 952 test, subroutine calls are considered to be branches. */ 953 write_1_short (opcode1, insn1, fx->next, false); 954 return 1; 955 } 956 957 /* Note: we do not have to worry about subroutine calls occurring 958 in the right hand container. The return address is always 959 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */ 960 switch (exec_type) 961 { 962 case EXEC_UNKNOWN: /* Order not specified. */ 963 if (Optimizing 964 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type) 965 && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU 966 || opcode1->op->unit == MU) 967 && 968 ( opcode2->op->unit == EITHER_BUT_PREFER_MU 969 || opcode2->op->unit == MU))) 970 { 971 /* Parallel. */ 972 exec_type = EXEC_PARALLEL; 973 974 if (opcode1->op->unit == IU 975 || opcode2->op->unit == MU 976 || opcode2->op->unit == EITHER_BUT_PREFER_MU) 977 insn = FM00 | (insn2 << 32) | insn1; 978 else 979 { 980 insn = FM00 | (insn1 << 32) | insn2; 981 fx = fx->next; 982 } 983 } 984 else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR) 985 && ((opcode1->op->flags_used & FLAG_DELAY) == 0)) 986 || opcode1->op->flags_used & FLAG_RP) 987 { 988 /* We must emit (non-delayed) branch type instructions 989 on their own with nothing in the right container. */ 990 /* We must treat repeat instructions likewise, since the 991 following instruction has to be separate from the repeat 992 in order to be repeated. */ 993 write_1_short (opcode1, insn1, fx->next, false); 994 return 1; 995 } 996 else if (prev_left_kills_right_p) 997 { 998 /* The left instruction kills the right slot, so we 999 must leave it empty. */ 1000 write_1_short (opcode1, insn1, fx->next, false); 1001 return 1; 1002 } 1003 else if (opcode1->op->unit == IU) 1004 { 1005 if (opcode2->op->unit == EITHER_BUT_PREFER_MU) 1006 { 1007 /* Case 103810 is a request from Mitsubishi that opcodes 1008 with EITHER_BUT_PREFER_MU should not be executed in 1009 reverse sequential order. */ 1010 write_1_short (opcode1, insn1, fx->next, false); 1011 return 1; 1012 } 1013 1014 /* Reverse sequential. */ 1015 insn = FM10 | (insn2 << 32) | insn1; 1016 exec_type = EXEC_REVSEQ; 1017 } 1018 else 1019 { 1020 /* Sequential. */ 1021 insn = FM01 | (insn1 << 32) | insn2; 1022 fx = fx->next; 1023 exec_type = EXEC_SEQ; 1024 } 1025 break; 1026 1027 case EXEC_PARALLEL: /* Parallel. */ 1028 flag_explicitly_parallel = flag_xp_state; 1029 if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) 1030 as_bad (_("Instructions may not be executed in parallel")); 1031 else if (opcode1->op->unit == IU) 1032 { 1033 if (opcode2->op->unit == IU) 1034 as_bad (_("Two IU instructions may not be executed in parallel")); 1035 as_warn (_("Swapping instruction order")); 1036 insn = FM00 | (insn2 << 32) | insn1; 1037 } 1038 else if (opcode2->op->unit == MU) 1039 { 1040 if (opcode1->op->unit == MU) 1041 as_bad (_("Two MU instructions may not be executed in parallel")); 1042 else if (opcode1->op->unit == EITHER_BUT_PREFER_MU) 1043 as_warn (_("Executing %s in IU may not work"), opcode1->op->name); 1044 as_warn (_("Swapping instruction order")); 1045 insn = FM00 | (insn2 << 32) | insn1; 1046 } 1047 else 1048 { 1049 if (opcode2->op->unit == EITHER_BUT_PREFER_MU) 1050 as_warn (_("Executing %s in IU may not work in parallel execution"), 1051 opcode2->op->name); 1052 1053 insn = FM00 | (insn1 << 32) | insn2; 1054 fx = fx->next; 1055 } 1056 flag_explicitly_parallel = 0; 1057 break; 1058 1059 case EXEC_SEQ: /* Sequential. */ 1060 if (opcode1->op->unit == IU) 1061 as_bad (_("IU instruction may not be in the left container")); 1062 if (prev_left_kills_right_p) 1063 as_bad (_("special left instruction `%s' kills instruction " 1064 "`%s' in right container"), 1065 opcode1->op->name, opcode2->op->name); 1066 insn = FM01 | (insn1 << 32) | insn2; 1067 fx = fx->next; 1068 break; 1069 1070 case EXEC_REVSEQ: /* Reverse sequential. */ 1071 if (opcode2->op->unit == MU) 1072 as_bad (_("MU instruction may not be in the right container")); 1073 if (opcode1->op->unit == EITHER_BUT_PREFER_MU) 1074 as_warn (_("Executing %s in reverse serial with %s may not work"), 1075 opcode1->op->name, opcode2->op->name); 1076 else if (opcode2->op->unit == EITHER_BUT_PREFER_MU) 1077 as_warn (_("Executing %s in IU in reverse serial may not work"), 1078 opcode2->op->name); 1079 insn = FM10 | (insn1 << 32) | insn2; 1080 fx = fx->next; 1081 break; 1082 1083 default: 1084 as_fatal (_("unknown execution type passed to write_2_short()")); 1085 } 1086 1087 f = frag_more (8); 1088 dwarf2_emit_insn (8); 1089 d30v_number_to_chars (f, insn, 8); 1090 1091 /* If the previous instruction was a 32-bit multiply but it is put into a 1092 parallel container, mark the current instruction as being a 32-bit 1093 multiply. */ 1094 if (prev_mul32_p && exec_type == EXEC_PARALLEL) 1095 cur_mul32_p = 1; 1096 1097 for (j = 0; j < 2; j++) 1098 { 1099 for (i = 0; i < fx->fc; i++) 1100 { 1101 if (fx->fix[i].reloc) 1102 { 1103 where = (f - frag_now->fr_literal) + 4 * j; 1104 1105 fix_new_exp (frag_now, 1106 where, 1107 fx->fix[i].size, 1108 &(fx->fix[i].exp), 1109 fx->fix[i].pcrel, 1110 fx->fix[i].reloc); 1111 } 1112 } 1113 1114 fx->fc = 0; 1115 fx = fx->next; 1116 } 1117 1118 return 0; 1119 } 1120 1121 /* Get a pointer to an entry in the format table. 1122 It must look at all formats for an opcode and use the operands 1123 to choose the correct one. Return NULL on error. */ 1124 1125 static struct d30v_format * 1126 find_format (struct d30v_opcode *opcode, 1127 expressionS myops[], 1128 int fsize, 1129 int cmp_hack) 1130 { 1131 int match, opcode_index, i = 0, j, k; 1132 struct d30v_format *fm; 1133 1134 if (opcode == NULL) 1135 return NULL; 1136 1137 /* Get all the operands and save them as expressions. */ 1138 get_operands (myops, cmp_hack); 1139 1140 while ((opcode_index = opcode->format[i++]) != 0) 1141 { 1142 if (fsize == FORCE_SHORT && opcode_index >= LONG) 1143 continue; 1144 1145 if (fsize == FORCE_LONG && opcode_index < LONG) 1146 continue; 1147 1148 fm = (struct d30v_format *) &d30v_format_table[opcode_index]; 1149 k = opcode_index; 1150 while (fm->form == opcode_index) 1151 { 1152 match = 1; 1153 /* Now check the operands for compatibility. */ 1154 for (j = 0; match && fm->operands[j]; j++) 1155 { 1156 int flags = d30v_operand_table[fm->operands[j]].flags; 1157 int bits = d30v_operand_table[fm->operands[j]].bits; 1158 operatorT X_op = myops[j].X_op; 1159 int num = myops[j].X_add_number; 1160 1161 if (flags & OPERAND_SPECIAL) 1162 break; 1163 else if (X_op == O_illegal) 1164 match = 0; 1165 else if (flags & OPERAND_REG) 1166 { 1167 if (X_op != O_register 1168 || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) 1169 || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC)) 1170 || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) 1171 || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG)) 1172 || ((flags & OPERAND_CONTROL) 1173 && !(num & (OPERAND_CONTROL | OPERAND_FLAG)))) 1174 match = 0; 1175 } 1176 else if (((flags & OPERAND_MINUS) 1177 && (X_op != O_absent || num != OPERAND_MINUS)) 1178 || ((flags & OPERAND_PLUS) 1179 && (X_op != O_absent || num != OPERAND_PLUS)) 1180 || ((flags & OPERAND_ATMINUS) 1181 && (X_op != O_absent || num != OPERAND_ATMINUS)) 1182 || ((flags & OPERAND_ATPAR) 1183 && (X_op != O_absent || num != OPERAND_ATPAR)) 1184 || ((flags & OPERAND_ATSIGN) 1185 && (X_op != O_absent || num != OPERAND_ATSIGN))) 1186 match = 0; 1187 else if (flags & OPERAND_NUM) 1188 { 1189 /* A number can be a constant or symbol expression. */ 1190 1191 /* If we have found a register name, but that name 1192 also matches a symbol, then re-parse the name as 1193 an expression. */ 1194 if (X_op == O_register 1195 && symbol_find ((char *) myops[j].X_op_symbol)) 1196 { 1197 input_line_pointer = (char *) myops[j].X_op_symbol; 1198 expression (&myops[j]); 1199 } 1200 1201 /* Turn an expression into a symbol for later resolution. */ 1202 if (X_op != O_absent && X_op != O_constant 1203 && X_op != O_symbol && X_op != O_register 1204 && X_op != O_big) 1205 { 1206 symbolS *sym = make_expr_symbol (&myops[j]); 1207 myops[j].X_op = X_op = O_symbol; 1208 myops[j].X_add_symbol = sym; 1209 myops[j].X_add_number = num = 0; 1210 } 1211 1212 if (fm->form >= LONG) 1213 { 1214 /* If we're testing for a LONG format, either fits. */ 1215 if (X_op != O_constant && X_op != O_symbol) 1216 match = 0; 1217 } 1218 else if (fm->form < LONG 1219 && ((fsize == FORCE_SHORT && X_op == O_symbol) 1220 || (fm->form == SHORT_D2 && j == 0))) 1221 match = 1; 1222 1223 /* This is the tricky part. Will the constant or symbol 1224 fit into the space in the current format? */ 1225 else if (X_op == O_constant) 1226 { 1227 if (check_range (num, bits, flags)) 1228 match = 0; 1229 } 1230 else if (X_op == O_symbol 1231 && S_IS_DEFINED (myops[j].X_add_symbol) 1232 && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg 1233 && opcode->reloc_flag == RELOC_PCREL) 1234 { 1235 /* If the symbol is defined, see if the value will fit 1236 into the form we're considering. */ 1237 fragS *f; 1238 long value; 1239 1240 /* Calculate the current address by running through the 1241 previous frags and adding our current offset. */ 1242 value = frag_now_fix_octets (); 1243 for (f = frchain_now->frch_root; f; f = f->fr_next) 1244 value += f->fr_fix + f->fr_offset; 1245 value = S_GET_VALUE (myops[j].X_add_symbol) - value; 1246 if (check_range (value, bits, flags)) 1247 match = 0; 1248 } 1249 else 1250 match = 0; 1251 } 1252 } 1253 /* We're only done if the operands matched so far AND there 1254 are no more to check. */ 1255 if (match && myops[j].X_op == 0) 1256 { 1257 /* Final check - issue a warning if an odd numbered register 1258 is used as the first register in an instruction that reads 1259 or writes 2 registers. */ 1260 1261 for (j = 0; fm->operands[j]; j++) 1262 if (myops[j].X_op == O_register 1263 && (myops[j].X_add_number & 1) 1264 && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG)) 1265 as_warn (_("Odd numbered register used as target of multi-register instruction")); 1266 1267 return fm; 1268 } 1269 fm = (struct d30v_format *) &d30v_format_table[++k]; 1270 } 1271 } 1272 return NULL; 1273 } 1274 1275 /* Assemble a single instruction and return an opcode. 1276 Return -1 (an invalid opcode) on error. */ 1277 1278 #define NAME_BUF_LEN 20 1279 1280 static long long 1281 do_assemble (char *str, 1282 struct d30v_insn *opcode, 1283 int shortp, 1284 int is_parallel) 1285 { 1286 char *op_start; 1287 char *save; 1288 char *op_end; 1289 char name[NAME_BUF_LEN]; 1290 int cmp_hack; 1291 int nlen = 0; 1292 int fsize = (shortp ? FORCE_SHORT : 0); 1293 expressionS myops[6]; 1294 long long insn; 1295 1296 /* Drop leading whitespace. */ 1297 while (*str == ' ') 1298 str++; 1299 1300 /* Find the opcode end. */ 1301 for (op_start = op_end = str; 1302 *op_end 1303 && nlen < (NAME_BUF_LEN - 1) 1304 && *op_end != '/' 1305 && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' '; 1306 op_end++) 1307 { 1308 name[nlen] = TOLOWER (op_start[nlen]); 1309 nlen++; 1310 } 1311 1312 if (nlen == 0) 1313 return -1; 1314 1315 name[nlen] = 0; 1316 1317 /* If there is an execution condition code, handle it. */ 1318 if (*op_end == '/') 1319 { 1320 int i = 0; 1321 while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2)) 1322 i++; 1323 1324 if (i == ECC_MAX) 1325 { 1326 char tmp[4]; 1327 strncpy (tmp, op_end + 1, 2); 1328 tmp[2] = 0; 1329 as_bad (_("unknown condition code: %s"), tmp); 1330 return -1; 1331 } 1332 opcode->ecc = i; 1333 op_end += 3; 1334 } 1335 else 1336 opcode->ecc = ECC_AL; 1337 1338 /* CMP and CMPU change their name based on condition codes. */ 1339 if (startswith (name, "cmp")) 1340 { 1341 int p, i; 1342 char **d30v_str = (char **) d30v_cc_names; 1343 1344 if (name[3] == 'u') 1345 p = 4; 1346 else 1347 p = 3; 1348 1349 for (i = 1; *d30v_str && strncmp (*d30v_str, &name[p], 2); i++, d30v_str++) 1350 ; 1351 1352 /* cmpu only supports some condition codes. */ 1353 if (p == 4) 1354 { 1355 if (i < 3 || i > 6) 1356 { 1357 name[p + 2] = 0; 1358 as_bad (_("cmpu doesn't support condition code %s"), &name[p]); 1359 } 1360 } 1361 1362 if (!*d30v_str) 1363 { 1364 name[p + 2] = 0; 1365 as_bad (_("unknown condition code: %s"), &name[p]); 1366 } 1367 1368 cmp_hack = i; 1369 name[p] = 0; 1370 } 1371 else 1372 cmp_hack = 0; 1373 1374 /* Need to look for .s or .l. */ 1375 if (name[nlen - 2] == '.') 1376 { 1377 switch (name[nlen - 1]) 1378 { 1379 case 's': 1380 fsize = FORCE_SHORT; 1381 break; 1382 case 'l': 1383 fsize = FORCE_LONG; 1384 break; 1385 } 1386 name[nlen - 2] = 0; 1387 } 1388 1389 /* Find the first opcode with the proper name. */ 1390 opcode->op = (struct d30v_opcode *) str_hash_find (d30v_hash, name); 1391 if (opcode->op == NULL) 1392 { 1393 as_bad (_("unknown opcode: %s"), name); 1394 return -1; 1395 } 1396 1397 save = input_line_pointer; 1398 input_line_pointer = op_end; 1399 while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack))) 1400 { 1401 opcode->op++; 1402 if (opcode->op->name == NULL || strcmp (opcode->op->name, name)) 1403 { 1404 as_bad (_("operands for opcode `%s' do not match any valid format"), 1405 name); 1406 return -1; 1407 } 1408 } 1409 input_line_pointer = save; 1410 1411 insn = build_insn (opcode, myops); 1412 1413 /* Propagate multiply status. */ 1414 if (insn != -1) 1415 { 1416 if (is_parallel && prev_mul32_p) 1417 cur_mul32_p = 1; 1418 else 1419 { 1420 prev_mul32_p = cur_mul32_p; 1421 cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0; 1422 } 1423 } 1424 1425 /* Propagate left_kills_right status. */ 1426 if (insn != -1) 1427 { 1428 prev_left_kills_right_p = cur_left_kills_right_p; 1429 1430 if (opcode->op->flags_set & FLAG_LKR) 1431 { 1432 cur_left_kills_right_p = 1; 1433 1434 if (strcmp (opcode->op->name, "mvtsys") == 0) 1435 { 1436 /* Left kills right for only mvtsys only for 1437 PSW/PSWH/PSWL/flags target. */ 1438 if ((myops[0].X_op == O_register) && 1439 ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */ 1440 (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */ 1441 (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */ 1442 (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */ 1443 (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */ 1444 (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */ 1445 (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */ 1446 (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */ 1447 (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */ 1448 (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */ 1449 (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */ 1450 { 1451 cur_left_kills_right_p = 1; 1452 } 1453 else 1454 { 1455 /* Other mvtsys target registers don't kill right 1456 instruction. */ 1457 cur_left_kills_right_p = 0; 1458 } 1459 } /* mvtsys */ 1460 } 1461 else 1462 cur_left_kills_right_p = 0; 1463 } 1464 1465 return insn; 1466 } 1467 1468 /* Called internally to handle all alignment needs. This takes care 1469 of eliding calls to frag_align if'n the cached current alignment 1470 says we've already got it, as well as taking care of the auto-aligning 1471 labels wrt code. */ 1472 1473 static void 1474 d30v_align (int n, char *pfill, symbolS *label) 1475 { 1476 /* The front end is prone to changing segments out from under us 1477 temporarily when -g is in effect. */ 1478 int switched_seg_p = (d30v_current_align_seg != now_seg); 1479 1480 /* Do not assume that if 'd30v_current_align >= n' and 1481 '! switched_seg_p' that it is safe to avoid performing 1482 this alignment request. The alignment of the current frag 1483 can be changed under our feet, for example by a .ascii 1484 directive in the source code. cf testsuite/gas/d30v/reloc.s */ 1485 d30v_cleanup (false); 1486 1487 if (pfill == NULL) 1488 { 1489 if (n > 2 1490 && (bfd_section_flags (now_seg) & SEC_CODE) != 0) 1491 { 1492 static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 }; 1493 1494 /* First, make sure we're on a four-byte boundary, in case 1495 someone has been putting .byte values the text section. */ 1496 if (d30v_current_align < 2 || switched_seg_p) 1497 frag_align (2, 0, 0); 1498 frag_align_pattern (n, nop, sizeof nop, 0); 1499 } 1500 else 1501 frag_align (n, 0, 0); 1502 } 1503 else 1504 frag_align (n, *pfill, 0); 1505 1506 if (!switched_seg_p) 1507 d30v_current_align = n; 1508 1509 if (label != NULL) 1510 { 1511 symbolS *sym; 1512 int label_seen = false; 1513 struct frag *old_frag; 1514 valueT old_value; 1515 valueT new_value; 1516 1517 gas_assert (S_GET_SEGMENT (label) == now_seg); 1518 1519 old_frag = symbol_get_frag (label); 1520 old_value = S_GET_VALUE (label); 1521 new_value = (valueT) frag_now_fix (); 1522 1523 /* It is possible to have more than one label at a particular 1524 address, especially if debugging is enabled, so we must 1525 take care to adjust all the labels at this address in this 1526 fragment. To save time we search from the end of the symbol 1527 list, backwards, since the symbols we are interested in are 1528 almost certainly the ones that were most recently added. 1529 Also to save time we stop searching once we have seen at least 1530 one matching label, and we encounter a label that is no longer 1531 in the target fragment. Note, this search is guaranteed to 1532 find at least one match when sym == label, so no special case 1533 code is necessary. */ 1534 for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym)) 1535 { 1536 if (symbol_get_frag (sym) == old_frag 1537 && S_GET_VALUE (sym) == old_value) 1538 { 1539 label_seen = true; 1540 symbol_set_frag (sym, frag_now); 1541 S_SET_VALUE (sym, new_value); 1542 } 1543 else if (label_seen && symbol_get_frag (sym) != old_frag) 1544 break; 1545 } 1546 } 1547 1548 record_alignment (now_seg, n); 1549 } 1550 1551 /* This is the main entry point for the machine-dependent assembler. 1552 STR points to a machine-dependent instruction. This function is 1553 supposed to emit the frags/bytes it assembles to. For the D30V, it 1554 mostly handles the special VLIW parsing and packing and leaves the 1555 difficult stuff to do_assemble (). */ 1556 1557 static long long prev_insn = -1; 1558 static struct d30v_insn prev_opcode; 1559 static subsegT prev_subseg; 1560 static segT prev_seg = 0; 1561 1562 void 1563 md_assemble (char *str) 1564 { 1565 struct d30v_insn opcode; 1566 long long insn; 1567 /* Execution type; parallel, etc. */ 1568 exec_type_enum extype = EXEC_UNKNOWN; 1569 /* Saved extype. Used for multiline instructions. */ 1570 static exec_type_enum etype = EXEC_UNKNOWN; 1571 char *str2; 1572 1573 if ((prev_insn != -1) && prev_seg 1574 && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) 1575 d30v_cleanup (false); 1576 1577 if (d30v_current_align < 3) 1578 d30v_align (3, NULL, d30v_last_label); 1579 else if (d30v_current_align > 3) 1580 d30v_current_align = 3; 1581 d30v_last_label = NULL; 1582 1583 flag_explicitly_parallel = 0; 1584 flag_xp_state = 0; 1585 if (etype == EXEC_UNKNOWN) 1586 { 1587 /* Look for the special multiple instruction separators. */ 1588 str2 = strstr (str, "||"); 1589 if (str2) 1590 { 1591 extype = EXEC_PARALLEL; 1592 flag_xp_state = 1; 1593 } 1594 else 1595 { 1596 str2 = strstr (str, "->"); 1597 if (str2) 1598 extype = EXEC_SEQ; 1599 else 1600 { 1601 str2 = strstr (str, "<-"); 1602 if (str2) 1603 extype = EXEC_REVSEQ; 1604 } 1605 } 1606 1607 /* STR2 points to the separator, if one. */ 1608 if (str2) 1609 { 1610 *str2 = 0; 1611 1612 /* If two instructions are present and we already have one saved, 1613 then first write it out. */ 1614 d30v_cleanup (false); 1615 1616 /* Assemble first instruction and save it. */ 1617 prev_insn = do_assemble (str, &prev_opcode, 1, 0); 1618 if (prev_insn == -1) 1619 as_bad (_("Cannot assemble instruction")); 1620 if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG) 1621 as_bad (_("First opcode is long. Unable to mix instructions as specified.")); 1622 fixups = fixups->next; 1623 str = str2 + 2; 1624 prev_seg = now_seg; 1625 prev_subseg = now_subseg; 1626 } 1627 } 1628 1629 insn = do_assemble (str, &opcode, 1630 (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN), 1631 extype == EXEC_PARALLEL); 1632 if (insn == -1) 1633 { 1634 if (extype != EXEC_UNKNOWN) 1635 etype = extype; 1636 as_bad (_("Cannot assemble instruction")); 1637 return; 1638 } 1639 1640 if (etype != EXEC_UNKNOWN) 1641 { 1642 extype = etype; 1643 etype = EXEC_UNKNOWN; 1644 } 1645 1646 /* Word multiply instructions must not be followed by either a load or a 1647 16-bit multiply instruction in the next cycle. */ 1648 if ( (extype != EXEC_REVSEQ) 1649 && prev_mul32_p 1650 && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) 1651 { 1652 /* However, load and multiply should able to be combined in a parallel 1653 operation, so check for that first. */ 1654 if (prev_insn != -1 1655 && (opcode.op->flags_used & FLAG_MEM) 1656 && opcode.form->form < LONG 1657 && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN)) 1658 && parallel_ok (&prev_opcode, (long) prev_insn, 1659 &opcode, (long) insn, extype) 1660 && write_2_short (&prev_opcode, (long) prev_insn, 1661 &opcode, (long) insn, extype, fixups) == 0) 1662 { 1663 /* No instructions saved. */ 1664 prev_insn = -1; 1665 return; 1666 } 1667 else 1668 { 1669 /* Can't parallelize, flush previous instruction and emit a 1670 word of NOPS, unless the previous instruction is a NOP, 1671 in which case just flush it, as this will generate a word 1672 of NOPs for us. */ 1673 1674 if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0)) 1675 d30v_cleanup (false); 1676 else 1677 { 1678 char *f; 1679 1680 if (prev_insn != -1) 1681 d30v_cleanup (true); 1682 else 1683 { 1684 f = frag_more (8); 1685 dwarf2_emit_insn (8); 1686 d30v_number_to_chars (f, NOP2, 8); 1687 1688 if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY) 1689 { 1690 if (opcode.op->flags_used & FLAG_MEM) 1691 as_warn (_("word of NOPs added between word multiply and load")); 1692 else 1693 as_warn (_("word of NOPs added between word multiply and 16-bit multiply")); 1694 } 1695 } 1696 } 1697 1698 extype = EXEC_UNKNOWN; 1699 } 1700 } 1701 else if ( (extype == EXEC_REVSEQ) 1702 && cur_mul32_p 1703 && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16))) 1704 { 1705 /* Can't parallelize, flush current instruction and add a 1706 sequential NOP. */ 1707 write_1_short (&opcode, (long) insn, fixups->next->next, true); 1708 1709 /* Make the previous instruction the current one. */ 1710 extype = EXEC_UNKNOWN; 1711 insn = prev_insn; 1712 now_seg = prev_seg; 1713 now_subseg = prev_subseg; 1714 prev_insn = -1; 1715 cur_mul32_p = prev_mul32_p; 1716 prev_mul32_p = 0; 1717 memcpy (&opcode, &prev_opcode, sizeof (prev_opcode)); 1718 } 1719 1720 /* If this is a long instruction, write it and any previous short 1721 instruction. */ 1722 if (opcode.form->form >= LONG) 1723 { 1724 if (extype != EXEC_UNKNOWN) 1725 as_bad (_("Instruction uses long version, so it cannot be mixed as specified")); 1726 d30v_cleanup (false); 1727 write_long (&opcode, insn, fixups); 1728 prev_insn = -1; 1729 } 1730 else if ((prev_insn != -1) 1731 && (write_2_short 1732 (&prev_opcode, (long) prev_insn, &opcode, 1733 (long) insn, extype, fixups) == 0)) 1734 { 1735 /* No instructions saved. */ 1736 prev_insn = -1; 1737 } 1738 else 1739 { 1740 if (extype != EXEC_UNKNOWN) 1741 as_bad (_("Unable to mix instructions as specified")); 1742 1743 /* Save off last instruction so it may be packed on next pass. */ 1744 memcpy (&prev_opcode, &opcode, sizeof (prev_opcode)); 1745 prev_insn = insn; 1746 prev_seg = now_seg; 1747 prev_subseg = now_subseg; 1748 fixups = fixups->next; 1749 prev_mul32_p = cur_mul32_p; 1750 } 1751 } 1752 1753 /* If while processing a fixup, a reloc really needs to be created, 1754 then it is done here. */ 1755 1756 arelent * 1757 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 1758 { 1759 arelent *reloc; 1760 reloc = XNEW (arelent); 1761 reloc->sym_ptr_ptr = XNEW (asymbol *); 1762 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1763 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1764 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 1765 if (reloc->howto == NULL) 1766 { 1767 as_bad_where (fixp->fx_file, fixp->fx_line, 1768 _("reloc %d not supported by object file format"), 1769 (int) fixp->fx_r_type); 1770 return NULL; 1771 } 1772 1773 reloc->addend = 0; 1774 return reloc; 1775 } 1776 1777 int 1778 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, 1779 asection *seg ATTRIBUTE_UNUSED) 1780 { 1781 abort (); 1782 return 0; 1783 } 1784 1785 long 1786 md_pcrel_from_section (fixS *fixp, segT sec) 1787 { 1788 if (fixp->fx_addsy != (symbolS *) NULL 1789 && (!S_IS_DEFINED (fixp->fx_addsy) 1790 || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) 1791 return 0; 1792 return fixp->fx_frag->fr_address + fixp->fx_where; 1793 } 1794 1795 /* Called after the assembler has finished parsing the input file or 1796 after a label is defined. Because the D30V assembler sometimes 1797 saves short instructions to see if it can package them with the 1798 next instruction, there may be a short instruction that still needs 1799 written. */ 1800 1801 int 1802 d30v_cleanup (int use_sequential) 1803 { 1804 segT seg; 1805 subsegT subseg; 1806 1807 if (prev_insn != -1) 1808 { 1809 seg = now_seg; 1810 subseg = now_subseg; 1811 subseg_set (prev_seg, prev_subseg); 1812 write_1_short (&prev_opcode, (long) prev_insn, fixups->next, 1813 use_sequential); 1814 subseg_set (seg, subseg); 1815 prev_insn = -1; 1816 if (use_sequential) 1817 prev_mul32_p = false; 1818 } 1819 1820 return 1; 1821 } 1822 1823 /* This function is called at the start of every line. It checks to 1824 see if the first character is a '.', which indicates the start of a 1825 pseudo-op. If it is, then write out any unwritten instructions. */ 1826 1827 void 1828 d30v_start_line (void) 1829 { 1830 char *c = input_line_pointer; 1831 1832 while (ISSPACE (*c)) 1833 c++; 1834 1835 if (*c == '.') 1836 d30v_cleanup (false); 1837 } 1838 1839 static void 1840 check_size (long value, int bits, const char *file, int line) 1841 { 1842 int tmp, max; 1843 1844 if (value < 0) 1845 tmp = ~value; 1846 else 1847 tmp = value; 1848 1849 max = (1 << (bits - 1)) - 1; 1850 1851 if (tmp > max) 1852 as_bad_where (file, line, _("value too large to fit in %d bits"), bits); 1853 } 1854 1855 /* d30v_frob_label() is called when after a label is recognized. */ 1856 1857 void 1858 d30v_frob_label (symbolS *lab) 1859 { 1860 /* Emit any pending instructions. */ 1861 d30v_cleanup (false); 1862 1863 /* Update the label's address with the current output pointer. */ 1864 symbol_set_frag (lab, frag_now); 1865 S_SET_VALUE (lab, (valueT) frag_now_fix ()); 1866 1867 /* Record this label for future adjustment after we find out what 1868 kind of data it references, and the required alignment therewith. */ 1869 d30v_last_label = lab; 1870 1871 dwarf2_emit_label (lab); 1872 } 1873 1874 /* Hook into cons for capturing alignment changes. */ 1875 1876 void 1877 d30v_cons_align (int size) 1878 { 1879 int log_size; 1880 1881 /* Don't specially align anything in debug sections. */ 1882 if ((now_seg->flags & SEC_ALLOC) == 0 1883 || strcmp (now_seg->name, ".eh_frame") == 0) 1884 return; 1885 1886 log_size = 0; 1887 while ((size >>= 1) != 0) 1888 ++log_size; 1889 1890 if (d30v_current_align < log_size) 1891 d30v_align (log_size, (char *) NULL, NULL); 1892 else if (d30v_current_align > log_size) 1893 d30v_current_align = log_size; 1894 d30v_last_label = NULL; 1895 } 1896 1897 void 1898 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 1899 { 1900 char *where; 1901 unsigned long insn, insn2; 1902 long value = *valP; 1903 1904 if (fixP->fx_addsy == (symbolS *) NULL) 1905 fixP->fx_done = 1; 1906 1907 /* We don't support subtracting a symbol. */ 1908 if (fixP->fx_subsy != (symbolS *) NULL) 1909 as_bad_subtract (fixP); 1910 1911 /* Fetch the instruction, insert the fully resolved operand 1912 value, and stuff the instruction back again. */ 1913 where = fixP->fx_frag->fr_literal + fixP->fx_where; 1914 insn = bfd_getb32 ((unsigned char *) where); 1915 1916 switch (fixP->fx_r_type) 1917 { 1918 case BFD_RELOC_8: 1919 *(unsigned char *) where = value; 1920 break; 1921 1922 case BFD_RELOC_16: 1923 bfd_putb16 ((bfd_vma) value, (unsigned char *) where); 1924 break; 1925 1926 case BFD_RELOC_64: 1927 bfd_putb32 ((bfd_vma) value, (unsigned char *) where); 1928 bfd_putb32 (0, ((unsigned char *) where) + 4); 1929 break; 1930 1931 case BFD_RELOC_D30V_6: 1932 check_size (value, 6, fixP->fx_file, fixP->fx_line); 1933 insn |= value & 0x3F; 1934 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1935 break; 1936 1937 case BFD_RELOC_D30V_9_PCREL: 1938 if (fixP->fx_where & 0x7) 1939 { 1940 if (fixP->fx_done) 1941 value += 4; 1942 else 1943 fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R; 1944 } 1945 check_size (value, 9, fixP->fx_file, fixP->fx_line); 1946 insn |= ((value >> 3) & 0x3F) << 12; 1947 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1948 break; 1949 1950 case BFD_RELOC_D30V_15: 1951 check_size (value, 15, fixP->fx_file, fixP->fx_line); 1952 insn |= (value >> 3) & 0xFFF; 1953 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1954 break; 1955 1956 case BFD_RELOC_D30V_15_PCREL: 1957 if (fixP->fx_where & 0x7) 1958 { 1959 if (fixP->fx_done) 1960 value += 4; 1961 else 1962 fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R; 1963 } 1964 check_size (value, 15, fixP->fx_file, fixP->fx_line); 1965 insn |= (value >> 3) & 0xFFF; 1966 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1967 break; 1968 1969 case BFD_RELOC_D30V_21: 1970 check_size (value, 21, fixP->fx_file, fixP->fx_line); 1971 insn |= (value >> 3) & 0x3FFFF; 1972 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1973 break; 1974 1975 case BFD_RELOC_D30V_21_PCREL: 1976 if (fixP->fx_where & 0x7) 1977 { 1978 if (fixP->fx_done) 1979 value += 4; 1980 else 1981 fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R; 1982 } 1983 check_size (value, 21, fixP->fx_file, fixP->fx_line); 1984 insn |= (value >> 3) & 0x3FFFF; 1985 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1986 break; 1987 1988 case BFD_RELOC_D30V_32: 1989 insn2 = bfd_getb32 ((unsigned char *) where + 4); 1990 insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ 1991 insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ 1992 insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ 1993 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1994 bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); 1995 break; 1996 1997 case BFD_RELOC_D30V_32_PCREL: 1998 insn2 = bfd_getb32 ((unsigned char *) where + 4); 1999 insn |= (value >> 26) & 0x3F; /* Top 6 bits. */ 2000 insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */ 2001 insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */ 2002 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 2003 bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4); 2004 break; 2005 2006 case BFD_RELOC_32: 2007 bfd_putb32 ((bfd_vma) value, (unsigned char *) where); 2008 break; 2009 2010 default: 2011 as_bad (_("line %d: unknown relocation type: 0x%x"), 2012 fixP->fx_line, fixP->fx_r_type); 2013 } 2014 } 2015 2016 /* Handle the .align pseudo-op. This aligns to a power of two. We 2017 hook here to latch the current alignment. */ 2018 2019 static void 2020 s_d30v_align (int ignore ATTRIBUTE_UNUSED) 2021 { 2022 int align; 2023 char fill, *pfill = NULL; 2024 long max_alignment = 15; 2025 2026 align = get_absolute_expression (); 2027 if (align > max_alignment) 2028 { 2029 align = max_alignment; 2030 as_warn (_("Alignment too large: %d assumed"), align); 2031 } 2032 else if (align < 0) 2033 { 2034 as_warn (_("Alignment negative: 0 assumed")); 2035 align = 0; 2036 } 2037 2038 if (*input_line_pointer == ',') 2039 { 2040 input_line_pointer++; 2041 fill = get_absolute_expression (); 2042 pfill = &fill; 2043 } 2044 2045 d30v_last_label = NULL; 2046 d30v_align (align, pfill, NULL); 2047 2048 demand_empty_rest_of_line (); 2049 } 2050 2051 /* Handle the .text pseudo-op. This is like the usual one, but it 2052 clears the saved last label and resets known alignment. */ 2053 2054 static void 2055 s_d30v_text (int i) 2056 2057 { 2058 obj_elf_text (i); 2059 d30v_last_label = NULL; 2060 d30v_current_align = 0; 2061 d30v_current_align_seg = now_seg; 2062 } 2063 2064 /* Handle the .data pseudo-op. This is like the usual one, but it 2065 clears the saved last label and resets known alignment. */ 2066 2067 static void 2068 s_d30v_data (int i) 2069 { 2070 obj_elf_data (i); 2071 d30v_last_label = NULL; 2072 d30v_current_align = 0; 2073 d30v_current_align_seg = now_seg; 2074 } 2075 2076 /* Handle the .section pseudo-op. This is like the usual one, but it 2077 clears the saved last label and resets known alignment. */ 2078 2079 static void 2080 s_d30v_section (int ignore) 2081 { 2082 obj_elf_section (ignore); 2083 d30v_last_label = NULL; 2084 d30v_current_align = 0; 2085 d30v_current_align_seg = now_seg; 2086 } 2087 2088 /* The target specific pseudo-ops which we support. */ 2089 const pseudo_typeS md_pseudo_table[] = 2090 { 2091 { "word", cons, 4 }, 2092 { "hword", cons, 2 }, 2093 { "align", s_d30v_align, 0 }, 2094 { "text", s_d30v_text, 0 }, 2095 { "data", s_d30v_data, 0 }, 2096 { "section", s_d30v_section, 0 }, 2097 { "section.s", s_d30v_section, 0 }, 2098 { "sect", s_d30v_section, 0 }, 2099 { "sect.s", s_d30v_section, 0 }, 2100 { NULL, NULL, 0 } 2101 }; 2102