1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V 2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007 3 Free Software Foundation, Inc. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 #include "as.h" 23 #include "safe-ctype.h" 24 #include "subsegs.h" 25 #include "opcode/d10v.h" 26 #include "elf/ppc.h" 27 28 const char comment_chars[] = ";"; 29 const char line_comment_chars[] = "#"; 30 const char line_separator_chars[] = ""; 31 const char *md_shortopts = "O"; 32 const char EXP_CHARS[] = "eE"; 33 const char FLT_CHARS[] = "dD"; 34 35 int Optimizing = 0; 36 37 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \ 38 && (X)->X_op_symbol != NULL \ 39 && symbol_constant_p ((X)->X_op_symbol) \ 40 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) 41 #define AT_WORD_RIGHT_SHIFT 2 42 43 /* Fixups. */ 44 #define MAX_INSN_FIXUPS 5 45 46 struct d10v_fixup 47 { 48 expressionS exp; 49 int operand; 50 int pcrel; 51 int size; 52 bfd_reloc_code_real_type reloc; 53 }; 54 55 typedef struct _fixups 56 { 57 int fc; 58 struct d10v_fixup fix[MAX_INSN_FIXUPS]; 59 struct _fixups *next; 60 } Fixups; 61 62 static Fixups FixUps[2]; 63 static Fixups *fixups; 64 65 static int do_not_ignore_hash = 0; 66 67 typedef int packing_type; 68 #define PACK_UNSPEC (0) /* Packing order not specified. */ 69 #define PACK_PARALLEL (1) /* "||" */ 70 #define PACK_LEFT_RIGHT (2) /* "->" */ 71 #define PACK_RIGHT_LEFT (3) /* "<-" */ 72 static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */ 73 74 /* TRUE if instruction swapping warnings should be inhibited. 75 --nowarnswap. */ 76 static bfd_boolean flag_warn_suppress_instructionswap; 77 78 /* TRUE if instruction packing should be performed when --gstabs is specified. 79 --gstabs-packing, --no-gstabs-packing. */ 80 static bfd_boolean flag_allow_gstabs_packing = 1; 81 82 /* Local functions. */ 83 84 enum options 85 { 86 OPTION_NOWARNSWAP = OPTION_MD_BASE, 87 OPTION_GSTABSPACKING, 88 OPTION_NOGSTABSPACKING 89 }; 90 91 struct option md_longopts[] = 92 { 93 {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, 94 {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING}, 95 {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING}, 96 {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING}, 97 {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING}, 98 {NULL, no_argument, NULL, 0} 99 }; 100 101 size_t md_longopts_size = sizeof (md_longopts); 102 103 /* Opcode hash table. */ 104 static struct hash_control *d10v_hash; 105 106 /* Do a binary search of the d10v_predefined_registers array to see if 107 NAME is a valid regiter name. Return the register number from the 108 array on success, or -1 on failure. */ 109 110 static int 111 reg_name_search (char *name) 112 { 113 int middle, low, high; 114 int cmp; 115 116 low = 0; 117 high = d10v_reg_name_cnt () - 1; 118 119 do 120 { 121 middle = (low + high) / 2; 122 cmp = strcasecmp (name, d10v_predefined_registers[middle].name); 123 if (cmp < 0) 124 high = middle - 1; 125 else if (cmp > 0) 126 low = middle + 1; 127 else 128 return d10v_predefined_registers[middle].value; 129 } 130 while (low <= high); 131 return -1; 132 } 133 134 /* Check the string at input_line_pointer 135 to see if it is a valid register name. */ 136 137 static int 138 register_name (expressionS *expressionP) 139 { 140 int reg_number; 141 char c, *p = input_line_pointer; 142 143 while (*p 144 && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')') 145 p++; 146 147 c = *p; 148 if (c) 149 *p++ = 0; 150 151 /* Look to see if it's in the register table. */ 152 reg_number = reg_name_search (input_line_pointer); 153 if (reg_number >= 0) 154 { 155 expressionP->X_op = O_register; 156 /* Temporarily store a pointer to the string here. */ 157 expressionP->X_op_symbol = (symbolS *) input_line_pointer; 158 expressionP->X_add_number = reg_number; 159 input_line_pointer = p; 160 return 1; 161 } 162 if (c) 163 *(p - 1) = c; 164 return 0; 165 } 166 167 static int 168 check_range (unsigned long num, int bits, int flags) 169 { 170 long min, max; 171 int retval = 0; 172 173 /* Don't bother checking 16-bit values. */ 174 if (bits == 16) 175 return 0; 176 177 if (flags & OPERAND_SHIFT) 178 { 179 /* All special shift operands are unsigned and <= 16. 180 We allow 0 for now. */ 181 if (num > 16) 182 return 1; 183 else 184 return 0; 185 } 186 187 if (flags & OPERAND_SIGNED) 188 { 189 /* Signed 3-bit integers are restricted to the (-2, 3) range. */ 190 if (flags & RESTRICTED_NUM3) 191 { 192 if ((long) num < -2 || (long) num > 3) 193 retval = 1; 194 } 195 else 196 { 197 max = (1 << (bits - 1)) - 1; 198 min = - (1 << (bits - 1)); 199 if (((long) num > max) || ((long) num < min)) 200 retval = 1; 201 } 202 } 203 else 204 { 205 max = (1 << bits) - 1; 206 min = 0; 207 if (((long) num > max) || ((long) num < min)) 208 retval = 1; 209 } 210 return retval; 211 } 212 213 void 214 md_show_usage (FILE *stream) 215 { 216 fprintf (stream, _("D10V options:\n\ 217 -O Optimize. Will do some operations in parallel.\n\ 218 --gstabs-packing Pack adjacent short instructions together even\n\ 219 when --gstabs is specified. On by default.\n\ 220 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\ 221 instructions together.\n")); 222 } 223 224 int 225 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) 226 { 227 switch (c) 228 { 229 case 'O': 230 /* Optimize. Will attempt to parallelize operations. */ 231 Optimizing = 1; 232 break; 233 case OPTION_NOWARNSWAP: 234 flag_warn_suppress_instructionswap = 1; 235 break; 236 case OPTION_GSTABSPACKING: 237 flag_allow_gstabs_packing = 1; 238 break; 239 case OPTION_NOGSTABSPACKING: 240 flag_allow_gstabs_packing = 0; 241 break; 242 default: 243 return 0; 244 } 245 return 1; 246 } 247 248 symbolS * 249 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 250 { 251 return 0; 252 } 253 254 char * 255 md_atof (int type, char *litP, int *sizeP) 256 { 257 return ieee_md_atof (type, litP, sizeP, TRUE); 258 } 259 260 void 261 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 262 asection *sec ATTRIBUTE_UNUSED, 263 fragS *fragP ATTRIBUTE_UNUSED) 264 { 265 abort (); 266 } 267 268 valueT 269 md_section_align (asection *seg, valueT addr) 270 { 271 int align = bfd_get_section_alignment (stdoutput, seg); 272 return ((addr + (1 << align) - 1) & (-1 << align)); 273 } 274 275 void 276 md_begin (void) 277 { 278 char *prev_name = ""; 279 struct d10v_opcode *opcode; 280 d10v_hash = hash_new (); 281 282 /* Insert unique names into hash table. The D10v instruction set 283 has many identical opcode names that have different opcodes based 284 on the operands. This hash table then provides a quick index to 285 the first opcode with a particular name in the opcode table. */ 286 287 for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++) 288 { 289 if (strcmp (prev_name, opcode->name)) 290 { 291 prev_name = (char *) opcode->name; 292 hash_insert (d10v_hash, opcode->name, (char *) opcode); 293 } 294 } 295 296 fixups = &FixUps[0]; 297 FixUps[0].next = &FixUps[1]; 298 FixUps[1].next = &FixUps[0]; 299 } 300 301 /* Remove the postincrement or postdecrement operator ( '+' or '-' ) 302 from an expression. */ 303 304 static int 305 postfix (char *p) 306 { 307 while (*p != '-' && *p != '+') 308 { 309 if (*p == 0 || *p == '\n' || *p == '\r') 310 break; 311 p++; 312 } 313 314 if (*p == '-') 315 { 316 *p = ' '; 317 return -1; 318 } 319 if (*p == '+') 320 { 321 *p = ' '; 322 return 1; 323 } 324 325 return 0; 326 } 327 328 static bfd_reloc_code_real_type 329 get_reloc (struct d10v_operand *op) 330 { 331 int bits = op->bits; 332 333 if (bits <= 4) 334 return 0; 335 336 if (op->flags & OPERAND_ADDR) 337 { 338 if (bits == 8) 339 return BFD_RELOC_D10V_10_PCREL_R; 340 else 341 return BFD_RELOC_D10V_18_PCREL; 342 } 343 344 return BFD_RELOC_16; 345 } 346 347 /* Parse a string of operands. Return an array of expressions. */ 348 349 static int 350 get_operands (expressionS exp[]) 351 { 352 char *p = input_line_pointer; 353 int numops = 0; 354 int post = 0; 355 int uses_at = 0; 356 357 while (*p) 358 { 359 while (*p == ' ' || *p == '\t' || *p == ',') 360 p++; 361 if (*p == 0 || *p == '\n' || *p == '\r') 362 break; 363 364 if (*p == '@') 365 { 366 uses_at = 1; 367 368 p++; 369 exp[numops].X_op = O_absent; 370 if (*p == '(') 371 { 372 p++; 373 exp[numops].X_add_number = OPERAND_ATPAR; 374 } 375 else if (*p == '-') 376 { 377 p++; 378 exp[numops].X_add_number = OPERAND_ATMINUS; 379 } 380 else 381 { 382 exp[numops].X_add_number = OPERAND_ATSIGN; 383 if (*p == '+') 384 { 385 numops++; 386 exp[numops].X_op = O_absent; 387 exp[numops].X_add_number = OPERAND_PLUS; 388 p++; 389 } 390 post = postfix (p); 391 } 392 numops++; 393 continue; 394 } 395 396 if (*p == ')') 397 { 398 /* Just skip the trailing paren. */ 399 p++; 400 continue; 401 } 402 403 input_line_pointer = p; 404 405 /* Check to see if it might be a register name. */ 406 if (!register_name (&exp[numops])) 407 { 408 /* Parse as an expression. */ 409 if (uses_at) 410 { 411 /* Any expression that involves the indirect addressing 412 cannot also involve immediate addressing. Therefore 413 the use of the hash character is illegal. */ 414 int save = do_not_ignore_hash; 415 do_not_ignore_hash = 1; 416 417 expression (&exp[numops]); 418 419 do_not_ignore_hash = save; 420 } 421 else 422 expression (&exp[numops]); 423 } 424 425 if (strncasecmp (input_line_pointer, "@word", 5) == 0) 426 { 427 input_line_pointer += 5; 428 if (exp[numops].X_op == O_register) 429 { 430 /* If it looked like a register name but was followed by 431 "@word" then it was really a symbol, so change it to 432 one. */ 433 exp[numops].X_op = O_symbol; 434 exp[numops].X_add_symbol = 435 symbol_find_or_make ((char *) exp[numops].X_op_symbol); 436 } 437 438 /* Check for identifier@word+constant. */ 439 if (*input_line_pointer == '-' || *input_line_pointer == '+') 440 { 441 expressionS new_exp; 442 expression (&new_exp); 443 exp[numops].X_add_number = new_exp.X_add_number; 444 } 445 446 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */ 447 { 448 expressionS new_exp; 449 memset (&new_exp, 0, sizeof new_exp); 450 new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; 451 new_exp.X_op = O_constant; 452 new_exp.X_unsigned = 1; 453 exp[numops].X_op_symbol = make_expr_symbol (&new_exp); 454 exp[numops].X_op = O_right_shift; 455 } 456 457 know (AT_WORD_P (&exp[numops])); 458 } 459 460 if (exp[numops].X_op == O_illegal) 461 as_bad (_("illegal operand")); 462 else if (exp[numops].X_op == O_absent) 463 as_bad (_("missing operand")); 464 465 numops++; 466 p = input_line_pointer; 467 } 468 469 switch (post) 470 { 471 case -1: /* Postdecrement mode. */ 472 exp[numops].X_op = O_absent; 473 exp[numops++].X_add_number = OPERAND_MINUS; 474 break; 475 case 1: /* Postincrement mode. */ 476 exp[numops].X_op = O_absent; 477 exp[numops++].X_add_number = OPERAND_PLUS; 478 break; 479 } 480 481 exp[numops].X_op = 0; 482 return numops; 483 } 484 485 static unsigned long 486 d10v_insert_operand (unsigned long insn, 487 int op_type, 488 offsetT value, 489 int left, 490 fixS *fix) 491 { 492 int shift, bits; 493 494 shift = d10v_operands[op_type].shift; 495 if (left) 496 shift += 15; 497 498 bits = d10v_operands[op_type].bits; 499 500 /* Truncate to the proper number of bits. */ 501 if (check_range (value, bits, d10v_operands[op_type].flags)) 502 as_bad_where (fix->fx_file, fix->fx_line, 503 _("operand out of range: %ld"), (long) value); 504 505 value &= 0x7FFFFFFF >> (31 - bits); 506 insn |= (value << shift); 507 508 return insn; 509 } 510 511 /* Take a pointer to the opcode entry in the opcode table and the 512 array of operand expressions. Return the instruction. */ 513 514 static unsigned long 515 build_insn (struct d10v_opcode *opcode, 516 expressionS *opers, 517 unsigned long insn) 518 { 519 int i, bits, shift, flags, format; 520 unsigned long number; 521 522 /* The insn argument is only used for the DIVS kludge. */ 523 if (insn) 524 format = LONG_R; 525 else 526 { 527 insn = opcode->opcode; 528 format = opcode->format; 529 } 530 531 for (i = 0; opcode->operands[i]; i++) 532 { 533 flags = d10v_operands[opcode->operands[i]].flags; 534 bits = d10v_operands[opcode->operands[i]].bits; 535 shift = d10v_operands[opcode->operands[i]].shift; 536 number = opers[i].X_add_number; 537 538 if (flags & OPERAND_REG) 539 { 540 number &= REGISTER_MASK; 541 if (format == LONG_L) 542 shift += 15; 543 } 544 545 if (opers[i].X_op != O_register && opers[i].X_op != O_constant) 546 { 547 /* Now create a fixup. */ 548 549 if (fixups->fc >= MAX_INSN_FIXUPS) 550 as_fatal (_("too many fixups")); 551 552 if (AT_WORD_P (&opers[i])) 553 { 554 /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */ 555 fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; 556 opers[i].X_op = O_symbol; 557 opers[i].X_op_symbol = NULL; /* Should free it. */ 558 /* number is left shifted by AT_WORD_RIGHT_SHIFT so 559 that, it is aligned with the symbol's value. Later, 560 BFD_RELOC_D10V_18 will right shift (symbol_value + 561 X_add_number). */ 562 number <<= AT_WORD_RIGHT_SHIFT; 563 opers[i].X_add_number = number; 564 } 565 else 566 { 567 fixups->fix[fixups->fc].reloc = 568 get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]); 569 570 /* Check that an immediate was passed to ops that expect one. */ 571 if ((flags & OPERAND_NUM) 572 && (fixups->fix[fixups->fc].reloc == 0)) 573 as_bad (_("operand is not an immediate")); 574 } 575 576 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || 577 fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) 578 fixups->fix[fixups->fc].size = 2; 579 else 580 fixups->fix[fixups->fc].size = 4; 581 582 fixups->fix[fixups->fc].exp = opers[i]; 583 fixups->fix[fixups->fc].operand = opcode->operands[i]; 584 fixups->fix[fixups->fc].pcrel = 585 (flags & OPERAND_ADDR) ? TRUE : FALSE; 586 (fixups->fc)++; 587 } 588 589 /* Truncate to the proper number of bits. */ 590 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) 591 as_bad (_("operand out of range: %lu"), number); 592 number &= 0x7FFFFFFF >> (31 - bits); 593 insn = insn | (number << shift); 594 } 595 596 /* kludge: for DIVS, we need to put the operands in twice on the second 597 pass, format is changed to LONG_R to force the second set of operands 598 to not be shifted over 15. */ 599 if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L)) 600 insn = build_insn (opcode, opers, insn); 601 602 return insn; 603 } 604 605 /* Write out a long form instruction. */ 606 607 static void 608 write_long (unsigned long insn, Fixups *fx) 609 { 610 int i, where; 611 char *f = frag_more (4); 612 613 insn |= FM11; 614 number_to_chars_bigendian (f, insn, 4); 615 616 for (i = 0; i < fx->fc; i++) 617 { 618 if (fx->fix[i].reloc) 619 { 620 where = f - frag_now->fr_literal; 621 if (fx->fix[i].size == 2) 622 where += 2; 623 624 if (fx->fix[i].reloc == BFD_RELOC_D10V_18) 625 fx->fix[i].operand |= 4096; 626 627 fix_new_exp (frag_now, 628 where, 629 fx->fix[i].size, 630 &(fx->fix[i].exp), 631 fx->fix[i].pcrel, 632 fx->fix[i].operand|2048); 633 } 634 } 635 fx->fc = 0; 636 } 637 638 /* Write out a short form instruction by itself. */ 639 640 static void 641 write_1_short (struct d10v_opcode *opcode, 642 unsigned long insn, 643 Fixups *fx) 644 { 645 char *f = frag_more (4); 646 int i, where; 647 648 if (opcode->exec_type & PARONLY) 649 as_fatal (_("Instruction must be executed in parallel with another instruction.")); 650 651 /* The other container needs to be NOP. 652 According to 4.3.1: for FM=00, sub-instructions performed only by IU 653 cannot be encoded in L-container. */ 654 if (opcode->unit == IU) 655 insn |= FM00 | (NOP << 15); /* Right container. */ 656 else 657 insn = FM00 | (insn << 15) | NOP; /* Left container. */ 658 659 number_to_chars_bigendian (f, insn, 4); 660 for (i = 0; i < fx->fc; i++) 661 { 662 if (fx->fix[i].reloc) 663 { 664 where = f - frag_now->fr_literal; 665 if (fx->fix[i].size == 2) 666 where += 2; 667 668 if (fx->fix[i].reloc == BFD_RELOC_D10V_18) 669 fx->fix[i].operand |= 4096; 670 671 /* If it's an R reloc, we may have to switch it to L. */ 672 if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) 673 && (opcode->unit != IU)) 674 fx->fix[i].operand |= 1024; 675 676 fix_new_exp (frag_now, 677 where, 678 fx->fix[i].size, 679 &(fx->fix[i].exp), 680 fx->fix[i].pcrel, 681 fx->fix[i].operand|2048); 682 } 683 } 684 fx->fc = 0; 685 } 686 687 /* Determine if there are any resource conflicts among two manually 688 parallelized instructions. Some of this was lifted from parallel_ok. */ 689 690 static void 691 check_resource_conflict (struct d10v_opcode *op1, 692 unsigned long insn1, 693 struct d10v_opcode *op2, 694 unsigned long insn2) 695 { 696 int i, j, flags, mask, shift, regno; 697 unsigned long ins, mod[2]; 698 struct d10v_opcode *op; 699 700 if ((op1->exec_type & SEQ) 701 || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY))) 702 { 703 as_warn (_("packing conflict: %s must dispatch sequentially"), 704 op1->name); 705 return; 706 } 707 708 if ((op2->exec_type & SEQ) 709 || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY))) 710 { 711 as_warn (_("packing conflict: %s must dispatch sequentially"), 712 op2->name); 713 return; 714 } 715 716 /* See if both instructions write to the same resource. 717 718 The idea here is to create two sets of bitmasks (mod and used) which 719 indicate which registers are modified or used by each instruction. 720 The operation can only be done in parallel if neither instruction 721 modifies the same register. Accesses to control registers and memory 722 are treated as accesses to a single register. So if both instructions 723 write memory or if the first instruction writes memory and the second 724 reads, then they cannot be done in parallel. We treat reads to the PSW 725 (which includes C, F0, and F1) in isolation. So simultaneously writing 726 C and F0 in two different sub-instructions is permitted. */ 727 728 /* The bitmasks (mod and used) look like this (bit 31 = MSB). 729 r0-r15 0-15 730 a0-a1 16-17 731 cr (not psw) 18 732 psw(other) 19 733 mem 20 734 psw(C flag) 21 735 psw(F0 flag) 22 */ 736 737 for (j = 0; j < 2; j++) 738 { 739 if (j == 0) 740 { 741 op = op1; 742 ins = insn1; 743 } 744 else 745 { 746 op = op2; 747 ins = insn2; 748 } 749 mod[j] = 0; 750 if (op->exec_type & BRANCH_LINK) 751 mod[j] |= 1 << 13; 752 753 for (i = 0; op->operands[i]; i++) 754 { 755 flags = d10v_operands[op->operands[i]].flags; 756 shift = d10v_operands[op->operands[i]].shift; 757 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); 758 if (flags & OPERAND_REG) 759 { 760 regno = (ins >> shift) & mask; 761 if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) 762 regno += 16; 763 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ 764 { 765 if (regno == 0) 766 regno = 19; 767 else 768 regno = 18; 769 } 770 else if (flags & OPERAND_FFLAG) 771 regno = 22; 772 else if (flags & OPERAND_CFLAG) 773 regno = 21; 774 775 if (flags & OPERAND_DEST 776 /* Auto inc/dec also modifies the register. */ 777 || (op->operands[i + 1] != 0 778 && (d10v_operands[op->operands[i + 1]].flags 779 & (OPERAND_PLUS | OPERAND_MINUS)) != 0)) 780 { 781 mod[j] |= 1 << regno; 782 if (flags & OPERAND_EVEN) 783 mod[j] |= 1 << (regno + 1); 784 } 785 } 786 else if (flags & OPERAND_ATMINUS) 787 { 788 /* SP implicitly used/modified. */ 789 mod[j] |= 1 << 15; 790 } 791 } 792 793 if (op->exec_type & WMEM) 794 mod[j] |= 1 << 20; 795 else if (op->exec_type & WF0) 796 mod[j] |= 1 << 22; 797 else if (op->exec_type & WCAR) 798 mod[j] |= 1 << 21; 799 } 800 801 if ((mod[0] & mod[1]) == 0) 802 return; 803 else 804 { 805 unsigned long x; 806 x = mod[0] & mod[1]; 807 808 for (j = 0; j <= 15; j++) 809 if (x & (1 << j)) 810 as_warn (_("resource conflict (R%d)"), j); 811 for (j = 16; j <= 17; j++) 812 if (x & (1 << j)) 813 as_warn (_("resource conflict (A%d)"), j - 16); 814 if (x & (1 << 19)) 815 as_warn (_("resource conflict (PSW)")); 816 if (x & (1 << 21)) 817 as_warn (_("resource conflict (C flag)")); 818 if (x & (1 << 22)) 819 as_warn (_("resource conflict (F flag)")); 820 } 821 } 822 823 /* Check 2 instructions and determine if they can be safely 824 executed in parallel. Return 1 if they can be. */ 825 826 static int 827 parallel_ok (struct d10v_opcode *op1, 828 unsigned long insn1, 829 struct d10v_opcode *op2, 830 unsigned long insn2, 831 packing_type exec_type) 832 { 833 int i, j, flags, mask, shift, regno; 834 unsigned long ins, mod[2], used[2]; 835 struct d10v_opcode *op; 836 837 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0 838 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0 839 || (op1->unit == BOTH) || (op2->unit == BOTH) 840 || (op1->unit == IU && op2->unit == IU) 841 || (op1->unit == MU && op2->unit == MU)) 842 return 0; 843 844 /* If this is auto parallelization, and the first instruction is a 845 branch or should not be packed, then don't parallelize. */ 846 if (exec_type == PACK_UNSPEC 847 && (op1->exec_type & (ALONE | BRANCH))) 848 return 0; 849 850 /* The idea here is to create two sets of bitmasks (mod and used) 851 which indicate which registers are modified or used by each 852 instruction. The operation can only be done in parallel if 853 instruction 1 and instruction 2 modify different registers, and 854 the first instruction does not modify registers that the second 855 is using (The second instruction can modify registers that the 856 first is using as they are only written back after the first 857 instruction has completed). Accesses to control registers, PSW, 858 and memory are treated as accesses to a single register. So if 859 both instructions write memory or if the first instruction writes 860 memory and the second reads, then they cannot be done in 861 parallel. Likewise, if the first instruction mucks with the psw 862 and the second reads the PSW (which includes C, F0, and F1), then 863 they cannot operate safely in parallel. */ 864 865 /* The bitmasks (mod and used) look like this (bit 31 = MSB). 866 r0-r15 0-15 867 a0-a1 16-17 868 cr (not psw) 18 869 psw 19 870 mem 20 */ 871 872 for (j = 0; j < 2; j++) 873 { 874 if (j == 0) 875 { 876 op = op1; 877 ins = insn1; 878 } 879 else 880 { 881 op = op2; 882 ins = insn2; 883 } 884 mod[j] = used[j] = 0; 885 if (op->exec_type & BRANCH_LINK) 886 mod[j] |= 1 << 13; 887 888 for (i = 0; op->operands[i]; i++) 889 { 890 flags = d10v_operands[op->operands[i]].flags; 891 shift = d10v_operands[op->operands[i]].shift; 892 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits); 893 if (flags & OPERAND_REG) 894 { 895 regno = (ins >> shift) & mask; 896 if (flags & (OPERAND_ACC0 | OPERAND_ACC1)) 897 regno += 16; 898 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */ 899 { 900 if (regno == 0) 901 regno = 19; 902 else 903 regno = 18; 904 } 905 else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG)) 906 regno = 19; 907 908 if (flags & OPERAND_DEST) 909 { 910 mod[j] |= 1 << regno; 911 if (flags & OPERAND_EVEN) 912 mod[j] |= 1 << (regno + 1); 913 } 914 else 915 { 916 used[j] |= 1 << regno; 917 if (flags & OPERAND_EVEN) 918 used[j] |= 1 << (regno + 1); 919 920 /* Auto inc/dec also modifies the register. */ 921 if (op->operands[i + 1] != 0 922 && (d10v_operands[op->operands[i + 1]].flags 923 & (OPERAND_PLUS | OPERAND_MINUS)) != 0) 924 mod[j] |= 1 << regno; 925 } 926 } 927 else if (flags & OPERAND_ATMINUS) 928 { 929 /* SP implicitly used/modified. */ 930 mod[j] |= 1 << 15; 931 used[j] |= 1 << 15; 932 } 933 } 934 if (op->exec_type & RMEM) 935 used[j] |= 1 << 20; 936 else if (op->exec_type & WMEM) 937 mod[j] |= 1 << 20; 938 else if (op->exec_type & RF0) 939 used[j] |= 1 << 19; 940 else if (op->exec_type & WF0) 941 mod[j] |= 1 << 19; 942 else if (op->exec_type & WCAR) 943 mod[j] |= 1 << 19; 944 } 945 if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) 946 return 1; 947 return 0; 948 } 949 950 /* Expects two short instructions. 951 If possible, writes out both as a single packed instruction. 952 Otherwise, writes out the first one, packed with a NOP. 953 Returns number of instructions not written out. */ 954 955 static int 956 write_2_short (struct d10v_opcode *opcode1, 957 unsigned long insn1, 958 struct d10v_opcode *opcode2, 959 unsigned long insn2, 960 packing_type exec_type, 961 Fixups *fx) 962 { 963 unsigned long insn; 964 char *f; 965 int i, j, where; 966 967 if ((exec_type != PACK_PARALLEL) 968 && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY))) 969 as_fatal (_("Instruction must be executed in parallel")); 970 971 if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) 972 as_fatal (_("Long instructions may not be combined.")); 973 974 switch (exec_type) 975 { 976 case PACK_UNSPEC: /* Order not specified. */ 977 if (opcode1->exec_type & ALONE) 978 { 979 /* Case of a short branch on a separate GAS line. Pack with NOP. */ 980 write_1_short (opcode1, insn1, fx->next); 981 return 1; 982 } 983 if (Optimizing 984 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) 985 { 986 /* Parallel. */ 987 if (opcode1->unit == IU) 988 insn = FM00 | (insn2 << 15) | insn1; 989 else if (opcode2->unit == MU) 990 insn = FM00 | (insn2 << 15) | insn1; 991 else 992 insn = FM00 | (insn1 << 15) | insn2; 993 } 994 else if (opcode1->unit == IU) 995 /* Reverse sequential with IU opcode1 on right and done first. */ 996 insn = FM10 | (insn2 << 15) | insn1; 997 else 998 /* Sequential with non-IU opcode1 on left and done first. */ 999 insn = FM01 | (insn1 << 15) | insn2; 1000 break; 1001 1002 case PACK_PARALLEL: 1003 if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) 1004 as_fatal 1005 (_("One of these instructions may not be executed in parallel.")); 1006 if (opcode1->unit == IU) 1007 { 1008 if (opcode2->unit == IU) 1009 as_fatal (_("Two IU instructions may not be executed in parallel")); 1010 if (!flag_warn_suppress_instructionswap) 1011 as_warn (_("Swapping instruction order")); 1012 insn = FM00 | (insn2 << 15) | insn1; 1013 } 1014 else if (opcode2->unit == MU) 1015 { 1016 if (opcode1->unit == MU) 1017 as_fatal (_("Two MU instructions may not be executed in parallel")); 1018 if (!flag_warn_suppress_instructionswap) 1019 as_warn (_("Swapping instruction order")); 1020 insn = FM00 | (insn2 << 15) | insn1; 1021 } 1022 else 1023 insn = FM00 | (insn1 << 15) | insn2; 1024 check_resource_conflict (opcode1, insn1, opcode2, insn2); 1025 break; 1026 1027 case PACK_LEFT_RIGHT: 1028 if (opcode1->unit != IU) 1029 insn = FM01 | (insn1 << 15) | insn2; 1030 else if (opcode2->unit == MU || opcode2->unit == EITHER) 1031 { 1032 if (!flag_warn_suppress_instructionswap) 1033 as_warn (_("Swapping instruction order")); 1034 insn = FM10 | (insn2 << 15) | insn1; 1035 } 1036 else 1037 as_fatal (_("IU instruction may not be in the left container")); 1038 if (opcode1->exec_type & ALONE) 1039 as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); 1040 break; 1041 1042 case PACK_RIGHT_LEFT: 1043 if (opcode2->unit != MU) 1044 insn = FM10 | (insn1 << 15) | insn2; 1045 else if (opcode1->unit == IU || opcode1->unit == EITHER) 1046 { 1047 if (!flag_warn_suppress_instructionswap) 1048 as_warn (_("Swapping instruction order")); 1049 insn = FM01 | (insn2 << 15) | insn1; 1050 } 1051 else 1052 as_fatal (_("MU instruction may not be in the right container")); 1053 if (opcode2->exec_type & ALONE) 1054 as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); 1055 break; 1056 1057 default: 1058 as_fatal (_("unknown execution type passed to write_2_short()")); 1059 } 1060 1061 f = frag_more (4); 1062 number_to_chars_bigendian (f, insn, 4); 1063 1064 /* Process fixup chains. fx refers to insn2 when j == 0, and to 1065 insn1 when j == 1. Yes, it's reversed. */ 1066 1067 for (j = 0; j < 2; j++) 1068 { 1069 for (i = 0; i < fx->fc; i++) 1070 { 1071 if (fx->fix[i].reloc) 1072 { 1073 where = f - frag_now->fr_literal; 1074 if (fx->fix[i].size == 2) 1075 where += 2; 1076 1077 if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R 1078 /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to 1079 the instruction in the L container has to be 1080 adjusted to BDF_RELOC_D10V_10_PCREL_L. When 1081 j==0, we're processing insn2's operands, so we 1082 want to mark the operand if insn2 is *not* in the 1083 R container. When j==1, we're processing insn1's 1084 operands, so we want to mark the operand if insn2 1085 *is* in the R container. Note that, if two 1086 instructions are identical, we're never going to 1087 swap them, so the test is safe. */ 1088 && j == ((insn & 0x7fff) == insn2)) 1089 fx->fix[i].operand |= 1024; 1090 1091 if (fx->fix[i].reloc == BFD_RELOC_D10V_18) 1092 fx->fix[i].operand |= 4096; 1093 1094 fix_new_exp (frag_now, 1095 where, 1096 fx->fix[i].size, 1097 &(fx->fix[i].exp), 1098 fx->fix[i].pcrel, 1099 fx->fix[i].operand|2048); 1100 } 1101 } 1102 fx->fc = 0; 1103 fx = fx->next; 1104 } 1105 return 0; 1106 } 1107 1108 /* This is the main entry point for the machine-dependent assembler. 1109 str points to a machine-dependent instruction. This function is 1110 supposed to emit the frags/bytes it assembles to. For the D10V, it 1111 mostly handles the special VLIW parsing and packing and leaves the 1112 difficult stuff to do_assemble(). */ 1113 1114 static unsigned long prev_insn; 1115 static struct d10v_opcode *prev_opcode = 0; 1116 static subsegT prev_subseg; 1117 static segT prev_seg = 0;; 1118 1119 /* Find the symbol which has the same name as the register in exp. */ 1120 1121 static symbolS * 1122 find_symbol_matching_register (expressionS *exp) 1123 { 1124 int i; 1125 1126 if (exp->X_op != O_register) 1127 return NULL; 1128 1129 /* Find the name of the register. */ 1130 for (i = d10v_reg_name_cnt (); i--;) 1131 if (d10v_predefined_registers[i].value == exp->X_add_number) 1132 break; 1133 1134 if (i < 0) 1135 abort (); 1136 1137 /* Now see if a symbol has been defined with the same name. */ 1138 return symbol_find (d10v_predefined_registers[i].name); 1139 } 1140 1141 /* Get a pointer to an entry in the opcode table. 1142 The function must look at all opcodes with the same name and use 1143 the operands to choose the correct opcode. */ 1144 1145 static struct d10v_opcode * 1146 find_opcode (struct d10v_opcode *opcode, expressionS myops[]) 1147 { 1148 int i, match; 1149 struct d10v_opcode *next_opcode; 1150 1151 /* Get all the operands and save them as expressions. */ 1152 get_operands (myops); 1153 1154 /* Now see if the operand is a fake. If so, find the correct size 1155 instruction, if possible. */ 1156 if (opcode->format == OPCODE_FAKE) 1157 { 1158 int opnum = opcode->operands[0]; 1159 int flags; 1160 1161 if (myops[opnum].X_op == O_register) 1162 { 1163 myops[opnum].X_op = O_symbol; 1164 myops[opnum].X_add_symbol = 1165 symbol_find_or_make ((char *) myops[opnum].X_op_symbol); 1166 myops[opnum].X_add_number = 0; 1167 myops[opnum].X_op_symbol = NULL; 1168 } 1169 1170 next_opcode = opcode + 1; 1171 1172 /* If the first operand is supposed to be a register, make sure 1173 we got a valid one. */ 1174 flags = d10v_operands[next_opcode->operands[0]].flags; 1175 if (flags & OPERAND_REG) 1176 { 1177 int X_op = myops[0].X_op; 1178 int num = myops[0].X_add_number; 1179 1180 if (X_op != O_register 1181 || (num & ~flags 1182 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 1183 | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)) 1184 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) 1185 { 1186 as_bad (_("bad opcode or operands")); 1187 return 0; 1188 } 1189 } 1190 1191 if (myops[opnum].X_op == O_constant 1192 || (myops[opnum].X_op == O_symbol 1193 && S_IS_DEFINED (myops[opnum].X_add_symbol) 1194 && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg))) 1195 { 1196 for (i = 0; opcode->operands[i + 1]; i++) 1197 { 1198 int bits = d10v_operands[next_opcode->operands[opnum]].bits; 1199 int flags = d10v_operands[next_opcode->operands[opnum]].flags; 1200 if (flags & OPERAND_ADDR) 1201 bits += 2; 1202 1203 if (myops[opnum].X_op == O_constant) 1204 { 1205 if (!check_range (myops[opnum].X_add_number, bits, flags)) 1206 break; 1207 } 1208 else 1209 { 1210 fragS *sym_frag; 1211 fragS *f; 1212 unsigned long current_position; 1213 unsigned long symbol_position; 1214 unsigned long value; 1215 bfd_boolean found_symbol; 1216 1217 /* Calculate the address of the current instruction 1218 and the address of the symbol. Do this by summing 1219 the offsets of previous frags until we reach the 1220 frag containing the symbol, and the current frag. */ 1221 sym_frag = symbol_get_frag (myops[opnum].X_add_symbol); 1222 found_symbol = FALSE; 1223 1224 current_position = 1225 obstack_next_free (&frchain_now->frch_obstack) 1226 - frag_now->fr_literal; 1227 symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol); 1228 1229 for (f = frchain_now->frch_root; f; f = f->fr_next) 1230 { 1231 current_position += f->fr_fix + f->fr_offset; 1232 1233 if (f == sym_frag) 1234 found_symbol = TRUE; 1235 1236 if (! found_symbol) 1237 symbol_position += f->fr_fix + f->fr_offset; 1238 } 1239 1240 value = symbol_position; 1241 1242 if (flags & OPERAND_ADDR) 1243 value -= current_position; 1244 1245 if (AT_WORD_P (&myops[opnum])) 1246 { 1247 if (bits > 4) 1248 { 1249 bits += 2; 1250 if (!check_range (value, bits, flags)) 1251 break; 1252 } 1253 } 1254 else if (!check_range (value, bits, flags)) 1255 break; 1256 } 1257 next_opcode++; 1258 } 1259 1260 if (opcode->operands [i + 1] == 0) 1261 as_fatal (_("value out of range")); 1262 else 1263 opcode = next_opcode; 1264 } 1265 else 1266 /* Not a constant, so use a long instruction. */ 1267 opcode += 2; 1268 } 1269 1270 match = 0; 1271 1272 /* Now search the opcode table table for one with operands 1273 that matches what we've got. */ 1274 while (!match) 1275 { 1276 match = 1; 1277 for (i = 0; opcode->operands[i]; i++) 1278 { 1279 int flags = d10v_operands[opcode->operands[i]].flags; 1280 int X_op = myops[i].X_op; 1281 int num = myops[i].X_add_number; 1282 1283 if (X_op == 0) 1284 { 1285 match = 0; 1286 break; 1287 } 1288 1289 if (flags & OPERAND_REG) 1290 { 1291 if ((X_op != O_register) 1292 || (num & ~flags 1293 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 1294 | OPERAND_FFLAG | OPERAND_CFLAG 1295 | OPERAND_CONTROL)) 1296 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP))) 1297 { 1298 match = 0; 1299 break; 1300 } 1301 } 1302 1303 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || 1304 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || 1305 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || 1306 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || 1307 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR))))) 1308 { 1309 match = 0; 1310 break; 1311 } 1312 1313 /* Unfortunately, for the indirect operand in instructions such 1314 as ``ldb r1, @(c,r14)'' this function can be passed 1315 X_op == O_register (because 'c' is a valid register name). 1316 However we cannot just ignore the case when X_op == O_register 1317 but flags & OPERAND_REG is null, so we check to see if a symbol 1318 of the same name as the register exists. If the symbol does 1319 exist, then the parser was unable to distinguish the two cases 1320 and we fix things here. (Ref: PR14826) */ 1321 1322 if (!(flags & OPERAND_REG) && (X_op == O_register)) 1323 { 1324 symbolS * sym; 1325 1326 sym = find_symbol_matching_register (& myops[i]); 1327 1328 if (sym != NULL) 1329 { 1330 myops[i].X_op = X_op = O_symbol; 1331 myops[i].X_add_symbol = sym; 1332 } 1333 else 1334 as_bad 1335 (_("illegal operand - register name found where none expected")); 1336 } 1337 } 1338 1339 /* We're only done if the operands matched so far AND there 1340 are no more to check. */ 1341 if (match && myops[i].X_op == 0) 1342 break; 1343 else 1344 match = 0; 1345 1346 next_opcode = opcode + 1; 1347 1348 if (next_opcode->opcode == 0) 1349 break; 1350 1351 if (strcmp (next_opcode->name, opcode->name)) 1352 break; 1353 1354 opcode = next_opcode; 1355 } 1356 1357 if (!match) 1358 { 1359 as_bad (_("bad opcode or operands")); 1360 return 0; 1361 } 1362 1363 /* Check that all registers that are required to be even are. 1364 Also, if any operands were marked as registers, but were really symbols, 1365 fix that here. */ 1366 for (i = 0; opcode->operands[i]; i++) 1367 { 1368 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && 1369 (myops[i].X_add_number & 1)) 1370 as_fatal (_("Register number must be EVEN")); 1371 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP) 1372 && (myops[i].X_add_number & OPERAND_SP)) 1373 as_bad (_("Unsupported use of sp")); 1374 if (myops[i].X_op == O_register) 1375 { 1376 if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) 1377 { 1378 myops[i].X_op = O_symbol; 1379 myops[i].X_add_symbol = 1380 symbol_find_or_make ((char *) myops[i].X_op_symbol); 1381 myops[i].X_add_number = 0; 1382 myops[i].X_op_symbol = NULL; 1383 } 1384 } 1385 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL) 1386 && (myops[i].X_add_number == OPERAND_CONTROL + 4 1387 || myops[i].X_add_number == OPERAND_CONTROL + 5 1388 || myops[i].X_add_number == OPERAND_CONTROL + 6 1389 || myops[i].X_add_number == OPERAND_CONTROL + 12 1390 || myops[i].X_add_number == OPERAND_CONTROL + 13 1391 || myops[i].X_add_number == OPERAND_CONTROL + 15)) 1392 as_warn (_("cr%ld is a reserved control register"), 1393 myops[i].X_add_number - OPERAND_CONTROL); 1394 } 1395 return opcode; 1396 } 1397 1398 /* Assemble a single instruction. 1399 Return an opcode, or -1 (an invalid opcode) on error. */ 1400 1401 static unsigned long 1402 do_assemble (char *str, struct d10v_opcode **opcode) 1403 { 1404 unsigned char *op_start, *op_end; 1405 char *save; 1406 char name[20]; 1407 int nlen = 0; 1408 expressionS myops[6]; 1409 1410 /* Drop leading whitespace. */ 1411 while (*str == ' ') 1412 str++; 1413 1414 /* Find the opcode end. */ 1415 for (op_start = op_end = (unsigned char *) str; 1416 *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' '; 1417 op_end++) 1418 { 1419 name[nlen] = TOLOWER (op_start[nlen]); 1420 nlen++; 1421 } 1422 name[nlen] = 0; 1423 1424 if (nlen == 0) 1425 return -1; 1426 1427 /* Find the first opcode with the proper name. */ 1428 *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name); 1429 if (*opcode == NULL) 1430 return -1; 1431 1432 save = input_line_pointer; 1433 input_line_pointer = (char *) op_end; 1434 *opcode = find_opcode (*opcode, myops); 1435 if (*opcode == 0) 1436 return -1; 1437 input_line_pointer = save; 1438 1439 return build_insn ((*opcode), myops, 0); 1440 } 1441 1442 /* If while processing a fixup, a reloc really needs to be created. 1443 Then it is done here. */ 1444 1445 arelent * 1446 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) 1447 { 1448 arelent *reloc; 1449 reloc = xmalloc (sizeof (arelent)); 1450 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 1451 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1452 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1453 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 1454 if (reloc->howto == (reloc_howto_type *) NULL) 1455 { 1456 as_bad_where (fixp->fx_file, fixp->fx_line, 1457 _("reloc %d not supported by object file format"), 1458 (int) fixp->fx_r_type); 1459 return NULL; 1460 } 1461 1462 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1463 reloc->address = fixp->fx_offset; 1464 1465 reloc->addend = 0; 1466 1467 return reloc; 1468 } 1469 1470 int 1471 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, 1472 asection *seg ATTRIBUTE_UNUSED) 1473 { 1474 abort (); 1475 return 0; 1476 } 1477 1478 long 1479 md_pcrel_from_section (fixS *fixp, segT sec) 1480 { 1481 if (fixp->fx_addsy != (symbolS *) NULL 1482 && (!S_IS_DEFINED (fixp->fx_addsy) 1483 || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) 1484 return 0; 1485 return fixp->fx_frag->fr_address + fixp->fx_where; 1486 } 1487 1488 void 1489 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 1490 { 1491 char *where; 1492 unsigned long insn; 1493 long value = *valP; 1494 int op_type; 1495 int left = 0; 1496 1497 if (fixP->fx_addsy == (symbolS *) NULL) 1498 fixP->fx_done = 1; 1499 1500 /* We don't actually support subtracting a symbol. */ 1501 if (fixP->fx_subsy != (symbolS *) NULL) 1502 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); 1503 1504 op_type = fixP->fx_r_type; 1505 if (op_type & 2048) 1506 { 1507 op_type -= 2048; 1508 if (op_type & 1024) 1509 { 1510 op_type -= 1024; 1511 fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L; 1512 left = 1; 1513 } 1514 else if (op_type & 4096) 1515 { 1516 op_type -= 4096; 1517 fixP->fx_r_type = BFD_RELOC_D10V_18; 1518 } 1519 else 1520 fixP->fx_r_type = 1521 get_reloc ((struct d10v_operand *) &d10v_operands[op_type]); 1522 } 1523 1524 /* Fetch the instruction, insert the fully resolved operand 1525 value, and stuff the instruction back again. */ 1526 where = fixP->fx_frag->fr_literal + fixP->fx_where; 1527 insn = bfd_getb32 ((unsigned char *) where); 1528 1529 switch (fixP->fx_r_type) 1530 { 1531 case BFD_RELOC_D10V_10_PCREL_L: 1532 case BFD_RELOC_D10V_10_PCREL_R: 1533 case BFD_RELOC_D10V_18_PCREL: 1534 /* If the fix is relative to a global symbol, not a section 1535 symbol, then ignore the offset. 1536 XXX - Do we have to worry about branches to a symbol + offset ? */ 1537 if (fixP->fx_addsy != NULL 1538 && S_IS_EXTERNAL (fixP->fx_addsy) ) 1539 { 1540 segT fseg = S_GET_SEGMENT (fixP->fx_addsy); 1541 segment_info_type *segf = seg_info(fseg); 1542 1543 if ( segf && segf->sym != fixP->fx_addsy) 1544 value = 0; 1545 } 1546 /* Drop through. */ 1547 case BFD_RELOC_D10V_18: 1548 /* Instruction addresses are always right-shifted by 2. */ 1549 value >>= AT_WORD_RIGHT_SHIFT; 1550 if (fixP->fx_size == 2) 1551 bfd_putb16 ((bfd_vma) value, (unsigned char *) where); 1552 else 1553 { 1554 struct d10v_opcode *rep, *repi; 1555 1556 rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); 1557 repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); 1558 if ((insn & FM11) == FM11 1559 && ((repi != NULL 1560 && (insn & repi->mask) == (unsigned) repi->opcode) 1561 || (rep != NULL 1562 && (insn & rep->mask) == (unsigned) rep->opcode)) 1563 && value < 4) 1564 as_fatal 1565 (_("line %d: rep or repi must include at least 4 instructions"), 1566 fixP->fx_line); 1567 insn = 1568 d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP); 1569 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); 1570 } 1571 break; 1572 case BFD_RELOC_32: 1573 bfd_putb32 ((bfd_vma) value, (unsigned char *) where); 1574 break; 1575 case BFD_RELOC_16: 1576 bfd_putb16 ((bfd_vma) value, (unsigned char *) where); 1577 break; 1578 1579 case BFD_RELOC_VTABLE_INHERIT: 1580 case BFD_RELOC_VTABLE_ENTRY: 1581 fixP->fx_done = 0; 1582 return; 1583 1584 default: 1585 as_fatal (_("line %d: unknown relocation type: 0x%x"), 1586 fixP->fx_line, fixP->fx_r_type); 1587 } 1588 } 1589 1590 /* d10v_cleanup() is called after the assembler has finished parsing 1591 the input file, when a label is read from the input file, or when a 1592 stab directive is output. Because the D10V assembler sometimes 1593 saves short instructions to see if it can package them with the 1594 next instruction, there may be a short instruction that still needs 1595 to be written. 1596 1597 NOTE: accesses a global, etype. 1598 NOTE: invoked by various macros such as md_cleanup: see. */ 1599 1600 int 1601 d10v_cleanup (void) 1602 { 1603 segT seg; 1604 subsegT subseg; 1605 1606 /* If cleanup was invoked because the assembler encountered, e.g., a 1607 user label, we write out the pending instruction, if any. If it 1608 was invoked because the assembler is outputting a piece of line 1609 debugging information, though, we write out the pending 1610 instruction only if the --no-gstabs-packing command line switch 1611 has been specified. */ 1612 if (prev_opcode 1613 && etype == PACK_UNSPEC 1614 && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing)) 1615 { 1616 seg = now_seg; 1617 subseg = now_subseg; 1618 1619 if (prev_seg) 1620 subseg_set (prev_seg, prev_subseg); 1621 1622 write_1_short (prev_opcode, prev_insn, fixups->next); 1623 subseg_set (seg, subseg); 1624 prev_opcode = NULL; 1625 } 1626 return 1; 1627 } 1628 1629 /* Like normal .word, except support @word. 1630 Clobbers input_line_pointer, checks end-of-line. */ 1631 1632 static void 1633 d10v_dot_word (int dummy ATTRIBUTE_UNUSED) 1634 { 1635 expressionS exp; 1636 char *p; 1637 1638 if (is_it_end_of_statement ()) 1639 { 1640 demand_empty_rest_of_line (); 1641 return; 1642 } 1643 1644 do 1645 { 1646 expression (&exp); 1647 if (!strncasecmp (input_line_pointer, "@word", 5)) 1648 { 1649 exp.X_add_number = 0; 1650 input_line_pointer += 5; 1651 1652 p = frag_more (2); 1653 fix_new_exp (frag_now, p - frag_now->fr_literal, 2, 1654 &exp, 0, BFD_RELOC_D10V_18); 1655 } 1656 else 1657 emit_expr (&exp, 2); 1658 } 1659 while (*input_line_pointer++ == ','); 1660 1661 input_line_pointer--; /* Put terminator back into stream. */ 1662 demand_empty_rest_of_line (); 1663 } 1664 1665 /* Mitsubishi asked that we support some old syntax that apparently 1666 had immediate operands starting with '#'. This is in some of their 1667 sample code but is not documented (although it appears in some 1668 examples in their assembler manual). For now, we'll solve this 1669 compatibility problem by simply ignoring any '#' at the beginning 1670 of an operand. */ 1671 1672 /* Operands that begin with '#' should fall through to here. 1673 From expr.c. */ 1674 1675 void 1676 md_operand (expressionS *expressionP) 1677 { 1678 if (*input_line_pointer == '#' && ! do_not_ignore_hash) 1679 { 1680 input_line_pointer++; 1681 expression (expressionP); 1682 } 1683 } 1684 1685 bfd_boolean 1686 d10v_fix_adjustable (fixS *fixP) 1687 { 1688 /* We need the symbol name for the VTABLE entries. */ 1689 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 1690 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1691 return 0; 1692 1693 return 1; 1694 } 1695 1696 /* The target specific pseudo-ops which we support. */ 1697 const pseudo_typeS md_pseudo_table[] = 1698 { 1699 { "word", d10v_dot_word, 2 }, 1700 { NULL, NULL, 0 } 1701 }; 1702 1703 void 1704 md_assemble (char *str) 1705 { 1706 /* etype is saved extype. For multi-line instructions. */ 1707 packing_type extype = PACK_UNSPEC; /* Parallel, etc. */ 1708 struct d10v_opcode *opcode; 1709 unsigned long insn; 1710 char *str2; 1711 1712 if (etype == PACK_UNSPEC) 1713 { 1714 /* Look for the special multiple instruction separators. */ 1715 str2 = strstr (str, "||"); 1716 if (str2) 1717 extype = PACK_PARALLEL; 1718 else 1719 { 1720 str2 = strstr (str, "->"); 1721 if (str2) 1722 extype = PACK_LEFT_RIGHT; 1723 else 1724 { 1725 str2 = strstr (str, "<-"); 1726 if (str2) 1727 extype = PACK_RIGHT_LEFT; 1728 } 1729 } 1730 1731 /* str2 points to the separator, if there is one. */ 1732 if (str2) 1733 { 1734 *str2 = 0; 1735 1736 /* If two instructions are present and we already have one saved, 1737 then first write out the saved one. */ 1738 d10v_cleanup (); 1739 1740 /* Assemble first instruction and save it. */ 1741 prev_insn = do_assemble (str, &prev_opcode); 1742 prev_seg = now_seg; 1743 prev_subseg = now_subseg; 1744 if (prev_insn == (unsigned long) -1) 1745 as_fatal (_("can't find previous opcode ")); 1746 fixups = fixups->next; 1747 str = str2 + 2; 1748 } 1749 } 1750 1751 insn = do_assemble (str, &opcode); 1752 if (insn == (unsigned long) -1) 1753 { 1754 if (extype != PACK_UNSPEC) 1755 etype = extype; 1756 else 1757 as_bad (_("could not assemble: %s"), str); 1758 return; 1759 } 1760 1761 if (etype != PACK_UNSPEC) 1762 { 1763 extype = etype; 1764 etype = PACK_UNSPEC; 1765 } 1766 1767 /* If this is a long instruction, write it and any previous short 1768 instruction. */ 1769 if (opcode->format & LONG_OPCODE) 1770 { 1771 if (extype != PACK_UNSPEC) 1772 as_fatal (_("Unable to mix instructions as specified")); 1773 d10v_cleanup (); 1774 write_long (insn, fixups); 1775 prev_opcode = NULL; 1776 return; 1777 } 1778 1779 if (prev_opcode 1780 && prev_seg 1781 && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) 1782 d10v_cleanup (); 1783 1784 if (prev_opcode 1785 && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype, 1786 fixups))) 1787 { 1788 /* No instructions saved. */ 1789 prev_opcode = NULL; 1790 } 1791 else 1792 { 1793 if (extype != PACK_UNSPEC) 1794 as_fatal (_("Unable to mix instructions as specified")); 1795 /* Save last instruction so it may be packed on next pass. */ 1796 prev_opcode = opcode; 1797 prev_insn = insn; 1798 prev_seg = now_seg; 1799 prev_subseg = now_subseg; 1800 fixups = fixups->next; 1801 } 1802 } 1803 1804