1 /* tc-cris.c -- Assembler code for the CRIS CPU core. 2 Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 3 Free Software Foundation, Inc. 4 5 Contributed by Axis Communications AB, Lund, Sweden. 6 Originally written for GAS 1.38.1 by Mikael Asker. 7 Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson. 8 9 This file is part of GAS, the GNU Assembler. 10 11 GAS is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 GAS is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GAS; see the file COPYING. If not, write to the 23 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 24 MA 02110-1301, USA. */ 25 26 #include "as.h" 27 #include "safe-ctype.h" 28 #include "subsegs.h" 29 #include "opcode/cris.h" 30 #include "dwarf2dbg.h" 31 32 /* Conventions used here: 33 Generally speaking, pointers to binutils types such as "fragS" and 34 "expressionS" get parameter and variable names ending in "P", such as 35 "fragP", to harmonize with the rest of the binutils code. Other 36 pointers get a "p" suffix, such as "bufp". Any function or type-name 37 that could clash with a current or future binutils or GAS function get 38 a "cris_" prefix. */ 39 40 #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix" 41 #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix" 42 #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore" 43 #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore" 44 #define REGISTER_PREFIX_CHAR '$' 45 46 /* True for expressions where getting X_add_symbol and X_add_number is 47 enough to get the "base" and "offset"; no need to make_expr_symbol. 48 It's not enough to check if X_op_symbol is NULL; that misses unary 49 operations like O_uminus. */ 50 #define SIMPLE_EXPR(EXP) \ 51 ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol) 52 53 /* Like in ":GOT", ":GOTOFF" etc. Other ports use '@', but that's in 54 line_separator_chars for CRIS, so we avoid it. */ 55 #define RELOC_SUFFIX_CHAR ':' 56 57 /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only. 58 Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL. */ 59 enum cris_insn_kind 60 { 61 CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH, CRIS_INSN_MUL 62 }; 63 64 /* An instruction will have one of these prefixes. 65 Although the same bit-pattern, we handle BDAP with an immediate 66 expression (eventually quick or [pc+]) different from when we only have 67 register expressions. */ 68 enum prefix_kind 69 { 70 PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP, 71 PREFIX_PUSH 72 }; 73 74 /* The prefix for an instruction. */ 75 struct cris_prefix 76 { 77 enum prefix_kind kind; 78 int base_reg_number; 79 unsigned int opcode; 80 81 /* There might be an expression to be evaluated, like I in [rN+I]. */ 82 expressionS expr; 83 84 /* If there's an expression, we might need a relocation. Here's the 85 type of what relocation to start relaxaton with. 86 The relocation is assumed to start immediately after the prefix insn, 87 so we don't provide an offset. */ 88 enum bfd_reloc_code_real reloc; 89 }; 90 91 /* The description of the instruction being assembled. */ 92 struct cris_instruction 93 { 94 /* If CRIS_INSN_NONE, then this insn is of zero length. */ 95 enum cris_insn_kind insn_type; 96 97 /* If a special register was mentioned, this is its description, else 98 it is NULL. */ 99 const struct cris_spec_reg *spec_reg; 100 101 unsigned int opcode; 102 103 /* An insn may have at most one expression; theoretically there could be 104 another in its prefix (but I don't see how that could happen). */ 105 expressionS expr; 106 107 /* The expression might need a relocation. Here's one to start 108 relaxation with. */ 109 enum bfd_reloc_code_real reloc; 110 111 /* The size in bytes of an immediate expression, or zero if 112 nonapplicable. */ 113 int imm_oprnd_size; 114 }; 115 116 enum cris_archs 117 { 118 arch_cris_unknown, 119 arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10, 120 arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32 121 }; 122 123 static enum cris_archs cris_arch_from_string (char **); 124 static int cris_insn_ver_valid_for_arch (enum cris_insn_version_usage, 125 enum cris_archs); 126 127 static void cris_process_instruction (char *, struct cris_instruction *, 128 struct cris_prefix *); 129 static int get_bwd_size_modifier (char **, int *); 130 static int get_bw_size_modifier (char **, int *); 131 static int get_gen_reg (char **, int *); 132 static int get_spec_reg (char **, const struct cris_spec_reg **); 133 static int get_sup_reg (char **, int *); 134 static int get_autoinc_prefix_or_indir_op (char **, struct cris_prefix *, 135 int *, int *, int *, 136 expressionS *); 137 static int get_3op_or_dip_prefix_op (char **, struct cris_prefix *); 138 static int cris_get_expression (char **, expressionS *); 139 static int get_flags (char **, int *); 140 static void gen_bdap (int, expressionS *); 141 static int branch_disp (int); 142 static void gen_cond_branch_32 (char *, char *, fragS *, symbolS *, symbolS *, 143 long int); 144 static void cris_number_to_imm (char *, long, int, fixS *, segT); 145 static void s_syntax (int); 146 static void s_cris_file (int); 147 static void s_cris_loc (int); 148 static void s_cris_arch (int); 149 static void s_cris_dtpoff (int); 150 151 /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes. */ 152 static void cris_get_reloc_suffix (char **, bfd_reloc_code_real_type *, 153 expressionS *); 154 static unsigned int cris_get_specified_reloc_size (bfd_reloc_code_real_type); 155 156 /* All the .syntax functions. */ 157 static void cris_force_reg_prefix (void); 158 static void cris_relax_reg_prefix (void); 159 static void cris_sym_leading_underscore (void); 160 static void cris_sym_no_leading_underscore (void); 161 static char *cris_insn_first_word_frag (void); 162 163 /* Handle to the opcode hash table. */ 164 static struct hash_control *op_hash = NULL; 165 166 /* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf), 167 we default to no underscore and required register-prefixes. The 168 difference is in the default values. */ 169 #ifdef TE_LINUX 170 #define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE 171 #else 172 #define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE 173 #endif 174 175 /* Whether we demand that registers have a `$' prefix. Default here. */ 176 static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU; 177 178 /* Whether global user symbols have a leading underscore. Default here. */ 179 static bfd_boolean symbols_have_leading_underscore 180 = !DEFAULT_CRIS_AXIS_LINUX_GNU; 181 182 /* Whether or not we allow PIC, and expand to PIC-friendly constructs. */ 183 static bfd_boolean pic = FALSE; 184 185 /* Whether or not we allow TLS suffixes. For the moment, we always do. */ 186 static const bfd_boolean tls = TRUE; 187 188 /* If we're configured for "cris", default to allow all v0..v10 189 instructions and register names. */ 190 #ifndef DEFAULT_CRIS_ARCH 191 #define DEFAULT_CRIS_ARCH cris_any_v0_v10 192 #endif 193 194 /* No whitespace in the CONCAT2 parameter list. */ 195 static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH); 196 197 const pseudo_typeS md_pseudo_table[] = 198 { 199 {"dword", cons, 4}, 200 {"dtpoffd", s_cris_dtpoff, 4}, 201 {"syntax", s_syntax, 0}, 202 {"file", s_cris_file, 0}, 203 {"loc", s_cris_loc, 0}, 204 {"arch", s_cris_arch, 0}, 205 {NULL, 0, 0} 206 }; 207 208 static int warn_for_branch_expansion = 0; 209 210 /* Whether to emit error when a MULS/MULU could be located last on a 211 cache-line. */ 212 static int err_for_dangerous_mul_placement 213 = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32); 214 215 const char cris_comment_chars[] = ";"; 216 217 /* This array holds the chars that only start a comment at the beginning of 218 a line. If the line seems to have the form '# 123 filename' 219 .line and .file directives will appear in the pre-processed output. */ 220 /* Note that input_file.c hand-checks for '#' at the beginning of the 221 first line of the input file. This is because the compiler outputs 222 #NO_APP at the beginning of its output. */ 223 /* Also note that slash-star will always start a comment. */ 224 const char line_comment_chars[] = "#"; 225 const char line_separator_chars[] = "@"; 226 227 /* Now all floating point support is shut off. See md_atof. */ 228 const char EXP_CHARS[] = ""; 229 const char FLT_CHARS[] = ""; 230 231 /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as: 232 2 1 0 233 ---/ /--+-----------------+-----------------+-----------------+ 234 | what state ? | how long ? | 235 ---/ /--+-----------------+-----------------+-----------------+ 236 237 The "how long" bits are 00 = byte, 01 = word, 10 = dword (long). 238 Not all lengths are legit for a given value of (what state). 239 240 Groups for CRIS address relaxing: 241 242 1. Bcc (pre-V32) 243 length: byte, word, 10-byte expansion 244 245 2. BDAP 246 length: byte, word, dword 247 248 3. MULS/MULU 249 Not really a relaxation (no infrastructure to get delay-slots 250 right), just an alignment and placement checker for the v10 251 multiply/cache-bug. 252 253 4. Bcc (V32 and later) 254 length: byte, word, 14-byte expansion 255 256 5. Bcc (V10+V32) 257 length: byte, word, error 258 259 6. BA (V32) 260 length: byte, word, dword 261 262 7. LAPC (V32) 263 length: byte, dword 264 */ 265 266 #define STATE_COND_BRANCH (1) 267 #define STATE_BASE_PLUS_DISP_PREFIX (2) 268 #define STATE_MUL (3) 269 #define STATE_COND_BRANCH_V32 (4) 270 #define STATE_COND_BRANCH_COMMON (5) 271 #define STATE_ABS_BRANCH_V32 (6) 272 #define STATE_LAPC (7) 273 #define STATE_COND_BRANCH_PIC (8) 274 275 #define STATE_LENGTH_MASK (3) 276 #define STATE_BYTE (0) 277 #define STATE_WORD (1) 278 #define STATE_DWORD (2) 279 /* Symbol undefined. */ 280 #define STATE_UNDF (3) 281 #define STATE_MAX_LENGTH (3) 282 283 /* These displacements are relative to the address following the opcode 284 word of the instruction. The first letter is Byte, Word. The 2nd 285 letter is Forward, Backward. */ 286 287 #define BRANCH_BF ( 254) 288 #define BRANCH_BB (-256) 289 #define BRANCH_BF_V32 ( 252) 290 #define BRANCH_BB_V32 (-258) 291 #define BRANCH_WF (2 + 32767) 292 #define BRANCH_WB (2 + -32768) 293 #define BRANCH_WF_V32 (-2 + 32767) 294 #define BRANCH_WB_V32 (-2 + -32768) 295 296 #define BDAP_BF ( 127) 297 #define BDAP_BB (-128) 298 #define BDAP_WF ( 32767) 299 #define BDAP_WB (-32768) 300 301 #define ENCODE_RELAX(what, length) (((what) << 2) + (length)) 302 303 const relax_typeS md_cris_relax_table[] = 304 { 305 /* Error sentinel (0, 0). */ 306 {1, 1, 0, 0}, 307 308 /* Unused (0, 1). */ 309 {1, 1, 0, 0}, 310 311 /* Unused (0, 2). */ 312 {1, 1, 0, 0}, 313 314 /* Unused (0, 3). */ 315 {1, 1, 0, 0}, 316 317 /* Bcc o (1, 0). */ 318 {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (1, 1)}, 319 320 /* Bcc [PC+] (1, 1). */ 321 {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (1, 2)}, 322 323 /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default) 324 (1, 2). */ 325 {0, 0, 10, 0}, 326 327 /* Unused (1, 3). */ 328 {1, 1, 0, 0}, 329 330 /* BDAP o (2, 0). */ 331 {BDAP_BF, BDAP_BB, 0, ENCODE_RELAX (2, 1)}, 332 333 /* BDAP.[bw] [PC+] (2, 1). */ 334 {BDAP_WF, BDAP_WB, 2, ENCODE_RELAX (2, 2)}, 335 336 /* BDAP.d [PC+] (2, 2). */ 337 {0, 0, 4, 0}, 338 339 /* Unused (2, 3). */ 340 {1, 1, 0, 0}, 341 342 /* MULS/MULU (3, 0). Positions (3, 1..3) are unused. */ 343 {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, 344 345 /* V32: Bcc o (4, 0). */ 346 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (4, 1)}, 347 348 /* V32: Bcc [PC+] (4, 1). */ 349 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (4, 2)}, 350 351 /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6 (4, 2). */ 352 {0, 0, 12, 0}, 353 354 /* Unused (4, 3). */ 355 {1, 1, 0, 0}, 356 357 /* COMMON: Bcc o (5, 0). The offsets are calculated as for v32. Code 358 should contain two nop insns (or four if offset size is large or 359 unknown) after every label. */ 360 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (5, 1)}, 361 362 /* COMMON: Bcc [PC+] (5, 1). */ 363 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (5, 2)}, 364 365 /* COMMON: FIXME: ???. Treat as error currently. */ 366 {0, 0, 12, 0}, 367 368 /* Unused (5, 3). */ 369 {1, 1, 0, 0}, 370 371 /* V32: BA o (6, 0). */ 372 {BRANCH_BF_V32, BRANCH_BB_V32, 0, ENCODE_RELAX (6, 1)}, 373 374 /* V32: BA.W (6, 1). */ 375 {BRANCH_WF_V32, BRANCH_WB_V32, 2, ENCODE_RELAX (6, 2)}, 376 377 /* V32: BA.D (6, 2). */ 378 {0, 0, 4, 0}, 379 380 /* Unused (6, 3). */ 381 {1, 1, 0, 0}, 382 383 /* LAPC: LAPCQ .+0..15*2,Rn (7, 0). */ 384 {14*2, -1*2, 0, ENCODE_RELAX (7, 2)}, 385 386 /* Unused (7, 1). 387 While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ, 388 that would affect flags, so we can't do that as it wouldn't be a 389 proper insn expansion of LAPCQ. This row is associated with a 390 2-byte expansion, so it's unused rather than the next. */ 391 {1, 1, 0, 0}, 392 393 /* LAPC: LAPC.D (7, 2). */ 394 {0, 0, 4, 0}, 395 396 /* Unused (7, 3). */ 397 {1, 1, 0, 0}, 398 399 /* PIC for pre-v32: Bcc o (8, 0). */ 400 {BRANCH_BF, BRANCH_BB, 0, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 1)}, 401 402 /* Bcc [PC+] (8, 1). */ 403 {BRANCH_WF, BRANCH_WB, 2, ENCODE_RELAX (STATE_COND_BRANCH_PIC, 2)}, 404 405 /* 32-bit expansion, PIC (8, 2). */ 406 {0, 0, 12, 0}, 407 408 /* Unused (8, 3). */ 409 {1, 1, 0, 0} 410 }; 411 412 #undef BDAP_BF 413 #undef BDAP_BB 414 #undef BDAP_WF 415 #undef BDAP_WB 416 417 /* Target-specific multicharacter options, not const-declared. */ 418 struct option md_longopts[] = 419 { 420 #define OPTION_NO_US (OPTION_MD_BASE + 0) 421 {"no-underscore", no_argument, NULL, OPTION_NO_US}, 422 #define OPTION_US (OPTION_MD_BASE + 1) 423 {"underscore", no_argument, NULL, OPTION_US}, 424 #define OPTION_PIC (OPTION_US + 1) 425 {"pic", no_argument, NULL, OPTION_PIC}, 426 #define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1) 427 {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON}, 428 #define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1) 429 {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF}, 430 #define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1) 431 {"march", required_argument, NULL, OPTION_ARCH}, 432 {NULL, no_argument, NULL, 0} 433 }; 434 435 /* Not const-declared. */ 436 size_t md_longopts_size = sizeof (md_longopts); 437 const char *md_shortopts = "hHN"; 438 439 /* At first glance, this may seems wrong and should be 4 (ba + nop); but 440 since a short_jump must skip a *number* of long jumps, it must also be 441 a long jump. Here, we hope to make it a "ba [16bit_offs]" and a "nop" 442 for the delay slot and hope that the jump table at most needs 443 32767/4=8191 long-jumps. A branch is better than a jump, since it is 444 relative; we will not have a reloc to fix up somewhere. 445 446 Note that we can't add relocs, because relaxation uses these fixed 447 numbers, and md_create_short_jump is called after relaxation. */ 448 449 int md_short_jump_size = 6; 450 451 /* The v32 version has a delay-slot, hence two bytes longer. 452 The pre-v32 PIC version uses a prefixed insn. */ 453 #define cris_any_v0_v10_long_jump_size 6 454 #define cris_any_v0_v10_long_jump_size_pic 8 455 #define crisv32_long_jump_size 8 456 457 int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size); 458 459 /* Report output format. Small changes in output format (like elf 460 variants below) can happen until all options are parsed, but after 461 that, the output format must remain fixed. */ 462 463 const char * 464 cris_target_format (void) 465 { 466 switch (OUTPUT_FLAVOR) 467 { 468 case bfd_target_aout_flavour: 469 return "a.out-cris"; 470 471 case bfd_target_elf_flavour: 472 if (symbols_have_leading_underscore) 473 return "elf32-us-cris"; 474 return "elf32-cris"; 475 476 default: 477 abort (); 478 return NULL; 479 } 480 } 481 482 /* Return a bfd_mach_cris... value corresponding to the value of 483 cris_arch. */ 484 485 unsigned int 486 cris_mach (void) 487 { 488 unsigned int retval = 0; 489 490 switch (cris_arch) 491 { 492 case arch_cris_common_v10_v32: 493 retval = bfd_mach_cris_v10_v32; 494 break; 495 496 case arch_crisv32: 497 retval = bfd_mach_cris_v32; 498 break; 499 500 case arch_crisv10: 501 case arch_cris_any_v0_v10: 502 retval = bfd_mach_cris_v0_v10; 503 break; 504 505 default: 506 BAD_CASE (cris_arch); 507 } 508 509 return retval; 510 } 511 512 /* We need a port-specific relaxation function to cope with sym2 - sym1 513 relative expressions with both symbols in the same segment (but not 514 necessarily in the same frag as this insn), for example: 515 move.d [pc+sym2-(sym1-2)],r10 516 sym1: 517 The offset can be 8, 16 or 32 bits long. */ 518 519 long 520 cris_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP, 521 long stretch ATTRIBUTE_UNUSED) 522 { 523 long growth; 524 offsetT aim = 0; 525 symbolS *symbolP; 526 const relax_typeS *this_type; 527 const relax_typeS *start_type; 528 relax_substateT next_state; 529 relax_substateT this_state; 530 const relax_typeS *table = TC_GENERIC_RELAX_TABLE; 531 532 /* We only have to cope with frags as prepared by 533 md_estimate_size_before_relax. The dword cases may get here 534 because of the different reasons that they aren't relaxable. */ 535 switch (fragP->fr_subtype) 536 { 537 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): 538 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): 539 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): 540 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): 541 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): 542 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): 543 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): 544 /* When we get to these states, the frag won't grow any more. */ 545 return 0; 546 547 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): 548 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): 549 if (fragP->fr_symbol == NULL 550 || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 551 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), 552 __FUNCTION__, (long) fragP->fr_symbol); 553 symbolP = fragP->fr_symbol; 554 if (symbol_resolved_p (symbolP)) 555 as_fatal (_("internal inconsistency problem in %s: resolved symbol"), 556 __FUNCTION__); 557 aim = S_GET_VALUE (symbolP); 558 break; 559 560 case ENCODE_RELAX (STATE_MUL, STATE_BYTE): 561 /* Nothing to do here. */ 562 return 0; 563 564 default: 565 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), 566 __FUNCTION__, fragP->fr_subtype); 567 } 568 569 /* The rest is stolen from relax_frag. There's no obvious way to 570 share the code, but fortunately no requirement to keep in sync as 571 long as fragP->fr_symbol does not have its segment changed. */ 572 573 this_state = fragP->fr_subtype; 574 start_type = this_type = table + this_state; 575 576 if (aim < 0) 577 { 578 /* Look backwards. */ 579 for (next_state = this_type->rlx_more; next_state;) 580 if (aim >= this_type->rlx_backward) 581 next_state = 0; 582 else 583 { 584 /* Grow to next state. */ 585 this_state = next_state; 586 this_type = table + this_state; 587 next_state = this_type->rlx_more; 588 } 589 } 590 else 591 { 592 /* Look forwards. */ 593 for (next_state = this_type->rlx_more; next_state;) 594 if (aim <= this_type->rlx_forward) 595 next_state = 0; 596 else 597 { 598 /* Grow to next state. */ 599 this_state = next_state; 600 this_type = table + this_state; 601 next_state = this_type->rlx_more; 602 } 603 } 604 605 growth = this_type->rlx_length - start_type->rlx_length; 606 if (growth != 0) 607 fragP->fr_subtype = this_state; 608 return growth; 609 } 610 611 /* Prepare machine-dependent frags for relaxation. 612 613 Called just before relaxation starts. Any symbol that is now undefined 614 will not become defined. 615 616 Return the correct fr_subtype in the frag. 617 618 Return the initial "guess for fr_var" to caller. The guess for fr_var 619 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix 620 or fr_var contributes to our returned value. 621 622 Although it may not be explicit in the frag, pretend 623 fr_var starts with a value. */ 624 625 int 626 md_estimate_size_before_relax (fragS *fragP, segT segment_type) 627 { 628 int old_fr_fix; 629 symbolS *symbolP = fragP->fr_symbol; 630 631 #define HANDLE_RELAXABLE(state) \ 632 case ENCODE_RELAX (state, STATE_UNDF): \ 633 if (symbolP != NULL \ 634 && S_GET_SEGMENT (symbolP) == segment_type \ 635 && !S_IS_WEAK (symbolP)) \ 636 /* The symbol lies in the same segment - a relaxable \ 637 case. */ \ 638 fragP->fr_subtype \ 639 = ENCODE_RELAX (state, STATE_BYTE); \ 640 else \ 641 /* Unknown or not the same segment, so not relaxable. */ \ 642 fragP->fr_subtype \ 643 = ENCODE_RELAX (state, STATE_DWORD); \ 644 fragP->fr_var \ 645 = md_cris_relax_table[fragP->fr_subtype].rlx_length; \ 646 break 647 648 old_fr_fix = fragP->fr_fix; 649 650 switch (fragP->fr_subtype) 651 { 652 HANDLE_RELAXABLE (STATE_COND_BRANCH); 653 HANDLE_RELAXABLE (STATE_COND_BRANCH_V32); 654 HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON); 655 HANDLE_RELAXABLE (STATE_COND_BRANCH_PIC); 656 HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32); 657 658 case ENCODE_RELAX (STATE_LAPC, STATE_UNDF): 659 if (symbolP != NULL 660 && S_GET_SEGMENT (symbolP) == segment_type 661 && !S_IS_WEAK (symbolP)) 662 { 663 /* The symbol lies in the same segment - a relaxable case. 664 Check if we currently have an odd offset; we can't code 665 that into the instruction. Relaxing presumably only cause 666 multiple-of-two changes, so we should only need to adjust 667 for that here. */ 668 bfd_vma target_address 669 = (symbolP 670 ? S_GET_VALUE (symbolP) 671 : 0) + fragP->fr_offset; 672 bfd_vma var_part_offset = fragP->fr_fix; 673 bfd_vma address_of_var_part = fragP->fr_address + var_part_offset; 674 long offset = target_address - (address_of_var_part - 2); 675 676 fragP->fr_subtype 677 = (offset & 1) 678 ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD) 679 : ENCODE_RELAX (STATE_LAPC, STATE_BYTE); 680 } 681 else 682 /* Unknown or not the same segment, so not relaxable. */ 683 fragP->fr_subtype 684 = ENCODE_RELAX (STATE_LAPC, STATE_DWORD); 685 fragP->fr_var 686 = md_cris_relax_table[fragP->fr_subtype].rlx_length; 687 break; 688 689 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF): 690 /* Note that we can not do anything sane with relaxing 691 [rX + a_known_symbol_in_text], it will have to be a 32-bit 692 value. 693 694 We could play tricks with managing a constant pool and make 695 a_known_symbol_in_text a "bdap [pc + offset]" pointing there 696 (like the GOT for ELF shared libraries), but that's no use, it 697 would in general be no shorter or faster code, only more 698 complicated. */ 699 700 if (S_GET_SEGMENT (symbolP) != absolute_section) 701 { 702 /* Go for dword if not absolute or same segment. */ 703 fragP->fr_subtype 704 = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD); 705 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; 706 } 707 else if (!symbol_resolved_p (fragP->fr_symbol)) 708 { 709 /* The symbol will eventually be completely resolved as an 710 absolute expression, but right now it depends on the result 711 of relaxation and we don't know anything else about the 712 value. We start relaxation with the assumption that it'll 713 fit in a byte. */ 714 fragP->fr_subtype 715 = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE); 716 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; 717 } 718 else 719 { 720 /* Absolute expression. */ 721 long int value; 722 value = (symbolP != NULL 723 ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; 724 725 if (value >= -128 && value <= 127) 726 { 727 /* Byte displacement. */ 728 (fragP->fr_opcode)[0] = value; 729 } 730 else 731 { 732 /* Word or dword displacement. */ 733 int pow2_of_size = 1; 734 char *writep; 735 736 if (value < -32768 || value > 32767) 737 { 738 /* Outside word range, make it a dword. */ 739 pow2_of_size = 2; 740 } 741 742 /* Modify the byte-offset BDAP into a word or dword offset 743 BDAP. Or really, a BDAP rX,8bit into a 744 BDAP.[wd] rX,[PC+] followed by a word or dword. */ 745 (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16; 746 747 /* Keep the register number in the highest four bits. */ 748 (fragP->fr_opcode)[1] &= 0xF0; 749 (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH; 750 751 /* It grew by two or four bytes. */ 752 fragP->fr_fix += 1 << pow2_of_size; 753 writep = fragP->fr_literal + old_fr_fix; 754 md_number_to_chars (writep, value, 1 << pow2_of_size); 755 } 756 frag_wane (fragP); 757 } 758 break; 759 760 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): 761 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): 762 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): 763 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): 764 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): 765 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): 766 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): 767 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): 768 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): 769 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): 770 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): 771 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): 772 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): 773 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): 774 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): 775 case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): 776 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): 777 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): 778 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): 779 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): 780 /* When relaxing a section for the second time, we don't need to 781 do anything except making sure that fr_var is set right. */ 782 fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length; 783 break; 784 785 case ENCODE_RELAX (STATE_MUL, STATE_BYTE): 786 /* Nothing to do here. */ 787 break; 788 789 default: 790 BAD_CASE (fragP->fr_subtype); 791 } 792 793 return fragP->fr_var + (fragP->fr_fix - old_fr_fix); 794 } 795 796 /* Perform post-processing of machine-dependent frags after relaxation. 797 Called after relaxation is finished. 798 In: Address of frag. 799 fr_type == rs_machine_dependent. 800 fr_subtype is what the address relaxed to. 801 802 Out: Any fixS:s and constants are set up. 803 804 The caller will turn the frag into a ".space 0". */ 805 806 void 807 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, 808 fragS *fragP) 809 { 810 /* Pointer to first byte in variable-sized part of the frag. */ 811 char *var_partp; 812 813 /* Pointer to first opcode byte in frag. */ 814 char *opcodep; 815 816 /* Used to check integrity of the relaxation. 817 One of 2 = long, 1 = word, or 0 = byte. */ 818 int length_code ATTRIBUTE_UNUSED; 819 820 /* Size in bytes of variable-sized part of frag. */ 821 int var_part_size = 0; 822 823 /* This is part of *fragP. It contains all information about addresses 824 and offsets to varying parts. */ 825 symbolS *symbolP; 826 unsigned long var_part_offset; 827 828 /* Where, in file space, is _var of *fragP? */ 829 unsigned long address_of_var_part = 0; 830 831 /* Where, in file space, does addr point? */ 832 unsigned long target_address; 833 834 know (fragP->fr_type == rs_machine_dependent); 835 836 length_code = fragP->fr_subtype & STATE_LENGTH_MASK; 837 know (length_code >= 0 && length_code < STATE_MAX_LENGTH); 838 839 var_part_offset = fragP->fr_fix; 840 var_partp = fragP->fr_literal + var_part_offset; 841 opcodep = fragP->fr_opcode; 842 843 symbolP = fragP->fr_symbol; 844 target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset; 845 address_of_var_part = fragP->fr_address + var_part_offset; 846 847 switch (fragP->fr_subtype) 848 { 849 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE): 850 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE): 851 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE): 852 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE): 853 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE): 854 opcodep[0] = branch_disp ((target_address - address_of_var_part)); 855 var_part_size = 0; 856 break; 857 858 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD): 859 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD): 860 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD): 861 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD): 862 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD): 863 /* We had a quick immediate branch, now turn it into a word one i.e. a 864 PC autoincrement. */ 865 opcodep[0] = BRANCH_PC_LOW; 866 opcodep[1] &= 0xF0; 867 opcodep[1] |= BRANCH_INCR_HIGH; 868 md_number_to_chars (var_partp, 869 (long) 870 (target_address 871 - (address_of_var_part 872 + (cris_arch == arch_crisv32 873 || cris_arch == arch_cris_common_v10_v32 874 ? -2 : 2))), 875 2); 876 var_part_size = 2; 877 break; 878 879 case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD): 880 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, 881 fragP->fr_symbol, (symbolS *) NULL, 882 fragP->fr_offset); 883 /* Ten bytes added: a branch, nop and a jump. */ 884 var_part_size = 2 + 2 + 4 + 2; 885 break; 886 887 case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD): 888 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, 889 fragP->fr_symbol, (symbolS *) NULL, 890 fragP->fr_offset); 891 /* Twelve bytes added: a branch, nop and a pic-branch-32. */ 892 var_part_size = 2 + 2 + 4 + 2 + 2; 893 break; 894 895 case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD): 896 gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP, 897 fragP->fr_symbol, (symbolS *) NULL, 898 fragP->fr_offset); 899 /* Twelve bytes added: a branch, nop and another branch and nop. */ 900 var_part_size = 2 + 2 + 2 + 4 + 2; 901 break; 902 903 case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD): 904 as_bad_where (fragP->fr_file, fragP->fr_line, 905 _("Relaxation to long branches for .arch common_v10_v32\ 906 not implemented")); 907 /* Pretend we have twelve bytes for sake of quelling further 908 errors. */ 909 var_part_size = 2 + 2 + 2 + 4 + 2; 910 break; 911 912 case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD): 913 /* We had a quick immediate branch or a word immediate ba. Now 914 turn it into a dword one. */ 915 opcodep[0] = BA_DWORD_OPCODE & 255; 916 opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255; 917 fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP, 918 fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); 919 var_part_size = 4; 920 break; 921 922 case ENCODE_RELAX (STATE_LAPC, STATE_BYTE): 923 { 924 long offset = target_address - (address_of_var_part - 2); 925 926 /* This is mostly a sanity check; useful occurrences (if there 927 really are any) should have been caught in 928 md_estimate_size_before_relax. We can (at least 929 theoretically) stumble over invalid code with odd sizes and 930 .p2aligns within the code, so emit an error if that happens. 931 (The generic relaxation machinery is not fit to check this.) */ 932 933 if (offset & 1) 934 as_bad_where (fragP->fr_file, fragP->fr_line, 935 _("Complicated LAPC target operand is not\ 936 a multiple of two. Use LAPC.D")); 937 938 /* FIXME: This *is* a sanity check. Remove when done with. */ 939 if (offset > 15*2 || offset < 0) 940 as_fatal (_("Internal error found in md_convert_frag: offset %ld.\ 941 Please report this."), 942 offset); 943 944 opcodep[0] |= (offset / 2) & 0xf; 945 var_part_size = 0; 946 } 947 break; 948 949 case ENCODE_RELAX (STATE_LAPC, STATE_DWORD): 950 { 951 md_number_to_chars (opcodep, 952 LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256, 953 2); 954 /* Remember that the reloc is against the position *after* the 955 relocated contents, so we need to adjust to the start of 956 the insn. */ 957 fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, 958 fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL); 959 var_part_size = 4; 960 } 961 break; 962 963 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE): 964 if (symbolP == NULL) 965 as_fatal (_("internal inconsistency in %s: bdapq no symbol"), 966 __FUNCTION__); 967 opcodep[0] = S_GET_VALUE (symbolP); 968 var_part_size = 0; 969 break; 970 971 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD): 972 /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit 973 one that uses PC autoincrement. */ 974 opcodep[0] = BDAP_PC_LOW + (1 << 4); 975 opcodep[1] &= 0xF0; 976 opcodep[1] |= BDAP_INCR_HIGH; 977 if (symbolP == NULL) 978 as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"), 979 __FUNCTION__); 980 md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2); 981 var_part_size = 2; 982 break; 983 984 case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD): 985 /* We had a BDAP 16-bit "word", change the offset to a dword. */ 986 opcodep[0] = BDAP_PC_LOW + (2 << 4); 987 opcodep[1] &= 0xF0; 988 opcodep[1] |= BDAP_INCR_HIGH; 989 if (fragP->fr_symbol == NULL) 990 md_number_to_chars (var_partp, fragP->fr_offset, 4); 991 else 992 fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol, 993 fragP->fr_offset, 0, BFD_RELOC_32); 994 var_part_size = 4; 995 break; 996 997 case ENCODE_RELAX (STATE_MUL, STATE_BYTE): 998 /* This is the only time we check position and alignment of the 999 placement-tracking frag. */ 1000 if (sec->alignment_power < 2) 1001 as_bad_where (fragP->fr_file, fragP->fr_line, 1002 _("section alignment must be >= 4 bytes to check MULS/MULU safeness")); 1003 else 1004 { 1005 /* If the address after the MULS/MULU has alignment which is 1006 that of the section and may be that of a cache-size of the 1007 buggy versions, then the MULS/MULU can be placed badly. */ 1008 if ((address_of_var_part 1009 & ((1 << sec->alignment_power) - 1) & 31) == 0) 1010 as_bad_where (fragP->fr_file, fragP->fr_line, 1011 _("dangerous MULS/MULU location; give it higher alignment")); 1012 } 1013 break; 1014 1015 default: 1016 BAD_CASE (fragP->fr_subtype); 1017 break; 1018 } 1019 1020 fragP->fr_fix += var_part_size; 1021 } 1022 1023 /* Generate a short jump around a secondary jump table. 1024 Also called from md_create_long_jump, when sufficient. */ 1025 1026 void 1027 md_create_short_jump (char *storep, addressT from_addr, addressT to_addr, 1028 fragS *fragP ATTRIBUTE_UNUSED, 1029 symbolS *to_symbol ATTRIBUTE_UNUSED) 1030 { 1031 long int distance; 1032 1033 /* See md_create_long_jump about the comment on the "+ 2". */ 1034 long int max_minimal_minus_distance; 1035 long int max_minimal_plus_distance; 1036 long int max_minus_distance; 1037 long int max_plus_distance; 1038 int nop_opcode; 1039 1040 if (cris_arch == arch_crisv32) 1041 { 1042 max_minimal_minus_distance = BRANCH_BB_V32 + 2; 1043 max_minimal_plus_distance = BRANCH_BF_V32 + 2; 1044 max_minus_distance = BRANCH_WB_V32 + 2; 1045 max_plus_distance = BRANCH_WF_V32 + 2; 1046 nop_opcode = NOP_OPCODE_V32; 1047 } 1048 else if (cris_arch == arch_cris_common_v10_v32) 1049 /* Bail out for compatibility mode. (It seems it can be implemented, 1050 perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump 1051 $acr", "nop"; but doesn't seem worth it at the moment.) */ 1052 as_fatal (_("Out-of-range .word offset handling\ 1053 is not implemented for .arch common_v10_v32")); 1054 else 1055 { 1056 max_minimal_minus_distance = BRANCH_BB + 2; 1057 max_minimal_plus_distance = BRANCH_BF + 2; 1058 max_minus_distance = BRANCH_WB + 2; 1059 max_plus_distance = BRANCH_WF + 2; 1060 nop_opcode = NOP_OPCODE; 1061 } 1062 1063 distance = to_addr - from_addr; 1064 1065 if (max_minimal_minus_distance <= distance 1066 && distance <= max_minimal_plus_distance) 1067 { 1068 /* Create a "short" short jump: "BA distance - 2". */ 1069 storep[0] = branch_disp (distance - 2); 1070 storep[1] = BA_QUICK_HIGH; 1071 1072 /* A nop for the delay slot. */ 1073 md_number_to_chars (storep + 2, nop_opcode, 2); 1074 1075 /* The extra word should be filled with something sane too. Make it 1076 a nop to keep disassembly sane. */ 1077 md_number_to_chars (storep + 4, nop_opcode, 2); 1078 } 1079 else if (max_minus_distance <= distance 1080 && distance <= max_plus_distance) 1081 { 1082 /* Make it a "long" short jump: "BA (PC+)". */ 1083 md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2); 1084 1085 /* ".WORD distance - 4". */ 1086 md_number_to_chars (storep + 2, 1087 (long) (distance - 4 1088 - (cris_arch == arch_crisv32 1089 ? -4 : 0)), 1090 2); 1091 1092 /* A nop for the delay slot. */ 1093 md_number_to_chars (storep + 4, nop_opcode, 2); 1094 } 1095 else 1096 as_bad_where (fragP->fr_file, fragP->fr_line, 1097 _(".word case-table handling failed: table too large")); 1098 } 1099 1100 /* Generate a long jump in a secondary jump table. 1101 1102 storep Where to store the jump instruction. 1103 from_addr Address of the jump instruction. 1104 to_addr Destination address of the jump. 1105 fragP Which frag the destination address operand 1106 lies in. 1107 to_symbol Destination symbol. */ 1108 1109 void 1110 md_create_long_jump (char *storep, addressT from_addr, addressT to_addr, 1111 fragS *fragP, symbolS *to_symbol) 1112 { 1113 long int distance; 1114 1115 /* FIXME: What's that "+ 3"? It comes from the magic numbers that 1116 used to be here, it's just translated to the limit macros used in 1117 the relax table. But why + 3? */ 1118 long int max_short_minus_distance 1119 = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3; 1120 1121 long int max_short_plus_distance 1122 = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3; 1123 1124 distance = to_addr - from_addr; 1125 1126 if (max_short_minus_distance <= distance 1127 && distance <= max_short_plus_distance) 1128 /* Then make it a "short" long jump. */ 1129 md_create_short_jump (storep, from_addr, to_addr, fragP, 1130 to_symbol); 1131 else 1132 { 1133 /* We have a "long" long jump: "JUMP [PC+]". If CRISv32, always 1134 make it a BA. Else make it an "MOVE [PC=PC+N],P0" if we're supposed 1135 to emit PIC code. */ 1136 md_number_to_chars (storep, 1137 cris_arch == arch_crisv32 1138 ? BA_DWORD_OPCODE 1139 : (pic ? MOVE_PC_INCR_OPCODE_PREFIX 1140 : JUMP_PC_INCR_OPCODE), 1141 2); 1142 1143 /* Follow with a ".DWORD to_addr", PC-relative for PIC. */ 1144 fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol, 1145 cris_arch == arch_crisv32 ? 6 : 0, 1146 cris_arch == arch_crisv32 || pic ? 1 : 0, 1147 cris_arch == arch_crisv32 || pic 1148 ? BFD_RELOC_32_PCREL : BFD_RELOC_32); 1149 1150 /* Follow it with a "NOP" for CRISv32. */ 1151 if (cris_arch == arch_crisv32) 1152 md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2); 1153 else if (pic) 1154 /* ...and the rest of the move-opcode for pre-v32 PIC. */ 1155 md_number_to_chars (storep + 6, MOVE_PC_INCR_OPCODE_SUFFIX, 2); 1156 } 1157 } 1158 1159 /* Allocate space for the first piece of an insn, and mark it as the 1160 start of the insn for debug-format use. */ 1161 1162 static char * 1163 cris_insn_first_word_frag (void) 1164 { 1165 char *insnp = frag_more (2); 1166 1167 /* We need to mark the start of the insn by passing dwarf2_emit_insn 1168 the offset from the current fragment position. This must be done 1169 after the first fragment is created but before any other fragments 1170 (fixed or varying) are created. Note that the offset only 1171 corresponds to the "size" of the insn for a fixed-size, 1172 non-expanded insn. */ 1173 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 1174 dwarf2_emit_insn (2); 1175 1176 return insnp; 1177 } 1178 1179 /* Port-specific assembler initialization. */ 1180 1181 void 1182 md_begin (void) 1183 { 1184 const char *hashret = NULL; 1185 int i = 0; 1186 1187 /* Set up a hash table for the instructions. */ 1188 op_hash = hash_new (); 1189 if (op_hash == NULL) 1190 as_fatal (_("Virtual memory exhausted")); 1191 1192 /* Enable use of ".if ..asm.arch.cris.v32" 1193 and ".if ..asm.arch.cris.common_v10_v32" and a few others. */ 1194 symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section, 1195 (cris_arch == arch_crisv32), 1196 &zero_address_frag)); 1197 symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section, 1198 (cris_arch == arch_crisv10), 1199 &zero_address_frag)); 1200 symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32", 1201 absolute_section, 1202 (cris_arch == arch_cris_common_v10_v32), 1203 &zero_address_frag)); 1204 symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10", 1205 absolute_section, 1206 (cris_arch == arch_cris_any_v0_v10), 1207 &zero_address_frag)); 1208 1209 while (cris_opcodes[i].name != NULL) 1210 { 1211 const char *name = cris_opcodes[i].name; 1212 1213 if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version, 1214 cris_arch)) 1215 { 1216 i++; 1217 continue; 1218 } 1219 1220 /* Need to cast to get rid of "const". FIXME: Fix hash_insert instead. */ 1221 hashret = hash_insert (op_hash, name, (void *) &cris_opcodes[i]); 1222 1223 if (hashret != NULL && *hashret != '\0') 1224 as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name, 1225 *hashret == 0 ? _("(unknown reason)") : hashret); 1226 do 1227 { 1228 if (cris_opcodes[i].match & cris_opcodes[i].lose) 1229 as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name, 1230 cris_opcodes[i].args); 1231 1232 ++i; 1233 } 1234 while (cris_opcodes[i].name != NULL 1235 && strcmp (cris_opcodes[i].name, name) == 0); 1236 } 1237 } 1238 1239 /* Assemble a source line. */ 1240 1241 void 1242 md_assemble (char *str) 1243 { 1244 struct cris_instruction output_instruction; 1245 struct cris_prefix prefix; 1246 char *opcodep; 1247 char *p; 1248 1249 know (str); 1250 1251 /* Do the low-level grunt - assemble to bits and split up into a prefix 1252 and ordinary insn. */ 1253 cris_process_instruction (str, &output_instruction, &prefix); 1254 1255 /* Handle any prefixes to the instruction. */ 1256 switch (prefix.kind) 1257 { 1258 case PREFIX_NONE: 1259 break; 1260 1261 /* When the expression is unknown for a BDAP, it can need 0, 2 or 4 1262 extra bytes, so we handle it separately. */ 1263 case PREFIX_BDAP_IMM: 1264 /* We only do it if the relocation is unspecified, i.e. not a PIC or TLS 1265 relocation. */ 1266 if (prefix.reloc == BFD_RELOC_NONE) 1267 { 1268 gen_bdap (prefix.base_reg_number, &prefix.expr); 1269 break; 1270 } 1271 /* Fall through. */ 1272 case PREFIX_BDAP: 1273 case PREFIX_BIAP: 1274 case PREFIX_DIP: 1275 opcodep = cris_insn_first_word_frag (); 1276 1277 /* Output the prefix opcode. */ 1278 md_number_to_chars (opcodep, (long) prefix.opcode, 2); 1279 1280 /* Having a specified reloc only happens for DIP and for BDAP with 1281 PIC or TLS operands, but it is ok to drop through here for the other 1282 prefixes as they can have no relocs specified. */ 1283 if (prefix.reloc != BFD_RELOC_NONE) 1284 { 1285 unsigned int relocsize 1286 = (prefix.kind == PREFIX_DIP 1287 ? 4 : cris_get_specified_reloc_size (prefix.reloc)); 1288 1289 p = frag_more (relocsize); 1290 fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize, 1291 &prefix.expr, 0, prefix.reloc); 1292 } 1293 break; 1294 1295 case PREFIX_PUSH: 1296 opcodep = cris_insn_first_word_frag (); 1297 1298 /* Output the prefix opcode. Being a "push", we add the negative 1299 size of the register to "sp". */ 1300 if (output_instruction.spec_reg != NULL) 1301 { 1302 /* Special register. */ 1303 opcodep[0] = -output_instruction.spec_reg->reg_size; 1304 } 1305 else 1306 { 1307 /* General register. */ 1308 opcodep[0] = -4; 1309 } 1310 opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8); 1311 break; 1312 1313 default: 1314 BAD_CASE (prefix.kind); 1315 } 1316 1317 /* If we only had a prefix insn, we're done. */ 1318 if (output_instruction.insn_type == CRIS_INSN_NONE) 1319 return; 1320 1321 /* Done with the prefix. Continue with the main instruction. */ 1322 if (prefix.kind == PREFIX_NONE) 1323 opcodep = cris_insn_first_word_frag (); 1324 else 1325 opcodep = frag_more (2); 1326 1327 /* Output the instruction opcode. */ 1328 md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2); 1329 1330 /* Output the symbol-dependent instruction stuff. */ 1331 if (output_instruction.insn_type == CRIS_INSN_BRANCH) 1332 { 1333 segT to_seg = absolute_section; 1334 int is_undefined = 0; 1335 int length_code; 1336 1337 if (output_instruction.expr.X_op != O_constant) 1338 { 1339 to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol); 1340 1341 if (to_seg == undefined_section) 1342 is_undefined = 1; 1343 } 1344 1345 if (to_seg == now_seg || is_undefined 1346 /* In CRISv32, there *is* a 32-bit absolute branch, so don't 1347 emit the 12-byte sequence for known symbols in other 1348 segments. */ 1349 || (cris_arch == arch_crisv32 1350 && output_instruction.opcode == BA_QUICK_OPCODE)) 1351 { 1352 /* Handle complex expressions. */ 1353 valueT addvalue 1354 = (SIMPLE_EXPR (&output_instruction.expr) 1355 ? output_instruction.expr.X_add_number 1356 : 0); 1357 symbolS *sym 1358 = (SIMPLE_EXPR (&output_instruction.expr) 1359 ? output_instruction.expr.X_add_symbol 1360 : make_expr_symbol (&output_instruction.expr)); 1361 1362 /* If is_undefined, the expression may still become now_seg. 1363 That case is handled by md_estimate_size_before_relax. */ 1364 length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF; 1365 1366 /* Make room for max twelve bytes of variable length for v32 mode 1367 or PIC, ten for v10 and older. */ 1368 frag_var (rs_machine_dependent, 1369 (cris_arch == arch_crisv32 1370 || cris_arch == arch_cris_common_v10_v32 1371 || pic) ? 12 : 10, 0, 1372 ENCODE_RELAX (cris_arch == arch_crisv32 1373 ? (output_instruction.opcode 1374 == BA_QUICK_OPCODE 1375 ? STATE_ABS_BRANCH_V32 1376 : STATE_COND_BRANCH_V32) 1377 : (cris_arch == arch_cris_common_v10_v32 1378 ? STATE_COND_BRANCH_COMMON 1379 : (pic ? STATE_COND_BRANCH_PIC 1380 : STATE_COND_BRANCH)), 1381 length_code), 1382 sym, addvalue, opcodep); 1383 } 1384 else 1385 { 1386 /* We have: to_seg != now_seg && to_seg != undefined_section. 1387 This means it is a branch to a known symbol in another 1388 section, perhaps an absolute address. Emit a 32-bit branch. */ 1389 char *cond_jump 1390 = frag_more ((cris_arch == arch_crisv32 1391 || cris_arch == arch_cris_common_v10_v32 1392 || pic) 1393 ? 12 : 10); 1394 1395 gen_cond_branch_32 (opcodep, cond_jump, frag_now, 1396 output_instruction.expr.X_add_symbol, 1397 (symbolS *) NULL, 1398 output_instruction.expr.X_add_number); 1399 } 1400 } 1401 else if (output_instruction.insn_type == CRIS_INSN_MUL 1402 && err_for_dangerous_mul_placement) 1403 /* Create a frag which which we track the location of the mul insn 1404 (in the last two bytes before the mul-frag). */ 1405 frag_variant (rs_machine_dependent, 0, 0, 1406 ENCODE_RELAX (STATE_MUL, STATE_BYTE), 1407 NULL, 0, opcodep); 1408 else 1409 { 1410 if (output_instruction.imm_oprnd_size > 0) 1411 { 1412 /* The instruction has an immediate operand. */ 1413 enum bfd_reloc_code_real reloc = BFD_RELOC_NONE; 1414 1415 switch (output_instruction.imm_oprnd_size) 1416 { 1417 /* Any byte-size immediate constants are treated as 1418 word-size. FIXME: Thus overflow check does not work 1419 correctly. */ 1420 1421 case 2: 1422 /* Note that size-check for the explicit reloc has already 1423 been done when we get here. */ 1424 if (output_instruction.reloc != BFD_RELOC_NONE) 1425 reloc = output_instruction.reloc; 1426 else 1427 reloc = BFD_RELOC_16; 1428 break; 1429 1430 case 4: 1431 /* Allow a relocation specified in the operand. */ 1432 if (output_instruction.reloc != BFD_RELOC_NONE) 1433 reloc = output_instruction.reloc; 1434 else 1435 reloc = BFD_RELOC_32; 1436 break; 1437 1438 default: 1439 BAD_CASE (output_instruction.imm_oprnd_size); 1440 } 1441 1442 p = frag_more (output_instruction.imm_oprnd_size); 1443 fix_new_exp (frag_now, (p - frag_now->fr_literal), 1444 output_instruction.imm_oprnd_size, 1445 &output_instruction.expr, 1446 reloc == BFD_RELOC_32_PCREL 1447 || reloc == BFD_RELOC_16_PCREL 1448 || reloc == BFD_RELOC_8_PCREL, reloc); 1449 } 1450 else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET 1451 && output_instruction.expr.X_md != 0) 1452 { 1453 /* Handle complex expressions. */ 1454 valueT addvalue 1455 = (output_instruction.expr.X_op_symbol != NULL 1456 ? 0 : output_instruction.expr.X_add_number); 1457 symbolS *sym 1458 = (output_instruction.expr.X_op_symbol != NULL 1459 ? make_expr_symbol (&output_instruction.expr) 1460 : output_instruction.expr.X_add_symbol); 1461 1462 /* This is a relaxing construct, so we need a frag_var rather 1463 than the fix_new_exp call below. */ 1464 frag_var (rs_machine_dependent, 1465 4, 0, 1466 ENCODE_RELAX (STATE_LAPC, STATE_UNDF), 1467 sym, addvalue, opcodep); 1468 } 1469 else if (output_instruction.reloc != BFD_RELOC_NONE) 1470 { 1471 /* An immediate operand that has a relocation and needs to be 1472 processed further. */ 1473 1474 /* It is important to use fix_new_exp here and everywhere else 1475 (and not fix_new), as fix_new_exp can handle "difference 1476 expressions" - where the expression contains a difference of 1477 two symbols in the same segment. */ 1478 fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2, 1479 &output_instruction.expr, 1480 output_instruction.reloc == BFD_RELOC_32_PCREL 1481 || output_instruction.reloc == BFD_RELOC_16_PCREL 1482 || output_instruction.reloc == BFD_RELOC_8_PCREL 1483 || (output_instruction.reloc 1484 == BFD_RELOC_CRIS_LAPCQ_OFFSET), 1485 output_instruction.reloc); 1486 } 1487 } 1488 } 1489 1490 /* Low level text-to-bits assembly. */ 1491 1492 static void 1493 cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp, 1494 struct cris_prefix *prefixp) 1495 { 1496 char *s; 1497 char modified_char = 0; 1498 const char *args; 1499 struct cris_opcode *instruction; 1500 char *operands; 1501 int match = 0; 1502 int mode; 1503 int regno; 1504 int size_bits; 1505 1506 /* Reset these fields to a harmless state in case we need to return in 1507 error. */ 1508 prefixp->kind = PREFIX_NONE; 1509 prefixp->reloc = BFD_RELOC_NONE; 1510 out_insnp->insn_type = CRIS_INSN_NONE; 1511 out_insnp->imm_oprnd_size = 0; 1512 1513 /* Find the end of the opcode mnemonic. We assume (true in 2.9.1) 1514 that the caller has translated the opcode to lower-case, up to the 1515 first non-letter. */ 1516 for (operands = insn_text; ISLOWER (*operands); ++operands) 1517 ; 1518 1519 /* Terminate the opcode after letters, but save the character there if 1520 it was of significance. */ 1521 switch (*operands) 1522 { 1523 case '\0': 1524 break; 1525 1526 case '.': 1527 /* Put back the modified character later. */ 1528 modified_char = *operands; 1529 /* Fall through. */ 1530 1531 case ' ': 1532 /* Consume the character after the mnemonic 1533 and replace it with '\0'. */ 1534 *operands++ = '\0'; 1535 break; 1536 1537 default: 1538 as_bad (_("Unknown opcode: `%s'"), insn_text); 1539 return; 1540 } 1541 1542 /* Find the instruction. */ 1543 instruction = (struct cris_opcode *) hash_find (op_hash, insn_text); 1544 if (instruction == NULL) 1545 { 1546 as_bad (_("Unknown opcode: `%s'"), insn_text); 1547 return; 1548 } 1549 1550 /* Put back the modified character. */ 1551 switch (modified_char) 1552 { 1553 case 0: 1554 break; 1555 1556 default: 1557 *--operands = modified_char; 1558 } 1559 1560 /* Try to match an opcode table slot. */ 1561 for (s = operands;;) 1562 { 1563 int imm_expr_found; 1564 1565 /* Initialize *prefixp, perhaps after being modified for a 1566 "near match". */ 1567 prefixp->kind = PREFIX_NONE; 1568 prefixp->reloc = BFD_RELOC_NONE; 1569 1570 /* Initialize *out_insnp. */ 1571 memset (out_insnp, 0, sizeof (*out_insnp)); 1572 out_insnp->opcode = instruction->match; 1573 out_insnp->reloc = BFD_RELOC_NONE; 1574 out_insnp->insn_type = CRIS_INSN_NORMAL; 1575 out_insnp->imm_oprnd_size = 0; 1576 1577 imm_expr_found = 0; 1578 1579 /* Build the opcode, checking as we go to make sure that the 1580 operands match. */ 1581 for (args = instruction->args;; ++args) 1582 { 1583 switch (*args) 1584 { 1585 case '\0': 1586 /* If we've come to the end of arguments, we're done. */ 1587 if (*s == '\0') 1588 match = 1; 1589 break; 1590 1591 case '!': 1592 /* Non-matcher character for disassembly. 1593 Ignore it here. */ 1594 continue; 1595 1596 case '[': 1597 case ']': 1598 case ',': 1599 case ' ': 1600 /* These must match exactly. */ 1601 if (*s++ == *args) 1602 continue; 1603 break; 1604 1605 case 'A': 1606 /* "ACR", case-insensitive. 1607 Handle a sometimes-mandatory dollar sign as register 1608 prefix. */ 1609 if (*s == REGISTER_PREFIX_CHAR) 1610 s++; 1611 else if (demand_register_prefix) 1612 break; 1613 1614 if ((*s++ != 'a' && s[-1] != 'A') 1615 || (*s++ != 'c' && s[-1] != 'C') 1616 || (*s++ != 'r' && s[-1] != 'R')) 1617 break; 1618 continue; 1619 1620 case 'B': 1621 /* This is not really an operand, but causes a "BDAP 1622 -size,SP" prefix to be output, for PUSH instructions. */ 1623 prefixp->kind = PREFIX_PUSH; 1624 continue; 1625 1626 case 'b': 1627 /* This letter marks an operand that should not be matched 1628 in the assembler. It is a branch with 16-bit 1629 displacement. The assembler will create them from the 1630 8-bit flavor when necessary. The assembler does not 1631 support the [rN+] operand, as the [r15+] that is 1632 generated for 16-bit displacements. */ 1633 break; 1634 1635 case 'c': 1636 /* A 5-bit unsigned immediate in bits <4:0>. */ 1637 if (! cris_get_expression (&s, &out_insnp->expr)) 1638 break; 1639 else 1640 { 1641 if (out_insnp->expr.X_op == O_constant 1642 && (out_insnp->expr.X_add_number < 0 1643 || out_insnp->expr.X_add_number > 31)) 1644 as_bad (_("Immediate value not in 5 bit unsigned range: %ld"), 1645 out_insnp->expr.X_add_number); 1646 1647 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5; 1648 continue; 1649 } 1650 1651 case 'C': 1652 /* A 4-bit unsigned immediate in bits <3:0>. */ 1653 if (! cris_get_expression (&s, &out_insnp->expr)) 1654 break; 1655 else 1656 { 1657 if (out_insnp->expr.X_op == O_constant 1658 && (out_insnp->expr.X_add_number < 0 1659 || out_insnp->expr.X_add_number > 15)) 1660 as_bad (_("Immediate value not in 4 bit unsigned range: %ld"), 1661 out_insnp->expr.X_add_number); 1662 1663 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4; 1664 continue; 1665 } 1666 1667 /* For 'd', check for an optional ".d" or ".D" at the 1668 start of the operands, followed by a space character. */ 1669 case 'd': 1670 if (modified_char == '.' && *s == '.') 1671 { 1672 if ((s[1] != 'd' && s[1] == 'D') 1673 || ! ISSPACE (s[2])) 1674 break; 1675 s += 2; 1676 continue; 1677 } 1678 continue; 1679 1680 case 'D': 1681 /* General register in bits <15:12> and <3:0>. */ 1682 if (! get_gen_reg (&s, ®no)) 1683 break; 1684 else 1685 { 1686 out_insnp->opcode |= regno /* << 0 */; 1687 out_insnp->opcode |= regno << 12; 1688 continue; 1689 } 1690 1691 case 'f': 1692 /* Flags from the condition code register. */ 1693 { 1694 int flags = 0; 1695 1696 if (! get_flags (&s, &flags)) 1697 break; 1698 1699 out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf); 1700 continue; 1701 } 1702 1703 case 'i': 1704 /* A 6-bit signed immediate in bits <5:0>. */ 1705 if (! cris_get_expression (&s, &out_insnp->expr)) 1706 break; 1707 else 1708 { 1709 if (out_insnp->expr.X_op == O_constant 1710 && (out_insnp->expr.X_add_number < -32 1711 || out_insnp->expr.X_add_number > 31)) 1712 as_bad (_("Immediate value not in 6 bit range: %ld"), 1713 out_insnp->expr.X_add_number); 1714 out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6; 1715 continue; 1716 } 1717 1718 case 'I': 1719 /* A 6-bit unsigned immediate in bits <5:0>. */ 1720 if (! cris_get_expression (&s, &out_insnp->expr)) 1721 break; 1722 else 1723 { 1724 if (out_insnp->expr.X_op == O_constant 1725 && (out_insnp->expr.X_add_number < 0 1726 || out_insnp->expr.X_add_number > 63)) 1727 as_bad (_("Immediate value not in 6 bit unsigned range: %ld"), 1728 out_insnp->expr.X_add_number); 1729 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6; 1730 continue; 1731 } 1732 1733 case 'M': 1734 /* A size modifier, B, W or D, to be put in a bit position 1735 suitable for CLEAR instructions (i.e. reflecting a zero 1736 register). */ 1737 if (! get_bwd_size_modifier (&s, &size_bits)) 1738 break; 1739 else 1740 { 1741 switch (size_bits) 1742 { 1743 case 0: 1744 out_insnp->opcode |= 0 << 12; 1745 break; 1746 1747 case 1: 1748 out_insnp->opcode |= 4 << 12; 1749 break; 1750 1751 case 2: 1752 out_insnp->opcode |= 8 << 12; 1753 break; 1754 } 1755 continue; 1756 } 1757 1758 case 'm': 1759 /* A size modifier, B, W or D, to be put in bits <5:4>. */ 1760 if (modified_char != '.' 1761 || ! get_bwd_size_modifier (&s, &size_bits)) 1762 break; 1763 else 1764 { 1765 out_insnp->opcode |= size_bits << 4; 1766 continue; 1767 } 1768 1769 case 'o': 1770 /* A branch expression. */ 1771 if (! cris_get_expression (&s, &out_insnp->expr)) 1772 break; 1773 else 1774 { 1775 out_insnp->insn_type = CRIS_INSN_BRANCH; 1776 continue; 1777 } 1778 1779 case 'Q': 1780 /* A 8-bit quick BDAP expression, "expr,R". */ 1781 if (! cris_get_expression (&s, &out_insnp->expr)) 1782 break; 1783 1784 if (*s != ',') 1785 break; 1786 1787 s++; 1788 1789 if (!get_gen_reg (&s, ®no)) 1790 break; 1791 1792 out_insnp->opcode |= regno << 12; 1793 out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8; 1794 continue; 1795 1796 case 'O': 1797 /* A BDAP expression for any size, "expr,R". */ 1798 if (! cris_get_expression (&s, &prefixp->expr)) 1799 break; 1800 else 1801 { 1802 if (*s != ',') 1803 break; 1804 1805 s++; 1806 1807 if (!get_gen_reg (&s, &prefixp->base_reg_number)) 1808 break; 1809 1810 /* Since 'O' is used with an explicit bdap, we have no 1811 "real" instruction. */ 1812 prefixp->kind = PREFIX_BDAP_IMM; 1813 prefixp->opcode 1814 = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12); 1815 1816 out_insnp->insn_type = CRIS_INSN_NONE; 1817 continue; 1818 } 1819 1820 case 'P': 1821 /* Special register in bits <15:12>. */ 1822 if (! get_spec_reg (&s, &out_insnp->spec_reg)) 1823 break; 1824 else 1825 { 1826 /* Use of some special register names come with a 1827 specific warning. Note that we have no ".cpu type" 1828 pseudo yet, so some of this is just unused 1829 framework. */ 1830 if (out_insnp->spec_reg->warning) 1831 as_warn ("%s", out_insnp->spec_reg->warning); 1832 else if (out_insnp->spec_reg->applicable_version 1833 == cris_ver_warning) 1834 /* Others have a generic warning. */ 1835 as_warn (_("Unimplemented register `%s' specified"), 1836 out_insnp->spec_reg->name); 1837 1838 out_insnp->opcode 1839 |= out_insnp->spec_reg->number << 12; 1840 continue; 1841 } 1842 1843 case 'p': 1844 /* This character is used in the disassembler to 1845 recognize a prefix instruction to fold into the 1846 addressing mode for the next instruction. It is 1847 ignored here. */ 1848 continue; 1849 1850 case 'R': 1851 /* General register in bits <15:12>. */ 1852 if (! get_gen_reg (&s, ®no)) 1853 break; 1854 else 1855 { 1856 out_insnp->opcode |= regno << 12; 1857 continue; 1858 } 1859 1860 case 'r': 1861 /* General register in bits <3:0>. */ 1862 if (! get_gen_reg (&s, ®no)) 1863 break; 1864 else 1865 { 1866 out_insnp->opcode |= regno /* << 0 */; 1867 continue; 1868 } 1869 1870 case 'S': 1871 /* Source operand in bit <10> and a prefix; a 3-operand 1872 prefix. */ 1873 if (! get_3op_or_dip_prefix_op (&s, prefixp)) 1874 break; 1875 else 1876 continue; 1877 1878 case 's': 1879 /* Source operand in bits <10>, <3:0> and optionally a 1880 prefix; i.e. an indirect operand or an side-effect 1881 prefix (where valid). */ 1882 if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode, 1883 ®no, 1884 &imm_expr_found, 1885 &out_insnp->expr)) 1886 break; 1887 else 1888 { 1889 if (prefixp->kind != PREFIX_NONE) 1890 { 1891 /* A prefix, so it has the autoincrement bit 1892 set. */ 1893 out_insnp->opcode |= (AUTOINCR_BIT << 8); 1894 } 1895 else 1896 { 1897 /* No prefix. The "mode" variable contains bits like 1898 whether or not this is autoincrement mode. */ 1899 out_insnp->opcode |= (mode << 10); 1900 1901 /* If there was a reloc specifier, then it was 1902 attached to the prefix. Note that we can't check 1903 that the reloc size matches, since we don't have 1904 all the operands yet in all cases. */ 1905 if (prefixp->reloc != BFD_RELOC_NONE) 1906 out_insnp->reloc = prefixp->reloc; 1907 } 1908 1909 out_insnp->opcode |= regno /* << 0 */ ; 1910 continue; 1911 } 1912 1913 case 'N': 1914 case 'Y': 1915 /* Like 's', but immediate operand only. Also do not 1916 modify insn. There are no insns where an explicit reloc 1917 specifier makes sense. */ 1918 if (cris_get_expression (&s, &out_insnp->expr)) 1919 { 1920 imm_expr_found = 1; 1921 continue; 1922 } 1923 break; 1924 1925 case 'n': 1926 /* Like 'N', but PC-relative to the start of the insn. 1927 There might be a :PLT to request a PLT entry. */ 1928 if (cris_get_expression (&s, &out_insnp->expr)) 1929 { 1930 imm_expr_found = 1; 1931 out_insnp->reloc = BFD_RELOC_32_PCREL; 1932 1933 /* We have to adjust the expression, because that 1934 relocation is to the location *after* the 1935 relocation. So add 2 for the insn and 4 for the 1936 relocation. */ 1937 out_insnp->expr.X_add_number += 6; 1938 1939 /* TLS specifiers do not make sense here. */ 1940 if (pic && *s == RELOC_SUFFIX_CHAR) 1941 cris_get_reloc_suffix (&s, &out_insnp->reloc, 1942 &out_insnp->expr); 1943 1944 continue; 1945 } 1946 break; 1947 1948 case 'U': 1949 /* Maybe 'u', maybe 'n'. Only for LAPC/LAPCQ. */ 1950 if (cris_get_expression (&s, &out_insnp->expr)) 1951 { 1952 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; 1953 1954 /* Define 1 as relaxing. */ 1955 out_insnp->expr.X_md = 1; 1956 continue; 1957 } 1958 break; 1959 1960 case 'u': 1961 /* Four PC-relative bits in <3:0> representing <4:1>:0 of 1962 an offset relative to the beginning of the current 1963 insn. */ 1964 if (cris_get_expression (&s, &out_insnp->expr)) 1965 { 1966 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET; 1967 1968 /* Define 0 as non-relaxing. */ 1969 out_insnp->expr.X_md = 0; 1970 1971 /* We have to adjust the expression, because that 1972 relocation is to the location *after* the 1973 insn. So add 2 for the insn. */ 1974 out_insnp->expr.X_add_number += 2; 1975 continue; 1976 } 1977 break; 1978 1979 case 'x': 1980 /* Rs.m in bits <15:12> and <5:4>. */ 1981 if (! get_gen_reg (&s, ®no) 1982 || ! get_bwd_size_modifier (&s, &size_bits)) 1983 break; 1984 else 1985 { 1986 out_insnp->opcode |= (regno << 12) | (size_bits << 4); 1987 continue; 1988 } 1989 1990 case 'y': 1991 /* Source operand in bits <10>, <3:0> and optionally a 1992 prefix; i.e. an indirect operand or an side-effect 1993 prefix. 1994 1995 The difference to 's' is that this does not allow an 1996 "immediate" expression. */ 1997 if (! get_autoinc_prefix_or_indir_op (&s, prefixp, 1998 &mode, ®no, 1999 &imm_expr_found, 2000 &out_insnp->expr) 2001 || imm_expr_found) 2002 break; 2003 else 2004 { 2005 if (prefixp->kind != PREFIX_NONE) 2006 { 2007 /* A prefix, and those matched here always have 2008 side-effects (see 's' case). */ 2009 out_insnp->opcode |= (AUTOINCR_BIT << 8); 2010 } 2011 else 2012 { 2013 /* No prefix. The "mode" variable contains bits 2014 like whether or not this is autoincrement 2015 mode. */ 2016 out_insnp->opcode |= (mode << 10); 2017 } 2018 2019 out_insnp->opcode |= regno /* << 0 */; 2020 continue; 2021 } 2022 2023 case 'z': 2024 /* Size modifier (B or W) in bit <4>. */ 2025 if (! get_bw_size_modifier (&s, &size_bits)) 2026 break; 2027 else 2028 { 2029 out_insnp->opcode |= size_bits << 4; 2030 continue; 2031 } 2032 2033 case 'T': 2034 if (cris_arch == arch_crisv32 2035 && get_sup_reg (&s, ®no)) 2036 { 2037 out_insnp->opcode |= regno << 12; 2038 continue; 2039 } 2040 break; 2041 2042 default: 2043 BAD_CASE (*args); 2044 } 2045 2046 /* We get here when we fail a match above or we found a 2047 complete match. Break out of this loop. */ 2048 break; 2049 } 2050 2051 /* Was it a match or a miss? */ 2052 if (match == 0) 2053 { 2054 /* If it's just that the args don't match, maybe the next 2055 item in the table is the same opcode but with 2056 matching operands. First skip any invalid ones. */ 2057 while (instruction[1].name != NULL 2058 && strcmp (instruction->name, instruction[1].name) == 0 2059 && ! cris_insn_ver_valid_for_arch (instruction[1] 2060 .applicable_version, 2061 cris_arch)) 2062 ++instruction; 2063 2064 if (instruction[1].name != NULL 2065 && strcmp (instruction->name, instruction[1].name) == 0 2066 && cris_insn_ver_valid_for_arch (instruction[1] 2067 .applicable_version, 2068 cris_arch)) 2069 { 2070 /* Yep. Restart and try that one instead. */ 2071 ++instruction; 2072 s = operands; 2073 continue; 2074 } 2075 else 2076 { 2077 /* We've come to the end of instructions with this 2078 opcode, so it must be an error. */ 2079 as_bad (_("Illegal operands")); 2080 2081 /* As discard_rest_of_line, but without continuing to the 2082 next line. */ 2083 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 2084 input_line_pointer++; 2085 return; 2086 } 2087 } 2088 else 2089 { 2090 /* We have a match. Check if there's anything more to do. */ 2091 if (imm_expr_found) 2092 { 2093 /* There was an immediate mode operand, so we must check 2094 that it has an appropriate size. */ 2095 switch (instruction->imm_oprnd_size) 2096 { 2097 default: 2098 case SIZE_NONE: 2099 /* Shouldn't happen; this one does not have immediate 2100 operands with different sizes. */ 2101 BAD_CASE (instruction->imm_oprnd_size); 2102 break; 2103 2104 case SIZE_FIX_32: 2105 out_insnp->imm_oprnd_size = 4; 2106 break; 2107 2108 case SIZE_SPEC_REG: 2109 if (cris_arch == arch_crisv32) 2110 /* All immediate loads of special registers are 2111 32-bit on CRISv32. */ 2112 out_insnp->imm_oprnd_size = 4; 2113 else 2114 switch (out_insnp->spec_reg->reg_size) 2115 { 2116 case 1: 2117 if (out_insnp->expr.X_op == O_constant 2118 && (out_insnp->expr.X_add_number < -128 2119 || out_insnp->expr.X_add_number > 255)) 2120 as_bad (_("Immediate value not in 8 bit range: %ld"), 2121 out_insnp->expr.X_add_number); 2122 /* Fall through. */ 2123 case 2: 2124 /* FIXME: We need an indicator in the instruction 2125 table to pass on, to indicate if we need to check 2126 overflow for a signed or unsigned number. */ 2127 if (out_insnp->expr.X_op == O_constant 2128 && (out_insnp->expr.X_add_number < -32768 2129 || out_insnp->expr.X_add_number > 65535)) 2130 as_bad (_("Immediate value not in 16 bit range: %ld"), 2131 out_insnp->expr.X_add_number); 2132 out_insnp->imm_oprnd_size = 2; 2133 break; 2134 2135 case 4: 2136 out_insnp->imm_oprnd_size = 4; 2137 break; 2138 2139 default: 2140 BAD_CASE (out_insnp->spec_reg->reg_size); 2141 } 2142 break; 2143 2144 case SIZE_FIELD: 2145 case SIZE_FIELD_SIGNED: 2146 case SIZE_FIELD_UNSIGNED: 2147 switch (size_bits) 2148 { 2149 /* FIXME: Find way to pass un/signedness to 2150 caller, and set reloc type instead, postponing 2151 this check until cris_number_to_imm. That 2152 necessarily corrects the reloc type for the 2153 byte case, maybe requiring further changes. */ 2154 case 0: 2155 if (out_insnp->expr.X_op == O_constant) 2156 { 2157 if (instruction->imm_oprnd_size == SIZE_FIELD 2158 && (out_insnp->expr.X_add_number < -128 2159 || out_insnp->expr.X_add_number > 255)) 2160 as_bad (_("Immediate value not in 8 bit range: %ld"), 2161 out_insnp->expr.X_add_number); 2162 else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED 2163 && (out_insnp->expr.X_add_number < -128 2164 || out_insnp->expr.X_add_number > 127)) 2165 as_bad (_("Immediate value not in 8 bit signed range: %ld"), 2166 out_insnp->expr.X_add_number); 2167 else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED 2168 && (out_insnp->expr.X_add_number < 0 2169 || out_insnp->expr.X_add_number > 255)) 2170 as_bad (_("Immediate value not in 8 bit unsigned range: %ld"), 2171 out_insnp->expr.X_add_number); 2172 } 2173 2174 /* Fall through. */ 2175 case 1: 2176 if (out_insnp->expr.X_op == O_constant) 2177 { 2178 if (instruction->imm_oprnd_size == SIZE_FIELD 2179 && (out_insnp->expr.X_add_number < -32768 2180 || out_insnp->expr.X_add_number > 65535)) 2181 as_bad (_("Immediate value not in 16 bit range: %ld"), 2182 out_insnp->expr.X_add_number); 2183 else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED 2184 && (out_insnp->expr.X_add_number < -32768 2185 || out_insnp->expr.X_add_number > 32767)) 2186 as_bad (_("Immediate value not in 16 bit signed range: %ld"), 2187 out_insnp->expr.X_add_number); 2188 else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED 2189 && (out_insnp->expr.X_add_number < 0 2190 || out_insnp->expr.X_add_number > 65535)) 2191 as_bad (_("Immediate value not in 16 bit unsigned range: %ld"), 2192 out_insnp->expr.X_add_number); 2193 } 2194 out_insnp->imm_oprnd_size = 2; 2195 break; 2196 2197 case 2: 2198 out_insnp->imm_oprnd_size = 4; 2199 break; 2200 2201 default: 2202 BAD_CASE (out_insnp->spec_reg->reg_size); 2203 } 2204 } 2205 2206 /* If there was a relocation specified for the immediate 2207 expression (i.e. it had a PIC or TLS modifier) check that the 2208 size of the relocation matches the size specified by 2209 the opcode. */ 2210 if (out_insnp->reloc != BFD_RELOC_NONE 2211 && (cris_get_specified_reloc_size (out_insnp->reloc) 2212 != (unsigned int) out_insnp->imm_oprnd_size)) 2213 as_bad (out_insnp->reloc == BFD_RELOC_CRIS_32_GD 2214 || out_insnp->reloc == BFD_RELOC_CRIS_32_TPREL 2215 || out_insnp->reloc == BFD_RELOC_CRIS_16_TPREL 2216 || out_insnp->reloc == BFD_RELOC_CRIS_32_IE 2217 ? _("TLS relocation size does not match operand size") 2218 : _("PIC relocation size does not match operand size")); 2219 } 2220 else if (instruction->op == cris_muls_op 2221 || instruction->op == cris_mulu_op) 2222 out_insnp->insn_type = CRIS_INSN_MUL; 2223 } 2224 break; 2225 } 2226 } 2227 2228 /* Get a B, W, or D size modifier from the string pointed out by *cPP, 2229 which must point to a '.' in front of the modifier. On successful 2230 return, *cPP is advanced to the character following the size 2231 modifier, and is undefined otherwise. 2232 2233 cPP Pointer to pointer to string starting 2234 with the size modifier. 2235 2236 size_bitsp Pointer to variable to contain the size bits on 2237 successful return. 2238 2239 Return 1 iff a correct size modifier is found, else 0. */ 2240 2241 static int 2242 get_bwd_size_modifier (char **cPP, int *size_bitsp) 2243 { 2244 if (**cPP != '.') 2245 return 0; 2246 else 2247 { 2248 /* Consume the '.'. */ 2249 (*cPP)++; 2250 2251 switch (**cPP) 2252 { 2253 case 'B': 2254 case 'b': 2255 *size_bitsp = 0; 2256 break; 2257 2258 case 'W': 2259 case 'w': 2260 *size_bitsp = 1; 2261 break; 2262 2263 case 'D': 2264 case 'd': 2265 *size_bitsp = 2; 2266 break; 2267 2268 default: 2269 return 0; 2270 } 2271 2272 /* Consume the size letter. */ 2273 (*cPP)++; 2274 return 1; 2275 } 2276 } 2277 2278 /* Get a B or W size modifier from the string pointed out by *cPP, 2279 which must point to a '.' in front of the modifier. On successful 2280 return, *cPP is advanced to the character following the size 2281 modifier, and is undefined otherwise. 2282 2283 cPP Pointer to pointer to string starting 2284 with the size modifier. 2285 2286 size_bitsp Pointer to variable to contain the size bits on 2287 successful return. 2288 2289 Return 1 iff a correct size modifier is found, else 0. */ 2290 2291 static int 2292 get_bw_size_modifier (char **cPP, int *size_bitsp) 2293 { 2294 if (**cPP != '.') 2295 return 0; 2296 else 2297 { 2298 /* Consume the '.'. */ 2299 (*cPP)++; 2300 2301 switch (**cPP) 2302 { 2303 case 'B': 2304 case 'b': 2305 *size_bitsp = 0; 2306 break; 2307 2308 case 'W': 2309 case 'w': 2310 *size_bitsp = 1; 2311 break; 2312 2313 default: 2314 return 0; 2315 } 2316 2317 /* Consume the size letter. */ 2318 (*cPP)++; 2319 return 1; 2320 } 2321 } 2322 2323 /* Get a general register from the string pointed out by *cPP. The 2324 variable *cPP is advanced to the character following the general 2325 register name on a successful return, and has its initial position 2326 otherwise. 2327 2328 cPP Pointer to pointer to string, beginning with a general 2329 register name. 2330 2331 regnop Pointer to int containing the register number. 2332 2333 Return 1 iff a correct general register designator is found, 2334 else 0. */ 2335 2336 static int 2337 get_gen_reg (char **cPP, int *regnop) 2338 { 2339 char *oldp; 2340 oldp = *cPP; 2341 2342 /* Handle a sometimes-mandatory dollar sign as register prefix. */ 2343 if (**cPP == REGISTER_PREFIX_CHAR) 2344 (*cPP)++; 2345 else if (demand_register_prefix) 2346 return 0; 2347 2348 switch (**cPP) 2349 { 2350 case 'P': 2351 case 'p': 2352 /* "P" as in "PC"? Consume the "P". */ 2353 (*cPP)++; 2354 2355 if ((**cPP == 'C' || **cPP == 'c') 2356 && ! ISALNUM ((*cPP)[1]) 2357 /* Here's a little twist: For v32 and the compatibility mode, 2358 we only recognize PC as a register number if there's '+]' 2359 after. We don't consume that, but the presence can only be 2360 valid after a register in a post-increment context, which 2361 is also the only valid context for PC as a register for 2362 v32. Not that it's used very often, but saying "MOVE.D 2363 [PC+],R5" should remain valid. It's not supported for 2364 jump-type insns or other insns with no [Rn+] mode, though. */ 2365 && ((cris_arch != arch_crisv32 2366 && cris_arch != arch_cris_common_v10_v32) 2367 || ((*cPP)[1] == '+' && (*cPP)[2] == ']'))) 2368 { 2369 /* It's "PC": consume the "c" and we're done. */ 2370 (*cPP)++; 2371 *regnop = REG_PC; 2372 return 1; 2373 } 2374 break; 2375 2376 /* Like with PC, we recognize ACR, but only if it's *not* followed 2377 by '+', and only for v32. */ 2378 case 'A': 2379 case 'a': 2380 if (cris_arch != arch_crisv32 2381 || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C') 2382 || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R') 2383 || ISALNUM ((*cPP)[3]) 2384 || (*cPP)[3] == '+') 2385 break; 2386 (*cPP) += 3; 2387 *regnop = 15; 2388 return 1; 2389 2390 case 'R': 2391 case 'r': 2392 /* Hopefully r[0-9] or r1[0-5]. Consume 'R' or 'r'. */ 2393 (*cPP)++; 2394 2395 if (ISDIGIT (**cPP)) 2396 { 2397 /* It's r[0-9]. Consume and check the next digit. */ 2398 *regnop = **cPP - '0'; 2399 (*cPP)++; 2400 2401 if (! ISALNUM (**cPP)) 2402 { 2403 /* No more digits, we're done. */ 2404 return 1; 2405 } 2406 else 2407 { 2408 /* One more digit. Consume and add. */ 2409 *regnop = *regnop * 10 + (**cPP - '0'); 2410 2411 /* We need to check for a valid register number; Rn, 2412 0 <= n <= MAX_REG. */ 2413 if (*regnop <= MAX_REG) 2414 { 2415 /* Consume second digit. */ 2416 (*cPP)++; 2417 return 1; 2418 } 2419 } 2420 } 2421 break; 2422 2423 case 'S': 2424 case 's': 2425 /* "S" as in "SP"? Consume the "S". */ 2426 (*cPP)++; 2427 if (**cPP == 'P' || **cPP == 'p') 2428 { 2429 /* It's "SP": consume the "p" and we're done. */ 2430 (*cPP)++; 2431 *regnop = REG_SP; 2432 return 1; 2433 } 2434 break; 2435 2436 default: 2437 /* Just here to silence compilation warnings. */ 2438 ; 2439 } 2440 2441 /* We get here if we fail. Restore the pointer. */ 2442 *cPP = oldp; 2443 return 0; 2444 } 2445 2446 /* Get a special register from the string pointed out by *cPP. The 2447 variable *cPP is advanced to the character following the special 2448 register name if one is found, and retains its original position 2449 otherwise. 2450 2451 cPP Pointer to pointer to string starting with a special register 2452 name. 2453 2454 sregpp Pointer to Pointer to struct spec_reg, where a pointer to the 2455 register description will be stored. 2456 2457 Return 1 iff a correct special register name is found. */ 2458 2459 static int 2460 get_spec_reg (char **cPP, const struct cris_spec_reg **sregpp) 2461 { 2462 char *s1; 2463 const char *s2; 2464 char *name_begin = *cPP; 2465 2466 const struct cris_spec_reg *sregp; 2467 2468 /* Handle a sometimes-mandatory dollar sign as register prefix. */ 2469 if (*name_begin == REGISTER_PREFIX_CHAR) 2470 name_begin++; 2471 else if (demand_register_prefix) 2472 return 0; 2473 2474 /* Loop over all special registers. */ 2475 for (sregp = cris_spec_regs; sregp->name != NULL; sregp++) 2476 { 2477 /* Start over from beginning of the supposed name. */ 2478 s1 = name_begin; 2479 s2 = sregp->name; 2480 2481 while (*s2 != '\0' && TOLOWER (*s1) == *s2) 2482 { 2483 s1++; 2484 s2++; 2485 } 2486 2487 /* For a match, we must have consumed the name in the table, and we 2488 must be outside what could be part of a name. Assume here that a 2489 test for alphanumerics is sufficient for a name test. */ 2490 if (*s2 == 0 && ! ISALNUM (*s1) 2491 && cris_insn_ver_valid_for_arch (sregp->applicable_version, 2492 cris_arch)) 2493 { 2494 /* We have a match. Update the pointer and be done. */ 2495 *cPP = s1; 2496 *sregpp = sregp; 2497 return 1; 2498 } 2499 } 2500 2501 /* If we got here, we did not find any name. */ 2502 return 0; 2503 } 2504 2505 /* Get a support register from the string pointed out by *cPP. The 2506 variable *cPP is advanced to the character following the support- 2507 register name if one is found, and retains its original position 2508 otherwise. 2509 2510 cPP Pointer to pointer to string starting with a support-register 2511 name. 2512 2513 sregpp Pointer to int containing the register number. 2514 2515 Return 1 iff a correct support-register name is found. */ 2516 2517 static int 2518 get_sup_reg (char **cPP, int *regnop) 2519 { 2520 char *s1; 2521 const char *s2; 2522 char *name_begin = *cPP; 2523 2524 const struct cris_support_reg *sregp; 2525 2526 /* Handle a sometimes-mandatory dollar sign as register prefix. */ 2527 if (*name_begin == REGISTER_PREFIX_CHAR) 2528 name_begin++; 2529 else if (demand_register_prefix) 2530 return 0; 2531 2532 /* Loop over all support-registers. */ 2533 for (sregp = cris_support_regs; sregp->name != NULL; sregp++) 2534 { 2535 /* Start over from beginning of the supposed name. */ 2536 s1 = name_begin; 2537 s2 = sregp->name; 2538 2539 while (*s2 != '\0' && TOLOWER (*s1) == *s2) 2540 { 2541 s1++; 2542 s2++; 2543 } 2544 2545 /* For a match, we must have consumed the name in the table, and we 2546 must be outside what could be part of a name. Assume here that a 2547 test for alphanumerics is sufficient for a name test. */ 2548 if (*s2 == 0 && ! ISALNUM (*s1)) 2549 { 2550 /* We have a match. Update the pointer and be done. */ 2551 *cPP = s1; 2552 *regnop = sregp->number; 2553 return 1; 2554 } 2555 } 2556 2557 /* If we got here, we did not find any name. */ 2558 return 0; 2559 } 2560 2561 /* Get an unprefixed or side-effect-prefix operand from the string pointed 2562 out by *cPP. The pointer *cPP is advanced to the character following 2563 the indirect operand if we have success, else it contains an undefined 2564 value. 2565 2566 cPP Pointer to pointer to string beginning with the first 2567 character of the supposed operand. 2568 2569 prefixp Pointer to structure containing an optional instruction 2570 prefix. 2571 2572 is_autoincp Pointer to int indicating the indirect or autoincrement 2573 bits. 2574 2575 src_regnop Pointer to int containing the source register number in 2576 the instruction. 2577 2578 imm_foundp Pointer to an int indicating if an immediate expression 2579 is found. 2580 2581 imm_exprP Pointer to a structure containing an immediate 2582 expression, if success and if *imm_foundp is nonzero. 2583 2584 Return 1 iff a correct indirect operand is found. */ 2585 2586 static int 2587 get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp, 2588 int *is_autoincp, int *src_regnop, 2589 int *imm_foundp, expressionS *imm_exprP) 2590 { 2591 /* Assume there was no immediate mode expression. */ 2592 *imm_foundp = 0; 2593 2594 if (**cPP == '[') 2595 { 2596 /* So this operand is one of: 2597 Indirect: [rN] 2598 Autoincrement: [rN+] 2599 Indexed with assign: [rN=rM+rO.S] 2600 Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s] 2601 2602 Either way, consume the '['. */ 2603 (*cPP)++; 2604 2605 /* Get the rN register. */ 2606 if (! get_gen_reg (cPP, src_regnop)) 2607 /* If there was no register, then this cannot match. */ 2608 return 0; 2609 else 2610 { 2611 /* We got the register, now check the next character. */ 2612 switch (**cPP) 2613 { 2614 case ']': 2615 /* Indirect mode. We're done here. */ 2616 prefixp->kind = PREFIX_NONE; 2617 *is_autoincp = 0; 2618 break; 2619 2620 case '+': 2621 /* This must be an auto-increment mode, if there's a 2622 match. */ 2623 prefixp->kind = PREFIX_NONE; 2624 *is_autoincp = 1; 2625 2626 /* We consume this character and break out to check the 2627 closing ']'. */ 2628 (*cPP)++; 2629 break; 2630 2631 case '=': 2632 /* This must be indexed with assign, or offset with assign 2633 to match. Not supported for crisv32 or in 2634 compatibility mode. */ 2635 if (cris_arch == arch_crisv32 2636 || cris_arch == arch_cris_common_v10_v32) 2637 return 0; 2638 2639 (*cPP)++; 2640 2641 /* Either way, the next thing must be a register. */ 2642 if (! get_gen_reg (cPP, &prefixp->base_reg_number)) 2643 /* No register, no match. */ 2644 return 0; 2645 else 2646 { 2647 /* We've consumed "[rN=rM", so we must be looking at 2648 "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or 2649 "+[rO+].s]". */ 2650 if (**cPP == '+') 2651 { 2652 int index_reg_number; 2653 (*cPP)++; 2654 2655 if (**cPP == '[') 2656 { 2657 int size_bits; 2658 /* This must be [rx=ry+[rz].s] or 2659 [rx=ry+[rz+].s] or no match. We must be 2660 looking at rz after consuming the '['. */ 2661 (*cPP)++; 2662 2663 if (!get_gen_reg (cPP, &index_reg_number)) 2664 return 0; 2665 2666 prefixp->kind = PREFIX_BDAP; 2667 prefixp->opcode 2668 = (BDAP_INDIR_OPCODE 2669 + (prefixp->base_reg_number << 12) 2670 + index_reg_number); 2671 2672 if (**cPP == '+') 2673 { 2674 /* We've seen "[rx=ry+[rz+" here, so now we 2675 know that there must be "].s]" left to 2676 check. */ 2677 (*cPP)++; 2678 prefixp->opcode |= AUTOINCR_BIT << 8; 2679 } 2680 2681 /* If it wasn't autoincrement, we don't need to 2682 add anything. */ 2683 2684 /* Check the next-to-last ']'. */ 2685 if (**cPP != ']') 2686 return 0; 2687 2688 (*cPP)++; 2689 2690 /* Check the ".s" modifier. */ 2691 if (! get_bwd_size_modifier (cPP, &size_bits)) 2692 return 0; 2693 2694 prefixp->opcode |= size_bits << 4; 2695 2696 /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s. 2697 We break out to check the final ']'. */ 2698 break; 2699 } 2700 /* It wasn't an indirection. Check if it's a 2701 register. */ 2702 else if (get_gen_reg (cPP, &index_reg_number)) 2703 { 2704 int size_bits; 2705 2706 /* Indexed with assign mode: "[rN+rM.S]". */ 2707 prefixp->kind = PREFIX_BIAP; 2708 prefixp->opcode 2709 = (BIAP_OPCODE + (index_reg_number << 12) 2710 + prefixp->base_reg_number /* << 0 */); 2711 2712 if (! get_bwd_size_modifier (cPP, &size_bits)) 2713 /* Size missing, this isn't a match. */ 2714 return 0; 2715 else 2716 { 2717 /* Size found, break out to check the 2718 final ']'. */ 2719 prefixp->opcode |= size_bits << 4; 2720 break; 2721 } 2722 } 2723 /* Not a register. Then this must be "[rN+I]". */ 2724 else if (cris_get_expression (cPP, &prefixp->expr)) 2725 { 2726 /* We've got offset with assign mode. Fill 2727 in the blanks and break out to match the 2728 final ']'. */ 2729 prefixp->kind = PREFIX_BDAP_IMM; 2730 2731 /* We tentatively put an opcode corresponding to 2732 a 32-bit operand here, although it may be 2733 relaxed when there's no relocation 2734 specifier for the operand. */ 2735 prefixp->opcode 2736 = (BDAP_INDIR_OPCODE 2737 | (prefixp->base_reg_number << 12) 2738 | (AUTOINCR_BIT << 8) 2739 | (2 << 4) 2740 | REG_PC /* << 0 */); 2741 2742 /* This can have a PIC suffix, specifying reloc 2743 type to use. */ 2744 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) 2745 { 2746 unsigned int relocsize; 2747 2748 cris_get_reloc_suffix (cPP, &prefixp->reloc, 2749 &prefixp->expr); 2750 2751 /* Tweak the size of the immediate operand 2752 in the prefix opcode if it isn't what we 2753 set. */ 2754 relocsize 2755 = cris_get_specified_reloc_size (prefixp->reloc); 2756 if (relocsize != 4) 2757 prefixp->opcode 2758 = ((prefixp->opcode & ~(3 << 4)) 2759 | ((relocsize >> 1) << 4)); 2760 } 2761 break; 2762 } 2763 else 2764 /* Neither register nor expression found, so 2765 this can't be a match. */ 2766 return 0; 2767 } 2768 /* Not "[rN+" but perhaps "[rN-"? */ 2769 else if (**cPP == '-') 2770 { 2771 /* We must have an offset with assign mode. */ 2772 if (! cris_get_expression (cPP, &prefixp->expr)) 2773 /* No expression, no match. */ 2774 return 0; 2775 else 2776 { 2777 /* We've got offset with assign mode. Fill 2778 in the blanks and break out to match the 2779 final ']'. 2780 2781 Note that we don't allow a relocation 2782 suffix for an operand with a minus 2783 sign. */ 2784 prefixp->kind = PREFIX_BDAP_IMM; 2785 break; 2786 } 2787 } 2788 else 2789 /* Neither '+' nor '-' after "[rN=rM". Lose. */ 2790 return 0; 2791 } 2792 default: 2793 /* Neither ']' nor '+' nor '=' after "[rN". Lose. */ 2794 return 0; 2795 } 2796 } 2797 2798 /* When we get here, we have a match and will just check the closing 2799 ']'. We can still fail though. */ 2800 if (**cPP != ']') 2801 return 0; 2802 else 2803 { 2804 /* Don't forget to consume the final ']'. 2805 Then return in glory. */ 2806 (*cPP)++; 2807 return 1; 2808 } 2809 } 2810 /* No indirection. Perhaps a constant? */ 2811 else if (cris_get_expression (cPP, imm_exprP)) 2812 { 2813 /* Expression found, this is immediate mode. */ 2814 prefixp->kind = PREFIX_NONE; 2815 *is_autoincp = 1; 2816 *src_regnop = REG_PC; 2817 *imm_foundp = 1; 2818 2819 /* This can have a PIC suffix, specifying reloc type to use. The 2820 caller must check that the reloc size matches the operand size. */ 2821 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) 2822 cris_get_reloc_suffix (cPP, &prefixp->reloc, imm_exprP); 2823 2824 return 1; 2825 } 2826 2827 /* No luck today. */ 2828 return 0; 2829 } 2830 2831 /* This function gets an indirect operand in a three-address operand 2832 combination from the string pointed out by *cPP. The pointer *cPP is 2833 advanced to the character following the indirect operand on success, or 2834 has an unspecified value on failure. 2835 2836 cPP Pointer to pointer to string beginning 2837 with the operand 2838 2839 prefixp Pointer to structure containing an 2840 instruction prefix 2841 2842 Returns 1 iff a correct indirect operand is found. */ 2843 2844 static int 2845 get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp) 2846 { 2847 int reg_number; 2848 2849 if (**cPP != '[') 2850 /* We must have a '[' or it's a clean failure. */ 2851 return 0; 2852 2853 /* Eat the first '['. */ 2854 (*cPP)++; 2855 2856 if (**cPP == '[') 2857 { 2858 /* A second '[', so this must be double-indirect mode. */ 2859 (*cPP)++; 2860 prefixp->kind = PREFIX_DIP; 2861 prefixp->opcode = DIP_OPCODE; 2862 2863 /* Get the register or fail entirely. */ 2864 if (! get_gen_reg (cPP, ®_number)) 2865 return 0; 2866 else 2867 { 2868 prefixp->opcode |= reg_number /* << 0 */ ; 2869 if (**cPP == '+') 2870 { 2871 /* Since we found a '+', this must be double-indirect 2872 autoincrement mode. */ 2873 (*cPP)++; 2874 prefixp->opcode |= AUTOINCR_BIT << 8; 2875 } 2876 2877 /* There's nothing particular to do, if this was a 2878 double-indirect *without* autoincrement. */ 2879 } 2880 2881 /* Check the first ']'. The second one is checked at the end. */ 2882 if (**cPP != ']') 2883 return 0; 2884 2885 /* Eat the first ']', so we'll be looking at a second ']'. */ 2886 (*cPP)++; 2887 } 2888 /* No second '['. Then we should have a register here, making 2889 it "[rN". */ 2890 else if (get_gen_reg (cPP, &prefixp->base_reg_number)) 2891 { 2892 /* This must be indexed or offset mode: "[rN+I]" or 2893 "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ 2894 if (**cPP == '+') 2895 { 2896 int index_reg_number; 2897 2898 (*cPP)++; 2899 2900 if (**cPP == '[') 2901 { 2902 /* This is "[rx+["... Expect a register next. */ 2903 int size_bits; 2904 (*cPP)++; 2905 2906 if (!get_gen_reg (cPP, &index_reg_number)) 2907 return 0; 2908 2909 prefixp->kind = PREFIX_BDAP; 2910 prefixp->opcode 2911 = (BDAP_INDIR_OPCODE 2912 + (prefixp->base_reg_number << 12) 2913 + index_reg_number); 2914 2915 /* We've seen "[rx+[ry", so check if this is 2916 autoincrement. */ 2917 if (**cPP == '+') 2918 { 2919 /* Yep, now at "[rx+[ry+". */ 2920 (*cPP)++; 2921 prefixp->opcode |= AUTOINCR_BIT << 8; 2922 } 2923 /* If it wasn't autoincrement, we don't need to 2924 add anything. */ 2925 2926 /* Check a first closing ']': "[rx+[ry]" or 2927 "[rx+[ry+]". */ 2928 if (**cPP != ']') 2929 return 0; 2930 (*cPP)++; 2931 2932 /* Now expect a size modifier ".S". */ 2933 if (! get_bwd_size_modifier (cPP, &size_bits)) 2934 return 0; 2935 2936 prefixp->opcode |= size_bits << 4; 2937 2938 /* Ok, all interesting stuff has been seen: 2939 "[rx+[ry+].S" or "[rx+[ry].S". We only need to 2940 expect a final ']', which we'll do in a common 2941 closing session. */ 2942 } 2943 /* Seen "[rN+", but not a '[', so check if we have a 2944 register. */ 2945 else if (get_gen_reg (cPP, &index_reg_number)) 2946 { 2947 /* This is indexed mode: "[rN+rM.S]" or 2948 "[rN+rM.S+]". */ 2949 int size_bits; 2950 prefixp->kind = PREFIX_BIAP; 2951 prefixp->opcode 2952 = (BIAP_OPCODE 2953 | prefixp->base_reg_number /* << 0 */ 2954 | (index_reg_number << 12)); 2955 2956 /* Consume the ".S". */ 2957 if (! get_bwd_size_modifier (cPP, &size_bits)) 2958 /* Missing size, so fail. */ 2959 return 0; 2960 else 2961 /* Size found. Add that piece and drop down to 2962 the common checking of the closing ']'. */ 2963 prefixp->opcode |= size_bits << 4; 2964 } 2965 /* Seen "[rN+", but not a '[' or a register, so then 2966 it must be a constant "I". 2967 2968 As a quality of implementation improvement, we check for a 2969 closing ']', like in an erroneous "[rN+]". If we don't, 2970 the expression parser will emit a confusing "bad 2971 expression" when it sees the ']', probably because it 2972 doesn't like seeing no expression. */ 2973 else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr)) 2974 { 2975 /* Expression found, so fill in the bits of offset 2976 mode and drop down to check the closing ']'. */ 2977 prefixp->kind = PREFIX_BDAP_IMM; 2978 2979 /* We tentatively put an opcode corresponding to a 32-bit 2980 operand here, although it may be relaxed when there's no 2981 PIC specifier for the operand. */ 2982 prefixp->opcode 2983 = (BDAP_INDIR_OPCODE 2984 | (prefixp->base_reg_number << 12) 2985 | (AUTOINCR_BIT << 8) 2986 | (2 << 4) 2987 | REG_PC /* << 0 */); 2988 2989 /* This can have a PIC suffix, specifying reloc type to use. */ 2990 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) 2991 { 2992 unsigned int relocsize; 2993 2994 cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr); 2995 2996 /* Tweak the size of the immediate operand in the prefix 2997 opcode if it isn't what we set. */ 2998 relocsize = cris_get_specified_reloc_size (prefixp->reloc); 2999 if (relocsize != 4) 3000 prefixp->opcode 3001 = ((prefixp->opcode & ~(3 << 4)) 3002 | ((relocsize >> 1) << 4)); 3003 } 3004 } 3005 else 3006 /* Nothing valid here: lose. */ 3007 return 0; 3008 } 3009 /* Seen "[rN" but no '+', so check if it's a '-'. */ 3010 else if (**cPP == '-') 3011 { 3012 /* Yep, we must have offset mode. */ 3013 if (! cris_get_expression (cPP, &prefixp->expr)) 3014 /* No expression, so we lose. */ 3015 return 0; 3016 else 3017 { 3018 /* Expression found to make this offset mode, so 3019 fill those bits and drop down to check the 3020 closing ']'. 3021 3022 Note that we don't allow a PIC suffix for 3023 an operand with a minus sign like this. */ 3024 prefixp->kind = PREFIX_BDAP_IMM; 3025 } 3026 } 3027 else 3028 { 3029 /* We've seen "[rN", but not '+' or '-'; rather a ']'. 3030 Hmm. Normally this is a simple indirect mode that we 3031 shouldn't match, but if we expect ']', then we have a 3032 zero offset, so it can be a three-address-operand, 3033 like "[rN],rO,rP", thus offset mode. 3034 3035 Don't eat the ']', that will be done in the closing 3036 ceremony. */ 3037 prefixp->expr.X_op = O_constant; 3038 prefixp->expr.X_add_number = 0; 3039 prefixp->expr.X_add_symbol = NULL; 3040 prefixp->expr.X_op_symbol = NULL; 3041 prefixp->kind = PREFIX_BDAP_IMM; 3042 } 3043 } 3044 /* A '[', but no second '[', and no register. Check if we 3045 have an expression, making this "[I]" for a double-indirect 3046 prefix. */ 3047 else if (cris_get_expression (cPP, &prefixp->expr)) 3048 { 3049 /* Expression found, the so called absolute mode for a 3050 double-indirect prefix on PC. */ 3051 prefixp->kind = PREFIX_DIP; 3052 prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC; 3053 prefixp->reloc = BFD_RELOC_32; 3054 3055 /* For :GD and :IE, it makes sense to have TLS specifiers here. */ 3056 if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR) 3057 cris_get_reloc_suffix (cPP, &prefixp->reloc, &prefixp->expr); 3058 } 3059 else 3060 /* Neither '[' nor register nor expression. We lose. */ 3061 return 0; 3062 3063 /* We get here as a closing ceremony to a successful match. We just 3064 need to check the closing ']'. */ 3065 if (**cPP != ']') 3066 /* Oops. Close but no air-polluter. */ 3067 return 0; 3068 3069 /* Don't forget to consume that ']', before returning in glory. */ 3070 (*cPP)++; 3071 return 1; 3072 } 3073 3074 /* Get an expression from the string pointed out by *cPP. 3075 The pointer *cPP is advanced to the character following the expression 3076 on a success, or retains its original value otherwise. 3077 3078 cPP Pointer to pointer to string beginning with the expression. 3079 3080 exprP Pointer to structure containing the expression. 3081 3082 Return 1 iff a correct expression is found. */ 3083 3084 static int 3085 cris_get_expression (char **cPP, expressionS *exprP) 3086 { 3087 char *saved_input_line_pointer; 3088 3089 /* The "expression" function expects to find an expression at the 3090 global variable input_line_pointer, so we have to save it to give 3091 the impression that we don't fiddle with global variables. */ 3092 saved_input_line_pointer = input_line_pointer; 3093 input_line_pointer = *cPP; 3094 3095 /* Avoid a common error, confusing addressing modes. Beware that the 3096 call to expression below does not signal that error; it treats [] 3097 as parentheses, unless #define NEED_INDEX_OPERATOR in which case it 3098 gives them other confusing semantics rather than plain outlawing 3099 them, which is what we want. */ 3100 if (*input_line_pointer == '[') 3101 { 3102 input_line_pointer = saved_input_line_pointer; 3103 return 0; 3104 } 3105 3106 expression (exprP); 3107 if (exprP->X_op == O_illegal || exprP->X_op == O_absent) 3108 { 3109 input_line_pointer = saved_input_line_pointer; 3110 return 0; 3111 } 3112 3113 /* Everything seems to be fine, just restore the global 3114 input_line_pointer and say we're successful. */ 3115 *cPP = input_line_pointer; 3116 input_line_pointer = saved_input_line_pointer; 3117 return 1; 3118 } 3119 3120 /* Get a sequence of flag characters from *spp. The pointer *cPP is 3121 advanced to the character following the expression. The flag 3122 characters are consecutive, no commas or spaces. 3123 3124 cPP Pointer to pointer to string beginning with the expression. 3125 3126 flagp Pointer to int to return the flags expression. 3127 3128 Return 1 iff a correct flags expression is found. */ 3129 3130 static int 3131 get_flags (char **cPP, int *flagsp) 3132 { 3133 for (;;) 3134 { 3135 switch (**cPP) 3136 { 3137 case 'd': 3138 case 'D': 3139 if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, 3140 cris_arch)) 3141 return 0; 3142 *flagsp |= 0x80; 3143 break; 3144 3145 case 'm': 3146 case 'M': 3147 if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, 3148 cris_arch)) 3149 return 0; 3150 *flagsp |= 0x80; 3151 break; 3152 3153 case 'e': 3154 case 'E': 3155 if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3, 3156 cris_arch)) 3157 return 0; 3158 *flagsp |= 0x40; 3159 break; 3160 3161 case 'b': 3162 case 'B': 3163 if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10, 3164 cris_arch)) 3165 return 0; 3166 *flagsp |= 0x40; 3167 break; 3168 3169 case 'p': 3170 case 'P': 3171 if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, 3172 cris_arch)) 3173 return 0; 3174 *flagsp |= 0x80; 3175 break; 3176 3177 case 'u': 3178 case 'U': 3179 if (! cris_insn_ver_valid_for_arch (cris_ver_v32p, 3180 cris_arch)) 3181 return 0; 3182 *flagsp |= 0x40; 3183 break; 3184 3185 case 'i': 3186 case 'I': 3187 *flagsp |= 0x20; 3188 break; 3189 3190 case 'x': 3191 case 'X': 3192 *flagsp |= 0x10; 3193 break; 3194 3195 case 'n': 3196 case 'N': 3197 *flagsp |= 0x8; 3198 break; 3199 3200 case 'z': 3201 case 'Z': 3202 *flagsp |= 0x4; 3203 break; 3204 3205 case 'v': 3206 case 'V': 3207 *flagsp |= 0x2; 3208 break; 3209 3210 case 'c': 3211 case 'C': 3212 *flagsp |= 1; 3213 break; 3214 3215 default: 3216 /* We consider this successful if we stop at a comma or 3217 whitespace. Anything else, and we consider it a failure. */ 3218 if (**cPP != ',' 3219 && **cPP != 0 3220 && ! ISSPACE (**cPP)) 3221 return 0; 3222 else 3223 return 1; 3224 } 3225 3226 /* Don't forget to consume each flag character. */ 3227 (*cPP)++; 3228 } 3229 } 3230 3231 /* Generate code and fixes for a BDAP prefix. 3232 For v32, this handles ADDOQ because thankfully the opcodes are the 3233 same. 3234 3235 base_regno Int containing the base register number. 3236 3237 exprP Pointer to structure containing the offset expression. */ 3238 3239 static void 3240 gen_bdap (int base_regno, expressionS *exprP) 3241 { 3242 unsigned int opcode; 3243 char *opcodep; 3244 3245 /* Put out the prefix opcode; assume quick immediate mode at first. */ 3246 opcode = BDAP_QUICK_OPCODE | (base_regno << 12); 3247 opcodep = cris_insn_first_word_frag (); 3248 md_number_to_chars (opcodep, opcode, 2); 3249 3250 if (exprP->X_op == O_constant) 3251 { 3252 /* We have an absolute expression that we know the size of right 3253 now. */ 3254 long int value; 3255 int size; 3256 3257 value = exprP->X_add_number; 3258 if (value < -32768 || value > 32767) 3259 /* Outside range for a "word", make it a dword. */ 3260 size = 2; 3261 else 3262 /* Assume "word" size. */ 3263 size = 1; 3264 3265 /* If this is a signed-byte value, we can fit it into the prefix 3266 insn itself. */ 3267 if (value >= -128 && value <= 127) 3268 opcodep[0] = value; 3269 else 3270 { 3271 /* This is a word or dword displacement, which will be put in a 3272 word or dword after the prefix. */ 3273 char *p; 3274 3275 opcodep[0] = BDAP_PC_LOW + (size << 4); 3276 opcodep[1] &= 0xF0; 3277 opcodep[1] |= BDAP_INCR_HIGH; 3278 p = frag_more (1 << size); 3279 md_number_to_chars (p, value, 1 << size); 3280 } 3281 } 3282 else 3283 { 3284 /* Handle complex expressions. */ 3285 valueT addvalue 3286 = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0; 3287 symbolS *sym 3288 = (SIMPLE_EXPR (exprP) 3289 ? exprP->X_add_symbol : make_expr_symbol (exprP)); 3290 3291 /* The expression is not defined yet but may become absolute. We 3292 make it a relocation to be relaxed. */ 3293 frag_var (rs_machine_dependent, 4, 0, 3294 ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF), 3295 sym, addvalue, opcodep); 3296 } 3297 } 3298 3299 /* Encode a branch displacement in the range -256..254 into the form used 3300 by CRIS conditional branch instructions. 3301 3302 offset The displacement value in bytes. */ 3303 3304 static int 3305 branch_disp (int offset) 3306 { 3307 int disp; 3308 3309 /* Adjust all short branch offsets here. */ 3310 if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32) 3311 offset += 2; 3312 3313 disp = offset & 0xFE; 3314 3315 if (offset < 0) 3316 disp |= 1; 3317 3318 return disp; 3319 } 3320 3321 /* Generate code and fixes for a 32-bit conditional branch instruction 3322 created by "extending" an existing 8-bit branch instruction. 3323 3324 opcodep Pointer to the word containing the original 8-bit branch 3325 instruction. 3326 3327 writep Pointer to "extension area" following the first instruction 3328 word. 3329 3330 fragP Pointer to the frag containing the instruction. 3331 3332 add_symP, Parts of the destination address expression. 3333 sub_symP, 3334 add_num. */ 3335 3336 static void 3337 gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP, 3338 symbolS *add_symP, symbolS *sub_symP, long int add_num) 3339 { 3340 int nop_opcode; 3341 int opc_offset; 3342 int branch_offset; 3343 3344 if (cris_arch == arch_crisv32) 3345 { 3346 nop_opcode = NOP_OPCODE_V32; 3347 opc_offset = 10; 3348 branch_offset = -2 - 8; 3349 } 3350 else if (pic) 3351 { 3352 nop_opcode = NOP_OPCODE; 3353 opc_offset = 10; 3354 branch_offset = -2 - 8; 3355 } 3356 else 3357 { 3358 nop_opcode = NOP_OPCODE; 3359 opc_offset = 8; 3360 branch_offset = -2 - 6; 3361 } 3362 3363 /* We should never get here for compatibility mode. */ 3364 if (cris_arch == arch_cris_common_v10_v32) 3365 as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n")); 3366 3367 if (warn_for_branch_expansion) 3368 as_warn_where (fragP->fr_file, fragP->fr_line, 3369 _("32-bit conditional branch generated")); 3370 3371 /* Here, writep points to what will be opcodep + 2. First, we change 3372 the actual branch in opcodep[0] and opcodep[1], so that in the 3373 final insn, it will look like: 3374 opcodep+10: Bcc .-6 3375 3376 This means we don't have to worry about changing the opcode or 3377 messing with the delay-slot instruction. So, we move it to last in 3378 the "extended" branch, and just change the displacement. Admittedly, 3379 it's not the optimal extended construct, but we should get this 3380 rarely enough that it shouldn't matter. */ 3381 3382 writep[opc_offset] = branch_disp (branch_offset); 3383 writep[opc_offset + 1] = opcodep[1]; 3384 3385 /* Then, we change the branch to an unconditional branch over the 3386 extended part, to the new location of the Bcc: 3387 opcodep: BA .+10 3388 opcodep+2: NOP 3389 3390 Note that these two writes are to currently different locations, 3391 merged later. */ 3392 3393 md_number_to_chars (opcodep, BA_QUICK_OPCODE 3394 + (cris_arch == arch_crisv32 ? 12 : (pic ? 10 : 8)), 3395 2); 3396 md_number_to_chars (writep, nop_opcode, 2); 3397 3398 /* Then the extended thing, the 32-bit jump insn. 3399 opcodep+4: JUMP [PC+] 3400 or, in the PIC case, 3401 opcodep+4: MOVE [PC=PC+N],P0. */ 3402 3403 md_number_to_chars (writep + 2, 3404 cris_arch == arch_crisv32 3405 ? BA_DWORD_OPCODE 3406 : (pic ? MOVE_PC_INCR_OPCODE_PREFIX 3407 : JUMP_PC_INCR_OPCODE), 2); 3408 3409 /* We have to fill in the actual value too. 3410 opcodep+6: .DWORD 3411 This is most probably an expression, but we can cope with an absolute 3412 value too. FIXME: Testcase needed with and without pic. */ 3413 3414 if (add_symP == NULL && sub_symP == NULL) 3415 { 3416 /* An absolute address. */ 3417 if (pic || cris_arch == arch_crisv32) 3418 fix_new (fragP, writep + 4 - fragP->fr_literal, 4, 3419 section_symbol (absolute_section), 3420 add_num 3421 + (cris_arch == arch_crisv32 ? 6 : 0), 3422 1, BFD_RELOC_32_PCREL); 3423 else 3424 md_number_to_chars (writep + 4, add_num, 4); 3425 } 3426 else 3427 { 3428 if (sub_symP != NULL) 3429 as_bad_where (fragP->fr_file, fragP->fr_line, 3430 _("Complex expression not supported")); 3431 3432 /* Not absolute, we have to make it a frag for later evaluation. */ 3433 fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP, 3434 add_num + (cris_arch == arch_crisv32 ? 6 : 0), 3435 pic || cris_arch == arch_crisv32 ? 1 : 0, 3436 pic || cris_arch == arch_crisv32 3437 ? BFD_RELOC_32_PCREL : BFD_RELOC_32); 3438 } 3439 3440 if (cris_arch == arch_crisv32) 3441 /* Follow it with a "NOP" for CRISv32. */ 3442 md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2); 3443 else if (pic) 3444 /* ...and the rest of the move-opcode for pre-v32 PIC. */ 3445 md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2); 3446 } 3447 3448 /* Get the size of an immediate-reloc in bytes. Only valid for 3449 specified relocs (TLS, PIC). */ 3450 3451 static unsigned int 3452 cris_get_specified_reloc_size (bfd_reloc_code_real_type reloc) 3453 { 3454 return 3455 reloc == BFD_RELOC_CRIS_16_GOTPLT 3456 || reloc == BFD_RELOC_CRIS_16_GOT 3457 || reloc == BFD_RELOC_CRIS_16_GOT_GD 3458 || reloc == BFD_RELOC_CRIS_16_DTPREL 3459 || reloc == BFD_RELOC_CRIS_16_GOT_TPREL 3460 || reloc == BFD_RELOC_CRIS_16_TPREL 3461 ? 2 : 4; 3462 } 3463 3464 /* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP. 3465 Adjust *EXPRP with any addend found after the PIC suffix. */ 3466 3467 static void 3468 cris_get_reloc_suffix (char **cPP, bfd_reloc_code_real_type *relocp, 3469 expressionS *exprP) 3470 { 3471 char *s = *cPP; 3472 unsigned int i; 3473 expressionS const_expr; 3474 3475 const struct pic_suffixes_struct 3476 { 3477 const char *const suffix; 3478 unsigned int len; 3479 bfd_reloc_code_real_type reloc; 3480 bfd_boolean pic_p; 3481 bfd_boolean tls_p; 3482 } pic_suffixes[] = 3483 { 3484 #undef PICMAP 3485 #define PICMAP(s, r) {s, sizeof (s) - 1, r, TRUE, FALSE} 3486 #define PICTLSMAP(s, r) {s, sizeof (s) - 1, r, TRUE, TRUE} 3487 #define TLSMAP(s, r) {s, sizeof (s) - 1, r, FALSE, TRUE} 3488 /* Keep this in order with longest unambiguous prefix first. */ 3489 PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT), 3490 PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT), 3491 PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL), 3492 PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL), 3493 PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL), 3494 PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT), 3495 PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT), 3496 PICTLSMAP ("GDGOTREL16", BFD_RELOC_CRIS_16_GOT_GD), 3497 PICTLSMAP ("GDGOTREL", BFD_RELOC_CRIS_32_GOT_GD), 3498 TLSMAP ("GD", BFD_RELOC_CRIS_32_GD), 3499 PICTLSMAP ("DTPREL16", BFD_RELOC_CRIS_16_DTPREL), 3500 PICTLSMAP ("DTPREL", BFD_RELOC_CRIS_32_DTPREL), 3501 TLSMAP ("IE", BFD_RELOC_CRIS_32_IE), 3502 PICTLSMAP ("TPOFFGOT16", BFD_RELOC_CRIS_16_GOT_TPREL), 3503 PICTLSMAP ("TPOFFGOT", BFD_RELOC_CRIS_32_GOT_TPREL), 3504 TLSMAP ("TPOFF16", BFD_RELOC_CRIS_16_TPREL), 3505 TLSMAP ("TPOFF", BFD_RELOC_CRIS_32_TPREL) 3506 }; 3507 3508 /* We've already seen the ':', so consume it. */ 3509 s++; 3510 3511 for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++) 3512 { 3513 if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0 3514 && ! is_part_of_name (s[pic_suffixes[i].len]) 3515 /* PIC and non-PIC relocations are exclusive. */ 3516 && (pic != 0) == (pic_suffixes[i].pic_p != 0) 3517 /* But TLS can be active for non-TLS relocations too. */ 3518 && (pic_suffixes[i].tls_p == 0 || tls)) 3519 { 3520 /* We have a match. Consume the suffix and set the relocation 3521 type. */ 3522 s += pic_suffixes[i].len; 3523 3524 /* There can be a constant term appended. If so, we will add it 3525 to *EXPRP. */ 3526 if (*s == '+' || *s == '-') 3527 { 3528 if (! cris_get_expression (&s, &const_expr)) 3529 /* There was some kind of syntax error. Bail out. */ 3530 break; 3531 3532 /* Allow complex expressions as the constant part. It still 3533 has to be an assembly-time constant or there will be an 3534 error emitting the reloc. This makes the PIC qualifiers 3535 idempotent; foo:GOTOFF+32 == foo+32:GOTOFF. The former we 3536 recognize here; the latter is parsed in the incoming 3537 expression. */ 3538 exprP->X_add_symbol = make_expr_symbol (exprP); 3539 exprP->X_op = O_add; 3540 exprP->X_add_number = 0; 3541 exprP->X_op_symbol = make_expr_symbol (&const_expr); 3542 } 3543 3544 *relocp = pic_suffixes[i].reloc; 3545 *cPP = s; 3546 return; 3547 } 3548 } 3549 3550 /* No match. Don't consume anything; fall back and there will be a 3551 syntax error. */ 3552 } 3553 3554 /* This *could* have been: 3555 3556 Turn a string in input_line_pointer into a floating point constant 3557 of type TYPE, and store the appropriate bytes in *LITP. The number 3558 of LITTLENUMS emitted is stored in *SIZEP. 3559 3560 type A character from FLTCHARS that describes what kind of 3561 floating-point number is wanted. 3562 3563 litp A pointer to an array that the result should be stored in. 3564 3565 sizep A pointer to an integer where the size of the result is stored. 3566 3567 But we don't support floating point constants in assembly code *at all*, 3568 since it's suboptimal and just opens up bug opportunities. GCC emits 3569 the bit patterns as hex. All we could do here is to emit what GCC 3570 would have done in the first place. *Nobody* writes floating-point 3571 code as assembly code, but if they do, they should be able enough to 3572 find out the correct bit patterns and use them. */ 3573 3574 char * 3575 md_atof (int type ATTRIBUTE_UNUSED, char *litp ATTRIBUTE_UNUSED, 3576 int *sizep ATTRIBUTE_UNUSED) 3577 { 3578 /* FIXME: Is this function mentioned in the internals.texi manual? If 3579 not, add it. */ 3580 return _("Bad call to md_atof () - floating point formats are not supported"); 3581 } 3582 3583 /* Turn a number as a fixS * into a series of bytes that represents the 3584 number on the target machine. The purpose of this procedure is the 3585 same as that of md_number_to_chars but this procedure is supposed to 3586 handle general bit field fixes and machine-dependent fixups. 3587 3588 bufp Pointer to an array where the result should be stored. 3589 3590 val The value to store. 3591 3592 n The number of bytes in "val" that should be stored. 3593 3594 fixP The fix to be applied to the bit field starting at bufp. 3595 3596 seg The segment containing this number. */ 3597 3598 static void 3599 cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg) 3600 { 3601 segT sym_seg; 3602 3603 know (n <= 4); 3604 know (fixP); 3605 3606 /* We put the relative "vma" for the other segment for inter-segment 3607 relocations in the object data to stay binary "compatible" (with an 3608 uninteresting old version) for the relocation. 3609 Maybe delete some day. */ 3610 if (fixP->fx_addsy 3611 && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg) 3612 val += sym_seg->vma; 3613 3614 if (fixP->fx_addsy != NULL || fixP->fx_pcrel) 3615 switch (fixP->fx_r_type) 3616 { 3617 /* These must be fully resolved when getting here. */ 3618 case BFD_RELOC_16_PCREL: 3619 case BFD_RELOC_8_PCREL: 3620 as_bad_where (fixP->fx_file, fixP->fx_line, 3621 _("PC-relative relocation must be trivially resolved")); 3622 default: 3623 ; 3624 } 3625 3626 /* Only use the computed value for old-arch binaries. For all 3627 others, where we're going to output a relocation, put 0 in the 3628 code. */ 3629 if (cris_arch != arch_cris_any_v0_v10 3630 && (fixP->fx_addsy != NULL || fixP->fx_pcrel)) 3631 val = 0; 3632 3633 switch (fixP->fx_r_type) 3634 { 3635 /* Ditto here, we put the addend into the object code as 3636 well as the reloc addend. Keep it that way for now, to simplify 3637 regression tests on the object file contents. FIXME: Seems 3638 uninteresting now that we have a test suite. */ 3639 3640 case BFD_RELOC_CRIS_32_GOT_GD: 3641 case BFD_RELOC_CRIS_16_GOT_GD: 3642 case BFD_RELOC_CRIS_32_GD: 3643 case BFD_RELOC_CRIS_32_IE: 3644 case BFD_RELOC_CRIS_32_DTPREL: 3645 case BFD_RELOC_CRIS_16_DTPREL: 3646 case BFD_RELOC_CRIS_32_GOT_TPREL: 3647 case BFD_RELOC_CRIS_16_GOT_TPREL: 3648 case BFD_RELOC_CRIS_32_TPREL: 3649 case BFD_RELOC_CRIS_16_TPREL: 3650 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 3651 if (IS_ELF && fixP->fx_addsy != NULL) 3652 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3653 #endif 3654 /* Fall through. */ 3655 3656 case BFD_RELOC_CRIS_16_GOT: 3657 case BFD_RELOC_CRIS_32_GOT: 3658 case BFD_RELOC_CRIS_32_GOTREL: 3659 case BFD_RELOC_CRIS_16_GOTPLT: 3660 case BFD_RELOC_CRIS_32_GOTPLT: 3661 case BFD_RELOC_CRIS_32_PLT_GOTREL: 3662 case BFD_RELOC_CRIS_32_PLT_PCREL: 3663 /* We don't want to put in any kind of non-zero bits in the data 3664 being relocated for these. */ 3665 md_number_to_chars (bufp, 0, n); 3666 break; 3667 3668 case BFD_RELOC_32_PCREL: 3669 /* If this one isn't fully resolved, we don't want to put non-zero 3670 in the object. */ 3671 if (fixP->fx_addsy != NULL || fixP->fx_pcrel) 3672 val = 0; 3673 3674 /* Fall through. */ 3675 case BFD_RELOC_32: 3676 /* No use having warnings here, since most hosts have a 32-bit type 3677 for "long" (which will probably change soon, now that I wrote 3678 this). */ 3679 bufp[3] = (val >> 24) & 0xFF; 3680 bufp[2] = (val >> 16) & 0xFF; 3681 bufp[1] = (val >> 8) & 0xFF; 3682 bufp[0] = val & 0xFF; 3683 break; 3684 3685 /* FIXME: The 16 and 8-bit cases should have a way to check 3686 whether a signed or unsigned (or any signedness) number is 3687 accepted. */ 3688 3689 case BFD_RELOC_16: 3690 case BFD_RELOC_16_PCREL: 3691 if (val > 0xffff || val < -32768) 3692 as_bad_where (fixP->fx_file, fixP->fx_line, 3693 _("Value not in 16 bit range: %ld"), val); 3694 bufp[1] = (val >> 8) & 0xFF; 3695 bufp[0] = val & 0xFF; 3696 break; 3697 3698 case BFD_RELOC_CRIS_SIGNED_16: 3699 if (val > 32767 || val < -32768) 3700 as_bad_where (fixP->fx_file, fixP->fx_line, 3701 _("Value not in 16 bit signed range: %ld"), val); 3702 bufp[1] = (val >> 8) & 0xFF; 3703 bufp[0] = val & 0xFF; 3704 break; 3705 3706 case BFD_RELOC_8: 3707 case BFD_RELOC_8_PCREL: 3708 if (val > 255 || val < -128) 3709 as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val); 3710 bufp[0] = val & 0xFF; 3711 break; 3712 3713 case BFD_RELOC_CRIS_SIGNED_8: 3714 if (val > 127 || val < -128) 3715 as_bad_where (fixP->fx_file, fixP->fx_line, 3716 _("Value not in 8 bit signed range: %ld"), val); 3717 bufp[0] = val & 0xFF; 3718 break; 3719 3720 case BFD_RELOC_CRIS_LAPCQ_OFFSET: 3721 /* FIXME: Test-cases for out-of-range values. Probably also need 3722 to use as_bad_where. */ 3723 case BFD_RELOC_CRIS_UNSIGNED_4: 3724 if (val > 15 || val < 0) 3725 as_bad_where (fixP->fx_file, fixP->fx_line, 3726 _("Value not in 4 bit unsigned range: %ld"), val); 3727 bufp[0] |= val & 0x0F; 3728 break; 3729 3730 case BFD_RELOC_CRIS_UNSIGNED_5: 3731 if (val > 31 || val < 0) 3732 as_bad_where (fixP->fx_file, fixP->fx_line, 3733 _("Value not in 5 bit unsigned range: %ld"), val); 3734 bufp[0] |= val & 0x1F; 3735 break; 3736 3737 case BFD_RELOC_CRIS_SIGNED_6: 3738 if (val > 31 || val < -32) 3739 as_bad_where (fixP->fx_file, fixP->fx_line, 3740 _("Value not in 6 bit range: %ld"), val); 3741 bufp[0] |= val & 0x3F; 3742 break; 3743 3744 case BFD_RELOC_CRIS_UNSIGNED_6: 3745 if (val > 63 || val < 0) 3746 as_bad_where (fixP->fx_file, fixP->fx_line, 3747 _("Value not in 6 bit unsigned range: %ld"), val); 3748 bufp[0] |= val & 0x3F; 3749 break; 3750 3751 case BFD_RELOC_CRIS_BDISP8: 3752 bufp[0] = branch_disp (val); 3753 break; 3754 3755 case BFD_RELOC_NONE: 3756 /* May actually happen automatically. For example at broken 3757 words, if the word turns out not to be broken. 3758 FIXME: When? Which testcase? */ 3759 if (! fixP->fx_addsy) 3760 md_number_to_chars (bufp, val, n); 3761 break; 3762 3763 case BFD_RELOC_VTABLE_INHERIT: 3764 /* This borrowed from tc-ppc.c on a whim. */ 3765 if (fixP->fx_addsy 3766 && !S_IS_DEFINED (fixP->fx_addsy) 3767 && !S_IS_WEAK (fixP->fx_addsy)) 3768 S_SET_WEAK (fixP->fx_addsy); 3769 /* Fall through. */ 3770 3771 case BFD_RELOC_VTABLE_ENTRY: 3772 fixP->fx_done = 0; 3773 break; 3774 3775 default: 3776 BAD_CASE (fixP->fx_r_type); 3777 } 3778 } 3779 3780 /* Processes machine-dependent command line options. Called once for 3781 each option on the command line that the machine-independent part of 3782 GAS does not understand. */ 3783 3784 int 3785 md_parse_option (int arg, char *argp ATTRIBUTE_UNUSED) 3786 { 3787 switch (arg) 3788 { 3789 case 'H': 3790 case 'h': 3791 printf (_("Please use --help to see usage and options for this assembler.\n")); 3792 md_show_usage (stdout); 3793 exit (EXIT_SUCCESS); 3794 3795 case 'N': 3796 warn_for_branch_expansion = 1; 3797 break; 3798 3799 case OPTION_NO_US: 3800 demand_register_prefix = TRUE; 3801 3802 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 3803 as_bad (_("--no-underscore is invalid with a.out format")); 3804 else 3805 symbols_have_leading_underscore = FALSE; 3806 break; 3807 3808 case OPTION_US: 3809 demand_register_prefix = FALSE; 3810 symbols_have_leading_underscore = TRUE; 3811 break; 3812 3813 case OPTION_PIC: 3814 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 3815 as_bad (_("--pic is invalid for this object format")); 3816 pic = TRUE; 3817 if (cris_arch != arch_crisv32) 3818 md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; 3819 else 3820 md_long_jump_size = crisv32_long_jump_size; 3821 break; 3822 3823 case OPTION_ARCH: 3824 { 3825 char *str = argp; 3826 enum cris_archs argarch = cris_arch_from_string (&str); 3827 3828 if (argarch == arch_cris_unknown) 3829 as_bad (_("invalid <arch> in --march=<arch>: %s"), argp); 3830 else 3831 cris_arch = argarch; 3832 3833 if (argarch == arch_crisv32) 3834 { 3835 err_for_dangerous_mul_placement = 0; 3836 md_long_jump_size = crisv32_long_jump_size; 3837 } 3838 else 3839 { 3840 if (pic) 3841 md_long_jump_size = cris_any_v0_v10_long_jump_size_pic; 3842 else 3843 md_long_jump_size = cris_any_v0_v10_long_jump_size; 3844 } 3845 } 3846 break; 3847 3848 case OPTION_MULBUG_ABORT_OFF: 3849 err_for_dangerous_mul_placement = 0; 3850 break; 3851 3852 case OPTION_MULBUG_ABORT_ON: 3853 err_for_dangerous_mul_placement = 1; 3854 break; 3855 3856 default: 3857 return 0; 3858 } 3859 3860 return 1; 3861 } 3862 3863 /* Round up a section size to the appropriate boundary. */ 3864 valueT 3865 md_section_align (segT segment, valueT size) 3866 { 3867 /* Round all sects to multiple of 4, except the bss section, which 3868 we'll round to word-size. 3869 3870 FIXME: Check if this really matters. All sections should be 3871 rounded up, and all sections should (optionally) be assumed to be 3872 dword-aligned, it's just that there is actual usage of linking to a 3873 multiple of two. */ 3874 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 3875 { 3876 if (segment == bss_section) 3877 return (size + 1) & ~1; 3878 return (size + 3) & ~3; 3879 } 3880 else 3881 { 3882 /* FIXME: Is this wanted? It matches the testsuite, but that's not 3883 really a valid reason. */ 3884 if (segment == text_section) 3885 return (size + 3) & ~3; 3886 } 3887 3888 return size; 3889 } 3890 3891 /* Generate a machine-dependent relocation. */ 3892 arelent * 3893 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) 3894 { 3895 arelent *relP; 3896 bfd_reloc_code_real_type code; 3897 3898 switch (fixP->fx_r_type) 3899 { 3900 case BFD_RELOC_CRIS_SIGNED_8: 3901 code = BFD_RELOC_8; 3902 break; 3903 3904 case BFD_RELOC_CRIS_SIGNED_16: 3905 code = BFD_RELOC_16; 3906 break; 3907 3908 case BFD_RELOC_CRIS_16_GOT: 3909 case BFD_RELOC_CRIS_32_GOT: 3910 case BFD_RELOC_CRIS_16_GOTPLT: 3911 case BFD_RELOC_CRIS_32_GOTPLT: 3912 case BFD_RELOC_CRIS_32_GOTREL: 3913 case BFD_RELOC_CRIS_32_PLT_GOTREL: 3914 case BFD_RELOC_CRIS_32_PLT_PCREL: 3915 case BFD_RELOC_32: 3916 case BFD_RELOC_32_PCREL: 3917 case BFD_RELOC_16: 3918 case BFD_RELOC_8: 3919 case BFD_RELOC_VTABLE_INHERIT: 3920 case BFD_RELOC_VTABLE_ENTRY: 3921 case BFD_RELOC_CRIS_UNSIGNED_8: 3922 case BFD_RELOC_CRIS_UNSIGNED_16: 3923 case BFD_RELOC_CRIS_LAPCQ_OFFSET: 3924 case BFD_RELOC_CRIS_32_GOT_GD: 3925 case BFD_RELOC_CRIS_16_GOT_GD: 3926 case BFD_RELOC_CRIS_32_GD: 3927 case BFD_RELOC_CRIS_32_IE: 3928 case BFD_RELOC_CRIS_32_DTPREL: 3929 case BFD_RELOC_CRIS_16_DTPREL: 3930 case BFD_RELOC_CRIS_32_GOT_TPREL: 3931 case BFD_RELOC_CRIS_16_GOT_TPREL: 3932 case BFD_RELOC_CRIS_32_TPREL: 3933 case BFD_RELOC_CRIS_16_TPREL: 3934 code = fixP->fx_r_type; 3935 break; 3936 default: 3937 as_bad_where (fixP->fx_file, fixP->fx_line, 3938 _("Semantics error. This type of operand can not be relocated, it must be an assembly-time constant")); 3939 return 0; 3940 } 3941 3942 relP = (arelent *) xmalloc (sizeof (arelent)); 3943 gas_assert (relP != 0); 3944 relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3945 *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 3946 relP->address = fixP->fx_frag->fr_address + fixP->fx_where; 3947 3948 relP->addend = fixP->fx_offset; 3949 3950 /* This is the standard place for KLUDGEs to work around bugs in 3951 bfd_install_relocation (first such note in the documentation 3952 appears with binutils-2.8). 3953 3954 That function bfd_install_relocation does the wrong thing with 3955 putting stuff into the addend of a reloc (it should stay out) for a 3956 weak symbol. The really bad thing is that it adds the 3957 "segment-relative offset" of the symbol into the reloc. In this 3958 case, the reloc should instead be relative to the symbol with no 3959 other offset than the assembly code shows; and since the symbol is 3960 weak, any local definition should be ignored until link time (or 3961 thereafter). 3962 To wit: weaksym+42 should be weaksym+42 in the reloc, 3963 not weaksym+(offset_from_segment_of_local_weaksym_definition) 3964 3965 To "work around" this, we subtract the segment-relative offset of 3966 "known" weak symbols. This evens out the extra offset. 3967 3968 That happens for a.out but not for ELF, since for ELF, 3969 bfd_install_relocation uses the "special function" field of the 3970 howto, and does not execute the code that needs to be undone. */ 3971 3972 if (OUTPUT_FLAVOR == bfd_target_aout_flavour 3973 && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy) 3974 && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy))) 3975 { 3976 relP->addend -= S_GET_VALUE (fixP->fx_addsy); 3977 } 3978 3979 relP->howto = bfd_reloc_type_lookup (stdoutput, code); 3980 if (! relP->howto) 3981 { 3982 const char *name; 3983 3984 name = S_GET_NAME (fixP->fx_addsy); 3985 if (name == NULL) 3986 name = _("<unknown>"); 3987 as_fatal (_("Cannot generate relocation type for symbol %s, code %s"), 3988 name, bfd_get_reloc_code_name (code)); 3989 } 3990 3991 return relP; 3992 } 3993 3994 /* Machine-dependent usage-output. */ 3995 3996 void 3997 md_show_usage (FILE *stream) 3998 { 3999 /* The messages are formatted to line up with the generic options. */ 4000 fprintf (stream, _("CRIS-specific options:\n")); 4001 fprintf (stream, "%s", 4002 _(" -h, -H Don't execute, print this help text. Deprecated.\n")); 4003 fprintf (stream, "%s", 4004 _(" -N Warn when branches are expanded to jumps.\n")); 4005 fprintf (stream, "%s", 4006 _(" --underscore User symbols are normally prepended with underscore.\n")); 4007 fprintf (stream, "%s", 4008 _(" Registers will not need any prefix.\n")); 4009 fprintf (stream, "%s", 4010 _(" --no-underscore User symbols do not have any prefix.\n")); 4011 fprintf (stream, "%s", 4012 _(" Registers will require a `$'-prefix.\n")); 4013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4014 fprintf (stream, "%s", 4015 _(" --pic Enable generation of position-independent code.\n")); 4016 #endif 4017 fprintf (stream, "%s", 4018 _(" --march=<arch> Generate code for <arch>. Valid choices for <arch>\n\ 4019 are v0_v10, v10, v32 and common_v10_v32.\n")); 4020 } 4021 4022 /* Apply a fixS (fixup of an instruction or data that we didn't have 4023 enough info to complete immediately) to the data in a frag. */ 4024 4025 void 4026 md_apply_fix (fixS *fixP, valueT *valP, segT seg) 4027 { 4028 /* This assignment truncates upper bits if valueT is 64 bits (as with 4029 --enable-64-bit-bfd), which is fine here, though we cast to avoid 4030 any compiler warnings. */ 4031 long val = (long) *valP; 4032 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 4033 4034 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 4035 fixP->fx_done = 1; 4036 4037 if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0) 4038 { 4039 as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation")); 4040 fixP->fx_done = 1; 4041 } 4042 else 4043 { 4044 /* We can't actually support subtracting a symbol. */ 4045 if (fixP->fx_subsy != (symbolS *) NULL) 4046 as_bad_where (fixP->fx_file, fixP->fx_line, 4047 _("expression too complex")); 4048 4049 /* This operand-type is scaled. */ 4050 if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET) 4051 val /= 2; 4052 cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg); 4053 } 4054 } 4055 4056 /* All relocations are relative to the location just after the fixup; 4057 the address of the fixup plus its size. */ 4058 4059 long 4060 md_pcrel_from (fixS *fixP) 4061 { 4062 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; 4063 4064 /* FIXME: We get here only at the end of assembly, when X in ".-X" is 4065 still unknown. Since we don't have pc-relative relocations in a.out, 4066 this is invalid. What to do if anything for a.out, is to add 4067 pc-relative relocations everywhere including the elinux program 4068 loader. For ELF, allow straight-forward PC-relative relocations, 4069 which are always relative to the location after the relocation. */ 4070 if (OUTPUT_FLAVOR != bfd_target_elf_flavour 4071 || (fixP->fx_r_type != BFD_RELOC_8_PCREL 4072 && fixP->fx_r_type != BFD_RELOC_16_PCREL 4073 && fixP->fx_r_type != BFD_RELOC_32_PCREL 4074 && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET)) 4075 as_bad_where (fixP->fx_file, fixP->fx_line, 4076 _("Invalid pc-relative relocation")); 4077 return fixP->fx_size + addr; 4078 } 4079 4080 /* We have no need to give defaults for symbol-values. */ 4081 symbolS * 4082 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 4083 { 4084 return 0; 4085 } 4086 4087 /* If this function returns non-zero, it prevents the relocation 4088 against symbol(s) in the FIXP from being replaced with relocations 4089 against section symbols, and guarantees that a relocation will be 4090 emitted even when the value can be resolved locally. */ 4091 int 4092 md_cris_force_relocation (struct fix *fixp) 4093 { 4094 switch (fixp->fx_r_type) 4095 { 4096 case BFD_RELOC_CRIS_16_GOT: 4097 case BFD_RELOC_CRIS_32_GOT: 4098 case BFD_RELOC_CRIS_16_GOTPLT: 4099 case BFD_RELOC_CRIS_32_GOTPLT: 4100 case BFD_RELOC_CRIS_32_GOTREL: 4101 case BFD_RELOC_CRIS_32_PLT_GOTREL: 4102 case BFD_RELOC_CRIS_32_PLT_PCREL: 4103 return 1; 4104 default: 4105 ; 4106 } 4107 4108 return generic_force_reloc (fixp); 4109 } 4110 4111 /* Check and emit error if broken-word handling has failed to fix up a 4112 case-table. This is called from write.c, after doing everything it 4113 knows about how to handle broken words. */ 4114 4115 void 4116 tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP) 4117 { 4118 if (new_offset > 32767 || new_offset < -32768) 4119 /* We really want a genuine error, not a warning, so make it one. */ 4120 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line, 4121 _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."), 4122 (long) new_offset); 4123 } 4124 4125 /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers. */ 4126 4127 static void 4128 cris_force_reg_prefix (void) 4129 { 4130 demand_register_prefix = TRUE; 4131 } 4132 4133 /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers. */ 4134 4135 static void 4136 cris_relax_reg_prefix (void) 4137 { 4138 demand_register_prefix = FALSE; 4139 } 4140 4141 /* Adjust for having a leading '_' on all user symbols. */ 4142 4143 static void 4144 cris_sym_leading_underscore (void) 4145 { 4146 /* We can't really do anything more than assert that what the program 4147 thinks symbol starts with agrees with the command-line options, since 4148 the bfd is already created. */ 4149 4150 if (!symbols_have_leading_underscore) 4151 as_bad (_(".syntax %s requires command-line option `--underscore'"), 4152 SYNTAX_USER_SYM_LEADING_UNDERSCORE); 4153 } 4154 4155 /* Adjust for not having any particular prefix on user symbols. */ 4156 4157 static void cris_sym_no_leading_underscore (void) 4158 { 4159 if (symbols_have_leading_underscore) 4160 as_bad (_(".syntax %s requires command-line option `--no-underscore'"), 4161 SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE); 4162 } 4163 4164 /* Handle the .syntax pseudo, which takes an argument that decides what 4165 syntax the assembly code has. */ 4166 4167 static void 4168 s_syntax (int ignore ATTRIBUTE_UNUSED) 4169 { 4170 static const struct syntaxes 4171 { 4172 const char *const operand; 4173 void (*fn) (void); 4174 } syntax_table[] = 4175 {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix}, 4176 {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix}, 4177 {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore}, 4178 {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}}; 4179 4180 const struct syntaxes *sp; 4181 4182 for (sp = syntax_table; 4183 sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]); 4184 sp++) 4185 { 4186 if (strncmp (input_line_pointer, sp->operand, 4187 strlen (sp->operand)) == 0) 4188 { 4189 (sp->fn) (); 4190 4191 input_line_pointer += strlen (sp->operand); 4192 demand_empty_rest_of_line (); 4193 return; 4194 } 4195 } 4196 4197 as_bad (_("Unknown .syntax operand")); 4198 } 4199 4200 /* Wrapper for dwarf2_directive_file to emit error if this is seen when 4201 not emitting ELF. */ 4202 4203 static void 4204 s_cris_file (int dummy) 4205 { 4206 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 4207 as_bad (_("Pseudodirective .file is only valid when generating ELF")); 4208 else 4209 dwarf2_directive_file (dummy); 4210 } 4211 4212 /* Wrapper for dwarf2_directive_loc to emit error if this is seen when not 4213 emitting ELF. */ 4214 4215 static void 4216 s_cris_loc (int dummy) 4217 { 4218 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 4219 as_bad (_("Pseudodirective .loc is only valid when generating ELF")); 4220 else 4221 dwarf2_directive_loc (dummy); 4222 } 4223 4224 /* Worker for .dtpoffd: generate a R_CRIS_32_DTPREL reloc, as for 4225 expr:DTPREL but for use in debug info. */ 4226 4227 static void 4228 s_cris_dtpoff (int bytes) 4229 { 4230 expressionS ex; 4231 char *p; 4232 4233 if (bytes != 4) 4234 as_fatal (_("internal inconsistency problem: %s called for %d bytes"), 4235 __FUNCTION__, bytes); 4236 4237 expression (&ex); 4238 4239 p = frag_more (bytes); 4240 md_number_to_chars (p, 0, bytes); 4241 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE, 4242 BFD_RELOC_CRIS_32_DTPREL); 4243 4244 demand_empty_rest_of_line (); 4245 } 4246 4247 4248 /* Translate a <arch> string (as common to --march=<arch> and .arch <arch>) 4249 into an enum. If the string *STR is recognized, *STR is updated to point 4250 to the end of the string. If the string is not recognized, 4251 arch_cris_unknown is returned. */ 4252 4253 static enum cris_archs 4254 cris_arch_from_string (char **str) 4255 { 4256 static const struct cris_arch_struct 4257 { 4258 const char *const name; 4259 enum cris_archs arch; 4260 } arch_table[] = 4261 /* Keep in order longest-first for choices where one is a prefix 4262 of another. */ 4263 {{"v0_v10", arch_cris_any_v0_v10}, 4264 {"v10", arch_crisv10}, 4265 {"v32", arch_crisv32}, 4266 {"common_v10_v32", arch_cris_common_v10_v32}}; 4267 4268 const struct cris_arch_struct *ap; 4269 4270 for (ap = arch_table; 4271 ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]); 4272 ap++) 4273 { 4274 int len = strlen (ap->name); 4275 4276 if (strncmp (*str, ap->name, len) == 0 4277 && (str[0][len] == 0 || ISSPACE (str[0][len]))) 4278 { 4279 *str += strlen (ap->name); 4280 return ap->arch; 4281 } 4282 } 4283 4284 return arch_cris_unknown; 4285 } 4286 4287 /* Return nonzero if architecture version ARCH matches version range in 4288 IVER. */ 4289 4290 static int 4291 cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver, 4292 enum cris_archs arch) 4293 { 4294 switch (arch) 4295 { 4296 case arch_cris_any_v0_v10: 4297 return 4298 (iver == cris_ver_version_all 4299 || iver == cris_ver_warning 4300 || iver == cris_ver_v0_3 4301 || iver == cris_ver_v3p 4302 || iver == cris_ver_v0_10 4303 || iver == cris_ver_sim_v0_10 4304 || iver == cris_ver_v3_10 4305 || iver == cris_ver_v8 4306 || iver == cris_ver_v8p 4307 || iver == cris_ver_v8_10 4308 || iver == cris_ver_v10 4309 || iver == cris_ver_v10p); 4310 4311 case arch_crisv32: 4312 return 4313 (iver == cris_ver_version_all 4314 || iver == cris_ver_v3p 4315 || iver == cris_ver_v8p 4316 || iver == cris_ver_v10p 4317 || iver == cris_ver_v32p); 4318 4319 case arch_cris_common_v10_v32: 4320 return 4321 (iver == cris_ver_version_all 4322 || iver == cris_ver_v3p 4323 || iver == cris_ver_v8p 4324 || iver == cris_ver_v10p); 4325 4326 case arch_crisv0: 4327 return 4328 (iver == cris_ver_version_all 4329 || iver == cris_ver_v0_3 4330 || iver == cris_ver_v0_10 4331 || iver == cris_ver_sim_v0_10); 4332 4333 case arch_crisv3: 4334 return 4335 (iver == cris_ver_version_all 4336 || iver == cris_ver_v0_3 4337 || iver == cris_ver_v3p 4338 || iver == cris_ver_v0_10 4339 || iver == cris_ver_sim_v0_10 4340 || iver == cris_ver_v3_10); 4341 4342 case arch_crisv8: 4343 return 4344 (iver == cris_ver_version_all 4345 || iver == cris_ver_v3p 4346 || iver == cris_ver_v0_10 4347 || iver == cris_ver_sim_v0_10 4348 || iver == cris_ver_v3_10 4349 || iver == cris_ver_v8 4350 || iver == cris_ver_v8p 4351 || iver == cris_ver_v8_10); 4352 4353 case arch_crisv10: 4354 return 4355 (iver == cris_ver_version_all 4356 || iver == cris_ver_v3p 4357 || iver == cris_ver_v0_10 4358 || iver == cris_ver_sim_v0_10 4359 || iver == cris_ver_v3_10 4360 || iver == cris_ver_v8p 4361 || iver == cris_ver_v8_10 4362 || iver == cris_ver_v10 4363 || iver == cris_ver_v10p); 4364 4365 default: 4366 BAD_CASE (arch); 4367 } 4368 } 4369 4370 /* Assert that the .arch ARCHCHOICE1 is compatible with the specified or 4371 default --march=<ARCHCHOICE2> option. */ 4372 4373 static void 4374 s_cris_arch (int dummy ATTRIBUTE_UNUSED) 4375 { 4376 /* Right now we take the easy route and check for sameness. It's not 4377 obvious that allowing e.g. --march=v32 and .arch common_v0_v32 4378 would be more useful than confusing, implementation-wise and 4379 user-wise. */ 4380 4381 char *str = input_line_pointer; 4382 enum cris_archs arch = cris_arch_from_string (&str); 4383 4384 if (arch == arch_cris_unknown) 4385 { 4386 as_bad (_("unknown operand to .arch")); 4387 4388 /* For this one, str does not reflect the end of the operand, 4389 since there was no matching arch. Skip it manually; skip 4390 things that can be part of a word (a name). */ 4391 while (is_part_of_name (*str)) 4392 str++; 4393 } 4394 else if (arch != cris_arch) 4395 as_bad (_(".arch <arch> requires a matching --march=... option")); 4396 4397 input_line_pointer = str; 4398 demand_empty_rest_of_line (); 4399 return; 4400 } 4401 4402 /* 4403 * Local variables: 4404 * eval: (c-set-style "gnu") 4405 * indent-tabs-mode: t 4406 * End: 4407 */ 4408