1 /* tc-cr16.c -- Assembler code for the CR16 CPU core. 2 Copyright 2007, 2008, 2009, 2010, 2011 3 Free Software Foundation, Inc. 4 5 Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com> 6 7 This file is part of GAS, the GNU Assembler. 8 9 GAS is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GAS; see the file COPYING. If not, write to the 21 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #include "as.h" 25 #include "safe-ctype.h" 26 #include "dwarf2dbg.h" 27 #include "opcode/cr16.h" 28 #include "elf/cr16.h" 29 30 31 /* Word is considered here as a 16-bit unsigned short int. */ 32 #define WORD_SHIFT 16 33 34 /* Register is 2-byte size. */ 35 #define REG_SIZE 2 36 37 /* Maximum size of a single instruction (in words). */ 38 #define INSN_MAX_SIZE 3 39 40 /* Maximum bits which may be set in a `mask16' operand. */ 41 #define MAX_REGS_IN_MASK16 8 42 43 /* Assign a number NUM, shifted by SHIFT bytes, into a location 44 pointed by index BYTE of array 'output_opcode'. */ 45 #define CR16_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT) 46 47 /* Operand errors. */ 48 typedef enum 49 { 50 OP_LEGAL = 0, /* Legal operand. */ 51 OP_OUT_OF_RANGE, /* Operand not within permitted range. */ 52 OP_NOT_EVEN /* Operand is Odd number, should be even. */ 53 } 54 op_err; 55 56 /* Opcode mnemonics hash table. */ 57 static struct hash_control *cr16_inst_hash; 58 /* CR16 registers hash table. */ 59 static struct hash_control *reg_hash; 60 /* CR16 register pair hash table. */ 61 static struct hash_control *regp_hash; 62 /* CR16 processor registers hash table. */ 63 static struct hash_control *preg_hash; 64 /* CR16 processor registers 32 bit hash table. */ 65 static struct hash_control *pregp_hash; 66 /* Current instruction we're assembling. */ 67 const inst *instruction; 68 69 70 static int code_label = 0; 71 72 /* Global variables. */ 73 74 /* Array to hold an instruction encoding. */ 75 long output_opcode[2]; 76 77 /* Nonzero means a relocatable symbol. */ 78 int relocatable; 79 80 /* A copy of the original instruction (used in error messages). */ 81 char ins_parse[MAX_INST_LEN]; 82 83 /* The current processed argument number. */ 84 int cur_arg_num; 85 86 /* Generic assembler global variables which must be defined by all targets. */ 87 88 /* Characters which always start a comment. */ 89 const char comment_chars[] = "#"; 90 91 /* Characters which start a comment at the beginning of a line. */ 92 const char line_comment_chars[] = "#"; 93 94 /* This array holds machine specific line separator characters. */ 95 const char line_separator_chars[] = ";"; 96 97 /* Chars that can be used to separate mant from exp in floating point nums. */ 98 const char EXP_CHARS[] = "eE"; 99 100 /* Chars that mean this number is a floating point constant as in 0f12.456 */ 101 const char FLT_CHARS[] = "f'"; 102 103 #ifdef OBJ_ELF 104 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 105 symbolS * GOT_symbol; 106 #endif 107 108 /* Target-specific multicharacter options, not const-declared at usage. */ 109 const char *md_shortopts = ""; 110 struct option md_longopts[] = 111 { 112 {NULL, no_argument, NULL, 0} 113 }; 114 size_t md_longopts_size = sizeof (md_longopts); 115 116 static void 117 l_cons (int nbytes) 118 { 119 int c; 120 expressionS exp; 121 122 #ifdef md_flush_pending_output 123 md_flush_pending_output (); 124 #endif 125 126 if (is_it_end_of_statement ()) 127 { 128 demand_empty_rest_of_line (); 129 return; 130 } 131 132 #ifdef TC_ADDRESS_BYTES 133 if (nbytes == 0) 134 nbytes = TC_ADDRESS_BYTES (); 135 #endif 136 137 #ifdef md_cons_align 138 md_cons_align (nbytes); 139 #endif 140 141 c = 0; 142 do 143 { 144 unsigned int bits_available = BITS_PER_CHAR * nbytes; 145 char *hold = input_line_pointer; 146 147 expression (&exp); 148 149 if (*input_line_pointer == ':') 150 { 151 /* Bitfields. */ 152 long value = 0; 153 154 for (;;) 155 { 156 unsigned long width; 157 158 if (*input_line_pointer != ':') 159 { 160 input_line_pointer = hold; 161 break; 162 } 163 if (exp.X_op == O_absent) 164 { 165 as_warn (_("using a bit field width of zero")); 166 exp.X_add_number = 0; 167 exp.X_op = O_constant; 168 } 169 170 if (exp.X_op != O_constant) 171 { 172 *input_line_pointer = '\0'; 173 as_bad (_("field width \"%s\" too complex for a bitfield"), hold); 174 *input_line_pointer = ':'; 175 demand_empty_rest_of_line (); 176 return; 177 } 178 179 if ((width = exp.X_add_number) > 180 (unsigned int)(BITS_PER_CHAR * nbytes)) 181 { 182 as_warn (_("field width %lu too big to fit in %d bytes: truncated to %d bits"), width, nbytes, (BITS_PER_CHAR * nbytes)); 183 width = BITS_PER_CHAR * nbytes; 184 } /* Too big. */ 185 186 187 if (width > bits_available) 188 { 189 /* FIXME-SOMEDAY: backing up and reparsing is wasteful. */ 190 input_line_pointer = hold; 191 exp.X_add_number = value; 192 break; 193 } 194 195 /* Skip ':'. */ 196 hold = ++input_line_pointer; 197 198 expression (&exp); 199 if (exp.X_op != O_constant) 200 { 201 char cache = *input_line_pointer; 202 203 *input_line_pointer = '\0'; 204 as_bad (_("field value \"%s\" too complex for a bitfield"), hold); 205 *input_line_pointer = cache; 206 demand_empty_rest_of_line (); 207 return; 208 } 209 210 value |= ((~(-1 << width) & exp.X_add_number) 211 << ((BITS_PER_CHAR * nbytes) - bits_available)); 212 213 if ((bits_available -= width) == 0 214 || is_it_end_of_statement () 215 || *input_line_pointer != ',') 216 break; 217 218 hold = ++input_line_pointer; 219 expression (&exp); 220 } 221 222 exp.X_add_number = value; 223 exp.X_op = O_constant; 224 exp.X_unsigned = 1; 225 } 226 227 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c')) 228 code_label = 1; 229 emit_expr (&exp, (unsigned int) nbytes); 230 ++c; 231 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c')) 232 { 233 input_line_pointer +=3; 234 break; 235 } 236 } 237 while ((*input_line_pointer++ == ',')); 238 239 /* Put terminator back into stream. */ 240 input_line_pointer--; 241 242 demand_empty_rest_of_line (); 243 } 244 245 /* This table describes all the machine specific pseudo-ops 246 the assembler has to support. The fields are: 247 *** Pseudo-op name without dot. 248 *** Function to call to execute this pseudo-op. 249 *** Integer arg to pass to the function. */ 250 251 const pseudo_typeS md_pseudo_table[] = 252 { 253 /* In CR16 machine, align is in bytes (not a ptwo boundary). */ 254 {"align", s_align_bytes, 0}, 255 {"long", l_cons, 4 }, 256 {"4byte", l_cons, 4 }, 257 {0, 0, 0} 258 }; 259 260 /* CR16 relaxation table. */ 261 const relax_typeS md_relax_table[] = 262 { 263 /* bCC */ 264 {0x7f, -0x80, 2, 1}, /* 8 */ 265 {0xfffe, -0x10000, 4, 2}, /* 16 */ 266 {0xfffffe, -0x1000000, 6, 0}, /* 24 */ 267 }; 268 269 /* Return the bit size for a given operand. */ 270 271 static int 272 get_opbits (operand_type op) 273 { 274 if (op < MAX_OPRD) 275 return cr16_optab[op].bit_size; 276 277 return 0; 278 } 279 280 /* Return the argument type of a given operand. */ 281 282 static argtype 283 get_optype (operand_type op) 284 { 285 if (op < MAX_OPRD) 286 return cr16_optab[op].arg_type; 287 else 288 return nullargs; 289 } 290 291 /* Return the flags of a given operand. */ 292 293 static int 294 get_opflags (operand_type op) 295 { 296 if (op < MAX_OPRD) 297 return cr16_optab[op].flags; 298 299 return 0; 300 } 301 302 /* Get the cc code. */ 303 304 static int 305 get_cc (char *cc_name) 306 { 307 unsigned int i; 308 309 for (i = 0; i < cr16_num_cc; i++) 310 if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0) 311 return i; 312 313 return -1; 314 } 315 316 /* Get the core processor register 'reg_name'. */ 317 318 static reg 319 get_register (char *reg_name) 320 { 321 const reg_entry *rreg; 322 323 rreg = (const reg_entry *) hash_find (reg_hash, reg_name); 324 325 if (rreg != NULL) 326 return rreg->value.reg_val; 327 328 return nullregister; 329 } 330 /* Get the core processor register-pair 'reg_name'. */ 331 332 static reg 333 get_register_pair (char *reg_name) 334 { 335 const reg_entry *rreg; 336 char tmp_rp[16]="\0"; 337 338 /* Add '(' and ')' to the reg pair, if its not present. */ 339 if (reg_name[0] != '(') 340 { 341 tmp_rp[0] = '('; 342 strcat (tmp_rp, reg_name); 343 strcat (tmp_rp,")"); 344 rreg = (const reg_entry *) hash_find (regp_hash, tmp_rp); 345 } 346 else 347 rreg = (const reg_entry *) hash_find (regp_hash, reg_name); 348 349 if (rreg != NULL) 350 return rreg->value.reg_val; 351 352 return nullregister; 353 } 354 355 /* Get the index register 'reg_name'. */ 356 357 static reg 358 get_index_register (char *reg_name) 359 { 360 const reg_entry *rreg; 361 362 rreg = (const reg_entry *) hash_find (reg_hash, reg_name); 363 364 if ((rreg != NULL) 365 && ((rreg->value.reg_val == 12) || (rreg->value.reg_val == 13))) 366 return rreg->value.reg_val; 367 368 return nullregister; 369 } 370 /* Get the core processor index register-pair 'reg_name'. */ 371 372 static reg 373 get_index_register_pair (char *reg_name) 374 { 375 const reg_entry *rreg; 376 377 rreg = (const reg_entry *) hash_find (regp_hash, reg_name); 378 379 if (rreg != NULL) 380 { 381 if ((rreg->value.reg_val != 1) || (rreg->value.reg_val != 7) 382 || (rreg->value.reg_val != 9) || (rreg->value.reg_val > 10)) 383 return rreg->value.reg_val; 384 385 as_bad (_("Unknown register pair - index relative mode: `%d'"), rreg->value.reg_val); 386 } 387 388 return nullregister; 389 } 390 391 /* Get the processor register 'preg_name'. */ 392 393 static preg 394 get_pregister (char *preg_name) 395 { 396 const reg_entry *prreg; 397 398 prreg = (const reg_entry *) hash_find (preg_hash, preg_name); 399 400 if (prreg != NULL) 401 return prreg->value.preg_val; 402 403 return nullpregister; 404 } 405 406 /* Get the processor register 'preg_name 32 bit'. */ 407 408 static preg 409 get_pregisterp (char *preg_name) 410 { 411 const reg_entry *prreg; 412 413 prreg = (const reg_entry *) hash_find (pregp_hash, preg_name); 414 415 if (prreg != NULL) 416 return prreg->value.preg_val; 417 418 return nullpregister; 419 } 420 421 422 /* Round up a section size to the appropriate boundary. */ 423 424 valueT 425 md_section_align (segT seg, valueT val) 426 { 427 /* Round .text section to a multiple of 2. */ 428 if (seg == text_section) 429 return (val + 1) & ~1; 430 return val; 431 } 432 433 /* Parse an operand that is machine-specific (remove '*'). */ 434 435 void 436 md_operand (expressionS * exp) 437 { 438 char c = *input_line_pointer; 439 440 switch (c) 441 { 442 case '*': 443 input_line_pointer++; 444 expression (exp); 445 break; 446 default: 447 break; 448 } 449 } 450 451 /* Reset global variables before parsing a new instruction. */ 452 453 static void 454 reset_vars (char *op) 455 { 456 cur_arg_num = relocatable = 0; 457 memset (& output_opcode, '\0', sizeof (output_opcode)); 458 459 /* Save a copy of the original OP (used in error messages). */ 460 strncpy (ins_parse, op, sizeof ins_parse - 1); 461 ins_parse [sizeof ins_parse - 1] = 0; 462 } 463 464 /* This macro decides whether a particular reloc is an entry in a 465 switch table. It is used when relaxing, because the linker needs 466 to know about all such entries so that it can adjust them if 467 necessary. */ 468 469 #define SWITCH_TABLE(fix) \ 470 ( (fix)->fx_addsy != NULL \ 471 && (fix)->fx_subsy != NULL \ 472 && S_GET_SEGMENT ((fix)->fx_addsy) == \ 473 S_GET_SEGMENT ((fix)->fx_subsy) \ 474 && S_GET_SEGMENT (fix->fx_addsy) != undefined_section \ 475 && ( (fix)->fx_r_type == BFD_RELOC_CR16_NUM8 \ 476 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16 \ 477 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32 \ 478 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a)) 479 480 /* See whether we need to force a relocation into the output file. 481 This is used to force out switch and PC relative relocations when 482 relaxing. */ 483 484 int 485 cr16_force_relocation (fixS *fix) 486 { 487 if (generic_force_reloc (fix) || SWITCH_TABLE (fix)) 488 return 1; 489 490 return 0; 491 } 492 493 /* Record a fixup for a cons expression. */ 494 495 void 496 cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp) 497 { 498 int rtype = BFD_RELOC_UNUSED; 499 500 switch (len) 501 { 502 default: rtype = BFD_RELOC_NONE; break; 503 case 1: rtype = BFD_RELOC_CR16_NUM8 ; break; 504 case 2: rtype = BFD_RELOC_CR16_NUM16; break; 505 case 4: 506 if (code_label) 507 { 508 rtype = BFD_RELOC_CR16_NUM32a; 509 code_label = 0; 510 } 511 else 512 rtype = BFD_RELOC_CR16_NUM32; 513 break; 514 } 515 516 fix_new_exp (frag, offset, len, exp, 0, rtype); 517 } 518 519 /* Generate a relocation entry for a fixup. */ 520 521 arelent * 522 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP) 523 { 524 arelent * reloc; 525 bfd_reloc_code_real_type code; 526 527 /* If symbols are local and resolved, then no relocation needed. */ 528 if ( ((fixP->fx_addsy) 529 && (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section)) 530 || ((fixP->fx_subsy) 531 && (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section))) 532 return NULL; 533 534 reloc = xmalloc (sizeof (arelent)); 535 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); 536 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 537 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; 538 reloc->addend = fixP->fx_offset; 539 540 if (fixP->fx_subsy != NULL) 541 { 542 if (SWITCH_TABLE (fixP)) 543 { 544 /* Keep the current difference in the addend. */ 545 reloc->addend = (S_GET_VALUE (fixP->fx_addsy) 546 - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset); 547 548 switch (fixP->fx_r_type) 549 { 550 case BFD_RELOC_CR16_NUM8: 551 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH8; 552 break; 553 case BFD_RELOC_CR16_NUM16: 554 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH16; 555 break; 556 case BFD_RELOC_CR16_NUM32: 557 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH32; 558 break; 559 case BFD_RELOC_CR16_NUM32a: 560 fixP->fx_r_type = BFD_RELOC_CR16_NUM32a; 561 break; 562 default: 563 abort (); 564 break; 565 } 566 } 567 else 568 { 569 /* We only resolve difference expressions in the same section. */ 570 as_bad_where (fixP->fx_file, fixP->fx_line, 571 _("can't resolve `%s' {%s section} - `%s' {%s section}"), 572 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0", 573 segment_name (fixP->fx_addsy 574 ? S_GET_SEGMENT (fixP->fx_addsy) 575 : absolute_section), 576 S_GET_NAME (fixP->fx_subsy), 577 segment_name (S_GET_SEGMENT (fixP->fx_addsy))); 578 } 579 } 580 #ifdef OBJ_ELF 581 if ((fixP->fx_r_type == BFD_RELOC_CR16_GOT_REGREL20) 582 && GOT_symbol 583 && fixP->fx_addsy == GOT_symbol) 584 { 585 code = BFD_RELOC_CR16_GOT_REGREL20; 586 reloc->addend = fixP->fx_offset = reloc->address; 587 } 588 else if ((fixP->fx_r_type == BFD_RELOC_CR16_GOTC_REGREL20) 589 && GOT_symbol 590 && fixP->fx_addsy == GOT_symbol) 591 { 592 code = BFD_RELOC_CR16_GOTC_REGREL20; 593 reloc->addend = fixP->fx_offset = reloc->address; 594 } 595 #endif 596 597 gas_assert ((int) fixP->fx_r_type > 0); 598 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 599 600 if (reloc->howto == NULL) 601 { 602 as_bad_where (fixP->fx_file, fixP->fx_line, 603 _("internal error: reloc %d (`%s') not supported by object file format"), 604 fixP->fx_r_type, 605 bfd_get_reloc_code_name (fixP->fx_r_type)); 606 return NULL; 607 } 608 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); 609 610 return reloc; 611 } 612 613 /* Prepare machine-dependent frags for relaxation. */ 614 615 int 616 md_estimate_size_before_relax (fragS *fragp, asection *seg) 617 { 618 /* If symbol is undefined or located in a different section, 619 select the largest supported relocation. */ 620 relax_substateT subtype; 621 relax_substateT rlx_state[] = {0, 2}; 622 623 for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2) 624 { 625 if (fragp->fr_subtype == rlx_state[subtype] 626 && (!S_IS_DEFINED (fragp->fr_symbol) 627 || seg != S_GET_SEGMENT (fragp->fr_symbol))) 628 { 629 fragp->fr_subtype = rlx_state[subtype + 1]; 630 break; 631 } 632 } 633 634 if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table)) 635 abort (); 636 637 return md_relax_table[fragp->fr_subtype].rlx_length; 638 } 639 640 void 641 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP) 642 { 643 /* 'opcode' points to the start of the instruction, whether 644 we need to change the instruction's fixed encoding. */ 645 char *opcode = fragP->fr_literal + fragP->fr_fix; 646 bfd_reloc_code_real_type reloc; 647 648 subseg_change (sec, 0); 649 650 switch (fragP->fr_subtype) 651 { 652 case 0: 653 reloc = BFD_RELOC_CR16_DISP8; 654 break; 655 case 1: 656 /* If the subtype is not changed due to :m operand qualifier, 657 then no need to update the opcode value. */ 658 if ((int)opcode[1] != 0x18) 659 { 660 opcode[0] = (opcode[0] & 0xf0); 661 opcode[1] = 0x18; 662 } 663 reloc = BFD_RELOC_CR16_DISP16; 664 break; 665 case 2: 666 /* If the subtype is not changed due to :l operand qualifier, 667 then no need to update the opcode value. */ 668 if ((int)opcode[1] != 0) 669 { 670 opcode[2] = opcode[0]; 671 opcode[0] = opcode[1]; 672 opcode[1] = 0x0; 673 } 674 reloc = BFD_RELOC_CR16_DISP24; 675 break; 676 default: 677 abort(); 678 } 679 680 fix_new (fragP, fragP->fr_fix, 681 bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)), 682 fragP->fr_symbol, fragP->fr_offset, 1, reloc); 683 fragP->fr_var = 0; 684 fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length; 685 } 686 687 symbolS * 688 md_undefined_symbol (char *name) 689 { 690 if (*name == '_' && *(name + 1) == 'G' 691 && strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0) 692 { 693 if (!GOT_symbol) 694 { 695 if (symbol_find (name)) 696 as_bad (_("GOT already in symbol table")); 697 GOT_symbol = symbol_new (name, undefined_section, 698 (valueT) 0, &zero_address_frag); 699 } 700 return GOT_symbol; 701 } 702 return 0; 703 } 704 705 /* Process machine-dependent command line options. Called once for 706 each option on the command line that the machine-independent part of 707 GAS does not understand. */ 708 709 int 710 md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED) 711 { 712 return 0; 713 } 714 715 /* Machine-dependent usage-output. */ 716 717 void 718 md_show_usage (FILE *stream ATTRIBUTE_UNUSED) 719 { 720 return; 721 } 722 723 char * 724 md_atof (int type, char *litP, int *sizeP) 725 { 726 return ieee_md_atof (type, litP, sizeP, target_big_endian); 727 } 728 729 /* Apply a fixS (fixup of an instruction or data that we didn't have 730 enough info to complete immediately) to the data in a frag. 731 Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable 732 relaxation of debug sections, this function is called only when 733 fixuping relocations of debug sections. */ 734 735 void 736 md_apply_fix (fixS *fixP, valueT *valP, segT seg) 737 { 738 valueT val = * valP; 739 740 if (fixP->fx_addsy == NULL 741 && fixP->fx_pcrel == 0) 742 fixP->fx_done = 1; 743 else if (fixP->fx_pcrel == 1 744 && fixP->fx_addsy != NULL 745 && S_GET_SEGMENT (fixP->fx_addsy) == seg) 746 fixP->fx_done = 1; 747 else 748 fixP->fx_done = 0; 749 750 if (fixP->fx_addsy != NULL && !fixP->fx_pcrel) 751 { 752 val = fixP->fx_offset; 753 fixP->fx_done = 1; 754 } 755 756 if (fixP->fx_done) 757 { 758 char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; 759 760 fixP->fx_offset = 0; 761 762 switch (fixP->fx_r_type) 763 { 764 case BFD_RELOC_CR16_NUM8: 765 bfd_put_8 (stdoutput, (unsigned char) val, buf); 766 break; 767 case BFD_RELOC_CR16_NUM16: 768 bfd_put_16 (stdoutput, val, buf); 769 break; 770 case BFD_RELOC_CR16_NUM32: 771 bfd_put_32 (stdoutput, val, buf); 772 break; 773 case BFD_RELOC_CR16_NUM32a: 774 bfd_put_32 (stdoutput, val, buf); 775 break; 776 default: 777 /* We shouldn't ever get here because linkrelax is nonzero. */ 778 abort (); 779 break; 780 } 781 fixP->fx_done = 0; 782 } 783 else 784 fixP->fx_offset = * valP; 785 } 786 787 /* The location from which a PC relative jump should be calculated, 788 given a PC relative reloc. */ 789 790 long 791 md_pcrel_from (fixS *fixp) 792 { 793 return fixp->fx_frag->fr_address + fixp->fx_where; 794 } 795 796 static void 797 initialise_reg_hash_table (struct hash_control ** hash_table, 798 const reg_entry * register_table, 799 const unsigned int num_entries) 800 { 801 const reg_entry * rreg; 802 const char *hashret; 803 804 if ((* hash_table = hash_new ()) == NULL) 805 as_fatal (_("Virtual memory exhausted")); 806 807 for (rreg = register_table; 808 rreg < (register_table + num_entries); 809 rreg++) 810 { 811 hashret = hash_insert (* hash_table, rreg->name, (char *) rreg); 812 if (hashret) 813 as_fatal (_("Internal Error: Can't hash %s: %s"), 814 rreg->name, hashret); 815 } 816 } 817 818 /* This function is called once, at assembler startup time. This should 819 set up all the tables, etc that the MD part of the assembler needs. */ 820 821 void 822 md_begin (void) 823 { 824 int i = 0; 825 826 /* Set up a hash table for the instructions. */ 827 if ((cr16_inst_hash = hash_new ()) == NULL) 828 as_fatal (_("Virtual memory exhausted")); 829 830 while (cr16_instruction[i].mnemonic != NULL) 831 { 832 const char *hashret; 833 const char *mnemonic = cr16_instruction[i].mnemonic; 834 835 hashret = hash_insert (cr16_inst_hash, mnemonic, 836 (char *)(cr16_instruction + i)); 837 838 if (hashret != NULL && *hashret != '\0') 839 as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction[i].mnemonic, 840 *hashret == 0 ? _("(unknown reason)") : hashret); 841 842 /* Insert unique names into hash table. The CR16 instruction set 843 has many identical opcode names that have different opcodes based 844 on the operands. This hash table then provides a quick index to 845 the first opcode with a particular name in the opcode table. */ 846 do 847 { 848 ++i; 849 } 850 while (cr16_instruction[i].mnemonic != NULL 851 && streq (cr16_instruction[i].mnemonic, mnemonic)); 852 } 853 854 /* Initialize reg_hash hash table. */ 855 initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS); 856 /* Initialize regp_hash hash table. */ 857 initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS); 858 /* Initialize preg_hash hash table. */ 859 initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS); 860 /* Initialize pregp_hash hash table. */ 861 initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS); 862 863 /* Set linkrelax here to avoid fixups in most sections. */ 864 linkrelax = 1; 865 } 866 867 /* Process constants (immediate/absolute) 868 and labels (jump targets/Memory locations). */ 869 870 static void 871 process_label_constant (char *str, ins * cr16_ins) 872 { 873 char *saved_input_line_pointer; 874 int symbol_with_at = 0; 875 int symbol_with_s = 0; 876 int symbol_with_m = 0; 877 int symbol_with_l = 0; 878 int symbol_with_at_got = 0; 879 int symbol_with_at_gotc = 0; 880 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */ 881 882 saved_input_line_pointer = input_line_pointer; 883 input_line_pointer = str; 884 885 expression (&cr16_ins->exp); 886 887 switch (cr16_ins->exp.X_op) 888 { 889 case O_big: 890 case O_absent: 891 /* Missing or bad expr becomes absolute 0. */ 892 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 893 str); 894 cr16_ins->exp.X_op = O_constant; 895 cr16_ins->exp.X_add_number = 0; 896 cr16_ins->exp.X_add_symbol = NULL; 897 cr16_ins->exp.X_op_symbol = NULL; 898 /* Fall through. */ 899 900 case O_constant: 901 cur_arg->X_op = O_constant; 902 cur_arg->constant = cr16_ins->exp.X_add_number; 903 break; 904 905 case O_symbol: 906 case O_subtract: 907 case O_add: 908 cur_arg->X_op = O_symbol; 909 cur_arg->constant = cr16_ins->exp.X_add_number; 910 cr16_ins->exp.X_add_number = 0; 911 cr16_ins->rtype = BFD_RELOC_NONE; 912 relocatable = 1; 913 914 if (strneq (input_line_pointer, "@c", 2)) 915 symbol_with_at = 1; 916 917 if (strneq (input_line_pointer, "@l", 2) 918 || strneq (input_line_pointer, ":l", 2)) 919 symbol_with_l = 1; 920 921 if (strneq (input_line_pointer, "@m", 2) 922 || strneq (input_line_pointer, ":m", 2)) 923 symbol_with_m = 1; 924 925 if (strneq (input_line_pointer, "@s", 2) 926 || strneq (input_line_pointer, ":s", 2)) 927 symbol_with_s = 1; 928 929 if (strneq (input_line_pointer, "@cGOT", 5) 930 || strneq (input_line_pointer, "@cgot", 5)) 931 { 932 if (GOT_symbol == NULL) 933 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 934 935 symbol_with_at_gotc = 1; 936 } 937 else if (strneq (input_line_pointer, "@GOT", 4) 938 || strneq (input_line_pointer, "@got", 4)) 939 { 940 if ((strneq (input_line_pointer, "+", 1)) 941 || (strneq (input_line_pointer, "-", 1))) 942 as_warn (_("GOT bad expression with %s."), input_line_pointer); 943 944 if (GOT_symbol == NULL) 945 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 946 947 symbol_with_at_got = 1; 948 } 949 950 switch (cur_arg->type) 951 { 952 case arg_cr: 953 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 954 { 955 if (symbol_with_at_got) 956 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 957 else if (symbol_with_at_gotc) 958 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 959 else if (cur_arg->size == 20) 960 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 961 else 962 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a; 963 } 964 break; 965 966 case arg_crp: 967 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 968 { 969 if (symbol_with_at_got) 970 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 971 else if (symbol_with_at_gotc) 972 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 973 } else { 974 switch (instruction->size) 975 { 976 case 1: 977 switch (cur_arg->size) 978 { 979 case 0: 980 cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; 981 break; 982 case 4: 983 if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb")) 984 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4; 985 else 986 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a; 987 break; 988 default: break; 989 } 990 break; 991 case 2: 992 cr16_ins->rtype = BFD_RELOC_CR16_REGREL16; 993 break; 994 case 3: 995 if (cur_arg->size == 20) 996 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 997 else 998 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a; 999 break; 1000 default: 1001 break; 1002 } 1003 } 1004 break; 1005 1006 case arg_idxr: 1007 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 1008 { 1009 if (symbol_with_at_got) 1010 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1011 else if (symbol_with_at_gotc) 1012 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1013 else 1014 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 1015 } 1016 break; 1017 1018 case arg_idxrp: 1019 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 1020 { 1021 if (symbol_with_at_got) 1022 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1023 else if (symbol_with_at_gotc) 1024 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1025 else { 1026 switch (instruction->size) 1027 { 1028 case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break; 1029 case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break; 1030 case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break; 1031 default: break; 1032 } 1033 } 1034 } 1035 break; 1036 1037 case arg_c: 1038 if (IS_INSN_MNEMONIC ("bal")) 1039 cr16_ins->rtype = BFD_RELOC_CR16_DISP24; 1040 else if (IS_INSN_TYPE (BRANCH_INS)) 1041 { 1042 if (symbol_with_l) 1043 cr16_ins->rtype = BFD_RELOC_CR16_DISP24; 1044 else if (symbol_with_m) 1045 cr16_ins->rtype = BFD_RELOC_CR16_DISP16; 1046 else 1047 cr16_ins->rtype = BFD_RELOC_CR16_DISP8; 1048 } 1049 else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS) 1050 || IS_INSN_TYPE (CSTBIT_INS)) 1051 { 1052 if (symbol_with_s) 1053 as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str); 1054 if (symbol_with_at_got) 1055 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1056 else if (symbol_with_at_gotc) 1057 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1058 else if (symbol_with_m) 1059 cr16_ins->rtype = BFD_RELOC_CR16_ABS20; 1060 else /* Default to (symbol_with_l) */ 1061 cr16_ins->rtype = BFD_RELOC_CR16_ABS24; 1062 } 1063 else if (IS_INSN_TYPE (BRANCH_NEQ_INS)) 1064 cr16_ins->rtype = BFD_RELOC_CR16_DISP4; 1065 break; 1066 1067 case arg_ic: 1068 if (IS_INSN_TYPE (ARITH_INS)) 1069 { 1070 if (symbol_with_at_got) 1071 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1072 else if (symbol_with_at_gotc) 1073 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1074 else if (symbol_with_s) 1075 cr16_ins->rtype = BFD_RELOC_CR16_IMM4; 1076 else if (symbol_with_m) 1077 cr16_ins->rtype = BFD_RELOC_CR16_IMM20; 1078 else if (symbol_with_at) 1079 cr16_ins->rtype = BFD_RELOC_CR16_IMM32a; 1080 else /* Default to (symbol_with_l) */ 1081 cr16_ins->rtype = BFD_RELOC_CR16_IMM32; 1082 } 1083 else if (IS_INSN_TYPE (ARITH_BYTE_INS)) 1084 { 1085 cr16_ins->rtype = BFD_RELOC_CR16_IMM16; 1086 } 1087 break; 1088 default: 1089 break; 1090 } 1091 break; 1092 1093 default: 1094 cur_arg->X_op = cr16_ins->exp.X_op; 1095 break; 1096 } 1097 1098 input_line_pointer = saved_input_line_pointer; 1099 return; 1100 } 1101 1102 /* Retrieve the opcode image of a given register. 1103 If the register is illegal for the current instruction, 1104 issue an error. */ 1105 1106 static int 1107 getreg_image (reg r) 1108 { 1109 const reg_entry *rreg; 1110 char *reg_name; 1111 int is_procreg = 0; /* Nonzero means argument should be processor reg. */ 1112 1113 /* Check whether the register is in registers table. */ 1114 if (r < MAX_REG) 1115 rreg = cr16_regtab + r; 1116 else /* Register not found. */ 1117 { 1118 as_bad (_("Unknown register: `%d'"), r); 1119 return 0; 1120 } 1121 1122 reg_name = rreg->name; 1123 1124 /* Issue a error message when register is illegal. */ 1125 #define IMAGE_ERR \ 1126 as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \ 1127 reg_name, ins_parse); \ 1128 break; 1129 1130 switch (rreg->type) 1131 { 1132 case CR16_R_REGTYPE: 1133 if (! is_procreg) 1134 return rreg->image; 1135 else 1136 IMAGE_ERR; 1137 1138 case CR16_P_REGTYPE: 1139 return rreg->image; 1140 break; 1141 1142 default: 1143 IMAGE_ERR; 1144 } 1145 1146 return 0; 1147 } 1148 1149 /* Parsing different types of operands 1150 -> constants Immediate/Absolute/Relative numbers 1151 -> Labels Relocatable symbols 1152 -> (reg pair base) Register pair base 1153 -> (rbase) Register base 1154 -> disp(rbase) Register relative 1155 -> [rinx]disp(reg pair) Register index with reg pair mode 1156 -> disp(rbase,ridx,scl) Register index mode. */ 1157 1158 static void 1159 set_operand (char *operand, ins * cr16_ins) 1160 { 1161 char *operandS; /* Pointer to start of sub-opearand. */ 1162 char *operandE; /* Pointer to end of sub-opearand. */ 1163 1164 argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */ 1165 1166 /* Initialize pointers. */ 1167 operandS = operandE = operand; 1168 1169 switch (cur_arg->type) 1170 { 1171 case arg_ic: /* Case $0x18. */ 1172 operandS++; 1173 case arg_c: /* Case 0x18. */ 1174 /* Set constant. */ 1175 process_label_constant (operandS, cr16_ins); 1176 1177 if (cur_arg->type != arg_ic) 1178 cur_arg->type = arg_c; 1179 break; 1180 1181 case arg_icr: /* Case $0x18(r1). */ 1182 operandS++; 1183 case arg_cr: /* Case 0x18(r1). */ 1184 /* Set displacement constant. */ 1185 while (*operandE != '(') 1186 operandE++; 1187 *operandE = '\0'; 1188 process_label_constant (operandS, cr16_ins); 1189 operandS = operandE; 1190 case arg_rbase: /* Case (r1) or (r1,r0). */ 1191 operandS++; 1192 /* Set register base. */ 1193 while (*operandE != ')') 1194 operandE++; 1195 *operandE = '\0'; 1196 if ((cur_arg->r = get_register (operandS)) == nullregister) 1197 as_bad (_("Illegal register `%s' in Instruction `%s'"), 1198 operandS, ins_parse); 1199 1200 /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */ 1201 if ((cur_arg->type != arg_rbase) 1202 && ((getreg_image (cur_arg->r) == 12) 1203 || (getreg_image (cur_arg->r) == 13) 1204 || (getreg_image (cur_arg->r) == 14) 1205 || (getreg_image (cur_arg->r) == 15))) 1206 { 1207 cur_arg->type = arg_crp; 1208 cur_arg->rp = cur_arg->r; 1209 } 1210 break; 1211 1212 case arg_crp: /* Case 0x18(r1,r0). */ 1213 /* Set displacement constant. */ 1214 while (*operandE != '(') 1215 operandE++; 1216 *operandE = '\0'; 1217 process_label_constant (operandS, cr16_ins); 1218 operandS = operandE; 1219 operandS++; 1220 /* Set register pair base. */ 1221 while (*operandE != ')') 1222 operandE++; 1223 *operandE = '\0'; 1224 if ((cur_arg->rp = get_register_pair (operandS)) == nullregister) 1225 as_bad (_("Illegal register pair `%s' in Instruction `%s'"), 1226 operandS, ins_parse); 1227 break; 1228 1229 case arg_idxr: 1230 /* Set register pair base. */ 1231 if ((strchr (operandS,'(') != NULL)) 1232 { 1233 while ((*operandE != '(') && (! ISSPACE (*operandE))) 1234 operandE++; 1235 if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister) 1236 as_bad (_("Illegal register pair `%s' in Instruction `%s'"), 1237 operandS, ins_parse); 1238 *operandE++ = '\0'; 1239 cur_arg->type = arg_idxrp; 1240 } 1241 else 1242 cur_arg->rp = -1; 1243 1244 operandE = operandS; 1245 /* Set displacement constant. */ 1246 while (*operandE != ']') 1247 operandE++; 1248 process_label_constant (++operandE, cr16_ins); 1249 *operandE++ = '\0'; 1250 operandE = operandS; 1251 1252 /* Set index register . */ 1253 operandS = strchr (operandE,'['); 1254 if (operandS != NULL) 1255 { /* Eliminate '[', detach from rest of operand. */ 1256 *operandS++ = '\0'; 1257 1258 operandE = strchr (operandS, ']'); 1259 1260 if (operandE == NULL) 1261 as_bad (_("unmatched '['")); 1262 else 1263 { /* Eliminate ']' and make sure it was the last thing 1264 in the string. */ 1265 *operandE = '\0'; 1266 if (*(operandE + 1) != '\0') 1267 as_bad (_("garbage after index spec ignored")); 1268 } 1269 } 1270 1271 if ((cur_arg->i_r = get_index_register (operandS)) == nullregister) 1272 as_bad (_("Illegal register `%s' in Instruction `%s'"), 1273 operandS, ins_parse); 1274 *operandE = '\0'; 1275 *operandS = '\0'; 1276 break; 1277 1278 default: 1279 break; 1280 } 1281 } 1282 1283 /* Parse a single operand. 1284 operand - Current operand to parse. 1285 cr16_ins - Current assembled instruction. */ 1286 1287 static void 1288 parse_operand (char *operand, ins * cr16_ins) 1289 { 1290 int ret_val; 1291 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */ 1292 1293 /* Initialize the type to NULL before parsing. */ 1294 cur_arg->type = nullargs; 1295 1296 /* Check whether this is a condition code . */ 1297 if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1)) 1298 { 1299 cur_arg->type = arg_cc; 1300 cur_arg->cc = ret_val; 1301 cur_arg->X_op = O_register; 1302 return; 1303 } 1304 1305 /* Check whether this is a general processor register. */ 1306 if ((ret_val = get_register (operand)) != nullregister) 1307 { 1308 cur_arg->type = arg_r; 1309 cur_arg->r = ret_val; 1310 cur_arg->X_op = 0; 1311 return; 1312 } 1313 1314 /* Check whether this is a general processor register pair. */ 1315 if ((operand[0] == '(') 1316 && ((ret_val = get_register_pair (operand)) != nullregister)) 1317 { 1318 cur_arg->type = arg_rp; 1319 cur_arg->rp = ret_val; 1320 cur_arg->X_op = O_register; 1321 return; 1322 } 1323 1324 /* Check whether the operand is a processor register. 1325 For "lprd" and "sprd" instruction, only 32 bit 1326 processor registers used. */ 1327 if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd"))) 1328 && ((ret_val = get_pregister (operand)) != nullpregister)) 1329 { 1330 cur_arg->type = arg_pr; 1331 cur_arg->pr = ret_val; 1332 cur_arg->X_op = O_register; 1333 return; 1334 } 1335 1336 /* Check whether this is a processor register - 32 bit. */ 1337 if ((ret_val = get_pregisterp (operand)) != nullpregister) 1338 { 1339 cur_arg->type = arg_prp; 1340 cur_arg->prp = ret_val; 1341 cur_arg->X_op = O_register; 1342 return; 1343 } 1344 1345 /* Deal with special characters. */ 1346 switch (operand[0]) 1347 { 1348 case '$': 1349 if (strchr (operand, '(') != NULL) 1350 cur_arg->type = arg_icr; 1351 else 1352 cur_arg->type = arg_ic; 1353 goto set_params; 1354 break; 1355 1356 case '(': 1357 cur_arg->type = arg_rbase; 1358 goto set_params; 1359 break; 1360 1361 case '[': 1362 cur_arg->type = arg_idxr; 1363 goto set_params; 1364 break; 1365 1366 default: 1367 break; 1368 } 1369 1370 if (strchr (operand, '(') != NULL) 1371 { 1372 if (strchr (operand, ',') != NULL 1373 && (strchr (operand, ',') > strchr (operand, '('))) 1374 cur_arg->type = arg_crp; 1375 else 1376 cur_arg->type = arg_cr; 1377 } 1378 else 1379 cur_arg->type = arg_c; 1380 1381 /* Parse an operand according to its type. */ 1382 set_params: 1383 cur_arg->constant = 0; 1384 set_operand (operand, cr16_ins); 1385 } 1386 1387 /* Parse the various operands. Each operand is then analyzed to fillup 1388 the fields in the cr16_ins data structure. */ 1389 1390 static void 1391 parse_operands (ins * cr16_ins, char *operands) 1392 { 1393 char *operandS; /* Operands string. */ 1394 char *operandH, *operandT; /* Single operand head/tail pointers. */ 1395 int allocated = 0; /* Indicates a new operands string was allocated.*/ 1396 char *operand[MAX_OPERANDS];/* Separating the operands. */ 1397 int op_num = 0; /* Current operand number we are parsing. */ 1398 int bracket_flag = 0; /* Indicates a bracket '(' was found. */ 1399 int sq_bracket_flag = 0; /* Indicates a square bracket '[' was found. */ 1400 1401 /* Preprocess the list of registers, if necessary. */ 1402 operandS = operandH = operandT = operands; 1403 1404 while (*operandT != '\0') 1405 { 1406 if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1) 1407 { 1408 *operandT++ = '\0'; 1409 operand[op_num++] = strdup (operandH); 1410 operandH = operandT; 1411 continue; 1412 } 1413 1414 if (*operandT == ' ') 1415 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse); 1416 1417 if (*operandT == '(') 1418 bracket_flag = 1; 1419 else if (*operandT == '[') 1420 sq_bracket_flag = 1; 1421 1422 if (*operandT == ')') 1423 { 1424 if (bracket_flag) 1425 bracket_flag = 0; 1426 else 1427 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1428 } 1429 else if (*operandT == ']') 1430 { 1431 if (sq_bracket_flag) 1432 sq_bracket_flag = 0; 1433 else 1434 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1435 } 1436 1437 if (bracket_flag == 1 && *operandT == ')') 1438 bracket_flag = 0; 1439 else if (sq_bracket_flag == 1 && *operandT == ']') 1440 sq_bracket_flag = 0; 1441 1442 operandT++; 1443 } 1444 1445 /* Adding the last operand. */ 1446 operand[op_num++] = strdup (operandH); 1447 cr16_ins->nargs = op_num; 1448 1449 /* Verifying correct syntax of operands (all brackets should be closed). */ 1450 if (bracket_flag || sq_bracket_flag) 1451 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1452 1453 /* Now we parse each operand separately. */ 1454 for (op_num = 0; op_num < cr16_ins->nargs; op_num++) 1455 { 1456 cur_arg_num = op_num; 1457 parse_operand (operand[op_num], cr16_ins); 1458 free (operand[op_num]); 1459 } 1460 1461 if (allocated) 1462 free (operandS); 1463 } 1464 1465 /* Get the trap index in dispatch table, given its name. 1466 This routine is used by assembling the 'excp' instruction. */ 1467 1468 static int 1469 gettrap (char *s) 1470 { 1471 const trap_entry *trap; 1472 1473 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++) 1474 if (strcasecmp (trap->name, s) == 0) 1475 return trap->entry; 1476 1477 /* To make compatable with CR16 4.1 tools, the below 3-lines of 1478 * code added. Refer: Development Tracker item #123 */ 1479 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++) 1480 if (trap->entry == (unsigned int) atoi (s)) 1481 return trap->entry; 1482 1483 as_bad (_("Unknown exception: `%s'"), s); 1484 return 0; 1485 } 1486 1487 /* Top level module where instruction parsing starts. 1488 cr16_ins - data structure holds some information. 1489 operands - holds the operands part of the whole instruction. */ 1490 1491 static void 1492 parse_insn (ins *insn, char *operands) 1493 { 1494 int i; 1495 1496 /* Handle instructions with no operands. */ 1497 for (i = 0; cr16_no_op_insn[i] != NULL; i++) 1498 { 1499 if (streq (cr16_no_op_insn[i], instruction->mnemonic)) 1500 { 1501 insn->nargs = 0; 1502 return; 1503 } 1504 } 1505 1506 /* Handle 'excp' instructions. */ 1507 if (IS_INSN_MNEMONIC ("excp")) 1508 { 1509 insn->nargs = 1; 1510 insn->arg[0].type = arg_ic; 1511 insn->arg[0].constant = gettrap (operands); 1512 insn->arg[0].X_op = O_constant; 1513 return; 1514 } 1515 1516 if (operands != NULL) 1517 parse_operands (insn, operands); 1518 } 1519 1520 /* bCC instruction requires special handling. */ 1521 static char * 1522 get_b_cc (char * op) 1523 { 1524 unsigned int i; 1525 char op1[5]; 1526 1527 for (i = 1; i < strlen (op); i++) 1528 op1[i-1] = op[i]; 1529 1530 op1[i-1] = '\0'; 1531 1532 for (i = 0; i < cr16_num_cc ; i++) 1533 if (streq (op1, cr16_b_cond_tab[i])) 1534 return (char *) cr16_b_cond_tab[i]; 1535 1536 return NULL; 1537 } 1538 1539 /* bCC instruction requires special handling. */ 1540 static int 1541 is_bcc_insn (char * op) 1542 { 1543 if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b") 1544 || streq (op, "beq0w") || streq (op, "bnq0w"))) 1545 if ((op[0] == 'b') && (get_b_cc (op) != NULL)) 1546 return 1; 1547 return 0; 1548 } 1549 1550 /* Cinv instruction requires special handling. */ 1551 1552 static int 1553 check_cinv_options (char * operand) 1554 { 1555 char *p = operand; 1556 int i_used = 0, u_used = 0, d_used = 0; 1557 1558 while (*++p != ']') 1559 { 1560 if (*p == ',' || *p == ' ') 1561 continue; 1562 1563 else if (*p == 'i') 1564 i_used = 1; 1565 else if (*p == 'u') 1566 u_used = 1; 1567 else if (*p == 'd') 1568 d_used = 1; 1569 else 1570 as_bad (_("Illegal `cinv' parameter: `%c'"), *p); 1571 } 1572 1573 return 0; 1574 } 1575 1576 /* Retrieve the opcode image of a given register pair. 1577 If the register is illegal for the current instruction, 1578 issue an error. */ 1579 1580 static int 1581 getregp_image (reg r) 1582 { 1583 const reg_entry *rreg; 1584 char *reg_name; 1585 1586 /* Check whether the register is in registers table. */ 1587 if (r < MAX_REG) 1588 rreg = cr16_regptab + r; 1589 /* Register not found. */ 1590 else 1591 { 1592 as_bad (_("Unknown register pair: `%d'"), r); 1593 return 0; 1594 } 1595 1596 reg_name = rreg->name; 1597 1598 /* Issue a error message when register pair is illegal. */ 1599 #define RPAIR_IMAGE_ERR \ 1600 as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \ 1601 reg_name, ins_parse); \ 1602 break; 1603 1604 switch (rreg->type) 1605 { 1606 case CR16_RP_REGTYPE: 1607 return rreg->image; 1608 default: 1609 RPAIR_IMAGE_ERR; 1610 } 1611 1612 return 0; 1613 } 1614 1615 /* Retrieve the opcode image of a given index register pair. 1616 If the register is illegal for the current instruction, 1617 issue an error. */ 1618 1619 static int 1620 getidxregp_image (reg r) 1621 { 1622 const reg_entry *rreg; 1623 char *reg_name; 1624 1625 /* Check whether the register is in registers table. */ 1626 if (r < MAX_REG) 1627 rreg = cr16_regptab + r; 1628 /* Register not found. */ 1629 else 1630 { 1631 as_bad (_("Unknown register pair: `%d'"), r); 1632 return 0; 1633 } 1634 1635 reg_name = rreg->name; 1636 1637 /* Issue a error message when register pair is illegal. */ 1638 #define IDX_RPAIR_IMAGE_ERR \ 1639 as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \ 1640 reg_name, ins_parse); \ 1641 1642 if (rreg->type == CR16_RP_REGTYPE) 1643 { 1644 switch (rreg->image) 1645 { 1646 case 0: return 0; break; 1647 case 2: return 1; break; 1648 case 4: return 2; break; 1649 case 6: return 3; break; 1650 case 8: return 4; break; 1651 case 10: return 5; break; 1652 case 3: return 6; break; 1653 case 5: return 7; break; 1654 default: 1655 break; 1656 } 1657 } 1658 1659 IDX_RPAIR_IMAGE_ERR; 1660 return 0; 1661 } 1662 1663 /* Retrieve the opcode image of a given processort register. 1664 If the register is illegal for the current instruction, 1665 issue an error. */ 1666 static int 1667 getprocreg_image (reg r) 1668 { 1669 const reg_entry *rreg; 1670 char *reg_name; 1671 1672 /* Check whether the register is in registers table. */ 1673 if (r >= MAX_REG && r < MAX_PREG) 1674 rreg = &cr16_pregtab[r - MAX_REG]; 1675 /* Register not found. */ 1676 else 1677 { 1678 as_bad (_("Unknown processor register : `%d'"), r); 1679 return 0; 1680 } 1681 1682 reg_name = rreg->name; 1683 1684 /* Issue a error message when register pair is illegal. */ 1685 #define PROCREG_IMAGE_ERR \ 1686 as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \ 1687 reg_name, ins_parse); \ 1688 break; 1689 1690 switch (rreg->type) 1691 { 1692 case CR16_P_REGTYPE: 1693 return rreg->image; 1694 default: 1695 PROCREG_IMAGE_ERR; 1696 } 1697 1698 return 0; 1699 } 1700 1701 /* Retrieve the opcode image of a given processort register. 1702 If the register is illegal for the current instruction, 1703 issue an error. */ 1704 static int 1705 getprocregp_image (reg r) 1706 { 1707 const reg_entry *rreg; 1708 char *reg_name; 1709 int pregptab_disp = 0; 1710 1711 /* Check whether the register is in registers table. */ 1712 if (r >= MAX_REG && r < MAX_PREG) 1713 { 1714 r = r - MAX_REG; 1715 switch (r) 1716 { 1717 case 4: pregptab_disp = 1; break; 1718 case 6: pregptab_disp = 2; break; 1719 case 8: 1720 case 9: 1721 case 10: 1722 pregptab_disp = 3; break; 1723 case 12: 1724 pregptab_disp = 4; break; 1725 case 14: 1726 pregptab_disp = 5; break; 1727 default: break; 1728 } 1729 rreg = &cr16_pregptab[r - pregptab_disp]; 1730 } 1731 /* Register not found. */ 1732 else 1733 { 1734 as_bad (_("Unknown processor register (32 bit) : `%d'"), r); 1735 return 0; 1736 } 1737 1738 reg_name = rreg->name; 1739 1740 /* Issue a error message when register pair is illegal. */ 1741 #define PROCREGP_IMAGE_ERR \ 1742 as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\ 1743 reg_name, ins_parse); \ 1744 break; 1745 1746 switch (rreg->type) 1747 { 1748 case CR16_P_REGTYPE: 1749 return rreg->image; 1750 default: 1751 PROCREGP_IMAGE_ERR; 1752 } 1753 1754 return 0; 1755 } 1756 1757 /* Routine used to represent integer X using NBITS bits. */ 1758 1759 static long 1760 getconstant (long x, int nbits) 1761 { 1762 /* The following expression avoids overflow if 1763 'nbits' is the number of bits in 'bfd_vma'. */ 1764 return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1)); 1765 } 1766 1767 /* Print a constant value to 'output_opcode': 1768 ARG holds the operand's type and value. 1769 SHIFT represents the location of the operand to be print into. 1770 NBITS determines the size (in bits) of the constant. */ 1771 1772 static void 1773 print_constant (int nbits, int shift, argument *arg) 1774 { 1775 unsigned long mask = 0; 1776 1777 long constant = getconstant (arg->constant, nbits); 1778 1779 switch (nbits) 1780 { 1781 case 32: 1782 case 28: 1783 /* mask the upper part of the constant, that is, the bits 1784 going to the lowest byte of output_opcode[0]. 1785 The upper part of output_opcode[1] is always filled, 1786 therefore it is always masked with 0xFFFF. */ 1787 mask = (1 << (nbits - 16)) - 1; 1788 /* Divide the constant between two consecutive words : 1789 0 1 2 3 1790 +---------+---------+---------+---------+ 1791 | | X X X X | x X x X | | 1792 +---------+---------+---------+---------+ 1793 output_opcode[0] output_opcode[1] */ 1794 1795 CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0); 1796 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1797 break; 1798 1799 case 21: 1800 if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) nbits = 20; 1801 case 24: 1802 case 22: 1803 case 20: 1804 /* mask the upper part of the constant, that is, the bits 1805 going to the lowest byte of output_opcode[0]. 1806 The upper part of output_opcode[1] is always filled, 1807 therefore it is always masked with 0xFFFF. */ 1808 mask = (1 << (nbits - 16)) - 1; 1809 /* Divide the constant between two consecutive words : 1810 0 1 2 3 1811 +---------+---------+---------+---------+ 1812 | | X X X X | - X - X | | 1813 +---------+---------+---------+---------+ 1814 output_opcode[0] output_opcode[1] */ 1815 1816 if ((instruction->size > 2) && (shift == WORD_SHIFT)) 1817 { 1818 if (arg->type == arg_idxrp) 1819 { 1820 CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0); 1821 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1822 } 1823 else 1824 { 1825 CR16_PRINT (0, (((((constant >> WORD_SHIFT) & mask) << 8) & 0x0f00) | ((((constant >> WORD_SHIFT) & mask) >> 4) & 0xf)),0); 1826 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1827 } 1828 } 1829 else 1830 CR16_PRINT (0, constant, shift); 1831 break; 1832 1833 case 14: 1834 if (arg->type == arg_idxrp) 1835 { 1836 if (instruction->size == 2) 1837 { 1838 CR16_PRINT (0, ((constant) & 0xf), shift); /* 0-3 bits. */ 1839 CR16_PRINT (0, ((constant >> 4) & 0x3), (shift + 20)); /* 4-5 bits. */ 1840 CR16_PRINT (0, ((constant >> 6) & 0x3), (shift + 14)); /* 6-7 bits. */ 1841 CR16_PRINT (0, ((constant >> 8) & 0x3f), (shift + 8)); /* 8-13 bits. */ 1842 } 1843 else 1844 CR16_PRINT (0, constant, shift); 1845 } 1846 break; 1847 1848 case 16: 1849 case 12: 1850 /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is 1851 always filling the upper part of output_opcode[1]. If we mistakenly 1852 write it to output_opcode[0], the constant prefix (that is, 'match') 1853 will be overriden. 1854 0 1 2 3 1855 +---------+---------+---------+---------+ 1856 | 'match' | | X X X X | | 1857 +---------+---------+---------+---------+ 1858 output_opcode[0] output_opcode[1] */ 1859 1860 if ((instruction->size > 2) && (shift == WORD_SHIFT)) 1861 CR16_PRINT (1, constant, WORD_SHIFT); 1862 else 1863 CR16_PRINT (0, constant, shift); 1864 break; 1865 1866 case 8: 1867 CR16_PRINT (0, ((constant / 2) & 0xf), shift); 1868 CR16_PRINT (0, ((constant / 2) >> 4), (shift + 8)); 1869 break; 1870 1871 default: 1872 CR16_PRINT (0, constant, shift); 1873 break; 1874 } 1875 } 1876 1877 /* Print an operand to 'output_opcode', which later on will be 1878 printed to the object file: 1879 ARG holds the operand's type, size and value. 1880 SHIFT represents the printing location of operand. 1881 NBITS determines the size (in bits) of a constant operand. */ 1882 1883 static void 1884 print_operand (int nbits, int shift, argument *arg) 1885 { 1886 switch (arg->type) 1887 { 1888 case arg_cc: 1889 CR16_PRINT (0, arg->cc, shift); 1890 break; 1891 1892 case arg_r: 1893 CR16_PRINT (0, getreg_image (arg->r), shift); 1894 break; 1895 1896 case arg_rp: 1897 CR16_PRINT (0, getregp_image (arg->rp), shift); 1898 break; 1899 1900 case arg_pr: 1901 CR16_PRINT (0, getprocreg_image (arg->pr), shift); 1902 break; 1903 1904 case arg_prp: 1905 CR16_PRINT (0, getprocregp_image (arg->prp), shift); 1906 break; 1907 1908 case arg_idxrp: 1909 /* 16 12 8 6 0 1910 +-----------------------------+ 1911 | r_index | disp | rp_base | 1912 +-----------------------------+ */ 1913 1914 if (instruction->size == 3) 1915 { 1916 CR16_PRINT (0, getidxregp_image (arg->rp), 0); 1917 if (getreg_image (arg->i_r) == 12) 1918 CR16_PRINT (0, 0, 3); 1919 else 1920 CR16_PRINT (0, 1, 3); 1921 } 1922 else 1923 { 1924 CR16_PRINT (0, getidxregp_image (arg->rp), 16); 1925 if (getreg_image (arg->i_r) == 12) 1926 CR16_PRINT (0, 0, 19); 1927 else 1928 CR16_PRINT (0, 1, 19); 1929 } 1930 print_constant (nbits, shift, arg); 1931 break; 1932 1933 case arg_idxr: 1934 if (getreg_image (arg->i_r) == 12) 1935 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb") 1936 || IS_INSN_MNEMONIC ("tbitb")) 1937 CR16_PRINT (0, 0, 23); 1938 else CR16_PRINT (0, 0, 24); 1939 else 1940 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb") 1941 || IS_INSN_MNEMONIC ("tbitb")) 1942 CR16_PRINT (0, 1, 23); 1943 else CR16_PRINT (0, 1, 24); 1944 1945 print_constant (nbits, shift, arg); 1946 break; 1947 1948 case arg_ic: 1949 case arg_c: 1950 print_constant (nbits, shift, arg); 1951 break; 1952 1953 case arg_rbase: 1954 CR16_PRINT (0, getreg_image (arg->r), shift); 1955 break; 1956 1957 case arg_cr: 1958 print_constant (nbits, shift , arg); 1959 /* Add the register argument to the output_opcode. */ 1960 CR16_PRINT (0, getreg_image (arg->r), (shift+16)); 1961 break; 1962 1963 case arg_crp: 1964 print_constant (nbits, shift , arg); 1965 if (instruction->size > 1) 1966 CR16_PRINT (0, getregp_image (arg->rp), (shift + 16)); 1967 else if (IS_INSN_TYPE (LD_STOR_INS) || (IS_INSN_TYPE (CSTBIT_INS))) 1968 { 1969 if (instruction->size == 2) 1970 CR16_PRINT (0, getregp_image (arg->rp), (shift - 8)); 1971 else if (instruction->size == 1) 1972 CR16_PRINT (0, getregp_image (arg->rp), 16); 1973 } 1974 else 1975 CR16_PRINT (0, getregp_image (arg->rp), shift); 1976 break; 1977 1978 default: 1979 break; 1980 } 1981 } 1982 1983 /* Retrieve the number of operands for the current assembled instruction. */ 1984 1985 static int 1986 get_number_of_operands (void) 1987 { 1988 int i; 1989 1990 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) 1991 ; 1992 return i; 1993 } 1994 1995 /* Verify that the number NUM can be represented in BITS bits (that is, 1996 within its permitted range), based on the instruction's FLAGS. 1997 If UPDATE is nonzero, update the value of NUM if necessary. 1998 Return OP_LEGAL upon success, actual error type upon failure. */ 1999 2000 static op_err 2001 check_range (long *num, int bits, int unsigned flags, int update) 2002 { 2003 long min, max; 2004 int retval = OP_LEGAL; 2005 long value = *num; 2006 2007 if (bits == 0 && value > 0) return OP_OUT_OF_RANGE; 2008 2009 /* For hosts witah longs bigger than 32-bits make sure that the top 2010 bits of a 32-bit negative value read in by the parser are set, 2011 so that the correct comparisons are made. */ 2012 if (value & 0x80000000) 2013 value |= (-1L << 31); 2014 2015 2016 /* Verify operand value is even. */ 2017 if (flags & OP_EVEN) 2018 { 2019 if (value % 2) 2020 return OP_NOT_EVEN; 2021 } 2022 2023 if (flags & OP_DEC) 2024 { 2025 value -= 1; 2026 if (update) 2027 *num = value; 2028 } 2029 2030 if (flags & OP_SHIFT) 2031 { 2032 value >>= 1; 2033 if (update) 2034 *num = value; 2035 } 2036 else if (flags & OP_SHIFT_DEC) 2037 { 2038 value = (value >> 1) - 1; 2039 if (update) 2040 *num = value; 2041 } 2042 2043 if (flags & OP_ABS20) 2044 { 2045 if (value > 0xEFFFF) 2046 return OP_OUT_OF_RANGE; 2047 } 2048 2049 if (flags & OP_ESC) 2050 { 2051 if (value == 0xB || value == 0x9) 2052 return OP_OUT_OF_RANGE; 2053 else if (value == -1) 2054 { 2055 if (update) 2056 *num = 9; 2057 return retval; 2058 } 2059 } 2060 2061 if (flags & OP_ESC1) 2062 { 2063 if (value > 13) 2064 return OP_OUT_OF_RANGE; 2065 } 2066 2067 if (flags & OP_SIGNED) 2068 { 2069 max = (1 << (bits - 1)) - 1; 2070 min = - (1 << (bits - 1)); 2071 if ((value > max) || (value < min)) 2072 retval = OP_OUT_OF_RANGE; 2073 } 2074 else if (flags & OP_UNSIGNED) 2075 { 2076 max = ((((1 << (bits - 1)) - 1) << 1) | 1); 2077 min = 0; 2078 if (((unsigned long) value > (unsigned long) max) 2079 || ((unsigned long) value < (unsigned long) min)) 2080 retval = OP_OUT_OF_RANGE; 2081 } 2082 else if (flags & OP_NEG) 2083 { 2084 max = - 1; 2085 min = - ((1 << (bits - 1)) - 1); 2086 if ((value > max) || (value < min)) 2087 retval = OP_OUT_OF_RANGE; 2088 } 2089 return retval; 2090 } 2091 2092 /* Bunch of error checkings. 2093 The checks are made after a matching instruction was found. */ 2094 2095 static void 2096 warn_if_needed (ins *insn) 2097 { 2098 /* If the post-increment address mode is used and the load/store 2099 source register is the same as rbase, the result of the 2100 instruction is undefined. */ 2101 if (IS_INSN_TYPE (LD_STOR_INS_INC)) 2102 { 2103 /* Enough to verify that one of the arguments is a simple reg. */ 2104 if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r)) 2105 if (insn->arg[0].r == insn->arg[1].r) 2106 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn->arg[0].r); 2107 } 2108 2109 if (IS_INSN_MNEMONIC ("pop") 2110 || IS_INSN_MNEMONIC ("push") 2111 || IS_INSN_MNEMONIC ("popret")) 2112 { 2113 unsigned int count = insn->arg[0].constant, reg_val; 2114 2115 /* Check if count operand caused to save/retrive the RA twice 2116 to generate warning message. */ 2117 if (insn->nargs > 2) 2118 { 2119 reg_val = getreg_image (insn->arg[1].r); 2120 2121 if ( ((reg_val == 9) && (count > 7)) 2122 || ((reg_val == 10) && (count > 6)) 2123 || ((reg_val == 11) && (count > 5)) 2124 || ((reg_val == 12) && (count > 4)) 2125 || ((reg_val == 13) && (count > 2)) 2126 || ((reg_val == 14) && (count > 0))) 2127 as_warn (_("RA register is saved twice.")); 2128 2129 /* Check if the third operand is "RA" or "ra" */ 2130 if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA))) 2131 as_bad (_("`%s' Illegal use of registers."), ins_parse); 2132 } 2133 2134 if (insn->nargs > 1) 2135 { 2136 reg_val = getreg_image (insn->arg[1].r); 2137 2138 /* If register is a register pair ie r12/r13/r14 in operand1, then 2139 the count constant should be validated. */ 2140 if (((reg_val == 11) && (count > 7)) 2141 || ((reg_val == 12) && (count > 6)) 2142 || ((reg_val == 13) && (count > 4)) 2143 || ((reg_val == 14) && (count > 2)) 2144 || ((reg_val == 15) && (count > 0))) 2145 as_bad (_("`%s' Illegal count-register combination."), ins_parse); 2146 } 2147 else 2148 { 2149 /* Check if the operand is "RA" or "ra" */ 2150 if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA))) 2151 as_bad (_("`%s' Illegal use of register."), ins_parse); 2152 } 2153 } 2154 2155 /* Some instruction assume the stack pointer as rptr operand. 2156 Issue an error when the register to be loaded is also SP. */ 2157 if (instruction->flags & NO_SP) 2158 { 2159 if (getreg_image (insn->arg[1].r) == getreg_image (sp)) 2160 as_bad (_("`%s' has undefined result"), ins_parse); 2161 } 2162 2163 /* If the rptr register is specified as one of the registers to be loaded, 2164 the final contents of rptr are undefined. Thus, we issue an error. */ 2165 if (instruction->flags & NO_RPTR) 2166 { 2167 if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant) 2168 as_bad (_("Same src/dest register is used (`r%d'),result is undefined"), 2169 getreg_image (insn->arg[0].r)); 2170 } 2171 } 2172 2173 /* In some cases, we need to adjust the instruction pointer although a 2174 match was already found. Here, we gather all these cases. 2175 Returns 1 if instruction pointer was adjusted, otherwise 0. */ 2176 2177 static int 2178 adjust_if_needed (ins *insn ATTRIBUTE_UNUSED) 2179 { 2180 int ret_value = 0; 2181 2182 if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS))) 2183 { 2184 if ((instruction->operands[0].op_type == abs24) 2185 && ((insn->arg[0].constant) > 0xF00000)) 2186 { 2187 insn->arg[0].constant &= 0xFFFFF; 2188 instruction--; 2189 ret_value = 1; 2190 } 2191 } 2192 2193 return ret_value; 2194 } 2195 2196 /* Assemble a single instruction: 2197 INSN is already parsed (that is, all operand values and types are set). 2198 For instruction to be assembled, we need to find an appropriate template in 2199 the instruction table, meeting the following conditions: 2200 1: Has the same number of operands. 2201 2: Has the same operand types. 2202 3: Each operand size is sufficient to represent the instruction's values. 2203 Returns 1 upon success, 0 upon failure. */ 2204 2205 static int 2206 assemble_insn (char *mnemonic, ins *insn) 2207 { 2208 /* Type of each operand in the current template. */ 2209 argtype cur_type[MAX_OPERANDS]; 2210 /* Size (in bits) of each operand in the current template. */ 2211 unsigned int cur_size[MAX_OPERANDS]; 2212 /* Flags of each operand in the current template. */ 2213 unsigned int cur_flags[MAX_OPERANDS]; 2214 /* Instruction type to match. */ 2215 unsigned int ins_type; 2216 /* Boolean flag to mark whether a match was found. */ 2217 int match = 0; 2218 int i; 2219 /* Nonzero if an instruction with same number of operands was found. */ 2220 int found_same_number_of_operands = 0; 2221 /* Nonzero if an instruction with same argument types was found. */ 2222 int found_same_argument_types = 0; 2223 /* Nonzero if a constant was found within the required range. */ 2224 int found_const_within_range = 0; 2225 /* Argument number of an operand with invalid type. */ 2226 int invalid_optype = -1; 2227 /* Argument number of an operand with invalid constant value. */ 2228 int invalid_const = -1; 2229 /* Operand error (used for issuing various constant error messages). */ 2230 op_err op_error, const_err = OP_LEGAL; 2231 2232 /* Retrieve data (based on FUNC) for each operand of a given instruction. */ 2233 #define GET_CURRENT_DATA(FUNC, ARRAY) \ 2234 for (i = 0; i < insn->nargs; i++) \ 2235 ARRAY[i] = FUNC (instruction->operands[i].op_type) 2236 2237 #define GET_CURRENT_TYPE GET_CURRENT_DATA (get_optype, cur_type) 2238 #define GET_CURRENT_SIZE GET_CURRENT_DATA (get_opbits, cur_size) 2239 #define GET_CURRENT_FLAGS GET_CURRENT_DATA (get_opflags, cur_flags) 2240 2241 /* Instruction has no operands -> only copy the constant opcode. */ 2242 if (insn->nargs == 0) 2243 { 2244 output_opcode[0] = BIN (instruction->match, instruction->match_bits); 2245 return 1; 2246 } 2247 2248 /* In some case, same mnemonic can appear with different instruction types. 2249 For example, 'storb' is supported with 3 different types : 2250 LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS. 2251 We assume that when reaching this point, the instruction type was 2252 pre-determined. We need to make sure that the type stays the same 2253 during a search for matching instruction. */ 2254 ins_type = CR16_INS_TYPE (instruction->flags); 2255 2256 while (/* Check that match is still not found. */ 2257 match != 1 2258 /* Check we didn't get to end of table. */ 2259 && instruction->mnemonic != NULL 2260 /* Check that the actual mnemonic is still available. */ 2261 && IS_INSN_MNEMONIC (mnemonic) 2262 /* Check that the instruction type wasn't changed. */ 2263 && IS_INSN_TYPE (ins_type)) 2264 { 2265 /* Check whether number of arguments is legal. */ 2266 if (get_number_of_operands () != insn->nargs) 2267 goto next_insn; 2268 found_same_number_of_operands = 1; 2269 2270 /* Initialize arrays with data of each operand in current template. */ 2271 GET_CURRENT_TYPE; 2272 GET_CURRENT_SIZE; 2273 GET_CURRENT_FLAGS; 2274 2275 /* Check for type compatibility. */ 2276 for (i = 0; i < insn->nargs; i++) 2277 { 2278 if (cur_type[i] != insn->arg[i].type) 2279 { 2280 if (invalid_optype == -1) 2281 invalid_optype = i + 1; 2282 goto next_insn; 2283 } 2284 } 2285 found_same_argument_types = 1; 2286 2287 for (i = 0; i < insn->nargs; i++) 2288 { 2289 /* If 'bal' instruction size is '2' and reg operand is not 'ra' 2290 then goto next instruction. */ 2291 if (IS_INSN_MNEMONIC ("bal") && (i == 0) 2292 && (instruction->size == 2) && (insn->arg[i].rp != 14)) 2293 goto next_insn; 2294 2295 /* If 'storb' instruction with 'sp' reg and 16-bit disp of 2296 * reg-pair, leads to undifined trap, so this should use 2297 * 20-bit disp of reg-pair. */ 2298 if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2) 2299 && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp)) 2300 goto next_insn; 2301 2302 /* Only check range - don't update the constant's value, since the 2303 current instruction may not be the last we try to match. 2304 The constant's value will be updated later, right before printing 2305 it to the object file. */ 2306 if ((insn->arg[i].X_op == O_constant) 2307 && (op_error = check_range (&insn->arg[i].constant, cur_size[i], 2308 cur_flags[i], 0))) 2309 { 2310 if (invalid_const == -1) 2311 { 2312 invalid_const = i + 1; 2313 const_err = op_error; 2314 } 2315 goto next_insn; 2316 } 2317 /* For symbols, we make sure the relocation size (which was already 2318 determined) is sufficient. */ 2319 else if ((insn->arg[i].X_op == O_symbol) 2320 && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize 2321 > cur_size[i])) 2322 goto next_insn; 2323 } 2324 found_const_within_range = 1; 2325 2326 /* If we got till here -> Full match is found. */ 2327 match = 1; 2328 break; 2329 2330 /* Try again with next instruction. */ 2331 next_insn: 2332 instruction++; 2333 } 2334 2335 if (!match) 2336 { 2337 /* We haven't found a match - instruction can't be assembled. */ 2338 if (!found_same_number_of_operands) 2339 as_bad (_("Incorrect number of operands")); 2340 else if (!found_same_argument_types) 2341 as_bad (_("Illegal type of operand (arg %d)"), invalid_optype); 2342 else if (!found_const_within_range) 2343 { 2344 switch (const_err) 2345 { 2346 case OP_OUT_OF_RANGE: 2347 as_bad (_("Operand out of range (arg %d)"), invalid_const); 2348 break; 2349 case OP_NOT_EVEN: 2350 as_bad (_("Operand has odd displacement (arg %d)"), invalid_const); 2351 break; 2352 default: 2353 as_bad (_("Illegal operand (arg %d)"), invalid_const); 2354 break; 2355 } 2356 } 2357 2358 return 0; 2359 } 2360 else 2361 /* Full match - print the encoding to output file. */ 2362 { 2363 /* Make further checkings (such that couldn't be made earlier). 2364 Warn the user if necessary. */ 2365 warn_if_needed (insn); 2366 2367 /* Check whether we need to adjust the instruction pointer. */ 2368 if (adjust_if_needed (insn)) 2369 /* If instruction pointer was adjusted, we need to update 2370 the size of the current template operands. */ 2371 GET_CURRENT_SIZE; 2372 2373 for (i = 0; i < insn->nargs; i++) 2374 { 2375 int j = instruction->flags & REVERSE_MATCH ? 2376 i == 0 ? 1 : 2377 i == 1 ? 0 : i : 2378 i; 2379 2380 /* This time, update constant value before printing it. */ 2381 if ((insn->arg[j].X_op == O_constant) 2382 && (check_range (&insn->arg[j].constant, cur_size[j], 2383 cur_flags[j], 1) != OP_LEGAL)) 2384 as_fatal (_("Illegal operand (arg %d)"), j+1); 2385 } 2386 2387 /* First, copy the instruction's opcode. */ 2388 output_opcode[0] = BIN (instruction->match, instruction->match_bits); 2389 2390 for (i = 0; i < insn->nargs; i++) 2391 { 2392 /* For BAL (ra),disp17 instuction only. And also set the 2393 DISP24a relocation type. */ 2394 if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0) 2395 { 2396 insn->rtype = BFD_RELOC_CR16_DISP24a; 2397 continue; 2398 } 2399 cur_arg_num = i; 2400 print_operand (cur_size[i], instruction->operands[i].shift, 2401 &insn->arg[i]); 2402 } 2403 } 2404 2405 return 1; 2406 } 2407 2408 /* Print the instruction. 2409 Handle also cases where the instruction is relaxable/relocatable. */ 2410 2411 static void 2412 print_insn (ins *insn) 2413 { 2414 unsigned int i, j, insn_size; 2415 char *this_frag; 2416 unsigned short words[4]; 2417 int addr_mod; 2418 2419 /* Arrange the insn encodings in a WORD size array. */ 2420 for (i = 0, j = 0; i < 2; i++) 2421 { 2422 words[j++] = (output_opcode[i] >> 16) & 0xFFFF; 2423 words[j++] = output_opcode[i] & 0xFFFF; 2424 } 2425 2426 /* Handle relocation. */ 2427 if ((instruction->flags & RELAXABLE) && relocatable) 2428 { 2429 int relax_subtype; 2430 /* Write the maximal instruction size supported. */ 2431 insn_size = INSN_MAX_SIZE; 2432 2433 if (IS_INSN_TYPE (BRANCH_INS)) 2434 { 2435 switch (insn->rtype) 2436 { 2437 case BFD_RELOC_CR16_DISP24: 2438 relax_subtype = 2; 2439 break; 2440 case BFD_RELOC_CR16_DISP16: 2441 relax_subtype = 1; 2442 break; 2443 default: 2444 relax_subtype = 0; 2445 break; 2446 } 2447 } 2448 else 2449 abort (); 2450 2451 this_frag = frag_var (rs_machine_dependent, insn_size *2, 2452 4, relax_subtype, 2453 insn->exp.X_add_symbol, 2454 0, 2455 0); 2456 } 2457 else 2458 { 2459 insn_size = instruction->size; 2460 this_frag = frag_more (insn_size * 2); 2461 2462 if ((relocatable) && (insn->rtype != BFD_RELOC_NONE)) 2463 { 2464 reloc_howto_type *reloc_howto; 2465 int size; 2466 2467 reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype); 2468 2469 if (!reloc_howto) 2470 abort (); 2471 2472 size = bfd_get_reloc_size (reloc_howto); 2473 2474 if (size < 1 || size > 4) 2475 abort (); 2476 2477 fix_new_exp (frag_now, this_frag - frag_now->fr_literal, 2478 size, &insn->exp, reloc_howto->pc_relative, 2479 insn->rtype); 2480 } 2481 } 2482 2483 /* Verify a 2-byte code alignment. */ 2484 addr_mod = frag_now_fix () & 1; 2485 if (frag_now->has_code && frag_now->insn_addr != addr_mod) 2486 as_bad (_("instruction address is not a multiple of 2")); 2487 frag_now->insn_addr = addr_mod; 2488 frag_now->has_code = 1; 2489 2490 /* Write the instruction encoding to frag. */ 2491 for (i = 0; i < insn_size; i++) 2492 { 2493 md_number_to_chars (this_frag, (valueT) words[i], 2); 2494 this_frag += 2; 2495 } 2496 } 2497 2498 /* This is the guts of the machine-dependent assembler. OP points to a 2499 machine dependent instruction. This function is supposed to emit 2500 the frags/bytes it assembles to. */ 2501 2502 void 2503 md_assemble (char *op) 2504 { 2505 ins cr16_ins; 2506 char *param, param1[32]; 2507 char c; 2508 2509 /* Reset global variables for a new instruction. */ 2510 reset_vars (op); 2511 2512 /* Strip the mnemonic. */ 2513 for (param = op; *param != 0 && !ISSPACE (*param); param++) 2514 ; 2515 c = *param; 2516 *param++ = '\0'; 2517 2518 /* bCC instuctions and adjust the mnemonic by adding extra white spaces. */ 2519 if (is_bcc_insn (op)) 2520 { 2521 strcpy (param1, get_b_cc (op)); 2522 op = "b"; 2523 strcat (param1,","); 2524 strcat (param1, param); 2525 param = (char *) ¶m1; 2526 } 2527 2528 /* Checking the cinv options and adjust the mnemonic by removing the 2529 extra white spaces. */ 2530 if (streq ("cinv", op)) 2531 { 2532 /* Validate the cinv options. */ 2533 check_cinv_options (param); 2534 strcat (op, param); 2535 } 2536 2537 /* MAPPING - SHIFT INSN, if imm4/imm16 positive values 2538 lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg 2539 as CR16 core doesn't support lsh[b/w] right shift operaions. */ 2540 if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op)) 2541 && (param [0] == '$')) 2542 { 2543 strcpy (param1, param); 2544 /* Find the instruction. */ 2545 instruction = (const inst *) hash_find (cr16_inst_hash, op); 2546 parse_operands (&cr16_ins, param1); 2547 if (((&cr16_ins)->arg[0].type == arg_ic) 2548 && ((&cr16_ins)->arg[0].constant >= 0)) 2549 { 2550 if (streq ("lshb", op)) 2551 op = "ashub"; 2552 else if (streq ("lshd", op)) 2553 op = "ashud"; 2554 else 2555 op = "ashuw"; 2556 } 2557 } 2558 2559 /* Find the instruction. */ 2560 instruction = (const inst *) hash_find (cr16_inst_hash, op); 2561 if (instruction == NULL) 2562 { 2563 as_bad (_("Unknown opcode: `%s'"), op); 2564 return; 2565 } 2566 2567 /* Tie dwarf2 debug info to the address at the start of the insn. */ 2568 dwarf2_emit_insn (0); 2569 2570 /* Parse the instruction's operands. */ 2571 parse_insn (&cr16_ins, param); 2572 2573 /* Assemble the instruction - return upon failure. */ 2574 if (assemble_insn (op, &cr16_ins) == 0) 2575 return; 2576 2577 /* Print the instruction. */ 2578 print_insn (&cr16_ins); 2579 } 2580