1; OpenRISC 1000 architecture. -*- Scheme -*- 2; Copyright 2000-2019 Free Software Foundation, Inc. 3; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org 4; Modified by Julius Baxter, juliusbaxter@gmail.com 5; Modified by Peter Gavin, pgavin@gmail.com 6; Modified by Andrey Bacherov, avbacherov@opencores.org 7; 8; This program is free software; you can redistribute it and/or modify 9; it under the terms of the GNU General Public License as published by 10; the Free Software Foundation; either version 3 of the License, or 11; (at your option) any later version. 12; 13; This program is distributed in the hope that it will be useful, 14; but WITHOUT ANY WARRANTY; without even the implied warranty of 15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16; GNU General Public License for more details. 17; 18; You should have received a copy of the GNU General Public License 19; along with this program; if not, see <http://www.gnu.org/licenses/> 20 21(include "simplify.inc") 22 23; The OpenRISC family is a set of RISC microprocessor architectures with an 24; emphasis on scalability and is targetted at embedded use. 25; The CPU RTL development is a collaborative open source effort. 26; http://opencores.org/or1k 27; http://openrisc.net 28 29(define-arch 30 (name or1k) 31 (comment "OpenRISC 1000") 32 (default-alignment aligned) 33 (insn-lsb0? #t) 34 (machs or32 or32nd or64 or64nd) 35 (isas openrisc) 36) 37 38; Instruction set parameters. 39(define-isa 40 ; Name of the ISA. 41 (name openrisc) 42 ; Base insturction length. The insns are always 32 bits wide. 43 (base-insn-bitsize 32) 44 ) 45 46(define-pmacro OR32-MACHS or32,or32nd) 47(define-pmacro OR64-MACHS or64,or64nd) 48(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd) 49(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd) 50(define-pmacro ORFPX64-MACHS or64,or64nd) 51(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs 52 53(define-attr 54 (for model) 55 (type boolean) 56 (name NO-DELAY-SLOT) 57 (comment "does not have delay slots") 58 ) 59 60(if (keep-mach? (or32 or32nd)) 61 (begin 62 (define-cpu 63 (name or1k32bf) 64 (comment "OpenRISC 1000 32-bit CPU family") 65 (insn-endian big) 66 (data-endian big) 67 (word-bitsize 32) 68 (file-transform "") 69 ) 70 71 (define-mach 72 (name or32) 73 (comment "Generic OpenRISC 1000 32-bit CPU") 74 (cpu or1k32bf) 75 (bfd-name "or1k") 76 ) 77 78 (define-mach 79 (name or32nd) 80 (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot") 81 (cpu or1k32bf) 82 (bfd-name "or1knd") 83 ) 84 85 ; OpenRISC 1200 - 32-bit or1k CPU implementation 86 (define-model 87 (name or1200) (comment "OpenRISC 1200 model") 88 (attrs) 89 (mach or32) 90 (unit u-exec "Execution Unit" () 1 1 () () () ()) 91 ) 92 93 ; OpenRISC 1200 - 32-bit or1k CPU implementation 94 (define-model 95 (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot") 96 (attrs NO-DELAY-SLOT) 97 (mach or32nd) 98 (unit u-exec "Execution Unit" () 1 1 () () () ()) 99 ) 100 ) 101 ) 102 103(if (keep-mach? (or64 or64nd)) 104 (begin 105 (define-cpu 106 (name or1k64bf) 107 (comment "OpenRISC 1000 64-bit CPU family") 108 (insn-endian big) 109 (data-endian big) 110 (word-bitsize 64) 111 (file-transform "64") 112 ) 113 114 (define-mach 115 (name or64) 116 (comment "Generic OpenRISC 1000 64-bit CPU") 117 (cpu or1k64bf) 118 (bfd-name "or1k64") 119 ) 120 121 (define-mach 122 (name or64nd) 123 (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot") 124 (cpu or1k64bf) 125 (bfd-name "or1k64nd") 126 ) 127 ) 128 ) 129 130(include "or1kcommon.cpu") 131(include "or1korbis.cpu") 132(include "or1korfpx.cpu") 133