1 /* Table of opcodes for the sparc. 2 Copyright (C) 1989-2016 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this file; see the file COPYING. If not, write to the 18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 22 /* FIXME-someday: perhaps the ,a's and such should be embedded in the 23 instruction's name rather than the args. This would make gas faster, pinsn 24 slower, but would mess up some macros a bit. xoxorich. */ 25 26 #include "sysdep.h" 27 #include <stdio.h> 28 #include "opcode/sparc.h" 29 30 /* Some defines to make life easy. */ 31 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) 32 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) 33 #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) 34 #define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON) 35 #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) 36 #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) 37 #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) 38 #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) 39 #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) 40 #define MASK_V9C SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C) 41 #define MASK_V9D SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D) 42 #define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E) 43 #define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V) 44 #define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M) 45 46 /* Bit masks of architectures supporting the insn. */ 47 48 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \ 49 | MASK_SPARCLET | MASK_SPARCLITE \ 50 | MASK_V9 | MASK_V9A | MASK_V9B \ 51 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 52 /* v6 insns not supported on the sparclet. */ 53 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \ 54 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \ 55 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 56 #define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \ 57 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \ 58 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 59 /* Although not all insns are implemented in hardware, sparclite is defined 60 to be a superset of v8. Unimplemented insns trap and are then theoretically 61 implemented in software. 62 It's not clear that the same is true for sparclet, although the docs 63 suggest it is. Rather than complicating things, the sparclet assembler 64 recognizes all v8 insns. */ 65 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \ 66 | MASK_V9 | MASK_V9A | MASK_V9B \ 67 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 68 #define sparclet (MASK_SPARCLET) 69 /* sparclet insns supported by leon. */ 70 #define letandleon (MASK_SPARCLET | MASK_LEON) 71 #define sparclite (MASK_SPARCLITE) 72 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B \ 73 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 74 /* v9 insns supported by leon. */ 75 #define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \ 76 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 77 | MASK_LEON) 78 #define v9a (MASK_V9A | MASK_V9B \ 79 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 80 #define v9b (MASK_V9B \ 81 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 82 #define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 83 #define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) 84 #define v9e (MASK_V9E | MASK_V9V | MASK_V9M) 85 #define v9v (MASK_V9V | MASK_V9M) 86 #define v9m (MASK_V9M) 87 88 /* v6 insns not supported by v9. */ 89 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \ 90 | MASK_SPARCLET | MASK_SPARCLITE) 91 /* v9a instructions which would appear to be aliases to v9's impdep's 92 otherwise. */ 93 #define v9notv9a (MASK_V9) 94 95 /* Table of opcode architectures. 96 The order is defined in opcode/sparc.h. */ 97 98 const struct sparc_opcode_arch sparc_opcode_archs[] = 99 { 100 { "v6", MASK_V6 }, 101 { "v7", MASK_V6 | MASK_V7 }, 102 { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, 103 { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON }, 104 { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, 105 { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, 106 /* ??? Don't some v8 priviledged insns conflict with v9? */ 107 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, 108 /* v9 with ultrasparc additions */ 109 { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, 110 /* v9 with cheetah additions */ 111 { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B }, 112 /* v9 with UA2005 and T1 additions. */ 113 { "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 114 | MASK_V9C) }, 115 /* v9 with UA2007 and T3 additions. */ 116 { "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 117 | MASK_V9C | MASK_V9D) }, 118 /* v9 with OSA2011 and T4 additions modulus integer multiply-add. */ 119 { "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 120 | MASK_V9C | MASK_V9D | MASK_V9E) }, 121 /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp 122 multiply-add. */ 123 { "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 124 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V) }, 125 /* v9 with OSA2015 and M7 additions. */ 126 { "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 127 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) }, 128 { NULL, 0 } 129 }; 130 131 /* Given NAME, return it's architecture entry. */ 132 133 enum sparc_opcode_arch_val 134 sparc_opcode_lookup_arch (const char *name) 135 { 136 const struct sparc_opcode_arch *p; 137 138 for (p = &sparc_opcode_archs[0]; p->name; ++p) 139 if (strcmp (name, p->name) == 0) 140 return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); 141 142 return SPARC_OPCODE_ARCH_BAD; 143 } 144 145 /* Branch condition field. */ 146 #define COND(x) (((x) & 0xf) << 25) 147 148 /* Compare And Branch condition field. */ 149 #define CBCOND(x) (((x) & 0x1f) << 25) 150 151 /* v9: Move (MOVcc and FMOVcc) condition field. */ 152 #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ 153 154 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ 155 #define RCOND(x) (((x) & 0x7) << 10) /* v9 */ 156 157 #define CONDA (COND (0x8)) 158 #define CONDCC (COND (0xd)) 159 #define CONDCS (COND (0x5)) 160 #define CONDE (COND (0x1)) 161 #define CONDG (COND (0xa)) 162 #define CONDGE (COND (0xb)) 163 #define CONDGU (COND (0xc)) 164 #define CONDL (COND (0x3)) 165 #define CONDLE (COND (0x2)) 166 #define CONDLEU (COND (0x4)) 167 #define CONDN (COND (0x0)) 168 #define CONDNE (COND (0x9)) 169 #define CONDNEG (COND (0x6)) 170 #define CONDPOS (COND (0xe)) 171 #define CONDVC (COND (0xf)) 172 #define CONDVS (COND (0x7)) 173 174 #define CONDNZ CONDNE 175 #define CONDZ CONDE 176 #define CONDGEU CONDCC 177 #define CONDLU CONDCS 178 179 #define FCONDA (COND (0x8)) 180 #define FCONDE (COND (0x9)) 181 #define FCONDG (COND (0x6)) 182 #define FCONDGE (COND (0xb)) 183 #define FCONDL (COND (0x4)) 184 #define FCONDLE (COND (0xd)) 185 #define FCONDLG (COND (0x2)) 186 #define FCONDN (COND (0x0)) 187 #define FCONDNE (COND (0x1)) 188 #define FCONDO (COND (0xf)) 189 #define FCONDU (COND (0x7)) 190 #define FCONDUE (COND (0xa)) 191 #define FCONDUG (COND (0x5)) 192 #define FCONDUGE (COND (0xc)) 193 #define FCONDUL (COND (0x3)) 194 #define FCONDULE (COND (0xe)) 195 196 #define FCONDNZ FCONDNE 197 #define FCONDZ FCONDE 198 199 #define ICC (0) /* v9 */ 200 #define XCC (1 << 12) /* v9 */ 201 #define CBCOND_XCC (1 << 21) 202 #define FCC(x) (((x) & 0x3) << 11) /* v9 */ 203 #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ 204 205 /* The order of the opcodes in the table is significant: 206 207 * The assembler requires that all instances of the same mnemonic must 208 be consecutive. If they aren't, the assembler will bomb at runtime. 209 210 * The disassembler should not care about the order of the opcodes. */ 211 212 /* Entries for commutative arithmetic operations. */ 213 /* ??? More entries can make use of this. */ 214 #define COMMUTEOP(opcode, op3, arch_mask) \ 215 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, 0, 0, arch_mask }, \ 216 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, 0, 0, arch_mask }, \ 217 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, 0, 0, arch_mask } 218 219 const struct sparc_opcode sparc_opcodes[] = { 220 221 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, 0, v6 }, 222 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */ 223 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, 0, v6 }, 224 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, 0, v6 }, 225 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 226 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ld [rs1+0],d */ 227 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, 0, v6 }, 228 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */ 229 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, 0, v6 }, 230 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, 0, 0, v6 }, 231 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, 0, 0, v6 }, 232 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, 0, v6 }, /* ld [rs1+0],d */ 233 234 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, 0, v6 }, 235 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */ 236 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, 0, v6 }, 237 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, 0, v6 }, 238 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, 0, v6 }, 239 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+0],d */ 240 241 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, 0, 0, v6notv9 }, 242 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */ 243 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, 0, 0, v6notv9 }, 244 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, 0, 0, v6notv9 }, 245 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 }, 246 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */ 247 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, 0, 0, v6notv9 }, 248 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */ 249 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, 0, 0, v6notv9 }, 250 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, 0, 0, v6notv9 }, 251 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, 0, 0, v6notv9 }, 252 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */ 253 254 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the 255 'ld' pseudo-op in v9. */ 256 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, 0, 0, v9 }, 257 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+%g0],d */ 258 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, 0, 0, v9 }, 259 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, 0, 0, v9 }, 260 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v9 }, 261 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */ 262 263 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 }, 264 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */ 265 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, 0, 0, v9 }, 266 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, 0, 0, v9 }, 267 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 }, 268 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+0],d */ 269 270 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", F_ALIAS, 0, 0, v6 }, 271 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */ 272 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", F_ALIAS, 0, 0, v6 }, 273 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", F_ALIAS, 0, 0, v6 }, 274 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v6 }, 275 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */ 276 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", F_ALIAS, 0, 0, v6 }, 277 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */ 278 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", F_ALIAS, 0, 0, v6 }, 279 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", F_ALIAS, 0, 0, v6 }, 280 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", F_ALIAS, 0, 0, v6 }, 281 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */ 282 283 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, 0, 0, v6notv9 }, 284 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */ 285 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, 0, 0, v6notv9 }, 286 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, 0, 0, v6notv9 }, 287 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 }, 288 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+0],d */ 289 290 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, 0, 0, v9 }, 291 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */ 292 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, 0, 0, v9 }, 293 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, 0, 0, v9 }, 294 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, 0, 0, v9 }, 295 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */ 296 297 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 298 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+%g0],d */ 299 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, 0, 0, v6 }, 300 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, 0, 0, v6 }, 301 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 302 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+0],d */ 303 304 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+%g0],d */ 305 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 306 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, 0, 0, v6 }, 307 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, 0, 0, v6 }, 308 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 309 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+0],d */ 310 311 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 312 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+%g0],d */ 313 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, 0, 0, v6 }, 314 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, 0, 0, v6 }, 315 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 316 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+0],d */ 317 318 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 }, 319 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+%g0],d */ 320 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, 0, 0, v9 }, 321 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, 0, 0, v9 }, 322 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 }, 323 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+0],d */ 324 325 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 326 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+%g0],d */ 327 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, 0, 0, v6 }, 328 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, 0, 0, v6 }, 329 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 330 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+0],d */ 331 332 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 333 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+%g0],d */ 334 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, 0, 0, v6 }, 335 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, 0, 0, v6 }, 336 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 337 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+0],d */ 338 339 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 }, 340 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+%g0],d */ 341 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, 0, 0, v9 }, 342 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, 0, 0, v9 }, 343 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 }, 344 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+0],d */ 345 346 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, 0, v9 }, 347 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, 0, 0, v9 }, /* ld [rs1+%g0],d */ 348 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, 0, v9 }, 349 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, 0, v9 }, 350 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, 0, 0, v9 }, 351 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 352 353 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr */ 354 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1],%efsr */ 355 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1+0],%efsr */ 356 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0+%rs1],%efsr */ 357 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0],%efsr */ 358 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1], %efsr */ 359 360 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 361 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lda [rs1+%g0],d */ 362 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 363 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 364 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 365 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 366 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, 0, 0, v9 }, 367 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */ 368 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, 0, 0, v9 }, 369 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, 0, 0, v9 }, 370 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, 0, 0, v9 }, 371 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 372 373 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, 0, v9 }, 374 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */ 375 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 376 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 377 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 378 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 379 380 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", F_ALIAS, 0, 0, v6 }, 381 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v6 }, /* ldda [rs1+%g0],d */ 382 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", F_ALIAS, 0, 0, v9 }, 383 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", F_ALIAS, 0, 0, v9 }, 384 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 }, 385 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */ 386 387 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, 0, 0, v9 }, 388 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */ 389 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, 0, 0, v9 }, 390 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, 0, 0, v9 }, 391 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, 0, 0, v9 }, 392 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 393 394 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, 0, 0, v9 }, 395 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */ 396 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, 0, 0, v9 }, 397 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, 0, 0, v9 }, 398 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, 0, 0, v9 }, 399 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */ 400 401 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 402 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsba [rs1+%g0],d */ 403 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 404 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 405 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 406 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 407 408 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 409 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsha [rs1+%g0],d */ 410 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 411 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 412 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 413 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 414 415 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 416 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldstuba [rs1+%g0],d */ 417 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 418 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 419 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 420 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 421 422 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, 0, 0, v9 }, 423 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */ 424 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 425 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 426 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 427 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 428 429 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 430 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduba [rs1+%g0],d */ 431 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 432 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 433 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 434 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 435 436 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 437 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduha [rs1+%g0],d */ 438 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 439 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 440 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 441 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 442 443 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, 0, 0, v9 }, /* lduwa === lda */ 444 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v9 }, /* lda [rs1+%g0],d */ 445 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, 0, 0, v9 }, 446 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, 0, 0, v9 }, 447 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 }, 448 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */ 449 450 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, 0, 0, v9 }, 451 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */ 452 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 453 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 454 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 455 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 456 457 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 }, 458 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */ 459 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, 0, 0, v6 }, 460 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, 0, 0, v6 }, 461 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 }, 462 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */ 463 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, 0, 0, v6 }, 464 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, 0, 0, v6 }, /* st d[rs1+%g0] */ 465 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, 0, 0, v6 }, 466 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, 0, 0, v6 }, 467 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, 0, 0, v6 }, 468 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */ 469 470 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9 }, 471 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */ 472 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, 0, 0, v6notv9 }, 473 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, 0, 0, v6notv9 }, 474 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, 0, 0, v6notv9 }, 475 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */ 476 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, 0, 0, v6notv9 }, 477 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */ 478 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, 0, 0, v6notv9 }, 479 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, 0, 0, v6notv9 }, 480 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, 0, 0, v6notv9 }, 481 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */ 482 483 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, 0, 0, v6 }, 484 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */ 485 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, 0, 0, v6 }, 486 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, 0, 0, v6 }, 487 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, 0, 0, v6 }, 488 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */ 489 490 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 }, 491 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */ 492 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 }, 493 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 }, 494 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 }, 495 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 496 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 }, 497 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */ 498 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 }, 499 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 }, 500 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 }, 501 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 502 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 }, 503 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */ 504 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 }, 505 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 }, 506 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 }, 507 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 508 509 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 510 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+%g0] */ 511 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 512 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 513 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 514 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+0] */ 515 516 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, 0, 0, v6 }, 517 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* sta d,[rs1+%g0] */ 518 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 519 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 520 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 521 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */ 522 523 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, 0, 0, v9 }, 524 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 525 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, 0, 0, v9 }, 526 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, 0, 0, v9 }, 527 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, 0, 0, v9 }, 528 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */ 529 530 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 }, 531 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 532 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 533 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 534 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 535 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 536 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 }, 537 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 538 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 539 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 540 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 541 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 542 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 }, 543 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 544 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 545 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 546 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 547 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 548 549 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 }, 550 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+%g0] */ 551 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, 0, 0, v6 }, 552 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, 0, 0, v6 }, 553 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 }, 554 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+0] */ 555 556 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 557 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */ 558 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 559 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 560 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 561 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */ 562 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 563 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */ 564 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 565 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 566 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 567 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */ 568 569 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, 0, 0, v6 }, 570 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* stba d,[rs1+%g0] */ 571 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 572 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 573 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 574 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stb d,[rs1+0] */ 575 576 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 577 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */ 578 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 579 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 580 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 581 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */ 582 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 583 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */ 584 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 585 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 586 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 587 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */ 588 589 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9 }, 590 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+%g0] */ 591 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, 0, 0, v9 }, 592 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, 0, 0, v9 }, 593 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 }, 594 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+0] */ 595 596 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_PREF_ALIAS, 0, 0, v6 }, 597 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */ 598 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_PREF_ALIAS, 0, 0, v6 }, 599 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_PREF_ALIAS, 0, 0, v6 }, 600 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_PREF_ALIAS, 0, 0, v6 }, 601 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */ 602 603 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, 0, 0, v6notv9 }, 604 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ 605 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, 0, 0, v6notv9 }, 606 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, 0, 0, v6notv9 }, 607 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, 0, 0, v6notv9 }, 608 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */ 609 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, 0, 0, v6 }, 610 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+%g0] */ 611 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, 0, 0, v6 }, 612 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, 0, 0, v6 }, 613 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, 0, 0, v6 }, 614 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+0] */ 615 616 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, 0, 0, v6notv9 }, 617 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ 618 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, 0, 0, v6notv9 }, 619 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, 0, 0, v6notv9 }, 620 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, 0, 0, v6notv9 }, 621 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */ 622 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9 }, 623 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ 624 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, 0, 0, v6notv9 }, 625 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, 0, 0, v6notv9 }, 626 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, 0, 0, v6notv9 }, 627 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */ 628 629 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 630 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */ 631 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 632 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 633 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 634 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */ 635 636 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, 0, 0, v9 }, 637 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */ 638 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 639 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 640 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 641 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */ 642 643 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 644 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stda d,[rs1+%g0] */ 645 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 646 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 647 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 648 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* std d,[rs1+0] */ 649 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, 0, 0, v9 }, 650 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */ 651 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, 0, 0, v9 }, 652 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, 0, 0, v9 }, 653 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, 0, 0, v9 }, 654 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */ 655 656 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 }, 657 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+%g0] */ 658 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, 0, 0, v6 }, 659 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, 0, 0, v6 }, 660 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 }, 661 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+0] */ 662 663 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 664 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */ 665 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 666 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 667 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 668 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */ 669 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 670 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */ 671 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 672 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 673 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 674 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */ 675 676 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, 0, 0, v6 }, 677 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* stha ,[rs1+%g0] */ 678 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 679 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 680 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 681 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* sth d,[rs1+0] */ 682 683 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 684 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */ 685 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 686 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 687 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 688 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */ 689 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 690 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */ 691 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 692 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 693 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 694 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */ 695 696 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9 }, 697 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */ 698 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, 0, 0, v9 }, 699 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, 0, 0, v9 }, 700 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 }, 701 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */ 702 703 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, 0, v9 }, 704 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */ 705 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, 0, 0, v9 }, 706 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, 0, 0, v9 }, 707 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, 0, 0, v9 }, 708 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */ 709 710 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, 0, 0, v9 }, 711 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9 }, /* stxa d,[rs1+%g0] */ 712 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 713 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 714 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 715 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stx d,[rs1+0] */ 716 717 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, 0, 0, v9 }, 718 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+%g0] */ 719 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, 0, 0, v9 }, 720 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, 0, 0, v9 }, 721 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, 0, 0, v9 }, 722 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+0] */ 723 724 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, 0, 0, v9 }, 725 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, 0, 0, v9 }, /* stqa [rs1+%g0] */ 726 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, 0, 0, v9 }, 727 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, 0, 0, v9 }, 728 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, 0, 0, v9 }, 729 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, 0, v9 }, /* stqa [rs1+0] */ 730 731 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v7 }, 732 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v7 }, /* swap [rs1+%g0],d */ 733 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, 0, 0, v7 }, 734 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, 0, 0, v7 }, 735 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, 0, 0, v7 }, 736 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v7 }, /* swap [rs1+0],d */ 737 738 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, 0, 0, v7 }, 739 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, 0, 0, v7 }, /* swapa [rs1+%g0],d */ 740 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 741 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 742 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 743 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* swap [rs1+0],d */ 744 745 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 746 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v6 }, /* restore %g0,%g0,%g0 */ 747 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, 0, v6 }, 748 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, 0, 0, v6 }, /* restore %g0,0,%g0 */ 749 750 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+rs2 */ 751 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1,%g0 */ 752 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+X */ 753 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */ 754 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */ 755 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X */ 756 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+0 */ 757 758 { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 759 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, 0, v6 }, 760 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, 0, 0, v6 }, /* Sun assembler compatibility */ 761 { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, 0, 0, v6 }, 762 763 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %i7+8,%g0 */ 764 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %o7+8,%g0 */ 765 766 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, 0, 0, v6 }, 767 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,d */ 768 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,d */ 769 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,d */ 770 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, 0, 0, v6 }, 771 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, 0, 0, v6 }, 772 773 { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 774 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 775 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 776 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 777 { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 778 { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 779 { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 780 { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 781 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, 0, 0, v9 }, 782 783 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "[1+2]", 0, 0, 0, v9 }, 784 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "[1]", 0, 0, 0, v9 }, /* flush rs1+%g0 */ 785 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "[1]", 0, 0, 0, v9 }, /* flush rs1+0 */ 786 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "[i]", 0, 0, 0, v9 }, /* flush %g0+i */ 787 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[1+i]", 0, 0, 0, v9 }, 788 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[i+1]", 0, 0, 0, v9 }, 789 790 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 }, 791 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */ 792 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */ 793 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */ 794 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 }, 795 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, 0, v8 }, 796 797 /* IFLUSH was renamed to FLUSH in v8. */ 798 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v6 }, 799 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+%g0 */ 800 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+0 */ 801 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v6 }, 802 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v6 }, 803 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, 0, v6 }, 804 805 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, 0, 0, v9 }, 806 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, 0, 0, v9 }, /* return rs1+%g0 */ 807 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, 0, v9 }, /* return rs1+0 */ 808 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, 0, 0, v9 }, /* return %g0+i */ 809 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, 0, 0, v9 }, 810 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, 0, 0, v9 }, 811 812 { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v9 }, 813 814 { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, 0, v9 }, 815 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8 }, 816 817 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, 0, 0, v9 }, 818 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ 819 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, 0, 0, v9 }, 820 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, 0, 0, v9 }, 821 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, 0, 0, v9 }, 822 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ 823 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, 0, 0, v9 }, 824 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ 825 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, 0, 0, v9 }, 826 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, 0, 0, v9 }, 827 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, 0, 0, v9 }, 828 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, 0, v9 }, /* prefetcha [rs1+0],d */ 829 830 { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 }, 831 { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 }, 832 { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 }, 833 { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 }, 834 { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 }, 835 { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 }, 836 837 { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 }, 838 { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 }, 839 { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 }, 840 { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 }, 841 { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 }, 842 { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 }, 843 844 { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 845 { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, 0, 0, v6 }, 846 847 { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclite }, 848 { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, 0, 0, sparclite }, 849 850 { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet|sparclite }, 851 { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, 0, 0, sparclet|sparclite }, 852 853 { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, 0, v9 }, 854 { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, HWCAP_POPC, 0, v9 }, 855 856 { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, 0, 0, v6 }, /* or %g0,%g0,d */ 857 { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, 0, 0, v6 }, /* or %g0,0,d */ 858 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 }, 859 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+%g0] */ 860 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 }, 861 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 }, 862 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 }, 863 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+0] */ 864 865 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 }, 866 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+%g0] */ 867 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 }, 868 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 }, 869 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 }, 870 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+0] */ 871 872 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 }, 873 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+%g0] */ 874 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 }, 875 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 }, 876 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 }, 877 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+0] */ 878 879 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v9 }, 880 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+%g0] */ 881 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v9 }, 882 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v9 }, 883 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v9 }, 884 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+0] */ 885 886 { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 887 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, 0, 0, v6 }, 888 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, 0, 0, v6 }, 889 890 /* This is not a commutative instruction. */ 891 { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 892 { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, 0, 0, v6 }, 893 894 /* This is not a commutative instruction. */ 895 { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 896 { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, 0, 0, v6 }, 897 898 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, %g0, %g0 */ 899 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, 0, v6 }, /* orcc %g0, rs2, %g0 */ 900 { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, 0, %g0 */ 901 902 903 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */ 904 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */ 905 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */ 906 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */ 907 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%asrX */ 908 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%g0,%asrX */ 909 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, 0, 0, v6 }, /* wr r,r,%y */ 910 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, 0, 0, v6 }, /* wr r,i,%y */ 911 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */ 912 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */ 913 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,0,%y */ 914 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,%g0,%y */ 915 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, 0, 0, v6notv9 }, /* wr r,r,%psr */ 916 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, 0, 0, v6notv9 }, /* wr r,i,%psr */ 917 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */ 918 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */ 919 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%psr */ 920 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%psr */ 921 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, 0, 0, v6notv9 }, /* wr r,r,%wim */ 922 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, 0, 0, v6notv9 }, /* wr r,i,%wim */ 923 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */ 924 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */ 925 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%wim */ 926 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%wim */ 927 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, 0, 0, v6notv9 }, /* wr r,r,%tbr */ 928 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, 0, 0, v6notv9 }, /* wr r,i,%tbr */ 929 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */ 930 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */ 931 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%tbr */ 932 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%tbr */ 933 934 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, 0, v9 }, /* wr r,r,%ccr */ 935 { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, 0, 0, v9 }, /* wr r,i,%ccr */ 936 { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, 0, v9 }, /* wr r,r,%asi */ 937 { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, 0, 0, v9 }, /* wr r,i,%asi */ 938 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, 0, v9 }, /* wr r,r,%fprs */ 939 { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, 0, 0, v9 }, /* wr r,i,%fprs */ 940 { "wr", F3(2, 0x30, 0)|RD(14), F3(~2, ~0x30, ~0)|RD(~14), "1,2,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,r,%mcdper */ 941 { "wr", F3(2, 0x30, 1)|RD(14), F3(~2, ~0x30, ~1)|RD(~14), "1,i,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,i,%mcdper */ 942 943 /* Write to ASR registers 16..31, which is the range defined in SPARC 944 V9 for implementation-dependent uses. Note that the read-only ASR 945 registers can't be used in a `wr' instruction. */ 946 947 #define wrasr(asr,hwcap,hwcap2,arch) \ 948 { "wr", F3(2, 0x30, 0)|RD((asr)), F3(~2, ~0x30, ~0)|RD(~(asr))|ASI(~0), "1,2,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,r,%asr */ \ 949 { "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "1,i,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,i,%asr */ \ 950 { "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "i,1,_", F_ALIAS, (hwcap), (hwcap2), (arch) } /* wr i,r,%asr */ 951 952 wrasr (16, HWCAP_VIS, 0, v9a), /* wr ...,%pcr */ 953 wrasr (17, HWCAP_VIS, 0, v9a), /* wr ...,%pic */ 954 wrasr (18, HWCAP_VIS, 0, v9a), /* wr ...,%dcr */ 955 wrasr (19, HWCAP_VIS, 0, v9a), /* wr ...,%gsr */ 956 wrasr (20, HWCAP_VIS, 0, v9a), /* wr ...,%softint_set */ 957 wrasr (21, HWCAP_VIS, 0, v9a), /* wr ...,%softint_clear */ 958 wrasr (22, HWCAP_VIS, 0, v9a), /* wr ...,%softint */ 959 wrasr (23, HWCAP_VIS, 0, v9a), /* wr ...,%tick_cmpr */ 960 wrasr (24, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick */ 961 wrasr (25, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick_cmpr */ 962 wrasr (26, HWCAP_CBCOND, 0, v9e), /* wr ...,%cfr */ 963 wrasr (27, HWCAP_PAUSE, 0, v9e), /* wr ...,%pause */ 964 wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait */ 965 966 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9e }, /* wr %g0,i,%pause */ 967 968 { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, 0, v9 }, /* rd %ccr,r */ 969 { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, 0, v9 }, /* rd %asi,r */ 970 { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9 }, /* rd %tick,r */ 971 { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9 }, /* rd %pc,r */ 972 { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9 }, /* rd %fprs,r */ 973 { "rd", F3(2, 0x28, 0)|RS1(14), F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0), "{,d", 0, 0, HWCAP2_SPARC5, v9m }, /* rd %mcdper,r */ 974 975 /* Read from ASR registers 16..31, which is the range defined in SPARC 976 V9 for implementation-dependent uses. Note that the write-only ASR 977 registers can't be used in a `rd' instruction. */ 978 979 #define rdasr(asr,hwcap,hwcap2,arch) \ 980 { "rd", F3(2, 0x28, 0)|RS1((asr)), F3(~2, ~0x28, ~0)|RS1(~(asr))|SIMM13(~0), "/,d", 0, (hwcap), (hwcap2), (arch) } 981 982 rdasr (16, HWCAP_VIS, 0, v9a), /* rd %pcr,r */ 983 rdasr (17, HWCAP_VIS, 0, v9a), /* rd %pic,r */ 984 rdasr (18, HWCAP_VIS, 0, v9a), /* rd %dcr,r */ 985 rdasr (19, HWCAP_VIS, 0, v9a), /* rd %gsr,r */ 986 rdasr (22, HWCAP_VIS, 0, v9a), /* rd %softint,r */ 987 rdasr (23, HWCAP_VIS, 0, v9a), /* rd %tick_cmpr,r */ 988 rdasr (24, HWCAP_VIS2, 0, v9b), /* rd %sys_tick,r */ 989 rdasr (25, HWCAP_VIS2, 0, v9b), /* rd %sys_tick_cmpr,r */ 990 rdasr (26, HWCAP_CBCOND, 0, v9e), /* rd %cfr,r */ 991 992 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, 0, v8 }, /* rd %asrX,r */ 993 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, 0, 0, v6 }, /* rd %y,r */ 994 { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, 0, 0, v6notv9 }, /* rd %psr,r */ 995 { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, 0, 0, v6notv9 }, /* rd %wim,r */ 996 { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, 0, 0, v6notv9 }, /* rd %tbr,r */ 997 998 /* Instructions to read and write from/to privileged registers. */ 999 1000 #define rdpr(reg,hwcap,hwcap2,arch) \ 1001 { "rdpr", F3(2, 0x2a, 0)|RS1((reg)), F3(~2, ~0x2a, ~0)|RS1(~(reg))|SIMM13(~0),"?,d", 0, (hwcap), (hwcap2), (arch) } /* rdpr %priv,r */ 1002 1003 rdpr (0, 0, 0, v9), /* rdpr %tpc,r */ 1004 rdpr (1, 0, 0, v9), /* rdpr %tnpc,r */ 1005 rdpr (2, 0, 0, v9), /* rdpr %tstate,r */ 1006 rdpr (3, 0, 0, v9), /* rdpr %tt,r */ 1007 rdpr (4, 0, 0, v9), /* rdpr %tick,r */ 1008 rdpr (5, 0, 0, v9), /* rdpr %tba,r */ 1009 rdpr (6, 0, 0, v9), /* rdpr %pstate,r */ 1010 rdpr (7, 0, 0, v9), /* rdpr %tl,r */ 1011 rdpr (8, 0, 0, v9), /* rdpr %pil,r */ 1012 rdpr (9, 0, 0, v9), /* rdpr %cwp,r */ 1013 rdpr (10, 0, 0, v9), /* rdpr %cansave,r */ 1014 rdpr (11, 0, 0, v9), /* rdpr %canrestore,r */ 1015 rdpr (12, 0, 0, v9), /* rdpr %cleanwin,r */ 1016 rdpr (13, 0, 0, v9), /* rdpr %otherwin,r */ 1017 rdpr (14, 0, 0, v9), /* rdpr %wstate,r */ 1018 rdpr (15, 0, 0, v9), /* rdpr %fq,r */ 1019 rdpr (16, 0, 0, v9), /* rdpr %gl,r */ 1020 rdpr (23, 0, HWCAP2_SPARC5, v9m), /* rdpr %pmcdper,r */ 1021 rdpr (31, 0, 0, v9), /* rdpr %ver,r */ 1022 1023 #define wrpr(reg,hwcap,hwcap2,arch) \ 1024 { "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg)), "1,2,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,r2,%priv */ \ 1025 { "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg))|SIMM13(~0), "1,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,%priv */ \ 1026 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "1,i,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,i,%priv */ \ 1027 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "i,1,!", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrpr i,r1,%priv */ \ 1028 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg))|RS1(~0), "i,!", 0, (hwcap), (hwcap2), (arch) } /* wrpr i,%priv */ 1029 1030 wrpr (0, 0, 0, v9), /* wrpr ...,%tpc */ 1031 wrpr (1, 0, 0, v9), /* wrpr ...,%tnpc */ 1032 wrpr (2, 0, 0, v9), /* wrpr ...,%tstate */ 1033 wrpr (3, 0, 0, v9), /* wrpr ...,%tt */ 1034 wrpr (4, 0, 0, v9), /* wrpr ...,%tick */ 1035 wrpr (5, 0, 0, v9), /* wrpr ...,%tba */ 1036 wrpr (6, 0, 0, v9), /* wrpr ...,%pstate */ 1037 wrpr (7, 0, 0, v9), /* wrpr ...,%tl */ 1038 wrpr (8, 0, 0, v9), /* wrpr ...,%pil */ 1039 wrpr (9, 0, 0, v9), /* wrpr ...,%cwp */ 1040 wrpr (10, 0, 0, v9), /* wrpr ...,%cansave */ 1041 wrpr (11, 0, 0, v9), /* wrpr ...,%canrestore */ 1042 wrpr (12, 0, 0, v9), /* wrpr ...,%cleanwin */ 1043 wrpr (13, 0, 0, v9), /* wrpr ...,%otherwin */ 1044 wrpr (14, 0, 0, v9), /* wrpr ...,%wstate */ 1045 wrpr (15, 0, 0, v9), /* wrpr ...,%fq */ 1046 wrpr (16, 0, 0, v9), /* wrpr ...,%gl */ 1047 wrpr (23, 0, HWCAP2_SPARC5, v9m), /* wdpr ...,%pmcdper */ 1048 wrpr (31, 0, 0, v9), /* wrpr ...,%ver */ 1049 1050 /* Instructions to read and write from/to hyperprivileged 1051 registers. */ 1052 1053 #define rdhpr(reg,hwcap,hwcap2,arch) \ 1054 { "rdhpr", F3(2, 0x29, 0)|RS1((reg)), F3(~2, ~0x29, ~0)|RS1(~(reg))|SIMM13(~0), "$,d", 0, (hwcap), (hwcap2), (arch) } 1055 1056 rdhpr (0, HWCAP_VIS, 0, v9a), /* rdhpr %hpstate,r */ 1057 rdhpr (1, HWCAP_VIS, 0, v9a), /* rdhpr %htstate,r */ 1058 rdhpr (3, HWCAP_VIS, 0, v9a), /* rdhpr %hintp,r */ 1059 rdhpr (5, HWCAP_VIS, 0, v9a), /* rdhpr %htba,r */ 1060 rdhpr (6, HWCAP_VIS, 0, v9a), /* rdhpr %hver,r */ 1061 rdhpr (23, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcdper,r */ 1062 rdhpr (24, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcddfr,r */ 1063 rdhpr (27, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hva_mask_nz,r */ 1064 rdhpr (28, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_offset,r */ 1065 rdhpr (29, HWCAP_VIS, 0, v9a), /* rdhpar %hstick_enable,r */ 1066 rdhpr (31, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_cmpr,r */ 1067 1068 #define wrhpr(reg,hwcap,hwcap2,arch) \ 1069 { "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg)),"1,2,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,r2,%hpriv */ \ 1070 { "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg))|SIMM13(~0), "1,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,%hpriv */ \ 1071 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "1,i,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,i,%hpriv */ \ 1072 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "i,1,%", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrhpr i,r1,%hpriv */ \ 1073 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg))|RS1(~0), "i,%", 0, (hwcap), (hwcap2), (arch) } /* wrhpr i,%hpriv */ 1074 1075 wrhpr (0, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hpstate */ 1076 wrhpr (1, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htstate */ 1077 wrhpr (3, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hintp */ 1078 wrhpr (5, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htba */ 1079 wrhpr (23, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcdper */ 1080 wrhpr (24, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcddfr */ 1081 wrhpr (27, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hva_mask_nz */ 1082 wrhpr (28, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_offset */ 1083 wrhpr (29, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_enable */ 1084 wrhpr (31, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_cmpr */ 1085 1086 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, 0, 0, v8 }, /* rd %asr1,r */ 1087 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, 0, 0, v6 }, /* rd %y,r */ 1088 { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %psr,r */ 1089 { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %wim,r */ 1090 { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %tbr,r */ 1091 1092 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */ 1093 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */ 1094 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */ 1095 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */ 1096 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */ 1097 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */ 1098 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */ 1099 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */ 1100 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */ 1101 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */ 1102 1103 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, 0, 0, v6 }, /* or %g0,rs2,d */ 1104 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, 0, 0, v6 }, /* or %g0,i,d */ 1105 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, 0, 0, v6 }, /* or rs1,%g0,d */ 1106 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, 0, 0, v6 }, /* or rs1,0,d */ 1107 1108 { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1109 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, 0, 0, v6 }, 1110 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, 0, 0, v6 }, 1111 1112 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* or rd,rs2,rd */ 1113 { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* or rd,i,rd */ 1114 1115 /* This is not a commutative instruction. */ 1116 { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1117 { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, 0, 0, v6 }, 1118 1119 /* This is not a commutative instruction. */ 1120 { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1121 { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, 0, 0, v6 }, 1122 1123 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* andn rd,rs2,rd */ 1124 { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* andn rd,i,rd */ 1125 1126 { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, 0, 0, v6 }, /* subcc rs1,rs2,%g0 */ 1127 { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, 0, 0, v6 }, /* subcc rs1,i,%g0 */ 1128 1129 { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1130 { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, 0, 0, v6 }, 1131 1132 { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1133 { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, 0, 0, v6 }, 1134 1135 { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1136 { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1137 { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1138 { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v9 }, 1139 1140 { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1141 { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1142 { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1143 { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v9 }, 1144 1145 { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1146 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, 0, 0, v6 }, 1147 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, 0, 0, v6 }, 1148 1149 { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1150 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, 0, 0, v6 }, 1151 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, 0, 0, v6 }, 1152 1153 { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* sub rd,1,rd */ 1154 { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* sub rd,imm,rd */ 1155 { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* subcc rd,1,rd */ 1156 { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* subcc rd,imm,rd */ 1157 { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* add rd,1,rd */ 1158 { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* add rd,imm,rd */ 1159 { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* addcc rd,1,rd */ 1160 { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* addcc rd,imm,rd */ 1161 1162 { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, 0, v6 }, /* andcc rs1,rs2,%g0 */ 1163 { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, 0, v6 }, /* andcc rs1,i,%g0 */ 1164 1165 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, 0, v6 }, /* sub %g0,rs2,rd */ 1166 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, 0, v6 }, /* sub %g0,rd,rd */ 1167 1168 { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1169 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, 0, 0, v6 }, 1170 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, 0, 0, v6 }, 1171 { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1172 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, 0, 0, v6 }, 1173 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, 0, 0, v6 }, 1174 1175 { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1176 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1177 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v6notv9 }, 1178 { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1179 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v9 }, 1180 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v9 }, 1181 1182 { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1183 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1184 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v6notv9 }, 1185 { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1186 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v9 }, 1187 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v9 }, 1188 1189 { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1190 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1191 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1192 { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1193 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1194 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1195 { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1196 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1197 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1198 { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1199 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1200 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1201 { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1202 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1203 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1204 { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1205 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1206 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1207 { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1208 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1209 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1210 { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1211 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1212 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1213 1214 { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1215 { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, 0, 0, v9 }, 1216 { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1217 { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, v9 }, 1218 { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1219 { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, 0, 0, v9 }, 1220 1221 { "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, 0, v6 }, 1222 { "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1223 1224 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%o7 */ 1225 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1226 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%o7 */ 1227 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1228 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%o7 */ 1229 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1230 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%o7 */ 1231 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1232 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%o7 */ 1233 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1234 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%o7 */ 1235 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1236 1237 /* Conditional instructions. 1238 1239 Because this part of the table was such a mess earlier, I have 1240 macrofied it so that all the branches and traps are generated from 1241 a single-line description of each condition value. John Gilmore. */ 1242 1243 /* Define branches -- one annulled, one without, etc. */ 1244 #define br(opcode, mask, lose, flags) \ 1245 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), 0, 0, v6 }, \ 1246 { opcode, (mask) , (lose)|ANNUL, "l", (flags), 0, 0, v6 } 1247 1248 #define brx(opcode, mask, lose, flags) /* v9 */ \ 1249 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), 0, 0, v9 }, \ 1250 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), 0, 0, v9 }, \ 1251 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), 0, 0, v9 }, \ 1252 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, 0, v9 }, \ 1253 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), 0, 0, v9 }, \ 1254 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, 0, v9 }, \ 1255 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), 0, 0, v9 }, \ 1256 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), 0, 0, v9 }, \ 1257 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), 0, 0, v9 }, \ 1258 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, 0, v9 }, \ 1259 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), 0, 0, v9 }, \ 1260 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, 0, v9 } 1261 1262 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ 1263 #define tr(opcode, mask, lose, flags) \ 1264 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), 0, 0, v9 }, /* %g0 + imm */ \ 1265 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), 0, 0, v9 }, /* rs1 + imm */ \ 1266 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), 0, 0, v9 }, /* rs1 + rs2 */ \ 1267 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), 0, 0, v9 }, /* rs1 + %g0 */ \ 1268 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, 0, 0, v9 }, /* %g0 + imm */ \ 1269 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + imm */ \ 1270 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + rs2 */ \ 1271 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + %g0 */ \ 1272 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), 0, 0, v6 }, /* %g0 + imm */ \ 1273 { opcode, (mask)|IMMED, (lose), "1+i", (flags), 0, 0, v6 }, /* rs1 + imm */ \ 1274 { opcode, (mask)|IMMED, (lose), "i+1", (flags), 0, 0, v6 }, /* imm + rs1 */ \ 1275 { opcode, (mask), IMMED|(lose), "1+2", (flags), 0, 0, v6 }, /* rs1 + rs2 */ \ 1276 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), 0, 0, v6 } /* rs1 + %g0 */ 1277 1278 /* v9: We must put `brx' before `br', to ensure that we never match something 1279 v9: against an expression unless it is an expression. Otherwise, we end 1280 v9: up with undefined symbol tables entries, because they get added, but 1281 v9: are not deleted if the pattern fails to match. */ 1282 1283 /* Define both branches and traps based on condition mask */ 1284 #define cond(bop, top, mask, flags) \ 1285 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ 1286 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ 1287 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) 1288 1289 /* Define all the conditions, all the branches, all the traps. */ 1290 1291 /* Standard branch, trap mnemonics */ 1292 cond ("b", "ta", CONDA, F_UNBR), 1293 /* Alternative form (just for assembly, not for disassembly) */ 1294 cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), 1295 1296 cond ("bcc", "tcc", CONDCC, F_CONDBR), 1297 cond ("bcs", "tcs", CONDCS, F_CONDBR), 1298 cond ("be", "te", CONDE, F_CONDBR), 1299 cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), 1300 cond ("bg", "tg", CONDG, F_CONDBR), 1301 cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), 1302 cond ("bge", "tge", CONDGE, F_CONDBR), 1303 cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ 1304 cond ("bgu", "tgu", CONDGU, F_CONDBR), 1305 cond ("bl", "tl", CONDL, F_CONDBR), 1306 cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), 1307 cond ("ble", "tle", CONDLE, F_CONDBR), 1308 cond ("bleu", "tleu", CONDLEU, F_CONDBR), 1309 cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ 1310 cond ("bn", "tn", CONDN, F_CONDBR), 1311 cond ("bne", "tne", CONDNE, F_CONDBR), 1312 cond ("bneg", "tneg", CONDNEG, F_CONDBR), 1313 cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ 1314 cond ("bpos", "tpos", CONDPOS, F_CONDBR), 1315 cond ("bvc", "tvc", CONDVC, F_CONDBR), 1316 cond ("bvs", "tvs", CONDVS, F_CONDBR), 1317 cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ 1318 1319 #undef cond 1320 #undef br 1321 #undef brr /* v9 */ 1322 #undef tr 1323 1324 #define brr(opcode, mask, lose, flags) /* v9 */ \ 1325 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1326 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1327 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1328 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1329 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1330 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, 0, v9 } 1331 1332 #define condr(bop, mask, flags) /* v9 */ \ 1333 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ 1334 1335 /* v9 */ condr("brnz", 0x5, F_CONDBR), 1336 /* v9 */ condr("brz", 0x1, F_CONDBR), 1337 /* v9 */ condr("brgez", 0x7, F_CONDBR), 1338 /* v9 */ condr("brlz", 0x3, F_CONDBR), 1339 /* v9 */ condr("brlez", 0x2, F_CONDBR), 1340 /* v9 */ condr("brgz", 0x6, F_CONDBR), 1341 1342 #define cbcond(cop, cmask, flgs) \ 1343 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \ 1344 "1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \ 1345 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \ 1346 "1,X,=", flgs, HWCAP_CBCOND, 0, v9e}, \ 1347 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \ 1348 "1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \ 1349 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \ 1350 "1,X,=", flgs, HWCAP_CBCOND, 0, v9e}, 1351 1352 cbcond("be", 0x09, F_CONDBR) 1353 cbcond("bz", 0x09, F_CONDBR|F_ALIAS) 1354 cbcond("ble", 0x0a, F_CONDBR) 1355 cbcond("bl", 0x0b, F_CONDBR) 1356 cbcond("bleu", 0x0c, F_CONDBR) 1357 cbcond("bcs", 0x0d, F_CONDBR) 1358 cbcond("blu", 0x0d, F_CONDBR|F_ALIAS) 1359 cbcond("bneg", 0x0e, F_CONDBR) 1360 cbcond("bvs", 0x0f, F_CONDBR) 1361 cbcond("bne", 0x19, F_CONDBR) 1362 cbcond("bnz", 0x19, F_CONDBR|F_ALIAS) 1363 cbcond("bg", 0x1a, F_CONDBR) 1364 cbcond("bge", 0x1b, F_CONDBR) 1365 cbcond("bgu", 0x1c, F_CONDBR) 1366 cbcond("bcc", 0x1d, F_CONDBR) 1367 cbcond("bgeu", 0x1d, F_CONDBR|F_ALIAS) 1368 cbcond("bpos", 0x1e, F_CONDBR) 1369 cbcond("bvc", 0x1f, F_CONDBR) 1370 1371 #undef cbcond 1372 #undef condr /* v9 */ 1373 #undef brr /* v9 */ 1374 1375 #define movr(opcode, mask, flags) /* v9 */ \ 1376 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, 0, v9 }, \ 1377 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, 0, v9 } 1378 1379 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \ 1380 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, 0, v9 } 1381 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \ 1382 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, 0, v9 } 1383 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \ 1384 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, 0, v9 } 1385 1386 #define fmovrs(mop, mask, flags) /* v9 */ \ 1387 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ 1388 #define fmovrd(mop, mask, flags) /* v9 */ \ 1389 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ 1390 #define fmovrq(mop, mask, flags) /* v9 */ \ 1391 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ 1392 1393 /* v9 */ movr("movrne", 0x5, 0), 1394 /* v9 */ movr("movre", 0x1, 0), 1395 /* v9 */ movr("movrgez", 0x7, 0), 1396 /* v9 */ movr("movrlz", 0x3, 0), 1397 /* v9 */ movr("movrlez", 0x2, 0), 1398 /* v9 */ movr("movrgz", 0x6, 0), 1399 /* v9 */ movr("movrnz", 0x5, F_ALIAS), 1400 /* v9 */ movr("movrz", 0x1, F_ALIAS), 1401 1402 /* v9 */ fmovrs("fmovrsne", 0x5, 0), 1403 /* v9 */ fmovrs("fmovrse", 0x1, 0), 1404 /* v9 */ fmovrs("fmovrsgez", 0x7, 0), 1405 /* v9 */ fmovrs("fmovrslz", 0x3, 0), 1406 /* v9 */ fmovrs("fmovrslez", 0x2, 0), 1407 /* v9 */ fmovrs("fmovrsgz", 0x6, 0), 1408 /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), 1409 /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), 1410 1411 /* v9 */ fmovrd("fmovrdne", 0x5, 0), 1412 /* v9 */ fmovrd("fmovrde", 0x1, 0), 1413 /* v9 */ fmovrd("fmovrdgez", 0x7, 0), 1414 /* v9 */ fmovrd("fmovrdlz", 0x3, 0), 1415 /* v9 */ fmovrd("fmovrdlez", 0x2, 0), 1416 /* v9 */ fmovrd("fmovrdgz", 0x6, 0), 1417 /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), 1418 /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), 1419 1420 /* v9 */ fmovrq("fmovrqne", 0x5, 0), 1421 /* v9 */ fmovrq("fmovrqe", 0x1, 0), 1422 /* v9 */ fmovrq("fmovrqgez", 0x7, 0), 1423 /* v9 */ fmovrq("fmovrqlz", 0x3, 0), 1424 /* v9 */ fmovrq("fmovrqlez", 0x2, 0), 1425 /* v9 */ fmovrq("fmovrqgz", 0x6, 0), 1426 /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), 1427 /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), 1428 1429 #undef movr /* v9 */ 1430 #undef fmovr /* v9 */ 1431 #undef fmrr /* v9 */ 1432 1433 #define movicc(opcode, cond, flags) /* v9 */ \ 1434 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, 0, v9 }, \ 1435 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, 0, v9 }, \ 1436 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, 0, 0, v9 }, \ 1437 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, 0, 0, v9 } 1438 1439 #define movfcc(opcode, fcond, flags) /* v9 */ \ 1440 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, 0, v9 }, \ 1441 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, 0, v9 }, \ 1442 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, 0, v9 }, \ 1443 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, 0, v9 }, \ 1444 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, 0, v9 }, \ 1445 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, 0, v9 }, \ 1446 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, 0, v9 }, \ 1447 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, 0, v9 } 1448 1449 #define movcc(opcode, cond, fcond, flags) /* v9 */ \ 1450 movfcc (opcode, fcond, flags), /* v9 */ \ 1451 movicc (opcode, cond, flags) /* v9 */ 1452 1453 /* v9 */ movcc ("mova", CONDA, FCONDA, 0), 1454 /* v9 */ movicc ("movcc", CONDCC, 0), 1455 /* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), 1456 /* v9 */ movicc ("movcs", CONDCS, 0), 1457 /* v9 */ movicc ("movlu", CONDLU, F_ALIAS), 1458 /* v9 */ movcc ("move", CONDE, FCONDE, 0), 1459 /* v9 */ movcc ("movg", CONDG, FCONDG, 0), 1460 /* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), 1461 /* v9 */ movicc ("movgu", CONDGU, 0), 1462 /* v9 */ movcc ("movl", CONDL, FCONDL, 0), 1463 /* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), 1464 /* v9 */ movicc ("movleu", CONDLEU, 0), 1465 /* v9 */ movfcc ("movlg", FCONDLG, 0), 1466 /* v9 */ movcc ("movn", CONDN, FCONDN, 0), 1467 /* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), 1468 /* v9 */ movicc ("movneg", CONDNEG, 0), 1469 /* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), 1470 /* v9 */ movfcc ("movo", FCONDO, 0), 1471 /* v9 */ movicc ("movpos", CONDPOS, 0), 1472 /* v9 */ movfcc ("movu", FCONDU, 0), 1473 /* v9 */ movfcc ("movue", FCONDUE, 0), 1474 /* v9 */ movfcc ("movug", FCONDUG, 0), 1475 /* v9 */ movfcc ("movuge", FCONDUGE, 0), 1476 /* v9 */ movfcc ("movul", FCONDUL, 0), 1477 /* v9 */ movfcc ("movule", FCONDULE, 0), 1478 /* v9 */ movicc ("movvc", CONDVC, 0), 1479 /* v9 */ movicc ("movvs", CONDVS, 0), 1480 /* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), 1481 1482 #undef movicc /* v9 */ 1483 #undef movfcc /* v9 */ 1484 #undef movcc /* v9 */ 1485 1486 #define FM_SF 1 /* v9 - values for fpsize */ 1487 #define FM_DF 2 /* v9 */ 1488 #define FM_QF 3 /* v9 */ 1489 1490 #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ 1491 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, 0, 0, v9 }, \ 1492 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, 0, 0, v9 } 1493 1494 #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ 1495 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, 0, v9 }, \ 1496 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, 0, v9 }, \ 1497 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, 0, v9 }, \ 1498 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, 0, v9 } 1499 1500 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ 1501 #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ 1502 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, 0, 0, v9 }, \ 1503 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, 0, v9 }, \ 1504 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, 0, 0, v9 }, \ 1505 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, 0, v9 }, \ 1506 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, 0, v9 }, \ 1507 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, 0, v9 } 1508 1509 #define fmovicc(suffix, cond, flags) /* v9 */ \ 1510 fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ 1511 fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ 1512 fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) 1513 1514 #define fmovfcc(suffix, fcond, flags) /* v9 */ \ 1515 fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ 1516 fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ 1517 fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) 1518 1519 #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ 1520 fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ 1521 fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ 1522 fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) 1523 1524 /* v9 */ fmovcc ("a", CONDA, FCONDA, 0), 1525 /* v9 */ fmovicc ("cc", CONDCC, 0), 1526 /* v9 */ fmovicc ("cs", CONDCS, 0), 1527 /* v9 */ fmovcc ("e", CONDE, FCONDE, 0), 1528 /* v9 */ fmovcc ("g", CONDG, FCONDG, 0), 1529 /* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0), 1530 /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS), 1531 /* v9 */ fmovicc ("gu", CONDGU, 0), 1532 /* v9 */ fmovcc ("l", CONDL, FCONDL, 0), 1533 /* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0), 1534 /* v9 */ fmovicc ("leu", CONDLEU, 0), 1535 /* v9 */ fmovfcc ("lg", FCONDLG, 0), 1536 /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS), 1537 /* v9 */ fmovcc ("n", CONDN, FCONDN, 0), 1538 /* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0), 1539 /* v9 */ fmovicc ("neg", CONDNEG, 0), 1540 /* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS), 1541 /* v9 */ fmovfcc ("o", FCONDO, 0), 1542 /* v9 */ fmovicc ("pos", CONDPOS, 0), 1543 /* v9 */ fmovfcc ("u", FCONDU, 0), 1544 /* v9 */ fmovfcc ("ue", FCONDUE, 0), 1545 /* v9 */ fmovfcc ("ug", FCONDUG, 0), 1546 /* v9 */ fmovfcc ("uge", FCONDUGE, 0), 1547 /* v9 */ fmovfcc ("ul", FCONDUL, 0), 1548 /* v9 */ fmovfcc ("ule", FCONDULE, 0), 1549 /* v9 */ fmovicc ("vc", CONDVC, 0), 1550 /* v9 */ fmovicc ("vs", CONDVS, 0), 1551 /* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS), 1552 1553 #undef fmoviccx /* v9 */ 1554 #undef fmovfccx /* v9 */ 1555 #undef fmovccx /* v9 */ 1556 #undef fmovicc /* v9 */ 1557 #undef fmovfcc /* v9 */ 1558 #undef fmovcc /* v9 */ 1559 #undef FM_DF /* v9 */ 1560 #undef FM_QF /* v9 */ 1561 #undef FM_SF /* v9 */ 1562 1563 /* Coprocessor branches. */ 1564 #define CBR(opcode, mask, lose, flags, arch) \ 1565 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, 0, 0, arch }, \ 1566 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, 0, arch } 1567 1568 /* Floating point branches. */ 1569 #define FBR(opcode, mask, lose, flags) \ 1570 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, 0, 0, v6 }, \ 1571 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, 0, v6 } 1572 1573 /* V9 extended floating point branches. */ 1574 #define FBRX(opcode, mask, lose, flags) /* v9 */ \ 1575 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1576 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1577 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1578 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1579 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1580 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1581 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1582 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1583 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1584 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1585 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1586 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1587 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1588 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1589 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1590 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1591 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1592 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1593 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1594 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1595 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1596 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1597 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1598 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 } 1599 1600 /* v9: We must put `FBRX' before `FBR', to ensure that we never match 1601 v9: something against an expression unless it is an expression. Otherwise, 1602 v9: we end up with undefined symbol tables entries, because they get added, 1603 v9: but are not deleted if the pattern fails to match. */ 1604 1605 #define CONDFC(fop, cop, mask, flags) \ 1606 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ 1607 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ 1608 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) 1609 1610 #define CONDFCL(fop, cop, mask, flags) \ 1611 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ 1612 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ 1613 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) 1614 1615 #define CONDF(fop, mask, flags) \ 1616 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ 1617 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) 1618 1619 CONDFC ("fb", "cb", 0x8, F_UNBR), 1620 CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), 1621 CONDFC ("fbe", "cb0", 0x9, F_CONDBR), 1622 CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), 1623 CONDFC ("fbg", "cb2", 0x6, F_CONDBR), 1624 CONDFC ("fbge", "cb02", 0xb, F_CONDBR), 1625 CONDFC ("fbl", "cb1", 0x4, F_CONDBR), 1626 CONDFC ("fble", "cb01", 0xd, F_CONDBR), 1627 CONDFC ("fblg", "cb12", 0x2, F_CONDBR), 1628 CONDFCL ("fbn", "cbn", 0x0, F_UNBR), 1629 CONDFC ("fbne", "cb123", 0x1, F_CONDBR), 1630 CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), 1631 CONDFC ("fbo", "cb012", 0xf, F_CONDBR), 1632 CONDFC ("fbu", "cb3", 0x7, F_CONDBR), 1633 CONDFC ("fbue", "cb03", 0xa, F_CONDBR), 1634 CONDFC ("fbug", "cb23", 0x5, F_CONDBR), 1635 CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), 1636 CONDFC ("fbul", "cb13", 0x3, F_CONDBR), 1637 CONDFC ("fbule", "cb013", 0xe, F_CONDBR), 1638 1639 #undef CONDFC 1640 #undef CONDFCL 1641 #undef CONDF 1642 #undef CBR 1643 #undef FBR 1644 #undef FBRX /* v9 */ 1645 1646 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%g0 */ 1647 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%g0 */ 1648 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%g0 */ 1649 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%g0 */ 1650 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%g0 */ 1651 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%g0 */ 1652 1653 { "nop", F2(0, 4), 0xfeffffff, "", 0, 0, 0, v6 }, /* sethi 0, %g0 */ 1654 1655 { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v6 }, 1656 { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 }, 1657 { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 }, 1658 { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, 0, v9 }, 1659 1660 { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, 0, v6 }, 1661 1662 { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1663 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, 0, 0, v6 }, 1664 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, 0, 0, v6 }, 1665 { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1666 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, 0, 0, v6 }, 1667 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, 0, 0, v6 }, 1668 1669 { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1670 { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, 0, 0, v6 }, 1671 { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1672 { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, 0, 0, v6 }, 1673 1674 { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, 0, 0, v6notv9 }, 1675 { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, 0, v9 }, 1676 1677 /* This *is* a commutative instruction. */ 1678 { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1679 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, 0, 0, v6 }, 1680 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, 0, 0, v6 }, 1681 /* This *is* a commutative instruction. */ 1682 { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1683 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, 0, 0, v6 }, 1684 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, 0, 0, v6 }, 1685 { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1686 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, 0, 0, v6 }, 1687 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, 0, 0, v6 }, 1688 { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1689 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, 0, 0, v6 }, 1690 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, 0, 0, v6 }, 1691 1692 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, 0, v6 }, /* xnor rs1,%0,rd */ 1693 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, 0, v6 }, /* xnor rd,%0,rd */ 1694 1695 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* xor rd,rs2,rd */ 1696 { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* xor rd,i,rd */ 1697 1698 /* FPop1 and FPop2 are not instructions. Don't accept them. */ 1699 1700 { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 }, 1701 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1702 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 }, 1703 1704 { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1705 { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, 0, v9 }, 1706 { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, 0, v9 }, 1707 1708 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 }, 1709 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1710 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 }, 1711 1712 { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1713 { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, 0, v9 }, 1714 { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, 0, v9 }, 1715 1716 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, 0, v8 }, 1717 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 }, 1718 { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, 0, v8 }, 1719 { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 }, 1720 { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 }, 1721 { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 }, 1722 1723 { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, 0, v6 }, 1724 { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, 0, v8 }, 1725 { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1726 { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, 0, v6 }, 1727 { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, 0, v6 }, 1728 { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, 0, v8 }, 1729 { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1730 { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, 0, v6 }, 1731 1732 { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, 0, v8 }, 1733 { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1734 { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, 0, v8 }, 1735 1736 { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v7 }, 1737 { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v8 }, 1738 { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1739 { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, 0, v7 }, 1740 1741 { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1742 { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 }, 1743 { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1744 { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1745 { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1746 { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 }, 1747 { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1748 { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1749 { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1750 { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 }, 1751 { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1752 { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1753 1754 { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, 0, v6 }, 1755 { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, 0, v8 }, 1756 { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1757 { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, 0, v6 }, 1758 { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, 0, v6 }, 1759 { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, 0, v8 }, 1760 { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1761 { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, 0, v6 }, 1762 1763 #define CMPFCC(x) (((x)&0x3)<<25) 1764 1765 { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, 0, 0, v6 }, 1766 { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, 0, 0, v9 }, 1767 { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, 0, 0, v9 }, 1768 { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, 0, 0, v9 }, 1769 { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, 0, 0, v9 }, 1770 { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, 0, 0, v6 }, 1771 { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, 0, 0, v9 }, 1772 { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, 0, 0, v9 }, 1773 { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, 0, 0, v9 }, 1774 { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, 0, 0, v9 }, 1775 { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, 0, 0, v8 }, 1776 { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, 0, 0, v9 }, 1777 { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, 0, 0, v9 }, 1778 { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, 0, 0, v9 }, 1779 { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, 0, 0, v9 }, 1780 { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, 0, 0, v8 }, 1781 { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, 0, 0, v9 }, 1782 { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, 0, 0, v9 }, 1783 { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, 0, 0, v9 }, 1784 { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, 0, 0, v9 }, 1785 { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1786 { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1787 { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1788 { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1789 { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1790 { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1791 { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1792 { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1793 { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1794 { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1795 { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, 0, 0, v6 }, 1796 { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, 0, 0, v9 }, 1797 { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, 0, 0, v9 }, 1798 { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, 0, 0, v9 }, 1799 { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, 0, 0, v9 }, 1800 { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, 0, 0, v6 }, 1801 { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, 0, 0, v9 }, 1802 { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, 0, 0, v9 }, 1803 { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, 0, 0, v9 }, 1804 { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, 0, 0, v9 }, 1805 1806 /* These Extended FPop (FIFO) instructions are new in the Fujitsu 1807 MB86934, replacing the CPop instructions from v6 and later 1808 processors. */ 1809 1810 #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, 0, sparclite } 1811 #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, 0, 0, sparclite } 1812 #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, 0, 0, sparclite } 1813 1814 EFPOP1_2 ("efitod", 0x0c8, "f,H"), 1815 EFPOP1_2 ("efitos", 0x0c4, "f,g"), 1816 EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), 1817 EFPOP1_2 ("efstoi", 0x0d1, "f,g"), 1818 EFPOP1_2 ("efstod", 0x0c9, "f,H"), 1819 EFPOP1_2 ("efdtos", 0x0c6, "B,g"), 1820 EFPOP1_2 ("efmovs", 0x001, "f,g"), 1821 EFPOP1_2 ("efnegs", 0x005, "f,g"), 1822 EFPOP1_2 ("efabss", 0x009, "f,g"), 1823 EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), 1824 EFPOP1_2 ("efsqrts", 0x029, "f,g"), 1825 EFPOP1_3 ("efaddd", 0x042, "v,B,H"), 1826 EFPOP1_3 ("efadds", 0x041, "e,f,g"), 1827 EFPOP1_3 ("efsubd", 0x046, "v,B,H"), 1828 EFPOP1_3 ("efsubs", 0x045, "e,f,g"), 1829 EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), 1830 EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), 1831 EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), 1832 EFPOP1_3 ("efmuls", 0x049, "e,f,g"), 1833 EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), 1834 EFPOP2_2 ("efcmpd", 0x052, "v,B"), 1835 EFPOP2_2 ("efcmped", 0x056, "v,B"), 1836 EFPOP2_2 ("efcmps", 0x051, "e,f"), 1837 EFPOP2_2 ("efcmpes", 0x055, "e,f"), 1838 1839 #undef EFPOP1_2 1840 #undef EFPOP1_3 1841 #undef EFPOP2_2 1842 1843 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns 1844 present. Otherwise, the F_ALIAS flag is ignored. */ 1845 { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 }, 1846 { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 }, 1847 1848 /* sparclet specific insns */ 1849 1850 COMMUTEOP ("umac", 0x3e, letandleon), 1851 COMMUTEOP ("smac", 0x3f, letandleon), 1852 1853 COMMUTEOP ("umacd", 0x2e, sparclet), 1854 COMMUTEOP ("smacd", 0x2f, sparclet), 1855 COMMUTEOP ("umuld", 0x09, sparclet), 1856 COMMUTEOP ("smuld", 0x0d, sparclet), 1857 1858 { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet }, 1859 { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, sparclet }, 1860 1861 /* The manual isn't completely accurate on these insns. The `rs2' field is 1862 treated as being 6 bits to account for 6 bit immediates to cpush. It is 1863 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ 1864 #define BIT5 (1<<5) 1865 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, 0, sparclet }, 1866 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, 0, sparclet }, 1867 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet }, 1868 { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, 0, 0, sparclet }, 1869 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet }, 1870 { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, 0, 0, sparclet }, 1871 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet }, 1872 #undef BIT5 1873 1874 /* sparclet coprocessor branch insns */ 1875 #define SLCBCC2(opcode, mask, lose) \ 1876 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, 0, 0, sparclet }, \ 1877 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, 0, sparclet } 1878 #define SLCBCC(opcode, mask) \ 1879 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) 1880 1881 /* cbn,cba can't be defined here because they're defined elsewhere and GAS 1882 requires all mnemonics of the same name to be consecutive. */ 1883 /*SLCBCC("cbn", 0), - already defined */ 1884 SLCBCC("cbe", 1), 1885 SLCBCC("cbf", 2), 1886 SLCBCC("cbef", 3), 1887 SLCBCC("cbr", 4), 1888 SLCBCC("cber", 5), 1889 SLCBCC("cbfr", 6), 1890 SLCBCC("cbefr", 7), 1891 /*SLCBCC("cba", 8), - already defined */ 1892 SLCBCC("cbne", 9), 1893 SLCBCC("cbnf", 10), 1894 SLCBCC("cbnef", 11), 1895 SLCBCC("cbnr", 12), 1896 SLCBCC("cbner", 13), 1897 SLCBCC("cbnfr", 14), 1898 SLCBCC("cbnefr", 15), 1899 1900 #undef SLCBCC2 1901 #undef SLCBCC 1902 1903 { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, 0, v9andleon }, 1904 { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, 0, v9andleon }, 1905 { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, 0, v9 }, 1906 { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, 0, v9 }, 1907 1908 /* v9 synthetic insns */ 1909 { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, 0, v9 }, /* bn,a,pt %xcc,label */ 1910 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* sra rs1,%g0,rd */ 1911 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* sra rd,%g0,rd */ 1912 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* srl rs1,%g0,rd */ 1913 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* srl rd,%g0,rd */ 1914 { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */ 1915 { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ 1916 { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ 1917 { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ 1918 1919 /* Ultrasparc extensions */ 1920 { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, 0, v9a }, 1921 1922 /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ 1923 { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1924 { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1925 { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1926 { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1927 { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1928 { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1929 { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1930 { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1931 1932 { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1933 { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a }, 1934 { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a }, 1935 { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, 0, v9a }, 1936 { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 1937 1938 /* Note that the mixing of 32/64 bit regs is intentional. */ 1939 { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, 0, v9a }, 1940 { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 1941 { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 1942 { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1943 { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1944 { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 1945 { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 1946 1947 { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 1948 { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 1949 { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a }, /* faligndatag */ 1950 { "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9m }, /* faligndatai */ 1951 1952 { "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a }, 1953 { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1954 { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, 0, v9a }, 1955 { "foned", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, 0, v9a }, 1956 { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1957 { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, 0, v9a }, 1958 { "fsrc1d", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, 0, v9a }, 1959 { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1960 { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, 0, v9a }, 1961 { "fsrc2d", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, 0, v9a }, 1962 { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1963 { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, 0, v9a }, 1964 { "fnot1d", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, 0, v9a }, 1965 { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1966 { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, 0, v9a }, 1967 { "fnot2d", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, 0, v9a }, 1968 { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1969 { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, 0, v9a }, 1970 { "ford", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1971 { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1972 { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1973 { "fnord", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1974 { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1975 { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1976 { "fandd", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1977 { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1978 { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1979 { "fnandd", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1980 { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1981 { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1982 { "fxord", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1983 { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1984 { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1985 { "fxnord", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1986 { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1987 { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1988 { "fornot1d", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1989 { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1990 { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1991 { "fornot2d", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1992 { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1993 { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1994 { "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1995 { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1996 { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1997 { "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1998 { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 1999 { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2000 2001 { "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2002 { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2003 { "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2004 { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2005 { "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2006 { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2007 { "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2008 { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2009 { "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2010 { "fpcmpune16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2011 { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2012 { "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2013 { "fpcmpune32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2014 { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2015 { "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2016 { "fpcmpueq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2017 { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2018 { "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2019 { "fpcmpueq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2020 { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2021 2022 { "edge8cc", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2023 { "edge8lcc", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2024 { "edge16cc", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2025 { "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2026 { "edge32cc", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2027 { "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2028 2029 { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2030 { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2031 { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2032 { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2033 { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2034 { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2035 2036 { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2037 2038 { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2039 { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2040 { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2041 2042 /* Cheetah instructions */ 2043 { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2044 { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2045 { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2046 { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2047 { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2048 { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2049 2050 { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2051 { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, HWCAP_VIS2, 0, v9b }, 2052 2053 { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, HWCAP_VIS2, 0, v9b }, 2054 2055 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2056 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2057 { "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2058 { "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2059 { "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2060 { "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2061 { "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2062 { "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2063 { "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2064 { "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2065 { "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2066 { "fpmaddx", F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9v }, 2067 { "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2068 { "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2069 { "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9v }, 2070 { "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2071 { "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2072 { "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2073 { "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2074 { "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2075 { "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2076 { "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2077 { "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2078 { "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2079 { "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2080 { "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2081 { "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2082 { "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2083 { "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2084 { "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2085 { "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2086 { "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2087 { "lzcnt", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, 0, v9d }, 2088 { "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2089 { "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, 0, v9d }, 2090 { "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, 0, v9d }, 2091 { "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, 0, v9d }, 2092 { "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2093 { "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2094 { "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2095 { "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2096 { "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2097 { "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2098 { "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2099 { "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2100 { "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, 0, v9d }, 2101 { "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2102 { "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2103 { "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2104 { "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2105 { "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2106 { "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2107 { "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2108 { "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2109 { "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2110 { "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2111 { "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2112 { "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2113 { "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2114 { "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2115 { "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2116 { "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2117 { "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2118 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2119 { "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2120 { "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2121 { "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2122 { "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2123 { "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d }, 2124 { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2125 { "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2126 { "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2127 { "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2128 { "fpcmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d }, 2129 { "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2130 {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2131 {"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2132 { "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2133 { "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2134 { "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2135 {"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, 0, v9e }, 2136 { "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e }, 2137 {"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e }, 2138 { "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, 0, v9e }, 2139 { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9e }, 2140 { "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, 0, v9e }, 2141 { "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, 0, v9e }, 2142 { "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, 0, v9e }, 2143 { "xmpmul", F3F(2, 0x36, 0x148)|RD(1), F3F(~2, ~0x36, ~0x148)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMPMUL, v9m }, 2144 { "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, 0, v9e }, 2145 { "xmontmul", F3F(2, 0x36, 0x149)|RD(1), F3F(~2, ~0x36, ~0x149)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9m }, 2146 { "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, 0, v9e }, 2147 { "xmontsqr", F3F(2, 0x36, 0x14a)|RD(1), F3F(~2, ~0x36, ~0x14a)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9m }, 2148 { "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, 0, v9e }, 2149 {"aes_eround01", F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2150 {"aes_eround23", F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2151 {"aes_dround01", F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2152 {"aes_dround23", F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2153 {"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2154 {"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2155 {"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2156 {"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2157 {"aes_kexpand1", F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, 0, v9e }, 2158 {"des_round", F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2159 {"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9e }, 2160 {"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9e }, 2161 {"camellia_f", F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e }, 2162 { "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2163 { "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2164 { "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2165 { "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2166 { "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2167 { "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2168 { "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2169 { "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2170 2171 { "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0), "2", 0, 0, HWCAP2_MWAIT, v9m }, /* mwait r */ 2172 { "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9m }, /* mwait imm */ 2173 2174 /* Other SPARC5 and VIS4.0 instructions. */ 2175 2176 { "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5, v9m }, 2177 { "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5, v9m }, 2178 2179 { "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2180 { "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2181 { "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2182 { "fpaddus16", F3F(2, 0x36, 0x123), F3F(~2, ~0x36, ~0x123), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2183 { "fpcmple8", F3F(2, 0x36, 0x034), F3F(~2, ~0x36, ~0x034), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2184 { "fpcmpgt8", F3F(2, 0x36, 0x03c), F3F(~2, ~0x36, ~0x03c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2185 { "fpcmpule16", F3F(2, 0x36, 0x12e), F3F(~2, ~0x36, ~0x12e), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2186 { "fpcmpugt16", F3F(2, 0x36, 0x12b), F3F(~2, ~0x36, ~0x12b), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2187 { "fpcmpule32", F3F(2, 0x36, 0x12f), F3F(~2, ~0x36, ~0x12f), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2188 { "fpcmpugt32", F3F(2, 0x36, 0x12c), F3F(~2, ~0x36, ~0x12c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2189 { "fpmax8", F3F(2, 0x36, 0x11d), F3F(~2, ~0x36, ~0x11d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2190 { "fpmax16", F3F(2, 0x36, 0x11e), F3F(~2, ~0x36, ~0x11e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2191 { "fpmax32", F3F(2, 0x36, 0x11f), F3F(~2, ~0x36, ~0x11f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2192 { "fpmaxu8", F3F(2, 0x36, 0x15d), F3F(~2, ~0x36, ~0x15d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2193 { "fpmaxu16", F3F(2, 0x36, 0x15e), F3F(~2, ~0x36, ~0x15e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2194 { "fpmaxu32", F3F(2, 0x36, 0x15f), F3F(~2, ~0x36, ~0x15f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2195 { "fpmin8", F3F(2, 0x36, 0x11a), F3F(~2, ~0x36, ~0x11a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2196 { "fpmin16", F3F(2, 0x36, 0x11b), F3F(~2, ~0x36, ~0x11b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2197 { "fpmin32", F3F(2, 0x36, 0x11c), F3F(~2, ~0x36, ~0x11c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2198 { "fpminu8", F3F(2, 0x36, 0x15a), F3F(~2, ~0x36, ~0x15a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2199 { "fpminu16", F3F(2, 0x36, 0x15b), F3F(~2, ~0x36, ~0x15b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2200 { "fpminu32", F3F(2, 0x36, 0x15c), F3F(~2, ~0x36, ~0x15c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2201 { "fpsub8", F3F(2, 0x36, 0x154), F3F(~2, ~0x36, ~0x154), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2202 { "fpsubs8", F3F(2, 0x36, 0x156), F3F(~2, ~0x36, ~0x156), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2203 { "fpsubus8", F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2204 { "fpsubus16", F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2205 2206 /* More v9 specific insns, these need to come last so they do not clash 2207 with v9a instructions such as "edge8" which looks like impdep1. */ 2208 2209 #define IMPDEP(name, code) \ 2210 { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9notv9a }, \ 2211 { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, 0, 0, v9notv9a }, \ 2212 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, 0, 0, v9notv9a }, \ 2213 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, 0, 0, v9notv9a } 2214 2215 IMPDEP ("impdep1", 0x36), 2216 IMPDEP ("impdep2", 0x37), 2217 2218 #undef IMPDEP 2219 2220 }; 2221 2222 const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); 2223 2224 /* Utilities for argument parsing. */ 2225 2226 typedef struct 2227 { 2228 int value; 2229 const char *name; 2230 } arg; 2231 2232 /* Look up NAME in TABLE. */ 2233 2234 static int 2235 lookup_name (const arg *table, const char *name) 2236 { 2237 const arg *p; 2238 2239 for (p = table; p->name; ++p) 2240 if (strcmp (name, p->name) == 0) 2241 return p->value; 2242 2243 return -1; 2244 } 2245 2246 /* Look up VALUE in TABLE. */ 2247 2248 static const char * 2249 lookup_value (const arg *table, int value) 2250 { 2251 const arg *p; 2252 2253 for (p = table; p->name; ++p) 2254 if (value == p->value) 2255 return p->name; 2256 2257 return NULL; 2258 } 2259 2260 /* Handle ASI's. */ 2261 2262 static arg asi_table[] = 2263 { 2264 /* These are in the v9 architecture manual. */ 2265 /* The shorter versions appear first, they're here because Sun's as has them. 2266 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the 2267 UltraSPARC architecture manual). */ 2268 { 0x04, "#ASI_N" }, 2269 { 0x0c, "#ASI_N_L" }, 2270 { 0x10, "#ASI_AIUP" }, 2271 { 0x11, "#ASI_AIUS" }, 2272 { 0x18, "#ASI_AIUP_L" }, 2273 { 0x19, "#ASI_AIUS_L" }, 2274 { 0x80, "#ASI_P" }, 2275 { 0x81, "#ASI_S" }, 2276 { 0x82, "#ASI_PNF" }, 2277 { 0x83, "#ASI_SNF" }, 2278 { 0x88, "#ASI_P_L" }, 2279 { 0x89, "#ASI_S_L" }, 2280 { 0x8a, "#ASI_PNF_L" }, 2281 { 0x8b, "#ASI_SNF_L" }, 2282 { 0x04, "#ASI_NUCLEUS" }, 2283 { 0x0c, "#ASI_NUCLEUS_LITTLE" }, 2284 { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, 2285 { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, 2286 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, 2287 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, 2288 { 0x80, "#ASI_PRIMARY" }, 2289 { 0x81, "#ASI_SECONDARY" }, 2290 { 0x82, "#ASI_PRIMARY_NOFAULT" }, 2291 { 0x83, "#ASI_SECONDARY_NOFAULT" }, 2292 { 0x88, "#ASI_PRIMARY_LITTLE" }, 2293 { 0x89, "#ASI_SECONDARY_LITTLE" }, 2294 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, 2295 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, 2296 /* These are UltraSPARC and Niagara extensions. */ 2297 { 0x14, "#ASI_PHYS_USE_EC" }, 2298 { 0x15, "#ASI_PHYS_BYPASS_EC_E" }, 2299 { 0x16, "#ASI_BLK_AIUP_4V" }, 2300 { 0x17, "#ASI_BLK_AIUS_4V" }, 2301 { 0x1c, "#ASI_PHYS_USE_EC_L" }, 2302 { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" }, 2303 { 0x1e, "#ASI_BLK_AIUP_L_4V" }, 2304 { 0x1f, "#ASI_BLK_AIUS_L_4V" }, 2305 { 0x20, "#ASI_SCRATCHPAD" }, 2306 { 0x21, "#ASI_MMU" }, 2307 { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" }, 2308 { 0x24, "#ASI_NUCLEUS_QUAD_LDD" }, 2309 { 0x25, "#ASI_QUEUE" }, 2310 { 0x26, "#ASI_QUAD_LDD_PHYS_4V" }, 2311 { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" }, 2312 { 0x30, "#ASI_PCACHE_DATA_STATUS" }, 2313 { 0x31, "#ASI_PCACHE_DATA" }, 2314 { 0x32, "#ASI_PCACHE_TAG" }, 2315 { 0x33, "#ASI_PCACHE_SNOOP_TAG" }, 2316 { 0x34, "#ASI_QUAD_LDD_PHYS" }, 2317 { 0x38, "#ASI_WCACHE_VALID_BITS" }, 2318 { 0x39, "#ASI_WCACHE_DATA" }, 2319 { 0x3a, "#ASI_WCACHE_TAG" }, 2320 { 0x3b, "#ASI_WCACHE_SNOOP_TAG" }, 2321 { 0x3c, "#ASI_QUAD_LDD_PHYS_L" }, 2322 { 0x40, "#ASI_SRAM_FAST_INIT" }, 2323 { 0x41, "#ASI_CORE_AVAILABLE" }, 2324 { 0x41, "#ASI_CORE_ENABLE_STAT" }, 2325 { 0x41, "#ASI_CORE_ENABLE" }, 2326 { 0x41, "#ASI_XIR_STEERING" }, 2327 { 0x41, "#ASI_CORE_RUNNING_RW" }, 2328 { 0x41, "#ASI_CORE_RUNNING_W1S" }, 2329 { 0x41, "#ASI_CORE_RUNNING_W1C" }, 2330 { 0x41, "#ASI_CORE_RUNNING_STAT" }, 2331 { 0x41, "#ASI_CMT_ERROR_STEERING" }, 2332 { 0x41, "#ASI_DCACHE_INVALIDATE" }, 2333 { 0x41, "#ASI_DCACHE_UTAG" }, 2334 { 0x41, "#ASI_DCACHE_SNOOP_TAG" }, 2335 { 0x42, "#ASI_DCACHE_INVALIDATE" }, 2336 { 0x43, "#ASI_DCACHE_UTAG" }, 2337 { 0x44, "#ASI_DCACHE_SNOOP_TAG" }, 2338 { 0x45, "#ASI_LSU_CONTROL_REG" }, 2339 { 0x45, "#ASI_DCU_CONTROL_REG" }, 2340 { 0x46, "#ASI_DCACHE_DATA" }, 2341 { 0x47, "#ASI_DCACHE_TAG" }, 2342 { 0x48, "#ASI_INTR_DISPATCH_STAT" }, 2343 { 0x49, "#ASI_INTR_RECEIVE" }, 2344 { 0x4a, "#ASI_UPA_CONFIG" }, 2345 { 0x4a, "#ASI_JBUS_CONFIG" }, 2346 { 0x4a, "#ASI_SAFARI_CONFIG" }, 2347 { 0x4a, "#ASI_SAFARI_ADDRESS" }, 2348 { 0x4b, "#ASI_ESTATE_ERROR_EN" }, 2349 { 0x4c, "#ASI_AFSR" }, 2350 { 0x4d, "#ASI_AFAR" }, 2351 { 0x4e, "#ASI_EC_TAG_DATA" }, 2352 { 0x50, "#ASI_IMMU" }, 2353 { 0x51, "#ASI_IMMU_TSB_8KB_PTR" }, 2354 { 0x52, "#ASI_IMMU_TSB_16KB_PTR" }, 2355 { 0x54, "#ASI_ITLB_DATA_IN" }, 2356 { 0x55, "#ASI_ITLB_DATA_ACCESS" }, 2357 { 0x56, "#ASI_ITLB_TAG_READ" }, 2358 { 0x57, "#ASI_IMMU_DEMAP" }, 2359 { 0x58, "#ASI_DMMU" }, 2360 { 0x59, "#ASI_DMMU_TSB_8KB_PTR" }, 2361 { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" }, 2362 { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" }, 2363 { 0x5c, "#ASI_DTLB_DATA_IN" }, 2364 { 0x5d, "#ASI_DTLB_DATA_ACCESS" }, 2365 { 0x5e, "#ASI_DTLB_TAG_READ" }, 2366 { 0x5f, "#ASI_DMMU_DEMAP" }, 2367 { 0x60, "#ASI_IIU_INST_TRAP" }, 2368 { 0x63, "#ASI_INTR_ID" }, 2369 { 0x63, "#ASI_CORE_ID" }, 2370 { 0x63, "#ASI_CESR_ID" }, 2371 { 0x66, "#ASI_IC_INSTR" }, 2372 { 0x67, "#ASI_IC_TAG" }, 2373 { 0x68, "#ASI_IC_STAG" }, 2374 { 0x6e, "#ASI_IC_PRE_DECODE" }, 2375 { 0x6f, "#ASI_IC_NEXT_FIELD" }, 2376 { 0x6f, "#ASI_BRPRED_ARRAY" }, 2377 { 0x70, "#ASI_BLK_AIUP" }, 2378 { 0x71, "#ASI_BLK_AIUS" }, 2379 { 0x72, "#ASI_MCU_CTRL_REG" }, 2380 { 0x74, "#ASI_EC_DATA" }, 2381 { 0x75, "#ASI_EC_CTRL" }, 2382 { 0x76, "#ASI_EC_W" }, 2383 { 0x77, "#ASI_UDB_ERROR_W" }, 2384 { 0x77, "#ASI_UDB_CONTROL_W" }, 2385 { 0x77, "#ASI_INTR_W" }, 2386 { 0x77, "#ASI_INTR_DATAN_W" }, 2387 { 0x77, "#ASI_INTR_DISPATCH_W" }, 2388 { 0x78, "#ASI_BLK_AIUPL" }, 2389 { 0x79, "#ASI_BLK_AIUSL" }, 2390 { 0x7e, "#ASI_EC_R" }, 2391 { 0x7f, "#ASI_UDBH_ERROR_R" }, 2392 { 0x7f, "#ASI_UDBL_ERROR_R" }, 2393 { 0x7f, "#ASI_UDBH_CONTROL_R" }, 2394 { 0x7f, "#ASI_UDBL_CONTROL_R" }, 2395 { 0x7f, "#ASI_INTR_R" }, 2396 { 0x7f, "#ASI_INTR_DATAN_R" }, 2397 { 0xc0, "#ASI_PST8_P" }, 2398 { 0xc1, "#ASI_PST8_S" }, 2399 { 0xc2, "#ASI_PST16_P" }, 2400 { 0xc3, "#ASI_PST16_S" }, 2401 { 0xc4, "#ASI_PST32_P" }, 2402 { 0xc5, "#ASI_PST32_S" }, 2403 { 0xc8, "#ASI_PST8_PL" }, 2404 { 0xc9, "#ASI_PST8_SL" }, 2405 { 0xca, "#ASI_PST16_PL" }, 2406 { 0xcb, "#ASI_PST16_SL" }, 2407 { 0xcc, "#ASI_PST32_PL" }, 2408 { 0xcd, "#ASI_PST32_SL" }, 2409 { 0xd0, "#ASI_FL8_P" }, 2410 { 0xd1, "#ASI_FL8_S" }, 2411 { 0xd2, "#ASI_FL16_P" }, 2412 { 0xd3, "#ASI_FL16_S" }, 2413 { 0xd8, "#ASI_FL8_PL" }, 2414 { 0xd9, "#ASI_FL8_SL" }, 2415 { 0xda, "#ASI_FL16_PL" }, 2416 { 0xdb, "#ASI_FL16_SL" }, 2417 { 0xe0, "#ASI_BLK_COMMIT_P", }, 2418 { 0xe1, "#ASI_BLK_COMMIT_S", }, 2419 { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" }, 2420 { 0xf0, "#ASI_BLK_P", }, 2421 { 0xf1, "#ASI_BLK_S", }, 2422 { 0xf8, "#ASI_BLK_PL", }, 2423 { 0xf9, "#ASI_BLK_SL", }, 2424 { 0, 0 } 2425 }; 2426 2427 /* Return the value for ASI NAME, or -1 if not found. */ 2428 2429 int 2430 sparc_encode_asi (const char *name) 2431 { 2432 return lookup_name (asi_table, name); 2433 } 2434 2435 /* Return the name for ASI value VALUE or NULL if not found. */ 2436 2437 const char * 2438 sparc_decode_asi (int value) 2439 { 2440 return lookup_value (asi_table, value); 2441 } 2442 2443 /* Handle membar masks. */ 2444 2445 static arg membar_table[] = 2446 { 2447 { 0x40, "#Sync" }, 2448 { 0x20, "#MemIssue" }, 2449 { 0x10, "#Lookaside" }, 2450 { 0x08, "#StoreStore" }, 2451 { 0x04, "#LoadStore" }, 2452 { 0x02, "#StoreLoad" }, 2453 { 0x01, "#LoadLoad" }, 2454 { 0, 0 } 2455 }; 2456 2457 /* Return the value for membar arg NAME, or -1 if not found. */ 2458 2459 int 2460 sparc_encode_membar (const char *name) 2461 { 2462 return lookup_name (membar_table, name); 2463 } 2464 2465 /* Return the name for membar value VALUE or NULL if not found. */ 2466 2467 const char * 2468 sparc_decode_membar (int value) 2469 { 2470 return lookup_value (membar_table, value); 2471 } 2472 2473 /* Handle prefetch args. */ 2474 2475 static arg prefetch_table[] = 2476 { 2477 { 0, "#n_reads" }, 2478 { 1, "#one_read" }, 2479 { 2, "#n_writes" }, 2480 { 3, "#one_write" }, 2481 { 4, "#page" }, 2482 { 16, "#invalidate" }, 2483 { 17, "#unified", }, 2484 { 20, "#n_reads_strong", }, 2485 { 21, "#one_read_strong", }, 2486 { 22, "#n_writes_strong", }, 2487 { 23, "#one_write_strong", }, 2488 { 0, 0 } 2489 }; 2490 2491 /* Return the value for prefetch arg NAME, or -1 if not found. */ 2492 2493 int 2494 sparc_encode_prefetch (const char *name) 2495 { 2496 return lookup_name (prefetch_table, name); 2497 } 2498 2499 /* Return the name for prefetch value VALUE or NULL if not found. */ 2500 2501 const char * 2502 sparc_decode_prefetch (int value) 2503 { 2504 return lookup_value (prefetch_table, value); 2505 } 2506 2507 /* Handle sparclet coprocessor registers. */ 2508 2509 static arg sparclet_cpreg_table[] = 2510 { 2511 { 0, "%ccsr" }, 2512 { 1, "%ccfr" }, 2513 { 2, "%cccrcr" }, 2514 { 3, "%ccpr" }, 2515 { 4, "%ccsr2" }, 2516 { 5, "%cccrr" }, 2517 { 6, "%ccrstr" }, 2518 { 0, 0 } 2519 }; 2520 2521 /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ 2522 2523 int 2524 sparc_encode_sparclet_cpreg (const char *name) 2525 { 2526 return lookup_name (sparclet_cpreg_table, name); 2527 } 2528 2529 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */ 2530 2531 const char * 2532 sparc_decode_sparclet_cpreg (int value) 2533 { 2534 return lookup_value (sparclet_cpreg_table, value); 2535 } 2536