1 /* Print SPARC instructions. 2 Copyright (C) 1989-2020 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program; if not, write to the Free Software 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 #include "sysdep.h" 22 #include <stdio.h> 23 #include "opcode/sparc.h" 24 #include "dis-asm.h" 25 #include "libiberty.h" 26 #include "opintl.h" 27 28 /* Bitmask of v9 architectures. */ 29 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ 30 | (1 << SPARC_OPCODE_ARCH_V9A) \ 31 | (1 << SPARC_OPCODE_ARCH_V9B) \ 32 | (1 << SPARC_OPCODE_ARCH_V9C) \ 33 | (1 << SPARC_OPCODE_ARCH_V9D) \ 34 | (1 << SPARC_OPCODE_ARCH_V9E) \ 35 | (1 << SPARC_OPCODE_ARCH_V9V) \ 36 | (1 << SPARC_OPCODE_ARCH_V9M) \ 37 | (1 << SPARC_OPCODE_ARCH_M8)) 38 /* 1 if INSN is for v9 only. */ 39 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) 40 /* 1 if INSN is for v9. */ 41 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) 42 43 /* The sorted opcode table. */ 44 static const sparc_opcode **sorted_opcodes; 45 46 /* For faster lookup, after insns are sorted they are hashed. */ 47 /* ??? I think there is room for even more improvement. */ 48 49 #define HASH_SIZE 256 50 /* It is important that we only look at insn code bits as that is how the 51 opcode table is hashed. OPCODE_BITS is a table of valid bits for each 52 of the main types (0,1,2,3). */ 53 static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; 54 #define HASH_INSN(INSN) \ 55 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) 56 typedef struct sparc_opcode_hash 57 { 58 struct sparc_opcode_hash *next; 59 const sparc_opcode *opcode; 60 } sparc_opcode_hash; 61 62 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; 63 64 /* Sign-extend a value which is N bits long. */ 65 #define SEX(value, bits) \ 66 ((int) (((value & ((1u << (bits - 1) << 1) - 1)) \ 67 ^ (1u << (bits - 1))) - (1u << (bits - 1)))) 68 69 static char *reg_names[] = 70 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 71 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", 72 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 73 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", 74 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 75 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 76 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 77 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 78 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", 79 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", 80 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", 81 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", 82 /* psr, wim, tbr, fpsr, cpsr are v8 only. */ 83 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" 84 }; 85 86 #define freg_names (®_names[4 * 8]) 87 88 /* These are ordered according to there register number in 89 rdpr and wrpr insns. */ 90 static char *v9_priv_reg_names[] = 91 { 92 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", 93 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", 94 "wstate", "fq", "gl" 95 /* "ver" and "pmcdper" - special cased */ 96 }; 97 98 /* These are ordered according to there register number in 99 rdhpr and wrhpr insns. */ 100 static char *v9_hpriv_reg_names[] = 101 { 102 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver", 103 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", 104 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20", 105 "resv21", "resv22", "hmcdper", "hmcddfr", "resv25", "resv26", "hva_mask_nz", 106 "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr" 107 }; 108 109 /* These are ordered according to there register number in 110 rd and wr insns (-16). */ 111 static char *v9a_asr_reg_names[] = 112 { 113 "pcr", "pic", "dcr", "gsr", "softint_set", "softint_clear", 114 "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr", 115 "pause", "mwait" 116 }; 117 118 /* Macros used to extract instruction fields. Not all fields have 119 macros defined here, only those which are actually used. */ 120 121 #define X_RD(i) (((i) >> 25) & 0x1f) 122 #define X_RS1(i) (((i) >> 14) & 0x1f) 123 #define X_LDST_I(i) (((i) >> 13) & 1) 124 #define X_ASI(i) (((i) >> 5) & 0xff) 125 #define X_RS2(i) (((i) >> 0) & 0x1f) 126 #define X_RS3(i) (((i) >> 9) & 0x1f) 127 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) 128 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) 129 #define X_DISP22(i) (((i) >> 0) & 0x3fffff) 130 #define X_IMM22(i) X_DISP22 (i) 131 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) 132 #define X_IMM2(i) (((i & 0x10) >> 3) | (i & 0x1)) 133 134 /* These are for v9. */ 135 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) 136 #define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff)) 137 #define X_DISP19(i) (((i) >> 0) & 0x7ffff) 138 #define X_MEMBAR(i) ((i) & 0x7f) 139 140 /* Here is the union which was used to extract instruction fields 141 before the shift and mask macros were written. 142 143 union sparc_insn 144 { 145 unsigned long int code; 146 struct 147 { 148 unsigned int anop:2; 149 #define op ldst.anop 150 unsigned int anrd:5; 151 #define rd ldst.anrd 152 unsigned int op3:6; 153 unsigned int anrs1:5; 154 #define rs1 ldst.anrs1 155 unsigned int i:1; 156 unsigned int anasi:8; 157 #define asi ldst.anasi 158 unsigned int anrs2:5; 159 #define rs2 ldst.anrs2 160 #define shcnt rs2 161 } ldst; 162 struct 163 { 164 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; 165 unsigned int IMM13:13; 166 #define imm13 IMM13.IMM13 167 } IMM13; 168 struct 169 { 170 unsigned int anop:2; 171 unsigned int a:1; 172 unsigned int cond:4; 173 unsigned int op2:3; 174 unsigned int DISP22:22; 175 #define disp22 branch.DISP22 176 #define imm22 disp22 177 } branch; 178 struct 179 { 180 unsigned int anop:2; 181 unsigned int a:1; 182 unsigned int z:1; 183 unsigned int rcond:3; 184 unsigned int op2:3; 185 unsigned int DISP16HI:2; 186 unsigned int p:1; 187 unsigned int _rs1:5; 188 unsigned int DISP16LO:14; 189 } branch16; 190 struct 191 { 192 unsigned int anop:2; 193 unsigned int adisp30:30; 194 #define disp30 call.adisp30 195 } call; 196 }; */ 197 198 /* Nonzero if INSN is the opcode for a delayed branch. */ 199 200 static int 201 is_delayed_branch (unsigned long insn) 202 { 203 sparc_opcode_hash *op; 204 205 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 206 { 207 const sparc_opcode *opcode = op->opcode; 208 209 if ((opcode->match & insn) == opcode->match 210 && (opcode->lose & insn) == 0) 211 return opcode->flags & F_DELAYED; 212 } 213 return 0; 214 } 215 216 /* extern void qsort (); */ 217 218 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value 219 to compare_opcodes. */ 220 static unsigned int current_arch_mask; 221 222 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ 223 224 static int 225 compute_arch_mask (unsigned long mach) 226 { 227 switch (mach) 228 { 229 case 0 : 230 case bfd_mach_sparc : 231 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) 232 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)); 233 case bfd_mach_sparc_sparclet : 234 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); 235 case bfd_mach_sparc_sparclite : 236 case bfd_mach_sparc_sparclite_le : 237 /* sparclites insns are recognized by default (because that's how 238 they've always been treated, for better or worse). Kludge this by 239 indicating generic v8 is also selected. */ 240 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) 241 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); 242 case bfd_mach_sparc_v8plus : 243 case bfd_mach_sparc_v9 : 244 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 245 case bfd_mach_sparc_v8plusa : 246 case bfd_mach_sparc_v9a : 247 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); 248 case bfd_mach_sparc_v8plusb : 249 case bfd_mach_sparc_v9b : 250 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); 251 case bfd_mach_sparc_v8plusc : 252 case bfd_mach_sparc_v9c : 253 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C); 254 case bfd_mach_sparc_v8plusd : 255 case bfd_mach_sparc_v9d : 256 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D); 257 case bfd_mach_sparc_v8pluse : 258 case bfd_mach_sparc_v9e : 259 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E); 260 case bfd_mach_sparc_v8plusv : 261 case bfd_mach_sparc_v9v : 262 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V); 263 case bfd_mach_sparc_v8plusm : 264 case bfd_mach_sparc_v9m : 265 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M); 266 case bfd_mach_sparc_v8plusm8 : 267 case bfd_mach_sparc_v9m8 : 268 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8); 269 } 270 abort (); 271 } 272 273 /* Compare opcodes A and B. */ 274 275 static int 276 compare_opcodes (const void * a, const void * b) 277 { 278 sparc_opcode *op0 = * (sparc_opcode **) a; 279 sparc_opcode *op1 = * (sparc_opcode **) b; 280 unsigned long int match0 = op0->match, match1 = op1->match; 281 unsigned long int lose0 = op0->lose, lose1 = op1->lose; 282 register unsigned int i; 283 284 /* If one (and only one) insn isn't supported by the current architecture, 285 prefer the one that is. If neither are supported, but they're both for 286 the same architecture, continue processing. Otherwise (both unsupported 287 and for different architectures), prefer lower numbered arch's (fudged 288 by comparing the bitmasks). */ 289 if (op0->architecture & current_arch_mask) 290 { 291 if (! (op1->architecture & current_arch_mask)) 292 return -1; 293 } 294 else 295 { 296 if (op1->architecture & current_arch_mask) 297 return 1; 298 else if (op0->architecture != op1->architecture) 299 return op0->architecture - op1->architecture; 300 } 301 302 /* If a bit is set in both match and lose, there is something 303 wrong with the opcode table. */ 304 if (match0 & lose0) 305 { 306 opcodes_error_handler 307 /* xgettext:c-format */ 308 (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), 309 op0->name, match0, lose0); 310 op0->lose &= ~op0->match; 311 lose0 = op0->lose; 312 } 313 314 if (match1 & lose1) 315 { 316 opcodes_error_handler 317 /* xgettext:c-format */ 318 (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), 319 op1->name, match1, lose1); 320 op1->lose &= ~op1->match; 321 lose1 = op1->lose; 322 } 323 324 /* Because the bits that are variable in one opcode are constant in 325 another, it is important to order the opcodes in the right order. */ 326 for (i = 0; i < 32; ++i) 327 { 328 unsigned long int x = 1ul << i; 329 int x0 = (match0 & x) != 0; 330 int x1 = (match1 & x) != 0; 331 332 if (x0 != x1) 333 return x1 - x0; 334 } 335 336 for (i = 0; i < 32; ++i) 337 { 338 unsigned long int x = 1ul << i; 339 int x0 = (lose0 & x) != 0; 340 int x1 = (lose1 & x) != 0; 341 342 if (x0 != x1) 343 return x1 - x0; 344 } 345 346 /* They are functionally equal. So as long as the opcode table is 347 valid, we can put whichever one first we want, on aesthetic grounds. */ 348 349 /* Our first aesthetic ground is that aliases defer to real insns. */ 350 { 351 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); 352 353 if (alias_diff != 0) 354 /* Put the one that isn't an alias first. */ 355 return alias_diff; 356 } 357 358 /* Except for aliases, two "identical" instructions had 359 better have the same opcode. This is a sanity check on the table. */ 360 i = strcmp (op0->name, op1->name); 361 if (i) 362 { 363 if (op0->flags & F_ALIAS) 364 { 365 if (op0->flags & F_PREFERRED) 366 return -1; 367 if (op1->flags & F_PREFERRED) 368 return 1; 369 370 /* If they're both aliases, and neither is marked as preferred, 371 be arbitrary. */ 372 return i; 373 } 374 else 375 opcodes_error_handler 376 /* xgettext:c-format */ 377 (_("internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), 378 op0->name, op1->name); 379 } 380 381 /* Fewer arguments are preferred. */ 382 { 383 int length_diff = strlen (op0->args) - strlen (op1->args); 384 385 if (length_diff != 0) 386 /* Put the one with fewer arguments first. */ 387 return length_diff; 388 } 389 390 /* Put 1+i before i+1. */ 391 { 392 char *p0 = (char *) strchr (op0->args, '+'); 393 char *p1 = (char *) strchr (op1->args, '+'); 394 395 if (p0 && p1) 396 { 397 /* There is a plus in both operands. Note that a plus 398 sign cannot be the first character in args, 399 so the following [-1]'s are valid. */ 400 if (p0[-1] == 'i' && p1[1] == 'i') 401 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ 402 return 1; 403 if (p0[1] == 'i' && p1[-1] == 'i') 404 /* op0 is 1+i and op1 is i+1, so op0 goes first. */ 405 return -1; 406 } 407 } 408 409 /* Put 1,i before i,1. */ 410 { 411 int i0 = strncmp (op0->args, "i,1", 3) == 0; 412 int i1 = strncmp (op1->args, "i,1", 3) == 0; 413 414 if (i0 ^ i1) 415 return i0 - i1; 416 } 417 418 /* They are, as far as we can tell, identical. 419 Since qsort may have rearranged the table partially, there is 420 no way to tell which one was first in the opcode table as 421 written, so just say there are equal. */ 422 /* ??? This is no longer true now that we sort a vector of pointers, 423 not the table itself. */ 424 return 0; 425 } 426 427 /* Build a hash table from the opcode table. 428 OPCODE_TABLE is a sorted list of pointers into the opcode table. */ 429 430 static void 431 build_hash_table (const sparc_opcode **opcode_table, 432 sparc_opcode_hash **hash_table, 433 int num_opcodes) 434 { 435 int i; 436 int hash_count[HASH_SIZE]; 437 static sparc_opcode_hash *hash_buf = NULL; 438 439 /* Start at the end of the table and work backwards so that each 440 chain is sorted. */ 441 442 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); 443 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); 444 if (hash_buf != NULL) 445 free (hash_buf); 446 hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes); 447 for (i = num_opcodes - 1; i >= 0; --i) 448 { 449 int hash = HASH_INSN (opcode_table[i]->match); 450 sparc_opcode_hash *h = &hash_buf[i]; 451 452 h->next = hash_table[hash]; 453 h->opcode = opcode_table[i]; 454 hash_table[hash] = h; 455 ++hash_count[hash]; 456 } 457 458 #if 0 /* for debugging */ 459 { 460 int min_count = num_opcodes, max_count = 0; 461 int total; 462 463 for (i = 0; i < HASH_SIZE; ++i) 464 { 465 if (hash_count[i] < min_count) 466 min_count = hash_count[i]; 467 if (hash_count[i] > max_count) 468 max_count = hash_count[i]; 469 total += hash_count[i]; 470 } 471 472 printf ("Opcode hash table stats: min %d, max %d, ave %f\n", 473 min_count, max_count, (double) total / HASH_SIZE); 474 } 475 #endif 476 } 477 478 /* Print one instruction from MEMADDR on INFO->STREAM. 479 480 We suffix the instruction with a comment that gives the absolute 481 address involved, as well as its symbolic form, if the instruction 482 is preceded by a findable `sethi' and it either adds an immediate 483 displacement to that register, or it is an `add' or `or' instruction 484 on that register. */ 485 486 int 487 print_insn_sparc (bfd_vma memaddr, disassemble_info *info) 488 { 489 FILE *stream = info->stream; 490 bfd_byte buffer[4]; 491 unsigned long insn; 492 sparc_opcode_hash *op; 493 /* Nonzero of opcode table has been initialized. */ 494 static int opcodes_initialized = 0; 495 /* bfd mach number of last call. */ 496 static unsigned long current_mach = 0; 497 bfd_vma (*getword) (const void *); 498 499 if (!opcodes_initialized 500 || info->mach != current_mach) 501 { 502 int i; 503 504 current_arch_mask = compute_arch_mask (info->mach); 505 506 if (!opcodes_initialized) 507 sorted_opcodes = 508 xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *)); 509 /* Reset the sorted table so we can resort it. */ 510 for (i = 0; i < sparc_num_opcodes; ++i) 511 sorted_opcodes[i] = &sparc_opcodes[i]; 512 qsort ((char *) sorted_opcodes, sparc_num_opcodes, 513 sizeof (sorted_opcodes[0]), compare_opcodes); 514 515 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); 516 current_mach = info->mach; 517 opcodes_initialized = 1; 518 } 519 520 { 521 int status = 522 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); 523 524 if (status != 0) 525 { 526 (*info->memory_error_func) (status, memaddr, info); 527 return -1; 528 } 529 } 530 531 /* On SPARClite variants such as DANlite (sparc86x), instructions 532 are always big-endian even when the machine is in little-endian mode. */ 533 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) 534 getword = bfd_getb32; 535 else 536 getword = bfd_getl32; 537 538 insn = getword (buffer); 539 540 info->insn_info_valid = 1; /* We do return this info. */ 541 info->insn_type = dis_nonbranch; /* Assume non branch insn. */ 542 info->branch_delay_insns = 0; /* Assume no delay. */ 543 info->target = 0; /* Assume no target known. */ 544 545 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) 546 { 547 const sparc_opcode *opcode = op->opcode; 548 549 /* If the insn isn't supported by the current architecture, skip it. */ 550 if (! (opcode->architecture & current_arch_mask)) 551 continue; 552 553 if ((opcode->match & insn) == opcode->match 554 && (opcode->lose & insn) == 0) 555 { 556 /* Nonzero means that we have found an instruction which has 557 the effect of adding or or'ing the imm13 field to rs1. */ 558 int imm_added_to_rs1 = 0; 559 int imm_ored_to_rs1 = 0; 560 561 /* Nonzero means that we have found a plus sign in the args 562 field of the opcode table. */ 563 int found_plus = 0; 564 565 /* Nonzero means we have an annulled branch. */ 566 int is_annulled = 0; 567 568 /* Do we have an `add' or `or' instruction combining an 569 immediate with rs1? */ 570 if (opcode->match == 0x80102000) /* or */ 571 imm_ored_to_rs1 = 1; 572 if (opcode->match == 0x80002000) /* add */ 573 imm_added_to_rs1 = 1; 574 575 if (X_RS1 (insn) != X_RD (insn) 576 && strchr (opcode->args, 'r') != 0) 577 /* Can't do simple format if source and dest are different. */ 578 continue; 579 if (X_RS2 (insn) != X_RD (insn) 580 && strchr (opcode->args, 'O') != 0) 581 /* Can't do simple format if source and dest are different. */ 582 continue; 583 584 (*info->fprintf_func) (stream, "%s", opcode->name); 585 586 { 587 const char *s; 588 589 if (opcode->args[0] != ',') 590 (*info->fprintf_func) (stream, " "); 591 592 for (s = opcode->args; *s != '\0'; ++s) 593 { 594 while (*s == ',') 595 { 596 (*info->fprintf_func) (stream, ","); 597 ++s; 598 switch (*s) 599 { 600 case 'a': 601 (*info->fprintf_func) (stream, "a"); 602 is_annulled = 1; 603 ++s; 604 continue; 605 case 'N': 606 (*info->fprintf_func) (stream, "pn"); 607 ++s; 608 continue; 609 610 case 'T': 611 (*info->fprintf_func) (stream, "pt"); 612 ++s; 613 continue; 614 615 default: 616 break; 617 } 618 } 619 620 (*info->fprintf_func) (stream, " "); 621 622 switch (*s) 623 { 624 case '+': 625 found_plus = 1; 626 /* Fall through. */ 627 628 default: 629 (*info->fprintf_func) (stream, "%c", *s); 630 break; 631 632 case '#': 633 (*info->fprintf_func) (stream, "0"); 634 break; 635 636 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) 637 case '1': 638 case 'r': 639 reg (X_RS1 (insn)); 640 break; 641 642 case '2': 643 case 'O': 644 reg (X_RS2 (insn)); 645 break; 646 647 case 'd': 648 reg (X_RD (insn)); 649 break; 650 #undef reg 651 652 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) 653 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) 654 case 'e': 655 freg (X_RS1 (insn)); 656 break; 657 case 'v': /* Double/even. */ 658 case 'V': /* Quad/multiple of 4. */ 659 case ';': /* Double/even multiple of 8 doubles. */ 660 fregx (X_RS1 (insn)); 661 break; 662 663 case 'f': 664 freg (X_RS2 (insn)); 665 break; 666 case 'B': /* Double/even. */ 667 case 'R': /* Quad/multiple of 4. */ 668 case ':': /* Double/even multiple of 8 doubles. */ 669 fregx (X_RS2 (insn)); 670 break; 671 672 case '4': 673 freg (X_RS3 (insn)); 674 break; 675 case '5': /* Double/even. */ 676 fregx (X_RS3 (insn)); 677 break; 678 679 case 'g': 680 freg (X_RD (insn)); 681 break; 682 case 'H': /* Double/even. */ 683 case 'J': /* Quad/multiple of 4. */ 684 case '}': /* Double/even. */ 685 fregx (X_RD (insn)); 686 break; 687 688 case '^': /* Double/even multiple of 8 doubles. */ 689 fregx (X_RD (insn) & ~0x6); 690 break; 691 692 case '\'': /* Double/even in FPCMPSHL. */ 693 fregx (X_RS2 (insn | 0x11)); 694 break; 695 696 #undef freg 697 #undef fregx 698 699 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) 700 case 'b': 701 creg (X_RS1 (insn)); 702 break; 703 704 case 'c': 705 creg (X_RS2 (insn)); 706 break; 707 708 case 'D': 709 creg (X_RD (insn)); 710 break; 711 #undef creg 712 713 case 'h': 714 (*info->fprintf_func) (stream, "%%hi(%#x)", 715 (unsigned) X_IMM22 (insn) << 10); 716 break; 717 718 case 'i': /* 13 bit immediate. */ 719 case 'I': /* 11 bit immediate. */ 720 case 'j': /* 10 bit immediate. */ 721 { 722 int imm; 723 724 if (*s == 'i') 725 imm = X_SIMM (insn, 13); 726 else if (*s == 'I') 727 imm = X_SIMM (insn, 11); 728 else 729 imm = X_SIMM (insn, 10); 730 731 /* Check to see whether we have a 1+i, and take 732 note of that fact. 733 734 Note: because of the way we sort the table, 735 we will be matching 1+i rather than i+1, 736 so it is OK to assume that i is after +, 737 not before it. */ 738 if (found_plus) 739 imm_added_to_rs1 = 1; 740 741 if (imm <= 9) 742 (*info->fprintf_func) (stream, "%d", imm); 743 else 744 (*info->fprintf_func) (stream, "%#x", imm); 745 } 746 break; 747 748 case ')': /* 5 bit unsigned immediate from RS3. */ 749 (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn)); 750 break; 751 752 case 'X': /* 5 bit unsigned immediate. */ 753 case 'Y': /* 6 bit unsigned immediate. */ 754 { 755 int imm = X_IMM (insn, *s == 'X' ? 5 : 6); 756 757 if (imm <= 9) 758 (info->fprintf_func) (stream, "%d", imm); 759 else 760 (info->fprintf_func) (stream, "%#x", (unsigned) imm); 761 } 762 break; 763 764 case '3': 765 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); 766 break; 767 768 case 'K': 769 { 770 int mask = X_MEMBAR (insn); 771 int bit = 0x40, printed_one = 0; 772 const char *name; 773 774 if (mask == 0) 775 (info->fprintf_func) (stream, "0"); 776 else 777 while (bit) 778 { 779 if (mask & bit) 780 { 781 if (printed_one) 782 (info->fprintf_func) (stream, "|"); 783 name = sparc_decode_membar (bit); 784 (info->fprintf_func) (stream, "%s", name); 785 printed_one = 1; 786 } 787 bit >>= 1; 788 } 789 break; 790 } 791 792 case '=': 793 info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4; 794 (*info->print_address_func) (info->target, info); 795 break; 796 797 case 'k': 798 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; 799 (*info->print_address_func) (info->target, info); 800 break; 801 802 case 'G': 803 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; 804 (*info->print_address_func) (info->target, info); 805 break; 806 807 case '6': 808 case '7': 809 case '8': 810 case '9': 811 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); 812 break; 813 814 case 'z': 815 (*info->fprintf_func) (stream, "%%icc"); 816 break; 817 818 case 'Z': 819 (*info->fprintf_func) (stream, "%%xcc"); 820 break; 821 822 case 'E': 823 (*info->fprintf_func) (stream, "%%ccr"); 824 break; 825 826 case 's': 827 (*info->fprintf_func) (stream, "%%fprs"); 828 break; 829 830 case '{': 831 (*info->fprintf_func) (stream, "%%mcdper"); 832 break; 833 834 case '&': 835 (*info->fprintf_func) (stream, "%%entropy"); 836 break; 837 838 case 'o': 839 (*info->fprintf_func) (stream, "%%asi"); 840 break; 841 842 case 'W': 843 (*info->fprintf_func) (stream, "%%tick"); 844 break; 845 846 case 'P': 847 (*info->fprintf_func) (stream, "%%pc"); 848 break; 849 850 case '?': 851 if (X_RS1 (insn) == 31) 852 (*info->fprintf_func) (stream, "%%ver"); 853 else if (X_RS1 (insn) == 23) 854 (*info->fprintf_func) (stream, "%%pmcdper"); 855 else if ((unsigned) X_RS1 (insn) < 17) 856 (*info->fprintf_func) (stream, "%%%s", 857 v9_priv_reg_names[X_RS1 (insn)]); 858 else 859 (*info->fprintf_func) (stream, "%%reserved"); 860 break; 861 862 case '!': 863 if (X_RD (insn) == 31) 864 (*info->fprintf_func) (stream, "%%ver"); 865 else if (X_RD (insn) == 23) 866 (*info->fprintf_func) (stream, "%%pmcdper"); 867 else if ((unsigned) X_RD (insn) < 17) 868 (*info->fprintf_func) (stream, "%%%s", 869 v9_priv_reg_names[X_RD (insn)]); 870 else 871 (*info->fprintf_func) (stream, "%%reserved"); 872 break; 873 874 case '$': 875 if ((unsigned) X_RS1 (insn) < 32) 876 (*info->fprintf_func) (stream, "%%%s", 877 v9_hpriv_reg_names[X_RS1 (insn)]); 878 else 879 (*info->fprintf_func) (stream, "%%reserved"); 880 break; 881 882 case '%': 883 if ((unsigned) X_RD (insn) < 32) 884 (*info->fprintf_func) (stream, "%%%s", 885 v9_hpriv_reg_names[X_RD (insn)]); 886 else 887 (*info->fprintf_func) (stream, "%%reserved"); 888 break; 889 890 case '/': 891 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28) 892 (*info->fprintf_func) (stream, "%%reserved"); 893 else 894 (*info->fprintf_func) (stream, "%%%s", 895 v9a_asr_reg_names[X_RS1 (insn)-16]); 896 break; 897 898 case '_': 899 if (X_RD (insn) < 16 || X_RD (insn) > 28) 900 (*info->fprintf_func) (stream, "%%reserved"); 901 else 902 (*info->fprintf_func) (stream, "%%%s", 903 v9a_asr_reg_names[X_RD (insn)-16]); 904 break; 905 906 case '*': 907 { 908 const char *name = sparc_decode_prefetch (X_RD (insn)); 909 910 if (name) 911 (*info->fprintf_func) (stream, "%s", name); 912 else 913 (*info->fprintf_func) (stream, "%ld", X_RD (insn)); 914 break; 915 } 916 917 case 'M': 918 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); 919 break; 920 921 case 'm': 922 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); 923 break; 924 925 case 'L': 926 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; 927 (*info->print_address_func) (info->target, info); 928 break; 929 930 case 'n': 931 (*info->fprintf_func) 932 (stream, "%#x", SEX (X_DISP22 (insn), 22)); 933 break; 934 935 case 'l': 936 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; 937 (*info->print_address_func) (info->target, info); 938 break; 939 940 case 'A': 941 { 942 const char *name = sparc_decode_asi (X_ASI (insn)); 943 944 if (name) 945 (*info->fprintf_func) (stream, "%s", name); 946 else 947 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); 948 break; 949 } 950 951 case 'C': 952 (*info->fprintf_func) (stream, "%%csr"); 953 break; 954 955 case 'F': 956 (*info->fprintf_func) (stream, "%%fsr"); 957 break; 958 959 case '(': 960 (*info->fprintf_func) (stream, "%%efsr"); 961 break; 962 963 case 'p': 964 (*info->fprintf_func) (stream, "%%psr"); 965 break; 966 967 case 'q': 968 (*info->fprintf_func) (stream, "%%fq"); 969 break; 970 971 case 'Q': 972 (*info->fprintf_func) (stream, "%%cq"); 973 break; 974 975 case 't': 976 (*info->fprintf_func) (stream, "%%tbr"); 977 break; 978 979 case 'w': 980 (*info->fprintf_func) (stream, "%%wim"); 981 break; 982 983 case 'x': 984 (*info->fprintf_func) (stream, "%ld", 985 ((X_LDST_I (insn) << 8) 986 + X_ASI (insn))); 987 break; 988 989 case '|': /* 2-bit immediate */ 990 (*info->fprintf_func) (stream, "%ld", X_IMM2 (insn)); 991 break; 992 993 case 'y': 994 (*info->fprintf_func) (stream, "%%y"); 995 break; 996 997 case 'u': 998 case 'U': 999 { 1000 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); 1001 const char *name = sparc_decode_sparclet_cpreg (val); 1002 1003 if (name) 1004 (*info->fprintf_func) (stream, "%s", name); 1005 else 1006 (*info->fprintf_func) (stream, "%%cpreg(%d)", val); 1007 break; 1008 } 1009 } 1010 } 1011 } 1012 1013 /* If we are adding or or'ing something to rs1, then 1014 check to see whether the previous instruction was 1015 a sethi to the same register as in the sethi. 1016 If so, attempt to print the result of the add or 1017 or (in this context add and or do the same thing) 1018 and its symbolic value. */ 1019 if (imm_ored_to_rs1 || imm_added_to_rs1) 1020 { 1021 unsigned long prev_insn; 1022 int errcode; 1023 1024 if (memaddr >= 4) 1025 errcode = 1026 (*info->read_memory_func) 1027 (memaddr - 4, buffer, sizeof (buffer), info); 1028 else 1029 errcode = 1; 1030 1031 prev_insn = getword (buffer); 1032 1033 if (errcode == 0) 1034 { 1035 /* If it is a delayed branch, we need to look at the 1036 instruction before the delayed branch. This handles 1037 sequences such as: 1038 1039 sethi %o1, %hi(_foo), %o1 1040 call _printf 1041 or %o1, %lo(_foo), %o1 */ 1042 1043 if (is_delayed_branch (prev_insn)) 1044 { 1045 if (memaddr >= 8) 1046 errcode = (*info->read_memory_func) 1047 (memaddr - 8, buffer, sizeof (buffer), info); 1048 else 1049 errcode = 1; 1050 1051 prev_insn = getword (buffer); 1052 } 1053 } 1054 1055 /* If there was a problem reading memory, then assume 1056 the previous instruction was not sethi. */ 1057 if (errcode == 0) 1058 { 1059 /* Is it sethi to the same register? */ 1060 if ((prev_insn & 0xc1c00000) == 0x01000000 1061 && X_RD (prev_insn) == X_RS1 (insn)) 1062 { 1063 (*info->fprintf_func) (stream, "\t! "); 1064 info->target = (unsigned) X_IMM22 (prev_insn) << 10; 1065 if (imm_added_to_rs1) 1066 info->target += X_SIMM (insn, 13); 1067 else 1068 info->target |= X_SIMM (insn, 13); 1069 (*info->print_address_func) (info->target, info); 1070 info->insn_type = dis_dref; 1071 info->data_size = 4; /* FIXME!!! */ 1072 } 1073 } 1074 } 1075 1076 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) 1077 { 1078 /* FIXME -- check is_annulled flag. */ 1079 (void) is_annulled; 1080 if (opcode->flags & F_UNBR) 1081 info->insn_type = dis_branch; 1082 if (opcode->flags & F_CONDBR) 1083 info->insn_type = dis_condbranch; 1084 if (opcode->flags & F_JSR) 1085 info->insn_type = dis_jsr; 1086 if (opcode->flags & F_DELAYED) 1087 info->branch_delay_insns = 1; 1088 } 1089 1090 return sizeof (buffer); 1091 } 1092 } 1093 1094 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ 1095 (*info->fprintf_func) (stream, _("unknown")); 1096 return sizeof (buffer); 1097 } 1098