1 /* RISC-V disassembler 2 Copyright (C) 2011-2020 Free Software Foundation, Inc. 3 4 Contributed by Andrew Waterman (andrew@sifive.com). 5 Based on MIPS target. 6 7 This file is part of the GNU opcodes library. 8 9 This library is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; see the file COPYING3. If not, 21 see <http://www.gnu.org/licenses/>. */ 22 23 #include "sysdep.h" 24 #include "disassemble.h" 25 #include "libiberty.h" 26 #include "opcode/riscv.h" 27 #include "opintl.h" 28 #include "elf-bfd.h" 29 #include "elf/riscv.h" 30 31 #include "bfd_stdint.h" 32 #include <ctype.h> 33 34 struct riscv_private_data 35 { 36 bfd_vma gp; 37 bfd_vma print_addr; 38 bfd_vma hi_addr[OP_MASK_RD + 1]; 39 }; 40 41 static const char * const *riscv_gpr_names; 42 static const char * const *riscv_fpr_names; 43 44 /* Other options. */ 45 static int no_aliases; /* If set disassemble as most general inst. */ 46 47 static void 48 set_default_riscv_dis_options (void) 49 { 50 riscv_gpr_names = riscv_gpr_names_abi; 51 riscv_fpr_names = riscv_fpr_names_abi; 52 no_aliases = 0; 53 } 54 55 static void 56 parse_riscv_dis_option (const char *option) 57 { 58 if (strcmp (option, "no-aliases") == 0) 59 no_aliases = 1; 60 else if (strcmp (option, "numeric") == 0) 61 { 62 riscv_gpr_names = riscv_gpr_names_numeric; 63 riscv_fpr_names = riscv_fpr_names_numeric; 64 } 65 else 66 { 67 /* xgettext:c-format */ 68 opcodes_error_handler (_("unrecognized disassembler option: %s"), option); 69 } 70 } 71 72 static void 73 parse_riscv_dis_options (const char *opts_in) 74 { 75 char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; 76 77 set_default_riscv_dis_options (); 78 79 for ( ; opt_end != NULL; opt = opt_end + 1) 80 { 81 if ((opt_end = strchr (opt, ',')) != NULL) 82 *opt_end = 0; 83 parse_riscv_dis_option (opt); 84 } 85 86 free (opts); 87 } 88 89 /* Print one argument from an array. */ 90 91 static void 92 arg_print (struct disassemble_info *info, unsigned long val, 93 const char* const* array, size_t size) 94 { 95 const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; 96 (*info->fprintf_func) (info->stream, "%s", s); 97 } 98 99 static void 100 maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) 101 { 102 if (pd->hi_addr[base_reg] != (bfd_vma)-1) 103 { 104 pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset; 105 pd->hi_addr[base_reg] = -1; 106 } 107 else if (base_reg == X_GP && pd->gp != (bfd_vma)-1) 108 pd->print_addr = pd->gp + offset; 109 else if (base_reg == X_TP || base_reg == 0) 110 pd->print_addr = offset; 111 } 112 113 /* Print insn arguments for 32/64-bit code. */ 114 115 static void 116 print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) 117 { 118 struct riscv_private_data *pd = info->private_data; 119 int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; 120 int rd = (l >> OP_SH_RD) & OP_MASK_RD; 121 fprintf_ftype print = info->fprintf_func; 122 123 if (*d != '\0') 124 print (info->stream, "\t"); 125 126 for (; *d != '\0'; d++) 127 { 128 switch (*d) 129 { 130 case 'C': /* RVC */ 131 switch (*++d) 132 { 133 case 's': /* RS1 x8-x15 */ 134 case 'w': /* RS1 x8-x15 */ 135 print (info->stream, "%s", 136 riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); 137 break; 138 case 't': /* RS2 x8-x15 */ 139 case 'x': /* RS2 x8-x15 */ 140 print (info->stream, "%s", 141 riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); 142 break; 143 case 'U': /* RS1, constrained to equal RD */ 144 print (info->stream, "%s", riscv_gpr_names[rd]); 145 break; 146 case 'c': /* RS1, constrained to equal sp */ 147 print (info->stream, "%s", riscv_gpr_names[X_SP]); 148 break; 149 case 'V': /* RS2 */ 150 print (info->stream, "%s", 151 riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]); 152 break; 153 case 'i': 154 print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); 155 break; 156 case 'o': 157 case 'j': 158 print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); 159 break; 160 case 'k': 161 print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l)); 162 break; 163 case 'l': 164 print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l)); 165 break; 166 case 'm': 167 print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l)); 168 break; 169 case 'n': 170 print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l)); 171 break; 172 case 'K': 173 print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l)); 174 break; 175 case 'L': 176 print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l)); 177 break; 178 case 'M': 179 print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l)); 180 break; 181 case 'N': 182 print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l)); 183 break; 184 case 'p': 185 info->target = EXTRACT_RVC_B_IMM (l) + pc; 186 (*info->print_address_func) (info->target, info); 187 break; 188 case 'a': 189 info->target = EXTRACT_RVC_J_IMM (l) + pc; 190 (*info->print_address_func) (info->target, info); 191 break; 192 case 'u': 193 print (info->stream, "0x%x", 194 (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1))); 195 break; 196 case '>': 197 print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f); 198 break; 199 case '<': 200 print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f); 201 break; 202 case 'T': /* floating-point RS2 */ 203 print (info->stream, "%s", 204 riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]); 205 break; 206 case 'D': /* floating-point RS2 x8-x15 */ 207 print (info->stream, "%s", 208 riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); 209 break; 210 } 211 break; 212 213 case ',': 214 case '(': 215 case ')': 216 case '[': 217 case ']': 218 print (info->stream, "%c", *d); 219 break; 220 221 case '0': 222 /* Only print constant 0 if it is the last argument */ 223 if (!d[1]) 224 print (info->stream, "0"); 225 break; 226 227 case 'b': 228 case 's': 229 if ((l & MASK_JALR) == MATCH_JALR) 230 maybe_print_address (pd, rs1, 0); 231 print (info->stream, "%s", riscv_gpr_names[rs1]); 232 break; 233 234 case 't': 235 print (info->stream, "%s", 236 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); 237 break; 238 239 case 'u': 240 print (info->stream, "0x%x", 241 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); 242 break; 243 244 case 'm': 245 arg_print (info, EXTRACT_OPERAND (RM, l), 246 riscv_rm, ARRAY_SIZE (riscv_rm)); 247 break; 248 249 case 'P': 250 arg_print (info, EXTRACT_OPERAND (PRED, l), 251 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); 252 break; 253 254 case 'Q': 255 arg_print (info, EXTRACT_OPERAND (SUCC, l), 256 riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); 257 break; 258 259 case 'o': 260 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); 261 /* Fall through. */ 262 case 'j': 263 if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) 264 || (l & MASK_JALR) == MATCH_JALR) 265 maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); 266 print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l)); 267 break; 268 269 case 'q': 270 maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); 271 print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); 272 break; 273 274 case 'a': 275 info->target = EXTRACT_UJTYPE_IMM (l) + pc; 276 (*info->print_address_func) (info->target, info); 277 break; 278 279 case 'p': 280 info->target = EXTRACT_SBTYPE_IMM (l) + pc; 281 (*info->print_address_func) (info->target, info); 282 break; 283 284 case 'd': 285 if ((l & MASK_AUIPC) == MATCH_AUIPC) 286 pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l); 287 else if ((l & MASK_LUI) == MATCH_LUI) 288 pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); 289 else if ((l & MASK_C_LUI) == MATCH_C_LUI) 290 pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l); 291 print (info->stream, "%s", riscv_gpr_names[rd]); 292 break; 293 294 case 'z': 295 print (info->stream, "%s", riscv_gpr_names[0]); 296 break; 297 298 case '>': 299 print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l)); 300 break; 301 302 case '<': 303 print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l)); 304 break; 305 306 case 'S': 307 case 'U': 308 print (info->stream, "%s", riscv_fpr_names[rs1]); 309 break; 310 311 case 'T': 312 print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]); 313 break; 314 315 case 'D': 316 print (info->stream, "%s", riscv_fpr_names[rd]); 317 break; 318 319 case 'R': 320 print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]); 321 break; 322 323 case 'E': 324 { 325 const char* csr_name = NULL; 326 unsigned int csr = EXTRACT_OPERAND (CSR, l); 327 switch (csr) 328 { 329 #define DECLARE_CSR(name, num) case num: csr_name = #name; break; 330 #include "opcode/riscv-opc.h" 331 #undef DECLARE_CSR 332 } 333 if (csr_name) 334 print (info->stream, "%s", csr_name); 335 else 336 print (info->stream, "0x%x", csr); 337 break; 338 } 339 340 case 'Z': 341 print (info->stream, "%d", rs1); 342 break; 343 344 default: 345 /* xgettext:c-format */ 346 print (info->stream, _("# internal error, undefined modifier (%c)"), 347 *d); 348 return; 349 } 350 } 351 } 352 353 /* Print the RISC-V instruction at address MEMADDR in debugged memory, 354 on using INFO. Returns length of the instruction, in bytes. 355 BIGENDIAN must be 1 if this is big-endian code, 0 if 356 this is little-endian code. */ 357 358 static int 359 riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) 360 { 361 const struct riscv_opcode *op; 362 static bfd_boolean init = 0; 363 static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; 364 struct riscv_private_data *pd; 365 int insnlen; 366 367 #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) 368 369 /* Build a hash table to shorten the search time. */ 370 if (! init) 371 { 372 for (op = riscv_opcodes; op->name; op++) 373 if (!riscv_hash[OP_HASH_IDX (op->match)]) 374 riscv_hash[OP_HASH_IDX (op->match)] = op; 375 376 init = 1; 377 } 378 379 if (info->private_data == NULL) 380 { 381 int i; 382 383 pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); 384 pd->gp = -1; 385 pd->print_addr = -1; 386 for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) 387 pd->hi_addr[i] = -1; 388 389 for (i = 0; i < info->symtab_size; i++) 390 if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0) 391 pd->gp = bfd_asymbol_value (info->symtab[i]); 392 } 393 else 394 pd = info->private_data; 395 396 insnlen = riscv_insn_length (word); 397 398 /* RISC-V instructions are always little-endian. */ 399 info->endian_code = BFD_ENDIAN_LITTLE; 400 401 info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; 402 info->bytes_per_line = 8; 403 /* We don't support constant pools, so this must be code. */ 404 info->display_endian = info->endian_code; 405 info->insn_info_valid = 1; 406 info->branch_delay_insns = 0; 407 info->data_size = 0; 408 info->insn_type = dis_nonbranch; 409 info->target = 0; 410 info->target2 = 0; 411 412 op = riscv_hash[OP_HASH_IDX (word)]; 413 if (op != NULL) 414 { 415 unsigned xlen = 0; 416 417 /* If XLEN is not known, get its value from the ELF class. */ 418 if (info->mach == bfd_mach_riscv64) 419 xlen = 64; 420 else if (info->mach == bfd_mach_riscv32) 421 xlen = 32; 422 else if (info->section != NULL) 423 { 424 Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); 425 xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; 426 } 427 428 for (; op->name; op++) 429 { 430 /* Does the opcode match? */ 431 if (! (op->match_func) (op, word)) 432 continue; 433 /* Is this a pseudo-instruction and may we print it as such? */ 434 if (no_aliases && (op->pinfo & INSN_ALIAS)) 435 continue; 436 /* Is this instruction restricted to a certain value of XLEN? */ 437 if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) 438 continue; 439 440 /* It's a match. */ 441 (*info->fprintf_func) (info->stream, "%s", op->name); 442 print_insn_args (op->args, word, memaddr, info); 443 444 /* Try to disassemble multi-instruction addressing sequences. */ 445 if (pd->print_addr != (bfd_vma)-1) 446 { 447 info->target = pd->print_addr; 448 (*info->fprintf_func) (info->stream, " # "); 449 (*info->print_address_func) (info->target, info); 450 pd->print_addr = -1; 451 } 452 453 /* Finish filling out insn_info fields. */ 454 switch (op->pinfo & INSN_TYPE) 455 { 456 case INSN_BRANCH: 457 info->insn_type = dis_branch; 458 break; 459 case INSN_CONDBRANCH: 460 info->insn_type = dis_condbranch; 461 break; 462 case INSN_JSR: 463 info->insn_type = dis_jsr; 464 break; 465 case INSN_DREF: 466 info->insn_type = dis_dref; 467 break; 468 default: 469 break; 470 } 471 472 if (op->pinfo & INSN_DATA_SIZE) 473 { 474 int size = ((op->pinfo & INSN_DATA_SIZE) 475 >> INSN_DATA_SIZE_SHIFT); 476 info->data_size = 1 << (size - 1); 477 } 478 479 return insnlen; 480 } 481 } 482 483 /* We did not find a match, so just print the instruction bits. */ 484 info->insn_type = dis_noninsn; 485 (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word); 486 return insnlen; 487 } 488 489 int 490 print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) 491 { 492 bfd_byte packet[2]; 493 insn_t insn = 0; 494 bfd_vma n; 495 int status; 496 497 if (info->disassembler_options != NULL) 498 { 499 parse_riscv_dis_options (info->disassembler_options); 500 /* Avoid repeatedly parsing the options. */ 501 info->disassembler_options = NULL; 502 } 503 else if (riscv_gpr_names == NULL) 504 set_default_riscv_dis_options (); 505 506 /* Instructions are a sequence of 2-byte packets in little-endian order. */ 507 for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2) 508 { 509 status = (*info->read_memory_func) (memaddr + n, packet, 2, info); 510 if (status != 0) 511 { 512 /* Don't fail just because we fell off the end. */ 513 if (n > 0) 514 break; 515 (*info->memory_error_func) (status, memaddr, info); 516 return status; 517 } 518 519 insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n); 520 } 521 522 return riscv_disassemble_insn (memaddr, insn, info); 523 } 524 525 /* Prevent use of the fake labels that are generated as part of the DWARF 526 and for relaxable relocations in the assembler. */ 527 528 bfd_boolean 529 riscv_symbol_is_valid (asymbol * sym, 530 struct disassemble_info * info ATTRIBUTE_UNUSED) 531 { 532 const char * name; 533 534 if (sym == NULL) 535 return FALSE; 536 537 name = bfd_asymbol_name (sym); 538 539 return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0); 540 } 541 542 void 543 print_riscv_disassembler_options (FILE *stream) 544 { 545 fprintf (stream, _("\n\ 546 The following RISC-V-specific disassembler options are supported for use\n\ 547 with the -M switch (multiple options should be separated by commas):\n")); 548 549 fprintf (stream, _("\n\ 550 numeric Print numeric register names, rather than ABI names.\n")); 551 552 fprintf (stream, _("\n\ 553 no-aliases Disassemble only into canonical instructions, rather\n\ 554 than into pseudoinstructions.\n")); 555 556 fprintf (stream, _("\n")); 557 } 558