1 /* ppc-dis.c -- Disassemble PowerPC instructions 2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include <stdio.h> 24 #include "disassemble.h" 25 #include "elf-bfd.h" 26 #include "elf/ppc.h" 27 #include "opintl.h" 28 #include "opcode/ppc.h" 29 #include "libiberty.h" 30 31 /* This file provides several disassembler functions, all of which use 32 the disassembler interface defined in dis-asm.h. Several functions 33 are provided because this file handles disassembly for the PowerPC 34 in both big and little endian mode and also for the POWER (RS/6000) 35 chip. */ 36 static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, 37 ppc_cpu_t); 38 39 struct dis_private 40 { 41 /* Stash the result of parsing disassembler_options here. */ 42 ppc_cpu_t dialect; 43 } private; 44 45 #define POWERPC_DIALECT(INFO) \ 46 (((struct dis_private *) ((INFO)->private_data))->dialect) 47 48 struct ppc_mopt { 49 /* Option string, without -m or -M prefix. */ 50 const char *opt; 51 /* CPU option flags. */ 52 ppc_cpu_t cpu; 53 /* Flags that should stay on, even when combined with another cpu 54 option. This should only be used for generic options like 55 "-many" or "-maltivec" where it is reasonable to add some 56 capability to another cpu selection. The added flags are sticky 57 so that, for example, "-many -me500" and "-me500 -many" result in 58 the same assembler or disassembler behaviour. Do not use 59 "sticky" for specific cpus, as this will prevent that cpu's flags 60 from overriding the defaults set in powerpc_init_dialect or a 61 prior -m option. */ 62 ppc_cpu_t sticky; 63 }; 64 65 struct ppc_mopt ppc_opts[] = { 66 { "403", PPC_OPCODE_PPC | PPC_OPCODE_403, 67 0 }, 68 { "405", PPC_OPCODE_PPC | PPC_OPCODE_403 | PPC_OPCODE_405, 69 0 }, 70 { "440", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 71 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 72 0 }, 73 { "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440 74 | PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI), 75 0 }, 76 { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476 77 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5), 78 0 }, 79 { "601", PPC_OPCODE_PPC | PPC_OPCODE_601, 80 0 }, 81 { "603", PPC_OPCODE_PPC, 82 0 }, 83 { "604", PPC_OPCODE_PPC, 84 0 }, 85 { "620", PPC_OPCODE_PPC | PPC_OPCODE_64, 86 0 }, 87 { "7400", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, 88 0 }, 89 { "7410", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, 90 0 }, 91 { "7450", PPC_OPCODE_PPC | PPC_OPCODE_7450 | PPC_OPCODE_ALTIVEC, 92 0 }, 93 { "7455", PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC, 94 0 }, 95 { "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS 96 , 0 }, 97 { "821", PPC_OPCODE_PPC | PPC_OPCODE_860, 98 0 }, 99 { "850", PPC_OPCODE_PPC | PPC_OPCODE_860, 100 0 }, 101 { "860", PPC_OPCODE_PPC | PPC_OPCODE_860, 102 0 }, 103 { "a2", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_POWER4 104 | PPC_OPCODE_POWER5 | PPC_OPCODE_CACHELCK | PPC_OPCODE_64 105 | PPC_OPCODE_A2), 106 0 }, 107 { "altivec", PPC_OPCODE_PPC, 108 PPC_OPCODE_ALTIVEC }, 109 { "any", PPC_OPCODE_PPC, 110 PPC_OPCODE_ANY }, 111 { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, 112 0 }, 113 { "booke32", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, 114 0 }, 115 { "cell", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 116 | PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC), 117 0 }, 118 { "com", PPC_OPCODE_COMMON, 119 0 }, 120 { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE 121 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 122 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 123 | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4 124 | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP), 125 0 }, 126 { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300, 127 0 }, 128 { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 129 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 130 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 131 | PPC_OPCODE_E500), 132 0 }, 133 { "e500mc", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 134 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 135 | PPC_OPCODE_E500MC), 136 0 }, 137 { "e500mc64", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 138 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 139 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER5 140 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 141 0 }, 142 { "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 143 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 144 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 145 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 146 0 }, 147 { "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL 148 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 149 | PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC 150 | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4 151 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7), 152 0 }, 153 { "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE 154 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 155 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 156 | PPC_OPCODE_E500), 157 0 }, 158 { "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS, 159 0 }, 160 { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2, 161 0 }, 162 { "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, 163 0 }, 164 { "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 165 | PPC_OPCODE_POWER5), 166 0 }, 167 { "power6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 168 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 169 0 }, 170 { "power7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 171 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 172 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 173 0 }, 174 { "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 175 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 176 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 177 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 178 0 }, 179 { "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 180 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 181 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 182 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 183 0 }, 184 { "ppc", PPC_OPCODE_PPC, 185 0 }, 186 { "ppc32", PPC_OPCODE_PPC, 187 0 }, 188 { "32", PPC_OPCODE_PPC, 189 0 }, 190 { "ppc64", PPC_OPCODE_PPC | PPC_OPCODE_64, 191 0 }, 192 { "64", PPC_OPCODE_PPC | PPC_OPCODE_64, 193 0 }, 194 { "ppc64bridge", PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE, 195 0 }, 196 { "ppcps", PPC_OPCODE_PPC | PPC_OPCODE_PPCPS, 197 0 }, 198 { "pwr", PPC_OPCODE_POWER, 199 0 }, 200 { "pwr2", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, 201 0 }, 202 { "pwr4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4, 203 0 }, 204 { "pwr5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 205 | PPC_OPCODE_POWER5), 206 0 }, 207 { "pwr5x", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 208 | PPC_OPCODE_POWER5), 209 0 }, 210 { "pwr6", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4 211 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC), 212 0 }, 213 { "pwr7", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 214 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 215 | PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 216 0 }, 217 { "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 218 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 219 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 220 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 221 0 }, 222 { "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 223 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 224 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 225 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), 226 0 }, 227 { "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2, 228 0 }, 229 { "raw", PPC_OPCODE_PPC, 230 PPC_OPCODE_RAW }, 231 { "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS, 232 PPC_OPCODE_SPE }, 233 { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE, 234 PPC_OPCODE_SPE2 }, 235 { "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR 236 | PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN), 237 0 }, 238 { "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE 239 | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK 240 | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI 241 | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2), 242 PPC_OPCODE_VLE }, 243 { "vsx", PPC_OPCODE_PPC, 244 PPC_OPCODE_VSX }, 245 }; 246 247 /* Switch between Booke and VLE dialects for interlinked dumps. */ 248 static ppc_cpu_t 249 get_powerpc_dialect (struct disassemble_info *info) 250 { 251 ppc_cpu_t dialect = 0; 252 253 dialect = POWERPC_DIALECT (info); 254 255 /* Disassemble according to the section headers flags for VLE-mode. */ 256 if (dialect & PPC_OPCODE_VLE 257 && info->section != NULL && info->section->owner != NULL 258 && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour 259 && elf_object_id (info->section->owner) == PPC32_ELF_DATA 260 && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0) 261 return dialect; 262 else 263 return dialect & ~ PPC_OPCODE_VLE; 264 } 265 266 /* Handle -m and -M options that set cpu type, and .machine arg. */ 267 268 ppc_cpu_t 269 ppc_parse_cpu (ppc_cpu_t ppc_cpu, ppc_cpu_t *sticky, const char *arg) 270 { 271 unsigned int i; 272 273 for (i = 0; i < ARRAY_SIZE (ppc_opts); i++) 274 if (disassembler_options_cmp (ppc_opts[i].opt, arg) == 0) 275 { 276 if (ppc_opts[i].sticky) 277 { 278 *sticky |= ppc_opts[i].sticky; 279 if ((ppc_cpu & ~*sticky) != 0) 280 break; 281 } 282 ppc_cpu = ppc_opts[i].cpu; 283 break; 284 } 285 if (i >= ARRAY_SIZE (ppc_opts)) 286 return 0; 287 288 ppc_cpu |= *sticky; 289 return ppc_cpu; 290 } 291 292 /* Determine which set of machines to disassemble for. */ 293 294 static void 295 powerpc_init_dialect (struct disassemble_info *info) 296 { 297 ppc_cpu_t dialect = 0; 298 ppc_cpu_t sticky = 0; 299 struct dis_private *priv = calloc (sizeof (*priv), 1); 300 301 if (priv == NULL) 302 priv = &private; 303 304 switch (info->mach) 305 { 306 case bfd_mach_ppc_403: 307 case bfd_mach_ppc_403gc: 308 dialect = ppc_parse_cpu (dialect, &sticky, "403"); 309 break; 310 case bfd_mach_ppc_405: 311 dialect = ppc_parse_cpu (dialect, &sticky, "405"); 312 break; 313 case bfd_mach_ppc_601: 314 dialect = ppc_parse_cpu (dialect, &sticky, "601"); 315 break; 316 case bfd_mach_ppc_a35: 317 case bfd_mach_ppc_rs64ii: 318 case bfd_mach_ppc_rs64iii: 319 dialect = ppc_parse_cpu (dialect, &sticky, "pwr2") | PPC_OPCODE_64; 320 break; 321 case bfd_mach_ppc_e500: 322 dialect = ppc_parse_cpu (dialect, &sticky, "e500"); 323 break; 324 case bfd_mach_ppc_e500mc: 325 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc"); 326 break; 327 case bfd_mach_ppc_e500mc64: 328 dialect = ppc_parse_cpu (dialect, &sticky, "e500mc64"); 329 break; 330 case bfd_mach_ppc_e5500: 331 dialect = ppc_parse_cpu (dialect, &sticky, "e5500"); 332 break; 333 case bfd_mach_ppc_e6500: 334 dialect = ppc_parse_cpu (dialect, &sticky, "e6500"); 335 break; 336 case bfd_mach_ppc_titan: 337 dialect = ppc_parse_cpu (dialect, &sticky, "titan"); 338 break; 339 case bfd_mach_ppc_vle: 340 dialect = ppc_parse_cpu (dialect, &sticky, "vle"); 341 break; 342 default: 343 if (info->arch == bfd_arch_powerpc) 344 dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY; 345 else 346 dialect = ppc_parse_cpu (dialect, &sticky, "pwr"); 347 break; 348 } 349 350 const char *opt; 351 FOR_EACH_DISASSEMBLER_OPTION (opt, info->disassembler_options) 352 { 353 ppc_cpu_t new_cpu = 0; 354 355 if (disassembler_options_cmp (opt, "32") == 0) 356 dialect &= ~(ppc_cpu_t) PPC_OPCODE_64; 357 else if (disassembler_options_cmp (opt, "64") == 0) 358 dialect |= PPC_OPCODE_64; 359 else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0) 360 dialect = new_cpu; 361 else 362 /* xgettext: c-format */ 363 opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt); 364 } 365 366 info->private_data = priv; 367 POWERPC_DIALECT(info) = dialect; 368 } 369 370 #define PPC_OPCD_SEGS (1 + PPC_OP (-1)) 371 static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1]; 372 #define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff))) 373 static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1]; 374 #define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1))) 375 static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1]; 376 377 /* Calculate opcode table indices to speed up disassembly, 378 and init dialect. */ 379 380 void 381 disassemble_init_powerpc (struct disassemble_info *info) 382 { 383 if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0) 384 { 385 unsigned seg, idx, op; 386 387 /* PPC opcodes */ 388 for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++) 389 { 390 powerpc_opcd_indices[seg] = idx; 391 for (; idx < powerpc_num_opcodes; idx++) 392 if (seg < PPC_OP (powerpc_opcodes[idx].opcode)) 393 break; 394 } 395 396 /* VLE opcodes */ 397 for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++) 398 { 399 vle_opcd_indices[seg] = idx; 400 for (; idx < vle_num_opcodes; idx++) 401 { 402 op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask); 403 if (seg < VLE_OP_TO_SEG (op)) 404 break; 405 } 406 } 407 408 /* SPE2 opcodes */ 409 for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++) 410 { 411 spe2_opcd_indices[seg] = idx; 412 for (; idx < spe2_num_opcodes; idx++) 413 { 414 op = SPE2_XOP (spe2_opcodes[idx].opcode); 415 if (seg < SPE2_XOP_TO_SEG (op)) 416 break; 417 } 418 } 419 } 420 421 powerpc_init_dialect (info); 422 } 423 424 /* Print a big endian PowerPC instruction. */ 425 426 int 427 print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) 428 { 429 return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info)); 430 } 431 432 /* Print a little endian PowerPC instruction. */ 433 434 int 435 print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) 436 { 437 return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info)); 438 } 439 440 /* Extract the operand value from the PowerPC or POWER instruction. */ 441 442 static int64_t 443 operand_value_powerpc (const struct powerpc_operand *operand, 444 uint64_t insn, ppc_cpu_t dialect) 445 { 446 int64_t value; 447 int invalid; 448 /* Extract the value from the instruction. */ 449 if (operand->extract) 450 value = (*operand->extract) (insn, dialect, &invalid); 451 else 452 { 453 if (operand->shift >= 0) 454 value = (insn >> operand->shift) & operand->bitm; 455 else 456 value = (insn << -operand->shift) & operand->bitm; 457 if ((operand->flags & PPC_OPERAND_SIGNED) != 0) 458 { 459 /* BITM is always some number of zeros followed by some 460 number of ones, followed by some number of zeros. */ 461 uint64_t top = operand->bitm; 462 /* top & -top gives the rightmost 1 bit, so this 463 fills in any trailing zeros. */ 464 top |= (top & -top) - 1; 465 top &= ~(top >> 1); 466 value = (value ^ top) - top; 467 } 468 } 469 470 return value; 471 } 472 473 /* Determine whether the optional operand(s) should be printed. */ 474 475 static int 476 skip_optional_operands (const unsigned char *opindex, 477 uint64_t insn, ppc_cpu_t dialect) 478 { 479 const struct powerpc_operand *operand; 480 481 for (; *opindex != 0; opindex++) 482 { 483 operand = &powerpc_operands[*opindex]; 484 if ((operand->flags & PPC_OPERAND_NEXT) != 0 485 || ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 486 && operand_value_powerpc (operand, insn, dialect) != 487 ppc_optional_operand_value (operand))) 488 return 0; 489 } 490 491 return 1; 492 } 493 494 /* Find a match for INSN in the opcode table, given machine DIALECT. */ 495 496 static const struct powerpc_opcode * 497 lookup_powerpc (uint64_t insn, ppc_cpu_t dialect) 498 { 499 const struct powerpc_opcode *opcode, *opcode_end, *last; 500 unsigned long op; 501 502 /* Get the major opcode of the instruction. */ 503 op = PPC_OP (insn); 504 505 /* Find the first match in the opcode table for this major opcode. */ 506 opcode_end = powerpc_opcodes + powerpc_opcd_indices[op + 1]; 507 last = NULL; 508 for (opcode = powerpc_opcodes + powerpc_opcd_indices[op]; 509 opcode < opcode_end; 510 ++opcode) 511 { 512 const unsigned char *opindex; 513 const struct powerpc_operand *operand; 514 int invalid; 515 516 if ((insn & opcode->mask) != opcode->opcode 517 || ((dialect & PPC_OPCODE_ANY) == 0 518 && ((opcode->flags & dialect) == 0 519 || (opcode->deprecated & dialect) != 0))) 520 continue; 521 522 /* Check validity of operands. */ 523 invalid = 0; 524 for (opindex = opcode->operands; *opindex != 0; opindex++) 525 { 526 operand = powerpc_operands + *opindex; 527 if (operand->extract) 528 (*operand->extract) (insn, dialect, &invalid); 529 } 530 if (invalid) 531 continue; 532 533 if ((dialect & PPC_OPCODE_RAW) == 0) 534 return opcode; 535 536 /* The raw machine insn is one that is not a specialization. */ 537 if (last == NULL 538 || (last->mask & ~opcode->mask) != 0) 539 last = opcode; 540 } 541 542 return last; 543 } 544 545 /* Find a match for INSN in the VLE opcode table. */ 546 547 static const struct powerpc_opcode * 548 lookup_vle (uint64_t insn) 549 { 550 const struct powerpc_opcode *opcode; 551 const struct powerpc_opcode *opcode_end; 552 unsigned op, seg; 553 554 op = PPC_OP (insn); 555 if (op >= 0x20 && op <= 0x37) 556 { 557 /* This insn has a 4-bit opcode. */ 558 op &= 0x3c; 559 } 560 seg = VLE_OP_TO_SEG (op); 561 562 /* Find the first match in the opcode table for this major opcode. */ 563 opcode_end = vle_opcodes + vle_opcd_indices[seg + 1]; 564 for (opcode = vle_opcodes + vle_opcd_indices[seg]; 565 opcode < opcode_end; 566 ++opcode) 567 { 568 uint64_t table_opcd = opcode->opcode; 569 uint64_t table_mask = opcode->mask; 570 bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask); 571 uint64_t insn2; 572 const unsigned char *opindex; 573 const struct powerpc_operand *operand; 574 int invalid; 575 576 insn2 = insn; 577 if (table_op_is_short) 578 insn2 >>= 16; 579 if ((insn2 & table_mask) != table_opcd) 580 continue; 581 582 /* Check validity of operands. */ 583 invalid = 0; 584 for (opindex = opcode->operands; *opindex != 0; ++opindex) 585 { 586 operand = powerpc_operands + *opindex; 587 if (operand->extract) 588 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); 589 } 590 if (invalid) 591 continue; 592 593 return opcode; 594 } 595 596 return NULL; 597 } 598 599 /* Find a match for INSN in the SPE2 opcode table. */ 600 601 static const struct powerpc_opcode * 602 lookup_spe2 (uint64_t insn) 603 { 604 const struct powerpc_opcode *opcode, *opcode_end; 605 unsigned op, xop, seg; 606 607 op = PPC_OP (insn); 608 if (op != 0x4) 609 { 610 /* This is not SPE2 insn. 611 * All SPE2 instructions have OP=4 and differs by XOP */ 612 return NULL; 613 } 614 xop = SPE2_XOP (insn); 615 seg = SPE2_XOP_TO_SEG (xop); 616 617 /* Find the first match in the opcode table for this major opcode. */ 618 opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1]; 619 for (opcode = spe2_opcodes + spe2_opcd_indices[seg]; 620 opcode < opcode_end; 621 ++opcode) 622 { 623 uint64_t table_opcd = opcode->opcode; 624 uint64_t table_mask = opcode->mask; 625 uint64_t insn2; 626 const unsigned char *opindex; 627 const struct powerpc_operand *operand; 628 int invalid; 629 630 insn2 = insn; 631 if ((insn2 & table_mask) != table_opcd) 632 continue; 633 634 /* Check validity of operands. */ 635 invalid = 0; 636 for (opindex = opcode->operands; *opindex != 0; ++opindex) 637 { 638 operand = powerpc_operands + *opindex; 639 if (operand->extract) 640 (*operand->extract) (insn, (ppc_cpu_t)0, &invalid); 641 } 642 if (invalid) 643 continue; 644 645 return opcode; 646 } 647 648 return NULL; 649 } 650 651 /* Print a PowerPC or POWER instruction. */ 652 653 static int 654 print_insn_powerpc (bfd_vma memaddr, 655 struct disassemble_info *info, 656 int bigendian, 657 ppc_cpu_t dialect) 658 { 659 bfd_byte buffer[4]; 660 int status; 661 uint64_t insn; 662 const struct powerpc_opcode *opcode; 663 int insn_length = 4; /* Assume we have a normal 4-byte instruction. */ 664 665 status = (*info->read_memory_func) (memaddr, buffer, 4, info); 666 667 /* The final instruction may be a 2-byte VLE insn. */ 668 if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0) 669 { 670 /* Clear buffer so unused bytes will not have garbage in them. */ 671 buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0; 672 status = (*info->read_memory_func) (memaddr, buffer, 2, info); 673 } 674 675 if (status != 0) 676 { 677 (*info->memory_error_func) (status, memaddr, info); 678 return -1; 679 } 680 681 if (bigendian) 682 insn = bfd_getb32 (buffer); 683 else 684 insn = bfd_getl32 (buffer); 685 686 /* Get the major opcode of the insn. */ 687 opcode = NULL; 688 if ((dialect & PPC_OPCODE_VLE) != 0) 689 { 690 opcode = lookup_vle (insn); 691 if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask)) 692 { 693 /* The operands will be fetched out of the 16-bit instruction. */ 694 insn >>= 16; 695 insn_length = 2; 696 } 697 } 698 if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0) 699 opcode = lookup_spe2 (insn); 700 if (opcode == NULL) 701 opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY); 702 if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0) 703 opcode = lookup_powerpc (insn, dialect); 704 705 if (opcode != NULL) 706 { 707 const unsigned char *opindex; 708 const struct powerpc_operand *operand; 709 int need_comma; 710 int need_paren; 711 int skip_optional; 712 713 if (opcode->operands[0] != 0) 714 (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); 715 else 716 (*info->fprintf_func) (info->stream, "%s", opcode->name); 717 718 /* Now extract and print the operands. */ 719 need_comma = 0; 720 need_paren = 0; 721 skip_optional = -1; 722 for (opindex = opcode->operands; *opindex != 0; opindex++) 723 { 724 int64_t value; 725 726 operand = powerpc_operands + *opindex; 727 728 /* If all of the optional operands have the value zero, 729 then don't print any of them. */ 730 if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) 731 { 732 if (skip_optional < 0) 733 skip_optional = skip_optional_operands (opindex, insn, 734 dialect); 735 if (skip_optional) 736 continue; 737 } 738 739 value = operand_value_powerpc (operand, insn, dialect); 740 741 if (need_comma) 742 { 743 (*info->fprintf_func) (info->stream, ","); 744 need_comma = 0; 745 } 746 747 /* Print the operand as directed by the flags. */ 748 if ((operand->flags & PPC_OPERAND_GPR) != 0 749 || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) 750 (*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value); 751 else if ((operand->flags & PPC_OPERAND_FPR) != 0) 752 (*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value); 753 else if ((operand->flags & PPC_OPERAND_VR) != 0) 754 (*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value); 755 else if ((operand->flags & PPC_OPERAND_VSR) != 0) 756 (*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value); 757 else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) 758 (*info->print_address_func) (memaddr + value, info); 759 else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) 760 (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); 761 else if ((operand->flags & PPC_OPERAND_FSL) != 0) 762 (*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value); 763 else if ((operand->flags & PPC_OPERAND_FCR) != 0) 764 (*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value); 765 else if ((operand->flags & PPC_OPERAND_UDI) != 0) 766 (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value); 767 else if ((operand->flags & PPC_OPERAND_CR_REG) != 0 768 && (((dialect & PPC_OPCODE_PPC) != 0) 769 || ((dialect & PPC_OPCODE_VLE) != 0))) 770 (*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value); 771 else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0) 772 && (((dialect & PPC_OPCODE_PPC) != 0) 773 || ((dialect & PPC_OPCODE_VLE) != 0))) 774 { 775 static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; 776 int cr; 777 int cc; 778 779 cr = value >> 2; 780 if (cr != 0) 781 (*info->fprintf_func) (info->stream, "4*cr%d+", cr); 782 cc = value & 3; 783 (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); 784 } 785 else 786 (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value); 787 788 if (need_paren) 789 { 790 (*info->fprintf_func) (info->stream, ")"); 791 need_paren = 0; 792 } 793 794 if ((operand->flags & PPC_OPERAND_PARENS) == 0) 795 need_comma = 1; 796 else 797 { 798 (*info->fprintf_func) (info->stream, "("); 799 need_paren = 1; 800 } 801 } 802 803 /* We have found and printed an instruction. */ 804 return insn_length; 805 } 806 807 /* We could not find a match. */ 808 (*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn); 809 810 return 4; 811 } 812 813 const disasm_options_t * 814 disassembler_options_powerpc (void) 815 { 816 static disasm_options_t *opts = NULL; 817 818 if (opts == NULL) 819 { 820 size_t i, num_options = ARRAY_SIZE (ppc_opts); 821 opts = XNEW (disasm_options_t); 822 opts->name = XNEWVEC (const char *, num_options + 1); 823 for (i = 0; i < num_options; i++) 824 opts->name[i] = ppc_opts[i].opt; 825 /* The array we return must be NULL terminated. */ 826 opts->name[i] = NULL; 827 opts->description = NULL; 828 } 829 830 return opts; 831 } 832 833 void 834 print_ppc_disassembler_options (FILE *stream) 835 { 836 unsigned int i, col; 837 838 fprintf (stream, _("\n\ 839 The following PPC specific disassembler options are supported for use with\n\ 840 the -M switch:\n")); 841 842 for (col = 0, i = 0; i < ARRAY_SIZE (ppc_opts); i++) 843 { 844 col += fprintf (stream, " %s,", ppc_opts[i].opt); 845 if (col > 66) 846 { 847 fprintf (stream, "\n"); 848 col = 0; 849 } 850 } 851 fprintf (stream, "\n"); 852 } 853