1 /* Instruction printing code for the ARM 2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 4 Modification by James G. Smith (jsmith@cygnus.co.uk) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "sysdep.h" 24 25 #include "disassemble.h" 26 #include "opcode/arm.h" 27 #include "opintl.h" 28 #include "safe-ctype.h" 29 #include "libiberty.h" 30 #include "floatformat.h" 31 32 /* FIXME: This shouldn't be done here. */ 33 #include "coff/internal.h" 34 #include "libcoff.h" 35 #include "elf-bfd.h" 36 #include "elf/internal.h" 37 #include "elf/arm.h" 38 #include "mach-o.h" 39 40 /* FIXME: Belongs in global header. */ 41 #ifndef strneq 42 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 43 #endif 44 45 /* Cached mapping symbol state. */ 46 enum map_type 47 { 48 MAP_ARM, 49 MAP_THUMB, 50 MAP_DATA 51 }; 52 53 struct arm_private_data 54 { 55 /* The features to use when disassembling optional instructions. */ 56 arm_feature_set features; 57 58 /* Whether any mapping symbols are present in the provided symbol 59 table. -1 if we do not know yet, otherwise 0 or 1. */ 60 int has_mapping_symbols; 61 62 /* Track the last type (although this doesn't seem to be useful) */ 63 enum map_type last_type; 64 65 /* Tracking symbol table information */ 66 int last_mapping_sym; 67 bfd_vma last_mapping_addr; 68 }; 69 70 struct opcode32 71 { 72 arm_feature_set arch; /* Architecture defining this insn. */ 73 unsigned long value; /* If arch is 0 then value is a sentinel. */ 74 unsigned long mask; /* Recognise insn if (op & mask) == value. */ 75 const char * assembler; /* How to disassemble this insn. */ 76 }; 77 78 struct opcode16 79 { 80 arm_feature_set arch; /* Architecture defining this insn. */ 81 unsigned short value, mask; /* Recognise insn if (op & mask) == value. */ 82 const char *assembler; /* How to disassemble this insn. */ 83 }; 84 85 /* print_insn_coprocessor recognizes the following format control codes: 86 87 %% % 88 89 %c print condition code (always bits 28-31 in ARM mode) 90 %q print shifter argument 91 %u print condition code (unconditional in ARM mode, 92 UNPREDICTABLE if not AL in Thumb) 93 %A print address for ldc/stc/ldf/stf instruction 94 %B print vstm/vldm register list 95 %I print cirrus signed shift immediate: bits 0..3|4..6 96 %F print the COUNT field of a LFM/SFM instruction. 97 %P print floating point precision in arithmetic insn 98 %Q print floating point precision in ldf/stf insn 99 %R print floating point rounding mode 100 101 %<bitfield>c print as a condition code (for vsel) 102 %<bitfield>r print as an ARM register 103 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 104 %<bitfield>ru as %<>r but each u register must be unique. 105 %<bitfield>d print the bitfield in decimal 106 %<bitfield>k print immediate for VFPv3 conversion instruction 107 %<bitfield>x print the bitfield in hex 108 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 109 %<bitfield>f print a floating point constant if >7 else a 110 floating point register 111 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 112 %<bitfield>g print as an iWMMXt 64-bit register 113 %<bitfield>G print as an iWMMXt general purpose or control register 114 %<bitfield>D print as a NEON D register 115 %<bitfield>Q print as a NEON Q register 116 %<bitfield>V print as a NEON D or Q register 117 %<bitfield>E print a quarter-float immediate value 118 119 %y<code> print a single precision VFP reg. 120 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 121 %z<code> print a double precision VFP reg 122 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 123 124 %<bitfield>'c print specified char iff bitfield is all ones 125 %<bitfield>`c print specified char iff bitfield is all zeroes 126 %<bitfield>?ab... select from array of values in big endian order 127 128 %L print as an iWMMXt N/M width field. 129 %Z print the Immediate of a WSHUFH instruction. 130 %l like 'A' except use byte offsets for 'B' & 'H' 131 versions. 132 %i print 5-bit immediate in bits 8,3..0 133 (print "32" when 0) 134 %r print register offset address for wldt/wstr instruction. */ 135 136 enum opcode_sentinel_enum 137 { 138 SENTINEL_IWMMXT_START = 1, 139 SENTINEL_IWMMXT_END, 140 SENTINEL_GENERIC_START 141 } opcode_sentinels; 142 143 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x" 144 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>" 145 146 /* Common coprocessor opcodes shared between Arm and Thumb-2. */ 147 148 static const struct opcode32 coprocessor_opcodes[] = 149 { 150 /* XScale instructions. */ 151 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 152 0x0e200010, 0x0fff0ff0, 153 "mia%c\tacc0, %0-3r, %12-15r"}, 154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 155 0x0e280010, 0x0fff0ff0, 156 "miaph%c\tacc0, %0-3r, %12-15r"}, 157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 158 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 159 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 160 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 161 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 162 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 163 164 /* Intel Wireless MMX technology instructions. */ 165 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" }, 166 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), 167 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 168 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 169 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 170 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 171 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 172 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 173 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 174 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 175 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 176 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 177 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 178 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 179 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 180 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 181 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 182 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 183 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 184 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 185 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 186 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 187 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 188 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 189 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 190 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 191 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 192 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 193 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 194 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 195 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 196 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 197 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 198 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 199 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 200 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 201 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 202 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 203 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 204 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 205 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 206 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 207 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 208 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 209 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 210 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 211 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 212 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 213 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 214 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 215 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 216 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 217 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 218 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 219 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 220 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 221 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 222 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 223 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 224 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 225 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 226 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 227 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 228 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 229 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 230 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 231 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 232 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 233 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 234 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 235 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 236 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 237 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 238 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 239 0x0e800120, 0x0f800ff0, 240 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 242 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 243 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 244 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 245 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 246 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 247 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 248 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 249 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 250 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 251 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 252 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 253 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 254 0x0e8000a0, 0x0f800ff0, 255 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 257 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 258 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 259 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 260 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 261 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 262 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 263 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 264 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 265 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 266 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 267 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 268 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 269 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 270 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 271 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 272 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 273 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 274 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 275 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 276 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 277 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 278 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 279 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 280 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 281 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 282 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 283 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 284 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 285 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 286 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 287 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 288 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 289 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 290 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 291 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 292 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 293 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 294 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 295 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 296 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 297 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 298 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 299 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 300 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 301 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 302 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 303 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 304 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 305 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 306 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 307 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 308 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 309 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 310 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 311 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 312 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 313 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 314 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 315 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 316 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), 317 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 318 {ARM_FEATURE_CORE_LOW (0), 319 SENTINEL_IWMMXT_END, 0, "" }, 320 321 /* Floating point coprocessor (FPA) instructions. */ 322 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 323 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 324 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 325 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 326 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 327 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 328 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 329 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 330 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 331 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 332 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 333 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 334 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 335 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 336 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 337 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 338 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 339 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 340 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 341 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 342 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 343 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 344 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 345 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 346 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 347 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 348 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 349 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 350 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 351 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 352 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 353 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 354 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 355 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 356 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 357 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 358 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 359 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 360 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 361 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 362 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 363 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 364 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 365 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 366 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 367 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 368 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 369 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 370 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 371 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 372 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 373 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 374 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 375 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 376 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 377 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 378 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 379 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 380 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 381 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 382 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 383 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 384 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 385 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 386 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 387 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 388 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 389 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 390 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 391 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 392 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 393 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 394 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 395 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 396 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 397 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 398 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 399 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 400 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 401 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 402 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1), 403 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 404 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 405 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 406 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2), 407 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 408 409 /* ARMv8-M Mainline Security Extensions instructions. */ 410 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 411 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"}, 412 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN), 413 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"}, 414 415 /* Register load/store. */ 416 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 417 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"}, 418 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 419 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"}, 420 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 421 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"}, 422 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 423 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 424 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 425 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"}, 426 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 427 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 428 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 429 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"}, 430 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1), 431 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"}, 432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 433 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"}, 434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 435 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"}, 436 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 437 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"}, 438 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 439 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"}, 440 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 441 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"}, 442 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 443 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"}, 444 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 445 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"}, 446 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 447 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"}, 448 449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 450 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 451 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 452 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"}, 453 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 454 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 455 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 456 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"}, 457 458 /* Data transfer between ARM and NEON registers. */ 459 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 460 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 462 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 464 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 466 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 468 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 470 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 472 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 474 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 476 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 478 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 480 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 482 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 484 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 486 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 487 /* Half-precision conversion instructions. */ 488 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 489 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"}, 490 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 491 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"}, 492 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 493 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"}, 494 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 495 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"}, 496 497 /* Floating point coprocessor (VFP) instructions. */ 498 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 499 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"}, 500 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 501 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"}, 502 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 503 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"}, 504 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 505 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"}, 506 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 507 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"}, 508 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 509 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"}, 510 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 511 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"}, 512 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 513 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"}, 514 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 515 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"}, 516 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 517 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"}, 518 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 519 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"}, 520 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 521 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"}, 522 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 523 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"}, 524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 525 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"}, 526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 527 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"}, 528 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 529 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"}, 530 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 531 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"}, 532 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 533 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"}, 534 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 535 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"}, 536 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 537 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"}, 538 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 539 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"}, 540 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 541 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"}, 542 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 543 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"}, 544 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 545 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"}, 546 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 547 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"}, 548 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 549 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"}, 550 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 551 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"}, 552 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 553 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"}, 554 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 555 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"}, 556 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 557 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"}, 558 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 559 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"}, 560 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 561 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"}, 562 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 563 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"}, 564 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 565 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"}, 566 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 567 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"}, 568 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 569 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"}, 570 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 571 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"}, 572 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 573 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"}, 574 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 575 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"}, 576 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 577 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 578 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 579 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"}, 580 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 581 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"}, 582 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 583 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"}, 584 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 585 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"}, 586 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 587 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"}, 588 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 589 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"}, 590 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD), 591 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"}, 592 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3), 593 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"}, 594 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 595 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"}, 596 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 597 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"}, 598 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2), 599 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"}, 600 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 601 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"}, 602 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 603 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"}, 604 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 605 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"}, 606 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 607 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"}, 608 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 609 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"}, 610 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 611 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"}, 612 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 613 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"}, 614 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 615 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"}, 616 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 617 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"}, 618 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 619 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"}, 620 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 621 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"}, 622 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 623 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"}, 624 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 625 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"}, 626 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 627 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"}, 628 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 629 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"}, 630 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 631 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"}, 632 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD), 633 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"}, 634 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), 635 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 636 637 /* Cirrus coprocessor instructions. */ 638 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 639 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 640 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 641 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 642 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 643 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 644 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 645 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 646 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 647 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 648 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 649 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 650 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 651 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 652 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 653 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 654 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 655 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 656 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 657 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 658 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 659 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 660 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 661 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 662 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 663 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 664 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 665 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 666 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 667 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 668 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 669 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 670 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 671 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 672 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 673 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 674 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 675 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 676 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 677 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 678 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 679 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 680 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 681 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 682 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 683 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 684 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 685 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 686 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 687 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 688 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 689 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 690 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 691 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 692 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 693 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 694 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 695 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 696 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 697 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 698 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 699 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 700 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 701 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 702 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 703 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 704 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 705 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 706 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 707 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 708 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 709 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 710 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 711 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 712 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 713 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 714 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 715 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 716 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 717 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 718 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 719 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 720 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 721 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 722 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 723 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 724 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 725 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 726 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 727 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 728 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 729 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 730 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 731 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 732 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 733 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 734 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 735 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 736 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 737 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 738 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 739 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 740 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 741 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 742 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 743 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 744 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 745 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 746 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 747 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 748 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 749 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 750 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 751 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 752 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 753 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 754 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 755 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 756 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 757 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 758 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 759 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 760 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 761 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 762 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 763 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 764 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 765 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 766 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 767 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 768 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 769 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 770 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 771 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 772 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 773 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 774 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 775 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 776 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 777 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 778 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 779 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 780 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 781 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 782 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 783 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 784 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 785 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 786 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 787 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 788 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 789 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 790 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 791 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 792 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 793 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 794 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 795 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 796 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 797 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 798 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 799 0x0e000600, 0x0ff00f10, 800 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 802 0x0e100600, 0x0ff00f10, 803 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 805 0x0e200600, 0x0ff00f10, 806 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), 808 0x0e300600, 0x0ff00f10, 809 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 810 811 /* VFP Fused multiply add instructions. */ 812 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 813 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 814 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 815 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"}, 816 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 817 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"}, 818 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 819 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"}, 820 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 821 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"}, 822 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 823 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"}, 824 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 825 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"}, 826 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), 827 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"}, 828 829 /* FP v5. */ 830 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 831 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, 832 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 833 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, 834 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 835 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, 836 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 837 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, 838 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 839 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, 840 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 841 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, 842 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 843 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, 844 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 845 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"}, 846 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 847 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"}, 848 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 849 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, 850 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 851 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, 852 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 853 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, 854 855 /* Generic coprocessor instructions. */ 856 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, 857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 858 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"}, 859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 860 0x0c500000, 0x0ff00000, 861 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 863 0x0e000000, 0x0f000010, 864 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 866 0x0e10f010, 0x0f10f010, 867 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"}, 868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 869 0x0e100010, 0x0f100010, 870 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 872 0x0e000010, 0x0f100010, 873 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 875 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 877 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 878 879 /* V6 coprocessor instructions. */ 880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 881 0xfc500000, 0xfff00000, 882 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"}, 883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 884 0xfc400000, 0xfff00000, 885 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"}, 886 887 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */ 888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 889 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 891 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"}, 892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 893 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 895 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 896 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 897 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"}, 898 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 899 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, 900 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 901 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, 902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 903 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, 904 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 905 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, 906 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 907 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, 908 909 /* Dot Product instructions in the space of coprocessor 13. */ 910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 911 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"}, 912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 913 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, 914 915 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ 916 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 917 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 919 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, 920 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 921 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 922 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 923 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, 924 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 925 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 926 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 927 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, 928 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 929 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), 931 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, 932 933 /* V5 coprocessor instructions. */ 934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 935 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 937 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 939 0xfe000000, 0xff000010, 940 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 942 0xfe000010, 0xff100010, 943 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"}, 944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 945 0xfe100010, 0xff100010, 946 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 947 948 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions. 949 cp_num: bit <11:8> == 0b1001. 950 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */ 951 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 952 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"}, 953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 954 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"}, 955 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 956 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"}, 957 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 958 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"}, 959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 960 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"}, 961 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 962 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"}, 963 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 964 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"}, 965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 966 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"}, 967 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 968 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"}, 969 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 970 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"}, 971 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 972 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"}, 973 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 974 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"}, 975 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 976 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"}, 977 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 978 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"}, 979 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 980 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"}, 981 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 982 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"}, 983 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 984 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"}, 985 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 986 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"}, 987 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 988 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"}, 989 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 990 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"}, 991 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 992 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"}, 993 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 994 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"}, 995 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 996 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"}, 997 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 998 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"}, 999 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1000 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"}, 1001 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1002 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"}, 1003 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1004 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"}, 1005 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1006 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"}, 1007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1008 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"}, 1009 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1010 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"}, 1011 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1012 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"}, 1013 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1014 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"}, 1015 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1016 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"}, 1017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1018 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"}, 1019 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1020 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"}, 1021 1022 /* ARMv8.3 javascript conversion instruction. */ 1023 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 1024 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"}, 1025 1026 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 1027 }; 1028 1029 /* Neon opcode table: This does not encode the top byte -- that is 1030 checked by the print_insn_neon routine, as it depends on whether we are 1031 doing thumb32 or arm32 disassembly. */ 1032 1033 /* print_insn_neon recognizes the following format control codes: 1034 1035 %% % 1036 1037 %c print condition code 1038 %u print condition code (unconditional in ARM mode, 1039 UNPREDICTABLE if not AL in Thumb) 1040 %A print v{st,ld}[1234] operands 1041 %B print v{st,ld}[1234] any one operands 1042 %C print v{st,ld}[1234] single->all operands 1043 %D print scalar 1044 %E print vmov, vmvn, vorr, vbic encoded constant 1045 %F print vtbl,vtbx register list 1046 1047 %<bitfield>r print as an ARM register 1048 %<bitfield>d print the bitfield in decimal 1049 %<bitfield>e print the 2^N - bitfield in decimal 1050 %<bitfield>D print as a NEON D register 1051 %<bitfield>Q print as a NEON Q register 1052 %<bitfield>R print as a NEON D or Q register 1053 %<bitfield>Sn print byte scaled width limited by n 1054 %<bitfield>Tn print short scaled width limited by n 1055 %<bitfield>Un print long scaled width limited by n 1056 1057 %<bitfield>'c print specified char iff bitfield is all ones 1058 %<bitfield>`c print specified char iff bitfield is all zeroes 1059 %<bitfield>?ab... select from array of values in big endian order. */ 1060 1061 static const struct opcode32 neon_opcodes[] = 1062 { 1063 /* Extract. */ 1064 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1065 0xf2b00840, 0xffb00850, 1066 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1068 0xf2b00000, 0xffb00810, 1069 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 1070 1071 /* Move data element to all lanes. */ 1072 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1073 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 1074 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1075 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 1076 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1077 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 1078 1079 /* Table lookup. */ 1080 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1081 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 1082 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1083 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 1084 1085 /* Half-precision conversions. */ 1086 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1087 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"}, 1088 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16), 1089 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"}, 1090 1091 /* NEON fused multiply add instructions. */ 1092 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1093 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1094 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1095 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1096 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA), 1097 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1099 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1100 1101 /* Two registers, miscellaneous. */ 1102 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1103 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"}, 1104 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1105 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"}, 1106 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1107 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"}, 1108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1109 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"}, 1110 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1111 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"}, 1112 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1113 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"}, 1114 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1115 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"}, 1116 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1117 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"}, 1118 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1119 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"}, 1120 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1121 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"}, 1122 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1123 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"}, 1124 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1125 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 1126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1127 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 1128 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1129 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 1130 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1131 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 1132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1133 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 1134 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1135 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 1136 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1137 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 1138 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1139 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1140 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1141 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 1142 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1143 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 1144 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1145 0xf3b20300, 0xffb30fd0, 1146 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1148 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1149 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1150 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1152 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 1153 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1154 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"}, 1155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1156 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1158 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1160 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1162 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1164 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 1165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1166 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1168 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 1169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1170 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1172 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1174 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 1175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1176 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1178 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1179 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1180 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1181 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1182 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1183 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1184 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 1185 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1186 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1187 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1188 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 1189 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1190 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1191 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1192 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 1193 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1194 0xf3bb0600, 0xffbf0e10, 1195 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 1196 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1197 0xf3b70600, 0xffbf0e10, 1198 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"}, 1199 1200 /* Three registers of the same length. */ 1201 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1202 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1203 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1204 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1205 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1206 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1207 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1208 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1209 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1210 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1211 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1212 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1213 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1214 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, 1215 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1216 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1217 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1218 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1219 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8), 1220 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1221 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1222 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1223 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1224 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1225 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1226 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1227 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1228 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1229 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1230 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1231 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1232 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1233 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1234 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1235 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1236 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1237 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1238 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1239 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1240 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1241 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1242 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1243 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1244 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1245 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1246 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1247 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1248 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1249 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1250 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1251 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1252 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1253 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1254 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1255 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1256 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1257 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1258 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1260 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1261 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1262 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1263 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1264 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1265 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1266 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1268 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1270 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1272 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1273 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1274 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1276 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1277 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1278 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1279 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1280 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1281 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1282 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1284 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1286 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1287 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1288 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1289 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1290 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1292 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1293 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1294 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1295 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1296 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1298 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1299 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1300 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1301 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1302 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1303 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1304 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1305 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1306 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1307 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1308 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1310 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1312 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1313 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1314 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1316 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1317 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1318 0xf2000b00, 0xff800f10, 1319 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1321 0xf2000b10, 0xff800f10, 1322 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1324 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1325 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1326 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1327 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1328 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1329 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1330 0xf3000b00, 0xff800f10, 1331 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1333 0xf2000000, 0xfe800f10, 1334 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1336 0xf2000010, 0xfe800f10, 1337 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1339 0xf2000100, 0xfe800f10, 1340 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1342 0xf2000200, 0xfe800f10, 1343 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1345 0xf2000210, 0xfe800f10, 1346 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1348 0xf2000300, 0xfe800f10, 1349 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1351 0xf2000310, 0xfe800f10, 1352 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1354 0xf2000400, 0xfe800f10, 1355 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1357 0xf2000410, 0xfe800f10, 1358 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1360 0xf2000500, 0xfe800f10, 1361 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1363 0xf2000510, 0xfe800f10, 1364 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1366 0xf2000600, 0xfe800f10, 1367 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1369 0xf2000610, 0xfe800f10, 1370 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1372 0xf2000700, 0xfe800f10, 1373 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1375 0xf2000710, 0xfe800f10, 1376 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1378 0xf2000910, 0xfe800f10, 1379 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1381 0xf2000a00, 0xfe800f10, 1382 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1384 0xf2000a10, 0xfe800f10, 1385 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1387 0xf3000b10, 0xff800f10, 1388 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1390 0xf3000c10, 0xff800f10, 1391 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 1392 1393 /* One register and an immediate value. */ 1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1395 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1397 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1399 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1401 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1403 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1405 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1407 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1409 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1411 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1413 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1415 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 1416 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1417 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1419 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 1420 1421 /* Two registers and a shift amount. */ 1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1423 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1425 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1427 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1429 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1430 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1431 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1433 0xf2880950, 0xfeb80fd0, 1434 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1436 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"}, 1437 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1438 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1439 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1440 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1441 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1442 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1443 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1444 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1445 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1446 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1447 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1448 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1449 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1450 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1451 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1452 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1453 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1454 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1455 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1456 0xf2900950, 0xfeb00fd0, 1457 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1459 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"}, 1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1461 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1463 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1465 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1467 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1469 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1471 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1473 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1475 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1477 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1479 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1481 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1483 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"}, 1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1485 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1487 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1489 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1491 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1493 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 1494 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1495 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1497 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1499 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1501 0xf2a00950, 0xfea00fd0, 1502 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1504 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1506 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1508 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1510 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1512 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1514 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1516 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1518 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1520 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1522 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1524 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1526 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1528 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1530 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1532 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1534 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1536 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1538 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1540 0xf2a00e10, 0xfea00e90, 1541 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST), 1543 0xf2a00c10, 0xfea00e90, 1544 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"}, 1545 1546 /* Three registers of different lengths. */ 1547 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8), 1548 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1549 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1550 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1551 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1552 0xf2800400, 0xff800f50, 1553 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1555 0xf2800600, 0xff800f50, 1556 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1558 0xf2800900, 0xff800f50, 1559 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1561 0xf2800b00, 0xff800f50, 1562 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1564 0xf2800d00, 0xff800f50, 1565 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1567 0xf3800400, 0xff800f50, 1568 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1570 0xf3800600, 0xff800f50, 1571 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1573 0xf2800000, 0xfe800f50, 1574 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1576 0xf2800100, 0xfe800f50, 1577 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1579 0xf2800200, 0xfe800f50, 1580 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1582 0xf2800300, 0xfe800f50, 1583 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1585 0xf2800500, 0xfe800f50, 1586 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1588 0xf2800700, 0xfe800f50, 1589 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1591 0xf2800800, 0xfe800f50, 1592 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1594 0xf2800a00, 0xfe800f50, 1595 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1597 0xf2800c00, 0xfe800f50, 1598 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 1599 1600 /* Two registers and a scalar. */ 1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1602 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1604 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1605 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1606 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1608 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1610 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1612 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1613 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1614 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1616 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1618 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1620 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 1621 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1622 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"}, 1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1624 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1626 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1628 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1630 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1632 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1633 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1634 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1636 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1638 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1639 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1640 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1642 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1644 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 1645 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST), 1646 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"}, 1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1648 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1650 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1652 0xf2800240, 0xfe800f50, 1653 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1655 0xf2800640, 0xfe800f50, 1656 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1658 0xf2800a40, 0xfe800f50, 1659 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1661 0xf2800e40, 0xff800f50, 1662 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1664 0xf2800f40, 0xff800f50, 1665 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1667 0xf3800e40, 0xff800f50, 1668 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA), 1670 0xf3800f40, 0xff800f50, 1671 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D" 1672 }, 1673 1674 /* Element and structure load/store. */ 1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1676 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1678 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1680 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1682 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1684 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1686 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1688 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1690 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1692 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1694 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1696 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1698 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1700 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1702 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1704 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1706 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1708 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1710 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), 1712 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 1713 1714 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0} 1715 }; 1716 1717 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 1718 ordered: they must be searched linearly from the top to obtain a correct 1719 match. */ 1720 1721 /* print_insn_arm recognizes the following format control codes: 1722 1723 %% % 1724 1725 %a print address for ldr/str instruction 1726 %s print address for ldr/str halfword/signextend instruction 1727 %S like %s but allow UNPREDICTABLE addressing 1728 %b print branch destination 1729 %c print condition code (always bits 28-31) 1730 %m print register mask for ldm/stm instruction 1731 %o print operand2 (immediate or register + shift) 1732 %p print 'p' iff bits 12-15 are 15 1733 %t print 't' iff bit 21 set and bit 24 clear 1734 %B print arm BLX(1) destination 1735 %C print the PSR sub type. 1736 %U print barrier type. 1737 %P print address for pli instruction. 1738 1739 %<bitfield>r print as an ARM register 1740 %<bitfield>T print as an ARM register + 1 1741 %<bitfield>R as %r but r15 is UNPREDICTABLE 1742 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE 1743 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE 1744 %<bitfield>d print the bitfield in decimal 1745 %<bitfield>W print the bitfield plus one in decimal 1746 %<bitfield>x print the bitfield in hex 1747 %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 1748 1749 %<bitfield>'c print specified char iff bitfield is all ones 1750 %<bitfield>`c print specified char iff bitfield is all zeroes 1751 %<bitfield>?ab... select from array of values in big endian order 1752 1753 %e print arm SMI operand (bits 0..7,8..19). 1754 %E print the LSB and WIDTH fields of a BFI or BFC instruction. 1755 %V print the 16-bit immediate field of a MOVT or MOVW instruction. 1756 %R print the SPSR/CPSR or banked register of an MRS. */ 1757 1758 static const struct opcode32 arm_opcodes[] = 1759 { 1760 /* ARM instructions. */ 1761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1762 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"}, 1763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 1764 0xe7f000f0, 0xfff000f0, "udf\t#%e"}, 1765 1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5), 1767 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 1768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1769 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"}, 1770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2), 1771 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S), 1773 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"}, 1774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1775 0x00800090, 0x0fa000f0, 1776 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M), 1778 0x00a00090, 0x0fa000f0, 1779 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 1780 1781 /* V8.2 RAS extension instructions. */ 1782 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 1783 0xe320f010, 0xffffffff, "esb"}, 1784 1785 /* V8 instructions. */ 1786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1787 0x0320f005, 0x0fffffff, "sevl"}, 1788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1789 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"}, 1790 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS), 1791 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"}, 1792 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1793 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 1794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1795 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"}, 1796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 1797 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"}, 1798 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1799 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"}, 1800 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1801 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 1802 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1803 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"}, 1804 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1805 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 1806 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1807 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"}, 1808 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1809 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"}, 1810 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1811 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"}, 1812 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1813 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 1814 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1815 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"}, 1816 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS), 1817 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 1818 /* CRC32 instructions. */ 1819 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1820 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"}, 1821 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1822 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"}, 1823 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1824 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"}, 1825 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1826 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"}, 1827 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1828 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"}, 1829 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 1830 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"}, 1831 1832 /* Privileged Access Never extension instructions. */ 1833 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 1834 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"}, 1835 1836 /* Virtualization Extension instructions. */ 1837 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"}, 1838 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"}, 1839 1840 /* Integer Divide Extension instructions. */ 1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1842 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"}, 1843 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV), 1844 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"}, 1845 1846 /* MP Extension instructions. */ 1847 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"}, 1848 1849 /* Speculation Barriers. */ 1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, 1851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff040, 0xffffffff, "ssbb"}, 1852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xf57ff044, 0xffffffff, "pssbb"}, 1853 1854 /* V7 instructions. */ 1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"}, 1856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 1857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"}, 1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"}, 1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, 1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 1863 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, 1864 1865 /* ARM V6T2 instructions. */ 1866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1867 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"}, 1868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1869 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"}, 1870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1871 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 1872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1873 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"}, 1874 1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1876 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION }, 1877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1878 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, 1879 1880 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1881 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, 1882 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 1883 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, 1884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1885 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, 1886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 1887 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 1888 1889 /* ARM Security extension instructions. */ 1890 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 1891 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 1892 1893 /* ARM V6K instructions. */ 1894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1895 0xf57ff01f, 0xffffffff, "clrex"}, 1896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1897 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"}, 1898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1899 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"}, 1900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1901 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"}, 1902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1903 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"}, 1904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1905 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"}, 1906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1907 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, 1908 1909 /* ARM V6K NOP hints. */ 1910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1911 0x0320f001, 0x0fffffff, "yield%c"}, 1912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1913 0x0320f002, 0x0fffffff, "wfe%c"}, 1914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1915 0x0320f003, 0x0fffffff, "wfi%c"}, 1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1917 0x0320f004, 0x0fffffff, "sev%c"}, 1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 1919 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 1920 1921 /* ARM V6 instructions. */ 1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1923 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1925 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 1926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1927 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 1928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1929 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1931 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1933 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"}, 1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1935 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"}, 1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1937 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"}, 1938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1939 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"}, 1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1941 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"}, 1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1943 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"}, 1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1945 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"}, 1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1947 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"}, 1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1949 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"}, 1950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1951 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"}, 1952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1953 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"}, 1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1955 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"}, 1956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1957 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"}, 1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1959 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"}, 1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1961 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"}, 1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1963 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"}, 1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1965 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"}, 1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1967 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"}, 1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1969 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"}, 1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1971 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"}, 1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1973 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"}, 1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1975 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"}, 1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1977 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"}, 1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1979 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"}, 1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1981 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"}, 1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1983 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"}, 1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1985 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"}, 1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1987 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"}, 1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1989 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"}, 1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1991 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"}, 1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1993 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"}, 1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1995 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"}, 1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1997 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"}, 1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 1999 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"}, 2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2001 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"}, 2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2003 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"}, 2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2005 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"}, 2006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2007 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"}, 2008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2009 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"}, 2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2011 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"}, 2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2013 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"}, 2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2015 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"}, 2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2017 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"}, 2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2019 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"}, 2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2021 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"}, 2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2023 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"}, 2024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2025 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"}, 2026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2027 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"}, 2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2029 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"}, 2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2031 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"}, 2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2033 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"}, 2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2035 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"}, 2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2037 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"}, 2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2039 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"}, 2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2041 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"}, 2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2043 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"}, 2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2045 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"}, 2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2047 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"}, 2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2049 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"}, 2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2051 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"}, 2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2053 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"}, 2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2055 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"}, 2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2057 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"}, 2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2059 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"}, 2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2061 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"}, 2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2063 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"}, 2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2065 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"}, 2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2067 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"}, 2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2069 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"}, 2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2071 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"}, 2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2073 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2075 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2077 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2079 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2081 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2083 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2085 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2087 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"}, 2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2089 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2091 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2093 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2095 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"}, 2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2097 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2099 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2101 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2103 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"}, 2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2105 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2107 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2109 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"}, 2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2111 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"}, 2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2113 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"}, 2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2115 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"}, 2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2117 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"}, 2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2119 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"}, 2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2121 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2123 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2125 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"}, 2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2127 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2129 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2131 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2133 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2135 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"}, 2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2137 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2139 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2141 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2143 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"}, 2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2145 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"}, 2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2147 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"}, 2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2149 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2151 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"}, 2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2153 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"}, 2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2155 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"}, 2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2157 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2159 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"}, 2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2161 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"}, 2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2163 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"}, 2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 2165 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"}, 2166 2167 /* V5J instruction. */ 2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J), 2169 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"}, 2170 2171 /* V5 Instructions. */ 2172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2173 0xe1200070, 0xfff000f0, 2174 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 2175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2176 0xfa000000, 0xfe000000, "blx\t%B"}, 2177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2178 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"}, 2179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 2180 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"}, 2181 2182 /* V5E "El Segundo" Instructions. */ 2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2184 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2186 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 2187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E), 2188 0xf450f000, 0xfc70f000, "pld\t%a"}, 2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2190 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2192 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2194 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2196 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"}, 2197 2198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2199 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"}, 2200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2201 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"}, 2202 2203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2204 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2206 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2208 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2210 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, 2211 2212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2213 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"}, 2214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2215 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"}, 2216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2217 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"}, 2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2219 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"}, 2220 2221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2222 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"}, 2223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2224 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"}, 2225 2226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2227 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"}, 2228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2229 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"}, 2230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2231 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"}, 2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP), 2233 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"}, 2234 2235 /* ARM Instructions. */ 2236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2237 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 2238 2239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2240 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"}, 2241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2242 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"}, 2243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2244 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"}, 2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2246 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"}, 2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2248 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"}, 2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2250 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"}, 2251 2252 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2253 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"}, 2254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2255 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"}, 2256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2257 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"}, 2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2259 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"}, 2260 2261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2262 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION}, 2263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2264 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2266 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION}, 2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2268 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"}, 2269 2270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2271 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 2272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2273 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"}, 2274 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2275 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"}, 2276 2277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2278 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2280 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"}, 2281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2282 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"}, 2283 2284 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2285 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2286 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2287 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"}, 2288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2289 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"}, 2290 2291 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2292 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2293 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2294 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 2295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2296 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"}, 2297 2298 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2299 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 2300 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2301 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"}, 2302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2303 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"}, 2304 2305 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2306 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2307 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2308 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"}, 2309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2310 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"}, 2311 2312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2313 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2315 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 2316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2317 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"}, 2318 2319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2320 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2322 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 2323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2324 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"}, 2325 2326 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 2327 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"}, 2328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2329 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"}, 2330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 2331 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"}, 2332 2333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2334 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"}, 2335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2336 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"}, 2337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2338 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, 2339 2340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2341 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, 2342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2343 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, 2344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2345 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, 2346 2347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2348 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, 2349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2350 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"}, 2351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2352 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"}, 2353 2354 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2355 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"}, 2356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2357 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"}, 2358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2359 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"}, 2360 2361 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2362 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2364 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"}, 2365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2366 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"}, 2367 2368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2369 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 2370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2371 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 2372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2373 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"}, 2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2375 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"}, 2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2377 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"}, 2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2379 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2381 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"}, 2382 2383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2384 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2386 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"}, 2387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2388 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"}, 2389 2390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2391 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"}, 2392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2393 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"}, 2394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2395 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"}, 2396 2397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2398 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION}, 2399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2400 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 2401 2402 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2403 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"}, 2404 2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2406 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"}, 2407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2408 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"}, 2409 2410 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2411 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2413 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2415 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2417 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2419 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2421 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2423 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2425 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2427 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2429 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2431 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2433 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2435 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2437 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2439 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2441 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"}, 2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2443 0x092d0000, 0x0fff0000, "push%c\t%m"}, 2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2445 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"}, 2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2447 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2448 2449 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2450 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2452 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2454 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2456 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2458 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2460 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2462 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2464 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2466 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2468 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2470 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2472 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2474 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2476 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2478 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2480 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"}, 2481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2482 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2484 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"}, 2485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2486 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"}, 2487 2488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2489 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 2490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2491 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 2492 2493 /* The rest. */ 2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 2495 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, 2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 2497 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 2498 {ARM_FEATURE_CORE_LOW (0), 2499 0x00000000, 0x00000000, 0} 2500 }; 2501 2502 /* print_insn_thumb16 recognizes the following format control codes: 2503 2504 %S print Thumb register (bits 3..5 as high number if bit 6 set) 2505 %D print Thumb register (bits 0..2 as high number if bit 7 set) 2506 %<bitfield>I print bitfield as a signed decimal 2507 (top bit of range being the sign bit) 2508 %N print Thumb register mask (with LR) 2509 %O print Thumb register mask (with PC) 2510 %M print Thumb register mask 2511 %b print CZB's 6-bit unsigned branch destination 2512 %s print Thumb right-shift immediate (6..10; 0 == 32). 2513 %c print the condition code 2514 %C print the condition code, or "s" if not conditional 2515 %x print warning if conditional an not at end of IT block" 2516 %X print "\t; unpredictable <IT:code>" if conditional 2517 %I print IT instruction suffix and operands 2518 %W print Thumb Writeback indicator for LDMIA 2519 %<bitfield>r print bitfield as an ARM register 2520 %<bitfield>d print bitfield as a decimal 2521 %<bitfield>H print (bitfield * 2) as a decimal 2522 %<bitfield>W print (bitfield * 4) as a decimal 2523 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 2524 %<bitfield>B print Thumb branch destination (signed displacement) 2525 %<bitfield>c print bitfield as a condition code 2526 %<bitnum>'c print specified char iff bit is one 2527 %<bitnum>?ab print a if bit is one else print b. */ 2528 2529 static const struct opcode16 thumb_opcodes[] = 2530 { 2531 /* Thumb instructions. */ 2532 2533 /* ARMv8-M Security Extensions instructions. */ 2534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"}, 2535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff87, "bxns\t%3-6r"}, 2536 2537 /* ARM V8 instructions. */ 2538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"}, 2539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"}, 2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"}, 2541 2542 /* ARM V6K no-argument instructions. */ 2543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"}, 2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"}, 2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"}, 2546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"}, 2547 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"}, 2548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 2549 2550 /* ARM V6T2 instructions. */ 2551 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2552 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 2553 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2554 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 2555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, 2556 2557 /* ARM V6. */ 2558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 2559 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 2560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 2562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 2563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"}, 2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 2569 2570 /* ARM V5 ISA extends Thumb. */ 2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2572 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 2573 /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T), 2575 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 2576 /* ARM V4T ISA (Thumb v1). */ 2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2578 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"}, 2579 /* Format 4. */ 2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 2581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 2582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 2584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 2585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 2596 /* format 13 */ 2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 2599 /* format 5 */ 2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"}, 2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"}, 2602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"}, 2604 /* format 14 */ 2605 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"}, 2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"}, 2607 /* format 2 */ 2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2609 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 2610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2611 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2613 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2615 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 2616 /* format 8 */ 2617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2618 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 2619 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2620 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 2621 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2622 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 2623 /* format 7 */ 2624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2625 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2627 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 2628 /* format 1 */ 2629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"}, 2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2631 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 2633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 2634 /* format 3 */ 2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 2637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 2639 /* format 6 */ 2640 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2642 0x4800, 0xF800, 2643 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, 2644 /* format 9 */ 2645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2646 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2648 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 2649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2650 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2652 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 2653 /* format 10 */ 2654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2655 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2657 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 2658 /* format 11 */ 2659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2660 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 2661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2662 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 2663 /* format 12 */ 2664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2665 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"}, 2666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 2667 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 2668 /* format 15 */ 2669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"}, 2671 /* format 17 */ 2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 2673 /* format 16 */ 2674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"}, 2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION}, 2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 2677 /* format 18 */ 2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 2679 2680 /* The E800 .. FFFF range is unconditionally redirected to the 2681 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 2682 are processed via that table. Thus, we can never encounter a 2683 bare "second half of BL/BLX(1)" instruction here. */ 2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x0000, 0x0000, UNDEFINED_INSTRUCTION}, 2685 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 2686 }; 2687 2688 /* Thumb32 opcodes use the same table structure as the ARM opcodes. 2689 We adopt the convention that hw1 is the high 16 bits of .value and 2690 .mask, hw2 the low 16 bits. 2691 2692 print_insn_thumb32 recognizes the following format control codes: 2693 2694 %% % 2695 2696 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 2697 %M print a modified 12-bit immediate (same location) 2698 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 2699 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 2700 %H print a 16-bit immediate from hw2[3:0],hw1[11:0] 2701 %S print a possibly-shifted Rm 2702 2703 %L print address for a ldrd/strd instruction 2704 %a print the address of a plain load/store 2705 %w print the width and signedness of a core load/store 2706 %m print register mask for ldm/stm 2707 2708 %E print the lsb and width fields of a bfc/bfi instruction 2709 %F print the lsb and width fields of a sbfx/ubfx instruction 2710 %b print a conditional branch offset 2711 %B print an unconditional branch offset 2712 %s print the shift field of an SSAT instruction 2713 %R print the rotation field of an SXT instruction 2714 %U print barrier type. 2715 %P print address for pli instruction. 2716 %c print the condition code 2717 %x print warning if conditional an not at end of IT block" 2718 %X print "\t; unpredictable <IT:code>" if conditional 2719 2720 %<bitfield>d print bitfield in decimal 2721 %<bitfield>D print bitfield plus one in decimal 2722 %<bitfield>W print bitfield*4 in decimal 2723 %<bitfield>r print bitfield as an ARM register 2724 %<bitfield>R as %<>r but r15 is UNPREDICTABLE 2725 %<bitfield>c print bitfield as a condition code 2726 2727 %<bitfield>'c print specified char iff bitfield is all ones 2728 %<bitfield>`c print specified char iff bitfield is all zeroes 2729 %<bitfield>?ab... select from array of values in big endian order 2730 2731 With one exception at the bottom (done because BL and BLX(1) need 2732 to come dead last), this table was machine-sorted first in 2733 decreasing order of number of bits set in the mask, then in 2734 increasing numeric order of mask, then in increasing numeric order 2735 of opcode. This order is not the clearest for a human reader, but 2736 is guaranteed never to catch a special-case bit pattern with a more 2737 general mask, which is important, because this instruction encoding 2738 makes heavy use of special-case bit patterns. */ 2739 static const struct opcode32 thumb32_opcodes[] = 2740 { 2741 /* ARMv8-M and ARMv8-M Security Extensions instructions. */ 2742 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"}, 2743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2744 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"}, 2745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2746 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, 2747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2748 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"}, 2749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 2750 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"}, 2751 2752 /* ARM V8.2 RAS extension instructions. */ 2753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS), 2754 0xf3af8010, 0xffffffff, "esb"}, 2755 2756 /* V8 instructions. */ 2757 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2758 0xf3af8005, 0xffffffff, "sevl%c.w"}, 2759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2760 0xf78f8000, 0xfffffffc, "dcps%0-1d"}, 2761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2762 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"}, 2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2764 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"}, 2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2766 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"}, 2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2768 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"}, 2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2770 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"}, 2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2772 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"}, 2773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2774 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"}, 2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2776 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"}, 2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2778 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"}, 2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2780 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"}, 2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2782 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"}, 2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2784 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"}, 2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2786 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"}, 2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 2788 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"}, 2789 2790 /* CRC32 instructions. */ 2791 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2792 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, 2793 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2794 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, 2795 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2796 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, 2797 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2798 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, 2799 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2800 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, 2801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), 2802 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, 2803 2804 /* Speculation Barriers. */ 2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, 2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f40, 0xffffffff, "ssbb"}, 2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3bf8f44, 0xffffffff, "pssbb"}, 2808 2809 /* V7 instructions. */ 2810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, 2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"}, 2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"}, 2814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2818 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV), 2820 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 2821 2822 /* Virtualization Extension instructions. */ 2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"}, 2824 /* We skip ERET as that is SUBS pc, lr, #0. */ 2825 2826 /* MP Extension instructions. */ 2827 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf830f000, 0xff70f000, "pldw%c\t%a"}, 2828 2829 /* Security extension instructions. */ 2830 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 2831 2832 /* Instructions defined in the basic V6T2 set. */ 2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, 2834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, 2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"}, 2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"}, 2837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"}, 2838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2839 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 2840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, 2841 2842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2843 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2845 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2847 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 2848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2849 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 2850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2851 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 2852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2853 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 2854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2855 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"}, 2856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2857 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2859 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2861 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2863 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2865 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2867 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 2868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2869 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 2870 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2871 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 2872 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2873 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2875 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2877 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2879 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2881 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2883 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2885 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2887 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2889 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 2890 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2891 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2893 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2895 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2897 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2899 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2901 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2903 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2905 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2907 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2909 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2911 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2913 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2915 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2917 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2919 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2921 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2923 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2925 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2927 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2929 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2931 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2933 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2935 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"}, 2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2937 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"}, 2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2939 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"}, 2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2941 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"}, 2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2943 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"}, 2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2945 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"}, 2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2947 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2949 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2951 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2953 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2955 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2957 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2959 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2961 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2963 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2965 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2967 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2969 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2971 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2973 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2975 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"}, 2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2977 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"}, 2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2979 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"}, 2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2981 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"}, 2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2983 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"}, 2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2985 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"}, 2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2987 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2989 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2991 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2993 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2995 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, 2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 2997 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 2998 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 2999 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3001 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, 3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3003 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3005 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3007 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3009 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3011 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3013 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3015 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3017 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3019 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3021 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3023 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3025 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3027 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3029 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3031 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3033 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3035 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3037 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3039 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3041 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3043 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3045 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3047 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3049 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3051 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3053 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3055 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3057 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3059 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3061 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3063 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3065 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3066 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3067 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3069 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3071 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3073 0xf810f000, 0xff70f000, "pld%c\t%a"}, 3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3075 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3077 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3079 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3081 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3083 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"}, 3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3085 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3087 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, 3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3089 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3091 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3093 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3095 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3097 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3099 0xfb100000, 0xfff000c0, 3100 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3102 0xfbc00080, 0xfff000c0, 3103 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3105 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3107 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3109 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"}, 3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3111 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3113 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 3114 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3115 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3117 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 3118 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3119 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3121 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 3122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3123 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 3124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3125 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 3126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3127 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 3128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3129 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 3130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3131 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 3132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3133 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 3134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3135 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 3136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3137 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 3138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3139 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 3140 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 3141 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 3142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3143 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 3144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3145 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3147 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3149 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 3150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3151 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 3152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3153 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 3154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3155 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 3156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3157 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 3158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3159 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3161 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3163 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3165 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3167 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 3168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3169 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 3170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3171 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 3172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3173 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3175 0xe9400000, 0xff500000, 3176 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3178 0xe9500000, 0xff500000, 3179 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"}, 3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3181 0xe8600000, 0xff700000, 3182 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3184 0xe8700000, 0xff700000, 3185 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"}, 3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3187 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 3188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3189 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 3190 3191 /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3193 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 3194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3195 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 3196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3197 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 3198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 3199 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 3200 3201 /* These have been 32-bit since the invention of Thumb. */ 3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3203 0xf000c000, 0xf800d001, "blx%c\t%B%x"}, 3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 3205 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 3206 3207 /* Fallback. */ 3208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 3209 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, 3210 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0} 3211 }; 3212 3213 static const char *const arm_conditional[] = 3214 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 3215 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 3216 3217 static const char *const arm_fp_const[] = 3218 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 3219 3220 static const char *const arm_shift[] = 3221 {"lsl", "lsr", "asr", "ror"}; 3222 3223 typedef struct 3224 { 3225 const char *name; 3226 const char *description; 3227 const char *reg_names[16]; 3228 } 3229 arm_regname; 3230 3231 static const arm_regname regnames[] = 3232 { 3233 { "reg-names-raw", N_("Select raw register names"), 3234 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 3235 { "reg-names-gcc", N_("Select register names used by GCC"), 3236 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3237 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"), 3238 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 3239 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} }, 3240 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} }, 3241 { "reg-names-apcs", N_("Select register names used in the APCS"), 3242 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 3243 { "reg-names-atpcs", N_("Select register names used in the ATPCS"), 3244 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 3245 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"), 3246 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} 3247 }; 3248 3249 static const char *const iwmmxt_wwnames[] = 3250 {"b", "h", "w", "d"}; 3251 3252 static const char *const iwmmxt_wwssnames[] = 3253 {"b", "bus", "bc", "bss", 3254 "h", "hus", "hc", "hss", 3255 "w", "wus", "wc", "wss", 3256 "d", "dus", "dc", "dss" 3257 }; 3258 3259 static const char *const iwmmxt_regnames[] = 3260 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 3261 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 3262 }; 3263 3264 static const char *const iwmmxt_cregnames[] = 3265 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 3266 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 3267 }; 3268 3269 /* Default to GCC register name set. */ 3270 static unsigned int regname_selected = 1; 3271 3272 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames) 3273 #define arm_regnames regnames[regname_selected].reg_names 3274 3275 static bfd_boolean force_thumb = FALSE; 3276 3277 /* Current IT instruction state. This contains the same state as the IT 3278 bits in the CPSR. */ 3279 static unsigned int ifthen_state; 3280 /* IT state for the next instruction. */ 3281 static unsigned int ifthen_next_state; 3282 /* The address of the insn for which the IT state is valid. */ 3283 static bfd_vma ifthen_address; 3284 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 3285 /* Indicates that the current Conditional state is unconditional or outside 3286 an IT block. */ 3287 #define COND_UNCOND 16 3288 3289 3290 /* Functions. */ 3291 3292 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 3293 Returns pointer to following character of the format string and 3294 fills in *VALUEP and *WIDTHP with the extracted value and number of 3295 bits extracted. WIDTHP can be NULL. */ 3296 3297 static const char * 3298 arm_decode_bitfield (const char *ptr, 3299 unsigned long insn, 3300 unsigned long *valuep, 3301 int *widthp) 3302 { 3303 unsigned long value = 0; 3304 int width = 0; 3305 3306 do 3307 { 3308 int start, end; 3309 int bits; 3310 3311 for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 3312 start = start * 10 + *ptr - '0'; 3313 if (*ptr == '-') 3314 for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 3315 end = end * 10 + *ptr - '0'; 3316 else 3317 end = start; 3318 bits = end - start; 3319 if (bits < 0) 3320 abort (); 3321 value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 3322 width += bits + 1; 3323 } 3324 while (*ptr++ == ','); 3325 *valuep = value; 3326 if (widthp) 3327 *widthp = width; 3328 return ptr - 1; 3329 } 3330 3331 static void 3332 arm_decode_shift (long given, fprintf_ftype func, void *stream, 3333 bfd_boolean print_shift) 3334 { 3335 func (stream, "%s", arm_regnames[given & 0xf]); 3336 3337 if ((given & 0xff0) != 0) 3338 { 3339 if ((given & 0x10) == 0) 3340 { 3341 int amount = (given & 0xf80) >> 7; 3342 int shift = (given & 0x60) >> 5; 3343 3344 if (amount == 0) 3345 { 3346 if (shift == 3) 3347 { 3348 func (stream, ", rrx"); 3349 return; 3350 } 3351 3352 amount = 32; 3353 } 3354 3355 if (print_shift) 3356 func (stream, ", %s #%d", arm_shift[shift], amount); 3357 else 3358 func (stream, ", #%d", amount); 3359 } 3360 else if ((given & 0x80) == 0x80) 3361 func (stream, "\t; <illegal shifter operand>"); 3362 else if (print_shift) 3363 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 3364 arm_regnames[(given & 0xf00) >> 8]); 3365 else 3366 func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 3367 } 3368 } 3369 3370 #define W_BIT 21 3371 #define I_BIT 22 3372 #define U_BIT 23 3373 #define P_BIT 24 3374 3375 #define WRITEBACK_BIT_SET (given & (1 << W_BIT)) 3376 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT)) 3377 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0) 3378 #define PRE_BIT_SET (given & (1 << P_BIT)) 3379 3380 /* Print one coprocessor instruction on INFO->STREAM. 3381 Return TRUE if the instuction matched, FALSE if this is not a 3382 recognised coprocessor instruction. */ 3383 3384 static bfd_boolean 3385 print_insn_coprocessor (bfd_vma pc, 3386 struct disassemble_info *info, 3387 long given, 3388 bfd_boolean thumb) 3389 { 3390 const struct opcode32 *insn; 3391 void *stream = info->stream; 3392 fprintf_ftype func = info->fprintf_func; 3393 unsigned long mask; 3394 unsigned long value = 0; 3395 int cond; 3396 int cp_num; 3397 struct arm_private_data *private_data = info->private_data; 3398 arm_feature_set allowed_arches = ARM_ARCH_NONE; 3399 3400 allowed_arches = private_data->features; 3401 3402 for (insn = coprocessor_opcodes; insn->assembler; insn++) 3403 { 3404 unsigned long u_reg = 16; 3405 bfd_boolean is_unpredictable = FALSE; 3406 signed long value_in_comment = 0; 3407 const char *c; 3408 3409 if (ARM_FEATURE_ZERO (insn->arch)) 3410 switch (insn->value) 3411 { 3412 case SENTINEL_IWMMXT_START: 3413 if (info->mach != bfd_mach_arm_XScale 3414 && info->mach != bfd_mach_arm_iWMMXt 3415 && info->mach != bfd_mach_arm_iWMMXt2) 3416 do 3417 insn++; 3418 while ((! ARM_FEATURE_ZERO (insn->arch)) 3419 && insn->value != SENTINEL_IWMMXT_END); 3420 continue; 3421 3422 case SENTINEL_IWMMXT_END: 3423 continue; 3424 3425 case SENTINEL_GENERIC_START: 3426 allowed_arches = private_data->features; 3427 continue; 3428 3429 default: 3430 abort (); 3431 } 3432 3433 mask = insn->mask; 3434 value = insn->value; 3435 cp_num = (given >> 8) & 0xf; 3436 3437 if (thumb) 3438 { 3439 /* The high 4 bits are 0xe for Arm conditional instructions, and 3440 0xe for arm unconditional instructions. The rest of the 3441 encoding is the same. */ 3442 mask |= 0xf0000000; 3443 value |= 0xe0000000; 3444 if (ifthen_state) 3445 cond = IFTHEN_COND; 3446 else 3447 cond = COND_UNCOND; 3448 } 3449 else 3450 { 3451 /* Only match unconditional instuctions against unconditional 3452 patterns. */ 3453 if ((given & 0xf0000000) == 0xf0000000) 3454 { 3455 mask |= 0xf0000000; 3456 cond = COND_UNCOND; 3457 } 3458 else 3459 { 3460 cond = (given >> 28) & 0xf; 3461 if (cond == 0xe) 3462 cond = COND_UNCOND; 3463 } 3464 } 3465 3466 if ((given & mask) != value) 3467 continue; 3468 3469 if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches)) 3470 continue; 3471 3472 if (insn->value == 0xfe000010 /* mcr2 */ 3473 || insn->value == 0xfe100010 /* mrc2 */ 3474 || insn->value == 0xfc100000 /* ldc2 */ 3475 || insn->value == 0xfc000000) /* stc2 */ 3476 { 3477 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3478 is_unpredictable = TRUE; 3479 } 3480 else if (insn->value == 0x0e000000 /* cdp */ 3481 || insn->value == 0xfe000000 /* cdp2 */ 3482 || insn->value == 0x0e000010 /* mcr */ 3483 || insn->value == 0x0e100010 /* mrc */ 3484 || insn->value == 0x0c100000 /* ldc */ 3485 || insn->value == 0x0c000000) /* stc */ 3486 { 3487 /* Floating-point instructions. */ 3488 if (cp_num == 9 || cp_num == 10 || cp_num == 11) 3489 continue; 3490 } 3491 3492 for (c = insn->assembler; *c; c++) 3493 { 3494 if (*c == '%') 3495 { 3496 switch (*++c) 3497 { 3498 case '%': 3499 func (stream, "%%"); 3500 break; 3501 3502 case 'A': 3503 { 3504 int rn = (given >> 16) & 0xf; 3505 bfd_vma offset = given & 0xff; 3506 3507 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3508 3509 if (PRE_BIT_SET || WRITEBACK_BIT_SET) 3510 { 3511 /* Not unindexed. The offset is scaled. */ 3512 if (cp_num == 9) 3513 /* vldr.16/vstr.16 will shift the address 3514 left by 1 bit only. */ 3515 offset = offset * 2; 3516 else 3517 offset = offset * 4; 3518 3519 if (NEGATIVE_BIT_SET) 3520 offset = - offset; 3521 if (rn != 15) 3522 value_in_comment = offset; 3523 } 3524 3525 if (PRE_BIT_SET) 3526 { 3527 if (offset) 3528 func (stream, ", #%d]%s", 3529 (int) offset, 3530 WRITEBACK_BIT_SET ? "!" : ""); 3531 else if (NEGATIVE_BIT_SET) 3532 func (stream, ", #-0]"); 3533 else 3534 func (stream, "]"); 3535 } 3536 else 3537 { 3538 func (stream, "]"); 3539 3540 if (WRITEBACK_BIT_SET) 3541 { 3542 if (offset) 3543 func (stream, ", #%d", (int) offset); 3544 else if (NEGATIVE_BIT_SET) 3545 func (stream, ", #-0"); 3546 } 3547 else 3548 { 3549 func (stream, ", {%s%d}", 3550 (NEGATIVE_BIT_SET && !offset) ? "-" : "", 3551 (int) offset); 3552 value_in_comment = offset; 3553 } 3554 } 3555 if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET)) 3556 { 3557 func (stream, "\t; "); 3558 /* For unaligned PCs, apply off-by-alignment 3559 correction. */ 3560 info->print_address_func (offset + pc 3561 + info->bytes_per_chunk * 2 3562 - (pc & 3), 3563 info); 3564 } 3565 } 3566 break; 3567 3568 case 'B': 3569 { 3570 int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 3571 int offset = (given >> 1) & 0x3f; 3572 3573 if (offset == 1) 3574 func (stream, "{d%d}", regno); 3575 else if (regno + offset > 32) 3576 func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 3577 else 3578 func (stream, "{d%d-d%d}", regno, regno + offset - 1); 3579 } 3580 break; 3581 3582 case 'u': 3583 if (cond != COND_UNCOND) 3584 is_unpredictable = TRUE; 3585 3586 /* Fall through. */ 3587 case 'c': 3588 if (cond != COND_UNCOND && cp_num == 9) 3589 is_unpredictable = TRUE; 3590 3591 func (stream, "%s", arm_conditional[cond]); 3592 break; 3593 3594 case 'I': 3595 /* Print a Cirrus/DSP shift immediate. */ 3596 /* Immediates are 7bit signed ints with bits 0..3 in 3597 bits 0..3 of opcode and bits 4..6 in bits 5..7 3598 of opcode. */ 3599 { 3600 int imm; 3601 3602 imm = (given & 0xf) | ((given & 0xe0) >> 1); 3603 3604 /* Is ``imm'' a negative number? */ 3605 if (imm & 0x40) 3606 imm -= 0x80; 3607 3608 func (stream, "%d", imm); 3609 } 3610 3611 break; 3612 3613 case 'F': 3614 switch (given & 0x00408000) 3615 { 3616 case 0: 3617 func (stream, "4"); 3618 break; 3619 case 0x8000: 3620 func (stream, "1"); 3621 break; 3622 case 0x00400000: 3623 func (stream, "2"); 3624 break; 3625 default: 3626 func (stream, "3"); 3627 } 3628 break; 3629 3630 case 'P': 3631 switch (given & 0x00080080) 3632 { 3633 case 0: 3634 func (stream, "s"); 3635 break; 3636 case 0x80: 3637 func (stream, "d"); 3638 break; 3639 case 0x00080000: 3640 func (stream, "e"); 3641 break; 3642 default: 3643 func (stream, _("<illegal precision>")); 3644 break; 3645 } 3646 break; 3647 3648 case 'Q': 3649 switch (given & 0x00408000) 3650 { 3651 case 0: 3652 func (stream, "s"); 3653 break; 3654 case 0x8000: 3655 func (stream, "d"); 3656 break; 3657 case 0x00400000: 3658 func (stream, "e"); 3659 break; 3660 default: 3661 func (stream, "p"); 3662 break; 3663 } 3664 break; 3665 3666 case 'R': 3667 switch (given & 0x60) 3668 { 3669 case 0: 3670 break; 3671 case 0x20: 3672 func (stream, "p"); 3673 break; 3674 case 0x40: 3675 func (stream, "m"); 3676 break; 3677 default: 3678 func (stream, "z"); 3679 break; 3680 } 3681 break; 3682 3683 case '0': case '1': case '2': case '3': case '4': 3684 case '5': case '6': case '7': case '8': case '9': 3685 { 3686 int width; 3687 3688 c = arm_decode_bitfield (c, given, &value, &width); 3689 3690 switch (*c) 3691 { 3692 case 'R': 3693 if (value == 15) 3694 is_unpredictable = TRUE; 3695 /* Fall through. */ 3696 case 'r': 3697 if (c[1] == 'u') 3698 { 3699 /* Eat the 'u' character. */ 3700 ++ c; 3701 3702 if (u_reg == value) 3703 is_unpredictable = TRUE; 3704 u_reg = value; 3705 } 3706 func (stream, "%s", arm_regnames[value]); 3707 break; 3708 case 'V': 3709 if (given & (1 << 6)) 3710 goto Q; 3711 /* FALLTHROUGH */ 3712 case 'D': 3713 func (stream, "d%ld", value); 3714 break; 3715 case 'Q': 3716 Q: 3717 if (value & 1) 3718 func (stream, "<illegal reg q%ld.5>", value >> 1); 3719 else 3720 func (stream, "q%ld", value >> 1); 3721 break; 3722 case 'd': 3723 func (stream, "%ld", value); 3724 value_in_comment = value; 3725 break; 3726 case 'E': 3727 { 3728 /* Converts immediate 8 bit back to float value. */ 3729 unsigned floatVal = (value & 0x80) << 24 3730 | (value & 0x3F) << 19 3731 | ((value & 0x40) ? (0xF8 << 22) : (1 << 30)); 3732 3733 /* Quarter float have a maximum value of 31.0. 3734 Get floating point value multiplied by 1e7. 3735 The maximum value stays in limit of a 32-bit int. */ 3736 unsigned decVal = 3737 (78125 << (((floatVal >> 23) & 0xFF) - 124)) * 3738 (16 + (value & 0xF)); 3739 3740 if (!(decVal % 1000000)) 3741 func (stream, "%ld\t; 0x%08x %c%u.%01u", value, 3742 floatVal, value & 0x80 ? '-' : ' ', 3743 decVal / 10000000, 3744 decVal % 10000000 / 1000000); 3745 else if (!(decVal % 10000)) 3746 func (stream, "%ld\t; 0x%08x %c%u.%03u", value, 3747 floatVal, value & 0x80 ? '-' : ' ', 3748 decVal / 10000000, 3749 decVal % 10000000 / 10000); 3750 else 3751 func (stream, "%ld\t; 0x%08x %c%u.%07u", value, 3752 floatVal, value & 0x80 ? '-' : ' ', 3753 decVal / 10000000, decVal % 10000000); 3754 break; 3755 } 3756 case 'k': 3757 { 3758 int from = (given & (1 << 7)) ? 32 : 16; 3759 func (stream, "%ld", from - value); 3760 } 3761 break; 3762 3763 case 'f': 3764 if (value > 7) 3765 func (stream, "#%s", arm_fp_const[value & 7]); 3766 else 3767 func (stream, "f%ld", value); 3768 break; 3769 3770 case 'w': 3771 if (width == 2) 3772 func (stream, "%s", iwmmxt_wwnames[value]); 3773 else 3774 func (stream, "%s", iwmmxt_wwssnames[value]); 3775 break; 3776 3777 case 'g': 3778 func (stream, "%s", iwmmxt_regnames[value]); 3779 break; 3780 case 'G': 3781 func (stream, "%s", iwmmxt_cregnames[value]); 3782 break; 3783 3784 case 'x': 3785 func (stream, "0x%lx", (value & 0xffffffffUL)); 3786 break; 3787 3788 case 'c': 3789 switch (value) 3790 { 3791 case 0: 3792 func (stream, "eq"); 3793 break; 3794 3795 case 1: 3796 func (stream, "vs"); 3797 break; 3798 3799 case 2: 3800 func (stream, "ge"); 3801 break; 3802 3803 case 3: 3804 func (stream, "gt"); 3805 break; 3806 3807 default: 3808 func (stream, "??"); 3809 break; 3810 } 3811 break; 3812 3813 case '`': 3814 c++; 3815 if (value == 0) 3816 func (stream, "%c", *c); 3817 break; 3818 case '\'': 3819 c++; 3820 if (value == ((1ul << width) - 1)) 3821 func (stream, "%c", *c); 3822 break; 3823 case '?': 3824 func (stream, "%c", c[(1 << width) - (int) value]); 3825 c += 1 << width; 3826 break; 3827 default: 3828 abort (); 3829 } 3830 break; 3831 3832 case 'y': 3833 case 'z': 3834 { 3835 int single = *c++ == 'y'; 3836 int regno; 3837 3838 switch (*c) 3839 { 3840 case '4': /* Sm pair */ 3841 case '0': /* Sm, Dm */ 3842 regno = given & 0x0000000f; 3843 if (single) 3844 { 3845 regno <<= 1; 3846 regno += (given >> 5) & 1; 3847 } 3848 else 3849 regno += ((given >> 5) & 1) << 4; 3850 break; 3851 3852 case '1': /* Sd, Dd */ 3853 regno = (given >> 12) & 0x0000000f; 3854 if (single) 3855 { 3856 regno <<= 1; 3857 regno += (given >> 22) & 1; 3858 } 3859 else 3860 regno += ((given >> 22) & 1) << 4; 3861 break; 3862 3863 case '2': /* Sn, Dn */ 3864 regno = (given >> 16) & 0x0000000f; 3865 if (single) 3866 { 3867 regno <<= 1; 3868 regno += (given >> 7) & 1; 3869 } 3870 else 3871 regno += ((given >> 7) & 1) << 4; 3872 break; 3873 3874 case '3': /* List */ 3875 func (stream, "{"); 3876 regno = (given >> 12) & 0x0000000f; 3877 if (single) 3878 { 3879 regno <<= 1; 3880 regno += (given >> 22) & 1; 3881 } 3882 else 3883 regno += ((given >> 22) & 1) << 4; 3884 break; 3885 3886 default: 3887 abort (); 3888 } 3889 3890 func (stream, "%c%d", single ? 's' : 'd', regno); 3891 3892 if (*c == '3') 3893 { 3894 int count = given & 0xff; 3895 3896 if (single == 0) 3897 count >>= 1; 3898 3899 if (--count) 3900 { 3901 func (stream, "-%c%d", 3902 single ? 's' : 'd', 3903 regno + count); 3904 } 3905 3906 func (stream, "}"); 3907 } 3908 else if (*c == '4') 3909 func (stream, ", %c%d", single ? 's' : 'd', 3910 regno + 1); 3911 } 3912 break; 3913 3914 case 'L': 3915 switch (given & 0x00400100) 3916 { 3917 case 0x00000000: func (stream, "b"); break; 3918 case 0x00400000: func (stream, "h"); break; 3919 case 0x00000100: func (stream, "w"); break; 3920 case 0x00400100: func (stream, "d"); break; 3921 default: 3922 break; 3923 } 3924 break; 3925 3926 case 'Z': 3927 { 3928 /* given (20, 23) | given (0, 3) */ 3929 value = ((given >> 16) & 0xf0) | (given & 0xf); 3930 func (stream, "%d", (int) value); 3931 } 3932 break; 3933 3934 case 'l': 3935 /* This is like the 'A' operator, except that if 3936 the width field "M" is zero, then the offset is 3937 *not* multiplied by four. */ 3938 { 3939 int offset = given & 0xff; 3940 int multiplier = (given & 0x00000100) ? 4 : 1; 3941 3942 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 3943 3944 if (multiplier > 1) 3945 { 3946 value_in_comment = offset * multiplier; 3947 if (NEGATIVE_BIT_SET) 3948 value_in_comment = - value_in_comment; 3949 } 3950 3951 if (offset) 3952 { 3953 if (PRE_BIT_SET) 3954 func (stream, ", #%s%d]%s", 3955 NEGATIVE_BIT_SET ? "-" : "", 3956 offset * multiplier, 3957 WRITEBACK_BIT_SET ? "!" : ""); 3958 else 3959 func (stream, "], #%s%d", 3960 NEGATIVE_BIT_SET ? "-" : "", 3961 offset * multiplier); 3962 } 3963 else 3964 func (stream, "]"); 3965 } 3966 break; 3967 3968 case 'r': 3969 { 3970 int imm4 = (given >> 4) & 0xf; 3971 int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1); 3972 int ubit = ! NEGATIVE_BIT_SET; 3973 const char *rm = arm_regnames [given & 0xf]; 3974 const char *rn = arm_regnames [(given >> 16) & 0xf]; 3975 3976 switch (puw_bits) 3977 { 3978 case 1: 3979 case 3: 3980 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 3981 if (imm4) 3982 func (stream, ", lsl #%d", imm4); 3983 break; 3984 3985 case 4: 3986 case 5: 3987 case 6: 3988 case 7: 3989 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 3990 if (imm4 > 0) 3991 func (stream, ", lsl #%d", imm4); 3992 func (stream, "]"); 3993 if (puw_bits == 5 || puw_bits == 7) 3994 func (stream, "!"); 3995 break; 3996 3997 default: 3998 func (stream, "INVALID"); 3999 } 4000 } 4001 break; 4002 4003 case 'i': 4004 { 4005 long imm5; 4006 imm5 = ((given & 0x100) >> 4) | (given & 0xf); 4007 func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 4008 } 4009 break; 4010 4011 default: 4012 abort (); 4013 } 4014 } 4015 } 4016 else 4017 func (stream, "%c", *c); 4018 } 4019 4020 if (value_in_comment > 32 || value_in_comment < -16) 4021 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 4022 4023 if (is_unpredictable) 4024 func (stream, UNPREDICTABLE_INSTRUCTION); 4025 4026 return TRUE; 4027 } 4028 return FALSE; 4029 } 4030 4031 /* Decodes and prints ARM addressing modes. Returns the offset 4032 used in the address, if any, if it is worthwhile printing the 4033 offset as a hexadecimal value in a comment at the end of the 4034 line of disassembly. */ 4035 4036 static signed long 4037 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 4038 { 4039 void *stream = info->stream; 4040 fprintf_ftype func = info->fprintf_func; 4041 bfd_vma offset = 0; 4042 4043 if (((given & 0x000f0000) == 0x000f0000) 4044 && ((given & 0x02000000) == 0)) 4045 { 4046 offset = given & 0xfff; 4047 4048 func (stream, "[pc"); 4049 4050 if (PRE_BIT_SET) 4051 { 4052 /* Pre-indexed. Elide offset of positive zero when 4053 non-writeback. */ 4054 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4055 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4056 4057 if (NEGATIVE_BIT_SET) 4058 offset = -offset; 4059 4060 offset += pc + 8; 4061 4062 /* Cope with the possibility of write-back 4063 being used. Probably a very dangerous thing 4064 for the programmer to do, but who are we to 4065 argue ? */ 4066 func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : ""); 4067 } 4068 else /* Post indexed. */ 4069 { 4070 func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4071 4072 /* Ie ignore the offset. */ 4073 offset = pc + 8; 4074 } 4075 4076 func (stream, "\t; "); 4077 info->print_address_func (offset, info); 4078 offset = 0; 4079 } 4080 else 4081 { 4082 func (stream, "[%s", 4083 arm_regnames[(given >> 16) & 0xf]); 4084 4085 if (PRE_BIT_SET) 4086 { 4087 if ((given & 0x02000000) == 0) 4088 { 4089 /* Elide offset of positive zero when non-writeback. */ 4090 offset = given & 0xfff; 4091 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset) 4092 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4093 } 4094 else 4095 { 4096 func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : ""); 4097 arm_decode_shift (given, func, stream, TRUE); 4098 } 4099 4100 func (stream, "]%s", 4101 WRITEBACK_BIT_SET ? "!" : ""); 4102 } 4103 else 4104 { 4105 if ((given & 0x02000000) == 0) 4106 { 4107 /* Always show offset. */ 4108 offset = given & 0xfff; 4109 func (stream, "], #%s%d", 4110 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4111 } 4112 else 4113 { 4114 func (stream, "], %s", 4115 NEGATIVE_BIT_SET ? "-" : ""); 4116 arm_decode_shift (given, func, stream, TRUE); 4117 } 4118 } 4119 if (NEGATIVE_BIT_SET) 4120 offset = -offset; 4121 } 4122 4123 return (signed long) offset; 4124 } 4125 4126 /* Print one neon instruction on INFO->STREAM. 4127 Return TRUE if the instuction matched, FALSE if this is not a 4128 recognised neon instruction. */ 4129 4130 static bfd_boolean 4131 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 4132 { 4133 const struct opcode32 *insn; 4134 void *stream = info->stream; 4135 fprintf_ftype func = info->fprintf_func; 4136 4137 if (thumb) 4138 { 4139 if ((given & 0xef000000) == 0xef000000) 4140 { 4141 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 4142 unsigned long bit28 = given & (1 << 28); 4143 4144 given &= 0x00ffffff; 4145 if (bit28) 4146 given |= 0xf3000000; 4147 else 4148 given |= 0xf2000000; 4149 } 4150 else if ((given & 0xff000000) == 0xf9000000) 4151 given ^= 0xf9000000 ^ 0xf4000000; 4152 else 4153 return FALSE; 4154 } 4155 4156 for (insn = neon_opcodes; insn->assembler; insn++) 4157 { 4158 if ((given & insn->mask) == insn->value) 4159 { 4160 signed long value_in_comment = 0; 4161 bfd_boolean is_unpredictable = FALSE; 4162 const char *c; 4163 4164 for (c = insn->assembler; *c; c++) 4165 { 4166 if (*c == '%') 4167 { 4168 switch (*++c) 4169 { 4170 case '%': 4171 func (stream, "%%"); 4172 break; 4173 4174 case 'u': 4175 if (thumb && ifthen_state) 4176 is_unpredictable = TRUE; 4177 4178 /* Fall through. */ 4179 case 'c': 4180 if (thumb && ifthen_state) 4181 func (stream, "%s", arm_conditional[IFTHEN_COND]); 4182 break; 4183 4184 case 'A': 4185 { 4186 static const unsigned char enc[16] = 4187 { 4188 0x4, 0x14, /* st4 0,1 */ 4189 0x4, /* st1 2 */ 4190 0x4, /* st2 3 */ 4191 0x3, /* st3 4 */ 4192 0x13, /* st3 5 */ 4193 0x3, /* st1 6 */ 4194 0x1, /* st1 7 */ 4195 0x2, /* st2 8 */ 4196 0x12, /* st2 9 */ 4197 0x2, /* st1 10 */ 4198 0, 0, 0, 0, 0 4199 }; 4200 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4201 int rn = ((given >> 16) & 0xf); 4202 int rm = ((given >> 0) & 0xf); 4203 int align = ((given >> 4) & 0x3); 4204 int type = ((given >> 8) & 0xf); 4205 int n = enc[type] & 0xf; 4206 int stride = (enc[type] >> 4) + 1; 4207 int ix; 4208 4209 func (stream, "{"); 4210 if (stride > 1) 4211 for (ix = 0; ix != n; ix++) 4212 func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 4213 else if (n == 1) 4214 func (stream, "d%d", rd); 4215 else 4216 func (stream, "d%d-d%d", rd, rd + n - 1); 4217 func (stream, "}, [%s", arm_regnames[rn]); 4218 if (align) 4219 func (stream, " :%d", 32 << align); 4220 func (stream, "]"); 4221 if (rm == 0xd) 4222 func (stream, "!"); 4223 else if (rm != 0xf) 4224 func (stream, ", %s", arm_regnames[rm]); 4225 } 4226 break; 4227 4228 case 'B': 4229 { 4230 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4231 int rn = ((given >> 16) & 0xf); 4232 int rm = ((given >> 0) & 0xf); 4233 int idx_align = ((given >> 4) & 0xf); 4234 int align = 0; 4235 int size = ((given >> 10) & 0x3); 4236 int idx = idx_align >> (size + 1); 4237 int length = ((given >> 8) & 3) + 1; 4238 int stride = 1; 4239 int i; 4240 4241 if (length > 1 && size > 0) 4242 stride = (idx_align & (1 << size)) ? 2 : 1; 4243 4244 switch (length) 4245 { 4246 case 1: 4247 { 4248 int amask = (1 << size) - 1; 4249 if ((idx_align & (1 << size)) != 0) 4250 return FALSE; 4251 if (size > 0) 4252 { 4253 if ((idx_align & amask) == amask) 4254 align = 8 << size; 4255 else if ((idx_align & amask) != 0) 4256 return FALSE; 4257 } 4258 } 4259 break; 4260 4261 case 2: 4262 if (size == 2 && (idx_align & 2) != 0) 4263 return FALSE; 4264 align = (idx_align & 1) ? 16 << size : 0; 4265 break; 4266 4267 case 3: 4268 if ((size == 2 && (idx_align & 3) != 0) 4269 || (idx_align & 1) != 0) 4270 return FALSE; 4271 break; 4272 4273 case 4: 4274 if (size == 2) 4275 { 4276 if ((idx_align & 3) == 3) 4277 return FALSE; 4278 align = (idx_align & 3) * 64; 4279 } 4280 else 4281 align = (idx_align & 1) ? 32 << size : 0; 4282 break; 4283 4284 default: 4285 abort (); 4286 } 4287 4288 func (stream, "{"); 4289 for (i = 0; i < length; i++) 4290 func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 4291 rd + i * stride, idx); 4292 func (stream, "}, [%s", arm_regnames[rn]); 4293 if (align) 4294 func (stream, " :%d", align); 4295 func (stream, "]"); 4296 if (rm == 0xd) 4297 func (stream, "!"); 4298 else if (rm != 0xf) 4299 func (stream, ", %s", arm_regnames[rm]); 4300 } 4301 break; 4302 4303 case 'C': 4304 { 4305 int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 4306 int rn = ((given >> 16) & 0xf); 4307 int rm = ((given >> 0) & 0xf); 4308 int align = ((given >> 4) & 0x1); 4309 int size = ((given >> 6) & 0x3); 4310 int type = ((given >> 8) & 0x3); 4311 int n = type + 1; 4312 int stride = ((given >> 5) & 0x1); 4313 int ix; 4314 4315 if (stride && (n == 1)) 4316 n++; 4317 else 4318 stride++; 4319 4320 func (stream, "{"); 4321 if (stride > 1) 4322 for (ix = 0; ix != n; ix++) 4323 func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 4324 else if (n == 1) 4325 func (stream, "d%d[]", rd); 4326 else 4327 func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 4328 func (stream, "}, [%s", arm_regnames[rn]); 4329 if (align) 4330 { 4331 align = (8 * (type + 1)) << size; 4332 if (type == 3) 4333 align = (size > 1) ? align >> 1 : align; 4334 if (type == 2 || (type == 0 && !size)) 4335 func (stream, " :<bad align %d>", align); 4336 else 4337 func (stream, " :%d", align); 4338 } 4339 func (stream, "]"); 4340 if (rm == 0xd) 4341 func (stream, "!"); 4342 else if (rm != 0xf) 4343 func (stream, ", %s", arm_regnames[rm]); 4344 } 4345 break; 4346 4347 case 'D': 4348 { 4349 int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 4350 int size = (given >> 20) & 3; 4351 int reg = raw_reg & ((4 << size) - 1); 4352 int ix = raw_reg >> size >> 2; 4353 4354 func (stream, "d%d[%d]", reg, ix); 4355 } 4356 break; 4357 4358 case 'E': 4359 /* Neon encoded constant for mov, mvn, vorr, vbic. */ 4360 { 4361 int bits = 0; 4362 int cmode = (given >> 8) & 0xf; 4363 int op = (given >> 5) & 0x1; 4364 unsigned long value = 0, hival = 0; 4365 unsigned shift; 4366 int size = 0; 4367 int isfloat = 0; 4368 4369 bits |= ((given >> 24) & 1) << 7; 4370 bits |= ((given >> 16) & 7) << 4; 4371 bits |= ((given >> 0) & 15) << 0; 4372 4373 if (cmode < 8) 4374 { 4375 shift = (cmode >> 1) & 3; 4376 value = (unsigned long) bits << (8 * shift); 4377 size = 32; 4378 } 4379 else if (cmode < 12) 4380 { 4381 shift = (cmode >> 1) & 1; 4382 value = (unsigned long) bits << (8 * shift); 4383 size = 16; 4384 } 4385 else if (cmode < 14) 4386 { 4387 shift = (cmode & 1) + 1; 4388 value = (unsigned long) bits << (8 * shift); 4389 value |= (1ul << (8 * shift)) - 1; 4390 size = 32; 4391 } 4392 else if (cmode == 14) 4393 { 4394 if (op) 4395 { 4396 /* Bit replication into bytes. */ 4397 int ix; 4398 unsigned long mask; 4399 4400 value = 0; 4401 hival = 0; 4402 for (ix = 7; ix >= 0; ix--) 4403 { 4404 mask = ((bits >> ix) & 1) ? 0xff : 0; 4405 if (ix <= 3) 4406 value = (value << 8) | mask; 4407 else 4408 hival = (hival << 8) | mask; 4409 } 4410 size = 64; 4411 } 4412 else 4413 { 4414 /* Byte replication. */ 4415 value = (unsigned long) bits; 4416 size = 8; 4417 } 4418 } 4419 else if (!op) 4420 { 4421 /* Floating point encoding. */ 4422 int tmp; 4423 4424 value = (unsigned long) (bits & 0x7f) << 19; 4425 value |= (unsigned long) (bits & 0x80) << 24; 4426 tmp = bits & 0x40 ? 0x3c : 0x40; 4427 value |= (unsigned long) tmp << 24; 4428 size = 32; 4429 isfloat = 1; 4430 } 4431 else 4432 { 4433 func (stream, "<illegal constant %.8x:%x:%x>", 4434 bits, cmode, op); 4435 size = 32; 4436 break; 4437 } 4438 switch (size) 4439 { 4440 case 8: 4441 func (stream, "#%ld\t; 0x%.2lx", value, value); 4442 break; 4443 4444 case 16: 4445 func (stream, "#%ld\t; 0x%.4lx", value, value); 4446 break; 4447 4448 case 32: 4449 if (isfloat) 4450 { 4451 unsigned char valbytes[4]; 4452 double fvalue; 4453 4454 /* Do this a byte at a time so we don't have to 4455 worry about the host's endianness. */ 4456 valbytes[0] = value & 0xff; 4457 valbytes[1] = (value >> 8) & 0xff; 4458 valbytes[2] = (value >> 16) & 0xff; 4459 valbytes[3] = (value >> 24) & 0xff; 4460 4461 floatformat_to_double 4462 (& floatformat_ieee_single_little, valbytes, 4463 & fvalue); 4464 4465 func (stream, "#%.7g\t; 0x%.8lx", fvalue, 4466 value); 4467 } 4468 else 4469 func (stream, "#%ld\t; 0x%.8lx", 4470 (long) (((value & 0x80000000L) != 0) 4471 ? value | ~0xffffffffL : value), 4472 value); 4473 break; 4474 4475 case 64: 4476 func (stream, "#0x%.8lx%.8lx", hival, value); 4477 break; 4478 4479 default: 4480 abort (); 4481 } 4482 } 4483 break; 4484 4485 case 'F': 4486 { 4487 int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 4488 int num = (given >> 8) & 0x3; 4489 4490 if (!num) 4491 func (stream, "{d%d}", regno); 4492 else if (num + regno >= 32) 4493 func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 4494 else 4495 func (stream, "{d%d-d%d}", regno, regno + num); 4496 } 4497 break; 4498 4499 4500 case '0': case '1': case '2': case '3': case '4': 4501 case '5': case '6': case '7': case '8': case '9': 4502 { 4503 int width; 4504 unsigned long value; 4505 4506 c = arm_decode_bitfield (c, given, &value, &width); 4507 4508 switch (*c) 4509 { 4510 case 'r': 4511 func (stream, "%s", arm_regnames[value]); 4512 break; 4513 case 'd': 4514 func (stream, "%ld", value); 4515 value_in_comment = value; 4516 break; 4517 case 'e': 4518 func (stream, "%ld", (1ul << width) - value); 4519 break; 4520 4521 case 'S': 4522 case 'T': 4523 case 'U': 4524 /* Various width encodings. */ 4525 { 4526 int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 4527 int limit; 4528 unsigned low, high; 4529 4530 c++; 4531 if (*c >= '0' && *c <= '9') 4532 limit = *c - '0'; 4533 else if (*c >= 'a' && *c <= 'f') 4534 limit = *c - 'a' + 10; 4535 else 4536 abort (); 4537 low = limit >> 2; 4538 high = limit & 3; 4539 4540 if (value < low || value > high) 4541 func (stream, "<illegal width %d>", base << value); 4542 else 4543 func (stream, "%d", base << value); 4544 } 4545 break; 4546 case 'R': 4547 if (given & (1 << 6)) 4548 goto Q; 4549 /* FALLTHROUGH */ 4550 case 'D': 4551 func (stream, "d%ld", value); 4552 break; 4553 case 'Q': 4554 Q: 4555 if (value & 1) 4556 func (stream, "<illegal reg q%ld.5>", value >> 1); 4557 else 4558 func (stream, "q%ld", value >> 1); 4559 break; 4560 4561 case '`': 4562 c++; 4563 if (value == 0) 4564 func (stream, "%c", *c); 4565 break; 4566 case '\'': 4567 c++; 4568 if (value == ((1ul << width) - 1)) 4569 func (stream, "%c", *c); 4570 break; 4571 case '?': 4572 func (stream, "%c", c[(1 << width) - (int) value]); 4573 c += 1 << width; 4574 break; 4575 default: 4576 abort (); 4577 } 4578 break; 4579 4580 default: 4581 abort (); 4582 } 4583 } 4584 } 4585 else 4586 func (stream, "%c", *c); 4587 } 4588 4589 if (value_in_comment > 32 || value_in_comment < -16) 4590 func (stream, "\t; 0x%lx", value_in_comment); 4591 4592 if (is_unpredictable) 4593 func (stream, UNPREDICTABLE_INSTRUCTION); 4594 4595 return TRUE; 4596 } 4597 } 4598 return FALSE; 4599 } 4600 4601 /* Return the name of a v7A special register. */ 4602 4603 static const char * 4604 banked_regname (unsigned reg) 4605 { 4606 switch (reg) 4607 { 4608 case 15: return "CPSR"; 4609 case 32: return "R8_usr"; 4610 case 33: return "R9_usr"; 4611 case 34: return "R10_usr"; 4612 case 35: return "R11_usr"; 4613 case 36: return "R12_usr"; 4614 case 37: return "SP_usr"; 4615 case 38: return "LR_usr"; 4616 case 40: return "R8_fiq"; 4617 case 41: return "R9_fiq"; 4618 case 42: return "R10_fiq"; 4619 case 43: return "R11_fiq"; 4620 case 44: return "R12_fiq"; 4621 case 45: return "SP_fiq"; 4622 case 46: return "LR_fiq"; 4623 case 48: return "LR_irq"; 4624 case 49: return "SP_irq"; 4625 case 50: return "LR_svc"; 4626 case 51: return "SP_svc"; 4627 case 52: return "LR_abt"; 4628 case 53: return "SP_abt"; 4629 case 54: return "LR_und"; 4630 case 55: return "SP_und"; 4631 case 60: return "LR_mon"; 4632 case 61: return "SP_mon"; 4633 case 62: return "ELR_hyp"; 4634 case 63: return "SP_hyp"; 4635 case 79: return "SPSR"; 4636 case 110: return "SPSR_fiq"; 4637 case 112: return "SPSR_irq"; 4638 case 114: return "SPSR_svc"; 4639 case 116: return "SPSR_abt"; 4640 case 118: return "SPSR_und"; 4641 case 124: return "SPSR_mon"; 4642 case 126: return "SPSR_hyp"; 4643 default: return NULL; 4644 } 4645 } 4646 4647 /* Return the name of the DMB/DSB option. */ 4648 static const char * 4649 data_barrier_option (unsigned option) 4650 { 4651 switch (option & 0xf) 4652 { 4653 case 0xf: return "sy"; 4654 case 0xe: return "st"; 4655 case 0xd: return "ld"; 4656 case 0xb: return "ish"; 4657 case 0xa: return "ishst"; 4658 case 0x9: return "ishld"; 4659 case 0x7: return "un"; 4660 case 0x6: return "unst"; 4661 case 0x5: return "nshld"; 4662 case 0x3: return "osh"; 4663 case 0x2: return "oshst"; 4664 case 0x1: return "oshld"; 4665 default: return NULL; 4666 } 4667 } 4668 4669 /* Print one ARM instruction from PC on INFO->STREAM. */ 4670 4671 static void 4672 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 4673 { 4674 const struct opcode32 *insn; 4675 void *stream = info->stream; 4676 fprintf_ftype func = info->fprintf_func; 4677 struct arm_private_data *private_data = info->private_data; 4678 4679 if (print_insn_coprocessor (pc, info, given, FALSE)) 4680 return; 4681 4682 if (print_insn_neon (info, given, FALSE)) 4683 return; 4684 4685 for (insn = arm_opcodes; insn->assembler; insn++) 4686 { 4687 if ((given & insn->mask) != insn->value) 4688 continue; 4689 4690 if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features)) 4691 continue; 4692 4693 /* Special case: an instruction with all bits set in the condition field 4694 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 4695 or by the catchall at the end of the table. */ 4696 if ((given & 0xF0000000) != 0xF0000000 4697 || (insn->mask & 0xF0000000) == 0xF0000000 4698 || (insn->mask == 0 && insn->value == 0)) 4699 { 4700 unsigned long u_reg = 16; 4701 unsigned long U_reg = 16; 4702 bfd_boolean is_unpredictable = FALSE; 4703 signed long value_in_comment = 0; 4704 const char *c; 4705 4706 for (c = insn->assembler; *c; c++) 4707 { 4708 if (*c == '%') 4709 { 4710 bfd_boolean allow_unpredictable = FALSE; 4711 4712 switch (*++c) 4713 { 4714 case '%': 4715 func (stream, "%%"); 4716 break; 4717 4718 case 'a': 4719 value_in_comment = print_arm_address (pc, info, given); 4720 break; 4721 4722 case 'P': 4723 /* Set P address bit and use normal address 4724 printing routine. */ 4725 value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT)); 4726 break; 4727 4728 case 'S': 4729 allow_unpredictable = TRUE; 4730 /* Fall through. */ 4731 case 's': 4732 if ((given & 0x004f0000) == 0x004f0000) 4733 { 4734 /* PC relative with immediate offset. */ 4735 bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf); 4736 4737 if (PRE_BIT_SET) 4738 { 4739 /* Elide positive zero offset. */ 4740 if (offset || NEGATIVE_BIT_SET) 4741 func (stream, "[pc, #%s%d]\t; ", 4742 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4743 else 4744 func (stream, "[pc]\t; "); 4745 if (NEGATIVE_BIT_SET) 4746 offset = -offset; 4747 info->print_address_func (offset + pc + 8, info); 4748 } 4749 else 4750 { 4751 /* Always show the offset. */ 4752 func (stream, "[pc], #%s%d", 4753 NEGATIVE_BIT_SET ? "-" : "", (int) offset); 4754 if (! allow_unpredictable) 4755 is_unpredictable = TRUE; 4756 } 4757 } 4758 else 4759 { 4760 int offset = ((given & 0xf00) >> 4) | (given & 0xf); 4761 4762 func (stream, "[%s", 4763 arm_regnames[(given >> 16) & 0xf]); 4764 4765 if (PRE_BIT_SET) 4766 { 4767 if (IMMEDIATE_BIT_SET) 4768 { 4769 /* Elide offset for non-writeback 4770 positive zero. */ 4771 if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET 4772 || offset) 4773 func (stream, ", #%s%d", 4774 NEGATIVE_BIT_SET ? "-" : "", offset); 4775 4776 if (NEGATIVE_BIT_SET) 4777 offset = -offset; 4778 4779 value_in_comment = offset; 4780 } 4781 else 4782 { 4783 /* Register Offset or Register Pre-Indexed. */ 4784 func (stream, ", %s%s", 4785 NEGATIVE_BIT_SET ? "-" : "", 4786 arm_regnames[given & 0xf]); 4787 4788 /* Writing back to the register that is the source/ 4789 destination of the load/store is unpredictable. */ 4790 if (! allow_unpredictable 4791 && WRITEBACK_BIT_SET 4792 && ((given & 0xf) == ((given >> 12) & 0xf))) 4793 is_unpredictable = TRUE; 4794 } 4795 4796 func (stream, "]%s", 4797 WRITEBACK_BIT_SET ? "!" : ""); 4798 } 4799 else 4800 { 4801 if (IMMEDIATE_BIT_SET) 4802 { 4803 /* Immediate Post-indexed. */ 4804 /* PR 10924: Offset must be printed, even if it is zero. */ 4805 func (stream, "], #%s%d", 4806 NEGATIVE_BIT_SET ? "-" : "", offset); 4807 if (NEGATIVE_BIT_SET) 4808 offset = -offset; 4809 value_in_comment = offset; 4810 } 4811 else 4812 { 4813 /* Register Post-indexed. */ 4814 func (stream, "], %s%s", 4815 NEGATIVE_BIT_SET ? "-" : "", 4816 arm_regnames[given & 0xf]); 4817 4818 /* Writing back to the register that is the source/ 4819 destination of the load/store is unpredictable. */ 4820 if (! allow_unpredictable 4821 && (given & 0xf) == ((given >> 12) & 0xf)) 4822 is_unpredictable = TRUE; 4823 } 4824 4825 if (! allow_unpredictable) 4826 { 4827 /* Writeback is automatically implied by post- addressing. 4828 Setting the W bit is unnecessary and ARM specify it as 4829 being unpredictable. */ 4830 if (WRITEBACK_BIT_SET 4831 /* Specifying the PC register as the post-indexed 4832 registers is also unpredictable. */ 4833 || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf))) 4834 is_unpredictable = TRUE; 4835 } 4836 } 4837 } 4838 break; 4839 4840 case 'b': 4841 { 4842 bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 4843 info->print_address_func (disp * 4 + pc + 8, info); 4844 } 4845 break; 4846 4847 case 'c': 4848 if (((given >> 28) & 0xf) != 0xe) 4849 func (stream, "%s", 4850 arm_conditional [(given >> 28) & 0xf]); 4851 break; 4852 4853 case 'm': 4854 { 4855 int started = 0; 4856 int reg; 4857 4858 func (stream, "{"); 4859 for (reg = 0; reg < 16; reg++) 4860 if ((given & (1 << reg)) != 0) 4861 { 4862 if (started) 4863 func (stream, ", "); 4864 started = 1; 4865 func (stream, "%s", arm_regnames[reg]); 4866 } 4867 func (stream, "}"); 4868 if (! started) 4869 is_unpredictable = TRUE; 4870 } 4871 break; 4872 4873 case 'q': 4874 arm_decode_shift (given, func, stream, FALSE); 4875 break; 4876 4877 case 'o': 4878 if ((given & 0x02000000) != 0) 4879 { 4880 unsigned int rotate = (given & 0xf00) >> 7; 4881 unsigned int immed = (given & 0xff); 4882 unsigned int a, i; 4883 4884 a = (((immed << (32 - rotate)) 4885 | (immed >> rotate)) & 0xffffffff); 4886 /* If there is another encoding with smaller rotate, 4887 the rotate should be specified directly. */ 4888 for (i = 0; i < 32; i += 2) 4889 if ((a << i | a >> (32 - i)) <= 0xff) 4890 break; 4891 4892 if (i != rotate) 4893 func (stream, "#%d, %d", immed, rotate); 4894 else 4895 func (stream, "#%d", a); 4896 value_in_comment = a; 4897 } 4898 else 4899 arm_decode_shift (given, func, stream, TRUE); 4900 break; 4901 4902 case 'p': 4903 if ((given & 0x0000f000) == 0x0000f000) 4904 { 4905 arm_feature_set arm_ext_v6 = 4906 ARM_FEATURE_CORE_LOW (ARM_EXT_V6); 4907 4908 /* The p-variants of tst/cmp/cmn/teq are the pre-V6 4909 mechanism for setting PSR flag bits. They are 4910 obsolete in V6 onwards. */ 4911 if (! ARM_CPU_HAS_FEATURE (private_data->features, \ 4912 arm_ext_v6)) 4913 func (stream, "p"); 4914 else 4915 is_unpredictable = TRUE; 4916 } 4917 break; 4918 4919 case 't': 4920 if ((given & 0x01200000) == 0x00200000) 4921 func (stream, "t"); 4922 break; 4923 4924 case 'A': 4925 { 4926 int offset = given & 0xff; 4927 4928 value_in_comment = offset * 4; 4929 if (NEGATIVE_BIT_SET) 4930 value_in_comment = - value_in_comment; 4931 4932 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 4933 4934 if (PRE_BIT_SET) 4935 { 4936 if (offset) 4937 func (stream, ", #%d]%s", 4938 (int) value_in_comment, 4939 WRITEBACK_BIT_SET ? "!" : ""); 4940 else 4941 func (stream, "]"); 4942 } 4943 else 4944 { 4945 func (stream, "]"); 4946 4947 if (WRITEBACK_BIT_SET) 4948 { 4949 if (offset) 4950 func (stream, ", #%d", (int) value_in_comment); 4951 } 4952 else 4953 { 4954 func (stream, ", {%d}", (int) offset); 4955 value_in_comment = offset; 4956 } 4957 } 4958 } 4959 break; 4960 4961 case 'B': 4962 /* Print ARM V5 BLX(1) address: pc+25 bits. */ 4963 { 4964 bfd_vma address; 4965 bfd_vma offset = 0; 4966 4967 if (! NEGATIVE_BIT_SET) 4968 /* Is signed, hi bits should be ones. */ 4969 offset = (-1) ^ 0x00ffffff; 4970 4971 /* Offset is (SignExtend(offset field)<<2). */ 4972 offset += given & 0x00ffffff; 4973 offset <<= 2; 4974 address = offset + pc + 8; 4975 4976 if (given & 0x01000000) 4977 /* H bit allows addressing to 2-byte boundaries. */ 4978 address += 2; 4979 4980 info->print_address_func (address, info); 4981 } 4982 break; 4983 4984 case 'C': 4985 if ((given & 0x02000200) == 0x200) 4986 { 4987 const char * name; 4988 unsigned sysm = (given & 0x004f0000) >> 16; 4989 4990 sysm |= (given & 0x300) >> 4; 4991 name = banked_regname (sysm); 4992 4993 if (name != NULL) 4994 func (stream, "%s", name); 4995 else 4996 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 4997 } 4998 else 4999 { 5000 func (stream, "%cPSR_", 5001 (given & 0x00400000) ? 'S' : 'C'); 5002 if (given & 0x80000) 5003 func (stream, "f"); 5004 if (given & 0x40000) 5005 func (stream, "s"); 5006 if (given & 0x20000) 5007 func (stream, "x"); 5008 if (given & 0x10000) 5009 func (stream, "c"); 5010 } 5011 break; 5012 5013 case 'U': 5014 if ((given & 0xf0) == 0x60) 5015 { 5016 switch (given & 0xf) 5017 { 5018 case 0xf: func (stream, "sy"); break; 5019 default: 5020 func (stream, "#%d", (int) given & 0xf); 5021 break; 5022 } 5023 } 5024 else 5025 { 5026 const char * opt = data_barrier_option (given & 0xf); 5027 if (opt != NULL) 5028 func (stream, "%s", opt); 5029 else 5030 func (stream, "#%d", (int) given & 0xf); 5031 } 5032 break; 5033 5034 case '0': case '1': case '2': case '3': case '4': 5035 case '5': case '6': case '7': case '8': case '9': 5036 { 5037 int width; 5038 unsigned long value; 5039 5040 c = arm_decode_bitfield (c, given, &value, &width); 5041 5042 switch (*c) 5043 { 5044 case 'R': 5045 if (value == 15) 5046 is_unpredictable = TRUE; 5047 /* Fall through. */ 5048 case 'r': 5049 case 'T': 5050 /* We want register + 1 when decoding T. */ 5051 if (*c == 'T') 5052 ++value; 5053 5054 if (c[1] == 'u') 5055 { 5056 /* Eat the 'u' character. */ 5057 ++ c; 5058 5059 if (u_reg == value) 5060 is_unpredictable = TRUE; 5061 u_reg = value; 5062 } 5063 if (c[1] == 'U') 5064 { 5065 /* Eat the 'U' character. */ 5066 ++ c; 5067 5068 if (U_reg == value) 5069 is_unpredictable = TRUE; 5070 U_reg = value; 5071 } 5072 func (stream, "%s", arm_regnames[value]); 5073 break; 5074 case 'd': 5075 func (stream, "%ld", value); 5076 value_in_comment = value; 5077 break; 5078 case 'b': 5079 func (stream, "%ld", value * 8); 5080 value_in_comment = value * 8; 5081 break; 5082 case 'W': 5083 func (stream, "%ld", value + 1); 5084 value_in_comment = value + 1; 5085 break; 5086 case 'x': 5087 func (stream, "0x%08lx", value); 5088 5089 /* Some SWI instructions have special 5090 meanings. */ 5091 if ((given & 0x0fffffff) == 0x0FF00000) 5092 func (stream, "\t; IMB"); 5093 else if ((given & 0x0fffffff) == 0x0FF00001) 5094 func (stream, "\t; IMBRange"); 5095 break; 5096 case 'X': 5097 func (stream, "%01lx", value & 0xf); 5098 value_in_comment = value; 5099 break; 5100 case '`': 5101 c++; 5102 if (value == 0) 5103 func (stream, "%c", *c); 5104 break; 5105 case '\'': 5106 c++; 5107 if (value == ((1ul << width) - 1)) 5108 func (stream, "%c", *c); 5109 break; 5110 case '?': 5111 func (stream, "%c", c[(1 << width) - (int) value]); 5112 c += 1 << width; 5113 break; 5114 default: 5115 abort (); 5116 } 5117 break; 5118 5119 case 'e': 5120 { 5121 int imm; 5122 5123 imm = (given & 0xf) | ((given & 0xfff00) >> 4); 5124 func (stream, "%d", imm); 5125 value_in_comment = imm; 5126 } 5127 break; 5128 5129 case 'E': 5130 /* LSB and WIDTH fields of BFI or BFC. The machine- 5131 language instruction encodes LSB and MSB. */ 5132 { 5133 long msb = (given & 0x001f0000) >> 16; 5134 long lsb = (given & 0x00000f80) >> 7; 5135 long w = msb - lsb + 1; 5136 5137 if (w > 0) 5138 func (stream, "#%lu, #%lu", lsb, w); 5139 else 5140 func (stream, "(invalid: %lu:%lu)", lsb, msb); 5141 } 5142 break; 5143 5144 case 'R': 5145 /* Get the PSR/banked register name. */ 5146 { 5147 const char * name; 5148 unsigned sysm = (given & 0x004f0000) >> 16; 5149 5150 sysm |= (given & 0x300) >> 4; 5151 name = banked_regname (sysm); 5152 5153 if (name != NULL) 5154 func (stream, "%s", name); 5155 else 5156 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5157 } 5158 break; 5159 5160 case 'V': 5161 /* 16-bit unsigned immediate from a MOVT or MOVW 5162 instruction, encoded in bits 0:11 and 15:19. */ 5163 { 5164 long hi = (given & 0x000f0000) >> 4; 5165 long lo = (given & 0x00000fff); 5166 long imm16 = hi | lo; 5167 5168 func (stream, "#%lu", imm16); 5169 value_in_comment = imm16; 5170 } 5171 break; 5172 5173 default: 5174 abort (); 5175 } 5176 } 5177 } 5178 else 5179 func (stream, "%c", *c); 5180 } 5181 5182 if (value_in_comment > 32 || value_in_comment < -16) 5183 func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL)); 5184 5185 if (is_unpredictable) 5186 func (stream, UNPREDICTABLE_INSTRUCTION); 5187 5188 return; 5189 } 5190 } 5191 abort (); 5192 } 5193 5194 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 5195 5196 static void 5197 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 5198 { 5199 const struct opcode16 *insn; 5200 void *stream = info->stream; 5201 fprintf_ftype func = info->fprintf_func; 5202 5203 for (insn = thumb_opcodes; insn->assembler; insn++) 5204 if ((given & insn->mask) == insn->value) 5205 { 5206 signed long value_in_comment = 0; 5207 const char *c = insn->assembler; 5208 5209 for (; *c; c++) 5210 { 5211 int domaskpc = 0; 5212 int domasklr = 0; 5213 5214 if (*c != '%') 5215 { 5216 func (stream, "%c", *c); 5217 continue; 5218 } 5219 5220 switch (*++c) 5221 { 5222 case '%': 5223 func (stream, "%%"); 5224 break; 5225 5226 case 'c': 5227 if (ifthen_state) 5228 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5229 break; 5230 5231 case 'C': 5232 if (ifthen_state) 5233 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5234 else 5235 func (stream, "s"); 5236 break; 5237 5238 case 'I': 5239 { 5240 unsigned int tmp; 5241 5242 ifthen_next_state = given & 0xff; 5243 for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 5244 func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 5245 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 5246 } 5247 break; 5248 5249 case 'x': 5250 if (ifthen_next_state) 5251 func (stream, "\t; unpredictable branch in IT block\n"); 5252 break; 5253 5254 case 'X': 5255 if (ifthen_state) 5256 func (stream, "\t; unpredictable <IT:%s>", 5257 arm_conditional[IFTHEN_COND]); 5258 break; 5259 5260 case 'S': 5261 { 5262 long reg; 5263 5264 reg = (given >> 3) & 0x7; 5265 if (given & (1 << 6)) 5266 reg += 8; 5267 5268 func (stream, "%s", arm_regnames[reg]); 5269 } 5270 break; 5271 5272 case 'D': 5273 { 5274 long reg; 5275 5276 reg = given & 0x7; 5277 if (given & (1 << 7)) 5278 reg += 8; 5279 5280 func (stream, "%s", arm_regnames[reg]); 5281 } 5282 break; 5283 5284 case 'N': 5285 if (given & (1 << 8)) 5286 domasklr = 1; 5287 /* Fall through. */ 5288 case 'O': 5289 if (*c == 'O' && (given & (1 << 8))) 5290 domaskpc = 1; 5291 /* Fall through. */ 5292 case 'M': 5293 { 5294 int started = 0; 5295 int reg; 5296 5297 func (stream, "{"); 5298 5299 /* It would be nice if we could spot 5300 ranges, and generate the rS-rE format: */ 5301 for (reg = 0; (reg < 8); reg++) 5302 if ((given & (1 << reg)) != 0) 5303 { 5304 if (started) 5305 func (stream, ", "); 5306 started = 1; 5307 func (stream, "%s", arm_regnames[reg]); 5308 } 5309 5310 if (domasklr) 5311 { 5312 if (started) 5313 func (stream, ", "); 5314 started = 1; 5315 func (stream, "%s", arm_regnames[14] /* "lr" */); 5316 } 5317 5318 if (domaskpc) 5319 { 5320 if (started) 5321 func (stream, ", "); 5322 func (stream, "%s", arm_regnames[15] /* "pc" */); 5323 } 5324 5325 func (stream, "}"); 5326 } 5327 break; 5328 5329 case 'W': 5330 /* Print writeback indicator for a LDMIA. We are doing a 5331 writeback if the base register is not in the register 5332 mask. */ 5333 if ((given & (1 << ((given & 0x0700) >> 8))) == 0) 5334 func (stream, "!"); 5335 break; 5336 5337 case 'b': 5338 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 5339 { 5340 bfd_vma address = (pc + 4 5341 + ((given & 0x00f8) >> 2) 5342 + ((given & 0x0200) >> 3)); 5343 info->print_address_func (address, info); 5344 } 5345 break; 5346 5347 case 's': 5348 /* Right shift immediate -- bits 6..10; 1-31 print 5349 as themselves, 0 prints as 32. */ 5350 { 5351 long imm = (given & 0x07c0) >> 6; 5352 if (imm == 0) 5353 imm = 32; 5354 func (stream, "#%ld", imm); 5355 } 5356 break; 5357 5358 case '0': case '1': case '2': case '3': case '4': 5359 case '5': case '6': case '7': case '8': case '9': 5360 { 5361 int bitstart = *c++ - '0'; 5362 int bitend = 0; 5363 5364 while (*c >= '0' && *c <= '9') 5365 bitstart = (bitstart * 10) + *c++ - '0'; 5366 5367 switch (*c) 5368 { 5369 case '-': 5370 { 5371 bfd_vma reg; 5372 5373 c++; 5374 while (*c >= '0' && *c <= '9') 5375 bitend = (bitend * 10) + *c++ - '0'; 5376 if (!bitend) 5377 abort (); 5378 reg = given >> bitstart; 5379 reg &= (2 << (bitend - bitstart)) - 1; 5380 5381 switch (*c) 5382 { 5383 case 'r': 5384 func (stream, "%s", arm_regnames[reg]); 5385 break; 5386 5387 case 'd': 5388 func (stream, "%ld", (long) reg); 5389 value_in_comment = reg; 5390 break; 5391 5392 case 'H': 5393 func (stream, "%ld", (long) (reg << 1)); 5394 value_in_comment = reg << 1; 5395 break; 5396 5397 case 'W': 5398 func (stream, "%ld", (long) (reg << 2)); 5399 value_in_comment = reg << 2; 5400 break; 5401 5402 case 'a': 5403 /* PC-relative address -- the bottom two 5404 bits of the address are dropped 5405 before the calculation. */ 5406 info->print_address_func 5407 (((pc + 4) & ~3) + (reg << 2), info); 5408 value_in_comment = 0; 5409 break; 5410 5411 case 'x': 5412 func (stream, "0x%04lx", (long) reg); 5413 break; 5414 5415 case 'B': 5416 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 5417 info->print_address_func (reg * 2 + pc + 4, info); 5418 value_in_comment = 0; 5419 break; 5420 5421 case 'c': 5422 func (stream, "%s", arm_conditional [reg]); 5423 break; 5424 5425 default: 5426 abort (); 5427 } 5428 } 5429 break; 5430 5431 case '\'': 5432 c++; 5433 if ((given & (1 << bitstart)) != 0) 5434 func (stream, "%c", *c); 5435 break; 5436 5437 case '?': 5438 ++c; 5439 if ((given & (1 << bitstart)) != 0) 5440 func (stream, "%c", *c++); 5441 else 5442 func (stream, "%c", *++c); 5443 break; 5444 5445 default: 5446 abort (); 5447 } 5448 } 5449 break; 5450 5451 default: 5452 abort (); 5453 } 5454 } 5455 5456 if (value_in_comment > 32 || value_in_comment < -16) 5457 func (stream, "\t; 0x%lx", value_in_comment); 5458 return; 5459 } 5460 5461 /* No match. */ 5462 abort (); 5463 } 5464 5465 /* Return the name of an V7M special register. */ 5466 5467 static const char * 5468 psr_name (int regno) 5469 { 5470 switch (regno) 5471 { 5472 case 0x0: return "APSR"; 5473 case 0x1: return "IAPSR"; 5474 case 0x2: return "EAPSR"; 5475 case 0x3: return "PSR"; 5476 case 0x5: return "IPSR"; 5477 case 0x6: return "EPSR"; 5478 case 0x7: return "IEPSR"; 5479 case 0x8: return "MSP"; 5480 case 0x9: return "PSP"; 5481 case 0xa: return "MSPLIM"; 5482 case 0xb: return "PSPLIM"; 5483 case 0x10: return "PRIMASK"; 5484 case 0x11: return "BASEPRI"; 5485 case 0x12: return "BASEPRI_MAX"; 5486 case 0x13: return "FAULTMASK"; 5487 case 0x14: return "CONTROL"; 5488 case 0x88: return "MSP_NS"; 5489 case 0x89: return "PSP_NS"; 5490 case 0x8a: return "MSPLIM_NS"; 5491 case 0x8b: return "PSPLIM_NS"; 5492 case 0x90: return "PRIMASK_NS"; 5493 case 0x91: return "BASEPRI_NS"; 5494 case 0x93: return "FAULTMASK_NS"; 5495 case 0x94: return "CONTROL_NS"; 5496 case 0x98: return "SP_NS"; 5497 default: return "<unknown>"; 5498 } 5499 } 5500 5501 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 5502 5503 static void 5504 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 5505 { 5506 const struct opcode32 *insn; 5507 void *stream = info->stream; 5508 fprintf_ftype func = info->fprintf_func; 5509 5510 if (print_insn_coprocessor (pc, info, given, TRUE)) 5511 return; 5512 5513 if (print_insn_neon (info, given, TRUE)) 5514 return; 5515 5516 for (insn = thumb32_opcodes; insn->assembler; insn++) 5517 if ((given & insn->mask) == insn->value) 5518 { 5519 bfd_boolean is_unpredictable = FALSE; 5520 signed long value_in_comment = 0; 5521 const char *c = insn->assembler; 5522 5523 for (; *c; c++) 5524 { 5525 if (*c != '%') 5526 { 5527 func (stream, "%c", *c); 5528 continue; 5529 } 5530 5531 switch (*++c) 5532 { 5533 case '%': 5534 func (stream, "%%"); 5535 break; 5536 5537 case 'c': 5538 if (ifthen_state) 5539 func (stream, "%s", arm_conditional[IFTHEN_COND]); 5540 break; 5541 5542 case 'x': 5543 if (ifthen_next_state) 5544 func (stream, "\t; unpredictable branch in IT block\n"); 5545 break; 5546 5547 case 'X': 5548 if (ifthen_state) 5549 func (stream, "\t; unpredictable <IT:%s>", 5550 arm_conditional[IFTHEN_COND]); 5551 break; 5552 5553 case 'I': 5554 { 5555 unsigned int imm12 = 0; 5556 5557 imm12 |= (given & 0x000000ffu); 5558 imm12 |= (given & 0x00007000u) >> 4; 5559 imm12 |= (given & 0x04000000u) >> 15; 5560 func (stream, "#%u", imm12); 5561 value_in_comment = imm12; 5562 } 5563 break; 5564 5565 case 'M': 5566 { 5567 unsigned int bits = 0, imm, imm8, mod; 5568 5569 bits |= (given & 0x000000ffu); 5570 bits |= (given & 0x00007000u) >> 4; 5571 bits |= (given & 0x04000000u) >> 15; 5572 imm8 = (bits & 0x0ff); 5573 mod = (bits & 0xf00) >> 8; 5574 switch (mod) 5575 { 5576 case 0: imm = imm8; break; 5577 case 1: imm = ((imm8 << 16) | imm8); break; 5578 case 2: imm = ((imm8 << 24) | (imm8 << 8)); break; 5579 case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 5580 default: 5581 mod = (bits & 0xf80) >> 7; 5582 imm8 = (bits & 0x07f) | 0x80; 5583 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 5584 } 5585 func (stream, "#%u", imm); 5586 value_in_comment = imm; 5587 } 5588 break; 5589 5590 case 'J': 5591 { 5592 unsigned int imm = 0; 5593 5594 imm |= (given & 0x000000ffu); 5595 imm |= (given & 0x00007000u) >> 4; 5596 imm |= (given & 0x04000000u) >> 15; 5597 imm |= (given & 0x000f0000u) >> 4; 5598 func (stream, "#%u", imm); 5599 value_in_comment = imm; 5600 } 5601 break; 5602 5603 case 'K': 5604 { 5605 unsigned int imm = 0; 5606 5607 imm |= (given & 0x000f0000u) >> 16; 5608 imm |= (given & 0x00000ff0u) >> 0; 5609 imm |= (given & 0x0000000fu) << 12; 5610 func (stream, "#%u", imm); 5611 value_in_comment = imm; 5612 } 5613 break; 5614 5615 case 'H': 5616 { 5617 unsigned int imm = 0; 5618 5619 imm |= (given & 0x000f0000u) >> 4; 5620 imm |= (given & 0x00000fffu) >> 0; 5621 func (stream, "#%u", imm); 5622 value_in_comment = imm; 5623 } 5624 break; 5625 5626 case 'V': 5627 { 5628 unsigned int imm = 0; 5629 5630 imm |= (given & 0x00000fffu); 5631 imm |= (given & 0x000f0000u) >> 4; 5632 func (stream, "#%u", imm); 5633 value_in_comment = imm; 5634 } 5635 break; 5636 5637 case 'S': 5638 { 5639 unsigned int reg = (given & 0x0000000fu); 5640 unsigned int stp = (given & 0x00000030u) >> 4; 5641 unsigned int imm = 0; 5642 imm |= (given & 0x000000c0u) >> 6; 5643 imm |= (given & 0x00007000u) >> 10; 5644 5645 func (stream, "%s", arm_regnames[reg]); 5646 switch (stp) 5647 { 5648 case 0: 5649 if (imm > 0) 5650 func (stream, ", lsl #%u", imm); 5651 break; 5652 5653 case 1: 5654 if (imm == 0) 5655 imm = 32; 5656 func (stream, ", lsr #%u", imm); 5657 break; 5658 5659 case 2: 5660 if (imm == 0) 5661 imm = 32; 5662 func (stream, ", asr #%u", imm); 5663 break; 5664 5665 case 3: 5666 if (imm == 0) 5667 func (stream, ", rrx"); 5668 else 5669 func (stream, ", ror #%u", imm); 5670 } 5671 } 5672 break; 5673 5674 case 'a': 5675 { 5676 unsigned int Rn = (given & 0x000f0000) >> 16; 5677 unsigned int U = ! NEGATIVE_BIT_SET; 5678 unsigned int op = (given & 0x00000f00) >> 8; 5679 unsigned int i12 = (given & 0x00000fff); 5680 unsigned int i8 = (given & 0x000000ff); 5681 bfd_boolean writeback = FALSE, postind = FALSE; 5682 bfd_vma offset = 0; 5683 5684 func (stream, "[%s", arm_regnames[Rn]); 5685 if (U) /* 12-bit positive immediate offset. */ 5686 { 5687 offset = i12; 5688 if (Rn != 15) 5689 value_in_comment = offset; 5690 } 5691 else if (Rn == 15) /* 12-bit negative immediate offset. */ 5692 offset = - (int) i12; 5693 else if (op == 0x0) /* Shifted register offset. */ 5694 { 5695 unsigned int Rm = (i8 & 0x0f); 5696 unsigned int sh = (i8 & 0x30) >> 4; 5697 5698 func (stream, ", %s", arm_regnames[Rm]); 5699 if (sh) 5700 func (stream, ", lsl #%u", sh); 5701 func (stream, "]"); 5702 break; 5703 } 5704 else switch (op) 5705 { 5706 case 0xE: /* 8-bit positive immediate offset. */ 5707 offset = i8; 5708 break; 5709 5710 case 0xC: /* 8-bit negative immediate offset. */ 5711 offset = -i8; 5712 break; 5713 5714 case 0xF: /* 8-bit + preindex with wb. */ 5715 offset = i8; 5716 writeback = TRUE; 5717 break; 5718 5719 case 0xD: /* 8-bit - preindex with wb. */ 5720 offset = -i8; 5721 writeback = TRUE; 5722 break; 5723 5724 case 0xB: /* 8-bit + postindex. */ 5725 offset = i8; 5726 postind = TRUE; 5727 break; 5728 5729 case 0x9: /* 8-bit - postindex. */ 5730 offset = -i8; 5731 postind = TRUE; 5732 break; 5733 5734 default: 5735 func (stream, ", <undefined>]"); 5736 goto skip; 5737 } 5738 5739 if (postind) 5740 func (stream, "], #%d", (int) offset); 5741 else 5742 { 5743 if (offset) 5744 func (stream, ", #%d", (int) offset); 5745 func (stream, writeback ? "]!" : "]"); 5746 } 5747 5748 if (Rn == 15) 5749 { 5750 func (stream, "\t; "); 5751 info->print_address_func (((pc + 4) & ~3) + offset, info); 5752 } 5753 } 5754 skip: 5755 break; 5756 5757 case 'A': 5758 { 5759 unsigned int U = ! NEGATIVE_BIT_SET; 5760 unsigned int W = WRITEBACK_BIT_SET; 5761 unsigned int Rn = (given & 0x000f0000) >> 16; 5762 unsigned int off = (given & 0x000000ff); 5763 5764 func (stream, "[%s", arm_regnames[Rn]); 5765 5766 if (PRE_BIT_SET) 5767 { 5768 if (off || !U) 5769 { 5770 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 5771 value_in_comment = off * 4 * (U ? 1 : -1); 5772 } 5773 func (stream, "]"); 5774 if (W) 5775 func (stream, "!"); 5776 } 5777 else 5778 { 5779 func (stream, "], "); 5780 if (W) 5781 { 5782 func (stream, "#%c%u", U ? '+' : '-', off * 4); 5783 value_in_comment = off * 4 * (U ? 1 : -1); 5784 } 5785 else 5786 { 5787 func (stream, "{%u}", off); 5788 value_in_comment = off; 5789 } 5790 } 5791 } 5792 break; 5793 5794 case 'w': 5795 { 5796 unsigned int Sbit = (given & 0x01000000) >> 24; 5797 unsigned int type = (given & 0x00600000) >> 21; 5798 5799 switch (type) 5800 { 5801 case 0: func (stream, Sbit ? "sb" : "b"); break; 5802 case 1: func (stream, Sbit ? "sh" : "h"); break; 5803 case 2: 5804 if (Sbit) 5805 func (stream, "??"); 5806 break; 5807 case 3: 5808 func (stream, "??"); 5809 break; 5810 } 5811 } 5812 break; 5813 5814 case 'm': 5815 { 5816 int started = 0; 5817 int reg; 5818 5819 func (stream, "{"); 5820 for (reg = 0; reg < 16; reg++) 5821 if ((given & (1 << reg)) != 0) 5822 { 5823 if (started) 5824 func (stream, ", "); 5825 started = 1; 5826 func (stream, "%s", arm_regnames[reg]); 5827 } 5828 func (stream, "}"); 5829 } 5830 break; 5831 5832 case 'E': 5833 { 5834 unsigned int msb = (given & 0x0000001f); 5835 unsigned int lsb = 0; 5836 5837 lsb |= (given & 0x000000c0u) >> 6; 5838 lsb |= (given & 0x00007000u) >> 10; 5839 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 5840 } 5841 break; 5842 5843 case 'F': 5844 { 5845 unsigned int width = (given & 0x0000001f) + 1; 5846 unsigned int lsb = 0; 5847 5848 lsb |= (given & 0x000000c0u) >> 6; 5849 lsb |= (given & 0x00007000u) >> 10; 5850 func (stream, "#%u, #%u", lsb, width); 5851 } 5852 break; 5853 5854 case 'b': 5855 { 5856 unsigned int S = (given & 0x04000000u) >> 26; 5857 unsigned int J1 = (given & 0x00002000u) >> 13; 5858 unsigned int J2 = (given & 0x00000800u) >> 11; 5859 bfd_vma offset = 0; 5860 5861 offset |= !S << 20; 5862 offset |= J2 << 19; 5863 offset |= J1 << 18; 5864 offset |= (given & 0x003f0000) >> 4; 5865 offset |= (given & 0x000007ff) << 1; 5866 offset -= (1 << 20); 5867 5868 info->print_address_func (pc + 4 + offset, info); 5869 } 5870 break; 5871 5872 case 'B': 5873 { 5874 unsigned int S = (given & 0x04000000u) >> 26; 5875 unsigned int I1 = (given & 0x00002000u) >> 13; 5876 unsigned int I2 = (given & 0x00000800u) >> 11; 5877 bfd_vma offset = 0; 5878 5879 offset |= !S << 24; 5880 offset |= !(I1 ^ S) << 23; 5881 offset |= !(I2 ^ S) << 22; 5882 offset |= (given & 0x03ff0000u) >> 4; 5883 offset |= (given & 0x000007ffu) << 1; 5884 offset -= (1 << 24); 5885 offset += pc + 4; 5886 5887 /* BLX target addresses are always word aligned. */ 5888 if ((given & 0x00001000u) == 0) 5889 offset &= ~2u; 5890 5891 info->print_address_func (offset, info); 5892 } 5893 break; 5894 5895 case 's': 5896 { 5897 unsigned int shift = 0; 5898 5899 shift |= (given & 0x000000c0u) >> 6; 5900 shift |= (given & 0x00007000u) >> 10; 5901 if (WRITEBACK_BIT_SET) 5902 func (stream, ", asr #%u", shift); 5903 else if (shift) 5904 func (stream, ", lsl #%u", shift); 5905 /* else print nothing - lsl #0 */ 5906 } 5907 break; 5908 5909 case 'R': 5910 { 5911 unsigned int rot = (given & 0x00000030) >> 4; 5912 5913 if (rot) 5914 func (stream, ", ror #%u", rot * 8); 5915 } 5916 break; 5917 5918 case 'U': 5919 if ((given & 0xf0) == 0x60) 5920 { 5921 switch (given & 0xf) 5922 { 5923 case 0xf: func (stream, "sy"); break; 5924 default: 5925 func (stream, "#%d", (int) given & 0xf); 5926 break; 5927 } 5928 } 5929 else 5930 { 5931 const char * opt = data_barrier_option (given & 0xf); 5932 if (opt != NULL) 5933 func (stream, "%s", opt); 5934 else 5935 func (stream, "#%d", (int) given & 0xf); 5936 } 5937 break; 5938 5939 case 'C': 5940 if ((given & 0xff) == 0) 5941 { 5942 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 5943 if (given & 0x800) 5944 func (stream, "f"); 5945 if (given & 0x400) 5946 func (stream, "s"); 5947 if (given & 0x200) 5948 func (stream, "x"); 5949 if (given & 0x100) 5950 func (stream, "c"); 5951 } 5952 else if ((given & 0x20) == 0x20) 5953 { 5954 char const* name; 5955 unsigned sysm = (given & 0xf00) >> 8; 5956 5957 sysm |= (given & 0x30); 5958 sysm |= (given & 0x00100000) >> 14; 5959 name = banked_regname (sysm); 5960 5961 if (name != NULL) 5962 func (stream, "%s", name); 5963 else 5964 func (stream, "(UNDEF: %lu)", (unsigned long) sysm); 5965 } 5966 else 5967 { 5968 func (stream, "%s", psr_name (given & 0xff)); 5969 } 5970 break; 5971 5972 case 'D': 5973 if (((given & 0xff) == 0) 5974 || ((given & 0x20) == 0x20)) 5975 { 5976 char const* name; 5977 unsigned sm = (given & 0xf0000) >> 16; 5978 5979 sm |= (given & 0x30); 5980 sm |= (given & 0x00100000) >> 14; 5981 name = banked_regname (sm); 5982 5983 if (name != NULL) 5984 func (stream, "%s", name); 5985 else 5986 func (stream, "(UNDEF: %lu)", (unsigned long) sm); 5987 } 5988 else 5989 func (stream, "%s", psr_name (given & 0xff)); 5990 break; 5991 5992 case '0': case '1': case '2': case '3': case '4': 5993 case '5': case '6': case '7': case '8': case '9': 5994 { 5995 int width; 5996 unsigned long val; 5997 5998 c = arm_decode_bitfield (c, given, &val, &width); 5999 6000 switch (*c) 6001 { 6002 case 'd': 6003 func (stream, "%lu", val); 6004 value_in_comment = val; 6005 break; 6006 6007 case 'D': 6008 func (stream, "%lu", val + 1); 6009 value_in_comment = val + 1; 6010 break; 6011 6012 case 'W': 6013 func (stream, "%lu", val * 4); 6014 value_in_comment = val * 4; 6015 break; 6016 6017 case 'R': 6018 if (val == 15) 6019 is_unpredictable = TRUE; 6020 /* Fall through. */ 6021 case 'r': 6022 func (stream, "%s", arm_regnames[val]); 6023 break; 6024 6025 case 'c': 6026 func (stream, "%s", arm_conditional[val]); 6027 break; 6028 6029 case '\'': 6030 c++; 6031 if (val == ((1ul << width) - 1)) 6032 func (stream, "%c", *c); 6033 break; 6034 6035 case '`': 6036 c++; 6037 if (val == 0) 6038 func (stream, "%c", *c); 6039 break; 6040 6041 case '?': 6042 func (stream, "%c", c[(1 << width) - (int) val]); 6043 c += 1 << width; 6044 break; 6045 6046 case 'x': 6047 func (stream, "0x%lx", val & 0xffffffffUL); 6048 break; 6049 6050 default: 6051 abort (); 6052 } 6053 } 6054 break; 6055 6056 case 'L': 6057 /* PR binutils/12534 6058 If we have a PC relative offset in an LDRD or STRD 6059 instructions then display the decoded address. */ 6060 if (((given >> 16) & 0xf) == 0xf) 6061 { 6062 bfd_vma offset = (given & 0xff) * 4; 6063 6064 if ((given & (1 << 23)) == 0) 6065 offset = - offset; 6066 func (stream, "\t; "); 6067 info->print_address_func ((pc & ~3) + 4 + offset, info); 6068 } 6069 break; 6070 6071 default: 6072 abort (); 6073 } 6074 } 6075 6076 if (value_in_comment > 32 || value_in_comment < -16) 6077 func (stream, "\t; 0x%lx", value_in_comment); 6078 6079 if (is_unpredictable) 6080 func (stream, UNPREDICTABLE_INSTRUCTION); 6081 6082 return; 6083 } 6084 6085 /* No match. */ 6086 abort (); 6087 } 6088 6089 /* Print data bytes on INFO->STREAM. */ 6090 6091 static void 6092 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, 6093 struct disassemble_info *info, 6094 long given) 6095 { 6096 switch (info->bytes_per_chunk) 6097 { 6098 case 1: 6099 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 6100 break; 6101 case 2: 6102 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 6103 break; 6104 case 4: 6105 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 6106 break; 6107 default: 6108 abort (); 6109 } 6110 } 6111 6112 /* Disallow mapping symbols ($a, $b, $d, $t etc) from 6113 being displayed in symbol relative addresses. 6114 6115 Also disallow private symbol, with __tagsym$$ prefix, 6116 from ARM RVCT toolchain being displayed. */ 6117 6118 bfd_boolean 6119 arm_symbol_is_valid (asymbol * sym, 6120 struct disassemble_info * info ATTRIBUTE_UNUSED) 6121 { 6122 const char * name; 6123 6124 if (sym == NULL) 6125 return FALSE; 6126 6127 name = bfd_asymbol_name (sym); 6128 6129 return (name && *name != '$' && strncmp (name, "__tagsym$$", 10)); 6130 } 6131 6132 /* Parse the string of disassembler options. */ 6133 6134 static void 6135 parse_arm_disassembler_options (const char *options) 6136 { 6137 const char *opt; 6138 6139 FOR_EACH_DISASSEMBLER_OPTION (opt, options) 6140 { 6141 if (CONST_STRNEQ (opt, "reg-names-")) 6142 { 6143 unsigned int i; 6144 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6145 if (disassembler_options_cmp (opt, regnames[i].name) == 0) 6146 { 6147 regname_selected = i; 6148 break; 6149 } 6150 6151 if (i >= NUM_ARM_OPTIONS) 6152 /* xgettext: c-format */ 6153 opcodes_error_handler (_("unrecognised register name set: %s"), 6154 opt); 6155 } 6156 else if (CONST_STRNEQ (opt, "force-thumb")) 6157 force_thumb = 1; 6158 else if (CONST_STRNEQ (opt, "no-force-thumb")) 6159 force_thumb = 0; 6160 else 6161 /* xgettext: c-format */ 6162 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt); 6163 } 6164 6165 return; 6166 } 6167 6168 static bfd_boolean 6169 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6170 enum map_type *map_symbol); 6171 6172 /* Search back through the insn stream to determine if this instruction is 6173 conditionally executed. */ 6174 6175 static void 6176 find_ifthen_state (bfd_vma pc, 6177 struct disassemble_info *info, 6178 bfd_boolean little) 6179 { 6180 unsigned char b[2]; 6181 unsigned int insn; 6182 int status; 6183 /* COUNT is twice the number of instructions seen. It will be odd if we 6184 just crossed an instruction boundary. */ 6185 int count; 6186 int it_count; 6187 unsigned int seen_it; 6188 bfd_vma addr; 6189 6190 ifthen_address = pc; 6191 ifthen_state = 0; 6192 6193 addr = pc; 6194 count = 1; 6195 it_count = 0; 6196 seen_it = 0; 6197 /* Scan backwards looking for IT instructions, keeping track of where 6198 instruction boundaries are. We don't know if something is actually an 6199 IT instruction until we find a definite instruction boundary. */ 6200 for (;;) 6201 { 6202 if (addr == 0 || info->symbol_at_address_func (addr, info)) 6203 { 6204 /* A symbol must be on an instruction boundary, and will not 6205 be within an IT block. */ 6206 if (seen_it && (count & 1)) 6207 break; 6208 6209 return; 6210 } 6211 addr -= 2; 6212 status = info->read_memory_func (addr, (bfd_byte *) b, 2, info); 6213 if (status) 6214 return; 6215 6216 if (little) 6217 insn = (b[0]) | (b[1] << 8); 6218 else 6219 insn = (b[1]) | (b[0] << 8); 6220 if (seen_it) 6221 { 6222 if ((insn & 0xf800) < 0xe800) 6223 { 6224 /* Addr + 2 is an instruction boundary. See if this matches 6225 the expected boundary based on the position of the last 6226 IT candidate. */ 6227 if (count & 1) 6228 break; 6229 seen_it = 0; 6230 } 6231 } 6232 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 6233 { 6234 enum map_type type = MAP_ARM; 6235 bfd_boolean found = mapping_symbol_for_insn (addr, info, &type); 6236 6237 if (!found || (found && type == MAP_THUMB)) 6238 { 6239 /* This could be an IT instruction. */ 6240 seen_it = insn; 6241 it_count = count >> 1; 6242 } 6243 } 6244 if ((insn & 0xf800) >= 0xe800) 6245 count++; 6246 else 6247 count = (count + 2) | 1; 6248 /* IT blocks contain at most 4 instructions. */ 6249 if (count >= 8 && !seen_it) 6250 return; 6251 } 6252 /* We found an IT instruction. */ 6253 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 6254 if ((ifthen_state & 0xf) == 0) 6255 ifthen_state = 0; 6256 } 6257 6258 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a 6259 mapping symbol. */ 6260 6261 static int 6262 is_mapping_symbol (struct disassemble_info *info, int n, 6263 enum map_type *map_type) 6264 { 6265 const char *name; 6266 6267 name = bfd_asymbol_name (info->symtab[n]); 6268 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 6269 && (name[2] == 0 || name[2] == '.')) 6270 { 6271 *map_type = ((name[1] == 'a') ? MAP_ARM 6272 : (name[1] == 't') ? MAP_THUMB 6273 : MAP_DATA); 6274 return TRUE; 6275 } 6276 6277 return FALSE; 6278 } 6279 6280 /* Try to infer the code type (ARM or Thumb) from a mapping symbol. 6281 Returns nonzero if *MAP_TYPE was set. */ 6282 6283 static int 6284 get_map_sym_type (struct disassemble_info *info, 6285 int n, 6286 enum map_type *map_type) 6287 { 6288 /* If the symbol is in a different section, ignore it. */ 6289 if (info->section != NULL && info->section != info->symtab[n]->section) 6290 return FALSE; 6291 6292 return is_mapping_symbol (info, n, map_type); 6293 } 6294 6295 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol. 6296 Returns nonzero if *MAP_TYPE was set. */ 6297 6298 static int 6299 get_sym_code_type (struct disassemble_info *info, 6300 int n, 6301 enum map_type *map_type) 6302 { 6303 elf_symbol_type *es; 6304 unsigned int type; 6305 6306 /* If the symbol is in a different section, ignore it. */ 6307 if (info->section != NULL && info->section != info->symtab[n]->section) 6308 return FALSE; 6309 6310 es = *(elf_symbol_type **)(info->symtab + n); 6311 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6312 6313 /* If the symbol has function type then use that. */ 6314 if (type == STT_FUNC || type == STT_GNU_IFUNC) 6315 { 6316 if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6317 == ST_BRANCH_TO_THUMB) 6318 *map_type = MAP_THUMB; 6319 else 6320 *map_type = MAP_ARM; 6321 return TRUE; 6322 } 6323 6324 return FALSE; 6325 } 6326 6327 /* Search the mapping symbol state for instruction at pc. This is only 6328 applicable for elf target. 6329 6330 There is an assumption Here, info->private_data contains the correct AND 6331 up-to-date information about current scan process. The information will be 6332 used to speed this search process. 6333 6334 Return TRUE if the mapping state can be determined, and map_symbol 6335 will be updated accordingly. Otherwise, return FALSE. */ 6336 6337 static bfd_boolean 6338 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info, 6339 enum map_type *map_symbol) 6340 { 6341 bfd_vma addr; 6342 int n, start = 0; 6343 bfd_boolean found = FALSE; 6344 enum map_type type = MAP_ARM; 6345 struct arm_private_data *private_data; 6346 6347 if (info->private_data == NULL || info->symtab_size == 0 6348 || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour) 6349 return FALSE; 6350 6351 private_data = info->private_data; 6352 if (pc == 0) 6353 start = 0; 6354 else 6355 start = private_data->last_mapping_sym; 6356 6357 start = (start == -1)? 0 : start; 6358 addr = bfd_asymbol_value (info->symtab[start]); 6359 6360 if (pc >= addr) 6361 { 6362 if (get_map_sym_type (info, start, &type)) 6363 found = TRUE; 6364 } 6365 else 6366 { 6367 for (n = start - 1; n >= 0; n--) 6368 { 6369 if (get_map_sym_type (info, n, &type)) 6370 { 6371 found = TRUE; 6372 break; 6373 } 6374 } 6375 } 6376 6377 /* No mapping symbols were found. A leading $d may be 6378 omitted for sections which start with data; but for 6379 compatibility with legacy and stripped binaries, only 6380 assume the leading $d if there is at least one mapping 6381 symbol in the file. */ 6382 if (!found && private_data->has_mapping_symbols == 1) 6383 { 6384 type = MAP_DATA; 6385 found = TRUE; 6386 } 6387 6388 *map_symbol = type; 6389 return found; 6390 } 6391 6392 /* Given a bfd_mach_arm_XXX value, this function fills in the fields 6393 of the supplied arm_feature_set structure with bitmasks indicating 6394 the support base architectures and coprocessor extensions. 6395 6396 FIXME: This could more efficiently implemented as a constant array, 6397 although it would also be less robust. */ 6398 6399 static void 6400 select_arm_features (unsigned long mach, 6401 arm_feature_set * features) 6402 { 6403 #undef ARM_SET_FEATURES 6404 #define ARM_SET_FEATURES(FSET) \ 6405 { \ 6406 const arm_feature_set fset = FSET; \ 6407 arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \ 6408 ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \ 6409 } 6410 6411 switch (mach) 6412 { 6413 case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break; 6414 case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break; 6415 case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; 6416 case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; 6417 case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; 6418 case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; 6419 case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; 6420 case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; 6421 case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; 6422 case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; 6423 case bfd_mach_arm_ep9312: 6424 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T, 6425 ARM_CEXT_MAVERICK | FPU_MAVERICK)); 6426 break; 6427 case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; 6428 case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; 6429 /* If the machine type is unknown allow all 6430 architecture types and all extensions. */ 6431 case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break; 6432 default: 6433 abort (); 6434 } 6435 6436 #undef ARM_SET_FEATURES 6437 } 6438 6439 6440 /* NOTE: There are no checks in these routines that 6441 the relevant number of data bytes exist. */ 6442 6443 static int 6444 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 6445 { 6446 unsigned char b[4]; 6447 long given; 6448 int status; 6449 int is_thumb = FALSE; 6450 int is_data = FALSE; 6451 int little_code; 6452 unsigned int size = 4; 6453 void (*printer) (bfd_vma, struct disassemble_info *, long); 6454 bfd_boolean found = FALSE; 6455 struct arm_private_data *private_data; 6456 6457 if (info->disassembler_options) 6458 { 6459 parse_arm_disassembler_options (info->disassembler_options); 6460 6461 /* To avoid repeated parsing of these options, we remove them here. */ 6462 info->disassembler_options = NULL; 6463 } 6464 6465 /* PR 10288: Control which instructions will be disassembled. */ 6466 if (info->private_data == NULL) 6467 { 6468 static struct arm_private_data private; 6469 6470 if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0) 6471 /* If the user did not use the -m command line switch then default to 6472 disassembling all types of ARM instruction. 6473 6474 The info->mach value has to be ignored as this will be based on 6475 the default archictecture for the target and/or hints in the notes 6476 section, but it will never be greater than the current largest arm 6477 machine value (iWMMXt2), which is only equivalent to the V5TE 6478 architecture. ARM architectures have advanced beyond the machine 6479 value encoding, and these newer architectures would be ignored if 6480 the machine value was used. 6481 6482 Ie the -m switch is used to restrict which instructions will be 6483 disassembled. If it is necessary to use the -m switch to tell 6484 objdump that an ARM binary is being disassembled, eg because the 6485 input is a raw binary file, but it is also desired to disassemble 6486 all ARM instructions then use "-marm". This will select the 6487 "unknown" arm architecture which is compatible with any ARM 6488 instruction. */ 6489 info->mach = bfd_mach_arm_unknown; 6490 6491 /* Compute the architecture bitmask from the machine number. 6492 Note: This assumes that the machine number will not change 6493 during disassembly.... */ 6494 select_arm_features (info->mach, & private.features); 6495 6496 private.has_mapping_symbols = -1; 6497 private.last_mapping_sym = -1; 6498 private.last_mapping_addr = 0; 6499 6500 info->private_data = & private; 6501 } 6502 6503 private_data = info->private_data; 6504 6505 /* Decide if our code is going to be little-endian, despite what the 6506 function argument might say. */ 6507 little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little); 6508 6509 /* For ELF, consult the symbol table to determine what kind of code 6510 or data we have. */ 6511 if (info->symtab_size != 0 6512 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 6513 { 6514 bfd_vma addr; 6515 int n, start; 6516 int last_sym = -1; 6517 enum map_type type = MAP_ARM; 6518 6519 /* Start scanning at the start of the function, or wherever 6520 we finished last time. */ 6521 /* PR 14006. When the address is 0 we are either at the start of the 6522 very first function, or else the first function in a new, unlinked 6523 executable section (eg because of -ffunction-sections). Either way 6524 start scanning from the beginning of the symbol table, not where we 6525 left off last time. */ 6526 if (pc == 0) 6527 start = 0; 6528 else 6529 { 6530 start = info->symtab_pos + 1; 6531 if (start < private_data->last_mapping_sym) 6532 start = private_data->last_mapping_sym; 6533 } 6534 found = FALSE; 6535 6536 /* First, look for mapping symbols. */ 6537 if (private_data->has_mapping_symbols != 0) 6538 { 6539 /* Scan up to the location being disassembled. */ 6540 for (n = start; n < info->symtab_size; n++) 6541 { 6542 addr = bfd_asymbol_value (info->symtab[n]); 6543 if (addr > pc) 6544 break; 6545 if (get_map_sym_type (info, n, &type)) 6546 { 6547 last_sym = n; 6548 found = TRUE; 6549 } 6550 } 6551 6552 if (!found) 6553 { 6554 /* No mapping symbol found at this address. Look backwards 6555 for a preceding one. */ 6556 for (n = start - 1; n >= 0; n--) 6557 { 6558 if (get_map_sym_type (info, n, &type)) 6559 { 6560 last_sym = n; 6561 found = TRUE; 6562 break; 6563 } 6564 } 6565 } 6566 6567 if (found) 6568 private_data->has_mapping_symbols = 1; 6569 6570 /* No mapping symbols were found. A leading $d may be 6571 omitted for sections which start with data; but for 6572 compatibility with legacy and stripped binaries, only 6573 assume the leading $d if there is at least one mapping 6574 symbol in the file. */ 6575 if (!found && private_data->has_mapping_symbols == -1) 6576 { 6577 /* Look for mapping symbols, in any section. */ 6578 for (n = 0; n < info->symtab_size; n++) 6579 if (is_mapping_symbol (info, n, &type)) 6580 { 6581 private_data->has_mapping_symbols = 1; 6582 break; 6583 } 6584 if (private_data->has_mapping_symbols == -1) 6585 private_data->has_mapping_symbols = 0; 6586 } 6587 6588 if (!found && private_data->has_mapping_symbols == 1) 6589 { 6590 type = MAP_DATA; 6591 found = TRUE; 6592 } 6593 } 6594 6595 /* Next search for function symbols to separate ARM from Thumb 6596 in binaries without mapping symbols. */ 6597 if (!found) 6598 { 6599 /* Scan up to the location being disassembled. */ 6600 for (n = start; n < info->symtab_size; n++) 6601 { 6602 addr = bfd_asymbol_value (info->symtab[n]); 6603 if (addr > pc) 6604 break; 6605 if (get_sym_code_type (info, n, &type)) 6606 { 6607 last_sym = n; 6608 found = TRUE; 6609 } 6610 } 6611 6612 if (!found) 6613 { 6614 /* No mapping symbol found at this address. Look backwards 6615 for a preceding one. */ 6616 for (n = start - 1; n >= 0; n--) 6617 { 6618 if (get_sym_code_type (info, n, &type)) 6619 { 6620 last_sym = n; 6621 found = TRUE; 6622 break; 6623 } 6624 } 6625 } 6626 } 6627 6628 private_data->last_mapping_sym = last_sym; 6629 private_data->last_type = type; 6630 is_thumb = (private_data->last_type == MAP_THUMB); 6631 is_data = (private_data->last_type == MAP_DATA); 6632 6633 /* Look a little bit ahead to see if we should print out 6634 two or four bytes of data. If there's a symbol, 6635 mapping or otherwise, after two bytes then don't 6636 print more. */ 6637 if (is_data) 6638 { 6639 size = 4 - (pc & 3); 6640 for (n = last_sym + 1; n < info->symtab_size; n++) 6641 { 6642 addr = bfd_asymbol_value (info->symtab[n]); 6643 if (addr > pc 6644 && (info->section == NULL 6645 || info->section == info->symtab[n]->section)) 6646 { 6647 if (addr - pc < size) 6648 size = addr - pc; 6649 break; 6650 } 6651 } 6652 /* If the next symbol is after three bytes, we need to 6653 print only part of the data, so that we can use either 6654 .byte or .short. */ 6655 if (size == 3) 6656 size = (pc & 1) ? 1 : 2; 6657 } 6658 } 6659 6660 if (info->symbols != NULL) 6661 { 6662 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 6663 { 6664 coff_symbol_type * cs; 6665 6666 cs = coffsymbol (*info->symbols); 6667 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 6668 || cs->native->u.syment.n_sclass == C_THUMBSTAT 6669 || cs->native->u.syment.n_sclass == C_THUMBLABEL 6670 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 6671 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 6672 } 6673 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 6674 && !found) 6675 { 6676 /* If no mapping symbol has been found then fall back to the type 6677 of the function symbol. */ 6678 elf_symbol_type * es; 6679 unsigned int type; 6680 6681 es = *(elf_symbol_type **)(info->symbols); 6682 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 6683 6684 is_thumb = 6685 ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal) 6686 == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT); 6687 } 6688 else if (bfd_asymbol_flavour (*info->symbols) 6689 == bfd_target_mach_o_flavour) 6690 { 6691 bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols; 6692 6693 is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF); 6694 } 6695 } 6696 6697 if (force_thumb) 6698 is_thumb = TRUE; 6699 6700 if (is_data) 6701 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6702 else 6703 info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 6704 6705 info->bytes_per_line = 4; 6706 6707 /* PR 10263: Disassemble data if requested to do so by the user. */ 6708 if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0)) 6709 { 6710 int i; 6711 6712 /* Size was already set above. */ 6713 info->bytes_per_chunk = size; 6714 printer = print_insn_data; 6715 6716 status = info->read_memory_func (pc, (bfd_byte *) b, size, info); 6717 given = 0; 6718 if (little) 6719 for (i = size - 1; i >= 0; i--) 6720 given = b[i] | (given << 8); 6721 else 6722 for (i = 0; i < (int) size; i++) 6723 given = b[i] | (given << 8); 6724 } 6725 else if (!is_thumb) 6726 { 6727 /* In ARM mode endianness is a straightforward issue: the instruction 6728 is four bytes long and is either ordered 0123 or 3210. */ 6729 printer = print_insn_arm; 6730 info->bytes_per_chunk = 4; 6731 size = 4; 6732 6733 status = info->read_memory_func (pc, (bfd_byte *) b, 4, info); 6734 if (little_code) 6735 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 6736 else 6737 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); 6738 } 6739 else 6740 { 6741 /* In Thumb mode we have the additional wrinkle of two 6742 instruction lengths. Fortunately, the bits that determine 6743 the length of the current instruction are always to be found 6744 in the first two bytes. */ 6745 printer = print_insn_thumb16; 6746 info->bytes_per_chunk = 2; 6747 size = 2; 6748 6749 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); 6750 if (little_code) 6751 given = (b[0]) | (b[1] << 8); 6752 else 6753 given = (b[1]) | (b[0] << 8); 6754 6755 if (!status) 6756 { 6757 /* These bit patterns signal a four-byte Thumb 6758 instruction. */ 6759 if ((given & 0xF800) == 0xF800 6760 || (given & 0xF800) == 0xF000 6761 || (given & 0xF800) == 0xE800) 6762 { 6763 status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info); 6764 if (little_code) 6765 given = (b[0]) | (b[1] << 8) | (given << 16); 6766 else 6767 given = (b[1]) | (b[0] << 8) | (given << 16); 6768 6769 printer = print_insn_thumb32; 6770 size = 4; 6771 } 6772 } 6773 6774 if (ifthen_address != pc) 6775 find_ifthen_state (pc, info, little_code); 6776 6777 if (ifthen_state) 6778 { 6779 if ((ifthen_state & 0xf) == 0x8) 6780 ifthen_next_state = 0; 6781 else 6782 ifthen_next_state = (ifthen_state & 0xe0) 6783 | ((ifthen_state & 0xf) << 1); 6784 } 6785 } 6786 6787 if (status) 6788 { 6789 info->memory_error_func (status, pc, info); 6790 return -1; 6791 } 6792 if (info->flags & INSN_HAS_RELOC) 6793 /* If the instruction has a reloc associated with it, then 6794 the offset field in the instruction will actually be the 6795 addend for the reloc. (We are using REL type relocs). 6796 In such cases, we can ignore the pc when computing 6797 addresses, since the addend is not currently pc-relative. */ 6798 pc = 0; 6799 6800 printer (pc, info, given); 6801 6802 if (is_thumb) 6803 { 6804 ifthen_state = ifthen_next_state; 6805 ifthen_address += size; 6806 } 6807 return size; 6808 } 6809 6810 int 6811 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 6812 { 6813 /* Detect BE8-ness and record it in the disassembler info. */ 6814 if (info->flavour == bfd_target_elf_flavour 6815 && info->section != NULL 6816 && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8)) 6817 info->endian_code = BFD_ENDIAN_LITTLE; 6818 6819 return print_insn (pc, info, FALSE); 6820 } 6821 6822 int 6823 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 6824 { 6825 return print_insn (pc, info, TRUE); 6826 } 6827 6828 const disasm_options_t * 6829 disassembler_options_arm (void) 6830 { 6831 static disasm_options_t *opts = NULL; 6832 6833 if (opts == NULL) 6834 { 6835 unsigned int i; 6836 opts = XNEW (disasm_options_t); 6837 opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 6838 opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1); 6839 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6840 { 6841 opts->name[i] = regnames[i].name; 6842 if (regnames[i].description != NULL) 6843 opts->description[i] = _(regnames[i].description); 6844 else 6845 opts->description[i] = NULL; 6846 } 6847 /* The array we return must be NULL terminated. */ 6848 opts->name[i] = NULL; 6849 opts->description[i] = NULL; 6850 } 6851 6852 return opts; 6853 } 6854 6855 void 6856 print_arm_disassembler_options (FILE *stream) 6857 { 6858 unsigned int i, max_len = 0; 6859 fprintf (stream, _("\n\ 6860 The following ARM specific disassembler options are supported for use with\n\ 6861 the -M switch:\n")); 6862 6863 for (i = 0; i < NUM_ARM_OPTIONS; i++) 6864 { 6865 unsigned int len = strlen (regnames[i].name); 6866 if (max_len < len) 6867 max_len = len; 6868 } 6869 6870 for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++) 6871 fprintf (stream, " %s%*c %s\n", 6872 regnames[i].name, 6873 (int)(max_len - strlen (regnames[i].name)), ' ', 6874 _(regnames[i].description)); 6875 } 6876