1 /* Opcode table for the ARC. 2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 3 4 Contributed by Claudiu Zissulescu (claziss@synopsys.com) 5 6 This file is part of libopcodes. 7 8 This library is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 It is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software Foundation, 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21 22 #include "sysdep.h" 23 #include <stdio.h> 24 #include "bfd.h" 25 #include "opcode/arc.h" 26 #include "opintl.h" 27 #include "libiberty.h" 28 29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom 30 instructions. All NPS400 features are built into all ARC target builds as 31 this reduces the chances that regressions might creep in. */ 32 33 /* Insert RA register into a 32-bit opcode, with checks. */ 34 35 static unsigned long long 36 insert_ra_chk (unsigned long long insn, 37 long long value, 38 const char ** errmsg) 39 { 40 if (value == 60) 41 *errmsg = _("LP_COUNT register cannot be used as destination register"); 42 43 return insn | (value & 0x3F); 44 } 45 46 /* Insert RB register into a 32-bit opcode. */ 47 48 static unsigned long long 49 insert_rb (unsigned long long insn, 50 long long value, 51 const char ** errmsg ATTRIBUTE_UNUSED) 52 { 53 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); 54 } 55 56 /* Insert RB register with checks. */ 57 58 static unsigned long long 59 insert_rb_chk (unsigned long long insn, 60 long long value, 61 const char ** errmsg) 62 { 63 if (value == 60) 64 *errmsg = _("LP_COUNT register cannot be used as destination register"); 65 66 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); 67 } 68 69 static long long 70 extract_rb (unsigned long long insn, 71 bfd_boolean * invalid) 72 { 73 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); 74 75 if (value == 0x3e && invalid) 76 *invalid = TRUE; /* A limm operand, it should be extracted in a 77 different way. */ 78 79 return value; 80 } 81 82 static unsigned long long 83 insert_rad (unsigned long long insn, 84 long long value, 85 const char ** errmsg) 86 { 87 if (value & 0x01) 88 *errmsg = _("cannot use odd number destination register"); 89 if (value == 60) 90 *errmsg = _("LP_COUNT register cannot be used as destination register"); 91 92 return insn | (value & 0x3F); 93 } 94 95 static unsigned long long 96 insert_rcd (unsigned long long insn, 97 long long value, 98 const char ** errmsg) 99 { 100 if (value & 0x01) 101 *errmsg = _("cannot use odd number source register"); 102 103 return insn | ((value & 0x3F) << 6); 104 } 105 106 /* Dummy insert ZERO operand function. */ 107 108 static unsigned long long 109 insert_za (unsigned long long insn, 110 long long value, 111 const char ** errmsg) 112 { 113 if (value) 114 *errmsg = _("operand is not zero"); 115 return insn; 116 } 117 118 /* Insert Y-bit in bbit/br instructions. This function is called only 119 when solving fixups. */ 120 121 static unsigned long long 122 insert_Ybit (unsigned long long insn, 123 long long value, 124 const char ** errmsg ATTRIBUTE_UNUSED) 125 { 126 if (value > 0) 127 insn |= 0x08; 128 129 return insn; 130 } 131 132 /* Insert Y-bit in bbit/br instructions. This function is called only 133 when solving fixups. */ 134 135 static unsigned long long 136 insert_NYbit (unsigned long long insn, 137 long long value, 138 const char ** errmsg ATTRIBUTE_UNUSED) 139 { 140 if (value < 0) 141 insn |= 0x08; 142 143 return insn; 144 } 145 146 /* Insert H register into a 16-bit opcode. */ 147 148 static unsigned long long 149 insert_rhv1 (unsigned long long insn, 150 long long value, 151 const char ** errmsg ATTRIBUTE_UNUSED) 152 { 153 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); 154 } 155 156 static long long 157 extract_rhv1 (unsigned long long insn, 158 bfd_boolean * invalid ATTRIBUTE_UNUSED) 159 { 160 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7); 161 162 return value; 163 } 164 165 /* Insert H register into a 16-bit opcode. */ 166 167 static unsigned long long 168 insert_rhv2 (unsigned long long insn, 169 long long value, 170 const char ** errmsg) 171 { 172 if (value == 0x1E) 173 *errmsg = _("register R30 is a limm indicator"); 174 else if (value < 0 || value > 31) 175 *errmsg = _("register out of range"); 176 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); 177 } 178 179 static long long 180 extract_rhv2 (unsigned long long insn, 181 bfd_boolean * invalid ATTRIBUTE_UNUSED) 182 { 183 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); 184 185 return value; 186 } 187 188 static unsigned long long 189 insert_r0 (unsigned long long insn, 190 long long value, 191 const char ** errmsg) 192 { 193 if (value != 0) 194 *errmsg = _("register must be R0"); 195 return insn; 196 } 197 198 static long long 199 extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED, 200 bfd_boolean * invalid ATTRIBUTE_UNUSED) 201 { 202 return 0; 203 } 204 205 206 static unsigned long long 207 insert_r1 (unsigned long long insn, 208 long long value, 209 const char ** errmsg) 210 { 211 if (value != 1) 212 *errmsg = _("register must be R1"); 213 return insn; 214 } 215 216 static long long 217 extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED, 218 bfd_boolean * invalid ATTRIBUTE_UNUSED) 219 { 220 return 1; 221 } 222 223 static unsigned long long 224 insert_r2 (unsigned long long insn, 225 long long value, 226 const char ** errmsg) 227 { 228 if (value != 2) 229 *errmsg = _("register must be R2"); 230 return insn; 231 } 232 233 static long long 234 extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED, 235 bfd_boolean * invalid ATTRIBUTE_UNUSED) 236 { 237 return 2; 238 } 239 240 static unsigned long long 241 insert_r3 (unsigned long long insn, 242 long long value, 243 const char ** errmsg) 244 { 245 if (value != 3) 246 *errmsg = _("register must be R3"); 247 return insn; 248 } 249 250 static long long 251 extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED, 252 bfd_boolean * invalid ATTRIBUTE_UNUSED) 253 { 254 return 3; 255 } 256 257 static unsigned long long 258 insert_sp (unsigned long long insn, 259 long long value, 260 const char ** errmsg) 261 { 262 if (value != 28) 263 *errmsg = _("register must be SP"); 264 return insn; 265 } 266 267 static long long 268 extract_sp (unsigned long long insn ATTRIBUTE_UNUSED, 269 bfd_boolean * invalid ATTRIBUTE_UNUSED) 270 { 271 return 28; 272 } 273 274 static unsigned long long 275 insert_gp (unsigned long long insn, 276 long long value, 277 const char ** errmsg) 278 { 279 if (value != 26) 280 *errmsg = _("register must be GP"); 281 return insn; 282 } 283 284 static long long 285 extract_gp (unsigned long long insn ATTRIBUTE_UNUSED, 286 bfd_boolean * invalid ATTRIBUTE_UNUSED) 287 { 288 return 26; 289 } 290 291 static unsigned long long 292 insert_pcl (unsigned long long insn, 293 long long value, 294 const char ** errmsg) 295 { 296 if (value != 63) 297 *errmsg = _("register must be PCL"); 298 return insn; 299 } 300 301 static long long 302 extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED, 303 bfd_boolean * invalid ATTRIBUTE_UNUSED) 304 { 305 return 63; 306 } 307 308 static unsigned long long 309 insert_blink (unsigned long long insn, 310 long long value, 311 const char ** errmsg) 312 { 313 if (value != 31) 314 *errmsg = _("register must be BLINK"); 315 return insn; 316 } 317 318 static long long 319 extract_blink (unsigned long long insn ATTRIBUTE_UNUSED, 320 bfd_boolean * invalid ATTRIBUTE_UNUSED) 321 { 322 return 31; 323 } 324 325 static unsigned long long 326 insert_ilink1 (unsigned long long insn, 327 long long value, 328 const char ** errmsg) 329 { 330 if (value != 29) 331 *errmsg = _("register must be ILINK1"); 332 return insn; 333 } 334 335 static long long 336 extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED, 337 bfd_boolean * invalid ATTRIBUTE_UNUSED) 338 { 339 return 29; 340 } 341 342 static unsigned long long 343 insert_ilink2 (unsigned long long insn, 344 long long value, 345 const char ** errmsg) 346 { 347 if (value != 30) 348 *errmsg = _("register must be ILINK2"); 349 return insn; 350 } 351 352 static long long 353 extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED, 354 bfd_boolean * invalid ATTRIBUTE_UNUSED) 355 { 356 return 30; 357 } 358 359 static unsigned long long 360 insert_ras (unsigned long long insn, 361 long long value, 362 const char ** errmsg) 363 { 364 switch (value) 365 { 366 case 0: 367 case 1: 368 case 2: 369 case 3: 370 insn |= value; 371 break; 372 case 12: 373 case 13: 374 case 14: 375 case 15: 376 insn |= (value - 8); 377 break; 378 default: 379 *errmsg = _("register must be either r0-r3 or r12-r15"); 380 break; 381 } 382 return insn; 383 } 384 385 static long long 386 extract_ras (unsigned long long insn, 387 bfd_boolean * invalid ATTRIBUTE_UNUSED) 388 { 389 int value = insn & 0x07; 390 391 if (value > 3) 392 return (value + 8); 393 else 394 return value; 395 } 396 397 static unsigned long long 398 insert_rbs (unsigned long long insn, 399 long long value, 400 const char ** errmsg) 401 { 402 switch (value) 403 { 404 case 0: 405 case 1: 406 case 2: 407 case 3: 408 insn |= value << 8; 409 break; 410 case 12: 411 case 13: 412 case 14: 413 case 15: 414 insn |= ((value - 8)) << 8; 415 break; 416 default: 417 *errmsg = _("register must be either r0-r3 or r12-r15"); 418 break; 419 } 420 return insn; 421 } 422 423 static long long 424 extract_rbs (unsigned long long insn, 425 bfd_boolean * invalid ATTRIBUTE_UNUSED) 426 { 427 int value = (insn >> 8) & 0x07; 428 429 if (value > 3) 430 return (value + 8); 431 else 432 return value; 433 } 434 435 static unsigned long long 436 insert_rcs (unsigned long long insn, 437 long long value, 438 const char ** errmsg) 439 { 440 switch (value) 441 { 442 case 0: 443 case 1: 444 case 2: 445 case 3: 446 insn |= value << 5; 447 break; 448 case 12: 449 case 13: 450 case 14: 451 case 15: 452 insn |= ((value - 8)) << 5; 453 break; 454 default: 455 *errmsg = _("register must be either r0-r3 or r12-r15"); 456 break; 457 } 458 return insn; 459 } 460 461 static long long 462 extract_rcs (unsigned long long insn, 463 bfd_boolean * invalid ATTRIBUTE_UNUSED) 464 { 465 int value = (insn >> 5) & 0x07; 466 467 if (value > 3) 468 return (value + 8); 469 else 470 return value; 471 } 472 473 static unsigned long long 474 insert_simm3s (unsigned long long insn, 475 long long value, 476 const char ** errmsg) 477 { 478 int tmp = 0; 479 switch (value) 480 { 481 case -1: 482 tmp = 0x07; 483 break; 484 case 0: 485 tmp = 0x00; 486 break; 487 case 1: 488 tmp = 0x01; 489 break; 490 case 2: 491 tmp = 0x02; 492 break; 493 case 3: 494 tmp = 0x03; 495 break; 496 case 4: 497 tmp = 0x04; 498 break; 499 case 5: 500 tmp = 0x05; 501 break; 502 case 6: 503 tmp = 0x06; 504 break; 505 default: 506 *errmsg = _("accepted values are from -1 to 6"); 507 break; 508 } 509 510 insn |= tmp << 8; 511 return insn; 512 } 513 514 static long long 515 extract_simm3s (unsigned long long insn, 516 bfd_boolean * invalid ATTRIBUTE_UNUSED) 517 { 518 int value = (insn >> 8) & 0x07; 519 520 if (value == 7) 521 return -1; 522 else 523 return value; 524 } 525 526 static unsigned long long 527 insert_rrange (unsigned long long insn, 528 long long value, 529 const char ** errmsg) 530 { 531 int reg1 = (value >> 16) & 0xFFFF; 532 int reg2 = value & 0xFFFF; 533 534 if (reg1 != 13) 535 *errmsg = _("first register of the range should be r13"); 536 else if (reg2 < 13 || reg2 > 26) 537 *errmsg = _("last register of the range doesn't fit"); 538 else 539 insn |= ((reg2 - 12) & 0x0F) << 1; 540 return insn; 541 } 542 543 static long long 544 extract_rrange (unsigned long long insn, 545 bfd_boolean * invalid ATTRIBUTE_UNUSED) 546 { 547 return (insn >> 1) & 0x0F; 548 } 549 550 static unsigned long long 551 insert_r13el (unsigned long long insn, 552 long long int value, 553 const char **errmsg) 554 { 555 if (value != 13) 556 { 557 *errmsg = _("invalid register number, should be fp"); 558 return insn; 559 } 560 561 insn |= 0x02; 562 return insn; 563 } 564 565 static unsigned long long 566 insert_fpel (unsigned long long insn, 567 long long value, 568 const char ** errmsg) 569 { 570 if (value != 27) 571 { 572 *errmsg = _("invalid register number, should be fp"); 573 return insn; 574 } 575 576 insn |= 0x0100; 577 return insn; 578 } 579 580 static long long 581 extract_fpel (unsigned long long insn, 582 bfd_boolean * invalid ATTRIBUTE_UNUSED) 583 { 584 return (insn & 0x0100) ? 27 : -1; 585 } 586 587 static unsigned long long 588 insert_blinkel (unsigned long long insn, 589 long long value, 590 const char ** errmsg) 591 { 592 if (value != 31) 593 { 594 *errmsg = _("invalid register number, should be blink"); 595 return insn; 596 } 597 598 insn |= 0x0200; 599 return insn; 600 } 601 602 static long long 603 extract_blinkel (unsigned long long insn, 604 bfd_boolean * invalid ATTRIBUTE_UNUSED) 605 { 606 return (insn & 0x0200) ? 31 : -1; 607 } 608 609 static unsigned long long 610 insert_pclel (unsigned long long insn, 611 long long value, 612 const char ** errmsg) 613 { 614 if (value != 63) 615 { 616 *errmsg = _("invalid register number, should be pcl"); 617 return insn; 618 } 619 620 insn |= 0x0400; 621 return insn; 622 } 623 624 static long long 625 extract_pclel (unsigned long long insn, 626 bfd_boolean * invalid ATTRIBUTE_UNUSED) 627 { 628 return (insn & 0x0400) ? 63 : -1; 629 } 630 631 #define INSERT_W6 632 633 /* mask = 00000000000000000000111111000000 634 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ 635 636 static unsigned long long 637 insert_w6 (unsigned long long insn, 638 long long value, 639 const char ** errmsg ATTRIBUTE_UNUSED) 640 { 641 insn |= ((value >> 0) & 0x003f) << 6; 642 643 return insn; 644 } 645 646 #define EXTRACT_W6 647 648 /* mask = 00000000000000000000111111000000. */ 649 650 static long long 651 extract_w6 (unsigned long long insn, 652 bfd_boolean * invalid ATTRIBUTE_UNUSED) 653 { 654 unsigned value = 0; 655 656 value |= ((insn >> 6) & 0x003f) << 0; 657 658 return value; 659 } 660 661 #define INSERT_G_S 662 663 /* mask = 0000011100022000 664 insn = 01000ggghhhGG0HH. */ 665 666 static unsigned long long 667 insert_g_s (unsigned long long insn, 668 long long value, 669 const char ** errmsg ATTRIBUTE_UNUSED) 670 { 671 insn |= ((value >> 0) & 0x0007) << 8; 672 insn |= ((value >> 3) & 0x0003) << 3; 673 674 return insn; 675 } 676 677 #define EXTRACT_G_S 678 679 /* mask = 0000011100022000. */ 680 681 static long long 682 extract_g_s (unsigned long long insn, 683 bfd_boolean * invalid ATTRIBUTE_UNUSED) 684 { 685 int value = 0; 686 int signbit = 1 << (6 - 1); 687 688 value |= ((insn >> 8) & 0x0007) << 0; 689 value |= ((insn >> 3) & 0x0003) << 3; 690 691 /* Extend the sign. */ 692 value = (value ^ signbit) - signbit; 693 694 return value; 695 } 696 697 /* ARC NPS400 Support: See comment near head of file. */ 698 #define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \ 699 static unsigned long long \ 700 insert_nps_3bit_reg_at_##OFFSET##_##NAME \ 701 (unsigned long long insn, \ 702 long long value, \ 703 const char ** errmsg) \ 704 { \ 705 switch (value) \ 706 { \ 707 case 0: \ 708 case 1: \ 709 case 2: \ 710 case 3: \ 711 insn |= value << (OFFSET); \ 712 break; \ 713 case 12: \ 714 case 13: \ 715 case 14: \ 716 case 15: \ 717 insn |= (value - 8) << (OFFSET); \ 718 break; \ 719 default: \ 720 *errmsg = _("register must be either r0-r3 or r12-r15"); \ 721 break; \ 722 } \ 723 return insn; \ 724 } \ 725 \ 726 static long long \ 727 extract_nps_3bit_reg_at_##OFFSET##_##NAME \ 728 (unsigned long long insn, \ 729 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 730 { \ 731 int value = (insn >> (OFFSET)) & 0x07; \ 732 if (value > 3) \ 733 value += 8; \ 734 return value; \ 735 } \ 736 737 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8) 738 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24) 739 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40) 740 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56) 741 742 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5) 743 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21) 744 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37) 745 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53) 746 747 static unsigned long long 748 insert_nps_bitop_size_2b (unsigned long long insn, 749 long long value, 750 const char ** errmsg) 751 { 752 switch (value) 753 { 754 case 1: 755 value = 0; 756 break; 757 case 2: 758 value = 1; 759 break; 760 case 4: 761 value = 2; 762 break; 763 case 8: 764 value = 3; 765 break; 766 default: 767 value = 0; 768 *errmsg = _("invalid size, should be 1, 2, 4, or 8"); 769 break; 770 } 771 772 insn |= value << 10; 773 return insn; 774 } 775 776 static long long 777 extract_nps_bitop_size_2b (unsigned long long insn, 778 bfd_boolean * invalid ATTRIBUTE_UNUSED) 779 { 780 return 1 << ((insn >> 10) & 0x3); 781 } 782 783 static unsigned long long 784 insert_nps_bitop_uimm8 (unsigned long long insn, 785 long long value, 786 const char ** errmsg ATTRIBUTE_UNUSED) 787 { 788 insn |= ((value >> 5) & 7) << 12; 789 insn |= (value & 0x1f); 790 return insn; 791 } 792 793 static long long 794 extract_nps_bitop_uimm8 (unsigned long long insn, 795 bfd_boolean * invalid ATTRIBUTE_UNUSED) 796 { 797 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f); 798 } 799 800 static unsigned long long 801 insert_nps_rflt_uimm6 (unsigned long long insn, 802 long long value, 803 const char ** errmsg) 804 { 805 switch (value) 806 { 807 case 1: 808 case 2: 809 case 4: 810 break; 811 812 default: 813 *errmsg = _("invalid immediate, must be 1, 2, or 4"); 814 value = 0; 815 } 816 817 insn |= (value << 6); 818 return insn; 819 } 820 821 static long long 822 extract_nps_rflt_uimm6 (unsigned long long insn, 823 bfd_boolean * invalid ATTRIBUTE_UNUSED) 824 { 825 return (insn >> 6) & 0x3f; 826 } 827 828 static unsigned long long 829 insert_nps_dst_pos_and_size (unsigned long long insn, 830 long long value, 831 const char ** errmsg ATTRIBUTE_UNUSED) 832 { 833 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10)); 834 return insn; 835 } 836 837 static long long 838 extract_nps_dst_pos_and_size (unsigned long long insn, 839 bfd_boolean * invalid ATTRIBUTE_UNUSED) 840 { 841 return (insn & 0x1f); 842 } 843 844 static unsigned long long 845 insert_nps_cmem_uimm16 (unsigned long long insn, 846 long long value, 847 const char ** errmsg) 848 { 849 int top = (value >> 16) & 0xffff; 850 851 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE) 852 *errmsg = _("invalid value for CMEM ld/st immediate"); 853 insn |= (value & 0xffff); 854 return insn; 855 } 856 857 static long long 858 extract_nps_cmem_uimm16 (unsigned long long insn, 859 bfd_boolean * invalid ATTRIBUTE_UNUSED) 860 { 861 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff); 862 } 863 864 static unsigned long long 865 insert_nps_imm_offset (unsigned long long insn, 866 long long value, 867 const char ** errmsg) 868 { 869 switch (value) 870 { 871 case 0: 872 case 16: 873 case 32: 874 case 48: 875 case 64: 876 value = value >> 4; 877 break; 878 default: 879 *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64."); 880 value = 0; 881 } 882 insn |= (value << 10); 883 return insn; 884 } 885 886 static long long 887 extract_nps_imm_offset (unsigned long long insn, 888 bfd_boolean * invalid ATTRIBUTE_UNUSED) 889 { 890 return ((insn >> 10) & 0x7) * 16; 891 } 892 893 static unsigned long long 894 insert_nps_imm_entry (unsigned long long insn, 895 long long value, 896 const char ** errmsg) 897 { 898 switch (value) 899 { 900 case 16: 901 value = 0; 902 break; 903 case 32: 904 value = 1; 905 break; 906 case 64: 907 value = 2; 908 break; 909 case 128: 910 value = 3; 911 break; 912 default: 913 *errmsg = _("invalid position, should be 16, 32, 64 or 128."); 914 value = 0; 915 } 916 insn |= (value << 2); 917 return insn; 918 } 919 920 static long long 921 extract_nps_imm_entry (unsigned long long insn, 922 bfd_boolean * invalid ATTRIBUTE_UNUSED) 923 { 924 int imm_entry = ((insn >> 2) & 0x7); 925 return (1 << (imm_entry + 4)); 926 } 927 928 static unsigned long long 929 insert_nps_size_16bit (unsigned long long insn, 930 long long value, 931 const char ** errmsg) 932 { 933 if ((value < 1) || (value > 64)) 934 { 935 *errmsg = _("invalid size value must be on range 1-64."); 936 value = 0; 937 } 938 value = value & 0x3f; 939 insn |= (value << 6); 940 return insn; 941 } 942 943 static long long 944 extract_nps_size_16bit (unsigned long long insn, 945 bfd_boolean * invalid ATTRIBUTE_UNUSED) 946 { 947 return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64; 948 } 949 950 951 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \ 952 static unsigned long long \ 953 insert_nps_##NAME##_pos (unsigned long long insn, \ 954 long long value, \ 955 const char ** errmsg) \ 956 { \ 957 switch (value) \ 958 { \ 959 case 0: \ 960 case 8: \ 961 case 16: \ 962 case 24: \ 963 value = value / 8; \ 964 break; \ 965 default: \ 966 *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \ 967 value = 0; \ 968 } \ 969 insn |= (value << SHIFT); \ 970 return insn; \ 971 } \ 972 \ 973 static long long \ 974 extract_nps_##NAME##_pos (unsigned long long insn, \ 975 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 976 { \ 977 return ((insn >> SHIFT) & 0x3) * 8; \ 978 } 979 980 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12) 981 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10) 982 983 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \ 984 static unsigned long long \ 985 insert_nps_##NAME (unsigned long long insn, \ 986 long long value, \ 987 const char ** errmsg) \ 988 { \ 989 if (value < LOWER || value > UPPER) \ 990 { \ 991 *errmsg = _("invalid size, value must be " \ 992 #LOWER " to " #UPPER "."); \ 993 return insn; \ 994 } \ 995 value -= BIAS; \ 996 insn |= (value << SHIFT); \ 997 return insn; \ 998 } \ 999 \ 1000 static long long \ 1001 extract_nps_##NAME (unsigned long long insn, \ 1002 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 1003 { \ 1004 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \ 1005 } 1006 1007 MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5) 1008 MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5) 1009 MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5) 1010 MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5) 1011 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10) 1012 MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9) 1013 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20) 1014 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25) 1015 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6) 1016 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2) 1017 MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0) 1018 1019 static long long 1020 extract_nps_qcmp_m3 (unsigned long long insn, 1021 bfd_boolean * invalid) 1022 { 1023 int m3 = (insn >> 5) & 0xf; 1024 if (m3 == 0xf) 1025 *invalid = TRUE; 1026 return m3; 1027 } 1028 1029 static long long 1030 extract_nps_qcmp_m2 (unsigned long long insn, 1031 bfd_boolean * invalid) 1032 { 1033 bfd_boolean tmp_invalid = FALSE; 1034 int m2 = (insn >> 15) & 0x1; 1035 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); 1036 1037 if (m2 == 0 && m3 == 0xf) 1038 *invalid = TRUE; 1039 return m2; 1040 } 1041 1042 static long long 1043 extract_nps_qcmp_m1 (unsigned long long insn, 1044 bfd_boolean * invalid) 1045 { 1046 bfd_boolean tmp_invalid = FALSE; 1047 int m1 = (insn >> 14) & 0x1; 1048 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid); 1049 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid); 1050 1051 if (m1 == 0 && m2 == 0 && m3 == 0xf) 1052 *invalid = TRUE; 1053 return m1; 1054 } 1055 1056 static unsigned long long 1057 insert_nps_calc_entry_size (unsigned long long insn, 1058 long long value, 1059 const char ** errmsg) 1060 { 1061 unsigned pwr; 1062 1063 if (value < 1 || value > 256) 1064 { 1065 *errmsg = _("value out of range 1 - 256"); 1066 return 0; 1067 } 1068 1069 for (pwr = 0; (value & 1) == 0; value >>= 1) 1070 ++pwr; 1071 1072 if (value != 1) 1073 { 1074 *errmsg = _("value must be power of 2"); 1075 return 0; 1076 } 1077 1078 return insn | (pwr << 8); 1079 } 1080 1081 static long long 1082 extract_nps_calc_entry_size (unsigned long long insn, 1083 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1084 { 1085 unsigned entry_size = (insn >> 8) & 0xf; 1086 return 1 << entry_size; 1087 } 1088 1089 static unsigned long long 1090 insert_nps_bitop_mod4 (unsigned long long insn, 1091 long long value, 1092 const char ** errmsg ATTRIBUTE_UNUSED) 1093 { 1094 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47); 1095 } 1096 1097 static long long 1098 extract_nps_bitop_mod4 (unsigned long long insn, 1099 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1100 { 1101 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1); 1102 } 1103 1104 static unsigned long long 1105 insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn, 1106 long long value, 1107 const char ** errmsg ATTRIBUTE_UNUSED) 1108 { 1109 return insn | (value << 42) | (value << 37); 1110 } 1111 1112 static long long 1113 extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn, 1114 bfd_boolean * invalid) 1115 { 1116 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f)) 1117 *invalid = TRUE; 1118 return ((insn >> 37) & 0x1f); 1119 } 1120 1121 static unsigned long long 1122 insert_nps_bitop_ins_ext (unsigned long long insn, 1123 long long value, 1124 const char ** errmsg) 1125 { 1126 if (value < 0 || value > 28) 1127 *errmsg = _("value must be in the range 0 to 28"); 1128 return insn | (value << 20); 1129 } 1130 1131 static long long 1132 extract_nps_bitop_ins_ext (unsigned long long insn, 1133 bfd_boolean * invalid) 1134 { 1135 int value = (insn >> 20) & 0x1f; 1136 1137 if (value > 28) 1138 *invalid = TRUE; 1139 return value; 1140 } 1141 1142 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \ 1143 static unsigned long long \ 1144 insert_nps_##NAME (unsigned long long insn, \ 1145 long long value, \ 1146 const char ** errmsg) \ 1147 { \ 1148 if (value < 1 || value > UPPER) \ 1149 *errmsg = _("value must be in the range 1 to " #UPPER); \ 1150 if (value == UPPER) \ 1151 value = 0; \ 1152 return insn | (value << SHIFT); \ 1153 } \ 1154 \ 1155 static long long \ 1156 extract_nps_##NAME (unsigned long long insn, \ 1157 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 1158 { \ 1159 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \ 1160 if (value == 0) \ 1161 value = UPPER; \ 1162 return value; \ 1163 } 1164 1165 MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3) 1166 MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3) 1167 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3) 1168 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8) 1169 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3) 1170 MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2) 1171 MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6) 1172 1173 static unsigned long long 1174 insert_nps_min_hofs (unsigned long long insn, 1175 long long value, 1176 const char ** errmsg) 1177 { 1178 if (value < 0 || value > 240) 1179 *errmsg = _("value must be in the range 0 to 240"); 1180 if ((value % 16) != 0) 1181 *errmsg = _("value must be a multiple of 16"); 1182 value = value / 16; 1183 return insn | (value << 6); 1184 } 1185 1186 static long long 1187 extract_nps_min_hofs (unsigned long long insn, 1188 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1189 { 1190 int value = (insn >> 6) & 0xF; 1191 return value * 16; 1192 } 1193 1194 #define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \ 1195 static unsigned long long \ 1196 insert_nps_##NAME (unsigned long long insn, \ 1197 long long value, \ 1198 const char ** errmsg) \ 1199 { \ 1200 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \ 1201 *errmsg = _("invalid address type for operand"); \ 1202 return insn; \ 1203 } \ 1204 \ 1205 static long long \ 1206 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \ 1207 bfd_boolean * invalid ATTRIBUTE_UNUSED) \ 1208 { \ 1209 return ARC_NPS400_ADDRTYPE_##VALUE; \ 1210 } 1211 1212 MAKE_INSERT_NPS_ADDRTYPE (bd, BD) 1213 MAKE_INSERT_NPS_ADDRTYPE (jid, JID) 1214 MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD) 1215 MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD) 1216 MAKE_INSERT_NPS_ADDRTYPE (sd, SD) 1217 MAKE_INSERT_NPS_ADDRTYPE (sm, SM) 1218 MAKE_INSERT_NPS_ADDRTYPE (xa, XA) 1219 MAKE_INSERT_NPS_ADDRTYPE (xd, XD) 1220 MAKE_INSERT_NPS_ADDRTYPE (cd, CD) 1221 MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD) 1222 MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID) 1223 MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD) 1224 MAKE_INSERT_NPS_ADDRTYPE (cm, CM) 1225 MAKE_INSERT_NPS_ADDRTYPE (csd, CSD) 1226 MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA) 1227 MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD) 1228 1229 static unsigned long long 1230 insert_nps_rbdouble_64 (unsigned long long insn, 1231 long long value, 1232 const char ** errmsg) 1233 { 1234 if (value < 0 || value > 31) 1235 *errmsg = _("value must be in the range 0 to 31"); 1236 return insn | (value << 43) | (value << 48); 1237 } 1238 1239 1240 static long long 1241 extract_nps_rbdouble_64 (unsigned long long insn, 1242 bfd_boolean * invalid) 1243 { 1244 int value1 = (insn >> 43) & 0x1F; 1245 int value2 = (insn >> 48) & 0x1F; 1246 1247 if (value1 != value2) 1248 *invalid = TRUE; 1249 1250 return value1; 1251 } 1252 1253 static unsigned long long 1254 insert_nps_misc_imm_offset (unsigned long long insn, 1255 long long value, 1256 const char ** errmsg) 1257 { 1258 if (value & 0x3) 1259 { 1260 *errmsg = _("invalid position, should be one of: 0,4,8,...124."); 1261 value = 0; 1262 } 1263 insn |= (value << 6); 1264 return insn; 1265 } 1266 1267 static long long int 1268 extract_nps_misc_imm_offset (unsigned long long insn, 1269 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1270 { 1271 return ((insn >> 8) & 0x1f) * 4; 1272 } 1273 1274 static long long int 1275 extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED, 1276 bfd_boolean * invalid ATTRIBUTE_UNUSED) 1277 { 1278 int value = 0; 1279 1280 value |= ((insn >> 6) & 0x003f) << 0; 1281 value |= ((insn >> 0) & 0x003f) << 6; 1282 1283 return value; 1284 } 1285 1286 /* Include the generic extract/insert functions. Order is important 1287 as some of the functions present in the .h may be disabled via 1288 defines. */ 1289 #include "arc-fxi.h" 1290 1291 /* The flag operands table. 1292 1293 The format of the table is 1294 NAME CODE BITS SHIFT FAVAIL. */ 1295 const struct arc_flag_operand arc_flag_operands[] = 1296 { 1297 #define F_NULL 0 1298 { 0, 0, 0, 0, 0}, 1299 #define F_ALWAYS (F_NULL + 1) 1300 { "al", 0, 0, 0, 0 }, 1301 #define F_RA (F_ALWAYS + 1) 1302 { "ra", 0, 0, 0, 0 }, 1303 #define F_EQUAL (F_RA + 1) 1304 { "eq", 1, 5, 0, 1 }, 1305 #define F_ZERO (F_EQUAL + 1) 1306 { "z", 1, 5, 0, 0 }, 1307 #define F_NOTEQUAL (F_ZERO + 1) 1308 { "ne", 2, 5, 0, 1 }, 1309 #define F_NOTZERO (F_NOTEQUAL + 1) 1310 { "nz", 2, 5, 0, 0 }, 1311 #define F_POZITIVE (F_NOTZERO + 1) 1312 { "p", 3, 5, 0, 1 }, 1313 #define F_PL (F_POZITIVE + 1) 1314 { "pl", 3, 5, 0, 0 }, 1315 #define F_NEGATIVE (F_PL + 1) 1316 { "n", 4, 5, 0, 1 }, 1317 #define F_MINUS (F_NEGATIVE + 1) 1318 { "mi", 4, 5, 0, 0 }, 1319 #define F_CARRY (F_MINUS + 1) 1320 { "c", 5, 5, 0, 1 }, 1321 #define F_CARRYSET (F_CARRY + 1) 1322 { "cs", 5, 5, 0, 0 }, 1323 #define F_LOWER (F_CARRYSET + 1) 1324 { "lo", 5, 5, 0, 0 }, 1325 #define F_CARRYCLR (F_LOWER + 1) 1326 { "cc", 6, 5, 0, 0 }, 1327 #define F_NOTCARRY (F_CARRYCLR + 1) 1328 { "nc", 6, 5, 0, 1 }, 1329 #define F_HIGHER (F_NOTCARRY + 1) 1330 { "hs", 6, 5, 0, 0 }, 1331 #define F_OVERFLOWSET (F_HIGHER + 1) 1332 { "vs", 7, 5, 0, 0 }, 1333 #define F_OVERFLOW (F_OVERFLOWSET + 1) 1334 { "v", 7, 5, 0, 1 }, 1335 #define F_NOTOVERFLOW (F_OVERFLOW + 1) 1336 { "nv", 8, 5, 0, 1 }, 1337 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1) 1338 { "vc", 8, 5, 0, 0 }, 1339 #define F_GT (F_OVERFLOWCLR + 1) 1340 { "gt", 9, 5, 0, 1 }, 1341 #define F_GE (F_GT + 1) 1342 { "ge", 10, 5, 0, 1 }, 1343 #define F_LT (F_GE + 1) 1344 { "lt", 11, 5, 0, 1 }, 1345 #define F_LE (F_LT + 1) 1346 { "le", 12, 5, 0, 1 }, 1347 #define F_HI (F_LE + 1) 1348 { "hi", 13, 5, 0, 1 }, 1349 #define F_LS (F_HI + 1) 1350 { "ls", 14, 5, 0, 1 }, 1351 #define F_PNZ (F_LS + 1) 1352 { "pnz", 15, 5, 0, 1 }, 1353 #define F_NJ (F_PNZ + 1) 1354 { "nj", 21, 5, 0, 1 }, 1355 #define F_NM (F_NJ + 1) 1356 { "nm", 23, 5, 0, 1 }, 1357 #define F_NO_T (F_NM + 1) 1358 { "nt", 24, 5, 0, 1 }, 1359 1360 /* FLAG. */ 1361 #define F_FLAG (F_NO_T + 1) 1362 { "f", 1, 1, 15, 1 }, 1363 #define F_FFAKE (F_FLAG + 1) 1364 { "f", 0, 0, 0, 1 }, 1365 1366 /* Delay slot. */ 1367 #define F_ND (F_FFAKE + 1) 1368 { "nd", 0, 1, 5, 0 }, 1369 #define F_D (F_ND + 1) 1370 { "d", 1, 1, 5, 1 }, 1371 #define F_DFAKE (F_D + 1) 1372 { "d", 0, 0, 0, 1 }, 1373 #define F_DNZ_ND (F_DFAKE + 1) 1374 { "nd", 0, 1, 16, 0 }, 1375 #define F_DNZ_D (F_DNZ_ND + 1) 1376 { "d", 1, 1, 16, 1 }, 1377 1378 /* Data size. */ 1379 #define F_SIZEB1 (F_DNZ_D + 1) 1380 { "b", 1, 2, 1, 1 }, 1381 #define F_SIZEB7 (F_SIZEB1 + 1) 1382 { "b", 1, 2, 7, 1 }, 1383 #define F_SIZEB17 (F_SIZEB7 + 1) 1384 { "b", 1, 2, 17, 1 }, 1385 #define F_SIZEW1 (F_SIZEB17 + 1) 1386 { "w", 2, 2, 1, 0 }, 1387 #define F_SIZEW7 (F_SIZEW1 + 1) 1388 { "w", 2, 2, 7, 0 }, 1389 #define F_SIZEW17 (F_SIZEW7 + 1) 1390 { "w", 2, 2, 17, 0 }, 1391 1392 /* Sign extension. */ 1393 #define F_SIGN6 (F_SIZEW17 + 1) 1394 { "x", 1, 1, 6, 1 }, 1395 #define F_SIGN16 (F_SIGN6 + 1) 1396 { "x", 1, 1, 16, 1 }, 1397 #define F_SIGNX (F_SIGN16 + 1) 1398 { "x", 0, 0, 0, 1 }, 1399 1400 /* Address write-back modes. */ 1401 #define F_A3 (F_SIGNX + 1) 1402 { "a", 1, 2, 3, 0 }, 1403 #define F_A9 (F_A3 + 1) 1404 { "a", 1, 2, 9, 0 }, 1405 #define F_A22 (F_A9 + 1) 1406 { "a", 1, 2, 22, 0 }, 1407 #define F_AW3 (F_A22 + 1) 1408 { "aw", 1, 2, 3, 1 }, 1409 #define F_AW9 (F_AW3 + 1) 1410 { "aw", 1, 2, 9, 1 }, 1411 #define F_AW22 (F_AW9 + 1) 1412 { "aw", 1, 2, 22, 1 }, 1413 #define F_AB3 (F_AW22 + 1) 1414 { "ab", 2, 2, 3, 1 }, 1415 #define F_AB9 (F_AB3 + 1) 1416 { "ab", 2, 2, 9, 1 }, 1417 #define F_AB22 (F_AB9 + 1) 1418 { "ab", 2, 2, 22, 1 }, 1419 #define F_AS3 (F_AB22 + 1) 1420 { "as", 3, 2, 3, 1 }, 1421 #define F_AS9 (F_AS3 + 1) 1422 { "as", 3, 2, 9, 1 }, 1423 #define F_AS22 (F_AS9 + 1) 1424 { "as", 3, 2, 22, 1 }, 1425 #define F_ASFAKE (F_AS22 + 1) 1426 { "as", 0, 0, 0, 1 }, 1427 1428 /* Cache bypass. */ 1429 #define F_DI5 (F_ASFAKE + 1) 1430 { "di", 1, 1, 5, 1 }, 1431 #define F_DI11 (F_DI5 + 1) 1432 { "di", 1, 1, 11, 1 }, 1433 #define F_DI14 (F_DI11 + 1) 1434 { "di", 1, 1, 14, 1 }, 1435 #define F_DI15 (F_DI14 + 1) 1436 { "di", 1, 1, 15, 1 }, 1437 1438 /* ARCv2 specific. */ 1439 #define F_NT (F_DI15 + 1) 1440 { "nt", 0, 1, 3, 1}, 1441 #define F_T (F_NT + 1) 1442 { "t", 1, 1, 3, 1}, 1443 #define F_H1 (F_T + 1) 1444 { "h", 2, 2, 1, 1 }, 1445 #define F_H7 (F_H1 + 1) 1446 { "h", 2, 2, 7, 1 }, 1447 #define F_H17 (F_H7 + 1) 1448 { "h", 2, 2, 17, 1 }, 1449 #define F_SIZED (F_H17 + 1) 1450 { "dd", 8, 0, 0, 0 }, /* Fake. */ 1451 1452 /* Fake Flags. */ 1453 #define F_NE (F_SIZED + 1) 1454 { "ne", 0, 0, 0, 1 }, 1455 1456 /* ARC NPS400 Support: See comment near head of file. */ 1457 #define F_NPS_CL (F_NE + 1) 1458 { "cl", 0, 0, 0, 1 }, 1459 1460 #define F_NPS_NA (F_NPS_CL + 1) 1461 { "na", 1, 1, 9, 1 }, 1462 1463 #define F_NPS_SR (F_NPS_NA + 1) 1464 { "s", 1, 1, 13, 1 }, 1465 1466 #define F_NPS_M (F_NPS_SR + 1) 1467 { "m", 1, 1, 7, 1 }, 1468 1469 #define F_NPS_FLAG (F_NPS_M + 1) 1470 { "f", 1, 1, 20, 1 }, 1471 1472 #define F_NPS_R (F_NPS_FLAG + 1) 1473 { "r", 1, 1, 15, 1 }, 1474 1475 #define F_NPS_RW (F_NPS_R + 1) 1476 { "rw", 0, 1, 7, 1 }, 1477 1478 #define F_NPS_RD (F_NPS_RW + 1) 1479 { "rd", 1, 1, 7, 1 }, 1480 1481 #define F_NPS_WFT (F_NPS_RD + 1) 1482 { "wft", 0, 0, 0, 1 }, 1483 1484 #define F_NPS_IE1 (F_NPS_WFT + 1) 1485 { "ie1", 1, 2, 8, 1 }, 1486 1487 #define F_NPS_IE2 (F_NPS_IE1 + 1) 1488 { "ie2", 2, 2, 8, 1 }, 1489 1490 #define F_NPS_IE12 (F_NPS_IE2 + 1) 1491 { "ie12", 3, 2, 8, 1 }, 1492 1493 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1) 1494 { "rd", 0, 1, 6, 1 }, 1495 1496 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1) 1497 { "wr", 1, 1, 6, 1 }, 1498 1499 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1) 1500 { "off", 0, 0, 0, 1 }, 1501 1502 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1) 1503 { "restore", 0, 0, 0, 1 }, 1504 1505 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1) 1506 { "sx", 1, 1, 14, 1 }, 1507 1508 #define F_NPS_AR (F_NPS_SX + 1) 1509 { "ar", 0, 1, 0, 1 }, 1510 1511 #define F_NPS_AL (F_NPS_AR + 1) 1512 { "al", 1, 1, 0, 1 }, 1513 1514 #define F_NPS_S (F_NPS_AL + 1) 1515 { "s", 0, 0, 0, 1 }, 1516 1517 #define F_NPS_ZNCV_RD (F_NPS_S + 1) 1518 { "rd", 0, 1, 15, 1 }, 1519 1520 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1) 1521 { "wr", 1, 1, 15, 1 }, 1522 1523 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1) 1524 { "p0", 0, 0, 0, 1 }, 1525 1526 #define F_NPS_P1 (F_NPS_P0 + 1) 1527 { "p1", 0, 0, 0, 1 }, 1528 1529 #define F_NPS_P2 (F_NPS_P1 + 1) 1530 { "p2", 0, 0, 0, 1 }, 1531 1532 #define F_NPS_P3 (F_NPS_P2 + 1) 1533 { "p3", 0, 0, 0, 1 }, 1534 1535 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1) 1536 { "di", 0, 0, 0, 1 }, 1537 1538 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1) 1539 { "cl", 1, 1, 6, 1 }, 1540 1541 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1) 1542 { "cl", 1, 1, 16, 1 }, 1543 1544 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1) 1545 { "x2", 1, 2, 9, 1 }, 1546 1547 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1) 1548 { "x2", 1, 2, 22, 1 }, 1549 1550 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1) 1551 { "x4", 2, 2, 9, 1 }, 1552 1553 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1) 1554 { "x4", 2, 2, 22, 1 }, 1555 1556 #define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1) 1557 { "core", 1, 3, 6, 1 }, 1558 1559 #define F_NPS_CLSR (F_NPS_CORE + 1) 1560 { "clsr", 2, 3, 6, 1 }, 1561 1562 #define F_NPS_ALL (F_NPS_CLSR + 1) 1563 { "all", 3, 3, 6, 1 }, 1564 1565 #define F_NPS_GIC (F_NPS_ALL + 1) 1566 { "gic", 4, 3, 6, 1 }, 1567 1568 #define F_NPS_RSPI_GIC (F_NPS_GIC + 1) 1569 { "gic", 5, 3, 6, 1 }, 1570 }; 1571 1572 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); 1573 1574 /* Table of the flag classes. 1575 1576 The format of the table is 1577 CLASS {FLAG_CODE}. */ 1578 const struct arc_flag_class arc_flag_classes[] = 1579 { 1580 #define C_EMPTY 0 1581 { F_CLASS_NONE, { F_NULL } }, 1582 1583 #define C_CC_EQ (C_EMPTY + 1) 1584 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} }, 1585 1586 #define C_CC_GE (C_CC_EQ + 1) 1587 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} }, 1588 1589 #define C_CC_GT (C_CC_GE + 1) 1590 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} }, 1591 1592 #define C_CC_HI (C_CC_GT + 1) 1593 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} }, 1594 1595 #define C_CC_HS (C_CC_HI + 1) 1596 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} }, 1597 1598 #define C_CC_LE (C_CC_HS + 1) 1599 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} }, 1600 1601 #define C_CC_LO (C_CC_LE + 1) 1602 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} }, 1603 1604 #define C_CC_LS (C_CC_LO + 1) 1605 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} }, 1606 1607 #define C_CC_LT (C_CC_LS + 1) 1608 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} }, 1609 1610 #define C_CC_NE (C_CC_LT + 1) 1611 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} }, 1612 1613 #define C_AA_AB (C_CC_NE + 1) 1614 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} }, 1615 1616 #define C_AA_AW (C_AA_AB + 1) 1617 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} }, 1618 1619 #define C_ZZ_D (C_AA_AW + 1) 1620 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} }, 1621 1622 #define C_ZZ_H (C_ZZ_D + 1) 1623 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} }, 1624 1625 #define C_ZZ_B (C_ZZ_H + 1) 1626 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} }, 1627 1628 #define C_CC (C_ZZ_B + 1) 1629 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND, 1630 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, 1631 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, 1632 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 1633 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, 1634 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, 1635 F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } }, 1636 1637 #define C_AA_ADDR3 (C_CC + 1) 1638 #define C_AA27 (C_CC + 1) 1639 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, 1640 #define C_AA_ADDR9 (C_AA_ADDR3 + 1) 1641 #define C_AA21 (C_AA_ADDR3 + 1) 1642 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, 1643 #define C_AA_ADDR22 (C_AA_ADDR9 + 1) 1644 #define C_AA8 (C_AA_ADDR9 + 1) 1645 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, 1646 1647 #define C_F (C_AA_ADDR22 + 1) 1648 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } }, 1649 #define C_FHARD (C_F + 1) 1650 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } }, 1651 1652 #define C_T (C_FHARD + 1) 1653 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } }, 1654 #define C_D (C_T + 1) 1655 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } }, 1656 #define C_DNZ_D (C_D + 1) 1657 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } }, 1658 1659 #define C_DHARD (C_DNZ_D + 1) 1660 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } }, 1661 1662 #define C_DI20 (C_DHARD + 1) 1663 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }}, 1664 #define C_DI14 (C_DI20 + 1) 1665 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }}, 1666 #define C_DI16 (C_DI14 + 1) 1667 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }}, 1668 #define C_DI26 (C_DI16 + 1) 1669 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }}, 1670 1671 #define C_X25 (C_DI26 + 1) 1672 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }}, 1673 #define C_X15 (C_X25 + 1) 1674 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }}, 1675 #define C_XHARD (C_X15 + 1) 1676 #define C_X (C_X15 + 1) 1677 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }}, 1678 1679 #define C_ZZ13 (C_X + 1) 1680 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}}, 1681 #define C_ZZ23 (C_ZZ13 + 1) 1682 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}}, 1683 #define C_ZZ29 (C_ZZ23 + 1) 1684 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, 1685 1686 #define C_AS (C_ZZ29 + 1) 1687 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}}, 1688 1689 #define C_NE (C_AS + 1) 1690 { F_CLASS_OPTIONAL, { F_NE, F_NULL}}, 1691 1692 /* ARC NPS400 Support: See comment near head of file. */ 1693 #define C_NPS_CL (C_NE + 1) 1694 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}}, 1695 1696 #define C_NPS_NA (C_NPS_CL + 1) 1697 { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}}, 1698 1699 #define C_NPS_SR (C_NPS_NA + 1) 1700 { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}}, 1701 1702 #define C_NPS_M (C_NPS_SR + 1) 1703 { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}}, 1704 1705 #define C_NPS_F (C_NPS_M + 1) 1706 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, 1707 1708 #define C_NPS_R (C_NPS_F + 1) 1709 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}}, 1710 1711 #define C_NPS_SCHD_RW (C_NPS_R + 1) 1712 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}}, 1713 1714 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1) 1715 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}}, 1716 1717 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1) 1718 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}}, 1719 1720 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1) 1721 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}}, 1722 1723 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1) 1724 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}}, 1725 1726 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1) 1727 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}}, 1728 1729 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1) 1730 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}}, 1731 1732 #define C_NPS_AR_AL (C_NPS_SX + 1) 1733 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}}, 1734 1735 #define C_NPS_S (C_NPS_AR_AL + 1) 1736 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}}, 1737 1738 #define C_NPS_ZNCV (C_NPS_S + 1) 1739 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}}, 1740 1741 #define C_NPS_P0 (C_NPS_ZNCV + 1) 1742 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }}, 1743 1744 #define C_NPS_P1 (C_NPS_P0 + 1) 1745 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }}, 1746 1747 #define C_NPS_P2 (C_NPS_P1 + 1) 1748 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }}, 1749 1750 #define C_NPS_P3 (C_NPS_P2 + 1) 1751 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }}, 1752 1753 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1) 1754 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }}, 1755 1756 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1) 1757 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }}, 1758 1759 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1) 1760 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }}, 1761 1762 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1) 1763 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }}, 1764 1765 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1) 1766 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }}, 1767 1768 #define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1) 1769 { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}}, 1770 1771 #define C_NPS_CLSR (C_NPS_CORE + 1) 1772 { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}}, 1773 1774 #define C_NPS_ALL (C_NPS_CLSR + 1) 1775 { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}}, 1776 1777 #define C_NPS_GIC (C_NPS_ALL + 1) 1778 { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}}, 1779 1780 #define C_NPS_RSPI_GIC (C_NPS_GIC + 1) 1781 { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}}, 1782 }; 1783 1784 const unsigned char flags_none[] = { 0 }; 1785 const unsigned char flags_f[] = { C_F }; 1786 const unsigned char flags_cc[] = { C_CC }; 1787 const unsigned char flags_ccf[] = { C_CC, C_F }; 1788 1789 /* The operands table. 1790 1791 The format of the operands table is: 1792 1793 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ 1794 const struct arc_operand arc_operands[] = 1795 { 1796 /* The fields are bits, shift, insert, extract, flags. The zero 1797 index is used to indicate end-of-list. */ 1798 #define UNUSED 0 1799 { 0, 0, 0, 0, 0, 0 }, 1800 1801 #define IGNORED (UNUSED + 1) 1802 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 }, 1803 1804 /* The plain integer register fields. Used by 32 bit 1805 instructions. */ 1806 #define RA (IGNORED + 1) 1807 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, 1808 #define RA_CHK (RA + 1) 1809 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 }, 1810 #define RB (RA_CHK + 1) 1811 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, 1812 #define RB_CHK (RB + 1) 1813 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb }, 1814 #define RC (RB_CHK + 1) 1815 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, 1816 #define RBdup (RC + 1) 1817 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, 1818 1819 #define RAD (RBdup + 1) 1820 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, 1821 #define RCD (RAD + 1) 1822 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, 1823 1824 /* The plain integer register fields. Used by short 1825 instructions. */ 1826 #define RA16 (RCD + 1) 1827 #define RA_S (RCD + 1) 1828 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras }, 1829 #define RB16 (RA16 + 1) 1830 #define RB_S (RA16 + 1) 1831 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs }, 1832 #define RB16dup (RB16 + 1) 1833 #define RB_Sdup (RB16 + 1) 1834 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs }, 1835 #define RC16 (RB16dup + 1) 1836 #define RC_S (RB16dup + 1) 1837 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs }, 1838 #define R6H (RC16 + 1) /* 6bit register field 'h' used 1839 by V1 cpus. */ 1840 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 }, 1841 #define R5H (R6H + 1) /* 5bit register field 'h' used 1842 by V2 cpus. */ 1843 #define RH_S (R6H + 1) /* 5bit register field 'h' used 1844 by V2 cpus. */ 1845 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 }, 1846 #define R5Hdup (R5H + 1) 1847 #define RH_Sdup (R5H + 1) 1848 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, 1849 insert_rhv2, extract_rhv2 }, 1850 1851 #define RG (R5Hdup + 1) 1852 #define G_S (R5Hdup + 1) 1853 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s }, 1854 1855 /* Fix registers. */ 1856 #define R0 (RG + 1) 1857 #define R0_S (RG + 1) 1858 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 }, 1859 #define R1 (R0 + 1) 1860 #define R1_S (R0 + 1) 1861 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 }, 1862 #define R2 (R1 + 1) 1863 #define R2_S (R1 + 1) 1864 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 }, 1865 #define R3 (R2 + 1) 1866 #define R3_S (R2 + 1) 1867 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, 1868 #define RSP (R3 + 1) 1869 #define SP_S (R3 + 1) 1870 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, 1871 #define SPdup (RSP + 1) 1872 #define SP_Sdup (RSP + 1) 1873 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, 1874 #define GP (SPdup + 1) 1875 #define GP_S (SPdup + 1) 1876 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp }, 1877 1878 #define PCL_S (GP + 1) 1879 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl }, 1880 1881 #define BLINK (PCL_S + 1) 1882 #define BLINK_S (PCL_S + 1) 1883 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink }, 1884 1885 #define ILINK1 (BLINK + 1) 1886 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 }, 1887 #define ILINK2 (ILINK1 + 1) 1888 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 }, 1889 1890 /* Long immediate. */ 1891 #define LIMM (ILINK2 + 1) 1892 #define LIMM_S (ILINK2 + 1) 1893 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 }, 1894 #define LIMMdup (LIMM + 1) 1895 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 }, 1896 1897 /* Special operands. */ 1898 #define ZA (LIMMdup + 1) 1899 #define ZB (LIMMdup + 1) 1900 #define ZA_S (LIMMdup + 1) 1901 #define ZB_S (LIMMdup + 1) 1902 #define ZC_S (LIMMdup + 1) 1903 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 }, 1904 1905 #define RRANGE_EL (ZA + 1) 1906 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, 1907 insert_rrange, extract_rrange}, 1908 #define R13_EL (RRANGE_EL + 1) 1909 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, 1910 insert_r13el, extract_rrange }, 1911 #define FP_EL (R13_EL + 1) 1912 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, 1913 insert_fpel, extract_fpel }, 1914 #define BLINK_EL (FP_EL + 1) 1915 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, 1916 insert_blinkel, extract_blinkel }, 1917 #define PCL_EL (BLINK_EL + 1) 1918 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, 1919 insert_pclel, extract_pclel }, 1920 1921 /* Fake operand to handle the T flag. */ 1922 #define BRAKET (PCL_EL + 1) 1923 #define BRAKETdup (PCL_EL + 1) 1924 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 }, 1925 1926 /* Fake operand to handle the T flag. */ 1927 #define FKT_T (BRAKET + 1) 1928 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 }, 1929 /* Fake operand to handle the T flag. */ 1930 #define FKT_NT (FKT_T + 1) 1931 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 }, 1932 1933 /* UIMM6_20 mask = 00000000000000000000111111000000. */ 1934 #define UIMM6_20 (FKT_NT + 1) 1935 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20}, 1936 1937 /* Exactly like the above but used by relaxation. */ 1938 #define UIMM6_20R (UIMM6_20 + 1) 1939 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, 1940 insert_uimm6_20, extract_uimm6_20}, 1941 1942 /* SIMM12_20 mask = 00000000000000000000111111222222. */ 1943 #define SIMM12_20 (UIMM6_20R + 1) 1944 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20}, 1945 1946 /* Exactly like the above but used by relaxation. */ 1947 #define SIMM12_20R (SIMM12_20 + 1) 1948 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL, 1949 insert_simm12_20, extract_simm12_20}, 1950 1951 /* UIMM12_20 mask = 00000000000000000000111111222222. */ 1952 #define UIMM12_20 (SIMM12_20R + 1) 1953 {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20}, 1954 1955 /* SIMM3_5_S mask = 0000011100000000. */ 1956 #define SIMM3_5_S (UIMM12_20 + 1) 1957 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, 1958 insert_simm3s, extract_simm3s}, 1959 1960 /* UIMM7_A32_11_S mask = 0000000000011111. */ 1961 #define UIMM7_A32_11_S (SIMM3_5_S + 1) 1962 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 1963 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, 1964 extract_uimm7_a32_11_s}, 1965 1966 /* The same as above but used by relaxation. */ 1967 #define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1) 1968 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 1969 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL, 1970 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s}, 1971 1972 /* UIMM7_9_S mask = 0000000001111111. */ 1973 #define UIMM7_9_S (UIMM7_A32_11R_S + 1) 1974 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s}, 1975 1976 /* UIMM3_13_S mask = 0000000000000111. */ 1977 #define UIMM3_13_S (UIMM7_9_S + 1) 1978 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s}, 1979 1980 /* Exactly like the above but used for relaxation. */ 1981 #define UIMM3_13R_S (UIMM3_13_S + 1) 1982 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, 1983 insert_uimm3_13_s, extract_uimm3_13_s}, 1984 1985 /* SIMM11_A32_7_S mask = 0000000111111111. */ 1986 #define SIMM11_A32_7_S (UIMM3_13R_S + 1) 1987 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 1988 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s}, 1989 1990 /* UIMM6_13_S mask = 0000000002220111. */ 1991 #define UIMM6_13_S (SIMM11_A32_7_S + 1) 1992 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s}, 1993 /* UIMM5_11_S mask = 0000000000011111. */ 1994 #define UIMM5_11_S (UIMM6_13_S + 1) 1995 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, 1996 extract_uimm5_11_s}, 1997 1998 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ 1999 #define SIMM9_A16_8 (UIMM5_11_S + 1) 2000 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 2001 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, 2002 extract_simm9_a16_8}, 2003 2004 /* UIMM6_8 mask = 00000000000000000000111111000000. */ 2005 #define UIMM6_8 (SIMM9_A16_8 + 1) 2006 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8}, 2007 2008 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ 2009 #define SIMM21_A16_5 (UIMM6_8 + 1) 2010 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED 2011 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, 2012 insert_simm21_a16_5, extract_simm21_a16_5}, 2013 2014 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ 2015 #define SIMM25_A16_5 (SIMM21_A16_5 + 1) 2016 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED 2017 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, 2018 insert_simm25_a16_5, extract_simm25_a16_5}, 2019 2020 /* SIMM10_A16_7_S mask = 0000000111111111. */ 2021 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1) 2022 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 2023 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, 2024 extract_simm10_a16_7_s}, 2025 2026 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1) 2027 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 2028 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s}, 2029 2030 /* SIMM7_A16_10_S mask = 0000000000111111. */ 2031 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1) 2032 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 2033 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, 2034 extract_simm7_a16_10_s}, 2035 2036 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ 2037 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1) 2038 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 2039 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, 2040 extract_simm21_a32_5}, 2041 2042 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ 2043 #define SIMM25_A32_5 (SIMM21_A32_5 + 1) 2044 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 2045 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, 2046 extract_simm25_a32_5}, 2047 2048 /* SIMM13_A32_5_S mask = 0000011111111111. */ 2049 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1) 2050 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 2051 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, 2052 extract_simm13_a32_5_s}, 2053 2054 /* SIMM8_A16_9_S mask = 0000000001111111. */ 2055 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1) 2056 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 2057 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, 2058 extract_simm8_a16_9_s}, 2059 2060 /* UIMM10_6_S_JLIOFF mask = 0000001111111111. */ 2061 #define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1) 2062 {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED 2063 | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s, 2064 extract_uimm10_6_s}, 2065 2066 /* UIMM3_23 mask = 00000000000000000000000111000000. */ 2067 #define UIMM3_23 (UIMM10_6_S_JLIOFF + 1) 2068 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23}, 2069 2070 /* UIMM10_6_S mask = 0000001111111111. */ 2071 #define UIMM10_6_S (UIMM3_23 + 1) 2072 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s}, 2073 2074 /* UIMM6_11_S mask = 0000002200011110. */ 2075 #define UIMM6_11_S (UIMM10_6_S + 1) 2076 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s}, 2077 2078 /* SIMM9_8 mask = 00000000111111112000000000000000. */ 2079 #define SIMM9_8 (UIMM6_11_S + 1) 2080 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, 2081 insert_simm9_8, extract_simm9_8}, 2082 2083 /* The same as above but used by relaxation. */ 2084 #define SIMM9_8R (SIMM9_8 + 1) 2085 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE 2086 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8}, 2087 2088 /* UIMM10_A32_8_S mask = 0000000011111111. */ 2089 #define UIMM10_A32_8_S (SIMM9_8R + 1) 2090 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 2091 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, 2092 extract_uimm10_a32_8_s}, 2093 2094 /* SIMM9_7_S mask = 0000000111111111. */ 2095 #define SIMM9_7_S (UIMM10_A32_8_S + 1) 2096 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, 2097 extract_simm9_7_s}, 2098 2099 /* UIMM6_A16_11_S mask = 0000000000011111. */ 2100 #define UIMM6_A16_11_S (SIMM9_7_S + 1) 2101 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 2102 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, 2103 extract_uimm6_a16_11_s}, 2104 2105 /* UIMM5_A32_11_S mask = 0000020000011000. */ 2106 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1) 2107 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 2108 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, 2109 extract_uimm5_a32_11_s}, 2110 2111 /* SIMM11_A32_13_S mask = 0000022222200111. */ 2112 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1) 2113 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 2114 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s}, 2115 2116 /* UIMM7_13_S mask = 0000000022220111. */ 2117 #define UIMM7_13_S (SIMM11_A32_13_S + 1) 2118 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s}, 2119 2120 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ 2121 #define UIMM6_A16_21 (UIMM7_13_S + 1) 2122 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 2123 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21}, 2124 2125 /* UIMM7_11_S mask = 0000022200011110. */ 2126 #define UIMM7_11_S (UIMM6_A16_21 + 1) 2127 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s}, 2128 2129 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ 2130 #define UIMM7_A16_20 (UIMM7_11_S + 1) 2131 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 2132 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, 2133 extract_uimm7_a16_20}, 2134 2135 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ 2136 #define SIMM13_A16_20 (UIMM7_A16_20 + 1) 2137 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 2138 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, 2139 extract_simm13_a16_20}, 2140 2141 /* UIMM8_8_S mask = 0000000011111111. */ 2142 #define UIMM8_8_S (SIMM13_A16_20 + 1) 2143 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s}, 2144 2145 /* The same as above but used for relaxation. */ 2146 #define UIMM8_8R_S (UIMM8_8_S + 1) 2147 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL, 2148 insert_uimm8_8_s, extract_uimm8_8_s}, 2149 2150 /* W6 mask = 00000000000000000000111111000000. */ 2151 #define W6 (UIMM8_8R_S + 1) 2152 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6}, 2153 2154 /* UIMM6_5_S mask = 0000011111100000. */ 2155 #define UIMM6_5_S (W6 + 1) 2156 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, 2157 2158 /* ARC NPS400 Support: See comment near head of file. */ 2159 #define NPS_R_DST_3B (UIMM6_5_S + 1) 2160 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2161 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, 2162 2163 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1) 2164 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, 2165 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, 2166 2167 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1) 2168 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2169 insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 }, 2170 2171 #define NPS_R_DST (NPS_R_SRC2_3B + 1) 2172 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL }, 2173 2174 #define NPS_R_SRC1 (NPS_R_DST + 1) 2175 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, 2176 2177 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1) 2178 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, 2179 2180 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1) 2181 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, 2182 2183 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) 2184 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2185 insert_nps_bitop_size, extract_nps_bitop_size }, 2186 2187 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1) 2188 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 2189 insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size }, 2190 2191 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1) 2192 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2193 insert_nps_bitop_size_2b, extract_nps_bitop_size_2b }, 2194 2195 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1) 2196 { 8, 0, 0, ARC_OPERAND_UNSIGNED, 2197 insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 }, 2198 2199 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1) 2200 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2201 2202 #define NPS_SIMM16 (NPS_UIMM16 + 1) 2203 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL }, 2204 2205 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1) 2206 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2207 insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 }, 2208 2209 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1) 2210 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2211 insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 }, 2212 2213 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1) 2214 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2215 insert_nps_src2_pos, extract_nps_src2_pos }, 2216 2217 #define NPS_SRC1_POS (NPS_SRC2_POS + 1) 2218 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2219 insert_nps_src1_pos, extract_nps_src1_pos }, 2220 2221 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1) 2222 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2223 insert_nps_addb_size, extract_nps_addb_size }, 2224 2225 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1) 2226 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2227 insert_nps_andb_size, extract_nps_andb_size }, 2228 2229 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1) 2230 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2231 insert_nps_fxorb_size, extract_nps_fxorb_size }, 2232 2233 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1) 2234 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2235 insert_nps_wxorb_size, extract_nps_wxorb_size }, 2236 2237 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1) 2238 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL }, 2239 2240 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1) 2241 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2242 2243 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1) 2244 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2245 insert_nps_qcmp_size, extract_nps_qcmp_size }, 2246 2247 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1) 2248 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 }, 2249 2250 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1) 2251 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 }, 2252 2253 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1) 2254 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 }, 2255 2256 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1) 2257 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2258 insert_nps_calc_entry_size, extract_nps_calc_entry_size }, 2259 2260 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1) 2261 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2262 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, 2263 2264 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1) 2265 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, 2266 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst }, 2267 2268 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1) 2269 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2270 insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 }, 2271 2272 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1) 2273 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2274 insert_nps_bitop2_size, extract_nps_bitop2_size }, 2275 2276 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1) 2277 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2278 insert_nps_bitop1_size, extract_nps_bitop1_size }, 2279 2280 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1) 2281 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 2282 insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 }, 2283 2284 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1) 2285 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2286 2287 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1) 2288 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2289 2290 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1) 2291 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2292 2293 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1) 2294 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2295 2296 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1) 2297 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2298 2299 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1) 2300 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2301 2302 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1) 2303 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2304 2305 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1) 2306 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2307 2308 #define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1) 2309 { 2, 0, 0, ARC_OPERAND_UNSIGNED, 2310 insert_nps_bitop_mod4, extract_nps_bitop_mod4 }, 2311 2312 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1) 2313 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2314 2315 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1) 2316 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2317 2318 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1) 2319 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2320 2321 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1) 2322 { 5, 20, 0, ARC_OPERAND_UNSIGNED, 2323 insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext }, 2324 2325 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1) 2326 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2327 2328 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1) 2329 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2330 insert_nps_field_size, extract_nps_field_size }, 2331 2332 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1) 2333 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2334 insert_nps_shift_factor, extract_nps_shift_factor }, 2335 2336 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1) 2337 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2338 insert_nps_bits_to_scramble, extract_nps_bits_to_scramble }, 2339 2340 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1) 2341 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2342 2343 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1) 2344 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2345 insert_nps_bdlen_max_len, extract_nps_bdlen_max_len }, 2346 2347 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1) 2348 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2349 insert_nps_min_hofs, extract_nps_min_hofs }, 2350 2351 #define NPS_PSBC (NPS_MIN_HOFS + 1) 2352 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2353 2354 #define NPS_DPI_DST (NPS_PSBC + 1) 2355 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL }, 2356 2357 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B 2358 but doesn't duplicate an operand. */ 2359 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1) 2360 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2361 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst }, 2362 2363 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1) 2364 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2365 insert_nps_hash_width, extract_nps_hash_width }, 2366 2367 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1) 2368 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2369 2370 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1) 2371 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2372 2373 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1) 2374 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2375 2376 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1) 2377 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2378 insert_nps_hash_len, extract_nps_hash_len }, 2379 2380 #define NPS_HASH_OFS (NPS_HASH_LEN + 1) 2381 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2382 2383 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1) 2384 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2385 2386 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1) 2387 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2388 2389 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1) 2390 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2391 2392 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1) 2393 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2394 2395 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1) 2396 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2397 insert_nps_index3, extract_nps_index3 }, 2398 2399 #define COLON (NPS_E4BY_INDEX3 + 1) 2400 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL }, 2401 2402 #define NPS_BD (COLON + 1) 2403 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2404 insert_nps_bd, extract_nps_bd }, 2405 2406 #define NPS_JID (NPS_BD + 1) 2407 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2408 insert_nps_jid, extract_nps_jid }, 2409 2410 #define NPS_LBD (NPS_JID + 1) 2411 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2412 insert_nps_lbd, extract_nps_lbd }, 2413 2414 #define NPS_MBD (NPS_LBD + 1) 2415 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2416 insert_nps_mbd, extract_nps_mbd }, 2417 2418 #define NPS_SD (NPS_MBD + 1) 2419 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2420 insert_nps_sd, extract_nps_sd }, 2421 2422 #define NPS_SM (NPS_SD + 1) 2423 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2424 insert_nps_sm, extract_nps_sm }, 2425 2426 #define NPS_XA (NPS_SM + 1) 2427 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2428 insert_nps_xa, extract_nps_xa }, 2429 2430 #define NPS_XD (NPS_XA + 1) 2431 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2432 insert_nps_xd, extract_nps_xd }, 2433 2434 #define NPS_CD (NPS_XD + 1) 2435 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2436 insert_nps_cd, extract_nps_cd }, 2437 2438 #define NPS_CBD (NPS_CD + 1) 2439 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2440 insert_nps_cbd, extract_nps_cbd }, 2441 2442 #define NPS_CJID (NPS_CBD + 1) 2443 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2444 insert_nps_cjid, extract_nps_cjid }, 2445 2446 #define NPS_CLBD (NPS_CJID + 1) 2447 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2448 insert_nps_clbd, extract_nps_clbd }, 2449 2450 #define NPS_CM (NPS_CLBD + 1) 2451 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2452 insert_nps_cm, extract_nps_cm }, 2453 2454 #define NPS_CSD (NPS_CM + 1) 2455 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2456 insert_nps_csd, extract_nps_csd }, 2457 2458 #define NPS_CXA (NPS_CSD + 1) 2459 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2460 insert_nps_cxa, extract_nps_cxa }, 2461 2462 #define NPS_CXD (NPS_CXA + 1) 2463 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK, 2464 insert_nps_cxd, extract_nps_cxd }, 2465 2466 #define NPS_BD_TYPE (NPS_CXD + 1) 2467 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2468 2469 #define NPS_BMU_NUM (NPS_BD_TYPE + 1) 2470 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2471 insert_nps_bd_num_buff, extract_nps_bd_num_buff }, 2472 2473 #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1) 2474 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2475 2476 #define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1) 2477 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2478 insert_nps_size_16bit, extract_nps_size_16bit }, 2479 2480 #define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1) 2481 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2482 insert_nps_pmu_num_job, extract_nps_pmu_num_job }, 2483 2484 #define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1) 2485 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2486 insert_nps_imm_entry, extract_nps_imm_entry }, 2487 2488 #define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1) 2489 { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2490 insert_nps_imm_offset, extract_nps_imm_offset }, 2491 2492 #define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1) 2493 { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL }, 2494 2495 #define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1) 2496 { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2497 insert_nps_misc_imm_offset, extract_nps_misc_imm_offset }, 2498 2499 #define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1) 2500 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2501 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, 2502 2503 #define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1) 2504 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, 2505 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst }, 2506 2507 #define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1) 2508 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2509 insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 }, 2510 2511 #define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1) 2512 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2513 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, 2514 2515 #define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1) 2516 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, 2517 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst }, 2518 2519 #define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1) 2520 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2521 insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 }, 2522 2523 #define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1) 2524 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL }, 2525 2526 #define NPS_RB_64 (NPS_RA_64 + 1) 2527 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL }, 2528 2529 #define NPS_RBdup_64 (NPS_RB_64 + 1) 2530 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL }, 2531 2532 #define NPS_RBdouble_64 (NPS_RBdup_64 + 1) 2533 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, 2534 insert_nps_rbdouble_64, extract_nps_rbdouble_64 }, 2535 2536 #define NPS_RC_64 (NPS_RBdouble_64 + 1) 2537 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL }, 2538 2539 #define NPS_UIMM16_0_64 (NPS_RC_64 + 1) 2540 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, 2541 2542 #define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1) 2543 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 2544 insert_nps_proto_size, extract_nps_proto_size } 2545 }; 2546 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); 2547 2548 const unsigned arc_Toperand = FKT_T; 2549 const unsigned arc_NToperand = FKT_NT; 2550 2551 const unsigned char arg_none[] = { 0 }; 2552 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC }; 2553 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC }; 2554 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC }; 2555 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 }; 2556 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 }; 2557 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 }; 2558 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 }; 2559 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC }; 2560 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM }; 2561 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC }; 2562 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM }; 2563 2564 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM }; 2565 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 }; 2566 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 }; 2567 2568 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 }; 2569 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup }; 2570 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup }; 2571 2572 const unsigned char arg_32bit_rbrc[] = { RB, RC }; 2573 const unsigned char arg_32bit_zarc[] = { ZA, RC }; 2574 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 }; 2575 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 }; 2576 const unsigned char arg_32bit_rblimm[] = { RB, LIMM }; 2577 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM }; 2578 2579 const unsigned char arg_32bit_limmrc[] = { LIMM, RC }; 2580 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 }; 2581 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 }; 2582 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup }; 2583 2584 const unsigned char arg_32bit_rc[] = { RC }; 2585 const unsigned char arg_32bit_u6[] = { UIMM6_20 }; 2586 const unsigned char arg_32bit_limm[] = { LIMM }; 2587 2588 /* The opcode table. 2589 2590 The format of the opcode table is: 2591 2592 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. 2593 2594 The table is organised such that, where possible, all instructions with 2595 the same mnemonic are together in a block. When the assembler searches 2596 for a suitable instruction the entries are checked in table order, so 2597 more specific, or specialised cases should appear earlier in the table. 2598 2599 As an example, consider two instructions 'add a,b,u6' and 'add 2600 a,b,limm'. The first takes a 6-bit immediate that is encoded within the 2601 32-bit instruction, while the second takes a 32-bit immediate that is 2602 encoded in a follow-on 32-bit, making the total instruction length 2603 64-bits. In this case the u6 variant must appear first in the table, as 2604 all u6 immediates could also be encoded using the 'limm' extension, 2605 however, we want to use the shorter instruction wherever possible. 2606 2607 It is possible though to split instructions with the same mnemonic into 2608 multiple groups. However, the instructions are still checked in table 2609 order, even across groups. The only time that instructions with the 2610 same mnemonic should be split into different groups is when different 2611 variants of the instruction appear in different architectures, in which 2612 case, grouping all instructions from a particular architecture together 2613 might be preferable to merging the instruction into the main instruction 2614 table. 2615 2616 An example of this split instruction groups can be found with the 'sync' 2617 instruction. The core arc architecture provides a 'sync' instruction, 2618 while the nps instruction set extension provides 'sync.rd' and 2619 'sync.wr'. The rd/wr flags are instruction flags, not part of the 2620 mnemonic, so we end up with two groups for the sync instruction, the 2621 first within the core arc instruction table, and the second within the 2622 nps extension instructions. */ 2623 const struct arc_opcode arc_opcodes[] = 2624 { 2625 #include "arc-tbl.h" 2626 #include "arc-nps400-tbl.h" 2627 #include "arc-ext-tbl.h" 2628 2629 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } } 2630 }; 2631 2632 /* List with special cases instructions and the applicable flags. */ 2633 const struct arc_flag_special arc_flag_special_cases[] = 2634 { 2635 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2636 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2637 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2638 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, 2639 F_NO_T, F_NULL } }, 2640 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2641 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2642 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2643 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2644 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2645 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2646 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2647 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2648 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2649 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2650 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2651 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2652 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2653 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2654 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2655 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2656 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2657 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2658 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2659 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2660 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, 2661 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, 2662 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, 2663 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, 2664 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, 2665 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } 2666 }; 2667 2668 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); 2669 2670 /* Relocations. */ 2671 const struct arc_reloc_equiv_tab arc_reloc_equiv[] = 2672 { 2673 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL }, 2674 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2675 { "sda", "st", { F_ASFAKE, F_H1, F_NULL }, 2676 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2677 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL }, 2678 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2679 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL }, 2680 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 }, 2681 2682 /* Next two entries will cover the undefined behavior ldb/stb with 2683 address scaling. */ 2684 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL }, 2685 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, 2686 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL }, 2687 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST}, 2688 2689 { "sda", "ld", { F_ASFAKE, F_NULL }, 2690 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, 2691 { "sda", "st", { F_ASFAKE, F_NULL }, 2692 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, 2693 { "sda", "ldd", { F_ASFAKE, F_NULL }, 2694 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 }, 2695 { "sda", "std", { F_ASFAKE, F_NULL }, 2696 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2}, 2697 2698 /* Short instructions. */ 2699 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD }, 2700 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 }, 2701 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 }, 2702 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 }, 2703 2704 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME }, 2705 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST }, 2706 2707 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL, 2708 BFD_RELOC_ARC_S25H_PCREL_PLT }, 2709 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL, 2710 BFD_RELOC_ARC_S21H_PCREL_PLT }, 2711 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL, 2712 BFD_RELOC_ARC_S25W_PCREL_PLT }, 2713 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL, 2714 BFD_RELOC_ARC_S21W_PCREL_PLT }, 2715 2716 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 } 2717 }; 2718 2719 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); 2720 2721 const struct arc_pseudo_insn arc_pseudo_insns[] = 2722 { 2723 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, 2724 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, 2725 { BRAKETdup, 1, 0, 4} } }, 2726 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, 2727 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, 2728 { BRAKETdup, 1, 0, 4} } }, 2729 2730 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2731 { SIMM9_A16_8, 0, 0, 2 } } }, 2732 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2733 { SIMM9_A16_8, 0, 0, 2 } } }, 2734 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2735 { SIMM9_A16_8, 0, 0, 2 } } }, 2736 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2737 { SIMM9_A16_8, 0, 0, 2 } } }, 2738 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2739 { SIMM9_A16_8, 0, 0, 2 } } }, 2740 2741 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2742 { SIMM9_A16_8, 0, 0, 2 } } }, 2743 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2744 { SIMM9_A16_8, 0, 0, 2 } } }, 2745 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2746 { SIMM9_A16_8, 0, 0, 2 } } }, 2747 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2748 { SIMM9_A16_8, 0, 0, 2 } } }, 2749 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2750 { SIMM9_A16_8, 0, 0, 2 } } }, 2751 2752 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2753 { SIMM9_A16_8, 0, 0, 2 } } }, 2754 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2755 { SIMM9_A16_8, 0, 0, 2 } } }, 2756 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2757 { SIMM9_A16_8, 0, 0, 2 } } }, 2758 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2759 { SIMM9_A16_8, 0, 0, 2 } } }, 2760 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2761 { SIMM9_A16_8, 0, 0, 2 } } }, 2762 2763 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, 2764 { SIMM9_A16_8, 0, 0, 2 } } }, 2765 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2766 { SIMM9_A16_8, 0, 0, 2 } } }, 2767 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, 2768 { SIMM9_A16_8, 0, 0, 2 } } }, 2769 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, 2770 { SIMM9_A16_8, 0, 0, 2 } } }, 2771 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, 2772 { SIMM9_A16_8, 0, 0, 2 } } }, 2773 }; 2774 2775 const unsigned arc_num_pseudo_insn = 2776 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); 2777 2778 const struct arc_aux_reg arc_aux_regs[] = 2779 { 2780 #undef DEF 2781 #define DEF(ADDR, CPU, SUBCLASS, NAME) \ 2782 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, 2783 2784 #include "arc-regs.h" 2785 2786 #undef DEF 2787 }; 2788 2789 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); 2790 2791 /* NOTE: The order of this array MUST be consistent with 'enum 2792 arc_rlx_types' located in tc-arc.h! */ 2793 const struct arc_opcode arc_relax_opcodes[] = 2794 { 2795 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } }, 2796 2797 /* bl_s s13 11111sssssssssss. */ 2798 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2799 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2800 { SIMM13_A32_5_S }, { 0 }}, 2801 2802 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ 2803 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2804 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2805 { SIMM25_A32_5 }, { C_D }}, 2806 2807 /* b_s s10 1111000sssssssss. */ 2808 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2809 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2810 { SIMM10_A16_7_S }, { 0 }}, 2811 2812 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ 2813 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2814 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, 2815 { SIMM25_A16_5 }, { C_D }}, 2816 2817 /* add_s c,b,u3 01101bbbccc00uuu. */ 2818 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2819 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2820 { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, 2821 2822 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ 2823 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2824 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2825 { RA, RB, UIMM6_20R }, { C_F }}, 2826 2827 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ 2828 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2829 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2830 { RA, RB, LIMM }, { C_F }}, 2831 2832 /* ld_s c,b,u7 10000bbbcccuuuuu. */ 2833 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2834 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2835 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }}, 2836 2837 /* ld<.di><.aa><.x><zz> a,b,s9 2838 00010bbbssssssssSBBBDaaZZXAAAAAA. */ 2839 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2840 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2841 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup }, 2842 { C_ZZ23, C_DI20, C_AA21, C_X25 }}, 2843 2844 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ 2845 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2846 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2847 { RA, BRAKET, RB, LIMM, BRAKETdup }, 2848 { C_ZZ13, C_DI16, C_AA8, C_X15 }}, 2849 2850 /* mov_s b,u8 11011bbbuuuuuuuu. */ 2851 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2852 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2853 { RB_S, UIMM8_8R_S }, { 0 }}, 2854 2855 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ 2856 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2857 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2858 { RB, SIMM12_20R }, { C_F }}, 2859 2860 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ 2861 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2862 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2863 { RB, LIMM }, { C_F }}, 2864 2865 /* sub_s c,b,u3 01101bbbccc01uuu. */ 2866 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2867 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2868 { RC_S, RB_S, UIMM3_13R_S }, { 0 }}, 2869 2870 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ 2871 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2872 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2873 { RA, RB, UIMM6_20R }, { C_F }}, 2874 2875 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ 2876 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2877 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2878 { RA, RB, LIMM }, { C_F }}, 2879 2880 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ 2881 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM 2882 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }}, 2883 2884 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ 2885 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM 2886 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, 2887 2888 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ 2889 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2890 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2891 { RB, UIMM6_20R }, { C_F, C_CC }}, 2892 2893 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ 2894 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2895 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, 2896 { RB, LIMM }, { C_F, C_CC }}, 2897 2898 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ 2899 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2900 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2901 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }}, 2902 2903 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ 2904 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 2905 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, 2906 { RB, RBdup, LIMM }, { C_F, C_CC }} 2907 }; 2908 2909 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes); 2910 2911 /* Return length of an opcode in bytes. */ 2912 2913 int 2914 arc_opcode_len (const struct arc_opcode *opcode) 2915 { 2916 if (opcode->mask < 0x10000ull) 2917 return 2; 2918 2919 if (opcode->mask < 0x100000000ull) 2920 return 4; 2921 2922 if (opcode->mask < 0x1000000000000ull) 2923 return 6; 2924 2925 return 8; 2926 } 2927