12013-03-25 Tristan Gingold <gingold@adacore.com> 2 Backport of: 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com> 3 4 * lm32-desc.c: Regenerate. 5 62013-03-08 Christian Groessler <chris@groessler.org> 7 8 Backport from mainline: 9 10 2012-10-26 Christian Groessler <chris@groessler.org> 11 12 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb, 13 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove 14 non-existing opcode trtrb. 15 * z8k-opc.h: Regenerate. 16 172013-02-15 Yufeng Zhang <yufeng.zhang@arm.com> 18 19 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name' 20 fields to NULL. 21 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP. 22 232013-02-12 Yufeng Zhang <yufeng.zhang@arm.com> 24 25 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and 26 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2. 27 * aarch64-asm.c (convert_xtl_to_shll): New function. 28 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by 29 calling convert_xtl_to_shll. 30 * aarch64-dis.c (convert_shll_to_xtl): New function. 31 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by 32 calling convert_shll_to_xtl. 33 * aarch64-gen.c: Update copyright year. 34 * aarch64-asm-2.c: Re-generate. 35 * aarch64-dis-2.c: Re-generate. 36 * aarch64-opc-2.c: Re-generate. 37 382013-02-12 Yufeng Zhang <yufeng.zhang@arm.com> 39 40 * aarch64-opc.c (aarch64_print_operand): Change to print 41 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal 42 in comment. 43 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag 44 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and 45 OP_MOV_IMM_WIDE. 46 472013-02-12 Yufeng Zhang <yufeng.zhang@arm.com> 48 49 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, 50 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. 51 522013-02-12 Yufeng Zhang <yufeng.zhang@arm.com> 53 54 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and 55 rmr_el3; remove daifset and daifclr. 56 572013-02-12 Yufeng Zhang <yufeng.zhang@arm.com> 58 59 * aarch64-opc.c (operand_general_constraint_met_p): Change to 60 check the alignment of addr.offset.imm instead of that of 61 shifter.amount for operand type AARCH64_OPND_ADDR_UIMM12. 62 632013-01-22 Alan Modra <amodra@gmail.com> 64 65 Apply mainline patches 66 2012-12-13 Alan Modra <amodra@gmail.com> 67 PR binutils/14950 68 * ppc-opc.c (insert_sci8, extract_sci8): Rewrite. 69 (insert_sci8n, extract_sci8n): Likewise. 70 71 2012-11-23 Alan Modra <amodra@gmail.com> 72 * ppc-dis.c (ppc_parse_cpu): Add "sticky" param. Track bits 73 set from ppc_opts.sticky in it. Delete "retain_mask". 74 (powerpc_init_dialect): Choose default dialect from info->mach 75 before parsing -M options. Handle more bfd_mach_ppc variants. 76 Update common default to power7. 77 78 2012-10-26 Alan Modra <amodra@gmail.com> 79 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset. 80 81 2012-10-22 Peter Bergner <bergner@vnet.ibm.com> 82 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling. 83 84 2012-10-05 Peter Bergner <bergner@vnet.ibm.com> 85 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2; 86 * ppc-opc.c (VBA): New define. 87 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot, 88 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics. 89 902012-11-20 Kirill Yukhin <kirill.yukhin@intel.com> 91 H.J. Lu <hongjiu.lu@intel.com> 92 93 PR gas/14859 94 * i386-opc.tbl: Fix opcode for 64-bit jecxz. 95 * i386-tbl.h: Regenerated. 96 972012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com> 98 99 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS. 100 * i386-init.h: Regenerated. 101 1022012-11-05 Alan Modra <amodra@gmail.com> 103 104 * configure.in: Apply 2012-09-10 change to config.in here. 105 1062012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 107 108 * arm-dis.c: Changed ldra and strl-form mnemonics 109 to lda and stl-form. 110 1112012-09-18 Chao-ying Fu <fu@mips.com> 112 113 * micromips-opc.c (micromips_opcodes): Correct the encoding of 114 the "swxc1" instruction. 115 1162012-09-17 Yufeng Zhang <yufeng.zhang@arm.com> 117 118 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from 119 the parameter 'inst'. 120 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'. 121 (convert_mov_to_movewide): Change to assert (0) when 122 aarch64_wide_constant_p returns FALSE. 123 1242012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> 125 126 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and 127 CPU_BTVER2_FLAGS. 128 129 * i386-opc.h: Update CpuPRFCHW comment. 130 131 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. 132 * i386-init.h: Regenerated. 133 * i386-tbl.h: Likewise. 134 1352012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com> 136 137 PR gas/14423 138 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS. 139 * i386-init.h: Regenerated. 140 1412012-09-10 Matthias Klose <doko@ubuntu.com> 142 143 * config.in: Disable sanity check for kfreebsd. 144 1452012-08-14 Maciej W. Rozycki <macro@codesourcery.com> 146 147 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local 148 macros, use local variables for info struct member accesses, 149 update the type of the variable used to hold the instruction 150 word. 151 (print_insn_mips, print_mips16_insn_arg): Likewise. 152 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use 153 local variables for info struct member accesses. 154 (print_insn_micromips): Add GET_OP_S local macro. 155 (_print_insn_mips): Update the type of the variable used to hold 156 the instruction word. 157 1582012-08-13 Maciej W. Rozycki <macro@codesourcery.com> 159 160 * micromips-opc.c (micromips_opcodes): Update comment. 161 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor 162 instructions for IOCT as appropriate. 163 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with 164 opcode_is_member. 165 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with 166 the result of a check for the -Wno-missing-field-initializers 167 GCC option. 168 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. 169 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to 170 compilation. 171 (mips16-opc.lo): Likewise. 172 (micromips-opc.lo): Likewise. 173 * aclocal.m4: Regenerate. 174 * configure: Regenerate. 175 * Makefile.in: Regenerate. 176 1772012-08-01 Alan Modra <amodra@gmail.com> 178 179 * h8300-dis.c: Fix printf arg warnings. 180 * i960-dis.c: Likewise. 181 * mips-dis.c: Likewise. 182 * pdp11-dis.c: Likewise. 183 * sh-dis.c: Likewise. 184 * v850-dis.c: Likewise. 185 * configure.in: Formatting. 186 * configure: Regenerate. 187 * rl78-decode.c: Regenerate. 188 * po/POTFILES.in: Regenerate. 189 190 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases. 1912012-07-31 Chao-Ying Fu <fu@mips.com> 192 Catherine Moore <clm@codesourcery.com> 193 Maciej W. Rozycki <macro@codesourcery.com> 194 195 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. 196 (DSP_VOLA): Likewise. 197 (D32, D33): Likewise. 198 (micromips_opcodes): Add DSP ASE instructions. 199 * micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases. 200 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise. 201 2022012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> 203 204 * ia64-asmtab.h (completer_index): Extend bitfield to full uint. 205 * ia64-gen.c: Promote completer index type to longlong. 206 (irf_operand): Add new register recognition. 207 (in_iclass_mov_x): Add an entry for the new mov_* instruction type. 208 (lookup_specifier): Add new resource recognition. 209 (insert_bit_table_ent): Relax abort condition according to the 210 changed completer index type. 211 (print_dis_table): Fix printf format for completer index. 212 * ia64-ic.tbl: Add a new instruction class. 213 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions. 214 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions. 215 * ia64-opc.h: Define short names for new operand types. 216 * ia64-raw.tbl: Add new RAW resource for DAHR register. 217 * ia64-waw.tbl: Add new WAW resource for DAHR register. 218 * ia64-asmtab.c: Regenerate. 219 2202012-08-31 H.J. Lu <hongjiu.lu@intel.com> 221 222 Backport from mainline 223 2012-07-31 Jan Beulich <jbeulich@suse.com> 224 225 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2 226 instruction group. Mark as requiring AVX2. 227 * i386-tbl.h: Re-generate. 228 2292012-08-29 Peter Bergner <bergner@vnet.ibm.com> 230 231 Backport from mainline 232 2012-08-29 Peter Bergner <bergner@vnet.ibm.com> 233 * ppc-opc.c (VXASHB_MASK): New define. 234 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK. 235 2362012-08-28 Peter Bergner <bergner@vnet.ibm.com> 237 238 Backport from mainline 239 2012-08-15 Peter Bergner <bergner@vnet.ibm.com> 240 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics. 241 242 2012-08-15 Peter Bergner <bergner@vnet.ibm.com> 243 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR. 244 245 2012-08-16 Peter Bergner <bergner@vnet.ibm.com> 246 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and 247 RBX for the third operand. 248 <"lswi">: Use RAX for second and NBI for the third operand. 249 250 2012-08-20 Edmar Wienskoski <edmar@freescale.com> 251 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub, 252 vabsduh, vabsduw, mviwsplt. 253 254 2012-08-28 Peter Bergner <bergner@vnet.ibm.com> 255 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK, 256 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines. 257 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip, 258 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb, 259 vupklsh>: Use VXVA_MASK. 260 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK. 261 <mfvscr>: Use VXVAVB_MASK. 262 <mtvscr>: Use VXVDVA_MASK. 263 <vspltb>: Use VXUIMM4_MASK. 264 <vsplth>: Use VXUIMM3_MASK. 265 <vspltw>: Use VXUIMM2_MASK. 266 2672012-08-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 268 269 Apply mainline patches. 270 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 271 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions. 272 273 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 274 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions. 275 276 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 277 * arm-dis.c (neon_opcodes): Handle VMULL.P64. 278 279 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 280 * arm-dis.c (neon_opcodes): Add support for AES instructions. 281 282 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 283 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP 284 conversions. 285 286 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 287 * arm-dis.c (coprocessor_opcodes): Add VRINT. 288 (neon_opcodes): Likewise. 289 290 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 291 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT 292 variants. 293 (neon_opcodes): Likewise. 294 295 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 296 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM. 297 (neon_opcodes): Likewise. 298 299 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 300 * arm-dis.c (coprocessor_opcodes): Add VSEL. 301 (print_insn_coprocessor): Add new %<>c bitfield format 302 specifier. 303 304 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 305 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions. 306 (thumb32_opcodes): Likewise. 307 (print_arm_insn): Add support for %<>T formatter. 308 309 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 310 * arm-dis.c (arm_opcodes): Add HLT. 311 (thumb_opcodes): Likewise. 312 313 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 314 * arm-dis.c (thumb32_opcodes): Add DCPS instruction. 315 316 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 317 * arm-dis.c (arm_opcodes): Add SEVL. 318 (thumb_opcodes): Likewise. 319 (thumb32_opcodes): Likewise. 320 321 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> 322 * arm-dis.c (data_barrier_option): New function. 323 (print_insn_arm): Use data_barrier_option. 324 (print_insn_thumb32): Use data_barrier_option. 325 326 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com 327 * arm-dis.c (COND_UNCOND): New constant. 328 (print_insn_coprocessor): Add support for %u format specifier. 329 (print_insn_neon): Likewise. 330 3312012-08-17 Nick Clifton <nickc@redhat.com> 332 333 * po/uk.po: New Ukranian translation. 334 * configure.in (ALL_LINGUAS): Add uk. 335 * configure: Regenerate. 336 3372012-08-16 Ian Bolton <ian.bolton@arm.com> 338 Laurent Desnogues <laurent.desnogues@arm.com> 339 Jim MacArthur <jim.macarthur@arm.com> 340 Marcus Shawcroft <marcus.shawcroft@arm.com> 341 Nigel Stephens <nigel.stephens@arm.com> 342 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> 343 Richard Earnshaw <rearnsha@arm.com> 344 Sofiane Naci <sofiane.naci@arm.com> 345 Tejas Belagod <tejas.belagod@arm.com> 346 Yufeng Zhang <yufeng.zhang@arm.com> 347 348 * Makefile.am: Add AArch64. 349 * Makefile.in: Regenerate. 350 * aarch64-asm.c: New file. 351 * aarch64-asm.h: New file. 352 * aarch64-dis.c: New file. 353 * aarch64-dis.h: New file. 354 * aarch64-gen.c: New file. 355 * aarch64-opc.c: New file. 356 * aarch64-opc.h: New file. 357 * aarch64-tbl.h: New file. 358 * configure.in: Add AArch64. 359 * configure: Regenerate. 360 * disassemble.c: Add AArch64. 361 * aarch64-asm-2.c: New file (automatically generated). 362 * aarch64-dis-2.c: New file (automatically generated). 363 * aarch64-opc-2.c: New file (automatically generated). 364 * po/POTFILES.in: Regenerate. 365 3662012-08-09 Nick Clifton <nickc@redhat.com> 367 368 * po/vi.po: Updated Vietnamese translation. 369 3702012-07-30 Nick Clifton <nickc@redhat.com> 371 372 * po/opcodes.pot: Updated template. 373 * po/es.po: Updated Spanish translation. 374 * po/fi.po: Updated Finnish translation. 375 3762012-07-25 James Lemke <jwlemke@codesourcery.com> 377 378 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns. 379 3802012-07-24 Stephan McCamant <smcc@cs.berkeley.edu> 381 Dr David Alan Gilbert <dave@treblig.org> 382 383 PR binutils/13135 384 * arm-dis.c: Add necessary casts for printing integer values. 385 Use %s when printing string values. 386 * hppa-dis.c: Likewise. 387 * m68k-dis.c: Likewise. 388 * microblaze-dis.c: Likewise. 389 * mips-dis.c: Likewise. 390 * sparc-dis.c: Likewise. 391 3922012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com> 393 394 PR binutils/14355 395 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New. 396 (VEX_LEN_0FXOP_08_CD): Likewise. 397 (VEX_LEN_0FXOP_08_CE): Likewise. 398 (VEX_LEN_0FXOP_08_CF): Likewise. 399 (VEX_LEN_0FXOP_08_EC): Likewise. 400 (VEX_LEN_0FXOP_08_ED): Likewise. 401 (VEX_LEN_0FXOP_08_EE): Likewise. 402 (VEX_LEN_0FXOP_08_EF): Likewise. 403 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq, 404 vpcomub, vpcomuw, vpcomud, vpcomuq. 405 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC, 406 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF, 407 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE, 408 VEX_LEN_0FXOP_08_EF. 409 4102012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com> 411 412 * i386-dis.c (PREFIX_0F38F6): New. 413 (prefix_table): Add adcx, adox instructions. 414 (three_byte_table): Use PREFIX_0F38F6. 415 (mod_table): Add rdseed instruction. 416 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW. 417 (cpu_flags): Likewise. 418 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW. 419 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw. 420 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend 421 prefetchw. 422 * i386-tbl.h: Regenerate. 423 * i386-init.h: Likewise. 424 4252012-07-05 Thomas Schwinge <thomas@codesourcery.com> 426 427 * mips-dis.c: Remove gratuitous newline. 428 4292012-07-02 Roland McGrath <mcgrathr@google.com> 430 431 * i386-opc.tbl: Add RepPrefixOk to nop. 432 * i386-tbl.h: Regenerate. 433 4342012-06-28 Nick Clifton <nickc@redhat.com> 435 436 * po/vi.po: Updated Vietnamese translation. 437 4382012-06-22 Roland McGrath <mcgrathr@google.com> 439 440 * i386-opc.tbl: Add RepPrefixOk to ret. 441 * i386-tbl.h: Regenerate. 442 443 * i386-opc.h (RepPrefixOk): New enum constant. 444 (i386_opcode_modifier): New bitfield 'repprefixok'. 445 * i386-gen.c (opcode_modifiers): Add RepPrefixOk. 446 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all 447 instructions that have IsString. 448 * i386-tbl.h: Regenerate. 449 4502012-06-11 Andreas Schwab <schwab@linux-m68k.org> 451 452 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx) 453 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx) 454 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls) 455 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst) 456 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep) 457 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls) 458 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x) 459 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx) 460 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0. 461 4622012-05-19 Alan Modra <amodra@gmail.com> 463 464 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h. 465 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags. 466 4672012-05-18 Alan Modra <amodra@gmail.com> 468 469 * ia64-opc.c: Remove #include "ansidecl.h". 470 * z8kgen.c: Include sysdep.h first. 471 472 * arc-dis.c: Include sysdep.h first, remove some redundant includes. 473 * bfin-dis.c: Likewise. 474 * i860-dis.c: Likewise. 475 * ia64-dis.c: Likewise. 476 * ia64-gen.c: Likewise. 477 * m68hc11-dis.c: Likewise. 478 * mmix-dis.c: Likewise. 479 * msp430-dis.c: Likewise. 480 * or32-dis.c: Likewise. 481 * rl78-dis.c: Likewise. 482 * rx-dis.c: Likewise. 483 * tic4x-dis.c: Likewise. 484 * tilegx-opc.c: Likewise. 485 * tilepro-opc.c: Likewise. 486 * rx-decode.c: Regenerate. 487 4882012-05-17 James Lemke <jwlemke@codesourcery.com> 489 490 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi. 491 4922012-05-17 James Lemke <jwlemke@codesourcery.com> 493 494 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE. 495 4962012-05-17 Daniel Richard G. <skunk@iskunk.org> 497 Nick Clifton <nickc@redhat.com> 498 499 PR 14072 500 * configure.in: Add check that sysdep.h has been included before 501 any system header files. 502 * configure: Regenerate. 503 * config.in: Regenerate. 504 * sysdep.h: Generate an error if included before config.h. 505 * alpha-opc.c: Include sysdep.h before any other header file. 506 * alpha-dis.c: Likewise. 507 * avr-dis.c: Likewise. 508 * cgen-opc.c: Likewise. 509 * cr16-dis.c: Likewise. 510 * cris-dis.c: Likewise. 511 * crx-dis.c: Likewise. 512 * d10v-dis.c: Likewise. 513 * d10v-opc.c: Likewise. 514 * d30v-dis.c: Likewise. 515 * d30v-opc.c: Likewise. 516 * h8500-dis.c: Likewise. 517 * i370-dis.c: Likewise. 518 * i370-opc.c: Likewise. 519 * m10200-dis.c: Likewise. 520 * m10300-dis.c: Likewise. 521 * micromips-opc.c: Likewise. 522 * mips-opc.c: Likewise. 523 * mips61-opc.c: Likewise. 524 * moxie-dis.c: Likewise. 525 * or32-opc.c: Likewise. 526 * pj-dis.c: Likewise. 527 * ppc-dis.c: Likewise. 528 * ppc-opc.c: Likewise. 529 * s390-dis.c: Likewise. 530 * sh-dis.c: Likewise. 531 * sh64-dis.c: Likewise. 532 * sparc-dis.c: Likewise. 533 * sparc-opc.c: Likewise. 534 * spu-dis.c: Likewise. 535 * tic30-dis.c: Likewise. 536 * tic54x-dis.c: Likewise. 537 * tic80-dis.c: Likewise. 538 * tic80-opc.c: Likewise. 539 * tilegx-dis.c: Likewise. 540 * tilepro-dis.c: Likewise. 541 * v850-dis.c: Likewise. 542 * v850-opc.c: Likewise. 543 * vax-dis.c: Likewise. 544 * w65-dis.c: Likewise. 545 * xgate-dis.c: Likewise. 546 * xtensa-dis.c: Likewise. 547 * rl78-decode.opc: Likewise. 548 * rl78-decode.c: Regenerate. 549 * rx-decode.opc: Likewise. 550 * rx-decode.c: Regenerate. 551 5522012-05-17 Alan Modra <amodra@gmail.com> 553 554 * ppc_dis.c: Don't include elf/ppc.h. 555 5562012-05-16 Meador Inge <meadori@codesourcery.com> 557 558 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg} 559 to PUSH/POP {reg}. 560 5612012-05-15 James Murray <jsm@jsm-net.demon.co.uk> 562 Stephane Carrez <stcarrez@nerim.fr> 563 564 * configure.in: Add S12X and XGATE co-processor support to m68hc11 565 target. 566 * disassemble.c: Likewise. 567 * configure: Regenerate. 568 * m68hc11-dis.c: Make objdump output more consistent, use hex 569 instead of decimal and use 0x prefix for hex. 570 * m68hc11-opc.c: Add S12X and XGATE opcodes. 571 5722012-05-14 James Lemke <jwlemke@codesourcery.com> 573 574 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle. 575 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines. 576 (vle_opcd_indices): New array. 577 (lookup_vle): New function. 578 (disassemble_init_powerpc): Revise for second (VLE) opcode table. 579 (print_insn_powerpc): Likewise. 580 * ppc-opc.c: Likewise. 581 5822012-05-14 Catherine Moore <clm@codesourcery.com> 583 Maciej W. Rozycki <macro@codesourcery.com> 584 Rhonda Wittels <rhonda@codesourcery.com> 585 Nathan Froyd <froydnj@codesourcery.com> 586 587 * ppc-opc.c (insert_arx, extract_arx): New functions. 588 (insert_ary, extract_ary): New functions. 589 (insert_li20, extract_li20): New functions. 590 (insert_rx, extract_rx): New functions. 591 (insert_ry, extract_ry): New functions. 592 (insert_sci8, extract_sci8): New functions. 593 (insert_sci8n, extract_sci8n): New functions. 594 (insert_sd4h, extract_sd4h): New functions. 595 (insert_sd4w, extract_sd4w): New functions. 596 (insert_vlesi, extract_vlesi): New functions. 597 (insert_vlensi, extract_vlensi): New functions. 598 (insert_vleui, extract_vleui): New functions. 599 (insert_vleil, extract_vleil): New functions. 600 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT. 601 (BI16, BI32, BO32, B8): New. 602 (B15, B24, CRD32, CRS): New. 603 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG. 604 (DB, IMM20, RD, Rx, ARX, RY, RZ): New. 605 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New. 606 (SH6_MASK): Use PPC_OPSHIFT_INV. 607 (SI8, UI5, OIMM5, UI7, BO16): New. 608 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New. 609 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV. 610 (ALLOW8_SPRG): New. 611 (insert_sprg, extract_sprg): Check ALLOW8_SPRG. 612 (OPVUP, OPVUP_MASK OPVUP): New 613 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New. 614 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New. 615 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New. 616 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New. 617 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New. 618 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New. 619 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New. 620 (SE_IM5, SE_IM5_MASK): New. 621 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New. 622 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New. 623 (BO32DNZ, BO32DZ): New. 624 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE. 625 (PPCVLE): New. 626 (powerpc_opcodes): Add new VLE instructions. Update existing 627 instruction to include PPCVLE if supported. 628 * ppc-dis.c (ppc_opts): Add vle entry. 629 (get_powerpc_dialect): New function. 630 (powerpc_init_dialect): VLE support. 631 (print_insn_big_powerpc): Call get_powerpc_dialect. 632 (print_insn_little_powerpc): Likewise. 633 (operand_value_powerpc): Handle negative shift counts. 634 (print_insn_powerpc): Handle 2-byte instruction lengths. 635 6362012-05-11 Daniel Richard G. <skunk@iskunk.org> 637 638 PR binutils/14028 639 * configure.in: Invoke ACX_HEADER_STRING. 640 * configure: Regenerate. 641 * config.in: Regenerate. 642 * sysdep.h: If STRINGS_WITH_STRING is defined then include both 643 string.h and strings.h. 644 6452012-05-11 Nick Clifton <nickc@redhat.com> 646 647 PR binutils/14006 648 * arm-dis.c (print_insn): Fix detection of instruction mode in 649 files containing multiple executable sections. 650 6512012-05-03 Sean Keys <skeys@ipdatasys.com> 652 653 * Makefile.in, configure: regenerate 654 * disassemble.c (disassembler): Recognize ARCH_XGATE. 655 * xgate-dis.c (read_memory, print_insn, print_insn_xgate): 656 New functions. 657 * configure.in: Recognize xgate. 658 * xgate-dis.c, xgate-opc.c: New files for support of xgate 659 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly 660 and opcode generation for xgate. 661 6622012-04-30 DJ Delorie <dj@redhat.com> 663 664 * rx-decode.opc (MOV): Do not sign-extend immediates which are 665 already the maximum bit size. 666 * rx-decode.c: Regenerate. 667 6682012-04-27 David S. Miller <davem@davemloft.net> 669 670 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'. 671 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr. 672 673 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'. 674 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'. 675 676 * sparc-opc.c (CBCOND): New define. 677 (CBCOND_XCC): Likewise. 678 (cbcond): New helper macro. 679 (sparc_opcodes): Add compare-and-branch instructions. 680 681 * sparc-dis.c (print_insn_sparc): Handle ')'. 682 * sparc-opc.c (sparc_opcodes): Add crypto instructions. 683 684 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values 685 into new struct sparc_opcode 'hwcaps' field instead of 'flags'. 686 6872012-04-12 David S. Miller <davem@davemloft.net> 688 689 * sparc-dis.c (X_DISP10): Define. 690 (print_insn_sparc): Handle '='. 691 6922012-04-01 Mike Frysinger <vapier@gentoo.org> 693 694 * bfin-dis.c (fmtconst): Replace decimal handling with a single 695 sprintf call and the '*' field width. 696 6972012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com> 698 699 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP. 700 7012012-03-16 Alan Modra <amodra@gmail.com> 702 703 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete. 704 (powerpc_opcd_indices): Bump array size. 705 (disassemble_init_powerpc): Set powerpc_opcd_indices entries 706 corresponding to unused opcodes to following entry. 707 (lookup_powerpc): New function, extracted and optimised from.. 708 (print_insn_powerpc): ..here. 709 7102012-03-15 Alan Modra <amodra@gmail.com> 711 James Lemke <jwlemke@codesourcery.com> 712 713 * disassemble.c (disassemble_init_for_target): Handle ppc init. 714 * ppc-dis.c (private): New var. 715 (powerpc_init_dialect): Don't return calloc failure, instead use 716 private. 717 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define. 718 (powerpc_opcd_indices): New array. 719 (disassemble_init_powerpc): New function. 720 (print_insn_big_powerpc): Don't init dialect here. 721 (print_insn_little_powerpc): Likewise. 722 (print_insn_powerpc): Start search using powerpc_opcd_indices. 723 7242012-03-10 Edmar Wienskoski <edmar@freescale.com> 725 726 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". 727 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. 728 (PPCVEC2, PPCTMR, E6500): New short names. 729 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, 730 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, 731 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, 732 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, 733 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC 734 optional operands on sync instruction for E6500 target. 735 7362012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 737 738 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD. 739 7402012-02-27 Alan Modra <amodra@gmail.com> 741 742 * mt-dis.c: Regenerate. 743 7442012-02-27 Alan Modra <amodra@gmail.com> 745 746 * v850-opc.c (extract_v8): Rearrange to make it obvious this 747 is the inverse of corresponding insert function. 748 (extract_d22, extract_u9, extract_r4): Likewise. 749 (extract_d9): Correct sign extension. 750 (extract_d16_15): Don't assume "long" is 32 bits, and don't 751 rely on implementation defined behaviour for shift right of 752 signed types. 753 (extract_d16_16, extract_d17_16, extract_i9): Likewise. 754 (extract_d23): Likewise, and correct mask. 755 7562012-02-27 Alan Modra <amodra@gmail.com> 757 758 * crx-dis.c (print_arg): Mask constant to 32 bits. 759 * crx-opc.c (cst4_map): Use int array. 760 7612012-02-27 Alan Modra <amodra@gmail.com> 762 763 * arc-dis.c (BITS): Don't use shifts to mask off bits. 764 (FIELDD): Sign extend with xor,sub. 765 7662012-02-25 Walter Lee <walt@tilera.com> 767 768 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS. 769 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and 770 TILEPRO_OPC_LW_TLS_SN. 771 7722012-02-21 H.J. Lu <hongjiu.lu@intel.com> 773 774 * i386-opc.h (HLEPrefixNone): New. 775 (HLEPrefixLock): Likewise. 776 (HLEPrefixAny): Likewise. 777 (HLEPrefixRelease): Likewise. 778 7792012-02-08 H.J. Lu <hongjiu.lu@intel.com> 780 781 * i386-dis.c (HLE_Fixup1): New. 782 (HLE_Fixup2): Likewise. 783 (HLE_Fixup3): Likewise. 784 (Ebh1): Likewise. 785 (Evh1): Likewise. 786 (Ebh2): Likewise. 787 (Evh2): Likewise. 788 (Ebh3): Likewise. 789 (Evh3): Likewise. 790 (MOD_C6_REG_7): Likewise. 791 (MOD_C7_REG_7): Likewise. 792 (RM_C6_REG_7): Likewise. 793 (RM_C7_REG_7): Likewise. 794 (XACQUIRE_PREFIX): Likewise. 795 (XRELEASE_PREFIX): Likewise. 796 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, 797 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use 798 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. 799 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, 800 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use 801 MOD_C6_REG_7 and MOD_C7_REG_7. 802 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. 803 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and 804 xtest. 805 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. 806 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. 807 808 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and 809 CPU_RTM_FLAGS. 810 (cpu_flags): Add CpuHLE and CpuRTM. 811 (opcode_modifiers): Add HLEPrefixOk. 812 813 * i386-opc.h (CpuHLE): New. 814 (CpuRTM): Likewise. 815 (HLEPrefixOk): Likewise. 816 (i386_cpu_flags): Add cpuhle and cpurtm. 817 (i386_opcode_modifier): Add hleprefixok. 818 819 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to 820 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, 821 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory 822 operand. Add xacquire, xrelease, xabort, xbegin, xend and 823 xtest. 824 * i386-init.h: Regenerated. 825 * i386-tbl.h: Likewise. 826 8272012-01-24 DJ Delorie <dj@redhat.com> 828 829 * rl78-decode.opc (rl78_decode_opcode): Add NOT1. 830 * rl78-decode.c: Regenerate. 831 8322012-01-17 James Murray <jsm@jsm-net.demon.co.uk> 833 834 PR binutils/10173 835 * cr16-dis.c (print_arg): Test symtab_size not num_symbols. 836 8372012-01-17 Andreas Schwab <schwab@linux-m68k.org> 838 839 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx 840 register and move them after pmove with PSR/PCSR register. 841 8422012-01-13 H.J. Lu <hongjiu.lu@intel.com> 843 844 * i386-dis.c (mod_table): Add vmfunc. 845 846 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS. 847 (cpu_flags): CpuVMFUNC. 848 849 * i386-opc.h (CpuVMFUNC): New. 850 (i386_cpu_flags): Add cpuvmfunc. 851 852 * i386-opc.tbl: Add vmfunc. 853 * i386-init.h: Regenerated. 854 * i386-tbl.h: Likewise. 855 856For older changes see ChangeLog-2011 857 858Local Variables: 859mode: change-log 860left-margin: 8 861fill-column: 74 862version-control: never 863End: 864