1 /* riscv.h. RISC-V opcode list for GDB, the GNU debugger. 2 Copyright 2011 3 Free Software Foundation, Inc. 4 Contributed by Andrew Waterman 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 1, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21 22 #ifndef _RISCV_H_ 23 #define _RISCV_H_ 24 25 #include "riscv-opc.h" 26 #include <stdlib.h> 27 #include <stdint.h> 28 29 /* RVC fields */ 30 31 #define OP_MASK_CRD 0x1f 32 #define OP_SH_CRD 5 33 #define OP_MASK_CRS2 0x1f 34 #define OP_SH_CRS2 5 35 #define OP_MASK_CRS1 0x1f 36 #define OP_SH_CRS1 10 37 #define OP_MASK_CRDS 0x7 38 #define OP_SH_CRDS 13 39 #define OP_MASK_CRS2S 0x7 40 #define OP_SH_CRS2S 13 41 #define OP_MASK_CRS2BS 0x7 42 #define OP_SH_CRS2BS 5 43 #define OP_MASK_CRS1S 0x7 44 #define OP_SH_CRS1S 10 45 #define OP_MASK_CIMM6 0x3f 46 #define OP_SH_CIMM6 10 47 #define OP_MASK_CIMM5 0x1f 48 #define OP_SH_CIMM5 5 49 #define OP_MASK_CIMM10 0x3ff 50 #define OP_SH_CIMM10 5 51 52 static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 }; 53 #define rvc_rd_regmap rvc_rs1_regmap 54 #define rvc_rs2b_regmap rvc_rs1_regmap 55 static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 }; 56 57 typedef uint64_t insn_t; 58 59 static inline unsigned int riscv_insn_length (insn_t insn) 60 { 61 if ((insn & 0x3) != 3) /* RVC */ 62 return 2; 63 if ((insn & 0x1f) != 0x1f) /* base ISA and extensions in 32-bit space */ 64 return 4; 65 if ((insn & 0x3f) == 0x1f) /* 48-bit extensions */ 66 return 6; 67 if ((insn & 0x7f) == 0x3f) /* 64-bit extensions */ 68 return 8; 69 /* longer instructions not supported at the moment */ 70 return 2; 71 } 72 73 static const char * const riscv_rm[8] = { 74 "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn" 75 }; 76 static const char* const riscv_pred_succ[16] = { 77 0, "w", "r", "rw", "o", "ow", "or", "orw", 78 "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw", 79 }; 80 81 #define RVC_JUMP_BITS 10 82 #define RVC_JUMP_ALIGN_BITS 1 83 #define RVC_JUMP_ALIGN (1 << RVC_JUMP_ALIGN_BITS) 84 #define RVC_JUMP_REACH ((1ULL<<RVC_JUMP_BITS)*RVC_JUMP_ALIGN) 85 86 #define RVC_BRANCH_BITS 5 87 #define RVC_BRANCH_ALIGN_BITS RVC_JUMP_ALIGN_BITS 88 #define RVC_BRANCH_ALIGN (1 << RVC_BRANCH_ALIGN_BITS) 89 #define RVC_BRANCH_REACH ((1ULL<<RVC_BRANCH_BITS)*RVC_BRANCH_ALIGN) 90 91 #define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1)) 92 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) 93 94 #define EXTRACT_ITYPE_IMM(x) \ 95 (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) 96 #define EXTRACT_STYPE_IMM(x) \ 97 (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) 98 #define EXTRACT_SBTYPE_IMM(x) \ 99 ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) 100 #define EXTRACT_UTYPE_IMM(x) \ 101 ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) 102 #define EXTRACT_UJTYPE_IMM(x) \ 103 ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) 104 105 #define ENCODE_ITYPE_IMM(x) \ 106 (RV_X(x, 0, 12) << 20) 107 #define ENCODE_STYPE_IMM(x) \ 108 ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) 109 #define ENCODE_SBTYPE_IMM(x) \ 110 ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) 111 #define ENCODE_UTYPE_IMM(x) \ 112 (RV_X(x, 12, 20) << 12) 113 #define ENCODE_UJTYPE_IMM(x) \ 114 ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) 115 116 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) 117 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) 118 #define VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) 119 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) 120 #define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) 121 122 #define RISCV_RTYPE(insn, rd, rs1, rs2) \ 123 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) 124 #define RISCV_ITYPE(insn, rd, rs1, imm) \ 125 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) 126 #define RISCV_STYPE(insn, rs1, rs2, imm) \ 127 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) 128 #define RISCV_SBTYPE(insn, rs1, rs2, target) \ 129 ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target)) 130 #define RISCV_UTYPE(insn, rd, bigimm) \ 131 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) 132 #define RISCV_UJTYPE(insn, rd, target) \ 133 ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) 134 135 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) 136 137 #define RISCV_CONST_HIGH_PART(VALUE) \ 138 (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) 139 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) 140 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) 141 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) 142 143 /* RV fields */ 144 145 #define OP_MASK_OP 0x7f 146 #define OP_SH_OP 0 147 #define OP_MASK_RS2 0x1f 148 #define OP_SH_RS2 20 149 #define OP_MASK_RS1 0x1f 150 #define OP_SH_RS1 15 151 #define OP_MASK_RS3 0x1f 152 #define OP_SH_RS3 27 153 #define OP_MASK_RD 0x1f 154 #define OP_SH_RD 7 155 #define OP_MASK_SHAMT 0x3f 156 #define OP_SH_SHAMT 20 157 #define OP_MASK_SHAMTW 0x1f 158 #define OP_SH_SHAMTW 20 159 #define OP_MASK_RM 0x7 160 #define OP_SH_RM 12 161 #define OP_MASK_PRED 0xf 162 #define OP_SH_PRED 24 163 #define OP_MASK_SUCC 0xf 164 #define OP_SH_SUCC 20 165 #define OP_MASK_AQ 0x1 166 #define OP_SH_AQ 26 167 #define OP_MASK_RL 0x1 168 #define OP_SH_RL 25 169 170 #define OP_MASK_VRD 0x1f 171 #define OP_SH_VRD 7 172 #define OP_MASK_VRS 0x1f 173 #define OP_SH_VRS 15 174 #define OP_MASK_VRT 0x1f 175 #define OP_SH_VRT 20 176 #define OP_MASK_VRR 0x1f 177 #define OP_SH_VRR 27 178 179 #define OP_MASK_VFD 0x1f 180 #define OP_SH_VFD 7 181 #define OP_MASK_VFS 0x1f 182 #define OP_SH_VFS 15 183 #define OP_MASK_VFT 0x1f 184 #define OP_SH_VFT 20 185 #define OP_MASK_VFR 0x1f 186 #define OP_SH_VFR 27 187 188 #define OP_MASK_IMMNGPR 0x3f 189 #define OP_SH_IMMNGPR 20 190 #define OP_MASK_IMMNFPR 0x3f 191 #define OP_SH_IMMNFPR 26 192 #define OP_MASK_IMMSEGNELM 0x7 193 #define OP_SH_IMMSEGNELM 29 194 #define OP_MASK_CUSTOM_IMM 0x7f 195 #define OP_SH_CUSTOM_IMM 25 196 #define OP_MASK_CSR 0xfff 197 #define OP_SH_CSR 20 198 199 #define X_RA 1 200 #define X_SP 2 201 #define X_GP 3 202 #define X_TP 4 203 #define X_T0 5 204 #define X_T1 6 205 #define X_T2 7 206 #define X_T3 28 207 208 #define NGPR 32 209 #define NFPR 32 210 #define NVGPR 32 211 #define NVFPR 32 212 213 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS 214 #define RISCV_JUMP_ALIGN_BITS 1 215 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) 216 #define RISCV_JUMP_REACH ((1ULL<<RISCV_JUMP_BITS)*RISCV_JUMP_ALIGN) 217 218 #define RISCV_IMM_BITS 12 219 #define RISCV_BIGIMM_BITS (32-RISCV_IMM_BITS) 220 #define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS) 221 #define RISCV_BIGIMM_REACH (1LL<<RISCV_BIGIMM_BITS) 222 #define RISCV_BRANCH_BITS RISCV_IMM_BITS 223 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS 224 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) 225 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH*RISCV_BRANCH_ALIGN) 226 227 /* This structure holds information for a particular instruction. */ 228 229 struct riscv_opcode 230 { 231 /* The name of the instruction. */ 232 const char *name; 233 /* The ISA subset name (I, M, A, F, D, Xextension). */ 234 const char *subset; 235 /* A string describing the arguments for this instruction. */ 236 const char *args; 237 /* The basic opcode for the instruction. When assembling, this 238 opcode is modified by the arguments to produce the actual opcode 239 that is used. If pinfo is INSN_MACRO, then this is 0. */ 240 insn_t match; 241 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 242 relevant portions of the opcode when disassembling. If the 243 actual opcode anded with the match field equals the opcode field, 244 then we have found the correct instruction. If pinfo is 245 INSN_MACRO, then this field is the macro identifier. */ 246 insn_t mask; 247 /* A function to determine if a word corresponds to this instruction. 248 Usually, this computes ((word & mask) == match). */ 249 int (*match_func)(const struct riscv_opcode *op, insn_t word); 250 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 251 of bits describing the instruction, notably any relevant hazard 252 information. */ 253 unsigned long pinfo; 254 }; 255 256 #define INSN_WRITE_GPR_D 0x00000001 257 #define INSN_WRITE_GPR_RA 0x00000004 258 #define INSN_WRITE_FPR_D 0x00000008 259 #define INSN_READ_GPR_S 0x00000040 260 #define INSN_READ_GPR_T 0x00000080 261 #define INSN_READ_FPR_S 0x00000100 262 #define INSN_READ_FPR_T 0x00000200 263 #define INSN_READ_FPR_R 0x00000400 264 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 265 #define INSN_ALIAS 0x00001000 266 /* Instruction is actually a macro. It should be ignored by the 267 disassembler, and requires special treatment by the assembler. */ 268 #define INSN_MACRO 0xffffffff 269 270 /* This is a list of macro expanded instructions. 271 272 _I appended means immediate 273 _A appended means address 274 _AB appended means address with base register 275 _D appended means 64 bit floating point constant 276 _S appended means 32 bit floating point constant. */ 277 278 enum 279 { 280 M_LA, 281 M_LLA, 282 M_LA_TLS_GD, 283 M_LA_TLS_IE, 284 M_LB, 285 M_LBU, 286 M_LH, 287 M_LHU, 288 M_LW, 289 M_LWU, 290 M_LD, 291 M_SB, 292 M_SH, 293 M_SW, 294 M_SD, 295 M_FLW, 296 M_FLD, 297 M_FSW, 298 M_FSD, 299 M_CALL, 300 M_J, 301 M_LI, 302 M_VF, 303 M_NUM_MACROS 304 }; 305 306 307 extern const char * const riscv_gpr_names_numeric[NGPR]; 308 extern const char * const riscv_gpr_names_abi[NGPR]; 309 extern const char * const riscv_fpr_names_numeric[NFPR]; 310 extern const char * const riscv_fpr_names_abi[NFPR]; 311 extern const char * const riscv_vec_gpr_names[NVGPR]; 312 extern const char * const riscv_vec_fpr_names[NVFPR]; 313 314 extern const struct riscv_opcode riscv_builtin_opcodes[]; 315 extern const int bfd_riscv_num_builtin_opcodes; 316 extern struct riscv_opcode *riscv_opcodes; 317 extern int bfd_riscv_num_opcodes; 318 #define NUMOPCODES bfd_riscv_num_opcodes 319 320 #endif /* _RISCV_H_ */ 321