1 /* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright (C) 1993-2020 Free Software Foundation, Inc. 3 Contributed by Ralph Campbell and OSF 4 Commented and modified by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 3, 11 or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING3. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #ifndef _MIPS_H_ 24 #define _MIPS_H_ 25 26 #include "bfd.h" 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /* These are bit masks and shift counts to use to access the various 33 fields of an instruction. To retrieve the X field of an 34 instruction, use the expression 35 (i >> OP_SH_X) & OP_MASK_X 36 To set the same field (to j), use 37 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 38 39 Make sure you use fields that are appropriate for the instruction, 40 of course. 41 42 The 'i' format uses OP, RS, RT and IMMEDIATE. 43 44 The 'j' format uses OP and TARGET. 45 46 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 47 48 The 'b' format uses OP, RS, RT and DELTA. 49 50 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 51 52 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 53 54 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 55 breakpoint instruction are not defined; Kane says the breakpoint 56 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 57 only use ten bits). An optional two-operand form of break/sdbbp 58 allows the lower ten bits to be set too, and MIPS32 and later 59 architectures allow 20 bits to be set with a single operand for 60 the sdbbp instruction (using CODE20). 61 62 The syscall instruction uses CODE20. 63 64 The general coprocessor instructions use COPZ. */ 65 66 #define OP_MASK_OP 0x3f 67 #define OP_SH_OP 26 68 #define OP_MASK_RS 0x1f 69 #define OP_SH_RS 21 70 #define OP_MASK_FR 0x1f 71 #define OP_SH_FR 21 72 #define OP_MASK_FMT 0x1f 73 #define OP_SH_FMT 21 74 #define OP_MASK_BCC 0x7 75 #define OP_SH_BCC 18 76 #define OP_MASK_CODE 0x3ff 77 #define OP_SH_CODE 16 78 #define OP_MASK_CODE2 0x3ff 79 #define OP_SH_CODE2 6 80 #define OP_MASK_RT 0x1f 81 #define OP_SH_RT 16 82 #define OP_MASK_FT 0x1f 83 #define OP_SH_FT 16 84 #define OP_MASK_CACHE 0x1f 85 #define OP_SH_CACHE 16 86 #define OP_MASK_RD 0x1f 87 #define OP_SH_RD 11 88 #define OP_MASK_FS 0x1f 89 #define OP_SH_FS 11 90 #define OP_MASK_PREFX 0x1f 91 #define OP_SH_PREFX 11 92 #define OP_MASK_CCC 0x7 93 #define OP_SH_CCC 8 94 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 95 #define OP_SH_CODE20 6 96 #define OP_MASK_SHAMT 0x1f 97 #define OP_SH_SHAMT 6 98 #define OP_MASK_EXTLSB OP_MASK_SHAMT 99 #define OP_SH_EXTLSB OP_SH_SHAMT 100 #define OP_MASK_STYPE OP_MASK_SHAMT 101 #define OP_SH_STYPE OP_SH_SHAMT 102 #define OP_MASK_FD 0x1f 103 #define OP_SH_FD 6 104 #define OP_MASK_TARGET 0x3ffffff 105 #define OP_SH_TARGET 0 106 #define OP_MASK_COPZ 0x1ffffff 107 #define OP_SH_COPZ 0 108 #define OP_MASK_IMMEDIATE 0xffff 109 #define OP_SH_IMMEDIATE 0 110 #define OP_MASK_DELTA 0xffff 111 #define OP_SH_DELTA 0 112 #define OP_MASK_FUNCT 0x3f 113 #define OP_SH_FUNCT 0 114 #define OP_MASK_SPEC 0x3f 115 #define OP_SH_SPEC 0 116 #define OP_SH_LOCC 8 /* FP condition code. */ 117 #define OP_SH_HICC 18 /* FP condition code. */ 118 #define OP_MASK_CC 0x7 119 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 120 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 121 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 122 #define OP_MASK_COP1SPEC 0xf 123 #define OP_MASK_COP1SCLR 0x4 124 #define OP_MASK_COP1CMP 0x3 125 #define OP_SH_COP1CMP 4 126 #define OP_SH_FORMAT 21 /* FP short format field. */ 127 #define OP_MASK_FORMAT 0x7 128 #define OP_SH_TRUE 16 129 #define OP_MASK_TRUE 0x1 130 #define OP_SH_GE 17 131 #define OP_MASK_GE 0x01 132 #define OP_SH_UNSIGNED 16 133 #define OP_MASK_UNSIGNED 0x1 134 #define OP_SH_HINT 16 135 #define OP_MASK_HINT 0x1f 136 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 137 #define OP_MASK_MMI 0x3f 138 #define OP_SH_MMISUB 6 139 #define OP_MASK_MMISUB 0x1f 140 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 141 #define OP_SH_PERFREG 1 142 #define OP_SH_SEL 0 /* Coprocessor select field. */ 143 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 144 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 145 #define OP_MASK_CODE19 0x7ffff 146 #define OP_SH_ALN 21 147 #define OP_MASK_ALN 0x7 148 #define OP_SH_VSEL 21 149 #define OP_MASK_VSEL 0x1f 150 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 151 but 0x8-0xf don't select bytes. */ 152 #define OP_SH_VECBYTE 22 153 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 154 #define OP_SH_VECALIGN 21 155 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 156 #define OP_SH_INSMSB 11 157 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 158 #define OP_SH_EXTMSBD 11 159 160 /* MIPS DSP ASE */ 161 #define OP_SH_DSPACC 11 162 #define OP_MASK_DSPACC 0x3 163 #define OP_SH_DSPACC_S 21 164 #define OP_MASK_DSPACC_S 0x3 165 #define OP_SH_DSPSFT 20 166 #define OP_MASK_DSPSFT 0x3f 167 #define OP_SH_DSPSFT_7 19 168 #define OP_MASK_DSPSFT_7 0x7f 169 #define OP_SH_SA3 21 170 #define OP_MASK_SA3 0x7 171 #define OP_SH_SA4 21 172 #define OP_MASK_SA4 0xf 173 #define OP_SH_IMM8 16 174 #define OP_MASK_IMM8 0xff 175 #define OP_SH_IMM10 16 176 #define OP_MASK_IMM10 0x3ff 177 #define OP_SH_WRDSP 11 178 #define OP_MASK_WRDSP 0x3f 179 #define OP_SH_RDDSP 16 180 #define OP_MASK_RDDSP 0x3f 181 #define OP_SH_BP 11 182 #define OP_MASK_BP 0x3 183 184 /* MIPS MT ASE */ 185 #define OP_SH_MT_U 5 186 #define OP_MASK_MT_U 0x1 187 #define OP_SH_MT_H 4 188 #define OP_MASK_MT_H 0x1 189 #define OP_SH_MTACC_T 18 190 #define OP_MASK_MTACC_T 0x3 191 #define OP_SH_MTACC_D 13 192 #define OP_MASK_MTACC_D 0x3 193 194 /* MIPS MCU ASE */ 195 #define OP_MASK_3BITPOS 0x7 196 #define OP_SH_3BITPOS 12 197 #define OP_MASK_OFFSET12 0xfff 198 #define OP_SH_OFFSET12 0 199 200 #define OP_OP_COP0 0x10 201 #define OP_OP_COP1 0x11 202 #define OP_OP_COP2 0x12 203 #define OP_OP_COP3 0x13 204 #define OP_OP_LWC1 0x31 205 #define OP_OP_LWC2 0x32 206 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 207 #define OP_OP_LDC1 0x35 208 #define OP_OP_LDC2 0x36 209 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 210 #define OP_OP_SWC1 0x39 211 #define OP_OP_SWC2 0x3a 212 #define OP_OP_SWC3 0x3b 213 #define OP_OP_SDC1 0x3d 214 #define OP_OP_SDC2 0x3e 215 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 216 217 /* MIPS VIRT ASE */ 218 #define OP_MASK_CODE10 0x3ff 219 #define OP_SH_CODE10 11 220 221 /* Values in the 'VSEL' field. */ 222 #define MDMX_FMTSEL_IMM_QH 0x1d 223 #define MDMX_FMTSEL_IMM_OB 0x1e 224 #define MDMX_FMTSEL_VEC_QH 0x15 225 #define MDMX_FMTSEL_VEC_OB 0x16 226 227 /* UDI */ 228 #define OP_SH_UDI1 6 229 #define OP_MASK_UDI1 0x1f 230 #define OP_SH_UDI2 6 231 #define OP_MASK_UDI2 0x3ff 232 #define OP_SH_UDI3 6 233 #define OP_MASK_UDI3 0x7fff 234 #define OP_SH_UDI4 6 235 #define OP_MASK_UDI4 0xfffff 236 237 /* Octeon */ 238 #define OP_SH_BBITIND 16 239 #define OP_MASK_BBITIND 0x1f 240 #define OP_SH_CINSPOS 6 241 #define OP_MASK_CINSPOS 0x1f 242 #define OP_SH_CINSLM1 11 243 #define OP_MASK_CINSLM1 0x1f 244 #define OP_SH_SEQI 6 245 #define OP_MASK_SEQI 0x3ff 246 247 /* Loongson */ 248 #define OP_SH_OFFSET_A 6 249 #define OP_MASK_OFFSET_A 0xff 250 #define OP_SH_OFFSET_B 3 251 #define OP_MASK_OFFSET_B 0xff 252 #define OP_SH_OFFSET_C 6 253 #define OP_MASK_OFFSET_C 0x1ff 254 #define OP_SH_RZ 0 255 #define OP_MASK_RZ 0x1f 256 #define OP_SH_FZ 0 257 #define OP_MASK_FZ 0x1f 258 259 /* Every MICROMIPSOP_X definition requires a corresponding OP_X 260 definition, and vice versa. This simplifies various parts 261 of the operand handling in GAS. The fields below only exist 262 in the microMIPS encoding, so define each one to have an empty 263 range. */ 264 #define OP_MASK_TRAP 0 265 #define OP_SH_TRAP 0 266 #define OP_MASK_OFFSET10 0 267 #define OP_SH_OFFSET10 0 268 #define OP_MASK_RS3 0 269 #define OP_SH_RS3 0 270 #define OP_MASK_MB 0 271 #define OP_SH_MB 0 272 #define OP_MASK_MC 0 273 #define OP_SH_MC 0 274 #define OP_MASK_MD 0 275 #define OP_SH_MD 0 276 #define OP_MASK_ME 0 277 #define OP_SH_ME 0 278 #define OP_MASK_MF 0 279 #define OP_SH_MF 0 280 #define OP_MASK_MG 0 281 #define OP_SH_MG 0 282 #define OP_MASK_MH 0 283 #define OP_SH_MH 0 284 #define OP_MASK_MJ 0 285 #define OP_SH_MJ 0 286 #define OP_MASK_ML 0 287 #define OP_SH_ML 0 288 #define OP_MASK_MM 0 289 #define OP_SH_MM 0 290 #define OP_MASK_MN 0 291 #define OP_SH_MN 0 292 #define OP_MASK_MP 0 293 #define OP_SH_MP 0 294 #define OP_MASK_MQ 0 295 #define OP_SH_MQ 0 296 #define OP_MASK_IMMA 0 297 #define OP_SH_IMMA 0 298 #define OP_MASK_IMMB 0 299 #define OP_SH_IMMB 0 300 #define OP_MASK_IMMC 0 301 #define OP_SH_IMMC 0 302 #define OP_MASK_IMMF 0 303 #define OP_SH_IMMF 0 304 #define OP_MASK_IMMG 0 305 #define OP_SH_IMMG 0 306 #define OP_MASK_IMMH 0 307 #define OP_SH_IMMH 0 308 #define OP_MASK_IMMI 0 309 #define OP_SH_IMMI 0 310 #define OP_MASK_IMMJ 0 311 #define OP_SH_IMMJ 0 312 #define OP_MASK_IMML 0 313 #define OP_SH_IMML 0 314 #define OP_MASK_IMMM 0 315 #define OP_SH_IMMM 0 316 #define OP_MASK_IMMN 0 317 #define OP_SH_IMMN 0 318 #define OP_MASK_IMMO 0 319 #define OP_SH_IMMO 0 320 #define OP_MASK_IMMP 0 321 #define OP_SH_IMMP 0 322 #define OP_MASK_IMMQ 0 323 #define OP_SH_IMMQ 0 324 #define OP_MASK_IMMU 0 325 #define OP_SH_IMMU 0 326 #define OP_MASK_IMMW 0 327 #define OP_SH_IMMW 0 328 #define OP_MASK_IMMX 0 329 #define OP_SH_IMMX 0 330 #define OP_MASK_IMMY 0 331 #define OP_SH_IMMY 0 332 333 /* Enhanced VA Scheme */ 334 #define OP_SH_EVAOFFSET 7 335 #define OP_MASK_EVAOFFSET 0x1ff 336 337 /* Enumerates the various types of MIPS operand. */ 338 enum mips_operand_type { 339 /* Described by mips_int_operand. */ 340 OP_INT, 341 342 /* Described by mips_mapped_int_operand. */ 343 OP_MAPPED_INT, 344 345 /* Described by mips_msb_operand. */ 346 OP_MSB, 347 348 /* Described by mips_reg_operand. */ 349 OP_REG, 350 351 /* Like OP_REG, but can be omitted if the register is the same as the 352 previous operand. */ 353 OP_OPTIONAL_REG, 354 355 /* Described by mips_reg_pair_operand. */ 356 OP_REG_PAIR, 357 358 /* Described by mips_pcrel_operand. */ 359 OP_PCREL, 360 361 /* A performance register. The field is 5 bits in size, but the supported 362 values are much more restricted. */ 363 OP_PERF_REG, 364 365 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts 366 as a normal 9-bit signed offset that is multiplied by four, but there 367 are four special cases: 368 369 -2 * 4 => -258 * 4 370 -1 * 4 => -257 * 4 371 0 * 4 => 256 * 4 372 1 * 4 => 257 * 4. */ 373 OP_ADDIUSP_INT, 374 375 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two 376 5-bit register fields, both of which must be set to the destination 377 register. */ 378 OP_CLO_CLZ_DEST, 379 380 /* A register list for a microMIPS LWM or SWM instruction. The operand 381 size determines whether the 16-bit or 32-bit encoding is required. */ 382 OP_LWM_SWM_LIST, 383 384 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ 385 OP_ENTRY_EXIT_LIST, 386 387 /* The register list and frame size for a MIPS16 SAVE or RESTORE 388 instruction. */ 389 OP_SAVE_RESTORE_LIST, 390 391 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: 392 393 V Meaning 394 ----- ------- 395 0EEE0 8 copies of $vN[E], OB format 396 0EE01 4 copies of $vN[E], QH format 397 10110 all 8 elements of $vN, OB format 398 10101 all 4 elements of $vN, QH format 399 11110 8 copies of immediate N, OB format 400 11101 4 copies of immediate N, QH format. */ 401 OP_MDMX_IMM_REG, 402 403 /* A register operand that must match the destination register. */ 404 OP_REPEAT_DEST_REG, 405 406 /* A register operand that must match the previous register. */ 407 OP_REPEAT_PREV_REG, 408 409 /* $pc, which has no encoding in the architectural instruction. */ 410 OP_PC, 411 412 /* $28, which has no encoding in the MIPS16e architectural instruction. */ 413 OP_REG28, 414 415 /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines 416 which. */ 417 OP_VU0_SUFFIX, 418 419 /* Like OP_VU0_SUFFIX, but used when the operand's value has already 420 been set. Any suffix used here must match the previous value. */ 421 OP_VU0_MATCH_SUFFIX, 422 423 /* An index selected by an integer, e.g. [1]. */ 424 OP_IMM_INDEX, 425 426 /* An index selected by a register, e.g. [$2]. */ 427 OP_REG_INDEX, 428 429 /* The operand spans two 5-bit register fields, both of which must be set to 430 the source register. */ 431 OP_SAME_RS_RT, 432 433 /* Described by mips_prev_operand. */ 434 OP_CHECK_PREV, 435 436 /* A register operand that must not be zero. */ 437 OP_NON_ZERO_REG 438 }; 439 440 /* Enumerates the types of MIPS register. */ 441 enum mips_reg_operand_type { 442 /* General registers $0-$31. Software names like $at can also be used. */ 443 OP_REG_GP, 444 445 /* Floating-point registers $f0-$f31. */ 446 OP_REG_FP, 447 448 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes 449 can also be written $fcc0-$fcc7. */ 450 OP_REG_CCC, 451 452 /* FPRs used in a vector capacity. They can be written $f0-$f31 453 or $v0-$v31, although the latter form is not used for the VR5400 454 vector instructions. */ 455 OP_REG_VEC, 456 457 /* DSP accumulator registers $ac0-$ac3. */ 458 OP_REG_ACC, 459 460 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can 461 also be used in some contexts. */ 462 OP_REG_COPRO, 463 464 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can 465 also be used in some contexts. */ 466 OP_REG_HW, 467 468 /* Floating-point registers $vf0-$vf31. */ 469 OP_REG_VF, 470 471 /* Integer registers $vi0-$vi31. */ 472 OP_REG_VI, 473 474 /* R5900 VU0 registers $I, $Q, $R and $ACC. */ 475 OP_REG_R5900_I, 476 OP_REG_R5900_Q, 477 OP_REG_R5900_R, 478 OP_REG_R5900_ACC, 479 480 /* MSA registers $w0-$w31. */ 481 OP_REG_MSA, 482 483 /* MSA control registers $0-$31. */ 484 OP_REG_MSA_CTRL 485 }; 486 487 /* Base class for all operands. */ 488 struct mips_operand 489 { 490 /* The type of the operand. */ 491 enum mips_operand_type type; 492 493 /* The operand occupies SIZE bits of the instruction, starting at LSB. */ 494 unsigned short size; 495 unsigned short lsb; 496 }; 497 498 /* Describes an integer operand with a regular encoding pattern. */ 499 struct mips_int_operand 500 { 501 struct mips_operand root; 502 503 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. 504 The cyclically previous field value encodes 1 << SHIFT less than that, 505 and so on. E.g. 506 507 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, 508 but 15 encodes -1. 509 510 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is 511 shifted left two places. 512 513 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except 514 that 0 encodes 8. 515 516 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ 517 unsigned int max_val; 518 int bias; 519 unsigned int shift; 520 521 /* True if the operand should be printed as hex rather than decimal. */ 522 bfd_boolean print_hex; 523 }; 524 525 /* Uses a lookup table to describe a small integer operand. */ 526 struct mips_mapped_int_operand 527 { 528 struct mips_operand root; 529 530 /* Maps each encoding value to the integer that it represents. */ 531 const int *int_map; 532 533 /* True if the operand should be printed as hex rather than decimal. */ 534 bfd_boolean print_hex; 535 }; 536 537 /* An operand that encodes the most significant bit position of a bitfield. 538 Given a bitfield that spans bits [MSB, LSB], some operands of this type 539 encode MSB directly while others encode MSB - LSB. Each operand of this 540 type is preceded by an integer operand that specifies LSB. 541 542 The assembly form varies between instructions. For some instructions, 543 such as EXT, the operand is written as the bitfield size. For others, 544 such as EXTS, it is written in raw MSB - LSB form. */ 545 struct mips_msb_operand 546 { 547 struct mips_operand root; 548 549 /* The assembly-level operand encoded by a field value of 0. */ 550 int bias; 551 552 /* True if the operand encodes MSB directly, false if it encodes 553 MSB - LSB. */ 554 bfd_boolean add_lsb; 555 556 /* The maximum value of MSB + 1. */ 557 unsigned int opsize; 558 }; 559 560 /* Describes a single register operand. */ 561 struct mips_reg_operand 562 { 563 struct mips_operand root; 564 565 /* The type of register. */ 566 enum mips_reg_operand_type reg_type; 567 568 /* If nonnull, REG_MAP[N] gives the register associated with encoding N, 569 otherwise the encoding is the same as the register number. */ 570 const unsigned char *reg_map; 571 }; 572 573 /* Describes an operand that which must match a condition based on the 574 previous operand. */ 575 struct mips_check_prev_operand 576 { 577 struct mips_operand root; 578 579 bfd_boolean greater_than_ok; 580 bfd_boolean less_than_ok; 581 bfd_boolean equal_ok; 582 bfd_boolean zero_ok; 583 }; 584 585 /* Describes an operand that encodes a pair of registers. */ 586 struct mips_reg_pair_operand 587 { 588 struct mips_operand root; 589 590 /* The type of register. */ 591 enum mips_reg_operand_type reg_type; 592 593 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ 594 unsigned char *reg1_map; 595 unsigned char *reg2_map; 596 }; 597 598 /* Describes an operand that is calculated relative to a base PC. 599 The base PC is usually the address of the following instruction, 600 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ 601 struct mips_pcrel_operand 602 { 603 /* Encodes the offset. */ 604 struct mips_int_operand root; 605 606 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', 607 which is then added to the offset encoded by ROOT. */ 608 unsigned int align_log2 : 8; 609 610 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then 611 reinstated. This is true for jumps and branches and false for 612 PC-relative data instructions. */ 613 unsigned int include_isa_bit : 1; 614 615 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. 616 This is true for JALX and false otherwise. */ 617 unsigned int flip_isa_bit : 1; 618 }; 619 620 /* Return true if the assembly syntax allows OPERAND to be omitted. */ 621 622 static inline bfd_boolean 623 mips_optional_operand_p (const struct mips_operand *operand) 624 { 625 return (operand->type == OP_OPTIONAL_REG 626 || operand->type == OP_REPEAT_PREV_REG); 627 } 628 629 /* Return a version of INSN in which the field specified by OPERAND 630 has value UVAL. */ 631 632 static inline unsigned int 633 mips_insert_operand (const struct mips_operand *operand, unsigned int insn, 634 unsigned int uval) 635 { 636 unsigned int mask; 637 638 mask = (1 << operand->size) - 1; 639 insn &= ~(mask << operand->lsb); 640 insn |= (uval & mask) << operand->lsb; 641 return insn; 642 } 643 644 /* Extract OPERAND from instruction INSN. */ 645 646 static inline unsigned int 647 mips_extract_operand (const struct mips_operand *operand, unsigned int insn) 648 { 649 return (insn >> operand->lsb) & ((1 << operand->size) - 1); 650 } 651 652 /* UVAL is the value encoded by OPERAND. Return it in signed form. */ 653 654 static inline int 655 mips_signed_operand (const struct mips_operand *operand, unsigned int uval) 656 { 657 unsigned int sign_bit, mask; 658 659 mask = (1 << operand->size) - 1; 660 sign_bit = 1 << (operand->size - 1); 661 return ((uval + sign_bit) & mask) - sign_bit; 662 } 663 664 /* Return the integer that OPERAND encodes as UVAL. */ 665 666 static inline int 667 mips_decode_int_operand (const struct mips_int_operand *operand, 668 unsigned int uval) 669 { 670 uval |= (operand->max_val - uval) & -(1 << operand->root.size); 671 uval += operand->bias; 672 uval <<= operand->shift; 673 return uval; 674 } 675 676 /* Return the maximum value that can be encoded by OPERAND. */ 677 678 static inline int 679 mips_int_operand_max (const struct mips_int_operand *operand) 680 { 681 return (operand->max_val + operand->bias) << operand->shift; 682 } 683 684 /* Return the minimum value that can be encoded by OPERAND. */ 685 686 static inline int 687 mips_int_operand_min (const struct mips_int_operand *operand) 688 { 689 unsigned int mask; 690 691 mask = (1 << operand->root.size) - 1; 692 return mips_int_operand_max (operand) - (mask << operand->shift); 693 } 694 695 /* Return the register that OPERAND encodes as UVAL. */ 696 697 static inline int 698 mips_decode_reg_operand (const struct mips_reg_operand *operand, 699 unsigned int uval) 700 { 701 if (operand->reg_map) 702 uval = operand->reg_map[uval]; 703 return uval; 704 } 705 706 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. 707 Return the address that it encodes. */ 708 709 static inline bfd_vma 710 mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, 711 bfd_vma base_pc, unsigned int uval) 712 { 713 bfd_vma addr; 714 715 addr = base_pc & -(1 << operand->align_log2); 716 addr += mips_decode_int_operand (&operand->root, uval); 717 if (operand->include_isa_bit) 718 addr |= base_pc & 1; 719 if (operand->flip_isa_bit) 720 addr ^= 1; 721 return addr; 722 } 723 724 /* This structure holds information for a particular instruction. */ 725 726 struct mips_opcode 727 { 728 /* The name of the instruction. */ 729 const char *name; 730 /* A string describing the arguments for this instruction. */ 731 const char *args; 732 /* The basic opcode for the instruction. When assembling, this 733 opcode is modified by the arguments to produce the actual opcode 734 that is used. If pinfo is INSN_MACRO, then this is 0. */ 735 unsigned long match; 736 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 737 relevant portions of the opcode when disassembling. If the 738 actual opcode anded with the match field equals the opcode field, 739 then we have found the correct instruction. If pinfo is 740 INSN_MACRO, then this field is the macro identifier. */ 741 unsigned long mask; 742 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 743 of bits describing the instruction, notably any relevant hazard 744 information. */ 745 unsigned long pinfo; 746 /* A collection of additional bits describing the instruction. */ 747 unsigned long pinfo2; 748 /* A collection of bits describing the instruction sets of which this 749 instruction or macro is a member. */ 750 unsigned long membership; 751 /* A collection of bits describing the ASE of which this instruction 752 or macro is a member. */ 753 unsigned long ase; 754 /* A collection of bits describing the instruction sets of which this 755 instruction or macro is not a member. */ 756 unsigned long exclusions; 757 }; 758 759 /* Return true if MO is an instruction that requires 32-bit encoding. */ 760 761 static inline bfd_boolean 762 mips_opcode_32bit_p (const struct mips_opcode *mo) 763 { 764 return mo->mask >> 16 != 0; 765 } 766 767 /* These are the characters which may appear in the args field of an 768 instruction. They appear in the order in which the fields appear 769 when the instruction is used. Commas and parentheses in the args 770 string are ignored when assembling, and written into the output 771 when disassembling. 772 773 Each of these characters corresponds to a mask field defined above. 774 775 "1" 5 bit sync type (OP_*_STYPE) 776 "<" 5 bit shift amount (OP_*_SHAMT) 777 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 778 "a" 26 bit target address (OP_*_TARGET) 779 "+i" likewise, but flips bit 0 780 "b" 5 bit base register (OP_*_RS) 781 "c" 10 bit breakpoint code (OP_*_CODE) 782 "d" 5 bit destination register specifier (OP_*_RD) 783 "h" 5 bit prefx hint (OP_*_PREFX) 784 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 785 "j" 16 bit signed immediate (OP_*_DELTA) 786 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 787 "o" 16 bit signed offset (OP_*_DELTA) 788 "p" 16 bit PC relative branch target address (OP_*_DELTA) 789 "q" 10 bit extra breakpoint code (OP_*_CODE2) 790 "r" 5 bit same register used as both source and target (OP_*_RS) 791 "s" 5 bit source register specifier (OP_*_RS) 792 "t" 5 bit target register (OP_*_RT) 793 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 794 "v" 5 bit same register used as both source and destination (OP_*_RS) 795 "w" 5 bit same register used as both target and destination (OP_*_RT) 796 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 797 (used by clo and clz) 798 "C" 25 bit coprocessor function code (OP_*_COPZ) 799 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 800 "J" 19 bit wait function code (OP_*_CODE19) 801 "x" accept and ignore register name 802 "z" must be zero register 803 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 804 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 805 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for 806 microMIPS compatibility). 807 Enforces: 0 <= pos < 32. 808 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 809 Requires that "+A" or "+E" occur first to set position. 810 Enforces: 0 < (pos+size) <= 32. 811 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 812 Requires that "+A" or "+E" occur first to set position. 813 Enforces: 0 < (pos+size) <= 32. 814 (Also used by "dext" w/ different limits, but limits for 815 that are checked by the M_DEXT macro.) 816 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 817 Enforces: 32 <= pos < 64. 818 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 819 Requires that "+A" or "+E" occur first to set position. 820 Enforces: 32 < (pos+size) <= 64. 821 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 822 Requires that "+A" or "+E" occur first to set position. 823 Enforces: 32 < (pos+size) <= 64. 824 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 825 Requires that "+A" or "+E" occur first to set position. 826 Enforces: 32 < (pos+size) <= 64. 827 828 Floating point instructions: 829 "D" 5 bit destination register (OP_*_FD) 830 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 831 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 832 "S" 5 bit fs source 1 register (OP_*_FS) 833 "T" 5 bit ft source 2 register (OP_*_FT) 834 "R" 5 bit fr source 3 register (OP_*_FR) 835 "V" 5 bit same register used as floating source and destination (OP_*_FS) 836 "W" 5 bit same register used as floating target and destination (OP_*_FT) 837 838 Coprocessor instructions: 839 "E" 5 bit target register (OP_*_RT) 840 "G" 5 bit destination register (OP_*_RD) 841 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 842 "P" 5 bit performance-monitor register (OP_*_PERFREG) 843 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 844 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 845 846 Macro instructions: 847 "A" General 32 bit expression 848 "I" 32 bit immediate (value placed in imm_expr). 849 "F" 64 bit floating point constant in .rdata 850 "L" 64 bit floating point constant in .lit8 851 "f" 32 bit floating point constant 852 "l" 32 bit floating point constant in .lit4 853 854 MDMX and VR5400 instruction operands (note that while these use the 855 FP register fields, the MDMX instructions accept both $fN and $vN names 856 for the registers): 857 "O" alignment offset (OP_*_ALN) 858 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 859 "X" destination register (OP_*_FD) 860 "Y" source register (OP_*_FS) 861 "Z" source register (OP_*_FT) 862 863 R5900 VU0 Macromode instructions: 864 "+5" 5 bit floating point register (FD) 865 "+6" 5 bit floating point register (FS) 866 "+7" 5 bit floating point register (FT) 867 "+8" 5 bit integer register (FD) 868 "+9" 5 bit integer register (FS) 869 "+0" 5 bit integer register (FT) 870 "+K" match an existing 4-bit channel mask starting at bit 21 871 "+L" 2-bit channel index starting at bit 21 872 "+M" 2-bit channel index starting at bit 23 873 "+N" match an existing 2-bit channel index starting at bit 0 874 "+f" 15 bit immediate for VCALLMS 875 "+g" 5 bit signed immediate for VIADDI 876 "+m" $ACC register (syntax only) 877 "+q" $Q register (syntax only) 878 "+r" $R register (syntax only) 879 "+y" $I register (syntax only) 880 "#+" "++" decorator in ($reg++) sequence 881 "#-" "--" decorator in (--$reg) sequence 882 883 DSP ASE usage: 884 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 885 "3" 3 bit unsigned immediate (OP_*_SA3) 886 "4" 4 bit unsigned immediate (OP_*_SA4) 887 "5" 8 bit unsigned immediate (OP_*_IMM8) 888 "6" 5 bit unsigned immediate (OP_*_RS) 889 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 890 "8" 6 bit unsigned immediate (OP_*_WRDSP) 891 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 892 "0" 6 bit signed immediate (OP_*_DSPSFT) 893 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 894 "'" 6 bit unsigned immediate (OP_*_RDDSP) 895 "@" 10 bit signed immediate (OP_*_IMM10) 896 897 MT ASE usage: 898 "!" 1 bit usermode flag (OP_*_MT_U) 899 "$" 1 bit load high flag (OP_*_MT_H) 900 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 901 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 902 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 903 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 904 905 MCU ASE usage: 906 "~" 12 bit offset (OP_*_OFFSET12) 907 "\" 3 bit position for aset and aclr (OP_*_3BITPOS) 908 909 VIRT ASE usage: 910 "+J" 10-bit hypcall code (OP_*CODE10) 911 912 UDI immediates: 913 "+1" UDI immediate bits 6-10 914 "+2" UDI immediate bits 6-15 915 "+3" UDI immediate bits 6-20 916 "+4" UDI immediate bits 6-25 917 918 Octeon: 919 "+x" Bit index field of bbit. Enforces: 0 <= index < 32. 920 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, 921 otherwise skips to next candidate. 922 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. 923 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if 924 32 <= pos < 64, otherwise skips to next candidate. 925 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. 926 "+s" Length-minus-one field of cins32/exts32. Requires msb position 927 of the field to be <= 31. 928 "+S" Length-minus-one field of cins/exts. Requires msb position 929 of the field to be <= 63. 930 931 Loongson-ext ASE: 932 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) 933 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) 934 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) 935 "+z" 5-bit rz register (OP_*_RZ) 936 "+Z" 5-bit fz register (OP_*_FZ) 937 938 interAptiv MR2: 939 "-m" register list for SAVE/RESTORE instruction 940 941 Enhanced VA Scheme: 942 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) 943 944 MSA Extension: 945 "+d" 5-bit MSA register (FD) 946 "+e" 5-bit MSA register (FS) 947 "+h" 5-bit MSA register (FT) 948 "+k" 5-bit GPR at bit 6 949 "+l" 5-bit MSA control register at bit 6 950 "+n" 5-bit MSA control register at bit 11 951 "+o" 4-bit vector element index at bit 16 952 "+u" 3-bit vector element index at bit 16 953 "+v" 2-bit vector element index at bit 16 954 "+w" 1-bit vector element index at bit 16 955 "+T" (-512 .. 511) << 0 at bit 16 956 "+U" (-512 .. 511) << 1 at bit 16 957 "+V" (-512 .. 511) << 2 at bit 16 958 "+W" (-512 .. 511) << 3 at bit 16 959 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 960 "+!" 3 bit unsigned bit position at bit 16 961 "+@" 4 bit unsigned bit position at bit 16 962 "+#" 6 bit unsigned bit position at bit 16 963 "+$" 5 bit unsigned immediate at bit 16 964 "+%" 5 bit signed immediate at bit 16 965 "+^" 10 bit signed immediate at bit 11 966 "+&" 0 vector element index 967 "+*" 5-bit register vector element index at bit 16 968 "+|" 8-bit mask at bit 16 969 970 MIPS R6: 971 "+:" 11-bit mask at bit 0 972 "+'" 26 bit PC relative branch target address 973 "+"" 21 bit PC relative branch target address 974 "+;" 5 bit same register in both OP_*_RS and OP_*_RT 975 "+I" 2bit unsigned bit position at bit 6 976 "+O" 3bit unsigned bit position at bit 6 977 "+R" must be program counter 978 "-a" (-262144 .. 262143) << 2 at bit 0 979 "-b" (-131072 .. 131071) << 3 at bit 0 980 "-d" Same as destination register GP 981 "-s" 5 bit source register specifier (OP_*_RS) not $0 982 "-t" 5 bit source register specifier (OP_*_RT) not $0 983 "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS 984 "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS 985 "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS 986 "-x" 5 bit source register specifier (OP_*_RT) greater than or 987 equal to OP_*_RS 988 "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS 989 "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 990 "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 991 992 GINV ASE usage: 993 "+\" 2 bit Global TLB invalidate type at bit 8 994 995 Other: 996 "()" parens surrounding optional value 997 "," separates operands 998 "+" Start of extension sequence. 999 1000 Characters used so far, for quick reference when adding more: 1001 "1234567890" 1002 "%[]<>(),+-:'@!#$*&\~" 1003 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 1004 "abcdefghijklopqrstuvwxz" 1005 1006 Extension character sequences used so far ("+" followed by the 1007 following), for quick reference when adding more: 1008 "1234567890" 1009 "~!@#$%^&*|:'";\" 1010 "ABCEFGHIJKLMNOPQRSTUVWXZ" 1011 "abcdefghijklmnopqrstuvwxyz" 1012 1013 Extension character sequences used so far ("-" followed by the 1014 following), for quick reference when adding more: 1015 "AB" 1016 "abdmstuvwxy" 1017 */ 1018 1019 /* These are the bits which may be set in the pinfo field of an 1020 instructions, if it is not equal to INSN_MACRO. */ 1021 1022 /* Writes to operand number N. */ 1023 #define INSN_WRITE_SHIFT 0 1024 #define INSN_WRITE_1 0x00000001 1025 #define INSN_WRITE_2 0x00000002 1026 #define INSN_WRITE_ALL 0x00000003 1027 /* Reads from operand number N. */ 1028 #define INSN_READ_SHIFT 2 1029 #define INSN_READ_1 0x00000004 1030 #define INSN_READ_2 0x00000008 1031 #define INSN_READ_3 0x00000010 1032 #define INSN_READ_4 0x00000020 1033 #define INSN_READ_ALL 0x0000003c 1034 /* Modifies general purpose register 31. */ 1035 #define INSN_WRITE_GPR_31 0x00000040 1036 /* Modifies coprocessor condition code. */ 1037 #define INSN_WRITE_COND_CODE 0x00000080 1038 /* Reads coprocessor condition code. */ 1039 #define INSN_READ_COND_CODE 0x00000100 1040 /* TLB operation. */ 1041 #define INSN_TLB 0x00000200 1042 /* Reads coprocessor register other than floating point register. */ 1043 #define INSN_COP 0x00000400 1044 /* Instruction loads value from memory. */ 1045 #define INSN_LOAD_MEMORY 0x00000800 1046 /* Instruction loads value from coprocessor, (may require delay). */ 1047 #define INSN_LOAD_COPROC 0x00001000 1048 /* Instruction has unconditional branch delay slot. */ 1049 #define INSN_UNCOND_BRANCH_DELAY 0x00002000 1050 /* Instruction has conditional branch delay slot. */ 1051 #define INSN_COND_BRANCH_DELAY 0x00004000 1052 /* Conditional branch likely: if branch not taken, insn nullified. */ 1053 #define INSN_COND_BRANCH_LIKELY 0x00008000 1054 /* Moves to coprocessor register, (may require delay). */ 1055 #define INSN_COPROC_MOVE 0x00010000 1056 /* Loads coprocessor register from memory, requiring delay. */ 1057 #define INSN_COPROC_MEMORY_DELAY 0x00020000 1058 /* Reads the HI register. */ 1059 #define INSN_READ_HI 0x00040000 1060 /* Reads the LO register. */ 1061 #define INSN_READ_LO 0x00080000 1062 /* Modifies the HI register. */ 1063 #define INSN_WRITE_HI 0x00100000 1064 /* Modifies the LO register. */ 1065 #define INSN_WRITE_LO 0x00200000 1066 /* Not to be placed in a branch delay slot, either architecturally 1067 or for ease of handling (such as with instructions that take a trap). */ 1068 #define INSN_NO_DELAY_SLOT 0x00400000 1069 /* Instruction stores value into memory. */ 1070 #define INSN_STORE_MEMORY 0x00800000 1071 /* Instruction uses single precision floating point. */ 1072 #define FP_S 0x01000000 1073 /* Instruction uses double precision floating point. */ 1074 #define FP_D 0x02000000 1075 /* Instruction is part of the tx39's integer multiply family. */ 1076 #define INSN_MULT 0x04000000 1077 /* Reads general purpose register 24. */ 1078 #define INSN_READ_GPR_24 0x08000000 1079 /* Writes to general purpose register 24. */ 1080 #define INSN_WRITE_GPR_24 0x10000000 1081 /* A user-defined instruction. */ 1082 #define INSN_UDI 0x20000000 1083 /* Instruction is actually a macro. It should be ignored by the 1084 disassembler, and requires special treatment by the assembler. */ 1085 #define INSN_MACRO 0xffffffff 1086 1087 /* These are the bits which may be set in the pinfo2 field of an 1088 instruction. */ 1089 1090 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 1091 #define INSN2_ALIAS 0x00000001 1092 /* Instruction reads MDMX accumulator. */ 1093 #define INSN2_READ_MDMX_ACC 0x00000002 1094 /* Instruction writes MDMX accumulator. */ 1095 #define INSN2_WRITE_MDMX_ACC 0x00000004 1096 /* Macro uses single-precision floating-point instructions. This should 1097 only be set for macros. For instructions, FP_S in pinfo carries the 1098 same information. */ 1099 #define INSN2_M_FP_S 0x00000008 1100 /* Macro uses double-precision floating-point instructions. This should 1101 only be set for macros. For instructions, FP_D in pinfo carries the 1102 same information. */ 1103 #define INSN2_M_FP_D 0x00000010 1104 /* Instruction has a branch delay slot that requires a 16-bit instruction. */ 1105 #define INSN2_BRANCH_DELAY_16BIT 0x00000020 1106 /* Instruction has a branch delay slot that requires a 32-bit instruction. */ 1107 #define INSN2_BRANCH_DELAY_32BIT 0x00000040 1108 /* Writes to the stack pointer ($29). */ 1109 #define INSN2_WRITE_SP 0x00000080 1110 /* Reads from the stack pointer ($29). */ 1111 #define INSN2_READ_SP 0x00000100 1112 /* Reads the RA ($31) register. */ 1113 #define INSN2_READ_GPR_31 0x00000200 1114 /* Reads the program counter ($pc). */ 1115 #define INSN2_READ_PC 0x00000400 1116 /* Is an unconditional branch insn. */ 1117 #define INSN2_UNCOND_BRANCH 0x00000800 1118 /* Is a conditional branch insn. */ 1119 #define INSN2_COND_BRANCH 0x00001000 1120 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */ 1121 #define INSN2_READ_GPR_16 0x00002000 1122 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ 1123 #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 1124 /* Instruction has a forbidden slot. */ 1125 #define INSN2_FORBIDDEN_SLOT 0x00008000 1126 /* Opcode table entry is for a short MIPS16 form only. An extended 1127 encoding may still exist, but with a separate opcode table entry 1128 required. In disassembly the presence of this flag in an otherwise 1129 successful match against an extended instruction encoding inhibits 1130 matching against any subsequent short table entry even if it does 1131 not have this flag set. A table entry matching the full extended 1132 encoding is needed or otherwise the final EXTEND entry will apply, 1133 for the disassembly of the prefix only. */ 1134 #define INSN2_SHORT_ONLY 0x00010000 1135 1136 /* Masks used to mark instructions to indicate which MIPS ISA level 1137 they were introduced in. INSN_ISA_MASK masks an enumeration that 1138 specifies the base ISA level(s). The remainder of a 32-bit 1139 word constructed using these macros is a bitmask of the remaining 1140 INSN_* values below. */ 1141 1142 #define INSN_ISA_MASK 0x0000001ful 1143 1144 /* We cannot start at zero due to ISA_UNKNOWN below. */ 1145 #define INSN_ISA1 1 1146 #define INSN_ISA2 2 1147 #define INSN_ISA3 3 1148 #define INSN_ISA4 4 1149 #define INSN_ISA5 5 1150 #define INSN_ISA32 6 1151 #define INSN_ISA32R2 7 1152 #define INSN_ISA32R3 8 1153 #define INSN_ISA32R5 9 1154 #define INSN_ISA32R6 10 1155 #define INSN_ISA64 11 1156 #define INSN_ISA64R2 12 1157 #define INSN_ISA64R3 13 1158 #define INSN_ISA64R5 14 1159 #define INSN_ISA64R6 15 1160 /* Below this point the INSN_* values correspond to combinations of ISAs. 1161 They are only for use in the opcodes table to indicate membership of 1162 a combination of ISAs that cannot be expressed using the usual inclusion 1163 ordering on the above INSN_* values. */ 1164 #define INSN_ISA3_32 16 1165 #define INSN_ISA3_32R2 17 1166 #define INSN_ISA4_32 18 1167 #define INSN_ISA4_32R2 19 1168 #define INSN_ISA5_32R2 20 1169 1170 /* The R6 definitions shown below state that they support all previous ISAs. 1171 This is not actually true as some instructions are removed in R6. 1172 The problem is that the removed instructions in R6 come from different 1173 ISAs. One approach to solve this would be to describe in the membership 1174 field of the opcode table the different ISAs an instruction belongs to. 1175 This would require us to create a large amount of different ISA 1176 combinations which is hard to manage. A cleaner approach (which is 1177 implemented here) is to say that R6 is an extension of R5 and then to 1178 deal with the removed instructions by adding instruction exclusions 1179 for R6 in the opcode table. */ 1180 1181 /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ 1182 1183 #define ISAF(X) (1 << (INSN_ISA##X - 1)) 1184 #define INSN_UPTO1 ISAF(1) 1185 #define INSN_UPTO2 INSN_UPTO1 | ISAF(2) 1186 #define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) 1187 #define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) 1188 #define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) 1189 #define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) 1190 #define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ 1191 | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) 1192 #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) 1193 #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) 1194 #define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) 1195 #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) 1196 #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) 1197 #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) 1198 #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) 1199 #define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) 1200 1201 /* The same information in table form: bit INSN_ISA<X> - 1 of index 1202 INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ 1203 static const unsigned int mips_isa_table[] = { 1204 INSN_UPTO1, 1205 INSN_UPTO2, 1206 INSN_UPTO3, 1207 INSN_UPTO4, 1208 INSN_UPTO5, 1209 INSN_UPTO32, 1210 INSN_UPTO32R2, 1211 INSN_UPTO32R3, 1212 INSN_UPTO32R5, 1213 INSN_UPTO32R6, 1214 INSN_UPTO64, 1215 INSN_UPTO64R2, 1216 INSN_UPTO64R3, 1217 INSN_UPTO64R5, 1218 INSN_UPTO64R6 1219 }; 1220 #undef ISAF 1221 1222 /* Masks used for Chip specific instructions. */ 1223 #define INSN_CHIP_MASK 0xc7ff4f60 1224 1225 /* Cavium Networks Octeon instructions. */ 1226 #define INSN_OCTEON 0x00000800 1227 #define INSN_OCTEONP 0x00000200 1228 #define INSN_OCTEON2 0x00000100 1229 #define INSN_OCTEON3 0x00000040 1230 1231 /* MIPS R5900 instruction */ 1232 #define INSN_5900 0x00004000 1233 1234 /* MIPS R4650 instruction. */ 1235 #define INSN_4650 0x00010000 1236 /* LSI R4010 instruction. */ 1237 #define INSN_4010 0x00020000 1238 /* NEC VR4100 instruction. */ 1239 #define INSN_4100 0x00040000 1240 /* Toshiba R3900 instruction. */ 1241 #define INSN_3900 0x00080000 1242 /* MIPS R10000 instruction. */ 1243 #define INSN_10000 0x00100000 1244 /* Broadcom SB-1 instruction. */ 1245 #define INSN_SB1 0x00200000 1246 /* NEC VR4111/VR4181 instruction. */ 1247 #define INSN_4111 0x00400000 1248 /* NEC VR4120 instruction. */ 1249 #define INSN_4120 0x00800000 1250 /* NEC VR5400 instruction. */ 1251 #define INSN_5400 0x01000000 1252 /* NEC VR5500 instruction. */ 1253 #define INSN_5500 0x02000000 1254 1255 /* ST Microelectronics Loongson 2E. */ 1256 #define INSN_LOONGSON_2E 0x40000000 1257 /* ST Microelectronics Loongson 2F. */ 1258 #define INSN_LOONGSON_2F 0x80000000 1259 /* RMI Xlr instruction */ 1260 #define INSN_XLR 0x00000020 1261 /* Imagination interAptiv MR2. */ 1262 #define INSN_INTERAPTIV_MR2 0x04000000 1263 1264 /* DSP ASE */ 1265 #define ASE_DSP 0x00000001 1266 #define ASE_DSP64 0x00000002 1267 /* DSP R2 ASE */ 1268 #define ASE_DSPR2 0x00000004 1269 /* Enhanced VA Scheme */ 1270 #define ASE_EVA 0x00000008 1271 /* MCU (MicroController) ASE */ 1272 #define ASE_MCU 0x00000010 1273 /* MDMX ASE */ 1274 #define ASE_MDMX 0x00000020 1275 /* MIPS-3D ASE */ 1276 #define ASE_MIPS3D 0x00000040 1277 /* MT ASE */ 1278 #define ASE_MT 0x00000080 1279 /* SmartMIPS ASE */ 1280 #define ASE_SMARTMIPS 0x00000100 1281 /* Virtualization ASE */ 1282 #define ASE_VIRT 0x00000200 1283 #define ASE_VIRT64 0x00000400 1284 /* MSA Extension */ 1285 #define ASE_MSA 0x00000800 1286 #define ASE_MSA64 0x00001000 1287 /* eXtended Physical Address (XPA) Extension. */ 1288 #define ASE_XPA 0x00002000 1289 /* DSP R3 Module. */ 1290 #define ASE_DSPR3 0x00004000 1291 /* MIPS16e2 ASE. */ 1292 #define ASE_MIPS16E2 0x00008000 1293 /* MIPS16e2 MT ASE instructions. */ 1294 #define ASE_MIPS16E2_MT 0x00010000 1295 /* The Virtualization ASE has eXtended Physical Addressing (XPA) 1296 instructions which are only valid when both ASEs are enabled. */ 1297 #define ASE_XPA_VIRT 0x00020000 1298 /* Cyclic redundancy check (CRC) ASE. */ 1299 #define ASE_CRC 0x00040000 1300 #define ASE_CRC64 0x00080000 1301 /* Global INValidate Extension. */ 1302 #define ASE_GINV 0x00100000 1303 /* Loongson MultiMedia extensions Instructions (MMI). */ 1304 #define ASE_LOONGSON_MMI 0x00200000 1305 /* Loongson Content Address Memory (CAM). */ 1306 #define ASE_LOONGSON_CAM 0x00400000 1307 /* Loongson EXTensions (EXT) instructions. */ 1308 #define ASE_LOONGSON_EXT 0x00800000 1309 /* Loongson EXTensions R2 (EXT2) instructions. */ 1310 #define ASE_LOONGSON_EXT2 0x01000000 1311 /* The Enhanced VA Scheme (EVA) extension has instructions which are 1312 only valid for the R6 ISA. */ 1313 #define ASE_EVA_R6 0x02000000 1314 1315 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 1316 1317 #define ISA_UNKNOWN 0 /* Gas internal use. */ 1318 #define ISA_MIPS1 INSN_ISA1 1319 #define ISA_MIPS2 INSN_ISA2 1320 #define ISA_MIPS3 INSN_ISA3 1321 #define ISA_MIPS4 INSN_ISA4 1322 #define ISA_MIPS5 INSN_ISA5 1323 1324 #define ISA_MIPS32 INSN_ISA32 1325 #define ISA_MIPS64 INSN_ISA64 1326 1327 #define ISA_MIPS32R2 INSN_ISA32R2 1328 #define ISA_MIPS32R3 INSN_ISA32R3 1329 #define ISA_MIPS32R5 INSN_ISA32R5 1330 #define ISA_MIPS64R2 INSN_ISA64R2 1331 #define ISA_MIPS64R3 INSN_ISA64R3 1332 #define ISA_MIPS64R5 INSN_ISA64R5 1333 1334 #define ISA_MIPS32R6 INSN_ISA32R6 1335 #define ISA_MIPS64R6 INSN_ISA64R6 1336 1337 /* CPU defines, use instead of hardcoding processor number. Keep this 1338 in sync with bfd/archures.c in order for machine selection to work. */ 1339 #define CPU_UNKNOWN 0 /* Gas internal use. */ 1340 #define CPU_R3000 3000 1341 #define CPU_R3900 3900 1342 #define CPU_R4000 4000 1343 #define CPU_R4010 4010 1344 #define CPU_VR4100 4100 1345 #define CPU_R4111 4111 1346 #define CPU_VR4120 4120 1347 #define CPU_R4300 4300 1348 #define CPU_R4400 4400 1349 #define CPU_R4600 4600 1350 #define CPU_R4650 4650 1351 #define CPU_R5000 5000 1352 #define CPU_VR5400 5400 1353 #define CPU_VR5500 5500 1354 #define CPU_R5900 5900 1355 #define CPU_R6000 6000 1356 #define CPU_RM7000 7000 1357 #define CPU_R8000 8000 1358 #define CPU_RM9000 9000 1359 #define CPU_R10000 10000 1360 #define CPU_R12000 12000 1361 #define CPU_R14000 14000 1362 #define CPU_R16000 16000 1363 #define CPU_MIPS16 16 1364 #define CPU_MIPS32 32 1365 #define CPU_MIPS32R2 33 1366 #define CPU_MIPS32R3 34 1367 #define CPU_MIPS32R5 36 1368 #define CPU_MIPS32R6 37 1369 #define CPU_MIPS5 5 1370 #define CPU_MIPS64 64 1371 #define CPU_MIPS64R2 65 1372 #define CPU_MIPS64R3 66 1373 #define CPU_MIPS64R5 68 1374 #define CPU_MIPS64R6 69 1375 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 1376 #define CPU_LOONGSON_2E 3001 1377 #define CPU_LOONGSON_2F 3002 1378 #define CPU_GS464 3003 1379 #define CPU_GS464E 3004 1380 #define CPU_GS264E 3005 1381 #define CPU_OCTEON 6501 1382 #define CPU_OCTEONP 6601 1383 #define CPU_OCTEON2 6502 1384 #define CPU_OCTEON3 6503 1385 #define CPU_XLR 887682 /* decimal 'XLR' */ 1386 #define CPU_INTERAPTIV_MR2 736550 /* decimal 'IA2' */ 1387 1388 /* Return true if the given CPU is included in INSN_* mask MASK. */ 1389 1390 static inline bfd_boolean 1391 cpu_is_member (int cpu, unsigned int mask) 1392 { 1393 switch (cpu) 1394 { 1395 case CPU_R4650: 1396 case CPU_RM7000: 1397 case CPU_RM9000: 1398 return (mask & INSN_4650) != 0; 1399 1400 case CPU_R4010: 1401 return (mask & INSN_4010) != 0; 1402 1403 case CPU_VR4100: 1404 return (mask & INSN_4100) != 0; 1405 1406 case CPU_R3900: 1407 return (mask & INSN_3900) != 0; 1408 1409 case CPU_R10000: 1410 case CPU_R12000: 1411 case CPU_R14000: 1412 case CPU_R16000: 1413 return (mask & INSN_10000) != 0; 1414 1415 case CPU_SB1: 1416 return (mask & INSN_SB1) != 0; 1417 1418 case CPU_R4111: 1419 return (mask & INSN_4111) != 0; 1420 1421 case CPU_VR4120: 1422 return (mask & INSN_4120) != 0; 1423 1424 case CPU_VR5400: 1425 return (mask & INSN_5400) != 0; 1426 1427 case CPU_VR5500: 1428 return (mask & INSN_5500) != 0; 1429 1430 case CPU_R5900: 1431 return (mask & INSN_5900) != 0; 1432 1433 case CPU_LOONGSON_2E: 1434 return (mask & INSN_LOONGSON_2E) != 0; 1435 1436 case CPU_LOONGSON_2F: 1437 return (mask & INSN_LOONGSON_2F) != 0; 1438 1439 case CPU_OCTEON: 1440 return (mask & INSN_OCTEON) != 0; 1441 1442 case CPU_OCTEONP: 1443 return (mask & INSN_OCTEONP) != 0; 1444 1445 case CPU_OCTEON2: 1446 return (mask & INSN_OCTEON2) != 0; 1447 1448 case CPU_OCTEON3: 1449 return (mask & INSN_OCTEON3) != 0; 1450 1451 case CPU_XLR: 1452 return (mask & INSN_XLR) != 0; 1453 1454 case CPU_INTERAPTIV_MR2: 1455 return (mask & INSN_INTERAPTIV_MR2) != 0; 1456 1457 case CPU_MIPS32R6: 1458 return (mask & INSN_ISA_MASK) == INSN_ISA32R6; 1459 1460 case CPU_MIPS64R6: 1461 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) 1462 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); 1463 1464 default: 1465 return FALSE; 1466 } 1467 } 1468 1469 /* Test for membership in an ISA including chip specific ISAs. INSN 1470 is pointer to an element of the opcode table; ISA is the specified 1471 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 1472 test, or zero if no CPU specific ISA test is desired. Return true 1473 if instruction INSN is available to the given ISA and CPU. */ 1474 1475 static inline bfd_boolean 1476 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) 1477 { 1478 if (!cpu_is_member (cpu, insn->exclusions)) 1479 { 1480 /* Test for ISA level compatibility. */ 1481 if ((isa & INSN_ISA_MASK) != 0 1482 && (insn->membership & INSN_ISA_MASK) != 0 1483 && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] 1484 >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) 1485 return TRUE; 1486 1487 /* Test for ASE compatibility. */ 1488 if ((ase & insn->ase) != 0) 1489 return TRUE; 1490 1491 /* Test for processor-specific extensions. */ 1492 if (cpu_is_member (cpu, insn->membership)) 1493 return TRUE; 1494 } 1495 return FALSE; 1496 } 1497 1498 /* This is a list of macro expanded instructions. 1499 1500 _I appended means immediate 1501 _A appended means target address of a jump 1502 _AB appended means address with (possibly zero) base register 1503 _D appended means 64 bit floating point constant 1504 _S appended means 32 bit floating point constant. */ 1505 1506 enum 1507 { 1508 M_ABS, 1509 M_ACLR_AB, 1510 M_ADD_I, 1511 M_ADDU_I, 1512 M_AND_I, 1513 M_ASET_AB, 1514 M_BALIGN, 1515 M_BC1FL, 1516 M_BC1TL, 1517 M_BC2FL, 1518 M_BC2TL, 1519 M_BEQ, 1520 M_BEQ_I, 1521 M_BEQL, 1522 M_BEQL_I, 1523 M_BGE, 1524 M_BGEL, 1525 M_BGE_I, 1526 M_BGEL_I, 1527 M_BGEU, 1528 M_BGEUL, 1529 M_BGEU_I, 1530 M_BGEUL_I, 1531 M_BGEZ, 1532 M_BGEZL, 1533 M_BGEZALL, 1534 M_BGT, 1535 M_BGTL, 1536 M_BGT_I, 1537 M_BGTL_I, 1538 M_BGTU, 1539 M_BGTUL, 1540 M_BGTU_I, 1541 M_BGTUL_I, 1542 M_BGTZ, 1543 M_BGTZL, 1544 M_BLE, 1545 M_BLEL, 1546 M_BLE_I, 1547 M_BLEL_I, 1548 M_BLEU, 1549 M_BLEUL, 1550 M_BLEU_I, 1551 M_BLEUL_I, 1552 M_BLEZ, 1553 M_BLEZL, 1554 M_BLT, 1555 M_BLTL, 1556 M_BLT_I, 1557 M_BLTL_I, 1558 M_BLTU, 1559 M_BLTUL, 1560 M_BLTU_I, 1561 M_BLTUL_I, 1562 M_BLTZ, 1563 M_BLTZL, 1564 M_BLTZALL, 1565 M_BNE, 1566 M_BNEL, 1567 M_BNE_I, 1568 M_BNEL_I, 1569 M_CACHE_AB, 1570 M_CACHEE_AB, 1571 M_DABS, 1572 M_DADD_I, 1573 M_DADDU_I, 1574 M_DDIV_3, 1575 M_DDIV_3I, 1576 M_DDIVU_3, 1577 M_DDIVU_3I, 1578 M_DIV_3, 1579 M_DIV_3I, 1580 M_DIVU_3, 1581 M_DIVU_3I, 1582 M_DLA_AB, 1583 M_DLCA_AB, 1584 M_DLI, 1585 M_DMUL, 1586 M_DMUL_I, 1587 M_DMULO, 1588 M_DMULO_I, 1589 M_DMULOU, 1590 M_DMULOU_I, 1591 M_DREM_3, 1592 M_DREM_3I, 1593 M_DREMU_3, 1594 M_DREMU_3I, 1595 M_DSUB_I, 1596 M_DSUBU_I, 1597 M_DSUBU_I_2, 1598 M_JR_S, 1599 M_J_S, 1600 M_J_A, 1601 M_JALR_S, 1602 M_JALR_DS, 1603 M_JAL_1, 1604 M_JAL_2, 1605 M_JAL_A, 1606 M_JALS_1, 1607 M_JALS_2, 1608 M_JALS_A, 1609 M_JRADDIUSP, 1610 M_JRC, 1611 M_L_DAB, 1612 M_LA_AB, 1613 M_LB_AB, 1614 M_LBE_AB, 1615 M_LBU_AB, 1616 M_LBUE_AB, 1617 M_LCA_AB, 1618 M_LD_AB, 1619 M_LDC1_AB, 1620 M_LDC2_AB, 1621 M_LQC2_AB, 1622 M_LDC3_AB, 1623 M_LDL_AB, 1624 M_LDM_AB, 1625 M_LDP_AB, 1626 M_LDR_AB, 1627 M_LH_AB, 1628 M_LHE_AB, 1629 M_LHU_AB, 1630 M_LHUE_AB, 1631 M_LI, 1632 M_LI_D, 1633 M_LI_DD, 1634 M_LI_S, 1635 M_LI_SS, 1636 M_LL_AB, 1637 M_LLD_AB, 1638 M_LLDP_AB, 1639 M_LLE_AB, 1640 M_LLWP_AB, 1641 M_LLWPE_AB, 1642 M_LQ_AB, 1643 M_LW_AB, 1644 M_LWE_AB, 1645 M_LWC0_AB, 1646 M_LWC1_AB, 1647 M_LWC2_AB, 1648 M_LWC3_AB, 1649 M_LWL_AB, 1650 M_LWLE_AB, 1651 M_LWM_AB, 1652 M_LWP_AB, 1653 M_LWR_AB, 1654 M_LWRE_AB, 1655 M_LWU_AB, 1656 M_MSGSND, 1657 M_MSGLD, 1658 M_MSGLD_T, 1659 M_MSGWAIT, 1660 M_MSGWAIT_T, 1661 M_MOVE, 1662 M_MOVEP, 1663 M_MUL, 1664 M_MUL_I, 1665 M_MULO, 1666 M_MULO_I, 1667 M_MULOU, 1668 M_MULOU_I, 1669 M_NOR_I, 1670 M_OR_I, 1671 M_PREF_AB, 1672 M_PREFE_AB, 1673 M_REM_3, 1674 M_REM_3I, 1675 M_REMU_3, 1676 M_REMU_3I, 1677 M_DROL, 1678 M_ROL, 1679 M_DROL_I, 1680 M_ROL_I, 1681 M_DROR, 1682 M_ROR, 1683 M_DROR_I, 1684 M_ROR_I, 1685 M_S_DA, 1686 M_S_DAB, 1687 M_S_S, 1688 M_SAA_AB, 1689 M_SAAD_AB, 1690 M_SC_AB, 1691 M_SCD_AB, 1692 M_SCDP_AB, 1693 M_SCE_AB, 1694 M_SCWP_AB, 1695 M_SCWPE_AB, 1696 M_SD_AB, 1697 M_SDC1_AB, 1698 M_SDC2_AB, 1699 M_SQC2_AB, 1700 M_SDC3_AB, 1701 M_SDL_AB, 1702 M_SDM_AB, 1703 M_SDP_AB, 1704 M_SDR_AB, 1705 M_SEQ, 1706 M_SEQ_I, 1707 M_SGE, 1708 M_SGE_I, 1709 M_SGEU, 1710 M_SGEU_I, 1711 M_SGT, 1712 M_SGT_I, 1713 M_SGTU, 1714 M_SGTU_I, 1715 M_SLE, 1716 M_SLE_I, 1717 M_SLEU, 1718 M_SLEU_I, 1719 M_SLT_I, 1720 M_SLTU_I, 1721 M_SNE, 1722 M_SNE_I, 1723 M_SB_AB, 1724 M_SBE_AB, 1725 M_SH_AB, 1726 M_SHE_AB, 1727 M_SQ_AB, 1728 M_SW_AB, 1729 M_SWE_AB, 1730 M_SWC0_AB, 1731 M_SWC1_AB, 1732 M_SWC2_AB, 1733 M_SWC3_AB, 1734 M_SWL_AB, 1735 M_SWLE_AB, 1736 M_SWM_AB, 1737 M_SWP_AB, 1738 M_SWR_AB, 1739 M_SWRE_AB, 1740 M_SUB_I, 1741 M_SUBU_I, 1742 M_SUBU_I_2, 1743 M_TEQ_I, 1744 M_TGE_I, 1745 M_TGEU_I, 1746 M_TLT_I, 1747 M_TLTU_I, 1748 M_TNE_I, 1749 M_TRUNCWD, 1750 M_TRUNCWS, 1751 M_ULD_AB, 1752 M_ULH_AB, 1753 M_ULHU_AB, 1754 M_ULW_AB, 1755 M_USH_AB, 1756 M_USW_AB, 1757 M_USD_AB, 1758 M_XOR_I, 1759 M_COP0, 1760 M_COP1, 1761 M_COP2, 1762 M_COP3, 1763 M_NUM_MACROS 1764 }; 1765 1766 1767 /* The order of overloaded instructions matters. Label arguments and 1768 register arguments look the same. Instructions that can have either 1769 for arguments must apear in the correct order in this table for the 1770 assembler to pick the right one. In other words, entries with 1771 immediate operands must apear after the same instruction with 1772 registers. 1773 1774 Many instructions are short hand for other instructions (i.e., The 1775 jal <register> instruction is short for jalr <register>). */ 1776 1777 extern const struct mips_operand mips_vu0_channel_mask; 1778 extern const struct mips_operand *decode_mips_operand (const char *); 1779 extern const struct mips_opcode mips_builtin_opcodes[]; 1780 extern const int bfd_mips_num_builtin_opcodes; 1781 extern struct mips_opcode *mips_opcodes; 1782 extern int bfd_mips_num_opcodes; 1783 #define NUMOPCODES bfd_mips_num_opcodes 1784 1785 1786 /* The rest of this file adds definitions for the mips16 TinyRISC 1787 processor. */ 1788 1789 /* These are the bitmasks and shift counts used for the different 1790 fields in the instruction formats. Other than OP, no masks are 1791 provided for the fixed portions of an instruction, since they are 1792 not needed. 1793 1794 The I format uses IMM11. 1795 1796 The RI format uses RX and IMM8. 1797 1798 The RR format uses RX, and RY. 1799 1800 The RRI format uses RX, RY, and IMM5. 1801 1802 The RRR format uses RX, RY, and RZ. 1803 1804 The RRI_A format uses RX, RY, and IMM4. 1805 1806 The SHIFT format uses RX, RY, and SHAMT. 1807 1808 The I8 format uses IMM8. 1809 1810 The I8_MOVR32 format uses RY and REGR32. 1811 1812 The IR_MOV32R format uses REG32R and MOV32Z. 1813 1814 The I64 format uses IMM8. 1815 1816 The RI64 format uses RY and IMM5. 1817 */ 1818 1819 #define MIPS16OP_MASK_OP 0x1f 1820 #define MIPS16OP_SH_OP 11 1821 #define MIPS16OP_MASK_IMM11 0x7ff 1822 #define MIPS16OP_SH_IMM11 0 1823 #define MIPS16OP_MASK_RX 0x7 1824 #define MIPS16OP_SH_RX 8 1825 #define MIPS16OP_MASK_IMM8 0xff 1826 #define MIPS16OP_SH_IMM8 0 1827 #define MIPS16OP_MASK_RY 0x7 1828 #define MIPS16OP_SH_RY 5 1829 #define MIPS16OP_MASK_IMM5 0x1f 1830 #define MIPS16OP_SH_IMM5 0 1831 #define MIPS16OP_MASK_RZ 0x7 1832 #define MIPS16OP_SH_RZ 2 1833 #define MIPS16OP_MASK_IMM4 0xf 1834 #define MIPS16OP_SH_IMM4 0 1835 #define MIPS16OP_MASK_REGR32 0x1f 1836 #define MIPS16OP_SH_REGR32 0 1837 #define MIPS16OP_MASK_REG32R 0x1f 1838 #define MIPS16OP_SH_REG32R 3 1839 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 1840 #define MIPS16OP_MASK_MOVE32Z 0x7 1841 #define MIPS16OP_SH_MOVE32Z 0 1842 #define MIPS16OP_MASK_IMM6 0x3f 1843 #define MIPS16OP_SH_IMM6 5 1844 1845 /* These are the characters which may appears in the args field of a MIPS16 1846 instruction. They appear in the order in which the fields appear when the 1847 instruction is used. Commas and parentheses in the args string are ignored 1848 when assembling, and written into the output when disassembling. 1849 1850 "y" 3 bit register (MIPS16OP_*_RY) 1851 "x" 3 bit register (MIPS16OP_*_RX) 1852 "z" 3 bit register (MIPS16OP_*_RZ) 1853 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 1854 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 1855 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 1856 "." zero register ($0) 1857 "S" stack pointer ($sp or $29) 1858 "P" program counter 1859 "R" return address register ($ra or $31) 1860 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 1861 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 1862 "0" 5-bit ASMACRO p0 immediate 1863 "1" 3-bit ASMACRO p1 immediate 1864 "2" 3-bit ASMACRO p2 immediate 1865 "3" 5-bit ASMACRO p3 immediate 1866 "4" 3-bit ASMACRO p4 immediate 1867 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 1868 "a" 26 bit jump address 1869 "i" likewise, but flips bit 0 1870 "e" 11 bit extension value 1871 "l" register list for entry instruction 1872 "L" register list for exit instruction 1873 ">" 5-bit SYNC code 1874 "9" 9-bit signed immediate 1875 "G" global pointer ($gp or $28) 1876 "N" 5-bit coprocessor register 1877 "O" 3-bit sel field for MFC0/MTC0 1878 "Q" 5-bit hardware register 1879 "T" 5-bit CACHE opcode or PREF hint 1880 "b" 5-bit INS/EXT position, which becomes LSB 1881 Enforces: 0 <= pos < 32. 1882 "c" 5-bit INS size, which becomes MSB 1883 Requires that "b" occurs first to set position. 1884 Enforces: 0 < (pos+size) <= 32. 1885 "d" 5-bit EXT size, which becomes MSBD 1886 Requires that "b" occurs first to set position. 1887 Enforces: 0 < (pos+size) <= 32. 1888 "n" 2-bit immediate (1 .. 4) 1889 "o" 5-bit unsigned immediate * 16 1890 "r" 3-bit register 1891 "s" 3-bit ASMACRO select immediate 1892 "u" 16-bit unsigned immediate 1893 1894 "I" an immediate value used for macros 1895 1896 The remaining codes may be extended. Except as otherwise noted, 1897 the full extended operand is a 16 bit signed value. 1898 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 1899 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 1900 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 1901 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 1902 "F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 1903 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 1904 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 1905 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 1906 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 1907 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 1908 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1909 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1910 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1911 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1912 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1913 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1914 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1915 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1916 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1917 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1918 "m" 7 bit register list for SAVE/RESTORE instruction (18 bit extended) 1919 1920 Characters used so far, for quick reference when adding more: 1921 "0123456 89" 1922 ".[]<>" 1923 "ABCDEFGHI KL NOPQRSTUVWXYZ" 1924 "abcde ijklmnopqrs uvwxyz" 1925 */ 1926 1927 /* Save/restore encoding for the args field when all 4 registers are 1928 either saved as arguments or saved/restored as statics. */ 1929 #define MIPS_SVRS_ALL_ARGS 0xe 1930 #define MIPS_SVRS_ALL_STATICS 0xb 1931 1932 /* The following flags have the same value for the mips16 opcode 1933 table: 1934 1935 INSN_ISA3 1936 1937 INSN_UNCOND_BRANCH_DELAY 1938 INSN_COND_BRANCH_DELAY 1939 INSN_COND_BRANCH_LIKELY (never used) 1940 INSN_READ_HI 1941 INSN_READ_LO 1942 INSN_WRITE_HI 1943 INSN_WRITE_LO 1944 INSN_TRAP 1945 FP_D (never used) 1946 */ 1947 1948 extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean); 1949 extern const struct mips_opcode mips16_opcodes[]; 1950 extern const int bfd_mips16_num_opcodes; 1951 1952 /* These are the bit masks and shift counts used for the different fields 1953 in the microMIPS instruction formats. No masks are provided for the 1954 fixed portions of an instruction, since they are not needed. */ 1955 1956 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff 1957 #define MICROMIPSOP_SH_IMMEDIATE 0 1958 #define MICROMIPSOP_MASK_DELTA 0xffff 1959 #define MICROMIPSOP_SH_DELTA 0 1960 #define MICROMIPSOP_MASK_CODE10 0x3ff 1961 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ 1962 #define MICROMIPSOP_MASK_TRAP 0xf 1963 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ 1964 #define MICROMIPSOP_MASK_SHAMT 0x1f 1965 #define MICROMIPSOP_SH_SHAMT 11 1966 #define MICROMIPSOP_MASK_TARGET 0x3ffffff 1967 #define MICROMIPSOP_SH_TARGET 0 1968 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ 1969 #define MICROMIPSOP_SH_EXTLSB 6 1970 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 1971 #define MICROMIPSOP_SH_EXTMSBD 11 1972 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ 1973 #define MICROMIPSOP_SH_INSMSB 11 1974 #define MICROMIPSOP_MASK_CODE 0x3ff 1975 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ 1976 #define MICROMIPSOP_MASK_CODE2 0x3ff 1977 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ 1978 #define MICROMIPSOP_MASK_CACHE 0x1f 1979 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ 1980 #define MICROMIPSOP_MASK_SEL 0x7 1981 #define MICROMIPSOP_SH_SEL 11 1982 #define MICROMIPSOP_MASK_OFFSET12 0xfff 1983 #define MICROMIPSOP_SH_OFFSET12 0 1984 #define MICROMIPSOP_MASK_3BITPOS 0x7 1985 #define MICROMIPSOP_SH_3BITPOS 21 1986 #define MICROMIPSOP_MASK_STYPE 0x1f 1987 #define MICROMIPSOP_SH_STYPE 16 1988 #define MICROMIPSOP_MASK_OFFSET10 0x3ff 1989 #define MICROMIPSOP_SH_OFFSET10 6 1990 #define MICROMIPSOP_MASK_RS 0x1f 1991 #define MICROMIPSOP_SH_RS 16 1992 #define MICROMIPSOP_MASK_RT 0x1f 1993 #define MICROMIPSOP_SH_RT 21 1994 #define MICROMIPSOP_MASK_RD 0x1f 1995 #define MICROMIPSOP_SH_RD 11 1996 #define MICROMIPSOP_MASK_FS 0x1f 1997 #define MICROMIPSOP_SH_FS 16 1998 #define MICROMIPSOP_MASK_FT 0x1f 1999 #define MICROMIPSOP_SH_FT 21 2000 #define MICROMIPSOP_MASK_FD 0x1f 2001 #define MICROMIPSOP_SH_FD 11 2002 #define MICROMIPSOP_MASK_FR 0x1f 2003 #define MICROMIPSOP_SH_FR 6 2004 #define MICROMIPSOP_MASK_RS3 0x1f 2005 #define MICROMIPSOP_SH_RS3 6 2006 #define MICROMIPSOP_MASK_PREFX 0x1f 2007 #define MICROMIPSOP_SH_PREFX 11 2008 #define MICROMIPSOP_MASK_BCC 0x7 2009 #define MICROMIPSOP_SH_BCC 18 2010 #define MICROMIPSOP_MASK_CCC 0x7 2011 #define MICROMIPSOP_SH_CCC 13 2012 #define MICROMIPSOP_MASK_COPZ 0x7fffff 2013 #define MICROMIPSOP_SH_COPZ 3 2014 2015 #define MICROMIPSOP_MASK_MB 0x7 2016 #define MICROMIPSOP_SH_MB 23 2017 #define MICROMIPSOP_MASK_MC 0x7 2018 #define MICROMIPSOP_SH_MC 4 2019 #define MICROMIPSOP_MASK_MD 0x7 2020 #define MICROMIPSOP_SH_MD 7 2021 #define MICROMIPSOP_MASK_ME 0x7 2022 #define MICROMIPSOP_SH_ME 1 2023 #define MICROMIPSOP_MASK_MF 0x7 2024 #define MICROMIPSOP_SH_MF 3 2025 #define MICROMIPSOP_MASK_MG 0x7 2026 #define MICROMIPSOP_SH_MG 0 2027 #define MICROMIPSOP_MASK_MH 0x7 2028 #define MICROMIPSOP_SH_MH 7 2029 #define MICROMIPSOP_MASK_MJ 0x1f 2030 #define MICROMIPSOP_SH_MJ 0 2031 #define MICROMIPSOP_MASK_ML 0x7 2032 #define MICROMIPSOP_SH_ML 4 2033 #define MICROMIPSOP_MASK_MM 0x7 2034 #define MICROMIPSOP_SH_MM 1 2035 #define MICROMIPSOP_MASK_MN 0x7 2036 #define MICROMIPSOP_SH_MN 4 2037 #define MICROMIPSOP_MASK_MP 0x1f 2038 #define MICROMIPSOP_SH_MP 5 2039 #define MICROMIPSOP_MASK_MQ 0x7 2040 #define MICROMIPSOP_SH_MQ 7 2041 2042 #define MICROMIPSOP_MASK_IMMA 0x7f 2043 #define MICROMIPSOP_SH_IMMA 0 2044 #define MICROMIPSOP_MASK_IMMB 0x7 2045 #define MICROMIPSOP_SH_IMMB 1 2046 #define MICROMIPSOP_MASK_IMMC 0xf 2047 #define MICROMIPSOP_SH_IMMC 0 2048 #define MICROMIPSOP_MASK_IMMD 0x3ff 2049 #define MICROMIPSOP_SH_IMMD 0 2050 #define MICROMIPSOP_MASK_IMME 0x7f 2051 #define MICROMIPSOP_SH_IMME 0 2052 #define MICROMIPSOP_MASK_IMMF 0xf 2053 #define MICROMIPSOP_SH_IMMF 0 2054 #define MICROMIPSOP_MASK_IMMG 0xf 2055 #define MICROMIPSOP_SH_IMMG 0 2056 #define MICROMIPSOP_MASK_IMMH 0xf 2057 #define MICROMIPSOP_SH_IMMH 0 2058 #define MICROMIPSOP_MASK_IMMI 0x7f 2059 #define MICROMIPSOP_SH_IMMI 0 2060 #define MICROMIPSOP_MASK_IMMJ 0xf 2061 #define MICROMIPSOP_SH_IMMJ 0 2062 #define MICROMIPSOP_MASK_IMML 0xf 2063 #define MICROMIPSOP_SH_IMML 0 2064 #define MICROMIPSOP_MASK_IMMM 0x7 2065 #define MICROMIPSOP_SH_IMMM 1 2066 #define MICROMIPSOP_MASK_IMMN 0x3 2067 #define MICROMIPSOP_SH_IMMN 4 2068 #define MICROMIPSOP_MASK_IMMO 0xf 2069 #define MICROMIPSOP_SH_IMMO 0 2070 #define MICROMIPSOP_MASK_IMMP 0x1f 2071 #define MICROMIPSOP_SH_IMMP 0 2072 #define MICROMIPSOP_MASK_IMMQ 0x7fffff 2073 #define MICROMIPSOP_SH_IMMQ 0 2074 #define MICROMIPSOP_MASK_IMMU 0x1f 2075 #define MICROMIPSOP_SH_IMMU 0 2076 #define MICROMIPSOP_MASK_IMMW 0x3f 2077 #define MICROMIPSOP_SH_IMMW 1 2078 #define MICROMIPSOP_MASK_IMMX 0xf 2079 #define MICROMIPSOP_SH_IMMX 1 2080 #define MICROMIPSOP_MASK_IMMY 0x1ff 2081 #define MICROMIPSOP_SH_IMMY 1 2082 2083 /* MIPS DSP ASE */ 2084 #define MICROMIPSOP_MASK_DSPACC 0x3 2085 #define MICROMIPSOP_SH_DSPACC 14 2086 #define MICROMIPSOP_MASK_DSPSFT 0x3f 2087 #define MICROMIPSOP_SH_DSPSFT 16 2088 #define MICROMIPSOP_MASK_SA3 0x7 2089 #define MICROMIPSOP_SH_SA3 13 2090 #define MICROMIPSOP_MASK_SA4 0xf 2091 #define MICROMIPSOP_SH_SA4 12 2092 #define MICROMIPSOP_MASK_IMM8 0xff 2093 #define MICROMIPSOP_SH_IMM8 13 2094 #define MICROMIPSOP_MASK_IMM10 0x3ff 2095 #define MICROMIPSOP_SH_IMM10 16 2096 #define MICROMIPSOP_MASK_WRDSP 0x3f 2097 #define MICROMIPSOP_SH_WRDSP 14 2098 #define MICROMIPSOP_MASK_BP 0x3 2099 #define MICROMIPSOP_SH_BP 14 2100 2101 /* Placeholders for fields that only exist in the traditional 32-bit 2102 instruction encoding; see the comment above for details. */ 2103 #define MICROMIPSOP_MASK_CODE20 0 2104 #define MICROMIPSOP_SH_CODE20 0 2105 #define MICROMIPSOP_MASK_PERFREG 0 2106 #define MICROMIPSOP_SH_PERFREG 0 2107 #define MICROMIPSOP_MASK_CODE19 0 2108 #define MICROMIPSOP_SH_CODE19 0 2109 #define MICROMIPSOP_MASK_ALN 0 2110 #define MICROMIPSOP_SH_ALN 0 2111 #define MICROMIPSOP_MASK_VECBYTE 0 2112 #define MICROMIPSOP_SH_VECBYTE 0 2113 #define MICROMIPSOP_MASK_VECALIGN 0 2114 #define MICROMIPSOP_SH_VECALIGN 0 2115 #define MICROMIPSOP_MASK_DSPACC_S 0 2116 #define MICROMIPSOP_SH_DSPACC_S 0 2117 #define MICROMIPSOP_MASK_DSPSFT_7 0 2118 #define MICROMIPSOP_SH_DSPSFT_7 0 2119 #define MICROMIPSOP_MASK_RDDSP 0 2120 #define MICROMIPSOP_SH_RDDSP 0 2121 #define MICROMIPSOP_MASK_MT_U 0 2122 #define MICROMIPSOP_SH_MT_U 0 2123 #define MICROMIPSOP_MASK_MT_H 0 2124 #define MICROMIPSOP_SH_MT_H 0 2125 #define MICROMIPSOP_MASK_MTACC_T 0 2126 #define MICROMIPSOP_SH_MTACC_T 0 2127 #define MICROMIPSOP_MASK_MTACC_D 0 2128 #define MICROMIPSOP_SH_MTACC_D 0 2129 #define MICROMIPSOP_MASK_BBITIND 0 2130 #define MICROMIPSOP_SH_BBITIND 0 2131 #define MICROMIPSOP_MASK_CINSPOS 0 2132 #define MICROMIPSOP_SH_CINSPOS 0 2133 #define MICROMIPSOP_MASK_CINSLM1 0 2134 #define MICROMIPSOP_SH_CINSLM1 0 2135 #define MICROMIPSOP_MASK_SEQI 0 2136 #define MICROMIPSOP_SH_SEQI 0 2137 #define MICROMIPSOP_SH_OFFSET_A 0 2138 #define MICROMIPSOP_MASK_OFFSET_A 0 2139 #define MICROMIPSOP_SH_OFFSET_B 0 2140 #define MICROMIPSOP_MASK_OFFSET_B 0 2141 #define MICROMIPSOP_SH_OFFSET_C 0 2142 #define MICROMIPSOP_MASK_OFFSET_C 0 2143 #define MICROMIPSOP_SH_RZ 0 2144 #define MICROMIPSOP_MASK_RZ 0 2145 #define MICROMIPSOP_SH_FZ 0 2146 #define MICROMIPSOP_MASK_FZ 0 2147 2148 /* microMIPS Enhanced VA Scheme */ 2149 #define MICROMIPSOP_SH_EVAOFFSET 0 2150 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff 2151 2152 /* These are the characters which may appears in the args field of a microMIPS 2153 instruction. They appear in the order in which the fields appear 2154 when the instruction is used. Commas and parentheses in the args 2155 string are ignored when assembling, and written into the output 2156 when disassembling. 2157 2158 The followings are for 16-bit microMIPS instructions. 2159 2160 "ma" must be $28 2161 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 2162 The same register used as both source and target. 2163 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 2164 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 2165 The same register used as both source and target. 2166 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 2167 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 2168 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 2169 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 2170 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 2171 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 2172 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 2173 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 2174 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 2175 "mr" must be program counter 2176 "ms" must be $29 2177 "mt" must be the same as the previous register 2178 "mx" must be the same as the destination register 2179 "my" must be $31 2180 "mz" must be $0 2181 2182 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) 2183 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) 2184 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, 2185 32768, 65535) (MICROMIPSOP_*_IMMC) 2186 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) 2187 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) 2188 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) 2189 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) 2190 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) 2191 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) 2192 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) 2193 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2194 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) 2195 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) 2196 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2197 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) 2198 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) 2199 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) 2200 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) 2201 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) 2202 "mZ" must be zero 2203 2204 In most cases 32-bit microMIPS instructions use the same characters 2205 as MIPS (with ADDIUPC being a notable exception, but there are some 2206 others too). 2207 2208 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) 2209 "1" 5-bit sync type (MICROMIPSOP_*_STYPE) 2210 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) 2211 ">" shift amount between 32 and 63, stored after subtracting 32 2212 (MICROMIPSOP_*_SHAMT) 2213 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) 2214 "|" 4-bit trap code (MICROMIPSOP_*_TRAP) 2215 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) 2216 "a" 26-bit target address (MICROMIPSOP_*_TARGET) 2217 "+i" likewise, but flips bit 0 2218 "b" 5-bit base register (MICROMIPSOP_*_RS) 2219 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) 2220 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) 2221 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) 2222 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) 2223 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) 2224 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) 2225 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) 2226 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) 2227 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) 2228 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) 2229 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) 2230 "s" 5-bit source register specifier (MICROMIPSOP_*_RS) 2231 "t" 5-bit target register (MICROMIPSOP_*_RT) 2232 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) 2233 "v" 5-bit same register used as both source and destination 2234 (MICROMIPSOP_*_RS) 2235 "w" 5-bit same register used as both target and destination 2236 (MICROMIPSOP_*_RT) 2237 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) 2238 "z" must be zero register 2239 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) 2240 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) 2241 2242 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes 2243 LSB (MICROMIPSOP_*_EXTLSB). 2244 Enforces: 0 <= pos < 32. 2245 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). 2246 Requires that "+A" or "+E" occur first to set position. 2247 Enforces: 0 < (pos+size) <= 32. 2248 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2249 Requires that "+A" or "+E" occur first to set position. 2250 Enforces: 0 < (pos+size) <= 32. 2251 (Also used by DEXT w/ different limits, but limits for 2252 that are checked by the M_DEXT macro.) 2253 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). 2254 Enforces: 32 <= pos < 64. 2255 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). 2256 Requires that "+A" or "+E" occur first to set position. 2257 Enforces: 32 < (pos+size) <= 64. 2258 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). 2259 Requires that "+A" or "+E" occur first to set position. 2260 Enforces: 32 < (pos+size) <= 64. 2261 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2262 Requires that "+A" or "+E" occur first to set position. 2263 Enforces: 32 < (pos+size) <= 64. 2264 "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code 2265 (MICROMIPSOP_*_CODE10) 2266 2267 PC-relative addition (ADDIUPC) instruction: 2268 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) 2269 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 2270 2271 Floating point instructions: 2272 "D" 5-bit destination register (MICROMIPSOP_*_FD) 2273 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) 2274 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) 2275 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) 2276 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) 2277 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) 2278 "V" 5-bit same register used as floating source and destination or target 2279 (MICROMIPSOP_*_FS) 2280 2281 Coprocessor instructions: 2282 "E" 5-bit target register (MICROMIPSOP_*_RT) 2283 "G" 5-bit source register (MICROMIPSOP_*_RS) 2284 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) 2285 2286 Macro instructions: 2287 "A" general 32 bit expression 2288 "I" 32-bit immediate (value placed in imm_expr). 2289 "F" 64-bit floating point constant in .rdata 2290 "L" 64-bit floating point constant in .lit8 2291 "f" 32-bit floating point constant 2292 "l" 32-bit floating point constant in .lit4 2293 2294 DSP ASE usage: 2295 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) 2296 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) 2297 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) 2298 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) 2299 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) 2300 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) 2301 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) 2302 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) 2303 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) 2304 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) 2305 2306 microMIPS Enhanced VA Scheme: 2307 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) 2308 2309 MSA Extension: 2310 "+d" 5-bit MSA register (FD) 2311 "+e" 5-bit MSA register (FS) 2312 "+h" 5-bit MSA register (FT) 2313 "+k" 5-bit GPR at bit 6 2314 "+l" 5-bit MSA control register at bit 6 2315 "+n" 5-bit MSA control register at bit 11 2316 "+o" 4-bit vector element index at bit 16 2317 "+u" 3-bit vector element index at bit 16 2318 "+v" 2-bit vector element index at bit 16 2319 "+w" 1-bit vector element index at bit 16 2320 "+x" 5-bit shift amount at bit 16 2321 "+T" (-512 .. 511) << 0 at bit 16 2322 "+U" (-512 .. 511) << 1 at bit 16 2323 "+V" (-512 .. 511) << 2 at bit 16 2324 "+W" (-512 .. 511) << 3 at bit 16 2325 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 2326 "+!" 3 bit unsigned bit position at bit 16 2327 "+@" 4 bit unsigned bit position at bit 16 2328 "+#" 6 bit unsigned bit position at bit 16 2329 "+$" 5 bit unsigned immediate at bit 16 2330 "+%" 5 bit signed immediate at bit 16 2331 "+^" 10 bit signed immediate at bit 11 2332 "+&" 0 vector element index 2333 "+*" 5-bit register vector element index at bit 16 2334 "+|" 8-bit mask at bit 16 2335 2336 Other: 2337 "()" parens surrounding optional value 2338 "," separates operands 2339 "+" start of extension sequence 2340 "m" start of microMIPS extension sequence 2341 2342 Characters used so far, for quick reference when adding more: 2343 "12345678 0" 2344 "<>(),+-.@\^|~" 2345 "ABCDEFGHI KLMN RST V " 2346 "abcd f hijklmnopqrstuvw yz" 2347 2348 Extension character sequences used so far ("+" followed by the 2349 following), for quick reference when adding more: 2350 "" 2351 "~!@#$%^&*|" 2352 "ABCEFGHJTUVW" 2353 "dehijklnouvwx" 2354 2355 Extension character sequences used so far ("m" followed by the 2356 following), for quick reference when adding more: 2357 "" 2358 "" 2359 " BCDEFGHIJ LMNOPQ U WXYZ" 2360 " bcdefghij lmn pq st xyz" 2361 2362 Extension character sequences used so far ("-" followed by the 2363 following), for quick reference when adding more: 2364 "" 2365 "" 2366 <none so far> 2367 */ 2368 2369 extern const struct mips_operand *decode_micromips_operand (const char *); 2370 extern const struct mips_opcode micromips_opcodes[]; 2371 extern const int bfd_micromips_num_opcodes; 2372 2373 /* A NOP insn impemented as "or at,at,zero". 2374 Used to implement -mfix-loongson2f. */ 2375 #define LOONGSON2F_NOP_INSN 0x00200825 2376 2377 #ifdef __cplusplus 2378 } 2379 #endif 2380 2381 #endif /* _MIPS_H_ */ 2382