1 /* Opcode table for the ARC. 2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 3 4 Contributed by Claudiu Zissulescu (claziss@synopsys.com) 5 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 7 the GNU Binutils. 8 9 GAS/GDB is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GAS/GDB is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GAS or GDB; see the file COPYING3. If not, write to 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 22 MA 02110-1301, USA. */ 23 24 #ifndef OPCODE_ARC_H 25 #define OPCODE_ARC_H 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #ifndef MAX_INSN_ARGS 32 #define MAX_INSN_ARGS 16 33 #endif 34 35 #ifndef MAX_INSN_FLGS 36 #define MAX_INSN_FLGS 4 37 #endif 38 39 /* Instruction Class. */ 40 typedef enum 41 { 42 ACL, 43 ARITH, 44 AUXREG, 45 BBIT0, 46 BBIT1, 47 BI, 48 BIH, 49 BITOP, 50 BITSTREAM, 51 BMU, 52 BRANCH, 53 BRCC, 54 CONTROL, 55 DIVREM, 56 DMA, 57 DPI, 58 DSP, 59 EI, 60 ENTER, 61 FLOAT, 62 INVALID, 63 JLI, 64 JUMP, 65 KERNEL, 66 LEAVE, 67 LOAD, 68 LOGICAL, 69 LOOP, 70 MEMORY, 71 MISC, 72 MOVE, 73 MPY, 74 NET, 75 PROTOCOL_DECODE, 76 PMU, 77 POP, 78 PUSH, 79 SJLI, 80 STORE, 81 SUB, 82 ULTRAIP, 83 XY 84 } insn_class_t; 85 86 /* Instruction Subclass. */ 87 typedef enum 88 { 89 NONE = 0, 90 CVT = (1U << 1), 91 BTSCN = (1U << 2), 92 CD = (1U << 3), 93 CD1 = CD, 94 CD2 = CD, 95 COND = (1U << 4), 96 DIV = (1U << 5), 97 DP = (1U << 6), 98 DPA = (1U << 7), 99 DPX = (1U << 8), 100 LL64 = (1U << 9), 101 MPY1E = (1U << 10), 102 MPY6E = (1U << 11), 103 MPY7E = (1U << 12), 104 MPY8E = (1U << 13), 105 MPY9E = (1U << 14), 106 NPS400 = (1U << 15), 107 QUARKSE1 = (1U << 16), 108 QUARKSE2 = (1U << 17), 109 SHFT1 = (1U << 18), 110 SHFT2 = (1U << 19), 111 SWAP = (1U << 20), 112 SP = (1U << 21), 113 SPX = (1U << 22) 114 } insn_subclass_t; 115 116 /* Flags class. */ 117 typedef enum 118 { 119 F_CLASS_NONE = 0, 120 121 /* At most one flag from the set of flags can appear in the 122 instruction. */ 123 F_CLASS_OPTIONAL = (1 << 0), 124 125 /* Exactly one from from the set of flags must appear in the 126 instruction. */ 127 F_CLASS_REQUIRED = (1 << 1), 128 129 /* The conditional code can be extended over the standard variants 130 via .extCondCode pseudo-op. */ 131 F_CLASS_EXTEND = (1 << 2), 132 133 /* Condition code flag. */ 134 F_CLASS_COND = (1 << 3), 135 136 /* Write back mode. */ 137 F_CLASS_WB = (1 << 4), 138 139 /* Data size. */ 140 F_CLASS_ZZ = (1 << 5), 141 142 /* Implicit flag. */ 143 F_CLASS_IMPLICIT = (1 << 6) 144 } flag_class_t; 145 146 /* The opcode table is an array of struct arc_opcode. */ 147 struct arc_opcode 148 { 149 /* The opcode name. */ 150 const char * name; 151 152 /* The opcode itself. Those bits which will be filled in with 153 operands are zeroes. */ 154 unsigned long long opcode; 155 156 /* The opcode mask. This is used by the disassembler. This is a 157 mask containing ones indicating those bits which must match the 158 opcode field, and zeroes indicating those bits which need not 159 match (and are presumably filled in by operands). */ 160 unsigned long long mask; 161 162 /* One bit flags for the opcode. These are primarily used to 163 indicate specific processors and environments support the 164 instructions. The defined values are listed below. */ 165 unsigned cpu; 166 167 /* The instruction class. This is used by gdb. */ 168 insn_class_t insn_class; 169 170 /* The instruction subclass. */ 171 insn_subclass_t subclass; 172 173 /* An array of operand codes. Each code is an index into the 174 operand table. They appear in the order which the operands must 175 appear in assembly code, and are terminated by a zero. */ 176 unsigned char operands[MAX_INSN_ARGS + 1]; 177 178 /* An array of flag codes. Each code is an index into the flag 179 table. They appear in the order which the flags must appear in 180 assembly code, and are terminated by a zero. */ 181 unsigned char flags[MAX_INSN_FLGS + 1]; 182 }; 183 184 /* The table itself is sorted by major opcode number, and is otherwise 185 in the order in which the disassembler should consider 186 instructions. */ 187 extern const struct arc_opcode arc_opcodes[]; 188 189 /* Return length of an instruction represented by OPCODE, in bytes. */ 190 extern int arc_opcode_len (const struct arc_opcode *opcode); 191 192 /* CPU Availability. */ 193 #define ARC_OPCODE_NONE 0x0000 194 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */ 195 #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ 196 #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ 197 #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ 198 199 /* CPU combi. */ 200 #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ 201 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) 202 #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM) 203 #define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) 204 #define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2) 205 206 /* The operands table is an array of struct arc_operand. */ 207 struct arc_operand 208 { 209 /* The number of bits in the operand. */ 210 unsigned int bits; 211 212 /* How far the operand is left shifted in the instruction. */ 213 unsigned int shift; 214 215 /* The default relocation type for this operand. */ 216 signed int default_reloc; 217 218 /* One bit syntax flags. */ 219 unsigned int flags; 220 221 /* Insertion function. This is used by the assembler. To insert an 222 operand value into an instruction, check this field. 223 224 If it is NULL, execute 225 i |= (op & ((1 << o->bits) - 1)) << o->shift; 226 (i is the instruction which we are filling in, o is a pointer to 227 this structure, and op is the opcode value; this assumes twos 228 complement arithmetic). 229 230 If this field is not NULL, then simply call it with the 231 instruction and the operand value. It will return the new value 232 of the instruction. If the ERRMSG argument is not NULL, then if 233 the operand value is illegal, *ERRMSG will be set to a warning 234 string (the operand will be inserted in any case). If the 235 operand value is legal, *ERRMSG will be unchanged (most operands 236 can accept any value). */ 237 unsigned long long (*insert) (unsigned long long instruction, 238 long long int op, 239 const char **errmsg); 240 241 /* Extraction function. This is used by the disassembler. To 242 extract this operand type from an instruction, check this field. 243 244 If it is NULL, compute 245 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 246 if ((o->flags & ARC_OPERAND_SIGNED) != 0 247 && (op & (1 << (o->bits - 1))) != 0) 248 op -= 1 << o->bits; 249 (i is the instruction, o is a pointer to this structure, and op 250 is the result; this assumes twos complement arithmetic). 251 252 If this field is not NULL, then simply call it with the 253 instruction value. It will return the value of the operand. If 254 the INVALID argument is not NULL, *INVALID will be set to 255 TRUE if this operand type can not actually be extracted from 256 this operand (i.e., the instruction does not match). If the 257 operand is valid, *INVALID will not be changed. */ 258 long long int (*extract) (unsigned long long instruction, 259 bfd_boolean *invalid); 260 }; 261 262 /* Elements in the table are retrieved by indexing with values from 263 the operands field of the arc_opcodes table. */ 264 extern const struct arc_operand arc_operands[]; 265 extern const unsigned arc_num_operands; 266 extern const unsigned arc_Toperand; 267 extern const unsigned arc_NToperand; 268 269 /* Values defined for the flags field of a struct arc_operand. */ 270 271 /* This operand does not actually exist in the assembler input. This 272 is used to support extended mnemonics, for which two operands fields 273 are identical. The assembler should call the insert function with 274 any op value. The disassembler should call the extract function, 275 ignore the return value, and check the value placed in the invalid 276 argument. */ 277 #define ARC_OPERAND_FAKE 0x0001 278 279 /* This operand names an integer register. */ 280 #define ARC_OPERAND_IR 0x0002 281 282 /* This operand takes signed values. */ 283 #define ARC_OPERAND_SIGNED 0x0004 284 285 /* This operand takes unsigned values. This exists primarily so that 286 a flags value of 0 can be treated as end-of-arguments. */ 287 #define ARC_OPERAND_UNSIGNED 0x0008 288 289 /* This operand takes long immediate values. */ 290 #define ARC_OPERAND_LIMM 0x0010 291 292 /* This operand is identical like the previous one. */ 293 #define ARC_OPERAND_DUPLICATE 0x0020 294 295 /* This operand is PC relative. Used for internal relocs. */ 296 #define ARC_OPERAND_PCREL 0x0040 297 298 /* This operand is truncated. The truncation is done accordingly to 299 operand alignment attribute. */ 300 #define ARC_OPERAND_TRUNCATE 0x0080 301 302 /* This operand is 16bit aligned. */ 303 #define ARC_OPERAND_ALIGNED16 0x0100 304 305 /* This operand is 32bit aligned. */ 306 #define ARC_OPERAND_ALIGNED32 0x0200 307 308 /* This operand can be ignored by matching process if it is not 309 present. */ 310 #define ARC_OPERAND_IGNORE 0x0400 311 312 /* Don't check the range when matching. */ 313 #define ARC_OPERAND_NCHK 0x0800 314 315 /* Mark the braket possition. */ 316 #define ARC_OPERAND_BRAKET 0x1000 317 318 /* Address type operand for NPS400. */ 319 #define ARC_OPERAND_ADDRTYPE 0x2000 320 321 /* Mark the colon position. */ 322 #define ARC_OPERAND_COLON 0x4000 323 324 /* Mask for selecting the type for typecheck purposes. */ 325 #define ARC_OPERAND_TYPECHECK_MASK \ 326 (ARC_OPERAND_IR \ 327 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \ 328 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \ 329 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON) 330 331 /* Macro to determine if an operand is a fake operand. */ 332 #define ARC_OPERAND_IS_FAKE(op) \ 333 ((operand->flags & ARC_OPERAND_FAKE) \ 334 && !((operand->flags & ARC_OPERAND_BRAKET) \ 335 || (operand->flags & ARC_OPERAND_COLON))) 336 337 /* The flags structure. */ 338 struct arc_flag_operand 339 { 340 /* The flag name. */ 341 const char * name; 342 343 /* The flag code. */ 344 unsigned code; 345 346 /* The number of bits in the operand. */ 347 unsigned int bits; 348 349 /* How far the operand is left shifted in the instruction. */ 350 unsigned int shift; 351 352 /* Available for disassembler. */ 353 unsigned char favail; 354 }; 355 356 /* The flag operands table. */ 357 extern const struct arc_flag_operand arc_flag_operands[]; 358 extern const unsigned arc_num_flag_operands; 359 360 /* The flag's class structure. */ 361 struct arc_flag_class 362 { 363 /* Flag class. */ 364 flag_class_t flag_class; 365 366 /* List of valid flags (codes). */ 367 unsigned flags[256]; 368 }; 369 370 extern const struct arc_flag_class arc_flag_classes[]; 371 372 /* Structure for special cases. */ 373 struct arc_flag_special 374 { 375 /* Name of special case instruction. */ 376 const char *name; 377 378 /* List of flags applicable for special case instruction. */ 379 unsigned flags[32]; 380 }; 381 382 extern const struct arc_flag_special arc_flag_special_cases[]; 383 extern const unsigned arc_num_flag_special; 384 385 /* Relocation equivalence structure. */ 386 struct arc_reloc_equiv_tab 387 { 388 const char * name; /* String to lookup. */ 389 const char * mnemonic; /* Extra matching condition. */ 390 unsigned flags[32]; /* Extra matching condition. */ 391 signed int oldreloc; /* Old relocation. */ 392 signed int newreloc; /* New relocation. */ 393 }; 394 395 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[]; 396 extern const unsigned arc_num_equiv_tab; 397 398 /* Structure for operand operations for pseudo/alias instructions. */ 399 struct arc_operand_operation 400 { 401 /* The index for operand from operand array. */ 402 unsigned operand_idx; 403 404 /* Defines if it needs the operand inserted by the assembler or 405 whether this operand comes from the pseudo instruction's 406 operands. */ 407 unsigned char needs_insert; 408 409 /* Count we have to add to the operand. Use negative number to 410 subtract from the operand. Also use this number to add to 0 if 411 the operand needs to be inserted (i.e. needs_insert == 1). */ 412 int count; 413 414 /* Index of the operand to swap with. To be done AFTER applying 415 inc_count. */ 416 unsigned swap_operand_idx; 417 }; 418 419 /* Structure for pseudo/alias instructions. */ 420 struct arc_pseudo_insn 421 { 422 /* Mnemonic for pseudo/alias insn. */ 423 const char * mnemonic_p; 424 425 /* Mnemonic for real instruction. */ 426 const char * mnemonic_r; 427 428 /* Flag that will have to be added (if any). */ 429 const char * flag_r; 430 431 /* Amount of operands. */ 432 unsigned operand_cnt; 433 434 /* Array of operand operations. */ 435 struct arc_operand_operation operand[6]; 436 }; 437 438 extern const struct arc_pseudo_insn arc_pseudo_insns[]; 439 extern const unsigned arc_num_pseudo_insn; 440 441 /* Structure for AUXILIARY registers. */ 442 struct arc_aux_reg 443 { 444 /* Register address. */ 445 int address; 446 447 /* One bit flags for the opcode. These are primarily used to 448 indicate specific processors and environments support the 449 instructions. */ 450 unsigned cpu; 451 452 /* AUX register subclass. */ 453 insn_subclass_t subclass; 454 455 /* Register name. */ 456 const char * name; 457 458 /* Size of the string. */ 459 size_t length; 460 }; 461 462 extern const struct arc_aux_reg arc_aux_regs[]; 463 extern const unsigned arc_num_aux_regs; 464 465 extern const struct arc_opcode arc_relax_opcodes[]; 466 extern const unsigned arc_num_relax_opcodes; 467 468 /* Macro used for generating one class of NPS instructions. */ 469 #define NPS_CMEM_HIGH_VALUE 0x57f0 470 471 /* Macros to help generating regular pattern instructions. */ 472 #define FIELDA(word) (word & 0x3F) 473 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12)) 474 #define FIELDC(word) ((word & 0x3F) << 6) 475 #define FIELDF (0x01 << 15) 476 #define FIELDQ (0x1F) 477 478 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16)) 479 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F)) 480 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP)) 481 482 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP)) 483 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62)) 484 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62)) 485 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) 486 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62)) 487 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62)) 488 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62)) 489 #define INSN3OP_0LL(MOP,SOP) \ 490 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62)) 491 #define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22)) 492 #define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62)) 493 #define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22)) 494 #define INSN3OP_0LU(MOP,SOP) \ 495 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62)) 496 #define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22)) 497 #define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62)) 498 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22)) 499 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62)) 500 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62)) 501 #define INSN3OP_C0LL(MOP,SOP) \ 502 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62)) 503 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5)) 504 #define INSN3OP_C0LU(MOP,SOP) \ 505 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62)) 506 507 #define MASK_32BIT(VAL) (0xffffffff & (VAL)) 508 509 #define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) 510 #define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) 511 #define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63)))) 512 #define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63)))) 513 #define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63)))) 514 #define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63)))) 515 #define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63)))) 516 #define MINSN3OP_0LL (MASK_32BIT (~(FIELDF))) 517 #define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) 518 #define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) 519 #define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63)))) 520 #define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63)))) 521 #define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))) 522 #define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63)))) 523 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))) 524 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63)))) 525 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63)))) 526 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ))) 527 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))) 528 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63)))) 529 530 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP)) 531 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62)) 532 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)) 533 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62)) 534 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22)) 535 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62)) 536 537 #define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63))))) 538 #define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63))))) 539 #define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63))))) 540 #define MINSN2OP_0L (MASK_32BIT ((~(FIELDF)))) 541 #define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63))))) 542 #define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63))))) 543 544 /* Various constants used when defining an extension instruction. */ 545 #define ARC_SYNTAX_3OP (1 << 0) 546 #define ARC_SYNTAX_2OP (1 << 1) 547 #define ARC_SYNTAX_1OP (1 << 2) 548 #define ARC_SYNTAX_NOP (1 << 3) 549 #define ARC_SYNTAX_MASK (0x0F) 550 551 #define ARC_OP1_MUST_BE_IMM (1 << 0) 552 #define ARC_OP1_IMM_IMPLIED (1 << 1) 553 554 #define ARC_SUFFIX_NONE (1 << 0) 555 #define ARC_SUFFIX_COND (1 << 1) 556 #define ARC_SUFFIX_FLAG (1 << 2) 557 558 #define ARC_REGISTER_READONLY (1 << 0) 559 #define ARC_REGISTER_WRITEONLY (1 << 1) 560 #define ARC_REGISTER_NOSHORT_CUT (1 << 2) 561 562 /* Constants needed to initialize extension instructions. */ 563 extern const unsigned char flags_none[MAX_INSN_FLGS + 1]; 564 extern const unsigned char flags_f[MAX_INSN_FLGS + 1]; 565 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1]; 566 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1]; 567 568 extern const unsigned char arg_none[MAX_INSN_ARGS + 1]; 569 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1]; 570 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1]; 571 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1]; 572 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1]; 573 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1]; 574 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1]; 575 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1]; 576 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1]; 577 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1]; 578 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1]; 579 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1]; 580 581 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1]; 582 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1]; 583 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1]; 584 585 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1]; 586 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1]; 587 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1]; 588 589 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1]; 590 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1]; 591 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1]; 592 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1]; 593 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1]; 594 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1]; 595 596 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1]; 597 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1]; 598 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1]; 599 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1]; 600 601 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1]; 602 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1]; 603 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1]; 604 605 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP 606 Instruction Set Reference Manual v2.4 for a description of address types. */ 607 608 typedef enum 609 { 610 /* Addresses in memory. */ 611 612 /* Buffer descriptor. */ 613 ARC_NPS400_ADDRTYPE_BD, 614 615 /* Job identifier. */ 616 ARC_NPS400_ADDRTYPE_JID, 617 618 /* Linked Buffer Descriptor. */ 619 ARC_NPS400_ADDRTYPE_LBD, 620 621 /* Multicast Buffer Descriptor. */ 622 ARC_NPS400_ADDRTYPE_MBD, 623 624 /* Summarized Address. */ 625 ARC_NPS400_ADDRTYPE_SD, 626 627 /* SMEM Security Context Local Memory. */ 628 ARC_NPS400_ADDRTYPE_SM, 629 630 /* Extended Address. */ 631 ARC_NPS400_ADDRTYPE_XA, 632 633 /* Extended Summarized Address. */ 634 ARC_NPS400_ADDRTYPE_XD, 635 636 /* CMEM offset addresses. */ 637 638 /* On-demand Counter Descriptor. */ 639 ARC_NPS400_ADDRTYPE_CD, 640 641 /* CMEM Buffer Descriptor. */ 642 ARC_NPS400_ADDRTYPE_CBD, 643 644 /* CMEM Job Identifier. */ 645 ARC_NPS400_ADDRTYPE_CJID, 646 647 /* CMEM Linked Buffer Descriptor. */ 648 ARC_NPS400_ADDRTYPE_CLBD, 649 650 /* CMEM Offset. */ 651 ARC_NPS400_ADDRTYPE_CM, 652 653 /* CMEM Summarized Address. */ 654 ARC_NPS400_ADDRTYPE_CSD, 655 656 /* CMEM Extended Address. */ 657 ARC_NPS400_ADDRTYPE_CXA, 658 659 /* CMEM Extended Summarized Address. */ 660 ARC_NPS400_ADDRTYPE_CXD 661 662 } arc_nps_address_type; 663 664 #define ARC_NUM_ADDRTYPES 16 665 666 #ifdef __cplusplus 667 } 668 #endif 669 670 #endif /* OPCODE_ARC_H */ 671