1*c42dbd0eSchristos /* This file defines the interface between the RISC-V simulator and GDB. 2*c42dbd0eSchristos 3*c42dbd0eSchristos Copyright (C) 2005-2022 Free Software Foundation, Inc. 4*c42dbd0eSchristos Contributed by Mike Frysinger. 5*c42dbd0eSchristos 6*c42dbd0eSchristos This file is part of GDB. 7*c42dbd0eSchristos 8*c42dbd0eSchristos This program is free software; you can redistribute it and/or modify 9*c42dbd0eSchristos it under the terms of the GNU General Public License as published by 10*c42dbd0eSchristos the Free Software Foundation; either version 3 of the License, or 11*c42dbd0eSchristos (at your option) any later version. 12*c42dbd0eSchristos 13*c42dbd0eSchristos This program is distributed in the hope that it will be useful, 14*c42dbd0eSchristos but WITHOUT ANY WARRANTY; without even the implied warranty of 15*c42dbd0eSchristos MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*c42dbd0eSchristos GNU General Public License for more details. 17*c42dbd0eSchristos 18*c42dbd0eSchristos You should have received a copy of the GNU General Public License 19*c42dbd0eSchristos along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20*c42dbd0eSchristos 21*c42dbd0eSchristos /* Order has to match gdb riscv-tdep list. */ 22*c42dbd0eSchristos enum sim_riscv_regnum { 23*c42dbd0eSchristos SIM_RISCV_ZERO_REGNUM = 0, 24*c42dbd0eSchristos SIM_RISCV_RA_REGNUM, 25*c42dbd0eSchristos SIM_RISCV_SP_REGNUM, 26*c42dbd0eSchristos SIM_RISCV_GP_REGNUM, 27*c42dbd0eSchristos SIM_RISCV_TP_REGNUM, 28*c42dbd0eSchristos SIM_RISCV_T0_REGNUM, 29*c42dbd0eSchristos SIM_RISCV_T1_REGNUM, 30*c42dbd0eSchristos SIM_RISCV_T2_REGNUM, 31*c42dbd0eSchristos SIM_RISCV_S0_REGNUM, 32*c42dbd0eSchristos #define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM 33*c42dbd0eSchristos SIM_RISCV_S1_REGNUM, 34*c42dbd0eSchristos SIM_RISCV_A0_REGNUM, 35*c42dbd0eSchristos SIM_RISCV_A1_REGNUM, 36*c42dbd0eSchristos SIM_RISCV_A2_REGNUM, 37*c42dbd0eSchristos SIM_RISCV_A3_REGNUM, 38*c42dbd0eSchristos SIM_RISCV_A4_REGNUM, 39*c42dbd0eSchristos SIM_RISCV_A5_REGNUM, 40*c42dbd0eSchristos SIM_RISCV_A6_REGNUM, 41*c42dbd0eSchristos SIM_RISCV_A7_REGNUM, 42*c42dbd0eSchristos SIM_RISCV_S2_REGNUM, 43*c42dbd0eSchristos SIM_RISCV_S3_REGNUM, 44*c42dbd0eSchristos SIM_RISCV_S4_REGNUM, 45*c42dbd0eSchristos SIM_RISCV_S5_REGNUM, 46*c42dbd0eSchristos SIM_RISCV_S6_REGNUM, 47*c42dbd0eSchristos SIM_RISCV_S7_REGNUM, 48*c42dbd0eSchristos SIM_RISCV_S8_REGNUM, 49*c42dbd0eSchristos SIM_RISCV_S9_REGNUM, 50*c42dbd0eSchristos SIM_RISCV_S10_REGNUM, 51*c42dbd0eSchristos SIM_RISCV_S11_REGNUM, 52*c42dbd0eSchristos SIM_RISCV_T3_REGNUM, 53*c42dbd0eSchristos SIM_RISCV_T4_REGNUM, 54*c42dbd0eSchristos SIM_RISCV_T5_REGNUM, 55*c42dbd0eSchristos SIM_RISCV_T6_REGNUM, 56*c42dbd0eSchristos SIM_RISCV_PC_REGNUM, 57*c42dbd0eSchristos SIM_RISCV_FT0_REGNUM, 58*c42dbd0eSchristos #define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM 59*c42dbd0eSchristos SIM_RISCV_FT1_REGNUM, 60*c42dbd0eSchristos SIM_RISCV_FT2_REGNUM, 61*c42dbd0eSchristos SIM_RISCV_FT3_REGNUM, 62*c42dbd0eSchristos SIM_RISCV_FT4_REGNUM, 63*c42dbd0eSchristos SIM_RISCV_FT5_REGNUM, 64*c42dbd0eSchristos SIM_RISCV_FT6_REGNUM, 65*c42dbd0eSchristos SIM_RISCV_FT7_REGNUM, 66*c42dbd0eSchristos SIM_RISCV_FS0_REGNUM, 67*c42dbd0eSchristos SIM_RISCV_FS1_REGNUM, 68*c42dbd0eSchristos SIM_RISCV_FA0_REGNUM, 69*c42dbd0eSchristos SIM_RISCV_FA1_REGNUM, 70*c42dbd0eSchristos SIM_RISCV_FA2_REGNUM, 71*c42dbd0eSchristos SIM_RISCV_FA3_REGNUM, 72*c42dbd0eSchristos SIM_RISCV_FA4_REGNUM, 73*c42dbd0eSchristos SIM_RISCV_FA5_REGNUM, 74*c42dbd0eSchristos SIM_RISCV_FA6_REGNUM, 75*c42dbd0eSchristos SIM_RISCV_FA7_REGNUM, 76*c42dbd0eSchristos SIM_RISCV_FS2_REGNUM, 77*c42dbd0eSchristos SIM_RISCV_FS3_REGNUM, 78*c42dbd0eSchristos SIM_RISCV_FS4_REGNUM, 79*c42dbd0eSchristos SIM_RISCV_FS5_REGNUM, 80*c42dbd0eSchristos SIM_RISCV_FS6_REGNUM, 81*c42dbd0eSchristos SIM_RISCV_FS7_REGNUM, 82*c42dbd0eSchristos SIM_RISCV_FS8_REGNUM, 83*c42dbd0eSchristos SIM_RISCV_FS9_REGNUM, 84*c42dbd0eSchristos SIM_RISCV_FS10_REGNUM, 85*c42dbd0eSchristos SIM_RISCV_FS11_REGNUM, 86*c42dbd0eSchristos SIM_RISCV_FT8_REGNUM, 87*c42dbd0eSchristos SIM_RISCV_FT9_REGNUM, 88*c42dbd0eSchristos SIM_RISCV_FT10_REGNUM, 89*c42dbd0eSchristos SIM_RISCV_FT11_REGNUM, 90*c42dbd0eSchristos #define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM 91*c42dbd0eSchristos 92*c42dbd0eSchristos #define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1 93*c42dbd0eSchristos #define DECLARE_CSR(name, num, ...) SIM_RISCV_ ## num ## _REGNUM, 94*c42dbd0eSchristos #include "opcode/riscv-opc.h" 95*c42dbd0eSchristos #undef DECLARE_CSR 96*c42dbd0eSchristos #define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1 97*c42dbd0eSchristos 98*c42dbd0eSchristos SIM_RISCV_LAST_REGNUM 99*c42dbd0eSchristos }; 100