1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, 2@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 3@c Free Software Foundation, Inc. 4@c This is part of the GAS manual. 5@c For copying conditions, see the file as.texinfo. 6@ifset GENERIC 7@page 8@node MIPS-Dependent 9@chapter MIPS Dependent Features 10@end ifset 11@ifclear GENERIC 12@node Machine Dependencies 13@chapter MIPS Dependent Features 14@end ifclear 15 16@cindex MIPS processor 17@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 18different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32, 19and MIPS64. For information about the @sc{mips} instruction set, see 20@cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). 21For an overview of @sc{mips} assembly conventions, see ``Appendix D: 22Assembly Language Programming'' in the same work. 23 24@menu 25* MIPS Opts:: Assembler options 26* MIPS Object:: ECOFF object code 27* MIPS Stabs:: Directives for debugging information 28* MIPS ISA:: Directives to override the ISA level 29* MIPS symbol sizes:: Directives to override the size of symbols 30* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 31* MIPS insn:: Directive to mark data as an instruction 32* MIPS option stack:: Directives to save and restore options 33* MIPS ASE instruction generation overrides:: Directives to control 34 generation of MIPS ASE instructions 35* MIPS floating-point:: Directives to override floating-point options 36* MIPS Syntax:: MIPS specific syntactical considerations 37@end menu 38 39@node MIPS Opts 40@section Assembler options 41 42The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 43special options: 44 45@table @code 46@cindex @code{-G} option (MIPS) 47@item -G @var{num} 48This option sets the largest size of an object that can be referenced 49implicitly with the @code{gp} register. It is only accepted for targets 50that use @sc{ecoff} format. The default value is 8. 51 52@cindex @code{-EB} option (MIPS) 53@cindex @code{-EL} option (MIPS) 54@cindex MIPS big-endian output 55@cindex MIPS little-endian output 56@cindex big-endian output, MIPS 57@cindex little-endian output, MIPS 58@item -EB 59@itemx -EL 60Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or 61little-endian output at run time (unlike the other @sc{gnu} development 62tools, which must be configured for one or the other). Use @samp{-EB} 63to select big-endian output, and @samp{-EL} for little-endian. 64 65@item -KPIC 66@cindex PIC selection, MIPS 67@cindex @option{-KPIC} option, MIPS 68Generate SVR4-style PIC. This option tells the assembler to generate 69SVR4-style position-independent macro expansions. It also tells the 70assembler to mark the output file as PIC. 71 72@item -mvxworks-pic 73@cindex @option{-mvxworks-pic} option, MIPS 74Generate VxWorks PIC. This option tells the assembler to generate 75VxWorks-style position-independent macro expansions. 76 77@cindex MIPS architecture options 78@item -mips1 79@itemx -mips2 80@itemx -mips3 81@itemx -mips4 82@itemx -mips5 83@itemx -mips32 84@itemx -mips32r2 85@itemx -mips64 86@itemx -mips64r2 87Generate code for a particular MIPS Instruction Set Architecture level. 88@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 89@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 90@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 91@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, 92@samp{-mips64}, and @samp{-mips64r2} 93correspond to generic 94@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, 95and @sc{MIPS64 Release 2} 96ISA processors, respectively. You can also switch 97instruction sets during the assembly; see @ref{MIPS ISA, Directives to 98override the ISA level}. 99 100@item -mgp32 101@itemx -mfp32 102Some macros have different expansions for 32-bit and 64-bit registers. 103The register sizes are normally inferred from the ISA and ABI, but these 104flags force a certain group of registers to be treated as 32 bits wide at 105all times. @samp{-mgp32} controls the size of general-purpose registers 106and @samp{-mfp32} controls the size of floating-point registers. 107 108The @code{.set gp=32} and @code{.set fp=32} directives allow the size 109of registers to be changed for parts of an object. The default value is 110restored by @code{.set gp=default} and @code{.set fp=default}. 111 112On some MIPS variants there is a 32-bit mode flag; when this flag is 113set, 64-bit instructions generate a trap. Also, some 32-bit OSes only 114save the 32-bit registers on a context switch, so it is essential never 115to use the 64-bit registers. 116 117@item -mgp64 118@itemx -mfp64 119Assume that 64-bit registers are available. This is provided in the 120interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. 121 122The @code{.set gp=64} and @code{.set fp=64} directives allow the size 123of registers to be changed for parts of an object. The default value is 124restored by @code{.set gp=default} and @code{.set fp=default}. 125 126@item -mips16 127@itemx -no-mips16 128Generate code for the MIPS 16 processor. This is equivalent to putting 129@code{.set mips16} at the start of the assembly file. @samp{-no-mips16} 130turns off this option. 131 132@item -mmicromips 133@itemx -mno-micromips 134Generate code for the microMIPS processor. This is equivalent to putting 135@code{.set micromips} at the start of the assembly file. @samp{-mno-micromips} 136turns off this option. This is equivalent to putting @code{.set nomicromips} 137at the start of the assembly file. 138 139@item -msmartmips 140@itemx -mno-smartmips 141Enables the SmartMIPS extensions to the MIPS32 instruction set, which 142provides a number of new instructions which target smartcard and 143cryptographic applications. This is equivalent to putting 144@code{.set smartmips} at the start of the assembly file. 145@samp{-mno-smartmips} turns off this option. 146 147@item -mips3d 148@itemx -no-mips3d 149Generate code for the MIPS-3D Application Specific Extension. 150This tells the assembler to accept MIPS-3D instructions. 151@samp{-no-mips3d} turns off this option. 152 153@item -mdmx 154@itemx -no-mdmx 155Generate code for the MDMX Application Specific Extension. 156This tells the assembler to accept MDMX instructions. 157@samp{-no-mdmx} turns off this option. 158 159@item -mdsp 160@itemx -mno-dsp 161Generate code for the DSP Release 1 Application Specific Extension. 162This tells the assembler to accept DSP Release 1 instructions. 163@samp{-mno-dsp} turns off this option. 164 165@item -mdspr2 166@itemx -mno-dspr2 167Generate code for the DSP Release 2 Application Specific Extension. 168This option implies -mdsp. 169This tells the assembler to accept DSP Release 2 instructions. 170@samp{-mno-dspr2} turns off this option. 171 172@item -mmt 173@itemx -mno-mt 174Generate code for the MT Application Specific Extension. 175This tells the assembler to accept MT instructions. 176@samp{-mno-mt} turns off this option. 177 178@item -mmcu 179@itemx -mno-mcu 180Generate code for the MCU Application Specific Extension. 181This tells the assembler to accept MCU instructions. 182@samp{-mno-mcu} turns off this option. 183 184@item -mfix7000 185@itemx -mno-fix7000 186Cause nops to be inserted if the read of the destination register 187of an mfhi or mflo instruction occurs in the following two instructions. 188 189@item -mfix-loongson2f-jump 190@itemx -mno-fix-loongson2f-jump 191Eliminate instruction fetch from outside 256M region to work around the 192Loongson2F @samp{jump} instructions. Without it, under extreme cases, 193the kernel may crash. The issue has been solved in latest processor 194batches, but this fix has no side effect to them. 195 196@item -mfix-loongson2f-nop 197@itemx -mno-fix-loongson2f-nop 198Replace nops by @code{or at,at,zero} to work around the Loongson2F 199@samp{nop} errata. Without it, under extreme cases, cpu might 200deadlock. The issue has been solved in latest loongson2f batches, but 201this fix has no side effect to them. 202 203@item -mfix-vr4120 204@itemx -mno-fix-vr4120 205Insert nops to work around certain VR4120 errata. This option is 206intended to be used on GCC-generated code: it is not designed to catch 207all problems in hand-written assembler code. 208 209@item -mfix-vr4130 210@itemx -mno-fix-vr4130 211Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. 212 213@item -mfix-loongson2f-btb 214@itemx -mno-fix-loongson2f-btb 215Clear the Branch Target Buffer before any jump through a register. This 216option is intended to be used on kernel code for the Loongson 2F processor 217only; userland code compiled with this option will fault, and kernel code 218compiled with this option run on another processor than Loongson 2F will 219yield unpredictable results. 220 221@item -mfix-24k 222@itemx -mno-fix-24k 223Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. 224 225@item -mfix-cn63xxp1 226@itemx -mno-fix-cn63xxp1 227Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around 228certain CN63XXP1 errata. 229 230@item -m4010 231@itemx -no-m4010 232Generate code for the LSI @sc{r4010} chip. This tells the assembler to 233accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 234etc.), and to not schedule @samp{nop} instructions around accesses to 235the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 236option. 237 238@item -m4650 239@itemx -no-m4650 240Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 241the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 242instructions around accesses to the @samp{HI} and @samp{LO} registers. 243@samp{-no-m4650} turns off this option. 244 245@itemx -m3900 246@itemx -no-m3900 247@itemx -m4100 248@itemx -no-m4100 249For each option @samp{-m@var{nnnn}}, generate code for the MIPS 250@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 251specific to that chip, and to schedule for that chip's hazards. 252 253@item -march=@var{cpu} 254Generate code for a particular MIPS cpu. It is exactly equivalent to 255@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 256understood. Valid @var{cpu} value are: 257 258@quotation 2592000, 2603000, 2613900, 2624000, 2634010, 2644100, 2654111, 266vr4120, 267vr4130, 268vr4181, 2694300, 2704400, 2714600, 2724650, 2735000, 274rm5200, 275rm5230, 276rm5231, 277rm5261, 278rm5721, 279vr5400, 280vr5500, 2816000, 282rm7000, 2838000, 284rm9000, 28510000, 28612000, 28714000, 28816000, 2894kc, 2904km, 2914kp, 2924ksc, 2934kec, 2944kem, 2954kep, 2964ksd, 297m4k, 298m4kp, 299m14k, 300m14kc, 301m14ke, 302m14kec, 30324kc, 30424kf2_1, 30524kf, 30624kf1_1, 30724kec, 30824kef2_1, 30924kef, 31024kef1_1, 31134kc, 31234kf2_1, 31334kf, 31434kf1_1, 31574kc, 31674kf2_1, 31774kf, 31874kf1_1, 31974kf3_2, 3201004kc, 3211004kf2_1, 3221004kf, 3231004kf1_1, 3245kc, 3255kf, 32620kc, 32725kf, 328sb1, 329sb1a, 330loongson2e, 331loongson2f, 332loongson3a, 333octeon, 334octeon+, 335octeon2, 336xlr, 337xlp 338@end quotation 339 340For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are 341accepted as synonyms for @samp{@var{n}f1_1}. These values are 342deprecated. 343 344@item -mtune=@var{cpu} 345Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are 346identical to @samp{-march=@var{cpu}}. 347 348@item -mabi=@var{abi} 349Record which ABI the source code uses. The recognized arguments 350are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. 351 352@item -msym32 353@itemx -mno-sym32 354@cindex -msym32 355@cindex -mno-sym32 356Equivalent to adding @code{.set sym32} or @code{.set nosym32} to 357the beginning of the assembler input. @xref{MIPS symbol sizes}. 358 359@cindex @code{-nocpp} ignored (MIPS) 360@item -nocpp 361This option is ignored. It is accepted for command-line compatibility with 362other assemblers, which use it to turn off C style preprocessing. With 363@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 364@sc{gnu} assembler itself never runs the C preprocessor. 365 366@item -msoft-float 367@itemx -mhard-float 368Disable or enable floating-point instructions. Note that by default 369floating-point instructions are always allowed even with CPU targets 370that don't have support for these instructions. 371 372@item -msingle-float 373@itemx -mdouble-float 374Disable or enable double-precision floating-point operations. Note 375that by default double-precision floating-point operations are always 376allowed even with CPU targets that don't have support for these 377operations. 378 379@item --construct-floats 380@itemx --no-construct-floats 381The @code{--no-construct-floats} option disables the construction of 382double width floating point constants by loading the two halves of the 383value into the two single width floating point registers that make up 384the double width register. This feature is useful if the processor 385support the FR bit in its status register, and this bit is known (by 386the programmer) to be set. This bit prevents the aliasing of the double 387width register by the single width registers. 388 389By default @code{--construct-floats} is selected, allowing construction 390of these floating point constants. 391 392@item --trap 393@itemx --no-break 394@c FIXME! (1) reflect these options (next item too) in option summaries; 395@c (2) stop teasing, say _which_ instructions expanded _how_. 396@code{@value{AS}} automatically macro expands certain division and 397multiplication instructions to check for overflow and division by zero. This 398option causes @code{@value{AS}} to generate code to take a trap exception 399rather than a break exception when an error is detected. The trap instructions 400are only supported at Instruction Set Architecture level 2 and higher. 401 402@item --break 403@itemx --no-trap 404Generate code to take a break exception rather than a trap exception when an 405error is detected. This is the default. 406 407@item -mpdr 408@itemx -mno-pdr 409Control generation of @code{.pdr} sections. Off by default on IRIX, on 410elsewhere. 411 412@item -mshared 413@itemx -mno-shared 414When generating code using the Unix calling conventions (selected by 415@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code 416which can go into a shared library. The @samp{-mno-shared} option 417tells gas to generate code which uses the calling convention, but can 418not go into a shared library. The resulting code is slightly more 419efficient. This option only affects the handling of the 420@samp{.cpload} and @samp{.cpsetup} pseudo-ops. 421@end table 422 423@node MIPS Object 424@section MIPS ECOFF object code 425 426@cindex ECOFF sections 427@cindex MIPS ECOFF sections 428Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections 429besides the usual @code{.text}, @code{.data} and @code{.bss}. The 430additional sections are @code{.rdata}, used for read-only data, 431@code{.sdata}, used for small data, and @code{.sbss}, used for small 432common objects. 433 434@cindex small objects, MIPS ECOFF 435@cindex @code{gp} register, MIPS 436When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 437register to form the address of a ``small object''. Any object in the 438@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 439For external objects, or for objects in the @code{.bss} section, you can use 440the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 441@code{$gp}; the default value is 8, meaning that a reference to any object 442eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 443@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 444of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 445or @code{sbss} in any case). The size of an object in the @code{.bss} section 446is set by the @code{.comm} or @code{.lcomm} directive that defines it. The 447size of an external object may be set with the @code{.extern} directive. For 448example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 449in length, whie leaving @code{sym} otherwise undefined. 450 451Using small @sc{ecoff} objects requires linker support, and assumes that the 452@code{$gp} register is correctly initialized (normally done automatically by 453the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 454@code{$gp} register. 455 456@node MIPS Stabs 457@section Directives for debugging information 458 459@cindex MIPS debugging directives 460@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 461generating debugging information which are not support by traditional @sc{mips} 462assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 463@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 464@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 465generated by the three @code{.stab} directives can only be read by @sc{gdb}, 466not by traditional @sc{mips} debuggers (this enhancement is required to fully 467support C++ debugging). These directives are primarily used by compilers, not 468assembly language programmers! 469 470@node MIPS symbol sizes 471@section Directives to override the size of symbols 472 473@cindex @code{.set sym32} 474@cindex @code{.set nosym32} 475The n64 ABI allows symbols to have any 64-bit value. Although this 476provides a great deal of flexibility, it means that some macros have 477much longer expansions than their 32-bit counterparts. For example, 478the non-PIC expansion of @samp{dla $4,sym} is usually: 479 480@smallexample 481lui $4,%highest(sym) 482lui $1,%hi(sym) 483daddiu $4,$4,%higher(sym) 484daddiu $1,$1,%lo(sym) 485dsll32 $4,$4,0 486daddu $4,$4,$1 487@end smallexample 488 489whereas the 32-bit expansion is simply: 490 491@smallexample 492lui $4,%hi(sym) 493daddiu $4,$4,%lo(sym) 494@end smallexample 495 496n64 code is sometimes constructed in such a way that all symbolic 497constants are known to have 32-bit values, and in such cases, it's 498preferable to use the 32-bit expansion instead of the 64-bit 499expansion. 500 501You can use the @code{.set sym32} directive to tell the assembler 502that, from this point on, all expressions of the form 503@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} 504have 32-bit values. For example: 505 506@smallexample 507.set sym32 508dla $4,sym 509lw $4,sym+16 510sw $4,sym+0x8000($4) 511@end smallexample 512 513will cause the assembler to treat @samp{sym}, @code{sym+16} and 514@code{sym+0x8000} as 32-bit values. The handling of non-symbolic 515addresses is not affected. 516 517The directive @code{.set nosym32} ends a @code{.set sym32} block and 518reverts to the normal behavior. It is also possible to change the 519symbol size using the command-line options @option{-msym32} and 520@option{-mno-sym32}. 521 522These options and directives are always accepted, but at present, 523they have no effect for anything other than n64. 524 525@node MIPS ISA 526@section Directives to override the ISA level 527 528@cindex MIPS ISA override 529@kindex @code{.set mips@var{n}} 530@sc{gnu} @code{@value{AS}} supports an additional directive to change 531the @sc{mips} Instruction Set Architecture level on the fly: @code{.set 532mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 533or 64r2. 534The values other than 0 make the assembler accept instructions 535for the corresponding @sc{isa} level, from that point on in the 536assembly. @code{.set mips@var{n}} affects not only which instructions 537are permitted, but also how certain macros are expanded. @code{.set 538mips0} restores the @sc{isa} level to its original level: either the 539level you selected with command line options, or the default for your 540configuration. You can use this feature to permit specific @sc{mips3} 541instructions while assembling in 32 bit mode. Use this directive with 542care! 543 544@cindex MIPS CPU override 545@kindex @code{.set arch=@var{cpu}} 546The @code{.set arch=@var{cpu}} directive provides even finer control. 547It changes the effective CPU target and allows the assembler to use 548instructions specific to a particular CPU. All CPUs supported by the 549@samp{-march} command line option are also selectable by this directive. 550The original value is restored by @code{.set arch=default}. 551 552The directive @code{.set mips16} puts the assembler into MIPS 16 mode, 553in which it will assemble instructions for the MIPS 16 processor. Use 554@code{.set nomips16} to return to normal 32 bit mode. 555 556Traditional @sc{mips} assemblers do not support this directive. 557 558The directive @code{.set micromips} puts the assembler into microMIPS mode, 559in which it will assemble instructions for the microMIPS processor. Use 560@code{.set nomicromips} to return to normal 32 bit mode. 561 562Traditional @sc{mips} assemblers do not support this directive. 563 564@node MIPS autoextend 565@section Directives for extending MIPS 16 bit instructions 566 567@kindex @code{.set autoextend} 568@kindex @code{.set noautoextend} 569By default, MIPS 16 instructions are automatically extended to 32 bits 570when necessary. The directive @code{.set noautoextend} will turn this 571off. When @code{.set noautoextend} is in effect, any 32 bit instruction 572must be explicitly extended with the @code{.e} modifier (e.g., 573@code{li.e $4,1000}). The directive @code{.set autoextend} may be used 574to once again automatically extend instructions when necessary. 575 576This directive is only meaningful when in MIPS 16 mode. Traditional 577@sc{mips} assemblers do not support this directive. 578 579@node MIPS insn 580@section Directive to mark data as an instruction 581 582@kindex @code{.insn} 583The @code{.insn} directive tells @code{@value{AS}} that the following 584data is actually instructions. This makes a difference in MIPS 16 and 585microMIPS modes: when loading the address of a label which precedes 586instructions, @code{@value{AS}} automatically adds 1 to the value, so 587that jumping to the loaded address will do the right thing. 588 589@kindex @code{.global} 590The @code{.global} and @code{.globl} directives supported by 591@code{@value{AS}} will by default mark the symbol as pointing to a 592region of data not code. This means that, for example, any 593instructions following such a symbol will not be disassembled by 594@code{objdump} as it will regard them as data. To change this 595behaviour an optional section name can be placed after the symbol name 596in the @code{.global} directive. If this section exists and is known 597to be a code section, then the symbol will be marked as poiting at 598code not data. Ie the syntax for the directive is: 599 600 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, 601 602Here is a short example: 603 604@example 605 .global foo .text, bar, baz .data 606foo: 607 nop 608bar: 609 .word 0x0 610baz: 611 .word 0x1 612 613@end example 614 615@node MIPS option stack 616@section Directives to save and restore options 617 618@cindex MIPS option stack 619@kindex @code{.set push} 620@kindex @code{.set pop} 621The directives @code{.set push} and @code{.set pop} may be used to save 622and restore the current settings for all the options which are 623controlled by @code{.set}. The @code{.set push} directive saves the 624current settings on a stack. The @code{.set pop} directive pops the 625stack and restores the settings. 626 627These directives can be useful inside an macro which must change an 628option such as the ISA level or instruction reordering but does not want 629to change the state of the code which invoked the macro. 630 631Traditional @sc{mips} assemblers do not support these directives. 632 633@node MIPS ASE instruction generation overrides 634@section Directives to control generation of MIPS ASE instructions 635 636@cindex MIPS MIPS-3D instruction generation override 637@kindex @code{.set mips3d} 638@kindex @code{.set nomips3d} 639The directive @code{.set mips3d} makes the assembler accept instructions 640from the MIPS-3D Application Specific Extension from that point on 641in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D 642instructions from being accepted. 643 644@cindex SmartMIPS instruction generation override 645@kindex @code{.set smartmips} 646@kindex @code{.set nosmartmips} 647The directive @code{.set smartmips} makes the assembler accept 648instructions from the SmartMIPS Application Specific Extension to the 649MIPS32 @sc{isa} from that point on in the assembly. The 650@code{.set nosmartmips} directive prevents SmartMIPS instructions from 651being accepted. 652 653@cindex MIPS MDMX instruction generation override 654@kindex @code{.set mdmx} 655@kindex @code{.set nomdmx} 656The directive @code{.set mdmx} makes the assembler accept instructions 657from the MDMX Application Specific Extension from that point on 658in the assembly. The @code{.set nomdmx} directive prevents MDMX 659instructions from being accepted. 660 661@cindex MIPS DSP Release 1 instruction generation override 662@kindex @code{.set dsp} 663@kindex @code{.set nodsp} 664The directive @code{.set dsp} makes the assembler accept instructions 665from the DSP Release 1 Application Specific Extension from that point 666on in the assembly. The @code{.set nodsp} directive prevents DSP 667Release 1 instructions from being accepted. 668 669@cindex MIPS DSP Release 2 instruction generation override 670@kindex @code{.set dspr2} 671@kindex @code{.set nodspr2} 672The directive @code{.set dspr2} makes the assembler accept instructions 673from the DSP Release 2 Application Specific Extension from that point 674on in the assembly. This dirctive implies @code{.set dsp}. The 675@code{.set nodspr2} directive prevents DSP Release 2 instructions from 676being accepted. 677 678@cindex MIPS MT instruction generation override 679@kindex @code{.set mt} 680@kindex @code{.set nomt} 681The directive @code{.set mt} makes the assembler accept instructions 682from the MT Application Specific Extension from that point on 683in the assembly. The @code{.set nomt} directive prevents MT 684instructions from being accepted. 685 686@cindex MIPS MCU instruction generation override 687@kindex @code{.set mcu} 688@kindex @code{.set nomcu} 689The directive @code{.set mcu} makes the assembler accept instructions 690from the MCU Application Specific Extension from that point on 691in the assembly. The @code{.set nomcu} directive prevents MCU 692instructions from being accepted. 693 694Traditional @sc{mips} assemblers do not support these directives. 695 696@node MIPS floating-point 697@section Directives to override floating-point options 698 699@cindex Disable floating-point instructions 700@kindex @code{.set softfloat} 701@kindex @code{.set hardfloat} 702The directives @code{.set softfloat} and @code{.set hardfloat} provide 703finer control of disabling and enabling float-point instructions. 704These directives always override the default (that hard-float 705instructions are accepted) or the command-line options 706(@samp{-msoft-float} and @samp{-mhard-float}). 707 708@cindex Disable single-precision floating-point operations 709@kindex @code{.set singlefloat} 710@kindex @code{.set doublefloat} 711The directives @code{.set singlefloat} and @code{.set doublefloat} 712provide finer control of disabling and enabling double-precision 713float-point operations. These directives always override the default 714(that double-precision operations are accepted) or the command-line 715options (@samp{-msingle-float} and @samp{-mdouble-float}). 716 717Traditional @sc{mips} assemblers do not support these directives. 718 719@node MIPS Syntax 720@section Syntactical considerations for the MIPS assembler 721@menu 722* MIPS-Chars:: Special Characters 723@end menu 724 725@node MIPS-Chars 726@subsection Special Characters 727 728@cindex line comment character, MIPS 729@cindex MIPS line comment character 730The presence of a @samp{#} on a line indicates the start of a comment 731that extends to the end of the current line. 732 733If a @samp{#} appears as the first character of a line, the whole line 734is treated as a comment, but in this case the line can also be a 735logical line number directive (@pxref{Comments}) or a 736preprocessor control command (@pxref{Preprocessing}). 737 738@cindex line separator, MIPS 739@cindex statement separator, MIPS 740@cindex MIPS line separator 741The @samp{;} character can be used to separate statements on the same 742line. 743