1@c Copyright 2005, 2006, 2009, 2010, 2011 2@c Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@c man end 6 7@ifset GENERIC 8@page 9@node Blackfin-Dependent 10@chapter Blackfin Dependent Features 11@end ifset 12 13@ifclear GENERIC 14@node Machine Dependencies 15@chapter Blackfin Dependent Features 16@end ifclear 17 18@cindex Blackfin support 19@menu 20* Blackfin Options:: Blackfin Options 21* Blackfin Syntax:: Blackfin Syntax 22* Blackfin Directives:: Blackfin Directives 23@end menu 24 25@node Blackfin Options 26@section Options 27@cindex Blackfin options (none) 28@cindex options for Blackfin (none) 29 30@c man begin OPTIONS 31@table @gcctabopt 32 33@cindex @code{-mcpu=} command line option, Blackfin 34@item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]} 35This option specifies the target processor. The optional @var{sirevision} 36is not used in assembler. It's here such that GCC can easily pass down its 37@code{-mcpu=} option. The assembler will issue an 38error message if an attempt is made to assemble an instruction which 39will not execute on the target processor. The following processor names are 40recognized: 41@code{bf504}, 42@code{bf506}, 43@code{bf512}, 44@code{bf514}, 45@code{bf516}, 46@code{bf518}, 47@code{bf522}, 48@code{bf523}, 49@code{bf524}, 50@code{bf525}, 51@code{bf526}, 52@code{bf527}, 53@code{bf531}, 54@code{bf532}, 55@code{bf533}, 56@code{bf534}, 57@code{bf535} (not implemented yet), 58@code{bf536}, 59@code{bf537}, 60@code{bf538}, 61@code{bf539}, 62@code{bf542}, 63@code{bf542m}, 64@code{bf544}, 65@code{bf544m}, 66@code{bf547}, 67@code{bf547m}, 68@code{bf548}, 69@code{bf548m}, 70@code{bf549}, 71@code{bf549m}, 72@code{bf561}, 73and 74@code{bf592}. 75 76@cindex @code{-mfdpic} command line option, Blackfin 77@item -mfdpic 78Assemble for the FDPIC ABI. 79 80@cindex @code{-mno-fdpic} command line option, Blackfin 81@cindex @code{-mnopic} command line option, Blackfin 82@item -mno-fdpic 83@itemx -mnopic 84Disable -mfdpic. 85@end table 86@c man end 87 88@node Blackfin Syntax 89@section Syntax 90@cindex Blackfin syntax 91@cindex syntax, Blackfin 92 93@table @code 94@item Special Characters 95Assembler input is free format and may appear anywhere on the line. 96One instruction may extend across multiple lines or more than one 97instruction may appear on the same line. White space (space, tab, 98comments or newline) may appear anywhere between tokens. A token must 99not have embedded spaces. Tokens include numbers, register names, 100keywords, user identifiers, and also some multicharacter special 101symbols like "+=", "/*" or "||". 102 103Comments are introduced by the @samp{#} character and extend to the 104end of the current line. If the @samp{#} appears as the first 105character of a line, the whole line is treated as a comment, but in 106this case the line can also be a logical line number directive 107(@pxref{Comments}) or a preprocessor control command 108(@pxref{Preprocessing}). 109 110@item Instruction Delimiting 111A semicolon must terminate every instruction. Sometimes a complete 112instruction will consist of more than one operation. There are two 113cases where this occurs. The first is when two general operations 114are combined. Normally a comma separates the different parts, as in 115 116@smallexample 117a0= r3.h * r2.l, a1 = r3.l * r2.h ; 118@end smallexample 119 120The second case occurs when a general instruction is combined with one 121or two memory references for joint issue. The latter portions are 122set off by a "||" token. 123 124@smallexample 125a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 126@end smallexample 127 128Multiple instructions can occur on the same line. Each must be 129terminated by a semicolon character. 130 131@item Register Names 132 133The assembler treats register names and instruction keywords in a case 134insensitive manner. User identifiers are case sensitive. Thus, R3.l, 135R3.L, r3.l and r3.L are all equivalent input to the assembler. 136 137Register names are reserved and may not be used as program identifiers. 138 139Some operations (such as "Move Register") require a register pair. 140Register pairs are always data registers and are denoted using a colon, 141eg., R3:2. The larger number must be written firsts. Note that the 142hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0. 143 144Some instructions (such as --SP (Push Multiple)) require a group of 145adjacent registers. Adjacent registers are denoted in the syntax by 146the range enclosed in parentheses and separated by a colon, eg., (R7:3). 147Again, the larger number appears first. 148 149Portions of a particular register may be individually specified. This 150is written with a dot (".") following the register name and then a 151letter denoting the desired portion. For 32-bit registers, ".H" 152denotes the most significant ("High") portion. ".L" denotes the 153least-significant portion. The subdivisions of the 40-bit registers 154are described later. 155 156@item Accumulators 157The set of 40-bit registers A1 and A0 that normally contain data that 158is being manipulated. Each accumulator can be accessed in four ways. 159 160@table @code 161@item one 40-bit register 162The register will be referred to as A1 or A0. 163@item one 32-bit register 164The registers are designated as A1.W or A0.W. 165@item two 16-bit registers 166The registers are designated as A1.H, A1.L, A0.H or A0.L. 167@item one 8-bit register 168The registers are designated as A1.X or A0.X for the bits that 169extend beyond bit 31. 170@end table 171 172@item Data Registers 173The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that 174normally contain data for manipulation. These are abbreviated as 175D-register or Dreg. Data registers can be accessed as 32-bit registers 176or as two independent 16-bit registers. The least significant 16 bits 177of each register is called the "low" half and is designated with ".L" 178following the register name. The most significant 16 bits are called 179the "high" half and is designated with ".H" following the name. 180 181@smallexample 182 R7.L, r2.h, r4.L, R0.H 183@end smallexample 184 185@item Pointer Registers 186The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that 187normally contain byte addresses of data structures. These are 188abbreviated as P-register or Preg. 189 190@smallexample 191p2, p5, fp, sp 192@end smallexample 193 194@item Stack Pointer SP 195The stack pointer contains the 32-bit address of the last occupied 196byte location in the stack. The stack grows by decrementing the 197stack pointer. 198 199@item Frame Pointer FP 200The frame pointer contains the 32-bit address of the previous frame 201pointer in the stack. It is located at the top of a frame. 202 203@item Loop Top 204LT0 and LT1. These registers contain the 32-bit address of the top of 205a zero overhead loop. 206 207@item Loop Count 208LC0 and LC1. These registers contain the 32-bit counter of the zero 209overhead loop executions. 210 211@item Loop Bottom 212LB0 and LB1. These registers contain the 32-bit address of the bottom 213of a zero overhead loop. 214 215@item Index Registers 216The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte 217addresses of data structures. Abbreviated I-register or Ireg. 218 219@item Modify Registers 220The set of 32-bit registers (M0, M1, M2, M3) that normally contain 221offset values that are added and subtracted to one of the index 222registers. Abbreviated as Mreg. 223 224@item Length Registers 225The set of 32-bit registers (L0, L1, L2, L3) that normally contain the 226length in bytes of the circular buffer. Abbreviated as Lreg. Clear 227the Lreg to disable circular addressing for the corresponding Ireg. 228 229@item Base Registers 230The set of 32-bit registers (B0, B1, B2, B3) that normally contain the 231base address in bytes of the circular buffer. Abbreviated as Breg. 232 233@item Floating Point 234The Blackfin family has no hardware floating point but the .float 235directive generates ieee floating point numbers for use with software 236floating point libraries. 237 238@item Blackfin Opcodes 239For detailed information on the Blackfin machine instruction set, see 240the Blackfin(r) Processor Instruction Set Reference. 241 242@end table 243 244@node Blackfin Directives 245@section Directives 246@cindex Blackfin directives 247@cindex directives, Blackfin 248 249The following directives are provided for compatibility with the VDSP assembler. 250 251@table @code 252@item .byte2 253Initializes a two byte data object. 254 255This maps to the @code{.short} directive. 256@item .byte4 257Initializes a four byte data object. 258 259This maps to the @code{.int} directive. 260@item .db 261Initializes a single byte data object. 262 263This directive is a synonym for @code{.byte}. 264@item .dw 265Initializes a two byte data object. 266 267This directive is a synonym for @code{.byte2}. 268@item .dd 269Initializes a four byte data object. 270 271This directive is a synonym for @code{.byte4}. 272@item .var 273Define and initialize a 32 bit data object. 274@end table 275