1This is as.info, produced by makeinfo version 6.5 from as.texi. 2 3This file documents the GNU Assembler "as". 4 5 Copyright (C) 1991-2020 Free Software Foundation, Inc. 6 7 Permission is granted to copy, distribute and/or modify this document 8under the terms of the GNU Free Documentation License, Version 1.3 or 9any later version published by the Free Software Foundation; with no 10Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 11Texts. A copy of the license is included in the section entitled "GNU 12Free Documentation License". 13 14INFO-DIR-SECTION Software development 15START-INFO-DIR-ENTRY 16* As: (as). The GNU assembler. 17* Gas: (as). The GNU assembler. 18END-INFO-DIR-ENTRY 19 20 21File: as.info, Node: Top, Next: Overview, Up: (dir) 22 23Using as 24******** 25 26This file is a user guide to the GNU assembler 'as' (GNU Binutils) 27version 2.34. 28 29 This document is distributed under the terms of the GNU Free 30Documentation License. A copy of the license is included in the section 31entitled "GNU Free Documentation License". 32 33* Menu: 34 35* Overview:: Overview 36* Invoking:: Command-Line Options 37* Syntax:: Syntax 38* Sections:: Sections and Relocation 39* Symbols:: Symbols 40* Expressions:: Expressions 41* Pseudo Ops:: Assembler Directives 42* Object Attributes:: Object Attributes 43* Machine Dependencies:: Machine Dependent Features 44* Reporting Bugs:: Reporting Bugs 45* Acknowledgements:: Who Did What 46* GNU Free Documentation License:: GNU Free Documentation License 47* AS Index:: AS Index 48 49 50File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 51 521 Overview 53********** 54 55Here is a brief summary of how to invoke 'as'. For details, see *note 56Command-Line Options: Invoking. 57 58 as [-a[cdghlns][=FILE]] [-alternate] [-D] 59 [-compress-debug-sections] [-nocompress-debug-sections] 60 [-debug-prefix-map OLD=NEW] 61 [-defsym SYM=VAL] [-f] [-g] [-gstabs] 62 [-gstabs+] [-gdwarf-2] [-gdwarf-sections] 63 [-gdwarf-cie-version=VERSION] 64 [-help] [-I DIR] [-J] 65 [-K] [-L] [-listing-lhs-width=NUM] 66 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] 67 [-listing-cont-lines=NUM] [-keep-locals] 68 [-no-pad-sections] 69 [-o OBJFILE] [-R] 70 [-hash-size=NUM] [-reduce-memory-overheads] 71 [-statistics] 72 [-v] [-version] [-version] 73 [-W] [-warn] [-fatal-warnings] [-w] [-x] 74 [-Z] [@FILE] 75 [-sectname-subst] [-size-check=[error|warning]] 76 [-elf-stt-common=[no|yes]] 77 [-generate-missing-build-notes=[no|yes]] 78 [-target-help] [TARGET-OPTIONS] 79 [-|FILES ...] 80 81 _Target AArch64 options:_ 82 [-EB|-EL] 83 [-mabi=ABI] 84 85 _Target Alpha options:_ 86 [-mCPU] 87 [-mdebug | -no-mdebug] 88 [-replace | -noreplace] 89 [-relax] [-g] [-GSIZE] 90 [-F] [-32addr] 91 92 _Target ARC options:_ 93 [-mcpu=CPU] 94 [-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS] 95 [-mcode-density] 96 [-mrelax] 97 [-EB|-EL] 98 99 _Target ARM options:_ 100 [-mcpu=PROCESSOR[+EXTENSION...]] 101 [-march=ARCHITECTURE[+EXTENSION...]] 102 [-mfpu=FLOATING-POINT-FORMAT] 103 [-mfloat-abi=ABI] 104 [-meabi=VER] 105 [-mthumb] 106 [-EB|-EL] 107 [-mapcs-32|-mapcs-26|-mapcs-float| 108 -mapcs-reentrant] 109 [-mthumb-interwork] [-k] 110 111 _Target Blackfin options:_ 112 [-mcpu=PROCESSOR[-SIREVISION]] 113 [-mfdpic] 114 [-mno-fdpic] 115 [-mnopic] 116 117 _Target BPF options:_ 118 [-EL] [-EB] 119 120 _Target CRIS options:_ 121 [-underscore | -no-underscore] 122 [-pic] [-N] 123 [-emulation=criself | -emulation=crisaout] 124 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] 125 126 _Target C-SKY options:_ 127 [-march=ARCH] [-mcpu=CPU] 128 [-EL] [-mlittle-endian] [-EB] [-mbig-endian] 129 [-fpic] [-pic] 130 [-mljump] [-mno-ljump] 131 [-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr] 132 [-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr] 133 [-mnolrw ] [-mno-lrw] 134 [-melrw] [-mno-elrw] 135 [-mlaf ] [-mliterals-after-func] 136 [-mno-laf] [-mno-literals-after-func] 137 [-mlabr] [-mliterals-after-br] 138 [-mno-labr] [-mnoliterals-after-br] 139 [-mistack] [-mno-istack] 140 [-mhard-float] [-mmp] [-mcp] [-mcache] 141 [-msecurity] [-mtrust] 142 [-mdsp] [-medsp] [-mvdsp] 143 144 _Target D10V options:_ 145 [-O] 146 147 _Target D30V options:_ 148 [-O|-n|-N] 149 150 _Target EPIPHANY options:_ 151 [-mepiphany|-mepiphany16] 152 153 _Target H8/300 options:_ 154 [-h-tick-hex] 155 156 _Target i386 options:_ 157 [-32|-x32|-64] [-n] 158 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 159 160 _Target IA-64 options:_ 161 [-mconstant-gp|-mauto-pic] 162 [-milp32|-milp64|-mlp64|-mp64] 163 [-mle|mbe] 164 [-mtune=itanium1|-mtune=itanium2] 165 [-munwind-check=warning|-munwind-check=error] 166 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 167 [-x|-xexplicit] [-xauto] [-xdebug] 168 169 _Target IP2K options:_ 170 [-mip2022|-mip2022ext] 171 172 _Target M32C options:_ 173 [-m32c|-m16c] [-relax] [-h-tick-hex] 174 175 _Target M32R options:_ 176 [-m32rx|-[no-]warn-explicit-parallel-conflicts| 177 -W[n]p] 178 179 _Target M680X0 options:_ 180 [-l] [-m68000|-m68010|-m68020|...] 181 182 _Target M68HC11 options:_ 183 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] 184 [-mshort|-mlong] 185 [-mshort-double|-mlong-double] 186 [-force-long-branches] [-short-branches] 187 [-strict-direct-mode] [-print-insn-syntax] 188 [-print-opcodes] [-generate-example] 189 190 _Target MCORE options:_ 191 [-jsri2bsr] [-sifilter] [-relax] 192 [-mcpu=[210|340]] 193 194 _Target Meta options:_ 195 [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU] 196 _Target MICROBLAZE options:_ 197 198 _Target MIPS options:_ 199 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 200 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 201 [-non_shared] [-xgot [-mvxworks-pic] 202 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 203 [-mfp64] [-mgp64] [-mfpxx] 204 [-modd-spreg] [-mno-odd-spreg] 205 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 206 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 207 [-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2] 208 [-mips64r3] [-mips64r5] [-mips64r6] 209 [-construct-floats] [-no-construct-floats] 210 [-mignore-branch-isa] [-mno-ignore-branch-isa] 211 [-mnan=ENCODING] 212 [-trap] [-no-break] [-break] [-no-trap] 213 [-mips16] [-no-mips16] 214 [-mmips16e2] [-mno-mips16e2] 215 [-mmicromips] [-mno-micromips] 216 [-msmartmips] [-mno-smartmips] 217 [-mips3d] [-no-mips3d] 218 [-mdmx] [-no-mdmx] 219 [-mdsp] [-mno-dsp] 220 [-mdspr2] [-mno-dspr2] 221 [-mdspr3] [-mno-dspr3] 222 [-mmsa] [-mno-msa] 223 [-mxpa] [-mno-xpa] 224 [-mmt] [-mno-mt] 225 [-mmcu] [-mno-mcu] 226 [-mcrc] [-mno-crc] 227 [-mginv] [-mno-ginv] 228 [-mloongson-mmi] [-mno-loongson-mmi] 229 [-mloongson-cam] [-mno-loongson-cam] 230 [-mloongson-ext] [-mno-loongson-ext] 231 [-mloongson-ext2] [-mno-loongson-ext2] 232 [-minsn32] [-mno-insn32] 233 [-mfix7000] [-mno-fix7000] 234 [-mfix-rm7000] [-mno-fix-rm7000] 235 [-mfix-vr4120] [-mno-fix-vr4120] 236 [-mfix-vr4130] [-mno-fix-vr4130] 237 [-mfix-r5900] [-mno-fix-r5900] 238 [-mdebug] [-no-mdebug] 239 [-mpdr] [-mno-pdr] 240 241 _Target MMIX options:_ 242 [-fixed-special-register-names] [-globalize-symbols] 243 [-gnu-syntax] [-relax] [-no-predefined-symbols] 244 [-no-expand] [-no-merge-gregs] [-x] 245 [-linker-allocated-gregs] 246 247 _Target Nios II options:_ 248 [-relax-all] [-relax-section] [-no-relax] 249 [-EB] [-EL] 250 251 _Target NDS32 options:_ 252 [-EL] [-EB] [-O] [-Os] [-mcpu=CPU] 253 [-misa=ISA] [-mabi=ABI] [-mall-ext] 254 [-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext] 255 [-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div] 256 [-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext] 257 [-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs] 258 [-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax] 259 [-mb2bb] 260 261 _Target PDP11 options:_ 262 [-mpic|-mno-pic] [-mall] [-mno-extensions] 263 [-mEXTENSION|-mno-EXTENSION] 264 [-mCPU] [-mMACHINE] 265 266 _Target picoJava options:_ 267 [-mb|-me] 268 269 _Target PowerPC options:_ 270 [-a32|-a64] 271 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| 272 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko| 273 -mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500| 274 -me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x| 275 -mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2| 276 -mcell|-mspe|-mspe2|-mtitan|-me300|-mcom] 277 [-many] [-maltivec|-mvsx|-mhtm|-mvle] 278 [-mregnames|-mno-regnames] 279 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] 280 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] 281 [-msolaris|-mno-solaris] 282 [-nops=COUNT] 283 284 _Target PRU options:_ 285 [-link-relax] 286 [-mnolink-relax] 287 [-mno-warn-regname-label] 288 289 _Target RISC-V options:_ 290 [-fpic|-fPIC|-fno-pic] 291 [-march=ISA] 292 [-mabi=ABI] 293 294 _Target RL78 options:_ 295 [-mg10] 296 [-m32bit-doubles|-m64bit-doubles] 297 298 _Target RX options:_ 299 [-mlittle-endian|-mbig-endian] 300 [-m32bit-doubles|-m64bit-doubles] 301 [-muse-conventional-section-names] 302 [-msmall-data-limit] 303 [-mpid] 304 [-mrelax] 305 [-mint-register=NUMBER] 306 [-mgcc-abi|-mrx-abi] 307 308 _Target s390 options:_ 309 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 310 [-mregnames|-mno-regnames] 311 [-mwarn-areg-zero] 312 313 _Target SCORE options:_ 314 [-EB][-EL][-FIXDD][-NWARN] 315 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 316 [-march=score7][-march=score3] 317 [-USE_R1][-KPIC][-O0][-G NUM][-V] 318 319 _Target SPARC options:_ 320 [-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite 321 -Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd 322 -Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c 323 -Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis 324 -Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3 325 -Asparcvisr|-Asparc5] 326 [-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc 327 -xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9 328 -xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e 329 -xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis 330 -xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima 331 -xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5 332 -bump] 333 [-32|-64] 334 [-enforce-aligned-data][-dcti-couples-detect] 335 336 _Target TIC54X options:_ 337 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 338 [-merrors-to-file <FILENAME>|-me <FILENAME>] 339 340 _Target TIC6X options:_ 341 [-march=ARCH] [-mbig-endian|-mlittle-endian] 342 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] 343 [-mpic|-mno-pic] 344 345 _Target TILE-Gx options:_ 346 [-m32|-m64][-EB][-EL] 347 348 _Target Visium options:_ 349 [-mtune=ARCH] 350 351 _Target Xtensa options:_ 352 [-[no-]text-section-literals] [-[no-]auto-litpools] 353 [-[no-]absolute-literals] 354 [-[no-]target-align] [-[no-]longcalls] 355 [-[no-]transform] 356 [-rename-section OLDNAME=NEWNAME] 357 [-[no-]trampolines] 358 359 _Target Z80 options:_ 360 [-z80]|[-z180]|[-r800]|[-ez80]|[-ez80-adl] 361 [-local-prefix=PREFIX] 362 [-colonless] 363 [-sdcc] 364 [-fp-s=FORMAT] 365 [-fp-d=FORMAT] 366 [-strict]|[-full] 367 [-with-inst=INST[,...]] [-Wnins INST[,...]] 368 [-without-inst=INST[,...]] [-Fins INST[,...]] 369 [ -ignore-undocumented-instructions] [-Wnud] 370 [ -ignore-unportable-instructions] [-Wnup] 371 [ -warn-undocumented-instructions] [-Wud] 372 [ -warn-unportable-instructions] [-Wup] 373 [ -forbid-undocumented-instructions] [-Fud] 374 [ -forbid-unportable-instructions] [-Fup] 375 376 377 378'@FILE' 379 Read command-line options from FILE. The options read are inserted 380 in place of the original @FILE option. If FILE does not exist, or 381 cannot be read, then the option will be treated literally, and not 382 removed. 383 384 Options in FILE are separated by whitespace. A whitespace 385 character may be included in an option by surrounding the entire 386 option in either single or double quotes. Any character (including 387 a backslash) may be included by prefixing the character to be 388 included with a backslash. The FILE may itself contain additional 389 @FILE options; any such options will be processed recursively. 390 391'-a[cdghlmns]' 392 Turn on listings, in any of a variety of ways: 393 394 '-ac' 395 omit false conditionals 396 397 '-ad' 398 omit debugging directives 399 400 '-ag' 401 include general information, like as version and options 402 passed 403 404 '-ah' 405 include high-level source 406 407 '-al' 408 include assembly 409 410 '-am' 411 include macro expansions 412 413 '-an' 414 omit forms processing 415 416 '-as' 417 include symbols 418 419 '=file' 420 set the name of the listing file 421 422 You may combine these options; for example, use '-aln' for assembly 423 listing without forms processing. The '=file' option, if used, 424 must be the last one. By itself, '-a' defaults to '-ahls'. 425 426'--alternate' 427 Begin in alternate macro mode. *Note '.altmacro': Altmacro. 428 429'--compress-debug-sections' 430 Compress DWARF debug sections using zlib with SHF_COMPRESSED from 431 the ELF ABI. The resulting object file may not be compatible with 432 older linkers and object file utilities. Note if compression would 433 make a given section _larger_ then it is not compressed. 434 435'--compress-debug-sections=none' 436'--compress-debug-sections=zlib' 437'--compress-debug-sections=zlib-gnu' 438'--compress-debug-sections=zlib-gabi' 439 These options control how DWARF debug sections are compressed. 440 '--compress-debug-sections=none' is equivalent to 441 '--nocompress-debug-sections'. '--compress-debug-sections=zlib' 442 and '--compress-debug-sections=zlib-gabi' are equivalent to 443 '--compress-debug-sections'. '--compress-debug-sections=zlib-gnu' 444 compresses DWARF debug sections using zlib. The debug sections are 445 renamed to begin with '.zdebug'. Note if compression would make a 446 given section _larger_ then it is not compressed nor renamed. 447 448'--nocompress-debug-sections' 449 Do not compress DWARF debug sections. This is usually the default 450 for all targets except the x86/x86_64, but a configure time option 451 can be used to override this. 452 453'-D' 454 Ignored. This option is accepted for script compatibility with 455 calls to other assemblers. 456 457'--debug-prefix-map OLD=NEW' 458 When assembling files in directory 'OLD', record debugging 459 information describing them as in 'NEW' instead. 460 461'--defsym SYM=VALUE' 462 Define the symbol SYM to be VALUE before assembling the input file. 463 VALUE must be an integer constant. As in C, a leading '0x' 464 indicates a hexadecimal value, and a leading '0' indicates an octal 465 value. The value of the symbol can be overridden inside a source 466 file via the use of a '.set' pseudo-op. 467 468'-f' 469 "fast"--skip whitespace and comment preprocessing (assume source is 470 compiler output). 471 472'-g' 473'--gen-debug' 474 Generate debugging information for each assembler source line using 475 whichever debug format is preferred by the target. This currently 476 means either STABS, ECOFF or DWARF2. 477 478'--gstabs' 479 Generate stabs debugging information for each assembler line. This 480 may help debugging assembler code, if the debugger can handle it. 481 482'--gstabs+' 483 Generate stabs debugging information for each assembler line, with 484 GNU extensions that probably only gdb can handle, and that could 485 make other debuggers crash or refuse to read your program. This 486 may help debugging assembler code. Currently the only GNU 487 extension is the location of the current working directory at 488 assembling time. 489 490'--gdwarf-2' 491 Generate DWARF2 debugging information for each assembler line. 492 This may help debugging assembler code, if the debugger can handle 493 it. Note--this option is only supported by some targets, not all 494 of them. 495 496'--gdwarf-sections' 497 Instead of creating a .debug_line section, create a series of 498 .debug_line.FOO sections where FOO is the name of the corresponding 499 code section. For example a code section called .TEXT.FUNC will 500 have its dwarf line number information placed into a section called 501 .DEBUG_LINE.TEXT.FUNC. If the code section is just called .TEXT 502 then debug line section will still be called just .DEBUG_LINE 503 without any suffix. 504 505'--gdwarf-cie-version=VERSION' 506 Control which version of DWARF Common Information Entries (CIEs) 507 are produced. When this flag is not specificed the default is 508 version 1, though some targets can modify this default. Other 509 possible values for VERSION are 3 or 4. 510 511'--size-check=error' 512'--size-check=warning' 513 Issue an error or warning for invalid ELF .size directive. 514 515'--elf-stt-common=no' 516'--elf-stt-common=yes' 517 These options control whether the ELF assembler should generate 518 common symbols with the 'STT_COMMON' type. The default can be 519 controlled by a configure option '--enable-elf-stt-common'. 520 521'--generate-missing-build-notes=yes' 522'--generate-missing-build-notes=no' 523 These options control whether the ELF assembler should generate GNU 524 Build attribute notes if none are present in the input sources. 525 The default can be controlled by the 526 '--enable-generate-build-notes' configure option. 527 528'--help' 529 Print a summary of the command-line options and exit. 530 531'--target-help' 532 Print a summary of all target specific options and exit. 533 534'-I DIR' 535 Add directory DIR to the search list for '.include' directives. 536 537'-J' 538 Don't warn about signed overflow. 539 540'-K' 541 Issue warnings when difference tables altered for long 542 displacements. 543 544'-L' 545'--keep-locals' 546 Keep (in the symbol table) local symbols. These symbols start with 547 system-specific local label prefixes, typically '.L' for ELF 548 systems or 'L' for traditional a.out systems. *Note Symbol 549 Names::. 550 551'--listing-lhs-width=NUMBER' 552 Set the maximum width, in words, of the output data column for an 553 assembler listing to NUMBER. 554 555'--listing-lhs-width2=NUMBER' 556 Set the maximum width, in words, of the output data column for 557 continuation lines in an assembler listing to NUMBER. 558 559'--listing-rhs-width=NUMBER' 560 Set the maximum width of an input source line, as displayed in a 561 listing, to NUMBER bytes. 562 563'--listing-cont-lines=NUMBER' 564 Set the maximum number of lines printed in a listing for a single 565 line of input to NUMBER + 1. 566 567'--no-pad-sections' 568 Stop the assembler for padding the ends of output sections to the 569 alignment of that section. The default is to pad the sections, but 570 this can waste space which might be needed on targets which have 571 tight memory constraints. 572 573'-o OBJFILE' 574 Name the object-file output from 'as' OBJFILE. 575 576'-R' 577 Fold the data section into the text section. 578 579'--hash-size=NUMBER' 580 Set the default size of GAS's hash tables to a prime number close 581 to NUMBER. Increasing this value can reduce the length of time it 582 takes the assembler to perform its tasks, at the expense of 583 increasing the assembler's memory requirements. Similarly reducing 584 this value can reduce the memory requirements at the expense of 585 speed. 586 587'--reduce-memory-overheads' 588 This option reduces GAS's memory requirements, at the expense of 589 making the assembly processes slower. Currently this switch is a 590 synonym for '--hash-size=4051', but in the future it may have other 591 effects as well. 592 593'--sectname-subst' 594 Honor substitution sequences in section names. *Note '.section 595 NAME': Section Name Substitutions. 596 597'--statistics' 598 Print the maximum space (in bytes) and total time (in seconds) used 599 by assembly. 600 601'--strip-local-absolute' 602 Remove local absolute symbols from the outgoing symbol table. 603 604'-v' 605'-version' 606 Print the 'as' version. 607 608'--version' 609 Print the 'as' version and exit. 610 611'-W' 612'--no-warn' 613 Suppress warning messages. 614 615'--fatal-warnings' 616 Treat warnings as errors. 617 618'--warn' 619 Don't suppress warning messages or treat them as errors. 620 621'-w' 622 Ignored. 623 624'-x' 625 Ignored. 626 627'-Z' 628 Generate an object file even after errors. 629 630'-- | FILES ...' 631 Standard input, or source files to assemble. 632 633 *Note AArch64 Options::, for the options available when as is 634configured for the 64-bit mode of the ARM Architecture (AArch64). 635 636 *Note Alpha Options::, for the options available when as is 637configured for an Alpha processor. 638 639 The following options are available when as is configured for an ARC 640processor. 641 642'-mcpu=CPU' 643 This option selects the core processor variant. 644'-EB | -EL' 645 Select either big-endian (-EB) or little-endian (-EL) output. 646'-mcode-density' 647 Enable Code Density extenssion instructions. 648 649 The following options are available when as is configured for the ARM 650processor family. 651 652'-mcpu=PROCESSOR[+EXTENSION...]' 653 Specify which ARM processor variant is the target. 654'-march=ARCHITECTURE[+EXTENSION...]' 655 Specify which ARM architecture variant is used by the target. 656'-mfpu=FLOATING-POINT-FORMAT' 657 Select which Floating Point architecture is the target. 658'-mfloat-abi=ABI' 659 Select which floating point ABI is in use. 660'-mthumb' 661 Enable Thumb only instruction decoding. 662'-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' 663 Select which procedure calling convention is in use. 664'-EB | -EL' 665 Select either big-endian (-EB) or little-endian (-EL) output. 666'-mthumb-interwork' 667 Specify that the code has been generated with interworking between 668 Thumb and ARM code in mind. 669'-mccs' 670 Turns on CodeComposer Studio assembly syntax compatibility mode. 671'-k' 672 Specify that PIC code has been generated. 673 674 *Note Blackfin Options::, for the options available when as is 675configured for the Blackfin processor family. 676 677 *Note BPF Options::, for the options available when as is configured 678for the Linux kernel BPF processor family. 679 680 See the info pages for documentation of the CRIS-specific options. 681 682 *Note C-SKY Options::, for the options available when as is 683configured for the C-SKY processor family. 684 685 The following options are available when as is configured for a D10V 686processor. 687'-O' 688 Optimize output by parallelizing instructions. 689 690 The following options are available when as is configured for a D30V 691processor. 692'-O' 693 Optimize output by parallelizing instructions. 694 695'-n' 696 Warn when nops are generated. 697 698'-N' 699 Warn when a nop after a 32-bit multiply instruction is generated. 700 701 The following options are available when as is configured for the 702Adapteva EPIPHANY series. 703 704 *Note Epiphany Options::, for the options available when as is 705configured for an Epiphany processor. 706 707 *Note i386-Options::, for the options available when as is configured 708for an i386 processor. 709 710 The following options are available when as is configured for the 711Ubicom IP2K series. 712 713'-mip2022ext' 714 Specifies that the extended IP2022 instructions are allowed. 715 716'-mip2022' 717 Restores the default behaviour, which restricts the permitted 718 instructions to just the basic IP2022 ones. 719 720 The following options are available when as is configured for the 721Renesas M32C and M16C processors. 722 723'-m32c' 724 Assemble M32C instructions. 725 726'-m16c' 727 Assemble M16C instructions (the default). 728 729'-relax' 730 Enable support for link-time relaxations. 731 732'-h-tick-hex' 733 Support H'00 style hex constants in addition to 0x00 style. 734 735 The following options are available when as is configured for the 736Renesas M32R (formerly Mitsubishi M32R) series. 737 738'--m32rx' 739 Specify which processor in the M32R family is the target. The 740 default is normally the M32R, but this option changes it to the 741 M32RX. 742 743'--warn-explicit-parallel-conflicts or --Wp' 744 Produce warning messages when questionable parallel constructs are 745 encountered. 746 747'--no-warn-explicit-parallel-conflicts or --Wnp' 748 Do not produce warning messages when questionable parallel 749 constructs are encountered. 750 751 The following options are available when as is configured for the 752Motorola 68000 series. 753 754'-l' 755 Shorten references to undefined symbols, to one word instead of 756 two. 757 758'-m68000 | -m68008 | -m68010 | -m68020 | -m68030' 759'| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' 760'| -m68333 | -m68340 | -mcpu32 | -m5200' 761 Specify what processor in the 68000 family is the target. The 762 default is normally the 68020, but this can be changed at 763 configuration time. 764 765'-m68881 | -m68882 | -mno-68881 | -mno-68882' 766 The target machine does (or does not) have a floating-point 767 coprocessor. The default is to assume a coprocessor for 68020, 768 68030, and cpu32. Although the basic 68000 is not compatible with 769 the 68881, a combination of the two can be specified, since it's 770 possible to do emulation of the coprocessor instructions with the 771 main processor. 772 773'-m68851 | -mno-68851' 774 The target machine does (or does not) have a memory-management unit 775 coprocessor. The default is to assume an MMU for 68020 and up. 776 777 *Note Nios II Options::, for the options available when as is 778configured for an Altera Nios II processor. 779 780 For details about the PDP-11 machine dependent features options, see 781*note PDP-11-Options::. 782 783'-mpic | -mno-pic' 784 Generate position-independent (or position-dependent) code. The 785 default is '-mpic'. 786 787'-mall' 788'-mall-extensions' 789 Enable all instruction set extensions. This is the default. 790 791'-mno-extensions' 792 Disable all instruction set extensions. 793 794'-mEXTENSION | -mno-EXTENSION' 795 Enable (or disable) a particular instruction set extension. 796 797'-mCPU' 798 Enable the instruction set extensions supported by a particular 799 CPU, and disable all other extensions. 800 801'-mMACHINE' 802 Enable the instruction set extensions supported by a particular 803 machine model, and disable all other extensions. 804 805 The following options are available when as is configured for a 806picoJava processor. 807 808'-mb' 809 Generate "big endian" format output. 810 811'-ml' 812 Generate "little endian" format output. 813 814 *Note PRU Options::, for the options available when as is configured 815for a PRU processor. 816 817 The following options are available when as is configured for the 818Motorola 68HC11 or 68HC12 series. 819 820'-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg' 821 Specify what processor is the target. The default is defined by 822 the configuration option when building the assembler. 823 824'--xgate-ramoffset' 825 Instruct the linker to offset RAM addresses from S12X address space 826 into XGATE address space. 827 828'-mshort' 829 Specify to use the 16-bit integer ABI. 830 831'-mlong' 832 Specify to use the 32-bit integer ABI. 833 834'-mshort-double' 835 Specify to use the 32-bit double ABI. 836 837'-mlong-double' 838 Specify to use the 64-bit double ABI. 839 840'--force-long-branches' 841 Relative branches are turned into absolute ones. This concerns 842 conditional branches, unconditional branches and branches to a sub 843 routine. 844 845'-S | --short-branches' 846 Do not turn relative branches into absolute ones when the offset is 847 out of range. 848 849'--strict-direct-mode' 850 Do not turn the direct addressing mode into extended addressing 851 mode when the instruction does not support direct addressing mode. 852 853'--print-insn-syntax' 854 Print the syntax of instruction in case of error. 855 856'--print-opcodes' 857 Print the list of instructions with syntax and then exit. 858 859'--generate-example' 860 Print an example of instruction for each possible instruction and 861 then exit. This option is only useful for testing 'as'. 862 863 The following options are available when 'as' is configured for the 864SPARC architecture: 865 866'-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 867'-Av8plus | -Av8plusa | -Av9 | -Av9a' 868 Explicitly select a variant of the SPARC architecture. 869 870 '-Av8plus' and '-Av8plusa' select a 32 bit environment. '-Av9' and 871 '-Av9a' select a 64 bit environment. 872 873 '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with 874 UltraSPARC extensions. 875 876'-xarch=v8plus | -xarch=v8plusa' 877 For compatibility with the Solaris v9 assembler. These options are 878 equivalent to -Av8plus and -Av8plusa, respectively. 879 880'-bump' 881 Warn when the assembler switches to another architecture. 882 883 The following options are available when as is configured for the 884'c54x architecture. 885 886'-mfar-mode' 887 Enable extended addressing mode. All addresses and relocations 888 will assume extended addressing (usually 23 bits). 889'-mcpu=CPU_VERSION' 890 Sets the CPU version being compiled for. 891'-merrors-to-file FILENAME' 892 Redirect error output to a file, for broken systems which don't 893 support such behaviour in the shell. 894 895 The following options are available when as is configured for a MIPS 896processor. 897 898'-G NUM' 899 This option sets the largest size of an object that can be 900 referenced implicitly with the 'gp' register. It is only accepted 901 for targets that use ECOFF format, such as a DECstation running 902 Ultrix. The default value is 8. 903 904'-EB' 905 Generate "big endian" format output. 906 907'-EL' 908 Generate "little endian" format output. 909 910'-mips1' 911'-mips2' 912'-mips3' 913'-mips4' 914'-mips5' 915'-mips32' 916'-mips32r2' 917'-mips32r3' 918'-mips32r5' 919'-mips32r6' 920'-mips64' 921'-mips64r2' 922'-mips64r3' 923'-mips64r5' 924'-mips64r6' 925 Generate code for a particular MIPS Instruction Set Architecture 926 level. '-mips1' is an alias for '-march=r3000', '-mips2' is an 927 alias for '-march=r6000', '-mips3' is an alias for '-march=r4000' 928 and '-mips4' is an alias for '-march=r8000'. '-mips5', '-mips32', 929 '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', '-mips64', 930 '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' correspond 931 to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, 932 MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, 933 MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA 934 processors, respectively. 935 936'-march=CPU' 937 Generate code for a particular MIPS CPU. 938 939'-mtune=CPU' 940 Schedule and tune for a particular MIPS CPU. 941 942'-mfix7000' 943'-mno-fix7000' 944 Cause nops to be inserted if the read of the destination register 945 of an mfhi or mflo instruction occurs in the following two 946 instructions. 947 948'-mfix-rm7000' 949'-mno-fix-rm7000' 950 Cause nops to be inserted if a dmult or dmultu instruction is 951 followed by a load instruction. 952 953'-mfix-r5900' 954'-mno-fix-r5900' 955 Do not attempt to schedule the preceding instruction into the delay 956 slot of a branch instruction placed at the end of a short loop of 957 six instructions or fewer and always schedule a 'nop' instruction 958 there instead. The short loop bug under certain conditions causes 959 loops to execute only once or twice, due to a hardware bug in the 960 R5900 chip. 961 962'-mdebug' 963'-no-mdebug' 964 Cause stabs-style debugging output to go into an ECOFF-style 965 .mdebug section instead of the standard ELF .stabs sections. 966 967'-mpdr' 968'-mno-pdr' 969 Control generation of '.pdr' sections. 970 971'-mgp32' 972'-mfp32' 973 The register sizes are normally inferred from the ISA and ABI, but 974 these flags force a certain group of registers to be treated as 32 975 bits wide at all times. '-mgp32' controls the size of 976 general-purpose registers and '-mfp32' controls the size of 977 floating-point registers. 978 979'-mgp64' 980'-mfp64' 981 The register sizes are normally inferred from the ISA and ABI, but 982 these flags force a certain group of registers to be treated as 64 983 bits wide at all times. '-mgp64' controls the size of 984 general-purpose registers and '-mfp64' controls the size of 985 floating-point registers. 986 987'-mfpxx' 988 The register sizes are normally inferred from the ISA and ABI, but 989 using this flag in combination with '-mabi=32' enables an ABI 990 variant which will operate correctly with floating-point registers 991 which are 32 or 64 bits wide. 992 993'-modd-spreg' 994'-mno-odd-spreg' 995 Enable use of floating-point operations on odd-numbered 996 single-precision registers when supported by the ISA. '-mfpxx' 997 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'. 998 999'-mips16' 1000'-no-mips16' 1001 Generate code for the MIPS 16 processor. This is equivalent to 1002 putting '.module mips16' at the start of the assembly file. 1003 '-no-mips16' turns off this option. 1004 1005'-mmips16e2' 1006'-mno-mips16e2' 1007 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is 1008 equivalent to putting '.module mips16e2' at the start of the 1009 assembly file. '-mno-mips16e2' turns off this option. 1010 1011'-mmicromips' 1012'-mno-micromips' 1013 Generate code for the microMIPS processor. This is equivalent to 1014 putting '.module micromips' at the start of the assembly file. 1015 '-mno-micromips' turns off this option. This is equivalent to 1016 putting '.module nomicromips' at the start of the assembly file. 1017 1018'-msmartmips' 1019'-mno-smartmips' 1020 Enables the SmartMIPS extension to the MIPS32 instruction set. 1021 This is equivalent to putting '.module smartmips' at the start of 1022 the assembly file. '-mno-smartmips' turns off this option. 1023 1024'-mips3d' 1025'-no-mips3d' 1026 Generate code for the MIPS-3D Application Specific Extension. This 1027 tells the assembler to accept MIPS-3D instructions. '-no-mips3d' 1028 turns off this option. 1029 1030'-mdmx' 1031'-no-mdmx' 1032 Generate code for the MDMX Application Specific Extension. This 1033 tells the assembler to accept MDMX instructions. '-no-mdmx' turns 1034 off this option. 1035 1036'-mdsp' 1037'-mno-dsp' 1038 Generate code for the DSP Release 1 Application Specific Extension. 1039 This tells the assembler to accept DSP Release 1 instructions. 1040 '-mno-dsp' turns off this option. 1041 1042'-mdspr2' 1043'-mno-dspr2' 1044 Generate code for the DSP Release 2 Application Specific Extension. 1045 This option implies '-mdsp'. This tells the assembler to accept 1046 DSP Release 2 instructions. '-mno-dspr2' turns off this option. 1047 1048'-mdspr3' 1049'-mno-dspr3' 1050 Generate code for the DSP Release 3 Application Specific Extension. 1051 This option implies '-mdsp' and '-mdspr2'. This tells the 1052 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns 1053 off this option. 1054 1055'-mmsa' 1056'-mno-msa' 1057 Generate code for the MIPS SIMD Architecture Extension. This tells 1058 the assembler to accept MSA instructions. '-mno-msa' turns off 1059 this option. 1060 1061'-mxpa' 1062'-mno-xpa' 1063 Generate code for the MIPS eXtended Physical Address (XPA) 1064 Extension. This tells the assembler to accept XPA instructions. 1065 '-mno-xpa' turns off this option. 1066 1067'-mmt' 1068'-mno-mt' 1069 Generate code for the MT Application Specific Extension. This 1070 tells the assembler to accept MT instructions. '-mno-mt' turns off 1071 this option. 1072 1073'-mmcu' 1074'-mno-mcu' 1075 Generate code for the MCU Application Specific Extension. This 1076 tells the assembler to accept MCU instructions. '-mno-mcu' turns 1077 off this option. 1078 1079'-mcrc' 1080'-mno-crc' 1081 Generate code for the MIPS cyclic redundancy check (CRC) 1082 Application Specific Extension. This tells the assembler to accept 1083 CRC instructions. '-mno-crc' turns off this option. 1084 1085'-mginv' 1086'-mno-ginv' 1087 Generate code for the Global INValidate (GINV) Application Specific 1088 Extension. This tells the assembler to accept GINV instructions. 1089 '-mno-ginv' turns off this option. 1090 1091'-mloongson-mmi' 1092'-mno-loongson-mmi' 1093 Generate code for the Loongson MultiMedia extensions Instructions 1094 (MMI) Application Specific Extension. This tells the assembler to 1095 accept MMI instructions. '-mno-loongson-mmi' turns off this 1096 option. 1097 1098'-mloongson-cam' 1099'-mno-loongson-cam' 1100 Generate code for the Loongson Content Address Memory (CAM) 1101 instructions. This tells the assembler to accept Loongson CAM 1102 instructions. '-mno-loongson-cam' turns off this option. 1103 1104'-mloongson-ext' 1105'-mno-loongson-ext' 1106 Generate code for the Loongson EXTensions (EXT) instructions. This 1107 tells the assembler to accept Loongson EXT instructions. 1108 '-mno-loongson-ext' turns off this option. 1109 1110'-mloongson-ext2' 1111'-mno-loongson-ext2' 1112 Generate code for the Loongson EXTensions R2 (EXT2) instructions. 1113 This option implies '-mloongson-ext'. This tells the assembler to 1114 accept Loongson EXT2 instructions. '-mno-loongson-ext2' turns off 1115 this option. 1116 1117'-minsn32' 1118'-mno-insn32' 1119 Only use 32-bit instruction encodings when generating code for the 1120 microMIPS processor. This option inhibits the use of any 16-bit 1121 instructions. This is equivalent to putting '.set insn32' at the 1122 start of the assembly file. '-mno-insn32' turns off this option. 1123 This is equivalent to putting '.set noinsn32' at the start of the 1124 assembly file. By default '-mno-insn32' is selected, allowing all 1125 instructions to be used. 1126 1127'--construct-floats' 1128'--no-construct-floats' 1129 The '--no-construct-floats' option disables the construction of 1130 double width floating point constants by loading the two halves of 1131 the value into the two single width floating point registers that 1132 make up the double width register. By default '--construct-floats' 1133 is selected, allowing construction of these floating point 1134 constants. 1135 1136'--relax-branch' 1137'--no-relax-branch' 1138 The '--relax-branch' option enables the relaxation of out-of-range 1139 branches. By default '--no-relax-branch' is selected, causing any 1140 out-of-range branches to produce an error. 1141 1142'-mignore-branch-isa' 1143'-mno-ignore-branch-isa' 1144 Ignore branch checks for invalid transitions between ISA modes. 1145 The semantics of branches does not provide for an ISA mode switch, 1146 so in most cases the ISA mode a branch has been encoded for has to 1147 be the same as the ISA mode of the branch's target label. 1148 Therefore GAS has checks implemented that verify in branch assembly 1149 that the two ISA modes match. '-mignore-branch-isa' disables these 1150 checks. By default '-mno-ignore-branch-isa' is selected, causing 1151 any invalid branch requiring a transition between ISA modes to 1152 produce an error. 1153 1154'-mnan=ENCODING' 1155 Select between the IEEE 754-2008 ('-mnan=2008') or the legacy 1156 ('-mnan=legacy') NaN encoding format. The latter is the default. 1157 1158'--emulation=NAME' 1159 This option was formerly used to switch between ELF and ECOFF 1160 output on targets like IRIX 5 that supported both. MIPS ECOFF 1161 support was removed in GAS 2.24, so the option now serves little 1162 purpose. It is retained for backwards compatibility. 1163 1164 The available configuration names are: 'mipself', 'mipslelf' and 1165 'mipsbelf'. Choosing 'mipself' now has no effect, since the output 1166 is always ELF. 'mipslelf' and 'mipsbelf' select little- and 1167 big-endian output respectively, but '-EL' and '-EB' are now the 1168 preferred options instead. 1169 1170'-nocpp' 1171 'as' ignores this option. It is accepted for compatibility with 1172 the native tools. 1173 1174'--trap' 1175'--no-trap' 1176'--break' 1177'--no-break' 1178 Control how to deal with multiplication overflow and division by 1179 zero. '--trap' or '--no-break' (which are synonyms) take a trap 1180 exception (and only work for Instruction Set Architecture level 2 1181 and higher); '--break' or '--no-trap' (also synonyms, and the 1182 default) take a break exception. 1183 1184'-n' 1185 When this option is used, 'as' will issue a warning every time it 1186 generates a nop instruction from a macro. 1187 1188 The following options are available when as is configured for an 1189MCore processor. 1190 1191'-jsri2bsr' 1192'-nojsri2bsr' 1193 Enable or disable the JSRI to BSR transformation. By default this 1194 is enabled. The command-line option '-nojsri2bsr' can be used to 1195 disable it. 1196 1197'-sifilter' 1198'-nosifilter' 1199 Enable or disable the silicon filter behaviour. By default this is 1200 disabled. The default can be overridden by the '-sifilter' 1201 command-line option. 1202 1203'-relax' 1204 Alter jump instructions for long displacements. 1205 1206'-mcpu=[210|340]' 1207 Select the cpu type on the target hardware. This controls which 1208 instructions can be assembled. 1209 1210'-EB' 1211 Assemble for a big endian target. 1212 1213'-EL' 1214 Assemble for a little endian target. 1215 1216 *Note Meta Options::, for the options available when as is configured 1217for a Meta processor. 1218 1219 See the info pages for documentation of the MMIX-specific options. 1220 1221 *Note NDS32 Options::, for the options available when as is 1222configured for a NDS32 processor. 1223 1224 *Note PowerPC-Opts::, for the options available when as is configured 1225for a PowerPC processor. 1226 1227 *Note RISC-V-Options::, for the options available when as is 1228configured for a RISC-V processor. 1229 1230 See the info pages for documentation of the RX-specific options. 1231 1232 The following options are available when as is configured for the 1233s390 processor family. 1234 1235'-m31' 1236'-m64' 1237 Select the word size, either 31/32 bits or 64 bits. 1238'-mesa' 1239'-mzarch' 1240 Select the architecture mode, either the Enterprise System 1241 Architecture (esa) or the z/Architecture mode (zarch). 1242'-march=PROCESSOR' 1243 Specify which s390 processor variant is the target, 'g5' (or 1244 'arch3'), 'g6', 'z900' (or 'arch5'), 'z990' (or 'arch6'), 'z9-109', 1245 'z9-ec' (or 'arch7'), 'z10' (or 'arch8'), 'z196' (or 'arch9'), 1246 'zEC12' (or 'arch10'), 'z13' (or 'arch11'), 'z14' (or 'arch12'), or 1247 'z15' (or 'arch13'). 1248'-mregnames' 1249'-mno-regnames' 1250 Allow or disallow symbolic names for registers. 1251'-mwarn-areg-zero' 1252 Warn whenever the operand for a base or index register has been 1253 specified but evaluates to zero. 1254 1255 *Note TIC6X Options::, for the options available when as is 1256configured for a TMS320C6000 processor. 1257 1258 *Note TILE-Gx Options::, for the options available when as is 1259configured for a TILE-Gx processor. 1260 1261 *Note Visium Options::, for the options available when as is 1262configured for a Visium processor. 1263 1264 *Note Xtensa Options::, for the options available when as is 1265configured for an Xtensa processor. 1266 1267 *Note Z80 Options::, for the options available when as is configured 1268for an Z80 processor. 1269 1270* Menu: 1271 1272* Manual:: Structure of this Manual 1273* GNU Assembler:: The GNU Assembler 1274* Object Formats:: Object File Formats 1275* Command Line:: Command Line 1276* Input Files:: Input Files 1277* Object:: Output (Object) File 1278* Errors:: Error and Warning Messages 1279 1280 1281File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1282 12831.1 Structure of this Manual 1284============================ 1285 1286This manual is intended to describe what you need to know to use GNU 1287'as'. We cover the syntax expected in source files, including notation 1288for symbols, constants, and expressions; the directives that 'as' 1289understands; and of course how to invoke 'as'. 1290 1291 This manual also describes some of the machine-dependent features of 1292various flavors of the assembler. 1293 1294 On the other hand, this manual is _not_ intended as an introduction 1295to programming in assembly language--let alone programming in general! 1296In a similar vein, we make no attempt to introduce the machine 1297architecture; we do _not_ describe the instruction set, standard 1298mnemonics, registers or addressing modes that are standard to a 1299particular architecture. You may want to consult the manufacturer's 1300machine architecture manual for this information. 1301 1302 1303File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1304 13051.2 The GNU Assembler 1306===================== 1307 1308GNU 'as' is really a family of assemblers. If you use (or have used) 1309the GNU assembler on one architecture, you should find a fairly similar 1310environment when you use it on another architecture. Each version has 1311much in common with the others, including object file formats, most 1312assembler directives (often called "pseudo-ops") and assembler syntax. 1313 1314 'as' is primarily intended to assemble the output of the GNU C 1315compiler 'gcc' for use by the linker 'ld'. Nevertheless, we've tried to 1316make 'as' assemble correctly everything that other assemblers for the 1317same machine would assemble. Any exceptions are documented explicitly 1318(*note Machine Dependencies::). This doesn't mean 'as' always uses the 1319same syntax as another assembler for the same architecture; for example, 1320we know of several incompatible versions of 680x0 assembly language 1321syntax. 1322 1323 Unlike older assemblers, 'as' is designed to assemble a source 1324program in one pass of the source file. This has a subtle impact on the 1325'.org' directive (*note '.org': Org.). 1326 1327 1328File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1329 13301.3 Object File Formats 1331======================= 1332 1333The GNU assembler can be configured to produce several alternative 1334object file formats. For the most part, this does not affect how you 1335write assembly language programs; but directives for debugging symbols 1336are typically different in different file formats. *Note Symbol 1337Attributes: Symbol Attributes. 1338 1339 1340File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1341 13421.4 Command Line 1343================ 1344 1345After the program name 'as', the command line may contain options and 1346file names. Options may appear in any order, and may be before, after, 1347or between file names. The order of file names is significant. 1348 1349 '--' (two hyphens) by itself names the standard input file 1350explicitly, as one of the files for 'as' to assemble. 1351 1352 Except for '--' any command-line argument that begins with a hyphen 1353('-') is an option. Each option changes the behavior of 'as'. No 1354option changes the way another option works. An option is a '-' 1355followed by one or more letters; the case of the letter is important. 1356All options are optional. 1357 1358 Some options expect exactly one file name to follow them. The file 1359name may either immediately follow the option's letter (compatible with 1360older assemblers) or it may be the next command argument (GNU standard). 1361These two command lines are equivalent: 1362 1363 as -o my-object-file.o mumble.s 1364 as -omy-object-file.o mumble.s 1365 1366 1367File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1368 13691.5 Input Files 1370=============== 1371 1372We use the phrase "source program", abbreviated "source", to describe 1373the program input to one run of 'as'. The program may be in one or more 1374files; how the source is partitioned into files doesn't change the 1375meaning of the source. 1376 1377 The source program is a concatenation of the text in all the files, 1378in the order specified. 1379 1380 Each time you run 'as' it assembles exactly one source program. The 1381source program is made up of one or more files. (The standard input is 1382also a file.) 1383 1384 You give 'as' a command line that has zero or more input file names. 1385The input files are read (from left file name to right). A command-line 1386argument (in any position) that has no special meaning is taken to be an 1387input file name. 1388 1389 If you give 'as' no file names it attempts to read one input file 1390from the 'as' standard input, which is normally your terminal. You may 1391have to type <ctl-D> to tell 'as' there is no more program to assemble. 1392 1393 Use '--' if you need to explicitly name the standard input file in 1394your command line. 1395 1396 If the source is empty, 'as' produces a small, empty object file. 1397 1398Filenames and Line-numbers 1399-------------------------- 1400 1401There are two ways of locating a line in the input file (or files) and 1402either may be used in reporting error messages. One way refers to a 1403line number in a physical file; the other refers to a line number in a 1404"logical" file. *Note Error and Warning Messages: Errors. 1405 1406 "Physical files" are those files named in the command line given to 1407'as'. 1408 1409 "Logical files" are simply names declared explicitly by assembler 1410directives; they bear no relation to physical files. Logical file names 1411help error messages reflect the original source file, when 'as' source 1412is itself synthesized from other files. 'as' understands the '#' 1413directives emitted by the 'gcc' preprocessor. See also *note '.file': 1414File. 1415 1416 1417File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1418 14191.6 Output (Object) File 1420======================== 1421 1422Every time you run 'as' it produces an output file, which is your 1423assembly language program translated into numbers. This file is the 1424object file. Its default name is 'a.out'. You can give it another name 1425by using the '-o' option. Conventionally, object file names end with 1426'.o'. The default name is used for historical reasons: older assemblers 1427were capable of assembling self-contained programs directly into a 1428runnable program. (For some formats, this isn't currently possible, but 1429it can be done for the 'a.out' format.) 1430 1431 The object file is meant for input to the linker 'ld'. It contains 1432assembled program code, information to help 'ld' integrate the assembled 1433program into a runnable file, and (optionally) symbolic information for 1434the debugger. 1435 1436 1437File: as.info, Node: Errors, Prev: Object, Up: Overview 1438 14391.7 Error and Warning Messages 1440============================== 1441 1442'as' may write warnings and error messages to the standard error file 1443(usually your terminal). This should not happen when a compiler runs 1444'as' automatically. Warnings report an assumption made so that 'as' 1445could keep assembling a flawed program; errors report a grave problem 1446that stops the assembly. 1447 1448 Warning messages have the format 1449 1450 file_name:NNN:Warning Message Text 1451 1452(where NNN is a line number). If both a logical file name (*note 1453'.file': File.) and a logical line number (*note '.line': Line.) have 1454been given then they will be used, otherwise the file name and line 1455number in the current assembler source file will be used. The message 1456text is intended to be self explanatory (in the grand Unix tradition). 1457 1458 Note the file name must be set via the logical version of the '.file' 1459directive, not the DWARF2 version of the '.file' directive. For 1460example: 1461 1462 .file 2 "bar.c" 1463 error_assembler_source 1464 .file "foo.c" 1465 .line 30 1466 error_c_source 1467 1468 produces this output: 1469 1470 Assembler messages: 1471 asm.s:2: Error: no such instruction: `error_assembler_source' 1472 foo.c:31: Error: no such instruction: `error_c_source' 1473 1474 Error messages have the format 1475 1476 file_name:NNN:FATAL:Error Message Text 1477 1478 The file name and line number are derived as for warning messages. 1479The actual message text may be rather less explanatory because many of 1480them aren't supposed to happen. 1481 1482 1483File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1484 14852 Command-Line Options 1486********************** 1487 1488This chapter describes command-line options available in _all_ versions 1489of the GNU assembler; see *note Machine Dependencies::, for options 1490specific to particular machine architectures. 1491 1492 If you are invoking 'as' via the GNU C compiler, you can use the 1493'-Wa' option to pass arguments through to the assembler. The assembler 1494arguments must be separated from each other (and the '-Wa') by commas. 1495For example: 1496 1497 gcc -c -g -O -Wa,-alh,-L file.c 1498 1499This passes two options to the assembler: '-alh' (emit a listing to 1500standard output with high-level and assembly source) and '-L' (retain 1501local symbols in the symbol table). 1502 1503 Usually you do not need to use this '-Wa' mechanism, since many 1504compiler command-line options are automatically passed to the assembler 1505by the compiler. (You can call the GNU compiler driver with the '-v' 1506option to see precisely what options it passes to each compilation pass, 1507including the assembler.) 1508 1509* Menu: 1510 1511* a:: -a[cdghlns] enable listings 1512* alternate:: -alternate enable alternate macro syntax 1513* D:: -D for compatibility 1514* f:: -f to work faster 1515* I:: -I for .include search path 1516* K:: -K for difference tables 1517 1518* L:: -L to retain local symbols 1519* listing:: -listing-XXX to configure listing output 1520* M:: -M or -mri to assemble in MRI compatibility mode 1521* MD:: -MD for dependency tracking 1522* no-pad-sections:: -no-pad-sections to stop section padding 1523* o:: -o to name the object file 1524* R:: -R to join data and text sections 1525* statistics:: -statistics to see statistics about assembly 1526* traditional-format:: -traditional-format for compatible output 1527* v:: -v to announce version 1528* W:: -W, -no-warn, -warn, -fatal-warnings to control warnings 1529* Z:: -Z to make object file even after errors 1530 1531 1532File: as.info, Node: a, Next: alternate, Up: Invoking 1533 15342.1 Enable Listings: '-a[cdghlns]' 1535================================== 1536 1537These options enable listing output from the assembler. By itself, '-a' 1538requests high-level, assembly, and symbols listing. You can use other 1539letters to select specific options for the list: '-ah' requests a 1540high-level language listing, '-al' requests an output-program assembly 1541listing, and '-as' requests a symbol table listing. High-level listings 1542require that a compiler debugging option like '-g' be used, and that 1543assembly listings ('-al') be requested also. 1544 1545 Use the '-ag' option to print a first section with general assembly 1546information, like as version, switches passed, or time stamp. 1547 1548 Use the '-ac' option to omit false conditionals from a listing. Any 1549lines which are not assembled because of a false '.if' (or '.ifdef', or 1550any other conditional), or a true '.if' followed by an '.else', will be 1551omitted from the listing. 1552 1553 Use the '-ad' option to omit debugging directives from the listing. 1554 1555 Once you have specified one of these options, you can further control 1556listing output and its appearance using the directives '.list', 1557'.nolist', '.psize', '.eject', '.title', and '.sbttl'. The '-an' option 1558turns off all forms processing. If you do not request listing output 1559with one of the '-a' options, the listing-control directives have no 1560effect. 1561 1562 The letters after '-a' may be combined into one option, _e.g._, 1563'-aln'. 1564 1565 Note if the assembler source is coming from the standard input (e.g., 1566because it is being created by 'gcc' and the '-pipe' command-line switch 1567is being used) then the listing will not contain any comments or 1568preprocessor directives. This is because the listing code buffers input 1569source lines from stdin only after they have been preprocessed by the 1570assembler. This reduces memory usage and makes the code more efficient. 1571 1572 1573File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1574 15752.2 '--alternate' 1576================= 1577 1578Begin in alternate macro mode, see *note '.altmacro': Altmacro. 1579 1580 1581File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1582 15832.3 '-D' 1584======== 1585 1586This option has no effect whatsoever, but it is accepted to make it more 1587likely that scripts written for other assemblers also work with 'as'. 1588 1589 1590File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1591 15922.4 Work Faster: '-f' 1593===================== 1594 1595'-f' should only be used when assembling programs written by a (trusted) 1596compiler. '-f' stops the assembler from doing whitespace and comment 1597preprocessing on the input file(s) before assembling them. *Note 1598Preprocessing: Preprocessing. 1599 1600 _Warning:_ if you use '-f' when the files actually need to be 1601 preprocessed (if they contain comments, for example), 'as' does not 1602 work correctly. 1603 1604 1605File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1606 16072.5 '.include' Search Path: '-I' PATH 1608===================================== 1609 1610Use this option to add a PATH to the list of directories 'as' searches 1611for files specified in '.include' directives (*note '.include': 1612Include.). You may use '-I' as many times as necessary to include a 1613variety of paths. The current working directory is always searched 1614first; after that, 'as' searches any '-I' directories in the same order 1615as they were specified (left to right) on the command line. 1616 1617 1618File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1619 16202.6 Difference Tables: '-K' 1621=========================== 1622 1623'as' sometimes alters the code emitted for directives of the form '.word 1624SYM1-SYM2'. *Note '.word': Word. You can use the '-K' option if you 1625want a warning issued when this is done. 1626 1627 1628File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1629 16302.7 Include Local Symbols: '-L' 1631=============================== 1632 1633Symbols beginning with system-specific local label prefixes, typically 1634'.L' for ELF systems or 'L' for traditional a.out systems, are called 1635"local symbols". *Note Symbol Names::. Normally you do not see such 1636symbols when debugging, because they are intended for the use of 1637programs (like compilers) that compose assembler programs, not for your 1638notice. Normally both 'as' and 'ld' discard such symbols, so you do not 1639normally debug with them. 1640 1641 This option tells 'as' to retain those local symbols in the object 1642file. Usually if you do this you also tell the linker 'ld' to preserve 1643those symbols. 1644 1645 1646File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1647 16482.8 Configuring listing output: '--listing' 1649=========================================== 1650 1651The listing feature of the assembler can be enabled via the command-line 1652switch '-a' (*note a::). This feature combines the input source file(s) 1653with a hex dump of the corresponding locations in the output object 1654file, and displays them as a listing file. The format of this listing 1655can be controlled by directives inside the assembler source (i.e., 1656'.list' (*note List::), '.title' (*note Title::), '.sbttl' (*note 1657Sbttl::), '.psize' (*note Psize::), and '.eject' (*note Eject::) and 1658also by the following switches: 1659 1660'--listing-lhs-width='number'' 1661 Sets the maximum width, in words, of the first line of the hex byte 1662 dump. This dump appears on the left hand side of the listing 1663 output. 1664 1665'--listing-lhs-width2='number'' 1666 Sets the maximum width, in words, of any further lines of the hex 1667 byte dump for a given input source line. If this value is not 1668 specified, it defaults to being the same as the value specified for 1669 '--listing-lhs-width'. If neither switch is used the default is to 1670 one. 1671 1672'--listing-rhs-width='number'' 1673 Sets the maximum width, in characters, of the source line that is 1674 displayed alongside the hex dump. The default value for this 1675 parameter is 100. The source line is displayed on the right hand 1676 side of the listing output. 1677 1678'--listing-cont-lines='number'' 1679 Sets the maximum number of continuation lines of hex dump that will 1680 be displayed for a given single line of source input. The default 1681 value is 4. 1682 1683 1684File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1685 16862.9 Assemble in MRI Compatibility Mode: '-M' 1687============================================ 1688 1689The '-M' or '--mri' option selects MRI compatibility mode. This changes 1690the syntax and pseudo-op handling of 'as' to make it compatible with the 1691'ASM68K' assembler from Microtec Research. The exact nature of the MRI 1692syntax will not be documented here; see the MRI manuals for more 1693information. Note in particular that the handling of macros and macro 1694arguments is somewhat different. The purpose of this option is to 1695permit assembling existing MRI assembler code using 'as'. 1696 1697 The MRI compatibility is not complete. Certain operations of the MRI 1698assembler depend upon its object file format, and can not be supported 1699using other object file formats. Supporting these would require 1700enhancing each object file format individually. These are: 1701 1702 * global symbols in common section 1703 1704 The m68k MRI assembler supports common sections which are merged by 1705 the linker. Other object file formats do not support this. 'as' 1706 handles common sections by treating them as a single common symbol. 1707 It permits local symbols to be defined within a common section, but 1708 it can not support global symbols, since it has no way to describe 1709 them. 1710 1711 * complex relocations 1712 1713 The MRI assemblers support relocations against a negated section 1714 address, and relocations which combine the start addresses of two 1715 or more sections. These are not support by other object file 1716 formats. 1717 1718 * 'END' pseudo-op specifying start address 1719 1720 The MRI 'END' pseudo-op permits the specification of a start 1721 address. This is not supported by other object file formats. The 1722 start address may instead be specified using the '-e' option to the 1723 linker, or in a linker script. 1724 1725 * 'IDNT', '.ident' and 'NAME' pseudo-ops 1726 1727 The MRI 'IDNT', '.ident' and 'NAME' pseudo-ops assign a module name 1728 to the output file. This is not supported by other object file 1729 formats. 1730 1731 * 'ORG' pseudo-op 1732 1733 The m68k MRI 'ORG' pseudo-op begins an absolute section at a given 1734 address. This differs from the usual 'as' '.org' pseudo-op, which 1735 changes the location within the current section. Absolute sections 1736 are not supported by other object file formats. The address of a 1737 section may be assigned within a linker script. 1738 1739 There are some other features of the MRI assembler which are not 1740supported by 'as', typically either because they are difficult or 1741because they seem of little consequence. Some of these may be supported 1742in future releases. 1743 1744 * EBCDIC strings 1745 1746 EBCDIC strings are not supported. 1747 1748 * packed binary coded decimal 1749 1750 Packed binary coded decimal is not supported. This means that the 1751 'DC.P' and 'DCB.P' pseudo-ops are not supported. 1752 1753 * 'FEQU' pseudo-op 1754 1755 The m68k 'FEQU' pseudo-op is not supported. 1756 1757 * 'NOOBJ' pseudo-op 1758 1759 The m68k 'NOOBJ' pseudo-op is not supported. 1760 1761 * 'OPT' branch control options 1762 1763 The m68k 'OPT' branch control options--'B', 'BRS', 'BRB', 'BRL', 1764 and 'BRW'--are ignored. 'as' automatically relaxes all branches, 1765 whether forward or backward, to an appropriate size, so these 1766 options serve no purpose. 1767 1768 * 'OPT' list control options 1769 1770 The following m68k 'OPT' list control options are ignored: 'C', 1771 'CEX', 'CL', 'CRE', 'E', 'G', 'I', 'M', 'MEX', 'MC', 'MD', 'X'. 1772 1773 * other 'OPT' options 1774 1775 The following m68k 'OPT' options are ignored: 'NEST', 'O', 'OLD', 1776 'OP', 'P', 'PCO', 'PCR', 'PCS', 'R'. 1777 1778 * 'OPT' 'D' option is default 1779 1780 The m68k 'OPT' 'D' option is the default, unlike the MRI assembler. 1781 'OPT NOD' may be used to turn it off. 1782 1783 * 'XREF' pseudo-op. 1784 1785 The m68k 'XREF' pseudo-op is ignored. 1786 1787 1788File: as.info, Node: MD, Next: no-pad-sections, Prev: M, Up: Invoking 1789 17902.10 Dependency Tracking: '--MD' 1791================================ 1792 1793'as' can generate a dependency file for the file it creates. This file 1794consists of a single rule suitable for 'make' describing the 1795dependencies of the main source file. 1796 1797 The rule is written to the file named in its argument. 1798 1799 This feature is used in the automatic updating of makefiles. 1800 1801 1802File: as.info, Node: no-pad-sections, Next: o, Prev: MD, Up: Invoking 1803 18042.11 Output Section Padding 1805=========================== 1806 1807Normally the assembler will pad the end of each output section up to its 1808alignment boundary. But this can waste space, which can be significant 1809on memory constrained targets. So the '--no-pad-sections' option will 1810disable this behaviour. 1811 1812 1813File: as.info, Node: o, Next: R, Prev: no-pad-sections, Up: Invoking 1814 18152.12 Name the Object File: '-o' 1816=============================== 1817 1818There is always one object file output when you run 'as'. By default it 1819has the name 'a.out'. You use this option (which takes exactly one 1820filename) to give the object file a different name. 1821 1822 Whatever the object file is called, 'as' overwrites any existing file 1823of the same name. 1824 1825 1826File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1827 18282.13 Join Data and Text Sections: '-R' 1829====================================== 1830 1831'-R' tells 'as' to write the object file as if all data-section data 1832lives in the text section. This is only done at the very last moment: 1833your binary data are the same, but data section parts are relocated 1834differently. The data section part of your object file is zero bytes 1835long because all its bytes are appended to the text section. (*Note 1836Sections and Relocation: Sections.) 1837 1838 When you specify '-R' it would be possible to generate shorter 1839address displacements (because we do not have to cross between text and 1840data section). We refrain from doing this simply for compatibility with 1841older versions of 'as'. In future, '-R' may work this way. 1842 1843 When 'as' is configured for COFF or ELF output, this option is only 1844useful if you use sections named '.text' and '.data'. 1845 1846 '-R' is not supported for any of the HPPA targets. Using '-R' 1847generates a warning from 'as'. 1848 1849 1850File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1851 18522.14 Display Assembly Statistics: '--statistics' 1853================================================ 1854 1855Use '--statistics' to display two statistics about the resources used by 1856'as': the maximum amount of space allocated during the assembly (in 1857bytes), and the total execution time taken for the assembly (in CPU 1858seconds). 1859 1860 1861File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1862 18632.15 Compatible Output: '--traditional-format' 1864============================================== 1865 1866For some targets, the output of 'as' is different in some ways from the 1867output of some existing assembler. This switch requests 'as' to use the 1868traditional format instead. 1869 1870 For example, it disables the exception frame optimizations which 'as' 1871normally does by default on 'gcc' output. 1872 1873 1874File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1875 18762.16 Announce Version: '-v' 1877=========================== 1878 1879You can find out what version of as is running by including the option 1880'-v' (which you can also spell as '-version') on the command line. 1881 1882 1883File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1884 18852.17 Control Warnings: '-W', '--warn', '--no-warn', '--fatal-warnings' 1886====================================================================== 1887 1888'as' should never give a warning or error message when assembling 1889compiler output. But programs written by people often cause 'as' to 1890give a warning that a particular assumption was made. All such warnings 1891are directed to the standard error file. 1892 1893 If you use the '-W' and '--no-warn' options, no warnings are issued. 1894This only affects the warning messages: it does not change any 1895particular of how 'as' assembles your file. Errors, which stop the 1896assembly, are still reported. 1897 1898 If you use the '--fatal-warnings' option, 'as' considers files that 1899generate warnings to be in error. 1900 1901 You can switch these options off again by specifying '--warn', which 1902causes warnings to be output as usual. 1903 1904 1905File: as.info, Node: Z, Prev: W, Up: Invoking 1906 19072.18 Generate Object File in Spite of Errors: '-Z' 1908================================================== 1909 1910After an error message, 'as' normally produces no output. If for some 1911reason you are interested in object file output even after 'as' gives an 1912error message on your program, use the '-Z' option. If there are any 1913errors, 'as' continues anyways, and writes an object file after a final 1914warning message of the form 'N errors, M warnings, generating bad object 1915file.' 1916 1917 1918File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1919 19203 Syntax 1921******** 1922 1923This chapter describes the machine-independent syntax allowed in a 1924source file. 'as' syntax is similar to what many other assemblers use; 1925it is inspired by the BSD 4.2 assembler, except that 'as' does not 1926assemble Vax bit-fields. 1927 1928* Menu: 1929 1930* Preprocessing:: Preprocessing 1931* Whitespace:: Whitespace 1932* Comments:: Comments 1933* Symbol Intro:: Symbols 1934* Statements:: Statements 1935* Constants:: Constants 1936 1937 1938File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 1939 19403.1 Preprocessing 1941================= 1942 1943The 'as' internal preprocessor: 1944 * adjusts and removes extra whitespace. It leaves one space or tab 1945 before the keywords on a line, and turns any other whitespace on 1946 the line into a single space. 1947 1948 * removes all comments, replacing them with a single space, or an 1949 appropriate number of newlines. 1950 1951 * converts character constants into the appropriate numeric values. 1952 1953 It does not do macro processing, include file handling, or anything 1954else you may get from your C compiler's preprocessor. You can do 1955include file processing with the '.include' directive (*note '.include': 1956Include.). You can use the GNU C compiler driver to get other "CPP" 1957style preprocessing by giving the input file a '.S' suffix. *Note 1958Options Controlling the Kind of Output: (gcc info)Overall Options. 1959 1960 Excess whitespace, comments, and character constants cannot be used 1961in the portions of the input text that are not preprocessed. 1962 1963 If the first line of an input file is '#NO_APP' or if you use the 1964'-f' option, whitespace and comments are not removed from the input 1965file. Within an input file, you can ask for whitespace and comment 1966removal in specific portions of the by putting a line that says '#APP' 1967before the text that may contain whitespace or comments, and putting a 1968line that says '#NO_APP' after this text. This feature is mainly intend 1969to support 'asm' statements in compilers whose output is otherwise free 1970of comments and whitespace. 1971 1972 1973File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 1974 19753.2 Whitespace 1976============== 1977 1978"Whitespace" is one or more blanks or tabs, in any order. Whitespace is 1979used to separate symbols, and to make programs neater for people to 1980read. Unless within character constants (*note Character Constants: 1981Characters.), any whitespace means the same as exactly one space. 1982 1983 1984File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 1985 19863.3 Comments 1987============ 1988 1989There are two ways of rendering comments to 'as'. In both cases the 1990comment is equivalent to one space. 1991 1992 Anything from '/*' through the next '*/' is a comment. This means 1993you may not nest these comments. 1994 1995 /* 1996 The only way to include a newline ('\n') in a comment 1997 is to use this sort of comment. 1998 */ 1999 2000 /* This sort of comment does not nest. */ 2001 2002 Anything from a "line comment" character up to the next newline is 2003considered a comment and is ignored. The line comment character is 2004target specific, and some targets multiple comment characters. Some 2005targets also have line comment characters that only work if they are the 2006first character on a line. Some targets use a sequence of two 2007characters to introduce a line comment. Some targets can also change 2008their line comment characters depending upon command-line options that 2009have been used. For more details see the _Syntax_ section in the 2010documentation for individual targets. 2011 2012 If the line comment character is the hash sign ('#') then it still 2013has the special ability to enable and disable preprocessing (*note 2014Preprocessing::) and to specify logical line numbers: 2015 2016 To be compatible with past assemblers, lines that begin with '#' have 2017a special interpretation. Following the '#' should be an absolute 2018expression (*note Expressions::): the logical line number of the _next_ 2019line. Then a string (*note Strings: Strings.) is allowed: if present it 2020is a new logical file name. The rest of the line, if any, should be 2021whitespace. 2022 2023 If the first non-whitespace characters on the line are not numeric, 2024the line is ignored. (Just like a comment.) 2025 2026 # This is an ordinary comment. 2027 # 42-6 "new_file_name" # New logical file name 2028 # This is logical line # 36. 2029 This feature is deprecated, and may disappear from future versions of 2030'as'. 2031 2032 2033File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 2034 20353.4 Symbols 2036=========== 2037 2038A "symbol" is one or more characters chosen from the set of all letters 2039(both upper and lower case), digits and the three characters '_.$'. On 2040most machines, you can also use '$' in symbol names; exceptions are 2041noted in *note Machine Dependencies::. No symbol may begin with a 2042digit. Case is significant. There is no length limit; all characters 2043are significant. Multibyte characters are supported. Symbols are 2044delimited by characters not in that set, or by the beginning of a file 2045(since the source program must end with a newline, the end of a file is 2046not a possible symbol delimiter). *Note Symbols::. 2047 2048 Symbol names may also be enclosed in double quote '"' characters. In 2049such cases any characters are allowed, except for the NUL character. If 2050a double quote character is to be included in the symbol name it must be 2051preceeded by a backslash '\' character. 2052 2053 2054File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 2055 20563.5 Statements 2057============== 2058 2059A "statement" ends at a newline character ('\n') or a "line separator 2060character". The line separator character is target specific and 2061described in the _Syntax_ section of each target's documentation. Not 2062all targets support a line separator character. The newline or line 2063separator character is considered to be part of the preceding statement. 2064Newlines and separators within character constants are an exception: 2065they do not end statements. 2066 2067 It is an error to end any statement with end-of-file: the last 2068character of any input file should be a newline. 2069 2070 An empty statement is allowed, and may include whitespace. It is 2071ignored. 2072 2073 A statement begins with zero or more labels, optionally followed by a 2074key symbol which determines what kind of statement it is. The key 2075symbol determines the syntax of the rest of the statement. If the 2076symbol begins with a dot '.' then the statement is an assembler 2077directive: typically valid for any computer. If the symbol begins with 2078a letter the statement is an assembly language "instruction": it 2079assembles into a machine language instruction. Different versions of 2080'as' for different computers recognize different instructions. In fact, 2081the same symbol may represent a different instruction in a different 2082computer's assembly language. 2083 2084 A label is a symbol immediately followed by a colon (':'). 2085Whitespace before a label or after a colon is permitted, but you may not 2086have whitespace between a label's symbol and its colon. *Note Labels::. 2087 2088 For HPPA targets, labels need not be immediately followed by a colon, 2089but the definition of a label must begin in column zero. This also 2090implies that only one label may be defined on each line. 2091 2092 label: .directive followed by something 2093 another_label: # This is an empty statement. 2094 instruction operand_1, operand_2, ... 2095 2096 2097File: as.info, Node: Constants, Prev: Statements, Up: Syntax 2098 20993.6 Constants 2100============= 2101 2102A constant is a number, written so that its value is known by 2103inspection, without knowing any context. Like this: 2104 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 2105 .ascii "Ring the bell\7" # A string constant. 2106 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 2107 .float 0f-314159265358979323846264338327\ 2108 95028841971.693993751E-40 # - pi, a flonum. 2109 2110* Menu: 2111 2112* Characters:: Character Constants 2113* Numbers:: Number Constants 2114 2115 2116File: as.info, Node: Characters, Next: Numbers, Up: Constants 2117 21183.6.1 Character Constants 2119------------------------- 2120 2121There are two kinds of character constants. A "character" stands for 2122one character in one byte and its value may be used in numeric 2123expressions. String constants (properly called string _literals_) are 2124potentially many bytes and their values may not be used in arithmetic 2125expressions. 2126 2127* Menu: 2128 2129* Strings:: Strings 2130* Chars:: Characters 2131 2132 2133File: as.info, Node: Strings, Next: Chars, Up: Characters 2134 21353.6.1.1 Strings 2136............... 2137 2138A "string" is written between double-quotes. It may contain 2139double-quotes or null characters. The way to get special characters 2140into a string is to "escape" these characters: precede them with a 2141backslash '\' character. For example '\\' represents one backslash: the 2142first '\' is an escape which tells 'as' to interpret the second 2143character literally as a backslash (which prevents 'as' from recognizing 2144the second '\' as an escape character). The complete list of escapes 2145follows. 2146 2147'\b' 2148 Mnemonic for backspace; for ASCII this is octal code 010. 2149 2150'backslash-f' 2151 Mnemonic for FormFeed; for ASCII this is octal code 014. 2152 2153'\n' 2154 Mnemonic for newline; for ASCII this is octal code 012. 2155 2156'\r' 2157 Mnemonic for carriage-Return; for ASCII this is octal code 015. 2158 2159'\t' 2160 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 2161 2162'\ DIGIT DIGIT DIGIT' 2163 An octal character code. The numeric code is 3 octal digits. For 2164 compatibility with other Unix systems, 8 and 9 are accepted as 2165 digits: for example, '\008' has the value 010, and '\009' the value 2166 011. 2167 2168'\x HEX-DIGITS...' 2169 A hex character code. All trailing hex digits are combined. 2170 Either upper or lower case 'x' works. 2171 2172'\\' 2173 Represents one '\' character. 2174 2175'\"' 2176 Represents one '"' character. Needed in strings to represent this 2177 character, because an unescaped '"' would end the string. 2178 2179'\ ANYTHING-ELSE' 2180 Any other character when escaped by '\' gives a warning, but 2181 assembles as if the '\' was not present. The idea is that if you 2182 used an escape sequence you clearly didn't want the literal 2183 interpretation of the following character. However 'as' has no 2184 other interpretation, so 'as' knows it is giving you the wrong code 2185 and warns you of the fact. 2186 2187 Which characters are escapable, and what those escapes represent, 2188varies widely among assemblers. The current set is what we think the 2189BSD 4.2 assembler recognizes, and is a subset of what most C compilers 2190recognize. If you are in doubt, do not use an escape sequence. 2191 2192 2193File: as.info, Node: Chars, Prev: Strings, Up: Characters 2194 21953.6.1.2 Characters 2196.................. 2197 2198A single character may be written as a single quote immediately followed 2199by that character. Some backslash escapes apply to characters, '\b', 2200'\f', '\n', '\r', '\t', and '\"' with the same meaning as for strings, 2201plus '\'' for a single quote. So if you want to write the character 2202backslash, you must write ''\\' where the first '\' escapes the second 2203'\'. As you can see, the quote is an acute accent, not a grave accent. 2204A newline immediately following an acute accent is taken as a literal 2205character and does not count as the end of a statement. The value of a 2206character constant in a numeric expression is the machine's byte-wide 2207code for that character. 'as' assumes your character code is ASCII: 2208''A' means 65, ''B' means 66, and so on. 2209 2210 2211File: as.info, Node: Numbers, Prev: Characters, Up: Constants 2212 22133.6.2 Number Constants 2214---------------------- 2215 2216'as' distinguishes three kinds of numbers according to how they are 2217stored in the target machine. _Integers_ are numbers that would fit 2218into an 'int' in the C language. _Bignums_ are integers, but they are 2219stored in more than 32 bits. _Flonums_ are floating point numbers, 2220described below. 2221 2222* Menu: 2223 2224* Integers:: Integers 2225* Bignums:: Bignums 2226* Flonums:: Flonums 2227 2228 2229File: as.info, Node: Integers, Next: Bignums, Up: Numbers 2230 22313.6.2.1 Integers 2232................ 2233 2234A binary integer is '0b' or '0B' followed by zero or more of the binary 2235digits '01'. 2236 2237 An octal integer is '0' followed by zero or more of the octal digits 2238('01234567'). 2239 2240 A decimal integer starts with a non-zero digit followed by zero or 2241more digits ('0123456789'). 2242 2243 A hexadecimal integer is '0x' or '0X' followed by one or more 2244hexadecimal digits chosen from '0123456789abcdefABCDEF'. 2245 2246 Integers have the usual values. To denote a negative integer, use 2247the prefix operator '-' discussed under expressions (*note Prefix 2248Operators: Prefix Ops.). 2249 2250 2251File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 2252 22533.6.2.2 Bignums 2254............... 2255 2256A "bignum" has the same syntax and semantics as an integer except that 2257the number (or its negative) takes more than 32 bits to represent in 2258binary. The distinction is made because in some places integers are 2259permitted while bignums are not. 2260 2261 2262File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2263 22643.6.2.3 Flonums 2265............... 2266 2267A "flonum" represents a floating point number. The translation is 2268indirect: a decimal floating point number from the text is converted by 2269'as' to a generic binary floating point number of more than sufficient 2270precision. This generic floating point number is converted to a 2271particular computer's floating point format (or formats) by a portion of 2272'as' specialized to that computer. 2273 2274 A flonum is written by writing (in order) 2275 * The digit '0'. ('0' is optional on the HPPA.) 2276 2277 * A letter, to tell 'as' the rest of the number is a flonum. 'e' is 2278 recommended. Case is not important. 2279 2280 On the H8/300 and Renesas / SuperH SH architectures, the letter 2281 must be one of the letters 'DFPRSX' (in upper or lower case). 2282 2283 On the ARC, the letter must be one of the letters 'DFRS' (in upper 2284 or lower case). 2285 2286 On the HPPA architecture, the letter must be 'E' (upper case only). 2287 2288 * An optional sign: either '+' or '-'. 2289 2290 * An optional "integer part": zero or more decimal digits. 2291 2292 * An optional "fractional part": '.' followed by zero or more decimal 2293 digits. 2294 2295 * An optional exponent, consisting of: 2296 2297 * An 'E' or 'e'. 2298 * Optional sign: either '+' or '-'. 2299 * One or more decimal digits. 2300 2301 At least one of the integer part or the fractional part must be 2302present. The floating point number has the usual base-10 value. 2303 2304 'as' does all processing using integers. Flonums are computed 2305independently of any floating point hardware in the computer running 2306'as'. 2307 2308 2309File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2310 23114 Sections and Relocation 2312************************* 2313 2314* Menu: 2315 2316* Secs Background:: Background 2317* Ld Sections:: Linker Sections 2318* As Sections:: Assembler Internal Sections 2319* Sub-Sections:: Sub-Sections 2320* bss:: bss Section 2321 2322 2323File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2324 23254.1 Background 2326============== 2327 2328Roughly, a section is a range of addresses, with no gaps; all data "in" 2329those addresses is treated the same for some particular purpose. For 2330example there may be a "read only" section. 2331 2332 The linker 'ld' reads many object files (partial programs) and 2333combines their contents to form a runnable program. When 'as' emits an 2334object file, the partial program is assumed to start at address 0. 'ld' 2335assigns the final addresses for the partial program, so that different 2336partial programs do not overlap. This is actually an 2337oversimplification, but it suffices to explain how 'as' uses sections. 2338 2339 'ld' moves blocks of bytes of your program to their run-time 2340addresses. These blocks slide to their run-time addresses as rigid 2341units; their length does not change and neither does the order of bytes 2342within them. Such a rigid unit is called a _section_. Assigning 2343run-time addresses to sections is called "relocation". It includes the 2344task of adjusting mentions of object-file addresses so they refer to the 2345proper run-time addresses. For the H8/300, and for the Renesas / SuperH 2346SH, 'as' pads sections if needed to ensure they end on a word (sixteen 2347bit) boundary. 2348 2349 An object file written by 'as' has at least three sections, any of 2350which may be empty. These are named "text", "data" and "bss" sections. 2351 2352 When it generates COFF or ELF output, 'as' can also generate whatever 2353other named sections you specify using the '.section' directive (*note 2354'.section': Section.). If you do not use any directives that place 2355output in the '.text' or '.data' sections, these sections still exist, 2356but are empty. 2357 2358 When 'as' generates SOM or ELF output for the HPPA, 'as' can also 2359generate whatever other named sections you specify using the '.space' 2360and '.subspace' directives. See 'HP9000 Series 800 Assembly Language 2361Reference Manual' (HP 92432-90001) for details on the '.space' and 2362'.subspace' assembler directives. 2363 2364 Additionally, 'as' uses different names for the standard text, data, 2365and bss sections when generating SOM output. Program text is placed 2366into the '$CODE$' section, data into '$DATA$', and BSS into '$BSS$'. 2367 2368 Within the object file, the text section starts at address '0', the 2369data section follows, and the bss section follows the data section. 2370 2371 When generating either SOM or ELF output files on the HPPA, the text 2372section starts at address '0', the data section at address '0x4000000', 2373and the bss section follows the data section. 2374 2375 To let 'ld' know which data changes when the sections are relocated, 2376and how to change that data, 'as' also writes to the object file details 2377of the relocation needed. To perform relocation 'ld' must know, each 2378time an address in the object file is mentioned: 2379 * Where in the object file is the beginning of this reference to an 2380 address? 2381 * How long (in bytes) is this reference? 2382 * Which section does the address refer to? What is the numeric value 2383 of 2384 (ADDRESS) - (START-ADDRESS OF SECTION)? 2385 * Is the reference to an address "Program-Counter relative"? 2386 2387 In fact, every address 'as' ever uses is expressed as 2388 (SECTION) + (OFFSET INTO SECTION) 2389Further, most expressions 'as' computes have this section-relative 2390nature. (For some object formats, such as SOM for the HPPA, some 2391expressions are symbol-relative instead.) 2392 2393 In this manual we use the notation {SECNAME N} to mean "offset N into 2394section SECNAME." 2395 2396 Apart from text, data and bss sections you need to know about the 2397"absolute" section. When 'ld' mixes partial programs, addresses in the 2398absolute section remain unchanged. For example, address '{absolute 0}' 2399is "relocated" to run-time address 0 by 'ld'. Although the linker never 2400arranges two partial programs' data sections with overlapping addresses 2401after linking, _by definition_ their absolute sections must overlap. 2402Address '{absolute 239}' in one part of a program is always the same 2403address when the program is running as address '{absolute 239}' in any 2404other part of the program. 2405 2406 The idea of sections is extended to the "undefined" section. Any 2407address whose section is unknown at assembly time is by definition 2408rendered {undefined U}--where U is filled in later. Since numbers are 2409always defined, the only way to generate an undefined address is to 2410mention an undefined symbol. A reference to a named common block would 2411be such a symbol: its value is unknown at assembly time so it has 2412section _undefined_. 2413 2414 By analogy the word _section_ is used to describe groups of sections 2415in the linked program. 'ld' puts all partial programs' text sections in 2416contiguous addresses in the linked program. It is customary to refer to 2417the _text section_ of a program, meaning all the addresses of all 2418partial programs' text sections. Likewise for data and bss sections. 2419 2420 Some sections are manipulated by 'ld'; others are invented for use of 2421'as' and have no meaning except during assembly. 2422 2423 2424File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2425 24264.2 Linker Sections 2427=================== 2428 2429'ld' deals with just four kinds of sections, summarized below. 2430 2431*named sections* 2432*text section* 2433*data section* 2434 These sections hold your program. 'as' and 'ld' treat them as 2435 separate but equal sections. Anything you can say of one section 2436 is true of another. When the program is running, however, it is 2437 customary for the text section to be unalterable. The text section 2438 is often shared among processes: it contains instructions, 2439 constants and the like. The data section of a running program is 2440 usually alterable: for example, C variables would be stored in the 2441 data section. 2442 2443*bss section* 2444 This section contains zeroed bytes when your program begins 2445 running. It is used to hold uninitialized variables or common 2446 storage. The length of each partial program's bss section is 2447 important, but because it starts out containing zeroed bytes there 2448 is no need to store explicit zero bytes in the object file. The 2449 bss section was invented to eliminate those explicit zeros from 2450 object files. 2451 2452*absolute section* 2453 Address 0 of this section is always "relocated" to runtime address 2454 0. This is useful if you want to refer to an address that 'ld' 2455 must not change when relocating. In this sense we speak of 2456 absolute addresses being "unrelocatable": they do not change during 2457 relocation. 2458 2459*undefined section* 2460 This "section" is a catch-all for address references to objects not 2461 in the preceding sections. 2462 2463 An idealized example of three relocatable sections follows. The 2464example uses the traditional section names '.text' and '.data'. Memory 2465addresses are on the horizontal axis. 2466 2467 +-----+----+--+ 2468 partial program # 1: |ttttt|dddd|00| 2469 +-----+----+--+ 2470 2471 text data bss 2472 seg. seg. seg. 2473 2474 +---+---+---+ 2475 partial program # 2: |TTT|DDD|000| 2476 +---+---+---+ 2477 2478 +--+---+-----+--+----+---+-----+~~ 2479 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2480 +--+---+-----+--+----+---+-----+~~ 2481 2482 addresses: 0 ... 2483 2484 2485File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2486 24874.3 Assembler Internal Sections 2488=============================== 2489 2490These sections are meant only for the internal use of 'as'. They have 2491no meaning at run-time. You do not really need to know about these 2492sections for most purposes; but they can be mentioned in 'as' warning 2493messages, so it might be helpful to have an idea of their meanings to 2494'as'. These sections are used to permit the value of every expression 2495in your assembly language program to be a section-relative address. 2496 2497ASSEMBLER-INTERNAL-LOGIC-ERROR! 2498 An internal assembler logic error has been found. This means there 2499 is a bug in the assembler. 2500 2501expr section 2502 The assembler stores complex expression internally as combinations 2503 of symbols. When it needs to represent an expression as a symbol, 2504 it puts it in the expr section. 2505 2506 2507File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2508 25094.4 Sub-Sections 2510================ 2511 2512Assembled bytes conventionally fall into two sections: text and data. 2513You may have separate groups of data in named sections that you want to 2514end up near to each other in the object file, even though they are not 2515contiguous in the assembler source. 'as' allows you to use 2516"subsections" for this purpose. Within each section, there can be 2517numbered subsections with values from 0 to 8192. Objects assembled into 2518the same subsection go into the object file together with other objects 2519in the same subsection. For example, a compiler might want to store 2520constants in the text section, but might not want to have them 2521interspersed with the program being assembled. In this case, the 2522compiler could issue a '.text 0' before each section of code being 2523output, and a '.text 1' before each group of constants being output. 2524 2525 Subsections are optional. If you do not use subsections, everything 2526goes in subsection number zero. 2527 2528 Each subsection is zero-padded up to a multiple of four bytes. 2529(Subsections may be padded a different amount on different flavors of 2530'as'.) 2531 2532 Subsections appear in your object file in numeric order, lowest 2533numbered to highest. (All this to be compatible with other people's 2534assemblers.) The object file contains no representation of subsections; 2535'ld' and other programs that manipulate object files see no trace of 2536them. They just see all your text subsections as a text section, and 2537all your data subsections as a data section. 2538 2539 To specify which subsection you want subsequent statements assembled 2540into, use a numeric argument to specify it, in a '.text EXPRESSION' or a 2541'.data EXPRESSION' statement. When generating COFF output, you can also 2542use an extra subsection argument with arbitrary named sections: 2543'.section NAME, EXPRESSION'. When generating ELF output, you can also 2544use the '.subsection' directive (*note SubSection::) to specify a 2545subsection: '.subsection EXPRESSION'. EXPRESSION should be an absolute 2546expression (*note Expressions::). If you just say '.text' then '.text 25470' is assumed. Likewise '.data' means '.data 0'. Assembly begins in 2548'text 0'. For instance: 2549 .text 0 # The default subsection is text 0 anyway. 2550 .ascii "This lives in the first text subsection. *" 2551 .text 1 2552 .ascii "But this lives in the second text subsection." 2553 .data 0 2554 .ascii "This lives in the data section," 2555 .ascii "in the first data subsection." 2556 .text 0 2557 .ascii "This lives in the first text section," 2558 .ascii "immediately following the asterisk (*)." 2559 2560 Each section has a "location counter" incremented by one for every 2561byte assembled into that section. Because subsections are merely a 2562convenience restricted to 'as' there is no concept of a subsection 2563location counter. There is no way to directly manipulate a location 2564counter--but the '.align' directive changes it, and any label definition 2565captures its current value. The location counter of the section where 2566statements are being assembled is said to be the "active" location 2567counter. 2568 2569 2570File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2571 25724.5 bss Section 2573=============== 2574 2575The bss section is used for local common variable storage. You may 2576allocate address space in the bss section, but you may not dictate data 2577to load into it before your program executes. When your program starts 2578running, all the contents of the bss section are zeroed bytes. 2579 2580 The '.lcomm' pseudo-op defines a symbol in the bss section; see *note 2581'.lcomm': Lcomm. 2582 2583 The '.comm' pseudo-op may be used to declare a common symbol, which 2584is another form of uninitialized symbol; see *note '.comm': Comm. 2585 2586 When assembling for a target which supports multiple sections, such 2587as ELF or COFF, you may switch into the '.bss' section and define 2588symbols as usual; see *note '.section': Section. You may only assemble 2589zero values into the section. Typically the section will only contain 2590symbol definitions and '.skip' directives (*note '.skip': Skip.). 2591 2592 2593File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2594 25955 Symbols 2596********* 2597 2598Symbols are a central concept: the programmer uses symbols to name 2599things, the linker uses symbols to link, and the debugger uses symbols 2600to debug. 2601 2602 _Warning:_ 'as' does not place symbols in the object file in the 2603 same order they were declared. This may break some debuggers. 2604 2605* Menu: 2606 2607* Labels:: Labels 2608* Setting Symbols:: Giving Symbols Other Values 2609* Symbol Names:: Symbol Names 2610* Dot:: The Special Dot Symbol 2611* Symbol Attributes:: Symbol Attributes 2612 2613 2614File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2615 26165.1 Labels 2617========== 2618 2619A "label" is written as a symbol immediately followed by a colon ':'. 2620The symbol then represents the current value of the active location 2621counter, and is, for example, a suitable instruction operand. You are 2622warned if you use the same symbol to represent two different locations: 2623the first definition overrides any other definitions. 2624 2625 On the HPPA, the usual form for a label need not be immediately 2626followed by a colon, but instead must start in column zero. Only one 2627label may be defined on a single line. To work around this, the HPPA 2628version of 'as' also provides a special directive '.label' for defining 2629labels more flexibly. 2630 2631 2632File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2633 26345.2 Giving Symbols Other Values 2635=============================== 2636 2637A symbol can be given an arbitrary value by writing a symbol, followed 2638by an equals sign '=', followed by an expression (*note Expressions::). 2639This is equivalent to using the '.set' directive. *Note '.set': Set. 2640In the same way, using a double equals sign '=''=' here represents an 2641equivalent of the '.eqv' directive. *Note '.eqv': Eqv. 2642 2643 Blackfin does not support symbol assignment with '='. 2644 2645 2646File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2647 26485.3 Symbol Names 2649================ 2650 2651Symbol names begin with a letter or with one of '._'. On most machines, 2652you can also use '$' in symbol names; exceptions are noted in *note 2653Machine Dependencies::. That character may be followed by any string of 2654digits, letters, dollar signs (unless otherwise noted for a particular 2655target machine), and underscores. 2656 2657 Case of letters is significant: 'foo' is a different symbol name than 2658'Foo'. 2659 2660 Symbol names do not start with a digit. An exception to this rule is 2661made for Local Labels. See below. 2662 2663 Multibyte characters are supported. To generate a symbol name 2664containing multibyte characters enclose it within double quotes and use 2665escape codes. cf *Note Strings::. Generating a multibyte symbol name 2666from a label is not currently supported. 2667 2668 Each symbol has exactly one name. Each name in an assembly language 2669program refers to exactly one symbol. You may use that symbol name any 2670number of times in a program. 2671 2672Local Symbol Names 2673------------------ 2674 2675A local symbol is any symbol beginning with certain local label 2676prefixes. By default, the local label prefix is '.L' for ELF systems or 2677'L' for traditional a.out systems, but each target may have its own set 2678of local label prefixes. On the HPPA local symbols begin with 'L$'. 2679 2680 Local symbols are defined and used within the assembler, but they are 2681normally not saved in object files. Thus, they are not visible when 2682debugging. You may use the '-L' option (*note Include Local Symbols: 2683L.) to retain the local symbols in the object files. 2684 2685Local Labels 2686------------ 2687 2688Local labels are different from local symbols. Local labels help 2689compilers and programmers use names temporarily. They create symbols 2690which are guaranteed to be unique over the entire scope of the input 2691source code and which can be referred to by a simple notation. To 2692define a local label, write a label of the form 'N:' (where N represents 2693any non-negative integer). To refer to the most recent previous 2694definition of that label write 'Nb', using the same number as when you 2695defined the label. To refer to the next definition of a local label, 2696write 'Nf'. The 'b' stands for "backwards" and the 'f' stands for 2697"forwards". 2698 2699 There is no restriction on how you can use these labels, and you can 2700reuse them too. So that it is possible to repeatedly define the same 2701local label (using the same number 'N'), although you can only refer to 2702the most recently defined local label of that number (for a backwards 2703reference) or the next definition of a specific local label for a 2704forward reference. It is also worth noting that the first 10 local 2705labels ('0:'...'9:') are implemented in a slightly more efficient manner 2706than the others. 2707 2708 Here is an example: 2709 2710 1: branch 1f 2711 2: branch 1b 2712 1: branch 2f 2713 2: branch 1b 2714 2715 Which is the equivalent of: 2716 2717 label_1: branch label_3 2718 label_2: branch label_1 2719 label_3: branch label_4 2720 label_4: branch label_3 2721 2722 Local label names are only a notational device. They are immediately 2723transformed into more conventional symbol names before the assembler 2724uses them. The symbol names are stored in the symbol table, appear in 2725error messages, and are optionally emitted to the object file. The 2726names are constructed using these parts: 2727 2728'_local label prefix_' 2729 All local symbols begin with the system-specific local label 2730 prefix. Normally both 'as' and 'ld' forget symbols that start with 2731 the local label prefix. These labels are used for symbols you are 2732 never intended to see. If you use the '-L' option then 'as' 2733 retains these symbols in the object file. If you also instruct 2734 'ld' to retain these symbols, you may use them in debugging. 2735 2736'NUMBER' 2737 This is the number that was used in the local label definition. So 2738 if the label is written '55:' then the number is '55'. 2739 2740'C-B' 2741 This unusual character is included so you do not accidentally 2742 invent a symbol of the same name. The character has ASCII value of 2743 '\002' (control-B). 2744 2745'_ordinal number_' 2746 This is a serial number to keep the labels distinct. The first 2747 definition of '0:' gets the number '1'. The 15th definition of 2748 '0:' gets the number '15', and so on. Likewise the first 2749 definition of '1:' gets the number '1' and its 15th definition gets 2750 '15' as well. 2751 2752 So for example, the first '1:' may be named '.L1C-B1', and the 44th 2753'3:' may be named '.L3C-B44'. 2754 2755Dollar Local Labels 2756------------------- 2757 2758On some targets 'as' also supports an even more local form of local 2759labels called dollar labels. These labels go out of scope (i.e., they 2760become undefined) as soon as a non-local label is defined. Thus they 2761remain valid for only a small region of the input source code. Normal 2762local labels, by contrast, remain in scope for the entire file, or until 2763they are redefined by another occurrence of the same local label. 2764 2765 Dollar labels are defined in exactly the same way as ordinary local 2766labels, except that they have a dollar sign suffix to their numeric 2767value, e.g., '55$:'. 2768 2769 They can also be distinguished from ordinary local labels by their 2770transformed names which use ASCII character '\001' (control-A) as the 2771magic character to distinguish them from ordinary labels. For example, 2772the fifth definition of '6$' may be named '.L6'C-A'5'. 2773 2774 2775File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2776 27775.4 The Special Dot Symbol 2778========================== 2779 2780The special symbol '.' refers to the current address that 'as' is 2781assembling into. Thus, the expression 'melvin: .long .' defines 2782'melvin' to contain its own address. Assigning a value to '.' is 2783treated the same as a '.org' directive. Thus, the expression '.=.+4' is 2784the same as saying '.space 4'. 2785 2786 2787File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2788 27895.5 Symbol Attributes 2790===================== 2791 2792Every symbol has, as well as its name, the attributes "Value" and 2793"Type". Depending on output format, symbols can also have auxiliary 2794attributes. 2795 2796 If you use a symbol without defining it, 'as' assumes zero for all 2797these attributes, and probably won't warn you. This makes the symbol an 2798externally defined symbol, which is generally what you would want. 2799 2800* Menu: 2801 2802* Symbol Value:: Value 2803* Symbol Type:: Type 2804* a.out Symbols:: Symbol Attributes: 'a.out' 2805* COFF Symbols:: Symbol Attributes for COFF 2806* SOM Symbols:: Symbol Attributes for SOM 2807 2808 2809File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2810 28115.5.1 Value 2812----------- 2813 2814The value of a symbol is (usually) 32 bits. For a symbol which labels a 2815location in the text, data, bss or absolute sections the value is the 2816number of addresses from the start of that section to the label. 2817Naturally for text, data and bss sections the value of a symbol changes 2818as 'ld' changes section base addresses during linking. Absolute 2819symbols' values do not change during linking: that is why they are 2820called absolute. 2821 2822 The value of an undefined symbol is treated in a special way. If it 2823is 0 then the symbol is not defined in this assembler source file, and 2824'ld' tries to determine its value from other files linked into the same 2825program. You make this kind of symbol simply by mentioning a symbol 2826name without defining it. A non-zero value represents a '.comm' common 2827declaration. The value is how much common storage to reserve, in bytes 2828(addresses). The symbol refers to the first address of the allocated 2829storage. 2830 2831 2832File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2833 28345.5.2 Type 2835---------- 2836 2837The type attribute of a symbol contains relocation (section) 2838information, any flag settings indicating that a symbol is external, and 2839(optionally), other information for linkers and debuggers. The exact 2840format depends on the object-code output format in use. 2841 2842 2843File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2844 28455.5.3 Symbol Attributes: 'a.out' 2846-------------------------------- 2847 2848* Menu: 2849 2850* Symbol Desc:: Descriptor 2851* Symbol Other:: Other 2852 2853 2854File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2855 28565.5.3.1 Descriptor 2857.................. 2858 2859This is an arbitrary 16-bit value. You may establish a symbol's 2860descriptor value by using a '.desc' statement (*note '.desc': Desc.). A 2861descriptor value means nothing to 'as'. 2862 2863 2864File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2865 28665.5.3.2 Other 2867............. 2868 2869This is an arbitrary 8-bit value. It means nothing to 'as'. 2870 2871 2872File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2873 28745.5.4 Symbol Attributes for COFF 2875-------------------------------- 2876 2877The COFF format supports a multitude of auxiliary symbol attributes; 2878like the primary symbol attributes, they are set between '.def' and 2879'.endef' directives. 2880 28815.5.4.1 Primary Attributes 2882.......................... 2883 2884The symbol name is set with '.def'; the value and type, respectively, 2885with '.val' and '.type'. 2886 28875.5.4.2 Auxiliary Attributes 2888............................ 2889 2890The 'as' directives '.dim', '.line', '.scl', '.size', '.tag', and 2891'.weak' can generate auxiliary symbol table information for COFF. 2892 2893 2894File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2895 28965.5.5 Symbol Attributes for SOM 2897------------------------------- 2898 2899The SOM format for the HPPA supports a multitude of symbol attributes 2900set with the '.EXPORT' and '.IMPORT' directives. 2901 2902 The attributes are described in 'HP9000 Series 800 Assembly Language 2903Reference Manual' (HP 92432-90001) under the 'IMPORT' and 'EXPORT' 2904assembler directive documentation. 2905 2906 2907File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 2908 29096 Expressions 2910************* 2911 2912An "expression" specifies an address or numeric value. Whitespace may 2913precede and/or follow an expression. 2914 2915 The result of an expression must be an absolute number, or else an 2916offset into a particular section. If an expression is not absolute, and 2917there is not enough information when 'as' sees the expression to know 2918its section, a second pass over the source program might be necessary to 2919interpret the expression--but the second pass is currently not 2920implemented. 'as' aborts with an error message in this situation. 2921 2922* Menu: 2923 2924* Empty Exprs:: Empty Expressions 2925* Integer Exprs:: Integer Expressions 2926 2927 2928File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 2929 29306.1 Empty Expressions 2931===================== 2932 2933An empty expression has no value: it is just whitespace or null. 2934Wherever an absolute expression is required, you may omit the 2935expression, and 'as' assumes a value of (absolute) 0. This is 2936compatible with other assemblers. 2937 2938 2939File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 2940 29416.2 Integer Expressions 2942======================= 2943 2944An "integer expression" is one or more _arguments_ delimited by 2945_operators_. 2946 2947* Menu: 2948 2949* Arguments:: Arguments 2950* Operators:: Operators 2951* Prefix Ops:: Prefix Operators 2952* Infix Ops:: Infix Operators 2953 2954 2955File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 2956 29576.2.1 Arguments 2958--------------- 2959 2960"Arguments" are symbols, numbers or subexpressions. In other contexts 2961arguments are sometimes called "arithmetic operands". In this manual, 2962to avoid confusing them with the "instruction operands" of the machine 2963language, we use the term "argument" to refer to parts of expressions 2964only, reserving the word "operand" to refer only to machine instruction 2965operands. 2966 2967 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 2968text, data, bss, absolute, or undefined. NNN is a signed, 2's 2969complement 32 bit integer. 2970 2971 Numbers are usually integers. 2972 2973 A number can be a flonum or bignum. In this case, you are warned 2974that only the low order 32 bits are used, and 'as' pretends these 32 2975bits are an integer. You may write integer-manipulating instructions 2976that act on exotic constants, compatible with other assemblers. 2977 2978 Subexpressions are a left parenthesis '(' followed by an integer 2979expression, followed by a right parenthesis ')'; or a prefix operator 2980followed by an argument. 2981 2982 2983File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 2984 29856.2.2 Operators 2986--------------- 2987 2988"Operators" are arithmetic functions, like '+' or '%'. Prefix operators 2989are followed by an argument. Infix operators appear between their 2990arguments. Operators may be preceded and/or followed by whitespace. 2991 2992 2993File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 2994 29956.2.3 Prefix Operator 2996--------------------- 2997 2998'as' has the following "prefix operators". They each take one argument, 2999which must be absolute. 3000 3001'-' 3002 "Negation". Two's complement negation. 3003'~' 3004 "Complementation". Bitwise not. 3005 3006 3007File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 3008 30096.2.4 Infix Operators 3010--------------------- 3011 3012"Infix operators" take two arguments, one on either side. Operators 3013have precedence, but operations with equal precedence are performed left 3014to right. Apart from '+' or '-', both arguments must be absolute, and 3015the result is absolute. 3016 3017 1. Highest Precedence 3018 3019 '*' 3020 "Multiplication". 3021 3022 '/' 3023 "Division". Truncation is the same as the C operator '/' 3024 3025 '%' 3026 "Remainder". 3027 3028 '<<' 3029 "Shift Left". Same as the C operator '<<'. 3030 3031 '>>' 3032 "Shift Right". Same as the C operator '>>'. 3033 3034 2. Intermediate precedence 3035 3036 '|' 3037 3038 "Bitwise Inclusive Or". 3039 3040 '&' 3041 "Bitwise And". 3042 3043 '^' 3044 "Bitwise Exclusive Or". 3045 3046 '!' 3047 "Bitwise Or Not". 3048 3049 3. Low Precedence 3050 3051 '+' 3052 "Addition". If either argument is absolute, the result has 3053 the section of the other argument. You may not add together 3054 arguments from different sections. 3055 3056 '-' 3057 "Subtraction". If the right argument is absolute, the result 3058 has the section of the left argument. If both arguments are 3059 in the same section, the result is absolute. You may not 3060 subtract arguments from different sections. 3061 3062 '==' 3063 "Is Equal To" 3064 '<>' 3065 '!=' 3066 "Is Not Equal To" 3067 '<' 3068 "Is Less Than" 3069 '>' 3070 "Is Greater Than" 3071 '>=' 3072 "Is Greater Than Or Equal To" 3073 '<=' 3074 "Is Less Than Or Equal To" 3075 3076 The comparison operators can be used as infix operators. A 3077 true results has a value of -1 whereas a false result has a 3078 value of 0. Note, these operators perform signed comparisons. 3079 3080 4. Lowest Precedence 3081 3082 '&&' 3083 "Logical And". 3084 3085 '||' 3086 "Logical Or". 3087 3088 These two logical operations can be used to combine the 3089 results of sub expressions. Note, unlike the comparison 3090 operators a true result returns a value of 1 but a false 3091 results does still return 0. Also note that the logical or 3092 operator has a slightly lower precedence than logical and. 3093 3094 In short, it's only meaningful to add or subtract the _offsets_ in an 3095address; you can only have a defined section in one of the two 3096arguments. 3097 3098 3099File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 3100 31017 Assembler Directives 3102********************** 3103 3104All assembler directives have names that begin with a period ('.'). The 3105names are case insensitive for most targets, and usually written in 3106lower case. 3107 3108 This chapter discusses directives that are available regardless of 3109the target machine configuration for the GNU assembler. Some machine 3110configurations provide additional directives. *Note Machine 3111Dependencies::. 3112 3113* Menu: 3114 3115* Abort:: '.abort' 3116* ABORT (COFF):: '.ABORT' 3117 3118* Align:: '.align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3119* Altmacro:: '.altmacro' 3120* Ascii:: '.ascii "STRING"'... 3121* Asciz:: '.asciz "STRING"'... 3122* Balign:: '.balign [ABS-EXPR[, ABS-EXPR]]' 3123* Bundle directives:: '.bundle_align_mode ABS-EXPR', etc 3124* Byte:: '.byte EXPRESSIONS' 3125* CFI directives:: '.cfi_startproc [simple]', '.cfi_endproc', etc. 3126* Comm:: '.comm SYMBOL , LENGTH ' 3127* Data:: '.data SUBSECTION' 3128* Dc:: '.dc[SIZE] EXPRESSIONS' 3129* Dcb:: '.dcb[SIZE] NUMBER [,FILL]' 3130* Ds:: '.ds[SIZE] NUMBER [,FILL]' 3131* Def:: '.def NAME' 3132* Desc:: '.desc SYMBOL, ABS-EXPRESSION' 3133* Dim:: '.dim' 3134 3135* Double:: '.double FLONUMS' 3136* Eject:: '.eject' 3137* Else:: '.else' 3138* Elseif:: '.elseif' 3139* End:: '.end' 3140* Endef:: '.endef' 3141 3142* Endfunc:: '.endfunc' 3143* Endif:: '.endif' 3144* Equ:: '.equ SYMBOL, EXPRESSION' 3145* Equiv:: '.equiv SYMBOL, EXPRESSION' 3146* Eqv:: '.eqv SYMBOL, EXPRESSION' 3147* Err:: '.err' 3148* Error:: '.error STRING' 3149* Exitm:: '.exitm' 3150* Extern:: '.extern' 3151* Fail:: '.fail' 3152* File:: '.file' 3153* Fill:: '.fill REPEAT , SIZE , VALUE' 3154* Float:: '.float FLONUMS' 3155* Func:: '.func' 3156* Global:: '.global SYMBOL', '.globl SYMBOL' 3157* Gnu_attribute:: '.gnu_attribute TAG,VALUE' 3158* Hidden:: '.hidden NAMES' 3159 3160* hword:: '.hword EXPRESSIONS' 3161* Ident:: '.ident' 3162* If:: '.if ABSOLUTE EXPRESSION' 3163* Incbin:: '.incbin "FILE"[,SKIP[,COUNT]]' 3164* Include:: '.include "FILE"' 3165* Int:: '.int EXPRESSIONS' 3166* Internal:: '.internal NAMES' 3167 3168* Irp:: '.irp SYMBOL,VALUES'... 3169* Irpc:: '.irpc SYMBOL,VALUES'... 3170* Lcomm:: '.lcomm SYMBOL , LENGTH' 3171* Lflags:: '.lflags' 3172* Line:: '.line LINE-NUMBER' 3173 3174* Linkonce:: '.linkonce [TYPE]' 3175* List:: '.list' 3176* Ln:: '.ln LINE-NUMBER' 3177* Loc:: '.loc FILENO LINENO' 3178* Loc_mark_labels:: '.loc_mark_labels ENABLE' 3179* Local:: '.local NAMES' 3180 3181* Long:: '.long EXPRESSIONS' 3182 3183* Macro:: '.macro NAME ARGS'... 3184* MRI:: '.mri VAL' 3185* Noaltmacro:: '.noaltmacro' 3186* Nolist:: '.nolist' 3187* Nops:: '.nops SIZE[, CONTROL]' 3188* Octa:: '.octa BIGNUMS' 3189* Offset:: '.offset LOC' 3190* Org:: '.org NEW-LC, FILL' 3191* P2align:: '.p2align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3192* PopSection:: '.popsection' 3193* Previous:: '.previous' 3194 3195* Print:: '.print STRING' 3196* Protected:: '.protected NAMES' 3197 3198* Psize:: '.psize LINES, COLUMNS' 3199* Purgem:: '.purgem NAME' 3200* PushSection:: '.pushsection NAME' 3201 3202* Quad:: '.quad BIGNUMS' 3203* Reloc:: '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 3204* Rept:: '.rept COUNT' 3205* Sbttl:: '.sbttl "SUBHEADING"' 3206* Scl:: '.scl CLASS' 3207* Section:: '.section NAME[, FLAGS]' 3208 3209* Set:: '.set SYMBOL, EXPRESSION' 3210* Short:: '.short EXPRESSIONS' 3211* Single:: '.single FLONUMS' 3212* Size:: '.size [NAME , EXPRESSION]' 3213* Skip:: '.skip SIZE [,FILL]' 3214 3215* Sleb128:: '.sleb128 EXPRESSIONS' 3216* Space:: '.space SIZE [,FILL]' 3217* Stab:: '.stabd, .stabn, .stabs' 3218 3219* String:: '.string "STR"', '.string8 "STR"', '.string16 "STR"', '.string32 "STR"', '.string64 "STR"' 3220* Struct:: '.struct EXPRESSION' 3221* SubSection:: '.subsection' 3222* Symver:: '.symver NAME,NAME2@NODENAME' 3223 3224* Tag:: '.tag STRUCTNAME' 3225 3226* Text:: '.text SUBSECTION' 3227* Title:: '.title "HEADING"' 3228* Type:: '.type <INT | NAME , TYPE DESCRIPTION>' 3229 3230* Uleb128:: '.uleb128 EXPRESSIONS' 3231* Val:: '.val ADDR' 3232 3233* Version:: '.version "STRING"' 3234* VTableEntry:: '.vtable_entry TABLE, OFFSET' 3235* VTableInherit:: '.vtable_inherit CHILD, PARENT' 3236 3237* Warning:: '.warning STRING' 3238* Weak:: '.weak NAMES' 3239* Weakref:: '.weakref ALIAS, SYMBOL' 3240* Word:: '.word EXPRESSIONS' 3241* Zero:: '.zero SIZE' 3242* 2byte:: '.2byte EXPRESSIONS' 3243* 4byte:: '.4byte EXPRESSIONS' 3244* 8byte:: '.8byte BIGNUMS' 3245* Deprecated:: Deprecated Directives 3246 3247 3248File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3249 32507.1 '.abort' 3251============ 3252 3253This directive stops the assembly immediately. It is for compatibility 3254with other assemblers. The original idea was that the assembly language 3255source would be piped into the assembler. If the sender of the source 3256quit, it could use this directive tells 'as' to quit also. One day 3257'.abort' will not be supported. 3258 3259 3260File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3261 32627.2 '.ABORT' (COFF) 3263=================== 3264 3265When producing COFF output, 'as' accepts this directive as a synonym for 3266'.abort'. 3267 3268 3269File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3270 32717.3 '.align [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3272=============================================== 3273 3274Pad the location counter (in the current subsection) to a particular 3275storage boundary. The first expression (which must be absolute) is the 3276alignment required, as described below. If this expression is omitted 3277then a default value of 0 is used, effectively disabling alignment 3278requirements. 3279 3280 The second expression (also absolute) gives the fill value to be 3281stored in the padding bytes. It (and the comma) may be omitted. If it 3282is omitted, the padding bytes are normally zero. However, on most 3283systems, if the section is marked as containing code and the fill value 3284is omitted, the space is filled with no-op instructions. 3285 3286 The third expression is also absolute, and is also optional. If it 3287is present, it is the maximum number of bytes that should be skipped by 3288this alignment directive. If doing the alignment would require skipping 3289more bytes than the specified maximum, then the alignment is not done at 3290all. You can omit the fill value (the second argument) entirely by 3291simply using two commas after the required alignment; this can be useful 3292if you want the alignment to be filled with no-op instructions when 3293appropriate. 3294 3295 The way the required alignment is specified varies from system to 3296system. For the arc, hppa, i386 using ELF, iq2000, m68k, or1k, s390, 3297sparc, tic4x and xtensa, the first expression is the alignment request 3298in bytes. For example '.align 8' advances the location counter until it 3299is a multiple of 8. If the location counter is already a multiple of 8, 3300no change is needed. For the tic54x, the first expression is the 3301alignment request in words. 3302 3303 For other systems, including ppc, i386 using a.out format, arm and 3304strongarm, it is the number of low-order zero bits the location counter 3305must have after advancement. For example '.align 3' advances the 3306location counter until it is a multiple of 8. If the location counter 3307is already a multiple of 8, no change is needed. 3308 3309 This inconsistency is due to the different behaviors of the various 3310native assemblers for these systems which GAS must emulate. GAS also 3311provides '.balign' and '.p2align' directives, described later, which 3312have a consistent behavior across all architectures (but are specific to 3313GAS). 3314 3315 3316File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3317 33187.4 '.altmacro' 3319=============== 3320 3321Enable alternate macro mode, enabling: 3322 3323'LOCAL NAME [ , ... ]' 3324 One additional directive, 'LOCAL', is available. It is used to 3325 generate a string replacement for each of the NAME arguments, and 3326 replace any instances of NAME in each macro expansion. The 3327 replacement string is unique in the assembly, and different for 3328 each separate macro expansion. 'LOCAL' allows you to write macros 3329 that define symbols, without fear of conflict between separate 3330 macro expansions. 3331 3332'String delimiters' 3333 You can write strings delimited in these other ways besides 3334 '"STRING"': 3335 3336 ''STRING'' 3337 You can delimit strings with single-quote characters. 3338 3339 '<STRING>' 3340 You can delimit strings with matching angle brackets. 3341 3342'single-character string escape' 3343 To include any single character literally in a string (even if the 3344 character would otherwise have some special meaning), you can 3345 prefix the character with '!' (an exclamation mark). For example, 3346 you can write '<4.3 !> 5.4!!>' to get the literal text '4.3 > 3347 5.4!'. 3348 3349'Expression results as strings' 3350 You can write '%EXPR' to evaluate the expression EXPR and use the 3351 result as a string. 3352 3353 3354File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3355 33567.5 '.ascii "STRING"'... 3357======================== 3358 3359'.ascii' expects zero or more string literals (*note Strings::) 3360separated by commas. It assembles each string (with no automatic 3361trailing zero byte) into consecutive addresses. 3362 3363 3364File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops 3365 33667.6 '.asciz "STRING"'... 3367======================== 3368 3369'.asciz' is just like '.ascii', but each string is followed by a zero 3370byte. The "z" in '.asciz' stands for "zero". 3371 3372 3373File: as.info, Node: Balign, Next: Bundle directives, Prev: Asciz, Up: Pseudo Ops 3374 33757.7 '.balign[wl] [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 3376==================================================== 3377 3378Pad the location counter (in the current subsection) to a particular 3379storage boundary. The first expression (which must be absolute) is the 3380alignment request in bytes. For example '.balign 8' advances the 3381location counter until it is a multiple of 8. If the location counter 3382is already a multiple of 8, no change is needed. If the expression is 3383omitted then a default value of 0 is used, effectively disabling 3384alignment requirements. 3385 3386 The second expression (also absolute) gives the fill value to be 3387stored in the padding bytes. It (and the comma) may be omitted. If it 3388is omitted, the padding bytes are normally zero. However, on most 3389systems, if the section is marked as containing code and the fill value 3390is omitted, the space is filled with no-op instructions. 3391 3392 The third expression is also absolute, and is also optional. If it 3393is present, it is the maximum number of bytes that should be skipped by 3394this alignment directive. If doing the alignment would require skipping 3395more bytes than the specified maximum, then the alignment is not done at 3396all. You can omit the fill value (the second argument) entirely by 3397simply using two commas after the required alignment; this can be useful 3398if you want the alignment to be filled with no-op instructions when 3399appropriate. 3400 3401 The '.balignw' and '.balignl' directives are variants of the 3402'.balign' directive. The '.balignw' directive treats the fill pattern 3403as a two byte word value. The '.balignl' directives treats the fill 3404pattern as a four byte longword value. For example, '.balignw 4,0x368d' 3405will align to a multiple of 4. If it skips two bytes, they will be 3406filled in with the value 0x368d (the exact placement of the bytes 3407depends upon the endianness of the processor). If it skips 1 or 3 3408bytes, the fill value is undefined. 3409 3410 3411File: as.info, Node: Bundle directives, Next: Byte, Prev: Balign, Up: Pseudo Ops 3412 34137.8 Bundle directives 3414===================== 3415 34167.8.1 '.bundle_align_mode ABS-EXPR' 3417----------------------------------- 3418 3419'.bundle_align_mode' enables or disables "aligned instruction bundle" 3420mode. In this mode, sequences of adjacent instructions are grouped into 3421fixed-sized "bundles". If the argument is zero, this mode is disabled 3422(which is the default state). If the argument it not zero, it gives the 3423size of an instruction bundle as a power of two (as for the '.p2align' 3424directive, *note P2align::). 3425 3426 For some targets, it's an ABI requirement that no instruction may 3427span a certain aligned boundary. A "bundle" is simply a sequence of 3428instructions that starts on an aligned boundary. For example, if 3429ABS-EXPR is '5' then the bundle size is 32, so each aligned chunk of 32 3430bytes is a bundle. When aligned instruction bundle mode is in effect, 3431no single instruction may span a boundary between bundles. If an 3432instruction would start too close to the end of a bundle for the length 3433of that particular instruction to fit within the bundle, then the space 3434at the end of that bundle is filled with no-op instructions so the 3435instruction starts in the next bundle. As a corollary, it's an error if 3436any single instruction's encoding is longer than the bundle size. 3437 34387.8.2 '.bundle_lock' and '.bundle_unlock' 3439----------------------------------------- 3440 3441The '.bundle_lock' and directive '.bundle_unlock' directives allow 3442explicit control over instruction bundle padding. These directives are 3443only valid when '.bundle_align_mode' has been used to enable aligned 3444instruction bundle mode. It's an error if they appear when 3445'.bundle_align_mode' has not been used at all, or when the last 3446directive was '.bundle_align_mode 0'. 3447 3448 For some targets, it's an ABI requirement that certain instructions 3449may appear only as part of specified permissible sequences of multiple 3450instructions, all within the same bundle. A pair of '.bundle_lock' and 3451'.bundle_unlock' directives define a "bundle-locked" instruction 3452sequence. For purposes of aligned instruction bundle mode, a sequence 3453starting with '.bundle_lock' and ending with '.bundle_unlock' is treated 3454as a single instruction. That is, the entire sequence must fit into a 3455single bundle and may not span a bundle boundary. If necessary, no-op 3456instructions will be inserted before the first instruction of the 3457sequence so that the whole sequence starts on an aligned bundle 3458boundary. It's an error if the sequence is longer than the bundle size. 3459 3460 For convenience when using '.bundle_lock' and '.bundle_unlock' inside 3461assembler macros (*note Macro::), bundle-locked sequences may be nested. 3462That is, a second '.bundle_lock' directive before the next 3463'.bundle_unlock' directive has no effect except that it must be matched 3464by another closing '.bundle_unlock' so that there is the same number of 3465'.bundle_lock' and '.bundle_unlock' directives. 3466 3467 3468File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops 3469 34707.9 '.byte EXPRESSIONS' 3471======================= 3472 3473'.byte' expects zero or more expressions, separated by commas. Each 3474expression is assembled into the next byte. 3475 3476 3477File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3478 34797.10 CFI directives 3480=================== 3481 34827.10.1 '.cfi_sections SECTION_LIST' 3483----------------------------------- 3484 3485'.cfi_sections' may be used to specify whether CFI directives should 3486emit '.eh_frame' section and/or '.debug_frame' section. If SECTION_LIST 3487is '.eh_frame', '.eh_frame' is emitted, if SECTION_LIST is 3488'.debug_frame', '.debug_frame' is emitted. To emit both use '.eh_frame, 3489.debug_frame'. The default if this directive is not used is 3490'.cfi_sections .eh_frame'. 3491 3492 On targets that support compact unwinding tables these can be 3493generated by specifying '.eh_frame_entry' instead of '.eh_frame'. 3494 3495 Some targets may support an additional name, such as '.c6xabi.exidx' 3496which is used by the target. 3497 3498 The '.cfi_sections' directive can be repeated, with the same or 3499different arguments, provided that CFI generation has not yet started. 3500Once CFI generation has started however the section list is fixed and 3501any attempts to redefine it will result in an error. 3502 35037.10.2 '.cfi_startproc [simple]' 3504-------------------------------- 3505 3506'.cfi_startproc' is used at the beginning of each function that should 3507have an entry in '.eh_frame'. It initializes some internal data 3508structures. Don't forget to close the function by '.cfi_endproc'. 3509 3510 Unless '.cfi_startproc' is used along with parameter 'simple' it also 3511emits some architecture dependent initial CFI instructions. 3512 35137.10.3 '.cfi_endproc' 3514--------------------- 3515 3516'.cfi_endproc' is used at the end of a function where it closes its 3517unwind entry previously opened by '.cfi_startproc', and emits it to 3518'.eh_frame'. 3519 35207.10.4 '.cfi_personality ENCODING [, EXP]' 3521------------------------------------------ 3522 3523'.cfi_personality' defines personality routine and its encoding. 3524ENCODING must be a constant determining how the personality should be 3525encoded. If it is 255 ('DW_EH_PE_omit'), second argument is not 3526present, otherwise second argument should be a constant or a symbol 3527name. When using indirect encodings, the symbol provided should be the 3528location where personality can be loaded from, not the personality 3529routine itself. The default after '.cfi_startproc' is '.cfi_personality 35300xff', no personality routine. 3531 35327.10.5 '.cfi_personality_id ID' 3533------------------------------- 3534 3535'cfi_personality_id' defines a personality routine by its index as 3536defined in a compact unwinding format. Only valid when generating 3537compact EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3538 35397.10.6 '.cfi_fde_data [OPCODE1 [, ...]]' 3540---------------------------------------- 3541 3542'cfi_fde_data' is used to describe the compact unwind opcodes to be used 3543for the current function. These are emitted inline in the 3544'.eh_frame_entry' section if small enough and there is no LSDA, or in 3545the '.gnu.extab' section otherwise. Only valid when generating compact 3546EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3547 35487.10.7 '.cfi_lsda ENCODING [, EXP]' 3549----------------------------------- 3550 3551'.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant 3552determining how the LSDA should be encoded. If it is 255 3553('DW_EH_PE_omit'), the second argument is not present, otherwise the 3554second argument should be a constant or a symbol name. The default 3555after '.cfi_startproc' is '.cfi_lsda 0xff', meaning that no LSDA is 3556present. 3557 35587.10.8 '.cfi_inline_lsda' [ALIGN] 3559--------------------------------- 3560 3561'.cfi_inline_lsda' marks the start of a LSDA data section and switches 3562to the corresponding '.gnu.extab' section. Must be preceded by a CFI 3563block containing a '.cfi_lsda' directive. Only valid when generating 3564compact EH frames (i.e. with '.cfi_sections eh_frame_entry'. 3565 3566 The table header and unwinding opcodes will be generated at this 3567point, so that they are immediately followed by the LSDA data. The 3568symbol referenced by the '.cfi_lsda' directive should still be defined 3569in case a fallback FDE based encoding is used. The LSDA data is 3570terminated by a section directive. 3571 3572 The optional ALIGN argument specifies the alignment required. The 3573alignment is specified as a power of two, as with the '.p2align' 3574directive. 3575 35767.10.9 '.cfi_def_cfa REGISTER, OFFSET' 3577-------------------------------------- 3578 3579'.cfi_def_cfa' defines a rule for computing CFA as: take address from 3580REGISTER and add OFFSET to it. 3581 35827.10.10 '.cfi_def_cfa_register REGISTER' 3583---------------------------------------- 3584 3585'.cfi_def_cfa_register' modifies a rule for computing CFA. From now on 3586REGISTER will be used instead of the old one. Offset remains the same. 3587 35887.10.11 '.cfi_def_cfa_offset OFFSET' 3589------------------------------------ 3590 3591'.cfi_def_cfa_offset' modifies a rule for computing CFA. Register 3592remains the same, but OFFSET is new. Note that it is the absolute 3593offset that will be added to a defined register to compute CFA address. 3594 35957.10.12 '.cfi_adjust_cfa_offset OFFSET' 3596--------------------------------------- 3597 3598Same as '.cfi_def_cfa_offset' but OFFSET is a relative value that is 3599added/subtracted from the previous offset. 3600 36017.10.13 '.cfi_offset REGISTER, OFFSET' 3602-------------------------------------- 3603 3604Previous value of REGISTER is saved at offset OFFSET from CFA. 3605 36067.10.14 '.cfi_val_offset REGISTER, OFFSET' 3607------------------------------------------ 3608 3609Previous value of REGISTER is CFA + OFFSET. 3610 36117.10.15 '.cfi_rel_offset REGISTER, OFFSET' 3612------------------------------------------ 3613 3614Previous value of REGISTER is saved at offset OFFSET from the current 3615CFA register. This is transformed to '.cfi_offset' using the known 3616displacement of the CFA register from the CFA. This is often easier to 3617use, because the number will match the code it's annotating. 3618 36197.10.16 '.cfi_register REGISTER1, REGISTER2' 3620-------------------------------------------- 3621 3622Previous value of REGISTER1 is saved in register REGISTER2. 3623 36247.10.17 '.cfi_restore REGISTER' 3625------------------------------- 3626 3627'.cfi_restore' says that the rule for REGISTER is now the same as it was 3628at the beginning of the function, after all initial instruction added by 3629'.cfi_startproc' were executed. 3630 36317.10.18 '.cfi_undefined REGISTER' 3632--------------------------------- 3633 3634From now on the previous value of REGISTER can't be restored anymore. 3635 36367.10.19 '.cfi_same_value REGISTER' 3637---------------------------------- 3638 3639Current value of REGISTER is the same like in the previous frame, i.e. 3640no restoration needed. 3641 36427.10.20 '.cfi_remember_state' and '.cfi_restore_state' 3643------------------------------------------------------ 3644 3645'.cfi_remember_state' pushes the set of rules for every register onto an 3646implicit stack, while '.cfi_restore_state' pops them off the stack and 3647places them in the current row. This is useful for situations where you 3648have multiple '.cfi_*' directives that need to be undone due to the 3649control flow of the program. For example, we could have something like 3650this (assuming the CFA is the value of 'rbp'): 3651 3652 je label 3653 popq %rbx 3654 .cfi_restore %rbx 3655 popq %r12 3656 .cfi_restore %r12 3657 popq %rbp 3658 .cfi_restore %rbp 3659 .cfi_def_cfa %rsp, 8 3660 ret 3661 label: 3662 /* Do something else */ 3663 3664 Here, we want the '.cfi' directives to affect only the rows 3665corresponding to the instructions before 'label'. This means we'd have 3666to add multiple '.cfi' directives after 'label' to recreate the original 3667save locations of the registers, as well as setting the CFA back to the 3668value of 'rbp'. This would be clumsy, and result in a larger binary 3669size. Instead, we can write: 3670 3671 je label 3672 popq %rbx 3673 .cfi_remember_state 3674 .cfi_restore %rbx 3675 popq %r12 3676 .cfi_restore %r12 3677 popq %rbp 3678 .cfi_restore %rbp 3679 .cfi_def_cfa %rsp, 8 3680 ret 3681 label: 3682 .cfi_restore_state 3683 /* Do something else */ 3684 3685 That way, the rules for the instructions after 'label' will be the 3686same as before the first '.cfi_restore' without having to use multiple 3687'.cfi' directives. 3688 36897.10.21 '.cfi_return_column REGISTER' 3690------------------------------------- 3691 3692Change return column REGISTER, i.e. the return address is either 3693directly in REGISTER or can be accessed by rules for REGISTER. 3694 36957.10.22 '.cfi_signal_frame' 3696--------------------------- 3697 3698Mark current function as signal trampoline. 3699 37007.10.23 '.cfi_window_save' 3701-------------------------- 3702 3703SPARC register window has been saved. 3704 37057.10.24 '.cfi_escape' EXPRESSION[, ...] 3706--------------------------------------- 3707 3708Allows the user to add arbitrary bytes to the unwind info. One might 3709use this to add OS-specific CFI opcodes, or generic CFI opcodes that GAS 3710does not yet support. 3711 37127.10.25 '.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' 3713--------------------------------------------------------- 3714 3715The current value of REGISTER is LABEL. The value of LABEL will be 3716encoded in the output file according to ENCODING; see the description of 3717'.cfi_personality' for details on this encoding. 3718 3719 The usefulness of equating a register to a fixed label is probably 3720limited to the return address register. Here, it can be useful to mark 3721a code segment that has only one return address which is reached by a 3722direct branch and no copy of the return address exists in memory or 3723another register. 3724 3725 3726File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3727 37287.11 '.comm SYMBOL , LENGTH ' 3729============================= 3730 3731'.comm' declares a common symbol named SYMBOL. When linking, a common 3732symbol in one object file may be merged with a defined or common symbol 3733of the same name in another object file. If 'ld' does not see a 3734definition for the symbol-just one or more common symbols-then it will 3735allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3736absolute expression. If 'ld' sees multiple common symbols with the same 3737name, and they do not all have the same size, it will allocate space 3738using the largest size. 3739 3740 When using ELF or (as a GNU extension) PE, the '.comm' directive 3741takes an optional third argument. This is the desired alignment of the 3742symbol, specified for ELF as a byte boundary (for example, an alignment 3743of 16 means that the least significant 4 bits of the address should be 3744zero), and for PE as a power of two (for example, an alignment of 5 3745means aligned to a 32-byte boundary). The alignment must be an absolute 3746expression, and it must be a power of two. If 'ld' allocates 3747uninitialized memory for the common symbol, it will use the alignment 3748when placing the symbol. If no alignment is specified, 'as' will set 3749the alignment to the largest power of two less than or equal to the size 3750of the symbol, up to a maximum of 16 on ELF, or the default section 3751alignment of 4 on PE(1). 3752 3753 The syntax for '.comm' differs slightly on the HPPA. The syntax is 3754'SYMBOL .comm, LENGTH'; SYMBOL is optional. 3755 3756 ---------- Footnotes ---------- 3757 3758 (1) This is not the same as the executable image file alignment 3759controlled by 'ld''s '--section-alignment' option; image file sections 3760in PE are aligned to multiples of 4096, which is far too large an 3761alignment for ordinary variables. It is rather the default alignment 3762for (non-debug) sections within object ('*.o') files, which are less 3763strictly aligned. 3764 3765 3766File: as.info, Node: Data, Next: Dc, Prev: Comm, Up: Pseudo Ops 3767 37687.12 '.data SUBSECTION' 3769======================= 3770 3771'.data' tells 'as' to assemble the following statements onto the end of 3772the data subsection numbered SUBSECTION (which is an absolute 3773expression). If SUBSECTION is omitted, it defaults to zero. 3774 3775 3776File: as.info, Node: Dc, Next: Dcb, Prev: Data, Up: Pseudo Ops 3777 37787.13 '.dc[SIZE] EXPRESSIONS' 3779============================ 3780 3781The '.dc' directive expects zero or more EXPRESSIONS separated by 3782commas. These expressions are evaluated and their values inserted into 3783the current section. The size of the emitted value depends upon the 3784suffix to the '.dc' directive: 3785 3786''.a'' 3787 Emits N-bit values, where N is the size of an address on the target 3788 system. 3789''.b'' 3790 Emits 8-bit values. 3791''.d'' 3792 Emits double precision floating-point values. 3793''.l'' 3794 Emits 32-bit values. 3795''.s'' 3796 Emits single precision floating-point values. 3797''.w'' 3798 Emits 16-bit values. Note - this is true even on targets where the 3799 '.word' directive would emit 32-bit values. 3800''.x'' 3801 Emits long double precision floating-point values. 3802 3803 If no suffix is used then '.w' is assumed. 3804 3805 The byte ordering is target dependent, as is the size and format of 3806floating point values. 3807 3808 3809File: as.info, Node: Dcb, Next: Ds, Prev: Dc, Up: Pseudo Ops 3810 38117.14 '.dcb[SIZE] NUMBER [,FILL]' 3812================================ 3813 3814This directive emits NUMBER copies of FILL, each of SIZE bytes. Both 3815NUMBER and FILL are absolute expressions. If the comma and FILL are 3816omitted, FILL is assumed to be zero. The SIZE suffix, if present, must 3817be one of: 3818 3819''.b'' 3820 Emits single byte values. 3821''.d'' 3822 Emits double-precision floating point values. 3823''.l'' 3824 Emits 4-byte values. 3825''.s'' 3826 Emits single-precision floating point values. 3827''.w'' 3828 Emits 2-byte values. 3829''.x'' 3830 Emits long double-precision floating point values. 3831 3832 If the SIZE suffix is omitted then '.w' is assumed. 3833 3834 The byte ordering is target dependent, as is the size and format of 3835floating point values. 3836 3837 3838File: as.info, Node: Ds, Next: Def, Prev: Dcb, Up: Pseudo Ops 3839 38407.15 '.ds[SIZE] NUMBER [,FILL]' 3841=============================== 3842 3843This directive emits NUMBER copies of FILL, each of SIZE bytes. Both 3844NUMBER and FILL are absolute expressions. If the comma and FILL are 3845omitted, FILL is assumed to be zero. The SIZE suffix, if present, must 3846be one of: 3847 3848''.b'' 3849 Emits single byte values. 3850''.d'' 3851 Emits 8-byte values. 3852''.l'' 3853 Emits 4-byte values. 3854''.p'' 3855 Emits 12-byte values. 3856''.s'' 3857 Emits 4-byte values. 3858''.w'' 3859 Emits 2-byte values. 3860''.x'' 3861 Emits 12-byte values. 3862 3863 Note - unlike the '.dcb' directive the '.d', '.s' and '.x' suffixes 3864do not indicate that floating-point values are to be inserted. 3865 3866 If the SIZE suffix is omitted then '.w' is assumed. 3867 3868 The byte ordering is target dependent. 3869 3870 3871File: as.info, Node: Def, Next: Desc, Prev: Ds, Up: Pseudo Ops 3872 38737.16 '.def NAME' 3874================ 3875 3876Begin defining debugging information for a symbol NAME; the definition 3877extends until the '.endef' directive is encountered. 3878 3879 3880File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 3881 38827.17 '.desc SYMBOL, ABS-EXPRESSION' 3883=================================== 3884 3885This directive sets the descriptor of the symbol (*note Symbol 3886Attributes::) to the low 16 bits of an absolute expression. 3887 3888 The '.desc' directive is not available when 'as' is configured for 3889COFF output; it is only for 'a.out' or 'b.out' object format. For the 3890sake of compatibility, 'as' accepts it, but produces no output, when 3891configured for COFF. 3892 3893 3894File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 3895 38967.18 '.dim' 3897=========== 3898 3899This directive is generated by compilers to include auxiliary debugging 3900information in the symbol table. It is only permitted inside 3901'.def'/'.endef' pairs. 3902 3903 3904File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 3905 39067.19 '.double FLONUMS' 3907====================== 3908 3909'.double' expects zero or more flonums, separated by commas. It 3910assembles floating point numbers. The exact kind of floating point 3911numbers emitted depends on how 'as' is configured. *Note Machine 3912Dependencies::. 3913 3914 3915File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 3916 39177.20 '.eject' 3918============= 3919 3920Force a page break at this point, when generating assembly listings. 3921 3922 3923File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 3924 39257.21 '.else' 3926============ 3927 3928'.else' is part of the 'as' support for conditional assembly; see *note 3929'.if': If. It marks the beginning of a section of code to be assembled 3930if the condition for the preceding '.if' was false. 3931 3932 3933File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 3934 39357.22 '.elseif' 3936============== 3937 3938'.elseif' is part of the 'as' support for conditional assembly; see 3939*note '.if': If. It is shorthand for beginning a new '.if' block that 3940would otherwise fill the entire '.else' section. 3941 3942 3943File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 3944 39457.23 '.end' 3946=========== 3947 3948'.end' marks the end of the assembly file. 'as' does not process 3949anything in the file past the '.end' directive. 3950 3951 3952File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 3953 39547.24 '.endef' 3955============= 3956 3957This directive flags the end of a symbol definition begun with '.def'. 3958 3959 3960File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 3961 39627.25 '.endfunc' 3963=============== 3964 3965'.endfunc' marks the end of a function specified with '.func'. 3966 3967 3968File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 3969 39707.26 '.endif' 3971============= 3972 3973'.endif' is part of the 'as' support for conditional assembly; it marks 3974the end of a block of code that is only assembled conditionally. *Note 3975'.if': If. 3976 3977 3978File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 3979 39807.27 '.equ SYMBOL, EXPRESSION' 3981============================== 3982 3983This directive sets the value of SYMBOL to EXPRESSION. It is synonymous 3984with '.set'; see *note '.set': Set. 3985 3986 The syntax for 'equ' on the HPPA is 'SYMBOL .equ EXPRESSION'. 3987 3988 The syntax for 'equ' on the Z80 is 'SYMBOL equ EXPRESSION'. On the 3989Z80 it is an error if SYMBOL is already defined, but the symbol is not 3990protected from later redefinition. Compare *note Equiv::. 3991 3992 3993File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 3994 39957.28 '.equiv SYMBOL, EXPRESSION' 3996================================ 3997 3998The '.equiv' directive is like '.equ' and '.set', except that the 3999assembler will signal an error if SYMBOL is already defined. Note a 4000symbol which has been referenced but not actually defined is considered 4001to be undefined. 4002 4003 Except for the contents of the error message, this is roughly 4004equivalent to 4005 .ifdef SYM 4006 .err 4007 .endif 4008 .equ SYM,VAL 4009 plus it protects the symbol from later redefinition. 4010 4011 4012File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 4013 40147.29 '.eqv SYMBOL, EXPRESSION' 4015============================== 4016 4017The '.eqv' directive is like '.equiv', but no attempt is made to 4018evaluate the expression or any part of it immediately. Instead each 4019time the resulting symbol is used in an expression, a snapshot of its 4020current value is taken. 4021 4022 4023File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 4024 40257.30 '.err' 4026=========== 4027 4028If 'as' assembles a '.err' directive, it will print an error message 4029and, unless the '-Z' option was used, it will not generate an object 4030file. This can be used to signal an error in conditionally compiled 4031code. 4032 4033 4034File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 4035 40367.31 '.error "STRING"' 4037====================== 4038 4039Similarly to '.err', this directive emits an error, but you can specify 4040a string that will be emitted as the error message. If you don't 4041specify the message, it defaults to '".error directive invoked in source 4042file"'. *Note Error and Warning Messages: Errors. 4043 4044 .error "This code has not been assembled and tested." 4045 4046 4047File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 4048 40497.32 '.exitm' 4050============= 4051 4052Exit early from the current macro definition. *Note Macro::. 4053 4054 4055File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 4056 40577.33 '.extern' 4058============== 4059 4060'.extern' is accepted in the source program--for compatibility with 4061other assemblers--but it is ignored. 'as' treats all undefined symbols 4062as external. 4063 4064 4065File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 4066 40677.34 '.fail EXPRESSION' 4068======================= 4069 4070Generates an error or a warning. If the value of the EXPRESSION is 500 4071or more, 'as' will print a warning message. If the value is less than 4072500, 'as' will print an error message. The message will include the 4073value of EXPRESSION. This can occasionally be useful inside complex 4074nested macros or conditional assembly. 4075 4076 4077File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 4078 40797.35 '.file' 4080============ 4081 4082There are two different versions of the '.file' directive. Targets that 4083support DWARF2 line number information use the DWARF2 version of 4084'.file'. Other targets use the default version. 4085 4086Default Version 4087--------------- 4088 4089This version of the '.file' directive tells 'as' that we are about to 4090start a new logical file. The syntax is: 4091 4092 .file STRING 4093 4094 STRING is the new file name. In general, the filename is recognized 4095whether or not it is surrounded by quotes '"'; but if you wish to 4096specify an empty file name, you must give the quotes-'""'. This 4097statement may go away in future: it is only recognized to be compatible 4098with old 'as' programs. 4099 4100DWARF2 Version 4101-------------- 4102 4103When emitting DWARF2 line number information, '.file' assigns filenames 4104to the '.debug_line' file name table. The syntax is: 4105 4106 .file FILENO FILENAME 4107 4108 The FILENO operand should be a unique positive integer to use as the 4109index of the entry in the table. The FILENAME operand is a C string 4110literal. 4111 4112 The detail of filename indices is exposed to the user because the 4113filename table is shared with the '.debug_info' section of the DWARF2 4114debugging information, and thus the user must know the exact indices 4115that table entries will have. 4116 4117 4118File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 4119 41207.36 '.fill REPEAT , SIZE , VALUE' 4121================================== 4122 4123REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 4124copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 4125more, but if it is more than 8, then it is deemed to have the value 8, 4126compatible with other people's assemblers. The contents of each REPEAT 4127bytes is taken from an 8-byte number. The highest order 4 bytes are 4128zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 4129an integer on the computer 'as' is assembling for. Each SIZE bytes in a 4130repetition is taken from the lowest order SIZE bytes of this number. 4131Again, this bizarre behavior is compatible with other people's 4132assemblers. 4133 4134 SIZE and VALUE are optional. If the second comma and VALUE are 4135absent, VALUE is assumed zero. If the first comma and following tokens 4136are absent, SIZE is assumed to be 1. 4137 4138 4139File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 4140 41417.37 '.float FLONUMS' 4142===================== 4143 4144This directive assembles zero or more flonums, separated by commas. It 4145has the same effect as '.single'. The exact kind of floating point 4146numbers emitted depends on how 'as' is configured. *Note Machine 4147Dependencies::. 4148 4149 4150File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 4151 41527.38 '.func NAME[,LABEL]' 4153========================= 4154 4155'.func' emits debugging information to denote function NAME, and is 4156ignored unless the file is assembled with debugging enabled. Only 4157'--gstabs[+]' is currently supported. LABEL is the entry point of the 4158function and if omitted NAME prepended with the 'leading char' is used. 4159'leading char' is usually '_' or nothing, depending on the target. All 4160functions are currently defined to have 'void' return type. The 4161function must be terminated with '.endfunc'. 4162 4163 4164File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 4165 41667.39 '.global SYMBOL', '.globl SYMBOL' 4167====================================== 4168 4169'.global' makes the symbol visible to 'ld'. If you define SYMBOL in 4170your partial program, its value is made available to other partial 4171programs that are linked with it. Otherwise, SYMBOL takes its 4172attributes from a symbol of the same name from another file linked into 4173the same program. 4174 4175 Both spellings ('.globl' and '.global') are accepted, for 4176compatibility with other assemblers. 4177 4178 On the HPPA, '.global' is not always enough to make it accessible to 4179other partial programs. You may need the HPPA-only '.EXPORT' directive 4180as well. *Note HPPA Assembler Directives: HPPA Directives. 4181 4182 4183File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 4184 41857.40 '.gnu_attribute TAG,VALUE' 4186=============================== 4187 4188Record a GNU object attribute for this file. *Note Object Attributes::. 4189 4190 4191File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 4192 41937.41 '.hidden NAMES' 4194==================== 4195 4196This is one of the ELF visibility directives. The other two are 4197'.internal' (*note '.internal': Internal.) and '.protected' (*note 4198'.protected': Protected.). 4199 4200 This directive overrides the named symbols default visibility (which 4201is set by their binding: local, global or weak). The directive sets the 4202visibility to 'hidden' which means that the symbols are not visible to 4203other components. Such symbols are always considered to be 'protected' 4204as well. 4205 4206 4207File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 4208 42097.42 '.hword EXPRESSIONS' 4210========================= 4211 4212This expects zero or more EXPRESSIONS, and emits a 16 bit number for 4213each. 4214 4215 This directive is a synonym for '.short'; depending on the target 4216architecture, it may also be a synonym for '.word'. 4217 4218 4219File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 4220 42217.43 '.ident' 4222============= 4223 4224This directive is used by some assemblers to place tags in object files. 4225The behavior of this directive varies depending on the target. When 4226using the a.out object file format, 'as' simply accepts the directive 4227for source-file compatibility with existing assemblers, but does not 4228emit anything for it. When using COFF, comments are emitted to the 4229'.comment' or '.rdata' section, depending on the target. When using 4230ELF, comments are emitted to the '.comment' section. 4231 4232 4233File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 4234 42357.44 '.if ABSOLUTE EXPRESSION' 4236============================== 4237 4238'.if' marks the beginning of a section of code which is only considered 4239part of the source program being assembled if the argument (which must 4240be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 4241section of code must be marked by '.endif' (*note '.endif': Endif.); 4242optionally, you may include code for the alternative condition, flagged 4243by '.else' (*note '.else': Else.). If you have several conditions to 4244check, '.elseif' may be used to avoid nesting blocks if/else within each 4245subsequent '.else' block. 4246 4247 The following variants of '.if' are also supported: 4248'.ifdef SYMBOL' 4249 Assembles the following section of code if the specified SYMBOL has 4250 been defined. Note a symbol which has been referenced but not yet 4251 defined is considered to be undefined. 4252 4253'.ifb TEXT' 4254 Assembles the following section of code if the operand is blank 4255 (empty). 4256 4257'.ifc STRING1,STRING2' 4258 Assembles the following section of code if the two strings are the 4259 same. The strings may be optionally quoted with single quotes. If 4260 they are not quoted, the first string stops at the first comma, and 4261 the second string stops at the end of the line. Strings which 4262 contain whitespace should be quoted. The string comparison is case 4263 sensitive. 4264 4265'.ifeq ABSOLUTE EXPRESSION' 4266 Assembles the following section of code if the argument is zero. 4267 4268'.ifeqs STRING1,STRING2' 4269 Another form of '.ifc'. The strings must be quoted using double 4270 quotes. 4271 4272'.ifge ABSOLUTE EXPRESSION' 4273 Assembles the following section of code if the argument is greater 4274 than or equal to zero. 4275 4276'.ifgt ABSOLUTE EXPRESSION' 4277 Assembles the following section of code if the argument is greater 4278 than zero. 4279 4280'.ifle ABSOLUTE EXPRESSION' 4281 Assembles the following section of code if the argument is less 4282 than or equal to zero. 4283 4284'.iflt ABSOLUTE EXPRESSION' 4285 Assembles the following section of code if the argument is less 4286 than zero. 4287 4288'.ifnb TEXT' 4289 Like '.ifb', but the sense of the test is reversed: this assembles 4290 the following section of code if the operand is non-blank 4291 (non-empty). 4292 4293'.ifnc STRING1,STRING2.' 4294 Like '.ifc', but the sense of the test is reversed: this assembles 4295 the following section of code if the two strings are not the same. 4296 4297'.ifndef SYMBOL' 4298'.ifnotdef SYMBOL' 4299 Assembles the following section of code if the specified SYMBOL has 4300 not been defined. Both spelling variants are equivalent. Note a 4301 symbol which has been referenced but not yet defined is considered 4302 to be undefined. 4303 4304'.ifne ABSOLUTE EXPRESSION' 4305 Assembles the following section of code if the argument is not 4306 equal to zero (in other words, this is equivalent to '.if'). 4307 4308'.ifnes STRING1,STRING2' 4309 Like '.ifeqs', but the sense of the test is reversed: this 4310 assembles the following section of code if the two strings are not 4311 the same. 4312 4313 4314File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 4315 43167.45 '.incbin "FILE"[,SKIP[,COUNT]]' 4317==================================== 4318 4319The 'incbin' directive includes FILE verbatim at the current location. 4320You can control the search paths used with the '-I' command-line option 4321(*note Command-Line Options: Invoking.). Quotation marks are required 4322around FILE. 4323 4324 The SKIP argument skips a number of bytes from the start of the FILE. 4325The COUNT argument indicates the maximum number of bytes to read. Note 4326that the data is not aligned in any way, so it is the user's 4327responsibility to make sure that proper alignment is provided both 4328before and after the 'incbin' directive. 4329 4330 4331File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 4332 43337.46 '.include "FILE"' 4334====================== 4335 4336This directive provides a way to include supporting files at specified 4337points in your source program. The code from FILE is assembled as if it 4338followed the point of the '.include'; when the end of the included file 4339is reached, assembly of the original file continues. You can control 4340the search paths used with the '-I' command-line option (*note 4341Command-Line Options: Invoking.). Quotation marks are required around 4342FILE. 4343 4344 4345File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 4346 43477.47 '.int EXPRESSIONS' 4348======================= 4349 4350Expect zero or more EXPRESSIONS, of any section, separated by commas. 4351For each expression, emit a number that, at run time, is the value of 4352that expression. The byte order and bit size of the number depends on 4353what kind of target the assembly is for. 4354 4355 4356File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 4357 43587.48 '.internal NAMES' 4359====================== 4360 4361This is one of the ELF visibility directives. The other two are 4362'.hidden' (*note '.hidden': Hidden.) and '.protected' (*note 4363'.protected': Protected.). 4364 4365 This directive overrides the named symbols default visibility (which 4366is set by their binding: local, global or weak). The directive sets the 4367visibility to 'internal' which means that the symbols are considered to 4368be 'hidden' (i.e., not visible to other components), and that some 4369extra, processor specific processing must also be performed upon the 4370symbols as well. 4371 4372 4373File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 4374 43757.49 '.irp SYMBOL,VALUES'... 4376============================ 4377 4378Evaluate a sequence of statements assigning different values to SYMBOL. 4379The sequence of statements starts at the '.irp' directive, and is 4380terminated by an '.endr' directive. For each VALUE, SYMBOL is set to 4381VALUE, and the sequence of statements is assembled. If no VALUE is 4382listed, the sequence of statements is assembled once, with SYMBOL set to 4383the null string. To refer to SYMBOL within the sequence of statements, 4384use \SYMBOL. 4385 4386 For example, assembling 4387 4388 .irp param,1,2,3 4389 move d\param,sp@- 4390 .endr 4391 4392 is equivalent to assembling 4393 4394 move d1,sp@- 4395 move d2,sp@- 4396 move d3,sp@- 4397 4398 For some caveats with the spelling of SYMBOL, see also *note Macro::. 4399 4400 4401File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 4402 44037.50 '.irpc SYMBOL,VALUES'... 4404============================= 4405 4406Evaluate a sequence of statements assigning different values to SYMBOL. 4407The sequence of statements starts at the '.irpc' directive, and is 4408terminated by an '.endr' directive. For each character in VALUE, SYMBOL 4409is set to the character, and the sequence of statements is assembled. 4410If no VALUE is listed, the sequence of statements is assembled once, 4411with SYMBOL set to the null string. To refer to SYMBOL within the 4412sequence of statements, use \SYMBOL. 4413 4414 For example, assembling 4415 4416 .irpc param,123 4417 move d\param,sp@- 4418 .endr 4419 4420 is equivalent to assembling 4421 4422 move d1,sp@- 4423 move d2,sp@- 4424 move d3,sp@- 4425 4426 For some caveats with the spelling of SYMBOL, see also the discussion 4427at *Note Macro::. 4428 4429 4430File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 4431 44327.51 '.lcomm SYMBOL , LENGTH' 4433============================= 4434 4435Reserve LENGTH (an absolute expression) bytes for a local common denoted 4436by SYMBOL. The section and value of SYMBOL are those of the new local 4437common. The addresses are allocated in the bss section, so that at 4438run-time the bytes start off zeroed. SYMBOL is not declared global 4439(*note '.global': Global.), so is normally not visible to 'ld'. 4440 4441 Some targets permit a third argument to be used with '.lcomm'. This 4442argument specifies the desired alignment of the symbol in the bss 4443section. 4444 4445 The syntax for '.lcomm' differs slightly on the HPPA. The syntax is 4446'SYMBOL .lcomm, LENGTH'; SYMBOL is optional. 4447 4448 4449File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 4450 44517.52 '.lflags' 4452============== 4453 4454'as' accepts this directive, for compatibility with other assemblers, 4455but ignores it. 4456 4457 4458File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 4459 44607.53 '.line LINE-NUMBER' 4461======================== 4462 4463Change the logical line number. LINE-NUMBER must be an absolute 4464expression. The next line has that logical line number. Therefore any 4465other statements on the current line (after a statement separator 4466character) are reported as on logical line number LINE-NUMBER - 1. One 4467day 'as' will no longer support this directive: it is recognized only 4468for compatibility with existing assembler programs. 4469 4470 Even though this is a directive associated with the 'a.out' or 4471'b.out' object-code formats, 'as' still recognizes it when producing 4472COFF output, and treats '.line' as though it were the COFF '.ln' _if_ it 4473is found outside a '.def'/'.endef' pair. 4474 4475 Inside a '.def', '.line' is, instead, one of the directives used by 4476compilers to generate auxiliary symbol information for debugging. 4477 4478 4479File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4480 44817.54 '.linkonce [TYPE]' 4482======================= 4483 4484Mark the current section so that the linker only includes a single copy 4485of it. This may be used to include the same section in several 4486different object files, but ensure that the linker will only include it 4487once in the final output file. The '.linkonce' pseudo-op must be used 4488for each instance of the section. Duplicate sections are detected based 4489on the section name, so it should be unique. 4490 4491 This directive is only supported by a few object file formats; as of 4492this writing, the only object file format which supports it is the 4493Portable Executable format used on Windows NT. 4494 4495 The TYPE argument is optional. If specified, it must be one of the 4496following strings. For example: 4497 .linkonce same_size 4498 Not all types may be supported on all object file formats. 4499 4500'discard' 4501 Silently discard duplicate sections. This is the default. 4502 4503'one_only' 4504 Warn if there are duplicate sections, but still keep only one copy. 4505 4506'same_size' 4507 Warn if any of the duplicates have different sizes. 4508 4509'same_contents' 4510 Warn if any of the duplicates do not have exactly the same 4511 contents. 4512 4513 4514File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4515 45167.55 '.list' 4517============ 4518 4519Control (in conjunction with the '.nolist' directive) whether or not 4520assembly listings are generated. These two directives maintain an 4521internal counter (which is zero initially). '.list' increments the 4522counter, and '.nolist' decrements it. Assembly listings are generated 4523whenever the counter is greater than zero. 4524 4525 By default, listings are disabled. When you enable them (with the 4526'-a' command-line option; *note Command-Line Options: Invoking.), the 4527initial value of the listing counter is one. 4528 4529 4530File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4531 45327.56 '.ln LINE-NUMBER' 4533====================== 4534 4535'.ln' is a synonym for '.line'. 4536 4537 4538File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4539 45407.57 '.loc FILENO LINENO [COLUMN] [OPTIONS]' 4541============================================ 4542 4543When emitting DWARF2 line number information, the '.loc' directive will 4544add a row to the '.debug_line' line number matrix corresponding to the 4545immediately following assembly instruction. The FILENO, LINENO, and 4546optional COLUMN arguments will be applied to the '.debug_line' state 4547machine before the row is added. 4548 4549 The OPTIONS are a sequence of the following tokens in any order: 4550 4551'basic_block' 4552 This option will set the 'basic_block' register in the 4553 '.debug_line' state machine to 'true'. 4554 4555'prologue_end' 4556 This option will set the 'prologue_end' register in the 4557 '.debug_line' state machine to 'true'. 4558 4559'epilogue_begin' 4560 This option will set the 'epilogue_begin' register in the 4561 '.debug_line' state machine to 'true'. 4562 4563'is_stmt VALUE' 4564 This option will set the 'is_stmt' register in the '.debug_line' 4565 state machine to 'value', which must be either 0 or 1. 4566 4567'isa VALUE' 4568 This directive will set the 'isa' register in the '.debug_line' 4569 state machine to VALUE, which must be an unsigned integer. 4570 4571'discriminator VALUE' 4572 This directive will set the 'discriminator' register in the 4573 '.debug_line' state machine to VALUE, which must be an unsigned 4574 integer. 4575 4576'view VALUE' 4577 This option causes a row to be added to '.debug_line' in reference 4578 to the current address (which might not be the same as that of the 4579 following assembly instruction), and to associate VALUE with the 4580 'view' register in the '.debug_line' state machine. If VALUE is a 4581 label, both the 'view' register and the label are set to the number 4582 of prior '.loc' directives at the same program location. If VALUE 4583 is the literal '0', the 'view' register is set to zero, and the 4584 assembler asserts that there aren't any prior '.loc' directives at 4585 the same program location. If VALUE is the literal '-0', the 4586 assembler arrange for the 'view' register to be reset in this row, 4587 even if there are prior '.loc' directives at the same program 4588 location. 4589 4590 4591File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4592 45937.58 '.loc_mark_labels ENABLE' 4594============================== 4595 4596When emitting DWARF2 line number information, the '.loc_mark_labels' 4597directive makes the assembler emit an entry to the '.debug_line' line 4598number matrix with the 'basic_block' register in the state machine set 4599whenever a code label is seen. The ENABLE argument should be either 1 4600or 0, to enable or disable this function respectively. 4601 4602 4603File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4604 46057.59 '.local NAMES' 4606=================== 4607 4608This directive, which is available for ELF targets, marks each symbol in 4609the comma-separated list of 'names' as a local symbol so that it will 4610not be externally visible. If the symbols do not already exist, they 4611will be created. 4612 4613 For targets where the '.lcomm' directive (*note Lcomm::) does not 4614accept an alignment argument, which is the case for most ELF targets, 4615the '.local' directive can be used in combination with '.comm' (*note 4616Comm::) to define aligned local common data. 4617 4618 4619File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4620 46217.60 '.long EXPRESSIONS' 4622======================== 4623 4624'.long' is the same as '.int'. *Note '.int': Int. 4625 4626 4627File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4628 46297.61 '.macro' 4630============= 4631 4632The commands '.macro' and '.endm' allow you to define macros that 4633generate assembly output. For example, this definition specifies a 4634macro 'sum' that puts a sequence of numbers into memory: 4635 4636 .macro sum from=0, to=5 4637 .long \from 4638 .if \to-\from 4639 sum "(\from+1)",\to 4640 .endif 4641 .endm 4642 4643With that definition, 'SUM 0,5' is equivalent to this assembly input: 4644 4645 .long 0 4646 .long 1 4647 .long 2 4648 .long 3 4649 .long 4 4650 .long 5 4651 4652'.macro MACNAME' 4653'.macro MACNAME MACARGS ...' 4654 Begin the definition of a macro called MACNAME. If your macro 4655 definition requires arguments, specify their names after the macro 4656 name, separated by commas or spaces. You can qualify the macro 4657 argument to indicate whether all invocations must specify a 4658 non-blank value (through ':'req''), or whether it takes all of the 4659 remaining arguments (through ':'vararg''). You can supply a 4660 default value for any macro argument by following the name with 4661 '=DEFLT'. You cannot define two macros with the same MACNAME 4662 unless it has been subject to the '.purgem' directive (*note 4663 Purgem::) between the two definitions. For example, these are all 4664 valid '.macro' statements: 4665 4666 '.macro comm' 4667 Begin the definition of a macro called 'comm', which takes no 4668 arguments. 4669 4670 '.macro plus1 p, p1' 4671 '.macro plus1 p p1' 4672 Either statement begins the definition of a macro called 4673 'plus1', which takes two arguments; within the macro 4674 definition, write '\p' or '\p1' to evaluate the arguments. 4675 4676 '.macro reserve_str p1=0 p2' 4677 Begin the definition of a macro called 'reserve_str', with two 4678 arguments. The first argument has a default value, but not 4679 the second. After the definition is complete, you can call 4680 the macro either as 'reserve_str A,B' (with '\p1' evaluating 4681 to A and '\p2' evaluating to B), or as 'reserve_str ,B' (with 4682 '\p1' evaluating as the default, in this case '0', and '\p2' 4683 evaluating to B). 4684 4685 '.macro m p1:req, p2=0, p3:vararg' 4686 Begin the definition of a macro called 'm', with at least 4687 three arguments. The first argument must always have a value 4688 specified, but not the second, which instead has a default 4689 value. The third formal will get assigned all remaining 4690 arguments specified at invocation time. 4691 4692 When you call a macro, you can specify the argument values 4693 either by position, or by keyword. For example, 'sum 9,17' is 4694 equivalent to 'sum to=17, from=9'. 4695 4696 Note that since each of the MACARGS can be an identifier exactly as 4697 any other one permitted by the target architecture, there may be 4698 occasional problems if the target hand-crafts special meanings to 4699 certain characters when they occur in a special position. For 4700 example, if the colon (':') is generally permitted to be part of a 4701 symbol name, but the architecture specific code special-cases it 4702 when occurring as the final character of a symbol (to denote a 4703 label), then the macro parameter replacement code will have no way 4704 of knowing that and consider the whole construct (including the 4705 colon) an identifier, and check only this identifier for being the 4706 subject to parameter substitution. So for example this macro 4707 definition: 4708 4709 .macro label l 4710 \l: 4711 .endm 4712 4713 might not work as expected. Invoking 'label foo' might not create 4714 a label called 'foo' but instead just insert the text '\l:' into 4715 the assembler source, probably generating an error about an 4716 unrecognised identifier. 4717 4718 Similarly problems might occur with the period character ('.') 4719 which is often allowed inside opcode names (and hence identifier 4720 names). So for example constructing a macro to build an opcode 4721 from a base name and a length specifier like this: 4722 4723 .macro opcode base length 4724 \base.\length 4725 .endm 4726 4727 and invoking it as 'opcode store l' will not create a 'store.l' 4728 instruction but instead generate some kind of error as the 4729 assembler tries to interpret the text '\base.\length'. 4730 4731 There are several possible ways around this problem: 4732 4733 'Insert white space' 4734 If it is possible to use white space characters then this is 4735 the simplest solution. eg: 4736 4737 .macro label l 4738 \l : 4739 .endm 4740 4741 'Use '\()'' 4742 The string '\()' can be used to separate the end of a macro 4743 argument from the following text. eg: 4744 4745 .macro opcode base length 4746 \base\().\length 4747 .endm 4748 4749 'Use the alternate macro syntax mode' 4750 In the alternative macro syntax mode the ampersand character 4751 ('&') can be used as a separator. eg: 4752 4753 .altmacro 4754 .macro label l 4755 l&: 4756 .endm 4757 4758 Note: this problem of correctly identifying string parameters to 4759 pseudo ops also applies to the identifiers used in '.irp' (*note 4760 Irp::) and '.irpc' (*note Irpc::) as well. 4761 4762'.endm' 4763 Mark the end of a macro definition. 4764 4765'.exitm' 4766 Exit early from the current macro definition. 4767 4768'\@' 4769 'as' maintains a counter of how many macros it has executed in this 4770 pseudo-variable; you can copy that number to your output with '\@', 4771 but _only within a macro definition_. 4772 4773'LOCAL NAME [ , ... ]' 4774 _Warning: 'LOCAL' is only available if you select "alternate macro 4775 syntax" with '--alternate' or '.altmacro'._ *Note '.altmacro': 4776 Altmacro. 4777 4778 4779File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4780 47817.62 '.mri VAL' 4782=============== 4783 4784If VAL is non-zero, this tells 'as' to enter MRI mode. If VAL is zero, 4785this tells 'as' to exit MRI mode. This change affects code assembled 4786until the next '.mri' directive, or until the end of the file. *Note 4787MRI mode: M. 4788 4789 4790File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4791 47927.63 '.noaltmacro' 4793================== 4794 4795Disable alternate macro mode. *Note Altmacro::. 4796 4797 4798File: as.info, Node: Nolist, Next: Nops, Prev: Noaltmacro, Up: Pseudo Ops 4799 48007.64 '.nolist' 4801============== 4802 4803Control (in conjunction with the '.list' directive) whether or not 4804assembly listings are generated. These two directives maintain an 4805internal counter (which is zero initially). '.list' increments the 4806counter, and '.nolist' decrements it. Assembly listings are generated 4807whenever the counter is greater than zero. 4808 4809 4810File: as.info, Node: Nops, Next: Octa, Prev: Nolist, Up: Pseudo Ops 4811 48127.65 '.nops SIZE[, CONTROL]' 4813============================ 4814 4815This directive emits SIZE bytes filled with no-op instructions. SIZE is 4816absolute expression, which must be a positve value. CONTROL controls 4817how no-op instructions should be generated. If the comma and CONTROL 4818are omitted, CONTROL is assumed to be zero. 4819 4820 Note: For Intel 80386 and AMD x86-64 targets, CONTROL specifies the 4821size limit of a no-op instruction. The valid values of CONTROL are 4822between 0 and 4 in 16-bit mode, between 0 and 7 when tuning for older 4823processors in 32-bit mode, between 0 and 11 in 64-bit mode or when 4824tuning for newer processors in 32-bit mode. When 0 is used, the no-op 4825instruction size limit is set to the maximum supported size. 4826 4827 4828File: as.info, Node: Octa, Next: Offset, Prev: Nops, Up: Pseudo Ops 4829 48307.66 '.octa BIGNUMS' 4831==================== 4832 4833This directive expects zero or more bignums, separated by commas. For 4834each bignum, it emits a 16-byte integer. 4835 4836 The term "octa" comes from contexts in which a "word" is two bytes; 4837hence _octa_-word for 16 bytes. 4838 4839 4840File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops 4841 48427.67 '.offset LOC' 4843================== 4844 4845Set the location counter to LOC in the absolute section. LOC must be an 4846absolute expression. This directive may be useful for defining symbols 4847with absolute values. Do not confuse it with the '.org' directive. 4848 4849 4850File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops 4851 48527.68 '.org NEW-LC , FILL' 4853========================= 4854 4855Advance the location counter of the current section to NEW-LC. NEW-LC 4856is either an absolute expression or an expression with the same section 4857as the current subsection. That is, you can't use '.org' to cross 4858sections: if NEW-LC has the wrong section, the '.org' directive is 4859ignored. To be compatible with former assemblers, if the section of 4860NEW-LC is absolute, 'as' issues a warning, then pretends the section of 4861NEW-LC is the same as the current subsection. 4862 4863 '.org' may only increase the location counter, or leave it unchanged; 4864you cannot use '.org' to move the location counter backwards. 4865 4866 Because 'as' tries to assemble programs in one pass, NEW-LC may not 4867be undefined. If you really detest this restriction we eagerly await a 4868chance to share your improved assembler. 4869 4870 Beware that the origin is relative to the start of the section, not 4871to the start of the subsection. This is compatible with other people's 4872assemblers. 4873 4874 When the location counter (of the current subsection) is advanced, 4875the intervening bytes are filled with FILL which should be an absolute 4876expression. If the comma and FILL are omitted, FILL defaults to zero. 4877 4878 4879File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 4880 48817.69 '.p2align[wl] [ABS-EXPR[, ABS-EXPR[, ABS-EXPR]]]' 4882====================================================== 4883 4884Pad the location counter (in the current subsection) to a particular 4885storage boundary. The first expression (which must be absolute) is the 4886number of low-order zero bits the location counter must have after 4887advancement. For example '.p2align 3' advances the location counter 4888until it is a multiple of 8. If the location counter is already a 4889multiple of 8, no change is needed. If the expression is omitted then a 4890default value of 0 is used, effectively disabling alignment 4891requirements. 4892 4893 The second expression (also absolute) gives the fill value to be 4894stored in the padding bytes. It (and the comma) may be omitted. If it 4895is omitted, the padding bytes are normally zero. However, on most 4896systems, if the section is marked as containing code and the fill value 4897is omitted, the space is filled with no-op instructions. 4898 4899 The third expression is also absolute, and is also optional. If it 4900is present, it is the maximum number of bytes that should be skipped by 4901this alignment directive. If doing the alignment would require skipping 4902more bytes than the specified maximum, then the alignment is not done at 4903all. You can omit the fill value (the second argument) entirely by 4904simply using two commas after the required alignment; this can be useful 4905if you want the alignment to be filled with no-op instructions when 4906appropriate. 4907 4908 The '.p2alignw' and '.p2alignl' directives are variants of the 4909'.p2align' directive. The '.p2alignw' directive treats the fill pattern 4910as a two byte word value. The '.p2alignl' directives treats the fill 4911pattern as a four byte longword value. For example, '.p2alignw 49122,0x368d' will align to a multiple of 4. If it skips two bytes, they 4913will be filled in with the value 0x368d (the exact placement of the 4914bytes depends upon the endianness of the processor). If it skips 1 or 3 4915bytes, the fill value is undefined. 4916 4917 4918File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 4919 49207.70 '.popsection' 4921================== 4922 4923This is one of the ELF section stack manipulation directives. The 4924others are '.section' (*note Section::), '.subsection' (*note 4925SubSection::), '.pushsection' (*note PushSection::), and '.previous' 4926(*note Previous::). 4927 4928 This directive replaces the current section (and subsection) with the 4929top section (and subsection) on the section stack. This section is 4930popped off the stack. 4931 4932 4933File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 4934 49357.71 '.previous' 4936================ 4937 4938This is one of the ELF section stack manipulation directives. The 4939others are '.section' (*note Section::), '.subsection' (*note 4940SubSection::), '.pushsection' (*note PushSection::), and '.popsection' 4941(*note PopSection::). 4942 4943 This directive swaps the current section (and subsection) with most 4944recently referenced section/subsection pair prior to this one. Multiple 4945'.previous' directives in a row will flip between two sections (and 4946their subsections). For example: 4947 4948 .section A 4949 .subsection 1 4950 .word 0x1234 4951 .subsection 2 4952 .word 0x5678 4953 .previous 4954 .word 0x9abc 4955 4956 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 4957subsection 2 of section A. Whilst: 4958 4959 .section A 4960 .subsection 1 4961 # Now in section A subsection 1 4962 .word 0x1234 4963 .section B 4964 .subsection 0 4965 # Now in section B subsection 0 4966 .word 0x5678 4967 .subsection 1 4968 # Now in section B subsection 1 4969 .word 0x9abc 4970 .previous 4971 # Now in section B subsection 0 4972 .word 0xdef0 4973 4974 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 0 4975of section B and 0x9abc into subsection 1 of section B. 4976 4977 In terms of the section stack, this directive swaps the current 4978section with the top section on the section stack. 4979 4980 4981File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 4982 49837.72 '.print STRING' 4984==================== 4985 4986'as' will print STRING on the standard output during assembly. You must 4987put STRING in double quotes. 4988 4989 4990File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 4991 49927.73 '.protected NAMES' 4993======================= 4994 4995This is one of the ELF visibility directives. The other two are 4996'.hidden' (*note Hidden::) and '.internal' (*note Internal::). 4997 4998 This directive overrides the named symbols default visibility (which 4999is set by their binding: local, global or weak). The directive sets the 5000visibility to 'protected' which means that any references to the symbols 5001from within the components that defines them must be resolved to the 5002definition in that component, even if a definition in another component 5003would normally preempt this. 5004 5005 5006File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 5007 50087.74 '.psize LINES , COLUMNS' 5009============================= 5010 5011Use this directive to declare the number of lines--and, optionally, the 5012number of columns--to use for each page, when generating listings. 5013 5014 If you do not use '.psize', listings use a default line-count of 60. 5015You may omit the comma and COLUMNS specification; the default width is 5016200 columns. 5017 5018 'as' generates formfeeds whenever the specified number of lines is 5019exceeded (or whenever you explicitly request one, using '.eject'). 5020 5021 If you specify LINES as '0', no formfeeds are generated save those 5022explicitly specified with '.eject'. 5023 5024 5025File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 5026 50277.75 '.purgem NAME' 5028=================== 5029 5030Undefine the macro NAME, so that later uses of the string will not be 5031expanded. *Note Macro::. 5032 5033 5034File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 5035 50367.76 '.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' 5037======================================================================== 5038 5039This is one of the ELF section stack manipulation directives. The 5040others are '.section' (*note Section::), '.subsection' (*note 5041SubSection::), '.popsection' (*note PopSection::), and '.previous' 5042(*note Previous::). 5043 5044 This directive pushes the current section (and subsection) onto the 5045top of the section stack, and then replaces the current section and 5046subsection with 'name' and 'subsection'. The optional 'flags', 'type' 5047and 'arguments' are treated the same as in the '.section' (*note 5048Section::) directive. 5049 5050 5051File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 5052 50537.77 '.quad BIGNUMS' 5054==================== 5055 5056'.quad' expects zero or more bignums, separated by commas. For each 5057bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes, 5058it prints a warning message; and just takes the lowest order 8 bytes of 5059the bignum. 5060 5061 The term "quad" comes from contexts in which a "word" is two bytes; 5062hence _quad_-word for 8 bytes. 5063 5064 5065File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 5066 50677.78 '.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 5068============================================== 5069 5070Generate a relocation at OFFSET of type RELOC_NAME with value 5071EXPRESSION. If OFFSET is a number, the relocation is generated in the 5072current section. If OFFSET is an expression that resolves to a symbol 5073plus offset, the relocation is generated in the given symbol's section. 5074EXPRESSION, if present, must resolve to a symbol plus addend or to an 5075absolute value, but note that not all targets support an addend. e.g. 5076ELF REL targets such as i386 store an addend in the section contents 5077rather than in the relocation. This low level interface does not 5078support addends stored in the section. 5079 5080 5081File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 5082 50837.79 '.rept COUNT' 5084================== 5085 5086Repeat the sequence of lines between the '.rept' directive and the next 5087'.endr' directive COUNT times. 5088 5089 For example, assembling 5090 5091 .rept 3 5092 .long 0 5093 .endr 5094 5095 is equivalent to assembling 5096 5097 .long 0 5098 .long 0 5099 .long 0 5100 5101 A count of zero is allowed, but nothing is generated. Negative 5102counts are not allowed and if encountered will be treated as if they 5103were zero. 5104 5105 5106File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 5107 51087.80 '.sbttl "SUBHEADING"' 5109========================== 5110 5111Use SUBHEADING as the title (third line, immediately after the title 5112line) when generating assembly listings. 5113 5114 This directive affects subsequent pages, as well as the current page 5115if it appears within ten lines of the top of a page. 5116 5117 5118File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 5119 51207.81 '.scl CLASS' 5121================= 5122 5123Set the storage-class value for a symbol. This directive may only be 5124used inside a '.def'/'.endef' pair. Storage class may flag whether a 5125symbol is static or external, or it may record further symbolic 5126debugging information. 5127 5128 5129File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 5130 51317.82 '.section NAME' 5132==================== 5133 5134Use the '.section' directive to assemble the following code into a 5135section named NAME. 5136 5137 This directive is only supported for targets that actually support 5138arbitrarily named sections; on 'a.out' targets, for example, it is not 5139accepted, even with a standard 'a.out' section name. 5140 5141COFF Version 5142------------ 5143 5144For COFF targets, the '.section' directive is used in one of the 5145following ways: 5146 5147 .section NAME[, "FLAGS"] 5148 .section NAME[, SUBSECTION] 5149 5150 If the optional argument is quoted, it is taken as flags to use for 5151the section. Each flag is a single character. The following flags are 5152recognized: 5153 5154'b' 5155 bss section (uninitialized data) 5156'n' 5157 section is not loaded 5158'w' 5159 writable section 5160'd' 5161 data section 5162'e' 5163 exclude section from linking 5164'r' 5165 read-only section 5166'x' 5167 executable section 5168's' 5169 shared section (meaningful for PE targets) 5170'a' 5171 ignored. (For compatibility with the ELF version) 5172'y' 5173 section is not readable (meaningful for PE targets) 5174'0-9' 5175 single-digit power-of-two section alignment (GNU extension) 5176 5177 If no flags are specified, the default flags depend upon the section 5178name. If the section name is not recognized, the default will be for 5179the section to be loaded and writable. Note the 'n' and 'w' flags 5180remove attributes from the section, rather than adding them, so if they 5181are used on their own it will be as if no flags had been specified at 5182all. 5183 5184 If the optional argument to the '.section' directive is not quoted, 5185it is taken as a subsection number (*note Sub-Sections::). 5186 5187ELF Version 5188----------- 5189 5190This is one of the ELF section stack manipulation directives. The 5191others are '.subsection' (*note SubSection::), '.pushsection' (*note 5192PushSection::), '.popsection' (*note PopSection::), and '.previous' 5193(*note Previous::). 5194 5195 For ELF targets, the '.section' directive is used like this: 5196 5197 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 5198 5199 If the '--sectname-subst' command-line option is provided, the NAME 5200argument may contain a substitution sequence. Only '%S' is supported at 5201the moment, and substitutes the current section name. For example: 5202 5203 .macro exception_code 5204 .section %S.exception 5205 [exception code here] 5206 .previous 5207 .endm 5208 5209 .text 5210 [code] 5211 exception_code 5212 [...] 5213 5214 .section .init 5215 [init code] 5216 exception_code 5217 [...] 5218 5219 The two 'exception_code' invocations above would create the 5220'.text.exception' and '.init.exception' sections respectively. This is 5221useful e.g. to discriminate between ancillary sections that are tied to 5222setup code to be discarded after use from ancillary sections that need 5223to stay resident without having to define multiple 'exception_code' 5224macros just for that purpose. 5225 5226 The optional FLAGS argument is a quoted string which may contain any 5227combination of the following characters: 5228 5229'a' 5230 section is allocatable 5231'd' 5232 section is a GNU_MBIND section 5233'e' 5234 section is excluded from executable and shared library. 5235'w' 5236 section is writable 5237'x' 5238 section is executable 5239'M' 5240 section is mergeable 5241'S' 5242 section contains zero terminated strings 5243'G' 5244 section is a member of a section group 5245'T' 5246 section is used for thread-local-storage 5247'?' 5248 section is a member of the previously-current section's group, if 5249 any 5250'<number>' 5251 a numeric value indicating the bits to be set in the ELF section 5252 header's flags field. Note - if one or more of the alphabetic 5253 characters described above is also included in the flags field, 5254 their bit values will be ORed into the resulting value. 5255'<target specific>' 5256 some targets extend this list with their own flag characters 5257 5258 Note - once a section's flags have been set they cannot be changed. 5259There are a few exceptions to this rule however. Processor and 5260application specific flags can be added to an already defined section. 5261The '.interp', '.strtab' and '.symtab' sections can have the allocate 5262flag ('a') set after they are initially defined, and the 5263'.note-GNU-stack' section may have the executable ('x') flag added. 5264 5265 The optional TYPE argument may contain one of the following 5266constants: 5267 5268'@progbits' 5269 section contains data 5270'@nobits' 5271 section does not contain data (i.e., section only occupies space) 5272'@note' 5273 section contains data which is used by things other than the 5274 program 5275'@init_array' 5276 section contains an array of pointers to init functions 5277'@fini_array' 5278 section contains an array of pointers to finish functions 5279'@preinit_array' 5280 section contains an array of pointers to pre-init functions 5281'@<number>' 5282 a numeric value to be set as the ELF section header's type field. 5283'@<target specific>' 5284 some targets extend this list with their own types 5285 5286 Many targets only support the first three section types. The type 5287may be enclosed in double quotes if necessary. 5288 5289 Note on targets where the '@' character is the start of a comment (eg 5290ARM) then another character is used instead. For example the ARM port 5291uses the '%' character. 5292 5293 Note - some sections, eg '.text' and '.data' are considered to be 5294special and have fixed types. Any attempt to declare them with a 5295different type will generate an error from the assembler. 5296 5297 If FLAGS contains the 'M' symbol then the TYPE argument must be 5298specified as well as an extra argument--ENTSIZE--like this: 5299 5300 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 5301 5302 Sections with the 'M' flag but not 'S' flag must contain fixed size 5303constants, each ENTSIZE octets long. Sections with both 'M' and 'S' 5304must contain zero terminated strings where each character is ENTSIZE 5305bytes long. The linker may remove duplicates within sections with the 5306same name, same entity size and same flags. ENTSIZE must be an absolute 5307expression. For sections with both 'M' and 'S', a string which is a 5308suffix of a larger string is considered a duplicate. Thus '"def"' will 5309be merged with '"abcdef"'; A reference to the first '"def"' will be 5310changed to a reference to '"abcdef"+3'. 5311 5312 If FLAGS contains the 'G' symbol then the TYPE argument must be 5313present along with an additional field like this: 5314 5315 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 5316 5317 The GROUPNAME field specifies the name of the section group to which 5318this particular section belongs. The optional linkage field can 5319contain: 5320 5321'comdat' 5322 indicates that only one copy of this section should be retained 5323'.gnu.linkonce' 5324 an alias for comdat 5325 5326 Note: if both the M and G flags are present then the fields for the 5327Merge flag should come first, like this: 5328 5329 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 5330 5331 If FLAGS contains the '?' symbol then it may not also contain the 'G' 5332symbol and the GROUPNAME or LINKAGE fields should not be present. 5333Instead, '?' says to consider the section that's current before this 5334directive. If that section used 'G', then the new section will use 'G' 5335with those same GROUPNAME and LINKAGE fields implicitly. If not, then 5336the '?' symbol has no effect. 5337 5338 If no flags are specified, the default flags depend upon the section 5339name. If the section name is not recognized, the default will be for 5340the section to have none of the above flags: it will not be allocated in 5341memory, nor writable, nor executable. The section will contain data. 5342 5343 For ELF targets, the assembler supports another type of '.section' 5344directive for compatibility with the Solaris assembler: 5345 5346 .section "NAME"[, FLAGS...] 5347 5348 Note that the section name is quoted. There may be a sequence of 5349comma separated flags: 5350 5351'#alloc' 5352 section is allocatable 5353'#write' 5354 section is writable 5355'#execinstr' 5356 section is executable 5357'#exclude' 5358 section is excluded from executable and shared library. 5359'#tls' 5360 section is used for thread local storage 5361 5362 This directive replaces the current section and subsection. See the 5363contents of the gas testsuite directory 'gas/testsuite/gas/elf' for some 5364examples of how this directive and the other section stack directives 5365work. 5366 5367 5368File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 5369 53707.83 '.set SYMBOL, EXPRESSION' 5371============================== 5372 5373Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and 5374type to conform to EXPRESSION. If SYMBOL was flagged as external, it 5375remains flagged (*note Symbol Attributes::). 5376 5377 You may '.set' a symbol many times in the same assembly provided that 5378the values given to the symbol are constants. Values that are based on 5379expressions involving other symbols are allowed, but some targets may 5380restrict this to only being done once per assembly. This is because 5381those targets do not set the addresses of symbols at assembly time, but 5382rather delay the assignment until a final link is performed. This 5383allows the linker a chance to change the code in the files, changing the 5384location of, and the relative distance between, various different 5385symbols. 5386 5387 If you '.set' a global symbol, the value stored in the object file is 5388the last value stored into it. 5389 5390 On Z80 'set' is a real instruction, use '.set' or 'SYMBOL defl 5391EXPRESSION' instead. 5392 5393 5394File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 5395 53967.84 '.short EXPRESSIONS' 5397========================= 5398 5399'.short' is normally the same as '.word'. *Note '.word': Word. 5400 5401 In some configurations, however, '.short' and '.word' generate 5402numbers of different lengths. *Note Machine Dependencies::. 5403 5404 5405File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 5406 54077.85 '.single FLONUMS' 5408====================== 5409 5410This directive assembles zero or more flonums, separated by commas. It 5411has the same effect as '.float'. The exact kind of floating point 5412numbers emitted depends on how 'as' is configured. *Note Machine 5413Dependencies::. 5414 5415 5416File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 5417 54187.86 '.size' 5419============ 5420 5421This directive is used to set the size associated with a symbol. 5422 5423COFF Version 5424------------ 5425 5426For COFF targets, the '.size' directive is only permitted inside 5427'.def'/'.endef' pairs. It is used like this: 5428 5429 .size EXPRESSION 5430 5431ELF Version 5432----------- 5433 5434For ELF targets, the '.size' directive is used like this: 5435 5436 .size NAME , EXPRESSION 5437 5438 This directive sets the size associated with a symbol NAME. The size 5439in bytes is computed from EXPRESSION which can make use of label 5440arithmetic. This directive is typically used to set the size of 5441function symbols. 5442 5443 5444File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 5445 54467.87 '.skip SIZE [,FILL]' 5447========================= 5448 5449This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5450are absolute expressions. If the comma and FILL are omitted, FILL is 5451assumed to be zero. This is the same as '.space'. 5452 5453 5454File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 5455 54567.88 '.sleb128 EXPRESSIONS' 5457=========================== 5458 5459SLEB128 stands for "signed little endian base 128." This is a compact, 5460variable length representation of numbers used by the DWARF symbolic 5461debugging format. *Note '.uleb128': Uleb128. 5462 5463 5464File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 5465 54667.89 '.space SIZE [,FILL]' 5467========================== 5468 5469This directive emits SIZE bytes, each of value FILL. Both SIZE and FILL 5470are absolute expressions. If the comma and FILL are omitted, FILL is 5471assumed to be zero. This is the same as '.skip'. 5472 5473 _Warning:_ '.space' has a completely different meaning for HPPA 5474 targets; use '.block' as a substitute. See 'HP9000 Series 800 5475 Assembly Language Reference Manual' (HP 92432-90001) for the 5476 meaning of the '.space' directive. *Note HPPA Assembler 5477 Directives: HPPA Directives, for a summary. 5478 5479 5480File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 5481 54827.90 '.stabd, .stabn, .stabs' 5483============================= 5484 5485There are three directives that begin '.stab'. All emit symbols (*note 5486Symbols::), for use by symbolic debuggers. The symbols are not entered 5487in the 'as' hash table: they cannot be referenced elsewhere in the 5488source file. Up to five fields are required: 5489 5490STRING 5491 This is the symbol's name. It may contain any character except 5492 '\000', so is more general than ordinary symbol names. Some 5493 debuggers used to code arbitrarily complex structures into symbol 5494 names using this field. 5495 5496TYPE 5497 An absolute expression. The symbol's type is set to the low 8 bits 5498 of this expression. Any bit pattern is permitted, but 'ld' and 5499 debuggers choke on silly bit patterns. 5500 5501OTHER 5502 An absolute expression. The symbol's "other" attribute is set to 5503 the low 8 bits of this expression. 5504 5505DESC 5506 An absolute expression. The symbol's descriptor is set to the low 5507 16 bits of this expression. 5508 5509VALUE 5510 An absolute expression which becomes the symbol's value. 5511 5512 If a warning is detected while reading a '.stabd', '.stabn', or 5513'.stabs' statement, the symbol has probably already been created; you 5514get a half-formed symbol in your object file. This is compatible with 5515earlier assemblers! 5516 5517'.stabd TYPE , OTHER , DESC' 5518 5519 The "name" of the symbol generated is not even an empty string. It 5520 is a null pointer, for compatibility. Older assemblers used a null 5521 pointer so they didn't waste space in object files with empty 5522 strings. 5523 5524 The symbol's value is set to the location counter, relocatably. 5525 When your program is linked, the value of this symbol is the 5526 address of the location counter when the '.stabd' was assembled. 5527 5528'.stabn TYPE , OTHER , DESC , VALUE' 5529 The name of the symbol is set to the empty string '""'. 5530 5531'.stabs STRING , TYPE , OTHER , DESC , VALUE' 5532 All five fields are specified. 5533 5534 5535File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 5536 55377.91 '.string' "STR", '.string8' "STR", '.string16' 5538=================================================== 5539 5540"STR", '.string32' "STR", '.string64' "STR" 5541 5542 Copy the characters in STR to the object file. You may specify more 5543than one string to copy, separated by commas. Unless otherwise 5544specified for a particular machine, the assembler marks the end of each 5545string with a 0 byte. You can use any of the escape sequences described 5546in *note Strings: Strings. 5547 5548 The variants 'string16', 'string32' and 'string64' differ from the 5549'string' pseudo opcode in that each 8-bit character from STR is copied 5550and expanded to 16, 32 or 64 bits respectively. The expanded characters 5551are stored in target endianness byte order. 5552 5553 Example: 5554 .string32 "BYE" 5555 expands to: 5556 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5557 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5558 5559 5560File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5561 55627.92 '.struct EXPRESSION' 5563========================= 5564 5565Switch to the absolute section, and set the section offset to 5566EXPRESSION, which must be an absolute expression. You might use this as 5567follows: 5568 .struct 0 5569 field1: 5570 .struct field1 + 4 5571 field2: 5572 .struct field2 + 4 5573 field3: 5574 This would define the symbol 'field1' to have the value 0, the symbol 5575'field2' to have the value 4, and the symbol 'field3' to have the value 55768. Assembly would be left in the absolute section, and you would need 5577to use a '.section' directive of some sort to change to some other 5578section before further assembly. 5579 5580 5581File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5582 55837.93 '.subsection NAME' 5584======================= 5585 5586This is one of the ELF section stack manipulation directives. The 5587others are '.section' (*note Section::), '.pushsection' (*note 5588PushSection::), '.popsection' (*note PopSection::), and '.previous' 5589(*note Previous::). 5590 5591 This directive replaces the current subsection with 'name'. The 5592current section is not changed. The replaced subsection is put onto the 5593section stack in place of the then current top of stack subsection. 5594 5595 5596File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5597 55987.94 '.symver' 5599============== 5600 5601Use the '.symver' directive to bind symbols to specific version nodes 5602within a source file. This is only supported on ELF platforms, and is 5603typically used when assembling files to be linked into a shared library. 5604There are cases where it may make sense to use this in objects to be 5605bound into an application itself so as to override a versioned symbol 5606from a shared library. 5607 5608 For ELF targets, the '.symver' directive can be used like this: 5609 .symver NAME, NAME2@NODENAME 5610 If the symbol NAME is defined within the file being assembled, the 5611'.symver' directive effectively creates a symbol alias with the name 5612NAME2@NODENAME, and in fact the main reason that we just don't try and 5613create a regular alias is that the @ character isn't permitted in symbol 5614names. The NAME2 part of the name is the actual name of the symbol by 5615which it will be externally referenced. The name NAME itself is merely 5616a name of convenience that is used so that it is possible to have 5617definitions for multiple versions of a function within a single source 5618file, and so that the compiler can unambiguously know which version of a 5619function is being mentioned. The NODENAME portion of the alias should 5620be the name of a node specified in the version script supplied to the 5621linker when building a shared library. If you are attempting to 5622override a versioned symbol from a shared library, then NODENAME should 5623correspond to the nodename of the symbol you are trying to override. 5624 5625 If the symbol NAME is not defined within the file being assembled, 5626all references to NAME will be changed to NAME2@NODENAME. If no 5627reference to NAME is made, NAME2@NODENAME will be removed from the 5628symbol table. 5629 5630 Another usage of the '.symver' directive is: 5631 .symver NAME, NAME2@@NODENAME 5632 In this case, the symbol NAME must exist and be defined within the 5633file being assembled. It is similar to NAME2@NODENAME. The difference 5634is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5635the linker. 5636 5637 The third usage of the '.symver' directive is: 5638 .symver NAME, NAME2@@@NODENAME 5639 When NAME is not defined within the file being assembled, it is 5640treated as NAME2@NODENAME. When NAME is defined within the file being 5641assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5642 5643 5644File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5645 56467.95 '.tag STRUCTNAME' 5647====================== 5648 5649This directive is generated by compilers to include auxiliary debugging 5650information in the symbol table. It is only permitted inside 5651'.def'/'.endef' pairs. Tags are used to link structure definitions in 5652the symbol table with instances of those structures. 5653 5654 5655File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5656 56577.96 '.text SUBSECTION' 5658======================= 5659 5660Tells 'as' to assemble the following statements onto the end of the text 5661subsection numbered SUBSECTION, which is an absolute expression. If 5662SUBSECTION is omitted, subsection number zero is used. 5663 5664 5665File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops 5666 56677.97 '.title "HEADING"' 5668======================= 5669 5670Use HEADING as the title (second line, immediately after the source file 5671name and pagenumber) when generating assembly listings. 5672 5673 This directive affects subsequent pages, as well as the current page 5674if it appears within ten lines of the top of a page. 5675 5676 5677File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops 5678 56797.98 '.type' 5680============ 5681 5682This directive is used to set the type of a symbol. 5683 5684COFF Version 5685------------ 5686 5687For COFF targets, this directive is permitted only within 5688'.def'/'.endef' pairs. It is used like this: 5689 5690 .type INT 5691 5692 This records the integer INT as the type attribute of a symbol table 5693entry. 5694 5695ELF Version 5696----------- 5697 5698For ELF targets, the '.type' directive is used like this: 5699 5700 .type NAME , TYPE DESCRIPTION 5701 5702 This sets the type of symbol NAME to be either a function symbol or 5703an object symbol. There are five different syntaxes supported for the 5704TYPE DESCRIPTION field, in order to provide compatibility with various 5705other assemblers. 5706 5707 Because some of the characters used in these syntaxes (such as '@' 5708and '#') are comment characters for some architectures, some of the 5709syntaxes below do not work on all architectures. The first variant will 5710be accepted by the GNU assembler on all architectures so that variant 5711should be used for maximum portability, if you do not need to assemble 5712your code with other assemblers. 5713 5714 The syntaxes supported are: 5715 5716 .type <name> STT_<TYPE_IN_UPPER_CASE> 5717 .type <name>,#<type> 5718 .type <name>,@<type> 5719 .type <name>,%<type> 5720 .type <name>,"<type>" 5721 5722 The types supported are: 5723 5724'STT_FUNC' 5725'function' 5726 Mark the symbol as being a function name. 5727 5728'STT_GNU_IFUNC' 5729'gnu_indirect_function' 5730 Mark the symbol as an indirect function when evaluated during reloc 5731 processing. (This is only supported on assemblers targeting GNU 5732 systems). 5733 5734'STT_OBJECT' 5735'object' 5736 Mark the symbol as being a data object. 5737 5738'STT_TLS' 5739'tls_object' 5740 Mark the symbol as being a thread-local data object. 5741 5742'STT_COMMON' 5743'common' 5744 Mark the symbol as being a common data object. 5745 5746'STT_NOTYPE' 5747'notype' 5748 Does not mark the symbol in any way. It is supported just for 5749 completeness. 5750 5751'gnu_unique_object' 5752 Marks the symbol as being a globally unique data object. The 5753 dynamic linker will make sure that in the entire process there is 5754 just one symbol with this name and type in use. (This is only 5755 supported on assemblers targeting GNU systems). 5756 5757 Changing between incompatible types other than from/to STT_NOTYPE 5758will result in a diagnostic. An intermediate change to STT_NOTYPE will 5759silence this. 5760 5761 Note: Some targets support extra types in addition to those listed 5762above. 5763 5764 5765File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 5766 57677.99 '.uleb128 EXPRESSIONS' 5768=========================== 5769 5770ULEB128 stands for "unsigned little endian base 128." This is a 5771compact, variable length representation of numbers used by the DWARF 5772symbolic debugging format. *Note '.sleb128': Sleb128. 5773 5774 5775File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 5776 57777.100 '.val ADDR' 5778================= 5779 5780This directive, permitted only within '.def'/'.endef' pairs, records the 5781address ADDR as the value attribute of a symbol table entry. 5782 5783 5784File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 5785 57867.101 '.version "STRING"' 5787========================= 5788 5789This directive creates a '.note' section and places into it an ELF 5790formatted note of type NT_VERSION. The note's name is set to 'string'. 5791 5792 5793File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 5794 57957.102 '.vtable_entry TABLE, OFFSET' 5796=================================== 5797 5798This directive finds or creates a symbol 'table' and creates a 5799'VTABLE_ENTRY' relocation for it with an addend of 'offset'. 5800 5801 5802File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 5803 58047.103 '.vtable_inherit CHILD, PARENT' 5805===================================== 5806 5807This directive finds the symbol 'child' and finds or creates the symbol 5808'parent' and then creates a 'VTABLE_INHERIT' relocation for the parent 5809whose addend is the value of the child symbol. As a special case the 5810parent name of '0' is treated as referring to the '*ABS*' section. 5811 5812 5813File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 5814 58157.104 '.warning "STRING"' 5816========================= 5817 5818Similar to the directive '.error' (*note '.error "STRING"': Error.), but 5819just emits a warning. 5820 5821 5822File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 5823 58247.105 '.weak NAMES' 5825=================== 5826 5827This directive sets the weak attribute on the comma separated list of 5828symbol 'names'. If the symbols do not already exist, they will be 5829created. 5830 5831 On COFF targets other than PE, weak symbols are a GNU extension. 5832This directive sets the weak attribute on the comma separated list of 5833symbol 'names'. If the symbols do not already exist, they will be 5834created. 5835 5836 On the PE target, weak symbols are supported natively as weak 5837aliases. When a weak symbol is created that is not an alias, GAS 5838creates an alternate symbol to hold the default value. 5839 5840 5841File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 5842 58437.106 '.weakref ALIAS, TARGET' 5844============================== 5845 5846This directive creates an alias to the target symbol that enables the 5847symbol to be referenced with weak-symbol semantics, but without actually 5848making it weak. If direct references or definitions of the symbol are 5849present, then the symbol will not be weak, but if all references to it 5850are through weak references, the symbol will be marked as weak in the 5851symbol table. 5852 5853 The effect is equivalent to moving all references to the alias to a 5854separate assembly source file, renaming the alias to the symbol in it, 5855declaring the symbol as weak there, and running a reloadable link to 5856merge the object files resulting from the assembly of the new source 5857file and the old source file that had the references to the alias 5858removed. 5859 5860 The alias itself never makes to the symbol table, and is entirely 5861handled within the assembler. 5862 5863 5864File: as.info, Node: Word, Next: Zero, Prev: Weakref, Up: Pseudo Ops 5865 58667.107 '.word EXPRESSIONS' 5867========================= 5868 5869This directive expects zero or more EXPRESSIONS, of any section, 5870separated by commas. 5871 5872 The size of the number emitted, and its byte order, depend on what 5873target computer the assembly is for. 5874 5875 _Warning: Special Treatment to support Compilers_ 5876 5877 Machines with a 32-bit address space, but that do less than 32-bit 5878addressing, require the following special treatment. If the machine of 5879interest to you does 32-bit addressing (or doesn't require it; *note 5880Machine Dependencies::), you can ignore this issue. 5881 5882 In order to assemble compiler output into something that works, 'as' 5883occasionally does strange things to '.word' directives. Directives of 5884the form '.word sym1-sym2' are often emitted by compilers as part of 5885jump tables. Therefore, when 'as' assembles a directive of the form 5886'.word sym1-sym2', and the difference between 'sym1' and 'sym2' does not 5887fit in 16 bits, 'as' creates a "secondary jump table", immediately 5888before the next label. This secondary jump table is preceded by a 5889short-jump to the first byte after the secondary table. This short-jump 5890prevents the flow of control from accidentally falling into the new 5891table. Inside the table is a long-jump to 'sym2'. The original '.word' 5892contains 'sym1' minus the address of the long-jump to 'sym2'. 5893 5894 If there were several occurrences of '.word sym1-sym2' before the 5895secondary jump table, all of them are adjusted. If there was a '.word 5896sym3-sym4', that also did not fit in sixteen bits, a long-jump to 'sym4' 5897is included in the secondary jump table, and the '.word' directives are 5898adjusted to contain 'sym3' minus the address of the long-jump to 'sym4'; 5899and so on, for as many entries in the original jump table as necessary. 5900 5901 5902File: as.info, Node: Zero, Next: 2byte, Prev: Word, Up: Pseudo Ops 5903 59047.108 '.zero SIZE' 5905================== 5906 5907This directive emits SIZE 0-valued bytes. SIZE must be an absolute 5908expression. This directive is actually an alias for the '.skip' 5909directive so it can take an optional second argument of the value to 5910store in the bytes instead of zero. Using '.zero' in this way would be 5911confusing however. 5912 5913 5914File: as.info, Node: 2byte, Next: 4byte, Prev: Zero, Up: Pseudo Ops 5915 59167.109 '.2byte EXPRESSION [, EXPRESSION]*' 5917========================================= 5918 5919This directive expects zero or more expressions, separated by commas. 5920If there are no expressions then the directive does nothing. Otherwise 5921each expression is evaluated in turn and placed in the next two bytes of 5922the current output section, using the endian model of the target. If an 5923expression will not fit in two bytes, a warning message is displayed and 5924the least significant two bytes of the expression's value are used. If 5925an expression cannot be evaluated at assembly time then relocations will 5926be generated in order to compute the value at link time. 5927 5928 This directive does not apply any alignment before or after inserting 5929the values. As a result of this, if relocations are generated, they may 5930be different from those used for inserting values with a guaranteed 5931alignment. 5932 5933 This directive is only available for ELF targets, 5934 5935 5936File: as.info, Node: 4byte, Next: 8byte, Prev: 2byte, Up: Pseudo Ops 5937 59387.110 '.4byte EXPRESSION [, EXPRESSION]*' 5939========================================= 5940 5941Like the '.2byte' directive, except that it inserts unaligned, four byte 5942long values into the output. 5943 5944 5945File: as.info, Node: 8byte, Next: Deprecated, Prev: 4byte, Up: Pseudo Ops 5946 59477.111 '.8byte EXPRESSION [, EXPRESSION]*' 5948========================================= 5949 5950Like the '.2byte' directive, except that it inserts unaligned, eight 5951byte long bignum values into the output. 5952 5953 5954File: as.info, Node: Deprecated, Prev: 8byte, Up: Pseudo Ops 5955 59567.112 Deprecated Directives 5957=========================== 5958 5959One day these directives won't work. They are included for 5960compatibility with older assemblers. 5961.abort 5962.line 5963 5964 5965File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 5966 59678 Object Attributes 5968******************* 5969 5970'as' assembles source files written for a specific architecture into 5971object files for that architecture. But not all object files are alike. 5972Many architectures support incompatible variations. For instance, 5973floating point arguments might be passed in floating point registers if 5974the object file requires hardware floating point support--or floating 5975point arguments might be passed in integer registers if the object file 5976supports processors with no hardware floating point unit. Or, if two 5977objects are built for different generations of the same architecture, 5978the combination may require the newer generation at run-time. 5979 5980 This information is useful during and after linking. At link time, 5981'ld' can warn about incompatible object files. After link time, tools 5982like 'gdb' can use it to process the linked file correctly. 5983 5984 Compatibility information is recorded as a series of object 5985attributes. Each attribute has a "vendor", "tag", and "value". The 5986vendor is a string, and indicates who sets the meaning of the tag. The 5987tag is an integer, and indicates what property the attribute describes. 5988The value may be a string or an integer, and indicates how the property 5989affects this object. Missing attributes are the same as attributes with 5990a zero value or empty string value. 5991 5992 Object attributes were developed as part of the ABI for the ARM 5993Architecture. The file format is documented in 'ELF for the ARM 5994Architecture'. 5995 5996* Menu: 5997 5998* GNU Object Attributes:: GNU Object Attributes 5999* Defining New Object Attributes:: Defining New Object Attributes 6000 6001 6002File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 6003 60048.1 GNU Object Attributes 6005========================= 6006 6007The '.gnu_attribute' directive records an object attribute with vendor 6008'gnu'. 6009 6010 Except for 'Tag_compatibility', which has both an integer and a 6011string for its value, GNU attributes have a string value if the tag 6012number is odd and an integer value if the tag number is even. The 6013second bit ('TAG & 2' is set for architecture-independent attributes and 6014clear for architecture-dependent ones. 6015 60168.1.1 Common GNU attributes 6017--------------------------- 6018 6019These attributes are valid on all architectures. 6020 6021Tag_compatibility (32) 6022 The compatibility attribute takes an integer flag value and a 6023 vendor name. If the flag value is 0, the file is compatible with 6024 other toolchains. If it is 1, then the file is only compatible 6025 with the named toolchain. If it is greater than 1, the file can 6026 only be processed by other toolchains under some private 6027 arrangement indicated by the flag value and the vendor name. 6028 60298.1.2 MIPS Attributes 6030--------------------- 6031 6032Tag_GNU_MIPS_ABI_FP (4) 6033 The floating-point ABI used by this object file. The value will 6034 be: 6035 6036 * 0 for files not affected by the floating-point ABI. 6037 * 1 for files using the hardware floating-point ABI with a 6038 standard double-precision FPU. 6039 * 2 for files using the hardware floating-point ABI with a 6040 single-precision FPU. 6041 * 3 for files using the software floating-point ABI. 6042 * 4 for files using the deprecated hardware floating-point ABI 6043 which used 64-bit floating-point registers, 32-bit 6044 general-purpose registers and increased the number of 6045 callee-saved floating-point registers. 6046 * 5 for files using the hardware floating-point ABI with a 6047 double-precision FPU with either 32-bit or 64-bit 6048 floating-point registers and 32-bit general-purpose registers. 6049 * 6 for files using the hardware floating-point ABI with 64-bit 6050 floating-point registers and 32-bit general-purpose registers. 6051 * 7 for files using the hardware floating-point ABI with 64-bit 6052 floating-point registers, 32-bit general-purpose registers and 6053 a rule that forbids the direct use of odd-numbered 6054 single-precision floating-point registers. 6055 60568.1.3 PowerPC Attributes 6057------------------------ 6058 6059Tag_GNU_Power_ABI_FP (4) 6060 The floating-point ABI used by this object file. The value will 6061 be: 6062 6063 * 0 for files not affected by the floating-point ABI. 6064 * 1 for files using double-precision hardware floating-point 6065 ABI. 6066 * 2 for files using the software floating-point ABI. 6067 * 3 for files using single-precision hardware floating-point 6068 ABI. 6069 6070Tag_GNU_Power_ABI_Vector (8) 6071 The vector ABI used by this object file. The value will be: 6072 6073 * 0 for files not affected by the vector ABI. 6074 * 1 for files using general purpose registers to pass vectors. 6075 * 2 for files using AltiVec registers to pass vectors. 6076 * 3 for files using SPE registers to pass vectors. 6077 60788.1.4 IBM z Systems Attributes 6079------------------------------ 6080 6081Tag_GNU_S390_ABI_Vector (8) 6082 The vector ABI used by this object file. The value will be: 6083 6084 * 0 for files not affected by the vector ABI. 6085 * 1 for files using software vector ABI. 6086 * 2 for files using hardware vector ABI. 6087 60888.1.5 MSP430 Attributes 6089----------------------- 6090 6091Tag_GNU_MSP430_Data_Region (4) 6092 The data region used by this object file. The value will be: 6093 6094 * 0 for files not using the large memory model. 6095 * 1 for files which have been compiled with the condition that 6096 all data is in the lower memory region, i.e. below address 6097 0x10000. 6098 * 2 for files which allow data to be placed in the full 20-bit 6099 memory range. 6100 6101 6102File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 6103 61048.2 Defining New Object Attributes 6105================================== 6106 6107If you want to define a new GNU object attribute, here are the places 6108you will need to modify. New attributes should be discussed on the 6109'binutils' mailing list. 6110 6111 * This manual, which is the official register of attributes. 6112 * The header for your architecture 'include/elf', to define the tag. 6113 * The 'bfd' support file for your architecture, to merge the 6114 attribute and issue any appropriate link warnings. 6115 * Test cases in 'ld/testsuite' for merging and link warnings. 6116 * 'binutils/readelf.c' to display your attribute. 6117 * GCC, if you want the compiler to mark the attribute automatically. 6118 6119 6120File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 6121 61229 Machine Dependent Features 6123**************************** 6124 6125The machine instruction sets are (almost by definition) different on 6126each machine where 'as' runs. Floating point representations vary as 6127well, and 'as' often supports a few additional directives or 6128command-line options for compatibility with other assemblers on a 6129particular platform. Finally, some versions of 'as' support special 6130pseudo-instructions for branch optimization. 6131 6132 This chapter discusses most of these differences, though it does not 6133include details on any machine's instruction set. For details on that 6134subject, see the hardware manufacturer's manual. 6135 6136* Menu: 6137 6138* AArch64-Dependent:: AArch64 Dependent Features 6139* Alpha-Dependent:: Alpha Dependent Features 6140* ARC-Dependent:: ARC Dependent Features 6141* ARM-Dependent:: ARM Dependent Features 6142* AVR-Dependent:: AVR Dependent Features 6143* Blackfin-Dependent:: Blackfin Dependent Features 6144* BPF-Dependent:: BPF Dependent Features 6145* CR16-Dependent:: CR16 Dependent Features 6146* CRIS-Dependent:: CRIS Dependent Features 6147* C-SKY-Dependent:: C-SKY Dependent Features 6148* D10V-Dependent:: D10V Dependent Features 6149* D30V-Dependent:: D30V Dependent Features 6150* Epiphany-Dependent:: EPIPHANY Dependent Features 6151* H8/300-Dependent:: Renesas H8/300 Dependent Features 6152* HPPA-Dependent:: HPPA Dependent Features 6153* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 6154* IA-64-Dependent:: Intel IA-64 Dependent Features 6155* IP2K-Dependent:: IP2K Dependent Features 6156* LM32-Dependent:: LM32 Dependent Features 6157* M32C-Dependent:: M32C Dependent Features 6158* M32R-Dependent:: M32R Dependent Features 6159* M68K-Dependent:: M680x0 Dependent Features 6160* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 6161* S12Z-Dependent:: S12Z Dependent Features 6162* Meta-Dependent :: Meta Dependent Features 6163* MicroBlaze-Dependent:: MICROBLAZE Dependent Features 6164* MIPS-Dependent:: MIPS Dependent Features 6165* MMIX-Dependent:: MMIX Dependent Features 6166* MSP430-Dependent:: MSP430 Dependent Features 6167* NDS32-Dependent:: Andes NDS32 Dependent Features 6168* NiosII-Dependent:: Altera Nios II Dependent Features 6169* NS32K-Dependent:: NS32K Dependent Features 6170* OpenRISC-Dependent:: OpenRISC 1000 Features 6171* PDP-11-Dependent:: PDP-11 Dependent Features 6172* PJ-Dependent:: picoJava Dependent Features 6173* PPC-Dependent:: PowerPC Dependent Features 6174* PRU-Dependent:: PRU Dependent Features 6175* RISC-V-Dependent:: RISC-V Dependent Features 6176* RL78-Dependent:: RL78 Dependent Features 6177* RX-Dependent:: RX Dependent Features 6178* S/390-Dependent:: IBM S/390 Dependent Features 6179* SCORE-Dependent:: SCORE Dependent Features 6180* SH-Dependent:: Renesas / SuperH SH Dependent Features 6181* Sparc-Dependent:: SPARC Dependent Features 6182* TIC54X-Dependent:: TI TMS320C54x Dependent Features 6183* TIC6X-Dependent :: TI TMS320C6x Dependent Features 6184* TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features 6185* TILEPro-Dependent :: Tilera TILEPro Dependent Features 6186* V850-Dependent:: V850 Dependent Features 6187* Vax-Dependent:: VAX Dependent Features 6188* Visium-Dependent:: Visium Dependent Features 6189* WebAssembly-Dependent:: WebAssembly Dependent Features 6190* XGATE-Dependent:: XGATE Dependent Features 6191* XSTORMY16-Dependent:: XStormy16 Dependent Features 6192* Xtensa-Dependent:: Xtensa Dependent Features 6193* Z80-Dependent:: Z80 Dependent Features 6194* Z8000-Dependent:: Z8000 Dependent Features 6195 6196 6197File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies 6198 61999.1 AArch64 Dependent Features 6200============================== 6201 6202* Menu: 6203 6204* AArch64 Options:: Options 6205* AArch64 Extensions:: Extensions 6206* AArch64 Syntax:: Syntax 6207* AArch64 Floating Point:: Floating Point 6208* AArch64 Directives:: AArch64 Machine Directives 6209* AArch64 Opcodes:: Opcodes 6210* AArch64 Mapping Symbols:: Mapping Symbols 6211 6212 6213File: as.info, Node: AArch64 Options, Next: AArch64 Extensions, Up: AArch64-Dependent 6214 62159.1.1 Options 6216------------- 6217 6218'-EB' 6219 This option specifies that the output generated by the assembler 6220 should be marked as being encoded for a big-endian processor. 6221 6222'-EL' 6223 This option specifies that the output generated by the assembler 6224 should be marked as being encoded for a little-endian processor. 6225 6226'-mabi=ABI' 6227 Specify which ABI the source code uses. The recognized arguments 6228 are: 'ilp32' and 'lp64', which decides the generated object file in 6229 ELF32 and ELF64 format respectively. The default is 'lp64'. 6230 6231'-mcpu=PROCESSOR[+EXTENSION...]' 6232 This option specifies the target processor. The assembler will 6233 issue an error message if an attempt is made to assemble an 6234 instruction which will not execute on the target processor. The 6235 following processor names are recognized: 'cortex-a34', 6236 'cortex-a35', 'cortex-a53', 'cortex-a55', 'cortex-a57', 6237 'cortex-a65', 'cortex-a65ae', 'cortex-a72', 'cortex-a73', 6238 'cortex-a75', 'cortex-a76', 'cortex-a76ae', 'cortex-a77', 'ares', 6239 'exynos-m1', 'falkor', 'neoverse-n1', 'neoverse-e1', 'qdf24xx', 6240 'saphira', 'thunderx', 'vulcan', 'xgene1' and 'xgene2'. The 6241 special name 'all' may be used to allow the assembler to accept 6242 instructions valid for any supported processor, including all 6243 optional extensions. 6244 6245 In addition to the basic instruction set, the assembler can be told 6246 to accept, or restrict, various extension mnemonics that extend the 6247 processor. *Note AArch64 Extensions::. 6248 6249 If some implementations of a particular processor can have an 6250 extension, then then those extensions are automatically enabled. 6251 Consequently, you will not normally have to specify any additional 6252 extensions. 6253 6254'-march=ARCHITECTURE[+EXTENSION...]' 6255 This option specifies the target architecture. The assembler will 6256 issue an error message if an attempt is made to assemble an 6257 instruction which will not execute on the target architecture. The 6258 following architecture names are recognized: 'armv8-a', 6259 'armv8.1-a', 'armv8.2-a', 'armv8.3-a', 'armv8.4-a' 'armv8.5-a', and 6260 'armv8.6-a'. 6261 6262 If both '-mcpu' and '-march' are specified, the assembler will use 6263 the setting for '-mcpu'. If neither are specified, the assembler 6264 will default to '-mcpu=all'. 6265 6266 The architecture option can be extended with the same instruction 6267 set extension options as the '-mcpu' option. Unlike '-mcpu', 6268 extensions are not always enabled by default, *Note AArch64 6269 Extensions::. 6270 6271'-mverbose-error' 6272 This option enables verbose error messages for AArch64 gas. This 6273 option is enabled by default. 6274 6275'-mno-verbose-error' 6276 This option disables verbose error messages in AArch64 gas. 6277 6278 6279File: as.info, Node: AArch64 Extensions, Next: AArch64 Syntax, Prev: AArch64 Options, Up: AArch64-Dependent 6280 62819.1.2 Architecture Extensions 6282----------------------------- 6283 6284The table below lists the permitted architecture extensions that are 6285supported by the assembler and the conditions under which they are 6286automatically enabled. 6287 6288 Multiple extensions may be specified, separated by a '+'. Extension 6289mnemonics may also be removed from those the assembler accepts. This is 6290done by prepending 'no' to the option that adds the extension. 6291Extensions that are removed must be listed after all extensions that 6292have been added. 6293 6294 Enabling an extension that requires other extensions will 6295automatically cause those extensions to be enabled. Similarly, 6296disabling an extension that is required by other extensions will 6297automatically cause those extensions to be disabled. 6298 6299Extension Minimum Enabled by Description 6300 Architecture default 6301---------------------------------------------------------------------------- 6302'i8mm' ARMv8.2-A ARMv8.6-A Enable Int8 Matrix Multiply 6303 or later extension. 6304'f32mm' ARMv8.2-A No Enable F32 Matrix Multiply extension. 6305'f64mm' ARMv8.2-A No Enable F64 Matrix Multiply extension. 6306'bf16' ARMv8.2-A ARMv8.6-A Enable BFloat16 extension. 6307 or later 6308'compnum' ARMv8.2-A ARMv8.3-A Enable the complex number SIMD 6309 or later extensions. This implies 'fp16' and 6310 'simd'. 6311'crc' ARMv8-A ARMv8.1-A Enable CRC instructions. 6312 or later 6313'crypto' ARMv8-A No Enable cryptographic extensions. 6314 This implies 'fp', 'simd', 'aes' and 6315 'sha2'. 6316'aes' ARMv8-A No Enable the AES cryptographic 6317 extensions. This implies 'fp' and 6318 'simd'. 6319'sha2' ARMv8-A No Enable the SHA2 cryptographic 6320 extensions. This implies 'fp' and 6321 'simd'. 6322'sha3' ARMv8.2-A No Enable the ARMv8.2-A SHA2 and SHA3 6323 cryptographic extensions. This 6324 implies 'fp', 'simd' and 'sha2'. 6325'sm4' ARMv8.2-A No Enable the ARMv8.2-A SM3 and SM4 6326 cryptographic extensions. This 6327 implies 'fp' and 'simd'. 6328'fp' ARMv8-A ARMv8-A or Enable floating-point extensions. 6329 later 6330'fp16' ARMv8.2-A ARMv8.2-A Enable ARMv8.2 16-bit floating-point 6331 or later support. This implies 'fp'. 6332'lor' ARMv8-A ARMv8.1-A Enable Limited Ordering Regions 6333 or later extensions. 6334'lse' ARMv8-A ARMv8.1-A Enable Large System extensions. 6335 or later 6336'pan' ARMv8-A ARMv8.1-A Enable Privileged Access Never 6337 or later support. 6338'profile' ARMv8.2-A No Enable statistical profiling 6339 extensions. 6340'ras' ARMv8-A ARMv8.2-A Enable the Reliability, Availability 6341 or later and Serviceability extension. 6342'rcpc' ARMv8.2-A ARMv8.3-A Enable the weak release consistency 6343 or later extension. 6344'rdma' ARMv8-A ARMv8.1-A Enable ARMv8.1 Advanced SIMD 6345 or later extensions. This implies 'simd'. 6346'simd' ARMv8-A ARMv8-A or Enable Advanced SIMD extensions. 6347 later This implies 'fp'. 6348'sve' ARMv8.2-A No Enable the Scalable Vector 6349 Extensions. This implies 'fp16', 6350 'simd' and 'compnum'. 6351'dotprod' ARMv8.2-A ARMv8.4-A Enable the Dot Product extension. 6352 or later This implies 'simd'. 6353'fp16fml' ARMv8.2-A ARMv8.4-A Enable ARMv8.2 16-bit floating-point 6354 or later multiplication variant support. This 6355 implies 'fp16'. 6356'sb' ARMv8-A ARMv8.5-A Enable the speculation barrier 6357 or later instruction sb. 6358'predres' ARMv8-A ARMv8.5-A Enable the Execution and Data and 6359 or later Prediction instructions. 6360'rng' ARMv8.5-A No Enable ARMv8.5-A random number 6361 instructions. 6362'ssbs' ARMv8-A ARMv8.5-A Enable Speculative Store Bypassing 6363 or later Safe state read and write. 6364'memtag' ARMv8.5-A No Enable ARMv8.5-A Memory Tagging 6365 Extensions. 6366'tme' ARMv8-A No Enable Transactional Memory 6367 Extensions. 6368'sve2' ARMv8-A No Enable the SVE2 Extension. 6369'sve2-bitperm'ARMv8-A No Enable SVE2 BITPERM Extension. 6370'sve2-sm4'ARMv8-A No Enable SVE2 SM4 Extension. 6371'sve2-aes'ARMv8-A No Enable SVE2 AES Extension. This also 6372 enables the .Q->.B form of the 6373 'pmullt' and 'pmullb' instructions. 6374'sve2-sha3'ARMv8-A No Enable SVE2 SHA3 Extension. 6375 6376 6377File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Extensions, Up: AArch64-Dependent 6378 63799.1.3 Syntax 6380------------ 6381 6382* Menu: 6383 6384* AArch64-Chars:: Special Characters 6385* AArch64-Regs:: Register Names 6386* AArch64-Relocations:: Relocations 6387 6388 6389File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax 6390 63919.1.3.1 Special Characters 6392.......................... 6393 6394The presence of a '//' on a line indicates the start of a comment that 6395extends to the end of the current line. If a '#' appears as the first 6396character of a line, the whole line is treated as a comment. 6397 6398 The ';' character can be used instead of a newline to separate 6399statements. 6400 6401 The '#' can be optionally used to indicate immediate operands. 6402 6403 6404File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax 6405 64069.1.3.2 Register Names 6407...................... 6408 6409Please refer to the section '4.4 Register Names' of 'ARMv8 Instruction 6410Set Overview', which is available at <http://infocenter.arm.com>. 6411 6412 6413File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax 6414 64159.1.3.3 Relocations 6416................... 6417 6418Relocations for 'MOVZ' and 'MOVK' instructions can be generated by 6419prefixing the label with '#:abs_g2:' etc. For example to load the 642048-bit absolute address of FOO into x0: 6421 6422 movz x0, #:abs_g2:foo // bits 32-47, overflow check 6423 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 6424 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 6425 6426 Relocations for 'ADRP', and 'ADD', 'LDR' or 'STR' instructions can be 6427generated by prefixing the label with ':pg_hi21:' and '#:lo12:' 6428respectively. 6429 6430 For example to use 33-bit (+/-4GB) pc-relative addressing to load the 6431address of FOO into x0: 6432 6433 adrp x0, :pg_hi21:foo 6434 add x0, x0, #:lo12:foo 6435 6436 Or to load the value of FOO into x0: 6437 6438 adrp x0, :pg_hi21:foo 6439 ldr x0, [x0, #:lo12:foo] 6440 6441 Note that ':pg_hi21:' is optional. 6442 6443 adrp x0, foo 6444 6445 is equivalent to 6446 6447 adrp x0, :pg_hi21:foo 6448 6449 6450File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent 6451 64529.1.4 Floating Point 6453-------------------- 6454 6455The AArch64 architecture uses IEEE floating-point numbers. 6456 6457 6458File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent 6459 64609.1.5 AArch64 Machine Directives 6461-------------------------------- 6462 6463'.arch NAME' 6464 Select the target architecture. Valid values for NAME are the same 6465 as for the '-march' command-line option. 6466 6467 Specifying '.arch' clears any previously selected architecture 6468 extensions. 6469 6470'.arch_extension NAME' 6471 Add or remove an architecture extension to the target architecture. 6472 Valid values for NAME are the same as those accepted as 6473 architectural extensions by the '-mcpu' command-line option. 6474 6475 '.arch_extension' may be used multiple times to add or remove 6476 extensions incrementally to the architecture being compiled for. 6477 6478'.bss' 6479 This directive switches to the '.bss' section. 6480 6481'.cpu NAME' 6482 Set the target processor. Valid values for NAME are the same as 6483 those accepted by the '-mcpu=' command-line option. 6484 6485'.dword EXPRESSIONS' 6486 The '.dword' directive produces 64 bit values. 6487 6488'.even' 6489 The '.even' directive aligns the output on the next even byte 6490 boundary. 6491 6492'.float16 VALUE [,...,VALUE_N]' 6493 Place the half precision floating point representation of one or 6494 more floating-point values into the current section. The format 6495 used to encode the floating point values is always the IEEE 6496 754-2008 half precision floating point format. 6497 6498'.inst EXPRESSIONS' 6499 Inserts the expressions into the output as if they were 6500 instructions, rather than data. 6501 6502'.ltorg' 6503 This directive causes the current contents of the literal pool to 6504 be dumped into the current section (which is assumed to be the 6505 .text section) at the current location (aligned to a word 6506 boundary). GAS maintains a separate literal pool for each section 6507 and each sub-section. The '.ltorg' directive will only affect the 6508 literal pool of the current section and sub-section. At the end of 6509 assembly all remaining, un-empty literal pools will automatically 6510 be dumped. 6511 6512 Note - older versions of GAS would dump the current literal pool 6513 any time a section change occurred. This is no longer done, since 6514 it prevents accurate control of the placement of literal pools. 6515 6516'.pool' 6517 This is a synonym for .ltorg. 6518 6519'NAME .req REGISTER NAME' 6520 This creates an alias for REGISTER NAME called NAME. For example: 6521 6522 foo .req w0 6523 6524 ip0, ip1, lr and fp are automatically defined to alias to X16, X17, 6525 X30 and X29 respectively. 6526 6527'.tlsdescadd' 6528 Emits a TLSDESC_ADD reloc on the next instruction. 6529 6530'.tlsdesccall' 6531 Emits a TLSDESC_CALL reloc on the next instruction. 6532 6533'.tlsdescldr' 6534 Emits a TLSDESC_LDR reloc on the next instruction. 6535 6536'.unreq ALIAS-NAME' 6537 This undefines a register alias which was previously defined using 6538 the 'req' directive. For example: 6539 6540 foo .req w0 6541 .unreq foo 6542 6543 An error occurs if the name is undefined. Note - this pseudo op 6544 can be used to delete builtin in register name aliases (eg 'w0'). 6545 This should only be done if it is really necessary. 6546 6547'.variant_pcs SYMBOL' 6548 This directive marks SYMBOL referencing a function that may follow 6549 a variant procedure call standard with different register usage 6550 convention from the base procedure call standard. 6551 6552'.xword EXPRESSIONS' 6553 The '.xword' directive produces 64 bit values. This is the same as 6554 the '.dword' directive. 6555 6556'.cfi_b_key_frame' 6557 The '.cfi_b_key_frame' directive inserts a 'B' character into the 6558 CIE corresponding to the current frame's FDE, meaning that its 6559 return address has been signed with the B-key. If two frames are 6560 signed with differing keys then they will not share the same CIE. 6561 This information is intended to be used by the stack unwinder in 6562 order to properly authenticate return addresses. 6563 6564 6565File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent 6566 65679.1.6 Opcodes 6568------------- 6569 6570GAS implements all the standard AArch64 opcodes. It also implements 6571several pseudo opcodes, including several synthetic load instructions. 6572 6573'LDR =' 6574 ldr <register> , =<expression> 6575 6576 The constant expression will be placed into the nearest literal 6577 pool (if it not already there) and a PC-relative LDR instruction 6578 will be generated. 6579 6580 For more information on the AArch64 instruction set and assembly 6581language notation, see 'ARMv8 Instruction Set Overview' available at 6582<http://infocenter.arm.com>. 6583 6584 6585File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent 6586 65879.1.7 Mapping Symbols 6588--------------------- 6589 6590The AArch64 ELF specification requires that special symbols be inserted 6591into object files to mark certain features: 6592 6593'$x' 6594 At the start of a region of code containing AArch64 instructions. 6595 6596'$d' 6597 At the start of a region of data. 6598 6599 6600File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies 6601 66029.2 Alpha Dependent Features 6603============================ 6604 6605* Menu: 6606 6607* Alpha Notes:: Notes 6608* Alpha Options:: Options 6609* Alpha Syntax:: Syntax 6610* Alpha Floating Point:: Floating Point 6611* Alpha Directives:: Alpha Machine Directives 6612* Alpha Opcodes:: Opcodes 6613 6614 6615File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 6616 66179.2.1 Notes 6618----------- 6619 6620The documentation here is primarily for the ELF object format. 'as' 6621also supports the ECOFF and EVAX formats, but features specific to these 6622formats are not yet documented. 6623 6624 6625File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 6626 66279.2.2 Options 6628------------- 6629 6630'-mCPU' 6631 This option specifies the target processor. If an attempt is made 6632 to assemble an instruction which will not execute on the target 6633 processor, the assembler may either expand the instruction as a 6634 macro or issue an error message. This option is equivalent to the 6635 '.arch' directive. 6636 6637 The following processor names are recognized: '21064', '21064a', 6638 '21066', '21068', '21164', '21164a', '21164pc', '21264', '21264a', 6639 '21264b', 'ev4', 'ev5', 'lca45', 'ev5', 'ev56', 'pca56', 'ev6', 6640 'ev67', 'ev68'. The special name 'all' may be used to allow the 6641 assembler to accept instructions valid for any Alpha processor. 6642 6643 In order to support existing practice in OSF/1 with respect to 6644 '.arch', and existing practice within 'MILO' (the Linux ARC 6645 bootloader), the numbered processor names (e.g. 21064) enable the 6646 processor-specific PALcode instructions, while the "electro-vlasic" 6647 names (e.g. 'ev4') do not. 6648 6649'-mdebug' 6650'-no-mdebug' 6651 Enables or disables the generation of '.mdebug' encapsulation for 6652 stabs directives and procedure descriptors. The default is to 6653 automatically enable '.mdebug' when the first stabs directive is 6654 seen. 6655 6656'-relax' 6657 This option forces all relocations to be put into the object file, 6658 instead of saving space and resolving some relocations at assembly 6659 time. Note that this option does not propagate all symbol 6660 arithmetic into the object file, because not all symbol arithmetic 6661 can be represented. However, the option can still be useful in 6662 specific applications. 6663 6664'-replace' 6665'-noreplace' 6666 Enables or disables the optimization of procedure calls, both at 6667 assemblage and at link time. These options are only available for 6668 VMS targets and '-replace' is the default. See section 1.4.1 of 6669 the OpenVMS Linker Utility Manual. 6670 6671'-g' 6672 This option is used when the compiler generates debug information. 6673 When 'gcc' is using 'mips-tfile' to generate debug information for 6674 ECOFF, local labels must be passed through to the object file. 6675 Otherwise this option has no effect. 6676 6677'-GSIZE' 6678 A local common symbol larger than SIZE is placed in '.bss', while 6679 smaller symbols are placed in '.sbss'. 6680 6681'-F' 6682'-32addr' 6683 These options are ignored for backward compatibility. 6684 6685 6686File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 6687 66889.2.3 Syntax 6689------------ 6690 6691The assembler syntax closely follow the Alpha Reference Manual; 6692assembler directives and general syntax closely follow the OSF/1 and 6693OpenVMS syntax, with a few differences for ELF. 6694 6695* Menu: 6696 6697* Alpha-Chars:: Special Characters 6698* Alpha-Regs:: Register Names 6699* Alpha-Relocs:: Relocations 6700 6701 6702File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 6703 67049.2.3.1 Special Characters 6705.......................... 6706 6707'#' is the line comment character. Note that if '#' is the first 6708character on a line then it can also be a logical line number directive 6709(*note Comments::) or a preprocessor control command (*note 6710Preprocessing::). 6711 6712 ';' can be used instead of a newline to separate statements. 6713 6714 6715File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 6716 67179.2.3.2 Register Names 6718...................... 6719 6720The 32 integer registers are referred to as '$N' or '$rN'. In addition, 6721registers 15, 28, 29, and 30 may be referred to by the symbols '$fp', 6722'$at', '$gp', and '$sp' respectively. 6723 6724 The 32 floating-point registers are referred to as '$fN'. 6725 6726 6727File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 6728 67299.2.3.3 Relocations 6730................... 6731 6732Some of these relocations are available for ECOFF, but mostly only for 6733ELF. They are modeled after the relocation format introduced in Digital 6734Unix 4.0, but there are additions. 6735 6736 The format is '!TAG' or '!TAG!NUMBER' where TAG is the name of the 6737relocation. In some cases NUMBER is used to relate specific 6738instructions. 6739 6740 The relocation is placed at the end of the instruction like so: 6741 6742 ldah $0,a($29) !gprelhigh 6743 lda $0,a($0) !gprellow 6744 ldq $1,b($29) !literal!100 6745 ldl $2,0($1) !lituse_base!100 6746 6747'!literal' 6748'!literal!N' 6749 Used with an 'ldq' instruction to load the address of a symbol from 6750 the GOT. 6751 6752 A sequence number N is optional, and if present is used to pair 6753 'lituse' relocations with this 'literal' relocation. The 'lituse' 6754 relocations are used by the linker to optimize the code based on 6755 the final location of the symbol. 6756 6757 Note that these optimizations are dependent on the data flow of the 6758 program. Therefore, if _any_ 'lituse' is paired with a 'literal' 6759 relocation, then _all_ uses of the register set by the 'literal' 6760 instruction must also be marked with 'lituse' relocations. This is 6761 because the original 'literal' instruction may be deleted or 6762 transformed into another instruction. 6763 6764 Also note that there may be a one-to-many relationship between 6765 'literal' and 'lituse', but not a many-to-one. That is, if there 6766 are two code paths that load up the same address and feed the value 6767 to a single use, then the use may not use a 'lituse' relocation. 6768 6769'!lituse_base!N' 6770 Used with any memory format instruction (e.g. 'ldl') to indicate 6771 that the literal is used for an address load. The offset field of 6772 the instruction must be zero. During relaxation, the code may be 6773 altered to use a gp-relative load. 6774 6775'!lituse_jsr!N' 6776 Used with a register branch format instruction (e.g. 'jsr') to 6777 indicate that the literal is used for a call. During relaxation, 6778 the code may be altered to use a direct branch (e.g. 'bsr'). 6779 6780'!lituse_jsrdirect!N' 6781 Similar to 'lituse_jsr', but also that this call cannot be vectored 6782 through a PLT entry. This is useful for functions with special 6783 calling conventions which do not allow the normal call-clobbered 6784 registers to be clobbered. 6785 6786'!lituse_bytoff!N' 6787 Used with a byte mask instruction (e.g. 'extbl') to indicate that 6788 only the low 3 bits of the address are relevant. During 6789 relaxation, the code may be altered to use an immediate instead of 6790 a register shift. 6791 6792'!lituse_addr!N' 6793 Used with any other instruction to indicate that the original 6794 address is in fact used, and the original 'ldq' instruction may not 6795 be altered or deleted. This is useful in conjunction with 6796 'lituse_jsr' to test whether a weak symbol is defined. 6797 6798 ldq $27,foo($29) !literal!1 6799 beq $27,is_undef !lituse_addr!1 6800 jsr $26,($27),foo !lituse_jsr!1 6801 6802'!lituse_tlsgd!N' 6803 Used with a register branch format instruction to indicate that the 6804 literal is the call to '__tls_get_addr' used to compute the address 6805 of the thread-local storage variable whose descriptor was loaded 6806 with '!tlsgd!N'. 6807 6808'!lituse_tlsldm!N' 6809 Used with a register branch format instruction to indicate that the 6810 literal is the call to '__tls_get_addr' used to compute the address 6811 of the base of the thread-local storage block for the current 6812 module. The descriptor for the module must have been loaded with 6813 '!tlsldm!N'. 6814 6815'!gpdisp!N' 6816 Used with 'ldah' and 'lda' to load the GP from the current address, 6817 a-la the 'ldgp' macro. The source register for the 'ldah' 6818 instruction must contain the address of the 'ldah' instruction. 6819 There must be exactly one 'lda' instruction paired with the 'ldah' 6820 instruction, though it may appear anywhere in the instruction 6821 stream. The immediate operands must be zero. 6822 6823 bsr $26,foo 6824 ldah $29,0($26) !gpdisp!1 6825 lda $29,0($29) !gpdisp!1 6826 6827'!gprelhigh' 6828 Used with an 'ldah' instruction to add the high 16 bits of a 32-bit 6829 displacement from the GP. 6830 6831'!gprellow' 6832 Used with any memory format instruction to add the low 16 bits of a 6833 32-bit displacement from the GP. 6834 6835'!gprel' 6836 Used with any memory format instruction to add a 16-bit 6837 displacement from the GP. 6838 6839'!samegp' 6840 Used with any branch format instruction to skip the GP load at the 6841 target address. The referenced symbol must have the same GP as the 6842 source object file, and it must be declared to either not use '$27' 6843 or perform a standard GP load in the first two instructions via the 6844 '.prologue' directive. 6845 6846'!tlsgd' 6847'!tlsgd!N' 6848 Used with an 'lda' instruction to load the address of a TLS 6849 descriptor for a symbol in the GOT. 6850 6851 The sequence number N is optional, and if present it used to pair 6852 the descriptor load with both the 'literal' loading the address of 6853 the '__tls_get_addr' function and the 'lituse_tlsgd' marking the 6854 call to that function. 6855 6856 For proper relaxation, both the 'tlsgd', 'literal' and 'lituse' 6857 relocations must be in the same extended basic block. That is, the 6858 relocation with the lowest address must be executed first at 6859 runtime. 6860 6861'!tlsldm' 6862'!tlsldm!N' 6863 Used with an 'lda' instruction to load the address of a TLS 6864 descriptor for the current module in the GOT. 6865 6866 Similar in other respects to 'tlsgd'. 6867 6868'!gotdtprel' 6869 Used with an 'ldq' instruction to load the offset of the TLS symbol 6870 within its module's thread-local storage block. Also known as the 6871 dynamic thread pointer offset or dtp-relative offset. 6872 6873'!dtprelhi' 6874'!dtprello' 6875'!dtprel' 6876 Like 'gprel' relocations except they compute dtp-relative offsets. 6877 6878'!gottprel' 6879 Used with an 'ldq' instruction to load the offset of the TLS symbol 6880 from the thread pointer. Also known as the tp-relative offset. 6881 6882'!tprelhi' 6883'!tprello' 6884'!tprel' 6885 Like 'gprel' relocations except they compute tp-relative offsets. 6886 6887 6888File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 6889 68909.2.4 Floating Point 6891-------------------- 6892 6893The Alpha family uses both IEEE and VAX floating-point numbers. 6894 6895 6896File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 6897 68989.2.5 Alpha Assembler Directives 6899-------------------------------- 6900 6901'as' for the Alpha supports many additional directives for compatibility 6902with the native assembler. This section describes them only briefly. 6903 6904 These are the additional directives in 'as' for the Alpha: 6905 6906'.arch CPU' 6907 Specifies the target processor. This is equivalent to the '-mCPU' 6908 command-line option. *Note Options: Alpha Options, for a list of 6909 values for CPU. 6910 6911'.ent FUNCTION[, N]' 6912 Mark the beginning of FUNCTION. An optional number may follow for 6913 compatibility with the OSF/1 assembler, but is ignored. When 6914 generating '.mdebug' information, this will create a procedure 6915 descriptor for the function. In ELF, it will mark the symbol as a 6916 function a-la the generic '.type' directive. 6917 6918'.end FUNCTION' 6919 Mark the end of FUNCTION. In ELF, it will set the size of the 6920 symbol a-la the generic '.size' directive. 6921 6922'.mask MASK, OFFSET' 6923 Indicate which of the integer registers are saved in the current 6924 function's stack frame. MASK is interpreted a bit mask in which 6925 bit N set indicates that register N is saved. The registers are 6926 saved in a block located OFFSET bytes from the "canonical frame 6927 address" (CFA) which is the value of the stack pointer on entry to 6928 the function. The registers are saved sequentially, except that 6929 the return address register (normally '$26') is saved first. 6930 6931 This and the other directives that describe the stack frame are 6932 currently only used when generating '.mdebug' information. They 6933 may in the future be used to generate DWARF2 '.debug_frame' unwind 6934 information for hand written assembly. 6935 6936'.fmask MASK, OFFSET' 6937 Indicate which of the floating-point registers are saved in the 6938 current stack frame. The MASK and OFFSET parameters are 6939 interpreted as with '.mask'. 6940 6941'.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' 6942 Describes the shape of the stack frame. The frame pointer in use 6943 is FRAMEREG; normally this is either '$fp' or '$sp'. The frame 6944 pointer is FRAMEOFFSET bytes below the CFA. The return address is 6945 initially located in RETREG until it is saved as indicated in 6946 '.mask'. For compatibility with OSF/1 an optional ARGOFFSET 6947 parameter is accepted and ignored. It is believed to indicate the 6948 offset from the CFA to the saved argument registers. 6949 6950'.prologue N' 6951 Indicate that the stack frame is set up and all registers have been 6952 spilled. The argument N indicates whether and how the function 6953 uses the incoming "procedure vector" (the address of the called 6954 function) in '$27'. 0 indicates that '$27' is not used; 1 6955 indicates that the first two instructions of the function use '$27' 6956 to perform a load of the GP register; 2 indicates that '$27' is 6957 used in some non-standard way and so the linker cannot elide the 6958 load of the procedure vector during relaxation. 6959 6960'.usepv FUNCTION, WHICH' 6961 Used to indicate the use of the '$27' register, similar to 6962 '.prologue', but without the other semantics of needing to be 6963 inside an open '.ent'/'.end' block. 6964 6965 The WHICH argument should be either 'no', indicating that '$27' is 6966 not used, or 'std', indicating that the first two instructions of 6967 the function perform a GP load. 6968 6969 One might use this directive instead of '.prologue' if you are also 6970 using dwarf2 CFI directives. 6971 6972'.gprel32 EXPRESSION' 6973 Computes the difference between the address in EXPRESSION and the 6974 GP for the current object file, and stores it in 4 bytes. In 6975 addition to being smaller than a full 8 byte address, this also 6976 does not require a dynamic relocation when used in a shared 6977 library. 6978 6979'.t_floating EXPRESSION' 6980 Stores EXPRESSION as an IEEE double precision value. 6981 6982'.s_floating EXPRESSION' 6983 Stores EXPRESSION as an IEEE single precision value. 6984 6985'.f_floating EXPRESSION' 6986 Stores EXPRESSION as a VAX F format value. 6987 6988'.g_floating EXPRESSION' 6989 Stores EXPRESSION as a VAX G format value. 6990 6991'.d_floating EXPRESSION' 6992 Stores EXPRESSION as a VAX D format value. 6993 6994'.set FEATURE' 6995 Enables or disables various assembler features. Using the positive 6996 name of the feature enables while using 'noFEATURE' disables. 6997 6998 'at' 6999 Indicates that macro expansions may clobber the "assembler 7000 temporary" ('$at' or '$28') register. Some macros may not be 7001 expanded without this and will generate an error message if 7002 'noat' is in effect. When 'at' is in effect, a warning will 7003 be generated if '$at' is used by the programmer. 7004 7005 'macro' 7006 Enables the expansion of macro instructions. Note that 7007 variants of real instructions, such as 'br label' vs 'br 7008 $31,label' are considered alternate forms and not macros. 7009 7010 'move' 7011 'reorder' 7012 'volatile' 7013 These control whether and how the assembler may re-order 7014 instructions. Accepted for compatibility with the OSF/1 7015 assembler, but 'as' does not do instruction scheduling, so 7016 these features are ignored. 7017 7018 The following directives are recognized for compatibility with the 7019OSF/1 assembler but are ignored. 7020 7021 .proc .aproc 7022 .reguse .livereg 7023 .option .aent 7024 .ugen .eflag 7025 .alias .noalias 7026 7027 7028File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 7029 70309.2.6 Opcodes 7031------------- 7032 7033For detailed information on the Alpha machine instruction set, see the 7034Alpha Architecture Handbook 7035(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 7036 7037 7038File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 7039 70409.3 ARC Dependent Features 7041========================== 7042 7043* Menu: 7044 7045* ARC Options:: Options 7046* ARC Syntax:: Syntax 7047* ARC Directives:: ARC Machine Directives 7048* ARC Modifiers:: ARC Assembler Modifiers 7049* ARC Symbols:: ARC Pre-defined Symbols 7050* ARC Opcodes:: Opcodes 7051 7052 7053File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 7054 70559.3.1 Options 7056------------- 7057 7058The following options control the type of CPU for which code is 7059assembled, and generic constraints on the code generated: 7060 7061'-mcpu=CPU' 7062 Set architecture type and register usage for CPU. There are also 7063 shortcut alias options available for backward compatibility and 7064 convenience. Supported values for CPU are 7065 7066 'arc600' 7067 Assemble for ARC 600. Aliases: '-mA6', '-mARC600'. 7068 7069 'arc600_norm' 7070 Assemble for ARC 600 with norm instructions. 7071 7072 'arc600_mul64' 7073 Assemble for ARC 600 with mul64 instructions. 7074 7075 'arc600_mul32x16' 7076 Assemble for ARC 600 with mul32x16 instructions. 7077 7078 'arc601' 7079 Assemble for ARC 601. Alias: '-mARC601'. 7080 7081 'arc601_norm' 7082 Assemble for ARC 601 with norm instructions. 7083 7084 'arc601_mul64' 7085 Assemble for ARC 601 with mul64 instructions. 7086 7087 'arc601_mul32x16' 7088 Assemble for ARC 601 with mul32x16 instructions. 7089 7090 'arc700' 7091 Assemble for ARC 700. Aliases: '-mA7', '-mARC700'. 7092 7093 'arcem' 7094 Assemble for ARC EM. Aliases: '-mEM' 7095 7096 'em' 7097 Assemble for ARC EM, identical as arcem variant. 7098 7099 'em4' 7100 Assemble for ARC EM with code-density instructions. 7101 7102 'em4_dmips' 7103 Assemble for ARC EM with code-density instructions. 7104 7105 'em4_fpus' 7106 Assemble for ARC EM with code-density instructions. 7107 7108 'em4_fpuda' 7109 Assemble for ARC EM with code-density, and double-precision 7110 assist instructions. 7111 7112 'quarkse_em' 7113 Assemble for QuarkSE-EM cpu. 7114 7115 'archs' 7116 Assemble for ARC HS. Aliases: '-mHS', '-mav2hs'. 7117 7118 'hs' 7119 Assemble for ARC HS. 7120 7121 'hs34' 7122 Assemble for ARC HS34. 7123 7124 'hs38' 7125 Assemble for ARC HS38. 7126 7127 'hs38_linux' 7128 Assemble for ARC HS38 with floating point support on. 7129 7130 'nps400' 7131 Assemble for ARC 700 with NPS-400 extended instructions. 7132 7133 Note: the '.cpu' directive (*note ARC Directives::) can to be used 7134 to select a core variant from within assembly code. 7135 7136'-EB' 7137 This option specifies that the output generated by the assembler 7138 should be marked as being encoded for a big-endian processor. 7139 7140'-EL' 7141 This option specifies that the output generated by the assembler 7142 should be marked as being encoded for a little-endian processor - 7143 this is the default. 7144 7145'-mcode-density' 7146 This option turns on Code Density instructions. Only valid for ARC 7147 EM processors. 7148 7149'-mrelax' 7150 Enable support for assembly-time relaxation. The assembler will 7151 replace a longer version of an instruction with a shorter one, 7152 whenever it is possible. 7153 7154'-mnps400' 7155 Enable support for NPS-400 extended instructions. 7156 7157'-mspfp' 7158 Enable support for single-precision floating point instructions. 7159 7160'-mdpfp' 7161 Enable support for double-precision floating point instructions. 7162 7163'-mfpuda' 7164 Enable support for double-precision assist floating point 7165 instructions. Only valid for ARC EM processors. 7166 7167 7168File: as.info, Node: ARC Syntax, Next: ARC Directives, Prev: ARC Options, Up: ARC-Dependent 7169 71709.3.2 Syntax 7171------------ 7172 7173* Menu: 7174 7175* ARC-Chars:: Special Characters 7176* ARC-Regs:: Register Names 7177 7178 7179File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 7180 71819.3.2.1 Special Characters 7182.......................... 7183 7184'%' 7185 A register name can optionally be prefixed by a '%' character. So 7186 register '%r0' is equivalent to 'r0' in the assembly code. 7187 7188'#' 7189 The presence of a '#' character within a line (but not at the start 7190 of a line) indicates the start of a comment that extends to the end 7191 of the current line. 7192 7193 _Note:_ if a line starts with a '#' character then it can also be a 7194 logical line number directive (*note Comments::) or a preprocessor 7195 control command (*note Preprocessing::). 7196 7197'@' 7198 Prefixing an operand with an '@' specifies that the operand is a 7199 symbol and not a register. This is how the assembler disambiguates 7200 the use of an ARC register name as a symbol. So the instruction 7201 mov r0, @r0 7202 moves the address of symbol 'r0' into register 'r0'. 7203 7204'`' 7205 The '`' (backtick) character is used to separate statements on a 7206 single line. 7207 7208'-' 7209 Used as a separator to obtain a sequence of commands from a C 7210 preprocessor macro. 7211 7212 7213File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 7214 72159.3.2.2 Register Names 7216...................... 7217 7218The ARC assembler uses the following register names for its core 7219registers: 7220 7221'r0-r31' 7222 The core general registers. Registers 'r26' through 'r31' have 7223 special functions, and are usually referred to by those synonyms. 7224 7225'gp' 7226 The global pointer and a synonym for 'r26'. 7227 7228'fp' 7229 The frame pointer and a synonym for 'r27'. 7230 7231'sp' 7232 The stack pointer and a synonym for 'r28'. 7233 7234'ilink1' 7235 For ARC 600 and ARC 700, the level 1 interrupt link register and a 7236 synonym for 'r29'. Not supported for ARCv2. 7237 7238'ilink' 7239 For ARCv2, the interrupt link register and a synonym for 'r29'. 7240 Not supported for ARC 600 and ARC 700. 7241 7242'ilink2' 7243 For ARC 600 and ARC 700, the level 2 interrupt link register and a 7244 synonym for 'r30'. Not supported for ARC v2. 7245 7246'blink' 7247 The link register and a synonym for 'r31'. 7248 7249'r32-r59' 7250 The extension core registers. 7251 7252'lp_count' 7253 The loop count register. 7254 7255'pcl' 7256 The word aligned program counter. 7257 7258 In addition the ARC processor has a large number of _auxiliary 7259registers_. The precise set depends on the extensions being supported, 7260but the following baseline set are always defined: 7261 7262'identity' 7263 Processor Identification register. Auxiliary register address 0x4. 7264 7265'pc' 7266 Program Counter. Auxiliary register address 0x6. 7267 7268'status32' 7269 Status register. Auxiliary register address 0x0a. 7270 7271'bta' 7272 Branch Target Address. Auxiliary register address 0x412. 7273 7274'ecr' 7275 Exception Cause Register. Auxiliary register address 0x403. 7276 7277'int_vector_base' 7278 Interrupt Vector Base address. Auxiliary register address 0x25. 7279 7280'status32_p0' 7281 Stored STATUS32 register on entry to level P0 interrupts. 7282 Auxiliary register address 0xb. 7283 7284'aux_user_sp' 7285 Saved User Stack Pointer. Auxiliary register address 0xd. 7286 7287'eret' 7288 Exception Return Address. Auxiliary register address 0x400. 7289 7290'erbta' 7291 BTA saved on exception entry. Auxiliary register address 0x401. 7292 7293'erstatus' 7294 STATUS32 saved on exception. Auxiliary register address 0x402. 7295 7296'bcr_ver' 7297 Build Configuration Registers Version. Auxiliary register address 7298 0x60. 7299 7300'bta_link_build' 7301 Build configuration for: BTA Registers. Auxiliary register address 7302 0x63. 7303 7304'vecbase_ac_build' 7305 Build configuration for: Interrupts. Auxiliary register address 7306 0x68. 7307 7308'rf_build' 7309 Build configuration for: Core Registers. Auxiliary register 7310 address 0x6e. 7311 7312'dccm_build' 7313 DCCM RAM Configuration Register. Auxiliary register address 0xc1. 7314 7315 Additional auxiliary register names are defined according to the 7316processor architecture version and extensions selected by the options. 7317 7318 7319File: as.info, Node: ARC Directives, Next: ARC Modifiers, Prev: ARC Syntax, Up: ARC-Dependent 7320 73219.3.3 ARC Machine Directives 7322---------------------------- 7323 7324The ARC version of 'as' supports the following additional machine 7325directives: 7326 7327'.lcomm SYMBOL, LENGTH[, ALIGNMENT]' 7328 Reserve LENGTH (an absolute expression) bytes for a local common 7329 denoted by SYMBOL. The section and value of SYMBOL are those of 7330 the new local common. The addresses are allocated in the bss 7331 section, so that at run-time the bytes start off zeroed. Since 7332 SYMBOL is not declared global, it is normally not visible to 'ld'. 7333 The optional third parameter, ALIGNMENT, specifies the desired 7334 alignment of the symbol in the bss section, specified as a byte 7335 boundary (for example, an alignment of 16 means that the least 7336 significant 4 bits of the address should be zero). The alignment 7337 must be an absolute expression, and it must be a power of two. If 7338 no alignment is specified, as will set the alignment to the largest 7339 power of two less than or equal to the size of the symbol, up to a 7340 maximum of 16. 7341 7342'.lcommon SYMBOL, LENGTH[, ALIGNMENT]' 7343 The same as 'lcomm' directive. 7344 7345'.cpu CPU' 7346 The '.cpu' directive must be followed by the desired core version. 7347 Permitted values for CPU are: 7348 'ARC600' 7349 Assemble for the ARC600 instruction set. 7350 7351 'arc600_norm' 7352 Assemble for ARC 600 with norm instructions. 7353 7354 'arc600_mul64' 7355 Assemble for ARC 600 with mul64 instructions. 7356 7357 'arc600_mul32x16' 7358 Assemble for ARC 600 with mul32x16 instructions. 7359 7360 'arc601' 7361 Assemble for ARC 601 instruction set. 7362 7363 'arc601_norm' 7364 Assemble for ARC 601 with norm instructions. 7365 7366 'arc601_mul64' 7367 Assemble for ARC 601 with mul64 instructions. 7368 7369 'arc601_mul32x16' 7370 Assemble for ARC 601 with mul32x16 instructions. 7371 7372 'ARC700' 7373 Assemble for the ARC700 instruction set. 7374 7375 'NPS400' 7376 Assemble for the NPS400 instruction set. 7377 7378 'EM' 7379 Assemble for the ARC EM instruction set. 7380 7381 'arcem' 7382 Assemble for ARC EM instruction set 7383 7384 'em4' 7385 Assemble for ARC EM with code-density instructions. 7386 7387 'em4_dmips' 7388 Assemble for ARC EM with code-density instructions. 7389 7390 'em4_fpus' 7391 Assemble for ARC EM with code-density instructions. 7392 7393 'em4_fpuda' 7394 Assemble for ARC EM with code-density, and double-precision 7395 assist instructions. 7396 7397 'quarkse_em' 7398 Assemble for QuarkSE-EM instruction set. 7399 7400 'HS' 7401 Assemble for the ARC HS instruction set. 7402 7403 'archs' 7404 Assemble for ARC HS instruction set. 7405 7406 'hs' 7407 Assemble for ARC HS instruction set. 7408 7409 'hs34' 7410 Assemble for ARC HS34 instruction set. 7411 7412 'hs38' 7413 Assemble for ARC HS38 instruction set. 7414 7415 'hs38_linux' 7416 Assemble for ARC HS38 with floating point support on. 7417 7418 Note: the '.cpu' directive overrides the command-line option 7419 '-mcpu=CPU'; a warning is emitted when the version is not 7420 consistent between the two. 7421 7422'.extAuxRegister NAME, ADDR, MODE' 7423 Auxiliary registers can be defined in the assembler source code by 7424 using this directive. The first parameter, NAME, is the name of 7425 the new auxiliary register. The second parameter, ADDR, is address 7426 the of the auxiliary register. The third parameter, MODE, 7427 specifies whether the register is readable and/or writable and is 7428 one of: 7429 'r' 7430 Read only; 7431 7432 'w' 7433 Write only; 7434 7435 'r|w' 7436 Read and write. 7437 7438 For example: 7439 .extAuxRegister mulhi, 0x12, w 7440 specifies a write only extension auxiliary register, MULHI at 7441 address 0x12. 7442 7443'.extCondCode SUFFIX, VAL' 7444 ARC supports extensible condition codes. This directive defines a 7445 new condition code, to be known by the suffix, SUFFIX and will 7446 depend on the value, VAL in the condition code. 7447 7448 For example: 7449 .extCondCode is_busy,0x14 7450 add.is_busy r1,r2,r3 7451 will only execute the 'add' instruction if the condition code value 7452 is 0x14. 7453 7454'.extCoreRegister NAME, REGNUM, MODE, SHORTCUT' 7455 Specifies an extension core register named NAME as a synonym for 7456 the register numbered REGNUM. The register number must be between 7457 32 and 59. The third argument, MODE, indicates whether the 7458 register is readable and/or writable and is one of: 7459 'r' 7460 Read only; 7461 7462 'w' 7463 Write only; 7464 7465 'r|w' 7466 Read and write. 7467 7468 The final parameter, SHORTCUT indicates whether the register has a 7469 short cut in the pipeline. The valid values are: 7470 'can_shortcut' 7471 The register has a short cut in the pipeline; 7472 7473 'cannot_shortcut' 7474 The register does not have a short cut in the pipeline. 7475 7476 For example: 7477 .extCoreRegister mlo, 57, r , can_shortcut 7478 defines a read only extension core register, 'mlo', which is 7479 register 57, and can short cut the pipeline. 7480 7481'.extInstruction NAME, OPCODE, SUBOPCODE, SUFFIXCLASS, SYNTAXCLASS' 7482 ARC allows the user to specify extension instructions. These 7483 extension instructions are not macros; the assembler creates 7484 encodings for use of these instructions according to the 7485 specification by the user. 7486 7487 The first argument, NAME, gives the name of the instruction. 7488 7489 The second argument, OPCODE, is the opcode to be used (bits 31:27 7490 in the encoding). 7491 7492 The third argument, SUBOPCODE, is the sub-opcode to be used, but 7493 the correct value also depends on the fifth argument, SYNTAXCLASS 7494 7495 The fourth argument, SUFFIXCLASS, determines the kinds of suffixes 7496 to be allowed. Valid values are: 7497 'SUFFIX_NONE' 7498 No suffixes are permitted; 7499 7500 'SUFFIX_COND' 7501 Conditional suffixes are permitted; 7502 7503 'SUFFIX_FLAG' 7504 Flag setting suffixes are permitted. 7505 7506 'SUFFIX_COND|SUFFIX_FLAG' 7507 Both conditional and flag setting suffices are permitted. 7508 7509 The fifth and final argument, SYNTAXCLASS, determines the syntax 7510 class for the instruction. It can have the following values: 7511 'SYNTAX_2OP' 7512 Two Operand Instruction; 7513 7514 'SYNTAX_3OP' 7515 Three Operand Instruction. 7516 7517 'SYNTAX_1OP' 7518 One Operand Instruction. 7519 7520 'SYNTAX_NOP' 7521 No Operand Instruction. 7522 7523 The syntax class may be followed by '|' and one of the following 7524 modifiers. 7525 7526 'OP1_MUST_BE_IMM' 7527 Modifies syntax class 'SYNTAX_3OP', specifying that the first 7528 operand of a three-operand instruction must be an immediate 7529 (i.e., the result is discarded). This is usually used to set 7530 the flags using specific instructions and not retain results. 7531 7532 'OP1_IMM_IMPLIED' 7533 Modifies syntax class 'SYNTAX_20P', specifying that there is 7534 an implied immediate destination operand which does not appear 7535 in the syntax. 7536 7537 For example, if the source code contains an instruction like: 7538 inst r1,r2 7539 the first argument is an implied immediate (that is, the 7540 result is discarded). This is the same as though the source 7541 code were: inst 0,r1,r2. 7542 7543 For example, defining a 64-bit multiplier with immediate operands: 7544 .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG, 7545 SYNTAX_3OP|OP1_MUST_BE_IMM 7546 which specifies an extension instruction named 'mp64' with 3 7547 operands. It sets the flags and can be used with a condition code, 7548 for which the first operand is an immediate, i.e. equivalent to 7549 discarding the result of the operation. 7550 7551 A two operands instruction variant would be: 7552 .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND, 7553 SYNTAX_2OP|OP1_IMM_IMPLIED 7554 which describes a two operand instruction with an implicit first 7555 immediate operand. The result of this operation would be 7556 discarded. 7557 7558'.arc_attribute TAG, VALUE' 7559 Set the ARC object attribute TAG to VALUE. 7560 7561 The TAG is either an attribute number, or one of the following: 7562 'Tag_ARC_PCS_config', 'Tag_ARC_CPU_base', 'Tag_ARC_CPU_variation', 7563 'Tag_ARC_CPU_name', 'Tag_ARC_ABI_rf16', 'Tag_ARC_ABI_osver', 7564 'Tag_ARC_ABI_sda', 'Tag_ARC_ABI_pic', 'Tag_ARC_ABI_tls', 7565 'Tag_ARC_ABI_enumsize', 'Tag_ARC_ABI_exceptions', 7566 'Tag_ARC_ABI_double_size', 'Tag_ARC_ISA_config', 7567 'Tag_ARC_ISA_apex', 'Tag_ARC_ISA_mpy_option' 7568 7569 The VALUE is either a 'number', '"string"', or 'number, "string"' 7570 depending on the tag. 7571 7572 7573File: as.info, Node: ARC Modifiers, Next: ARC Symbols, Prev: ARC Directives, Up: ARC-Dependent 7574 75759.3.4 ARC Assembler Modifiers 7576----------------------------- 7577 7578The following additional assembler modifiers have been added for 7579position-independent code. These modifiers are available only with the 7580ARC 700 and above processors and generate relocation entries, which are 7581interpreted by the linker as follows: 7582 7583'@pcl(SYMBOL)' 7584 Relative distance of SYMBOL's from the current program counter 7585 location. 7586 7587'@gotpc(SYMBOL)' 7588 Relative distance of SYMBOL's Global Offset Table entry from the 7589 current program counter location. 7590 7591'@gotoff(SYMBOL)' 7592 Distance of SYMBOL from the base of the Global Offset Table. 7593 7594'@plt(SYMBOL)' 7595 Distance of SYMBOL's Procedure Linkage Table entry from the current 7596 program counter. This is valid only with branch and link 7597 instructions and PC-relative calls. 7598 7599'@sda(SYMBOL)' 7600 Relative distance of SYMBOL from the base of the Small Data 7601 Pointer. 7602 7603 7604File: as.info, Node: ARC Symbols, Next: ARC Opcodes, Prev: ARC Modifiers, Up: ARC-Dependent 7605 76069.3.5 ARC Pre-defined Symbols 7607----------------------------- 7608 7609The following assembler symbols will prove useful when developing 7610position-independent code. These symbols are available only with the 7611ARC 700 and above processors. 7612 7613'__GLOBAL_OFFSET_TABLE__' 7614 Symbol referring to the base of the Global Offset Table. 7615 7616'__DYNAMIC__' 7617 An alias for the Global Offset Table 'Base__GLOBAL_OFFSET_TABLE__'. 7618 It can be used only with '@gotpc' modifiers. 7619 7620 7621File: as.info, Node: ARC Opcodes, Prev: ARC Symbols, Up: ARC-Dependent 7622 76239.3.6 Opcodes 7624------------- 7625 7626For information on the ARC instruction set, see 'ARC Programmers 7627Reference Manual', available where you download the processor IP 7628library. 7629 7630 7631File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 7632 76339.4 ARM Dependent Features 7634========================== 7635 7636* Menu: 7637 7638* ARM Options:: Options 7639* ARM Syntax:: Syntax 7640* ARM Floating Point:: Floating Point 7641* ARM Directives:: ARM Machine Directives 7642* ARM Opcodes:: Opcodes 7643* ARM Mapping Symbols:: Mapping Symbols 7644* ARM Unwinding Tutorial:: Unwinding 7645 7646 7647File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 7648 76499.4.1 Options 7650------------- 7651 7652'-mcpu=PROCESSOR[+EXTENSION...]' 7653 This option specifies the target processor. The assembler will 7654 issue an error message if an attempt is made to assemble an 7655 instruction which will not execute on the target processor. The 7656 following processor names are recognized: 'arm1', 'arm2', 'arm250', 7657 'arm3', 'arm6', 'arm60', 'arm600', 'arm610', 'arm620', 'arm7', 7658 'arm7m', 'arm7d', 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700', 7659 'arm700i', 'arm710', 'arm710t', 'arm720', 'arm720t', 'arm740t', 7660 'arm710c', 'arm7100', 'arm7500', 'arm7500fe', 'arm7t', 'arm7tdmi', 7661 'arm7tdmi-s', 'arm8', 'arm810', 'strongarm', 'strongarm1', 7662 'strongarm110', 'strongarm1100', 'strongarm1110', 'arm9', 'arm920', 7663 'arm920t', 'arm922t', 'arm940t', 'arm9tdmi', 'fa526' (Faraday FA526 7664 processor), 'fa626' (Faraday FA626 processor), 'arm9e', 'arm926e', 7665 'arm926ej-s', 'arm946e-r0', 'arm946e', 'arm946e-s', 'arm966e-r0', 7666 'arm966e', 'arm966e-s', 'arm968e-s', 'arm10t', 'arm10tdmi', 7667 'arm10e', 'arm1020', 'arm1020t', 'arm1020e', 'arm1022e', 7668 'arm1026ej-s', 'fa606te' (Faraday FA606TE processor), 'fa616te' 7669 (Faraday FA616TE processor), 'fa626te' (Faraday FA626TE processor), 7670 'fmp626' (Faraday FMP626 processor), 'fa726te' (Faraday FA726TE 7671 processor), 'arm1136j-s', 'arm1136jf-s', 'arm1156t2-s', 7672 'arm1156t2f-s', 'arm1176jz-s', 'arm1176jzf-s', 'mpcore', 7673 'mpcorenovfp', 'cortex-a5', 'cortex-a7', 'cortex-a8', 'cortex-a9', 7674 'cortex-a15', 'cortex-a17', 'cortex-a32', 'cortex-a35', 7675 'cortex-a53', 'cortex-a55', 'cortex-a57', 'cortex-a72', 7676 'cortex-a73', 'cortex-a75', 'cortex-a76', 'cortex-a76ae', 7677 'cortex-a77', 'ares', 'cortex-r4', 'cortex-r4f', 'cortex-r5', 7678 'cortex-r7', 'cortex-r8', 'cortex-r52', 'cortex-m35p', 7679 'cortex-m33', 'cortex-m23', 'cortex-m7', 'cortex-m4', 'cortex-m3', 7680 'cortex-m1', 'cortex-m0', 'cortex-m0plus', 'exynos-m1', 7681 'marvell-pj4', 'marvell-whitney', 'neoverse-n1', 'xgene1', 7682 'xgene2', 'ep9312' (ARM920 with Cirrus Maverick coprocessor), 7683 'i80200' (Intel XScale processor) 'iwmmxt' (Intel XScale processor 7684 with Wireless MMX technology coprocessor) and 'xscale'. The 7685 special name 'all' may be used to allow the assembler to accept 7686 instructions valid for any ARM processor. 7687 7688 In addition to the basic instruction set, the assembler can be told 7689 to accept various extension mnemonics that extend the processor 7690 using the co-processor instruction space. For example, 7691 '-mcpu=arm920+maverick' is equivalent to specifying '-mcpu=ep9312'. 7692 7693 Multiple extensions may be specified, separated by a '+'. The 7694 extensions should be specified in ascending alphabetical order. 7695 7696 Some extensions may be restricted to particular architectures; this 7697 is documented in the list of extensions below. 7698 7699 Extension mnemonics may also be removed from those the assembler 7700 accepts. This is done be prepending 'no' to the option that adds 7701 the extension. Extensions that are removed should be listed after 7702 all extensions which have been added, again in ascending 7703 alphabetical order. For example, '-mcpu=ep9312+nomaverick' is 7704 equivalent to specifying '-mcpu=arm920'. 7705 7706 The following extensions are currently supported: 'bf16' (BFloat16 7707 extensions for v8.6-A architecture), 'i8mm' (Int8 Matrix Multiply 7708 extensions for v8.6-A architecture), 'crc' 'crypto' (Cryptography 7709 Extensions for v8-A architecture, implies 'fp+simd'), 'dotprod' 7710 (Dot Product Extensions for v8.2-A architecture, implies 7711 'fp+simd'), 'fp' (Floating Point Extensions for v8-A architecture), 7712 'fp16' (FP16 Extensions for v8.2-A architecture, implies 'fp'), 7713 'fp16fml' (FP16 Floating Point Multiplication Variant Extensions 7714 for v8.2-A architecture, implies 'fp16'), 'idiv' (Integer Divide 7715 Extensions for v7-A and v7-R architectures), 'iwmmxt', 'iwmmxt2', 7716 'xscale', 'maverick', 'mp' (Multiprocessing Extensions for v7-A and 7717 v7-R architectures), 'os' (Operating System for v6M architecture), 7718 'predres' (Execution and Data Prediction Restriction Instruction 7719 for v8-A architectures, added by default from v8.5-A), 'sb' 7720 (Speculation Barrier Instruction for v8-A architectures, added by 7721 default from v8.5-A), 'sec' (Security Extensions for v6K and v7-A 7722 architectures), 'simd' (Advanced SIMD Extensions for v8-A 7723 architecture, implies 'fp'), 'virt' (Virtualization Extensions for 7724 v7-A architecture, implies 'idiv'), 'pan' (Privileged Access Never 7725 Extensions for v8-A architecture), 'ras' (Reliability, Availability 7726 and Serviceability extensions for v8-A architecture), 'rdma' 7727 (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies 7728 'simd') and 'xscale'. 7729 7730'-march=ARCHITECTURE[+EXTENSION...]' 7731 This option specifies the target architecture. The assembler will 7732 issue an error message if an attempt is made to assemble an 7733 instruction which will not execute on the target architecture. The 7734 following architecture names are recognized: 'armv1', 'armv2', 7735 'armv2a', 'armv2s', 'armv3', 'armv3m', 'armv4', 'armv4xm', 7736 'armv4t', 'armv4txm', 'armv5', 'armv5t', 'armv5txm', 'armv5te', 7737 'armv5texp', 'armv6', 'armv6j', 'armv6k', 'armv6z', 'armv6kz', 7738 'armv6-m', 'armv6s-m', 'armv7', 'armv7-a', 'armv7ve', 'armv7-r', 7739 'armv7-m', 'armv7e-m', 'armv8-a', 'armv8.1-a', 'armv8.2-a', 7740 'armv8.3-a', 'armv8-r', 'armv8.4-a', 'armv8.5-a', 'armv8-m.base', 7741 'armv8-m.main', 'armv8.1-m.main', 'armv8.6-a', 'iwmmxt', 'iwmmxt2' 7742 and 'xscale'. If both '-mcpu' and '-march' are specified, the 7743 assembler will use the setting for '-mcpu'. 7744 7745 The architecture option can be extended with a set extension 7746 options. These extensions are context sensitive, i.e. the same 7747 extension may mean different things when used with different 7748 architectures. When used together with a '-mfpu' option, the union 7749 of both feature enablement is taken. See their availability and 7750 meaning below: 7751 7752 For 'armv5te', 'armv5texp', 'armv5tej', 'armv6', 'armv6j', 7753 'armv6k', 'armv6z', 'armv6kz', 'armv6zk', 'armv6t2', 'armv6kt2' and 7754 'armv6zt2': 7755 7756 '+fp': Enables VFPv2 instructions. '+nofp': Disables all FPU 7757 instrunctions. 7758 7759 For 'armv7': 7760 7761 '+fp': Enables VFPv3 instructions with 16 double-word registers. 7762 '+nofp': Disables all FPU instructions. 7763 7764 For 'armv7-a': 7765 7766 '+fp': Enables VFPv3 instructions with 16 double-word registers. 7767 '+vfpv3-d16': Alias for '+fp'. '+vfpv3': Enables VFPv3 7768 instructions with 32 double-word registers. '+vfpv3-d16-fp16': 7769 Enables VFPv3 with half precision floating-point conversion 7770 instructions and 16 double-word registers. '+vfpv3-fp16': Enables 7771 VFPv3 with half precision floating-point conversion instructions 7772 and 32 double-word registers. '+vfpv4-d16': Enables VFPv4 7773 instructions with 16 double-word registers. '+vfpv4': Enables 7774 VFPv4 instructions with 32 double-word registers. '+simd': Enables 7775 VFPv3 and NEONv1 instructions with 32 double-word registers. 7776 '+neon': Alias for '+simd'. '+neon-vfpv3': Alias for '+simd'. 7777 '+neon-fp16': Enables VFPv3, half precision floating-point 7778 conversion and NEONv1 instructions with 32 double-word registers. 7779 '+neon-vfpv4': Enables VFPv4 and NEONv1 with Fused-MAC instructions 7780 and 32 double-word registers. '+mp': Enables Multiprocessing 7781 Extensions. '+sec': Enables Security Extensions. '+nofp': 7782 Disables all FPU and NEON instructions. '+nosimd': Disables all 7783 NEON instructions. 7784 7785 For 'armv7ve': 7786 7787 '+fp': Enables VFPv4 instructions with 16 double-word registers. 7788 '+vfpv4-d16': Alias for '+fp'. '+vfpv3-d16': Enables VFPv3 7789 instructions with 16 double-word registers. '+vfpv3': Enables 7790 VFPv3 instructions with 32 double-word registers. 7791 '+vfpv3-d16-fp16': Enables VFPv3 with half precision floating-point 7792 conversion instructions and 16 double-word registers. 7793 '+vfpv3-fp16': Enables VFPv3 with half precision floating-point 7794 conversion instructions and 32 double-word registers. '+vfpv4': 7795 Enables VFPv4 instructions with 32 double-word registers. '+simd': 7796 Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 7797 double-word registers. '+neon-vfpv4': Alias for '+simd'. '+neon': 7798 Enables VFPv3 and NEONv1 instructions with 32 double-word 7799 registers. '+neon-vfpv3': Alias for '+neon'. '+neon-fp16': 7800 Enables VFPv3, half precision floating-point conversion and NEONv1 7801 instructions with 32 double-word registers. double-word registers. 7802 '+nofp': Disables all FPU and NEON instructions. '+nosimd': 7803 Disables all NEON instructions. 7804 7805 For 'armv7-r': 7806 7807 '+fp.sp': Enables single-precision only VFPv3 instructions with 16 7808 double-word registers. '+vfpv3xd': Alias for '+fp.sp'. '+fp': 7809 Enables VFPv3 instructions with 16 double-word registers. 7810 '+vfpv3-d16': Alias for '+fp'. '+vfpv3xd-fp16': Enables 7811 single-precision only VFPv3 and half floating-point conversion 7812 instructions with 16 double-word registers. '+vfpv3-d16-fp16': 7813 Enables VFPv3 and half precision floating-point conversion 7814 instructions with 16 double-word registers. '+idiv': Enables 7815 integer division instructions in ARM mode. '+nofp': Disables all 7816 FPU instructions. 7817 7818 For 'armv7e-m': 7819 7820 '+fp': Enables single-precision only VFPv4 instructions with 16 7821 double-word registers. '+vfpvf4-sp-d16': Alias for '+fp'. 7822 '+fpv5': Enables single-precision only VFPv5 instructions with 16 7823 double-word registers. '+fp.dp': Enables VFPv5 instructions with 7824 16 double-word registers. '+fpv5-d16"': Alias for '+fp.dp'. 7825 '+nofp': Disables all FPU instructions. 7826 7827 For 'armv8-m.main': 7828 7829 '+dsp': Enables DSP Extension. '+fp': Enables single-precision 7830 only VFPv5 instructions with 16 double-word registers. '+fp.dp': 7831 Enables VFPv5 instructions with 16 double-word registers. '+nofp': 7832 Disables all FPU instructions. '+nodsp': Disables DSP Extension. 7833 7834 For 'armv8.1-m.main': 7835 7836 '+dsp': Enables DSP Extension. '+fp': Enables single and half 7837 precision scalar Floating Point Extensions for Armv8.1-M Mainline 7838 with 16 double-word registers. '+fp.dp': Enables double precision 7839 scalar Floating Point Extensions for Armv8.1-M Mainline, implies 7840 '+fp'. '+mve': Enables integer only M-profile Vector Extension for 7841 Armv8.1-M Mainline, implies '+dsp'. '+mve.fp': Enables Floating 7842 Point M-profile Vector Extension for Armv8.1-M Mainline, implies 7843 '+mve' and '+fp'. '+nofp': Disables all FPU instructions. 7844 '+nodsp': Disables DSP Extension. '+nomve': Disables all M-profile 7845 Vector Extensions. 7846 7847 For 'armv8-a': 7848 7849 '+crc': Enables CRC32 Extension. '+simd': Enables VFP and NEON for 7850 Armv8-A. '+crypto': Enables Cryptography Extensions for Armv8-A, 7851 implies '+simd'. '+sb': Enables Speculation Barrier Instruction 7852 for Armv8-A. '+predres': Enables Execution and Data Prediction 7853 Restriction Instruction for Armv8-A. '+nofp': Disables all FPU, 7854 NEON and Cryptography Extensions. '+nocrypto': Disables 7855 Cryptography Extensions. 7856 7857 For 'armv8.1-a': 7858 7859 '+simd': Enables VFP and NEON for Armv8.1-A. '+crypto': Enables 7860 Cryptography Extensions for Armv8-A, implies '+simd'. '+sb': 7861 Enables Speculation Barrier Instruction for Armv8-A. '+predres': 7862 Enables Execution and Data Prediction Restriction Instruction for 7863 Armv8-A. '+nofp': Disables all FPU, NEON and Cryptography 7864 Extensions. '+nocrypto': Disables Cryptography Extensions. 7865 7866 For 'armv8.2-a' and 'armv8.3-a': 7867 7868 '+simd': Enables VFP and NEON for Armv8.1-A. '+fp16': Enables FP16 7869 Extension for Armv8.2-A, implies '+simd'. '+fp16fml': Enables FP16 7870 Floating Point Multiplication Variant Extensions for Armv8.2-A, 7871 implies '+fp16'. '+crypto': Enables Cryptography Extensions for 7872 Armv8-A, implies '+simd'. '+dotprod': Enables Dot Product 7873 Extensions for Armv8.2-A, implies '+simd'. '+sb': Enables 7874 Speculation Barrier Instruction for Armv8-A. '+predres': Enables 7875 Execution and Data Prediction Restriction Instruction for Armv8-A. 7876 '+nofp': Disables all FPU, NEON, Cryptography and Dot Product 7877 Extensions. '+nocrypto': Disables Cryptography Extensions. 7878 7879 For 'armv8.4-a': 7880 7881 '+simd': Enables VFP and NEON for Armv8.1-A and Dot Product 7882 Extensions for Armv8.2-A. '+fp16': Enables FP16 Floating Point and 7883 Floating Point Multiplication Variant Extensions for Armv8.2-A, 7884 implies '+simd'. '+crypto': Enables Cryptography Extensions for 7885 Armv8-A, implies '+simd'. '+sb': Enables Speculation Barrier 7886 Instruction for Armv8-A. '+predres': Enables Execution and Data 7887 Prediction Restriction Instruction for Armv8-A. '+nofp': Disables 7888 all FPU, NEON, Cryptography and Dot Product Extensions. 7889 '+nocryptp': Disables Cryptography Extensions. 7890 7891 For 'armv8.5-a': 7892 7893 '+simd': Enables VFP and NEON for Armv8.1-A and Dot Product 7894 Extensions for Armv8.2-A. '+fp16': Enables FP16 Floating Point and 7895 Floating Point Multiplication Variant Extensions for Armv8.2-A, 7896 implies '+simd'. '+crypto': Enables Cryptography Extensions for 7897 Armv8-A, implies '+simd'. '+nofp': Disables all FPU, NEON, 7898 Cryptography and Dot Product Extensions. '+nocryptp': Disables 7899 Cryptography Extensions. 7900 7901'-mfpu=FLOATING-POINT-FORMAT' 7902 7903 This option specifies the floating point format to assemble for. 7904 The assembler will issue an error message if an attempt is made to 7905 assemble an instruction which will not execute on the target 7906 floating point unit. The following format options are recognized: 7907 'softfpa', 'fpe', 'fpe2', 'fpe3', 'fpa', 'fpa10', 'fpa11', 7908 'arm7500fe', 'softvfp', 'softvfp+vfp', 'vfp', 'vfp10', 'vfp10-r0', 7909 'vfp9', 'vfpxd', 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16', 7910 'vfpv3-d16-fp16', 'vfpv3xd', 'vfpv3xd-d16', 'vfpv4', 'vfpv4-d16', 7911 'fpv4-sp-d16', 'fpv5-sp-d16', 'fpv5-d16', 'fp-armv8', 'arm1020t', 7912 'arm1020e', 'arm1136jf-s', 'maverick', 'neon', 'neon-vfpv3', 7913 'neon-fp16', 'neon-vfpv4', 'neon-fp-armv8', 'crypto-neon-fp-armv8', 7914 'neon-fp-armv8.1' and 'crypto-neon-fp-armv8.1'. 7915 7916 In addition to determining which instructions are assembled, this 7917 option also affects the way in which the '.double' assembler 7918 directive behaves when assembling little-endian code. 7919 7920 The default is dependent on the processor selected. For 7921 Architecture 5 or later, the default is to assemble for VFP 7922 instructions; for earlier architectures the default is to assemble 7923 for FPA instructions. 7924 7925'-mfp16-format=FORMAT' 7926 This option specifies the half-precision floating point format to 7927 use when assembling floating point numbers emitted by the 7928 '.float16' directive. The following format options are recognized: 7929 'ieee', 'alternative'. If 'ieee' is specified then the IEEE 7930 754-2008 half-precision floating point format is used, if 7931 'alternative' is specified then the Arm alternative half-precision 7932 format is used. If this option is set on the command line then the 7933 format is fixed and cannot be changed with the 'float16_format' 7934 directive. If this value is not set then the IEEE 754-2008 format 7935 is used until the format is explicitly set with the 7936 'float16_format' directive. 7937 7938'-mthumb' 7939 This option specifies that the assembler should start assembling 7940 Thumb instructions; that is, it should behave as though the file 7941 starts with a '.code 16' directive. 7942 7943'-mthumb-interwork' 7944 This option specifies that the output generated by the assembler 7945 should be marked as supporting interworking. It also affects the 7946 behaviour of the 'ADR' and 'ADRL' pseudo opcodes. 7947 7948'-mimplicit-it=never' 7949'-mimplicit-it=always' 7950'-mimplicit-it=arm' 7951'-mimplicit-it=thumb' 7952 The '-mimplicit-it' option controls the behavior of the assembler 7953 when conditional instructions are not enclosed in IT blocks. There 7954 are four possible behaviors. If 'never' is specified, such 7955 constructs cause a warning in ARM code and an error in Thumb-2 7956 code. If 'always' is specified, such constructs are accepted in 7957 both ARM and Thumb-2 code, where the IT instruction is added 7958 implicitly. If 'arm' is specified, such constructs are accepted in 7959 ARM code and cause an error in Thumb-2 code. If 'thumb' is 7960 specified, such constructs cause a warning in ARM code and are 7961 accepted in Thumb-2 code. If you omit this option, the behavior is 7962 equivalent to '-mimplicit-it=arm'. 7963 7964'-mapcs-26' 7965'-mapcs-32' 7966 These options specify that the output generated by the assembler 7967 should be marked as supporting the indicated version of the Arm 7968 Procedure. Calling Standard. 7969 7970'-matpcs' 7971 This option specifies that the output generated by the assembler 7972 should be marked as supporting the Arm/Thumb Procedure Calling 7973 Standard. If enabled this option will cause the assembler to 7974 create an empty debugging section in the object file called 7975 .arm.atpcs. Debuggers can use this to determine the ABI being used 7976 by. 7977 7978'-mapcs-float' 7979 This indicates the floating point variant of the APCS should be 7980 used. In this variant floating point arguments are passed in FP 7981 registers rather than integer registers. 7982 7983'-mapcs-reentrant' 7984 This indicates that the reentrant variant of the APCS should be 7985 used. This variant supports position independent code. 7986 7987'-mfloat-abi=ABI' 7988 This option specifies that the output generated by the assembler 7989 should be marked as using specified floating point ABI. The 7990 following values are recognized: 'soft', 'softfp' and 'hard'. 7991 7992'-meabi=VER' 7993 This option specifies which EABI version the produced object files 7994 should conform to. The following values are recognized: 'gnu', '4' 7995 and '5'. 7996 7997'-EB' 7998 This option specifies that the output generated by the assembler 7999 should be marked as being encoded for a big-endian processor. 8000 8001 Note: If a program is being built for a system with big-endian data 8002 and little-endian instructions then it should be assembled with the 8003 '-EB' option, (all of it, code and data) and then linked with the 8004 '--be8' option. This will reverse the endianness of the 8005 instructions back to little-endian, but leave the data as 8006 big-endian. 8007 8008'-EL' 8009 This option specifies that the output generated by the assembler 8010 should be marked as being encoded for a little-endian processor. 8011 8012'-k' 8013 This option specifies that the output of the assembler should be 8014 marked as position-independent code (PIC). 8015 8016'--fix-v4bx' 8017 Allow 'BX' instructions in ARMv4 code. This is intended for use 8018 with the linker option of the same name. 8019 8020'-mwarn-deprecated' 8021'-mno-warn-deprecated' 8022 Enable or disable warnings about using deprecated options or 8023 features. The default is to warn. 8024 8025'-mccs' 8026 Turns on CodeComposer Studio assembly syntax compatibility mode. 8027 8028'-mwarn-syms' 8029'-mno-warn-syms' 8030 Enable or disable warnings about symbols that match the names of 8031 ARM instructions. The default is to warn. 8032 8033 8034File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 8035 80369.4.2 Syntax 8037------------ 8038 8039* Menu: 8040 8041* ARM-Instruction-Set:: Instruction Set 8042* ARM-Chars:: Special Characters 8043* ARM-Regs:: Register Names 8044* ARM-Relocations:: Relocations 8045* ARM-Neon-Alignment:: NEON Alignment Specifiers 8046 8047 8048File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 8049 80509.4.2.1 Instruction Set Syntax 8051.............................. 8052 8053Two slightly different syntaxes are support for ARM and THUMB 8054instructions. The default, 'divided', uses the old style where ARM and 8055THUMB instructions had their own, separate syntaxes. The new, 'unified' 8056syntax, which can be selected via the '.syntax' directive, and has the 8057following main features: 8058 8059 * Immediate operands do not require a '#' prefix. 8060 8061 * The 'IT' instruction may appear, and if it does it is validated 8062 against subsequent conditional affixes. In ARM mode it does not 8063 generate machine code, in THUMB mode it does. 8064 8065 * For ARM instructions the conditional affixes always appear at the 8066 end of the instruction. For THUMB instructions conditional affixes 8067 can be used, but only inside the scope of an 'IT' instruction. 8068 8069 * All of the instructions new to the V6T2 architecture (and later) 8070 are available. (Only a few such instructions can be written in the 8071 'divided' syntax). 8072 8073 * The '.N' and '.W' suffixes are recognized and honored. 8074 8075 * All instructions set the flags if and only if they have an 's' 8076 affix. 8077 8078 8079File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 8080 80819.4.2.2 Special Characters 8082.......................... 8083 8084The presence of a '@' anywhere on a line indicates the start of a 8085comment that extends to the end of that line. 8086 8087 If a '#' appears as the first character of a line then the whole line 8088is treated as a comment, but in this case the line could also be a 8089logical line number directive (*note Comments::) or a preprocessor 8090control command (*note Preprocessing::). 8091 8092 The ';' character can be used instead of a newline to separate 8093statements. 8094 8095 Either '#' or '$' can be used to indicate immediate operands. 8096 8097 *TODO* Explain about /data modifier on symbols. 8098 8099 8100File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 8101 81029.4.2.3 Register Names 8103...................... 8104 8105*TODO* Explain about ARM register naming, and the predefined names. 8106 8107 8108File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 8109 81109.4.2.4 ARM relocation generation 8111................................. 8112 8113Specific data relocations can be generated by putting the relocation 8114name in parentheses after the symbol name. For example: 8115 8116 .word foo(TARGET1) 8117 8118 This will generate an 'R_ARM_TARGET1' relocation against the symbol 8119FOO. The following relocations are supported: 'GOT', 'GOTOFF', 8120'TARGET1', 'TARGET2', 'SBREL', 'TLSGD', 'TLSLDM', 'TLSLDO', 'TLSDESC', 8121'TLSCALL', 'GOTTPOFF', 'GOT_PREL' and 'TPOFF'. 8122 8123 For compatibility with older toolchains the assembler also accepts 8124'(PLT)' after branch targets. On legacy targets this will generate the 8125deprecated 'R_ARM_PLT32' relocation. On EABI targets it will encode 8126either the 'R_ARM_CALL' or 'R_ARM_JUMP24' relocation, as appropriate. 8127 8128 Relocations for 'MOVW' and 'MOVT' instructions can be generated by 8129prefixing the value with '#:lower16:' and '#:upper16' respectively. For 8130example to load the 32-bit address of foo into r0: 8131 8132 MOVW r0, #:lower16:foo 8133 MOVT r0, #:upper16:foo 8134 8135 Relocations 'R_ARM_THM_ALU_ABS_G0_NC', 'R_ARM_THM_ALU_ABS_G1_NC', 8136'R_ARM_THM_ALU_ABS_G2_NC' and 'R_ARM_THM_ALU_ABS_G3_NC' can be generated 8137by prefixing the value with '#:lower0_7:#', '#:lower8_15:#', 8138'#:upper0_7:#' and '#:upper8_15:#' respectively. For example to load 8139the 32-bit address of foo into r0: 8140 8141 MOVS r0, #:upper8_15:#foo 8142 LSLS r0, r0, #8 8143 ADDS r0, #:upper0_7:#foo 8144 LSLS r0, r0, #8 8145 ADDS r0, #:lower8_15:#foo 8146 LSLS r0, r0, #8 8147 ADDS r0, #:lower0_7:#foo 8148 8149 8150File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 8151 81529.4.2.5 NEON Alignment Specifiers 8153................................. 8154 8155Some NEON load/store instructions allow an optional address alignment 8156qualifier. The ARM documentation specifies that this is indicated by '@ 8157ALIGN'. However GAS already interprets the '@' character as a "line 8158comment" start, so ': ALIGN' is used instead. For example: 8159 8160 vld1.8 {q0}, [r0, :128] 8161 8162 8163File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 8164 81659.4.3 Floating Point 8166-------------------- 8167 8168The ARM family uses IEEE floating-point numbers. 8169 8170 8171File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 8172 81739.4.4 ARM Machine Directives 8174---------------------------- 8175 8176'.align EXPRESSION [, EXPRESSION]' 8177 This is the generic .ALIGN directive. For the ARM however if the 8178 first argument is zero (ie no alignment is needed) the assembler 8179 will behave as if the argument had been 2 (ie pad to the next four 8180 byte boundary). This is for compatibility with ARM's own 8181 assembler. 8182 8183'.arch NAME' 8184 Select the target architecture. Valid values for NAME are the same 8185 as for the '-march' command-line option without the instruction set 8186 extension. 8187 8188 Specifying '.arch' clears any previously selected architecture 8189 extensions. 8190 8191'.arch_extension NAME' 8192 Add or remove an architecture extension to the target architecture. 8193 Valid values for NAME are the same as those accepted as 8194 architectural extensions by the '-mcpu' and '-march' command-line 8195 options. 8196 8197 '.arch_extension' may be used multiple times to add or remove 8198 extensions incrementally to the architecture being compiled for. 8199 8200'.arm' 8201 This performs the same action as .CODE 32. 8202 8203'.bss' 8204 This directive switches to the '.bss' section. 8205 8206'.cantunwind' 8207 Prevents unwinding through the current function. No personality 8208 routine or exception table data is required or permitted. 8209 8210'.code [16|32]' 8211 This directive selects the instruction set being generated. The 8212 value 16 selects Thumb, with the value 32 selecting ARM. 8213 8214'.cpu NAME' 8215 Select the target processor. Valid values for NAME are the same as 8216 for the '-mcpu' command-line option without the instruction set 8217 extension. 8218 8219 Specifying '.cpu' clears any previously selected architecture 8220 extensions. 8221 8222'NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' 8223'NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' 8224 8225 The 'dn' and 'qn' directives are used to create typed and/or 8226 indexed register aliases for use in Advanced SIMD Extension (Neon) 8227 instructions. The former should be used to create aliases of 8228 double-precision registers, and the latter to create aliases of 8229 quad-precision registers. 8230 8231 If these directives are used to create typed aliases, those aliases 8232 can be used in Neon instructions instead of writing types after the 8233 mnemonic or after each operand. For example: 8234 8235 x .dn d2.f32 8236 y .dn d3.f32 8237 z .dn d4.f32[1] 8238 vmul x,y,z 8239 8240 This is equivalent to writing the following: 8241 8242 vmul.f32 d2,d3,d4[1] 8243 8244 Aliases created using 'dn' or 'qn' can be destroyed using 'unreq'. 8245 8246'.eabi_attribute TAG, VALUE' 8247 Set the EABI object attribute TAG to VALUE. 8248 8249 The TAG is either an attribute number, or one of the following: 8250 'Tag_CPU_raw_name', 'Tag_CPU_name', 'Tag_CPU_arch', 8251 'Tag_CPU_arch_profile', 'Tag_ARM_ISA_use', 'Tag_THUMB_ISA_use', 8252 'Tag_FP_arch', 'Tag_WMMX_arch', 'Tag_Advanced_SIMD_arch', 8253 'Tag_MVE_arch', 'Tag_PCS_config', 'Tag_ABI_PCS_R9_use', 8254 'Tag_ABI_PCS_RW_data', 'Tag_ABI_PCS_RO_data', 8255 'Tag_ABI_PCS_GOT_use', 'Tag_ABI_PCS_wchar_t', 8256 'Tag_ABI_FP_rounding', 'Tag_ABI_FP_denormal', 8257 'Tag_ABI_FP_exceptions', 'Tag_ABI_FP_user_exceptions', 8258 'Tag_ABI_FP_number_model', 'Tag_ABI_align_needed', 8259 'Tag_ABI_align_preserved', 'Tag_ABI_enum_size', 8260 'Tag_ABI_HardFP_use', 'Tag_ABI_VFP_args', 'Tag_ABI_WMMX_args', 8261 'Tag_ABI_optimization_goals', 'Tag_ABI_FP_optimization_goals', 8262 'Tag_compatibility', 'Tag_CPU_unaligned_access', 8263 'Tag_FP_HP_extension', 'Tag_ABI_FP_16bit_format', 8264 'Tag_MPextension_use', 'Tag_DIV_use', 'Tag_nodefaults', 8265 'Tag_also_compatible_with', 'Tag_conformance', 'Tag_T2EE_use', 8266 'Tag_Virtualization_use' 8267 8268 The VALUE is either a 'number', '"string"', or 'number, "string"' 8269 depending on the tag. 8270 8271 Note - the following legacy values are also accepted by TAG: 8272 'Tag_VFP_arch', 'Tag_ABI_align8_needed', 8273 'Tag_ABI_align8_preserved', 'Tag_VFP_HP_extension', 8274 8275'.even' 8276 This directive aligns to an even-numbered address. 8277 8278'.extend EXPRESSION [, EXPRESSION]*' 8279'.ldouble EXPRESSION [, EXPRESSION]*' 8280 These directives write 12byte long double floating-point values to 8281 the output section. These are not compatible with current ARM 8282 processors or ABIs. 8283 8284'.float16 VALUE [,...,VALUE_N]' 8285 Place the half precision floating point representation of one or 8286 more floating-point values into the current section. The exact 8287 format of the encoding is specified by '.float16_format'. If the 8288 format has not been explicitly set yet (either via the 8289 '.float16_format' directive or the command line option) then the 8290 IEEE 754-2008 format is used. 8291 8292'.float16_format FORMAT' 8293 Set the format to use when encoding float16 values emitted by the 8294 '.float16' directive. Once the format has been set it cannot be 8295 changed. 'format' should be one of the following: 'ieee' (encode 8296 in the IEEE 754-2008 half precision format) or 'alternative' 8297 (encode in the Arm alternative half precision format). 8298 8299'.fnend' 8300 Marks the end of a function with an unwind table entry. The unwind 8301 index table entry is created when this directive is processed. 8302 8303 If no personality routine has been specified then standard 8304 personality routine 0 or 1 will be used, depending on the number of 8305 unwind opcodes required. 8306 8307'.fnstart' 8308 Marks the start of a function with an unwind table entry. 8309 8310'.force_thumb' 8311 This directive forces the selection of Thumb instructions, even if 8312 the target processor does not support those instructions 8313 8314'.fpu NAME' 8315 Select the floating-point unit to assemble for. Valid values for 8316 NAME are the same as for the '-mfpu' command-line option. 8317 8318'.handlerdata' 8319 Marks the end of the current function, and the start of the 8320 exception table entry for that function. Anything between this 8321 directive and the '.fnend' directive will be added to the exception 8322 table entry. 8323 8324 Must be preceded by a '.personality' or '.personalityindex' 8325 directive. 8326 8327'.inst OPCODE [ , ... ]' 8328'.inst.n OPCODE [ , ... ]' 8329'.inst.w OPCODE [ , ... ]' 8330 Generates the instruction corresponding to the numerical value 8331 OPCODE. '.inst.n' and '.inst.w' allow the Thumb instruction size 8332 to be specified explicitly, overriding the normal encoding rules. 8333 8334'.ldouble EXPRESSION [, EXPRESSION]*' 8335 See '.extend'. 8336 8337'.ltorg' 8338 This directive causes the current contents of the literal pool to 8339 be dumped into the current section (which is assumed to be the 8340 .text section) at the current location (aligned to a word 8341 boundary). 'GAS' maintains a separate literal pool for each 8342 section and each sub-section. The '.ltorg' directive will only 8343 affect the literal pool of the current section and sub-section. At 8344 the end of assembly all remaining, un-empty literal pools will 8345 automatically be dumped. 8346 8347 Note - older versions of 'GAS' would dump the current literal pool 8348 any time a section change occurred. This is no longer done, since 8349 it prevents accurate control of the placement of literal pools. 8350 8351'.movsp REG [, #OFFSET]' 8352 Tell the unwinder that REG contains an offset from the current 8353 stack pointer. If OFFSET is not specified then it is assumed to be 8354 zero. 8355 8356'.object_arch NAME' 8357 Override the architecture recorded in the EABI object attribute 8358 section. Valid values for NAME are the same as for the '.arch' 8359 directive. Typically this is useful when code uses runtime 8360 detection of CPU features. 8361 8362'.packed EXPRESSION [, EXPRESSION]*' 8363 This directive writes 12-byte packed floating-point values to the 8364 output section. These are not compatible with current ARM 8365 processors or ABIs. 8366 8367'.pad #COUNT' 8368 Generate unwinder annotations for a stack adjustment of COUNT 8369 bytes. A positive value indicates the function prologue allocated 8370 stack space by decrementing the stack pointer. 8371 8372'.personality NAME' 8373 Sets the personality routine for the current function to NAME. 8374 8375'.personalityindex INDEX' 8376 Sets the personality routine for the current function to the EABI 8377 standard routine number INDEX 8378 8379'.pool' 8380 This is a synonym for .ltorg. 8381 8382'NAME .req REGISTER NAME' 8383 This creates an alias for REGISTER NAME called NAME. For example: 8384 8385 foo .req r0 8386 8387'.save REGLIST' 8388 Generate unwinder annotations to restore the registers in REGLIST. 8389 The format of REGLIST is the same as the corresponding 8390 store-multiple instruction. 8391 8392 _core registers_ 8393 .save {r4, r5, r6, lr} 8394 stmfd sp!, {r4, r5, r6, lr} 8395 _FPA registers_ 8396 .save f4, 2 8397 sfmfd f4, 2, [sp]! 8398 _VFP registers_ 8399 .save {d8, d9, d10} 8400 fstmdx sp!, {d8, d9, d10} 8401 _iWMMXt registers_ 8402 .save {wr10, wr11} 8403 wstrd wr11, [sp, #-8]! 8404 wstrd wr10, [sp, #-8]! 8405 or 8406 .save wr11 8407 wstrd wr11, [sp, #-8]! 8408 .save wr10 8409 wstrd wr10, [sp, #-8]! 8410 8411'.setfp FPREG, SPREG [, #OFFSET]' 8412 Make all unwinder annotations relative to a frame pointer. Without 8413 this the unwinder will use offsets from the stack pointer. 8414 8415 The syntax of this directive is the same as the 'add' or 'mov' 8416 instruction used to set the frame pointer. SPREG must be either 8417 'sp' or mentioned in a previous '.movsp' directive. 8418 8419 .movsp ip 8420 mov ip, sp 8421 ... 8422 .setfp fp, ip, #4 8423 add fp, ip, #4 8424 8425'.secrel32 EXPRESSION [, EXPRESSION]*' 8426 This directive emits relocations that evaluate to the 8427 section-relative offset of each expression's symbol. This 8428 directive is only supported for PE targets. 8429 8430'.syntax [unified | divided]' 8431 This directive sets the Instruction Set Syntax as described in the 8432 *note ARM-Instruction-Set:: section. 8433 8434'.thumb' 8435 This performs the same action as .CODE 16. 8436 8437'.thumb_func' 8438 This directive specifies that the following symbol is the name of a 8439 Thumb encoded function. This information is necessary in order to 8440 allow the assembler and linker to generate correct code for 8441 interworking between Arm and Thumb instructions and should be used 8442 even if interworking is not going to be performed. The presence of 8443 this directive also implies '.thumb' 8444 8445 This directive is not necessary when generating EABI objects. On 8446 these targets the encoding is implicit when generating Thumb code. 8447 8448'.thumb_set' 8449 This performs the equivalent of a '.set' directive in that it 8450 creates a symbol which is an alias for another symbol (possibly not 8451 yet defined). This directive also has the added property in that 8452 it marks the aliased symbol as being a thumb function entry point, 8453 in the same way that the '.thumb_func' directive does. 8454 8455'.tlsdescseq TLS-VARIABLE' 8456 This directive is used to annotate parts of an inlined TLS 8457 descriptor trampoline. Normally the trampoline is provided by the 8458 linker, and this directive is not needed. 8459 8460'.unreq ALIAS-NAME' 8461 This undefines a register alias which was previously defined using 8462 the 'req', 'dn' or 'qn' directives. For example: 8463 8464 foo .req r0 8465 .unreq foo 8466 8467 An error occurs if the name is undefined. Note - this pseudo op 8468 can be used to delete builtin in register name aliases (eg 'r0'). 8469 This should only be done if it is really necessary. 8470 8471'.unwind_raw OFFSET, BYTE1, ...' 8472 Insert one of more arbitrary unwind opcode bytes, which are known 8473 to adjust the stack pointer by OFFSET bytes. 8474 8475 For example '.unwind_raw 4, 0xb1, 0x01' is equivalent to '.save 8476 {r0}' 8477 8478'.vsave VFP-REGLIST' 8479 Generate unwinder annotations to restore the VFP registers in 8480 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are to 8481 be restored using VLDM. The format of VFP-REGLIST is the same as 8482 the corresponding store-multiple instruction. 8483 8484 _VFP registers_ 8485 .vsave {d8, d9, d10} 8486 fstmdd sp!, {d8, d9, d10} 8487 _VFPv3 registers_ 8488 .vsave {d15, d16, d17} 8489 vstm sp!, {d15, d16, d17} 8490 8491 Since FLDMX and FSTMX are now deprecated, this directive should be 8492 used in favour of '.save' for saving VFP registers for ARMv6 and 8493 above. 8494 8495 8496File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 8497 84989.4.5 Opcodes 8499------------- 8500 8501'as' implements all the standard ARM opcodes. It also implements 8502several pseudo opcodes, including several synthetic load instructions. 8503 8504'NOP' 8505 nop 8506 8507 This pseudo op will always evaluate to a legal ARM instruction that 8508 does nothing. Currently it will evaluate to MOV r0, r0. 8509 8510'LDR' 8511 ldr <register> , = <expression> 8512 8513 If expression evaluates to a numeric constant then a MOV or MVN 8514 instruction will be used in place of the LDR instruction, if the 8515 constant can be generated by either of these instructions. 8516 Otherwise the constant will be placed into the nearest literal pool 8517 (if it not already there) and a PC relative LDR instruction will be 8518 generated. 8519 8520'ADR' 8521 adr <register> <label> 8522 8523 This instruction will load the address of LABEL into the indicated 8524 register. The instruction will evaluate to a PC relative ADD or 8525 SUB instruction depending upon where the label is located. If the 8526 label is out of range, or if it is not defined in the same file 8527 (and section) as the ADR instruction, then an error will be 8528 generated. This instruction will not make use of the literal pool. 8529 8530 If LABEL is a thumb function symbol, and thumb interworking has 8531 been enabled via the '-mthumb-interwork' option then the bottom bit 8532 of the value stored into REGISTER will be set. This allows the 8533 following sequence to work as expected: 8534 8535 adr r0, thumb_function 8536 blx r0 8537 8538'ADRL' 8539 adrl <register> <label> 8540 8541 This instruction will load the address of LABEL into the indicated 8542 register. The instruction will evaluate to one or two PC relative 8543 ADD or SUB instructions depending upon where the label is located. 8544 If a second instruction is not needed a NOP instruction will be 8545 generated in its place, so that this instruction is always 8 bytes 8546 long. 8547 8548 If the label is out of range, or if it is not defined in the same 8549 file (and section) as the ADRL instruction, then an error will be 8550 generated. This instruction will not make use of the literal pool. 8551 8552 If LABEL is a thumb function symbol, and thumb interworking has 8553 been enabled via the '-mthumb-interwork' option then the bottom bit 8554 of the value stored into REGISTER will be set. 8555 8556 For information on the ARM or Thumb instruction sets, see 'ARM 8557Software Development Toolkit Reference Manual', Advanced RISC Machines 8558Ltd. 8559 8560 8561File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 8562 85639.4.6 Mapping Symbols 8564--------------------- 8565 8566The ARM ELF specification requires that special symbols be inserted into 8567object files to mark certain features: 8568 8569'$a' 8570 At the start of a region of code containing ARM instructions. 8571 8572'$t' 8573 At the start of a region of code containing THUMB instructions. 8574 8575'$d' 8576 At the start of a region of data. 8577 8578 The assembler will automatically insert these symbols for you - there 8579is no need to code them yourself. Support for tagging symbols ($b, $f, 8580$p and $m) which is also mentioned in the current ARM ELF specification 8581is not implemented. This is because they have been dropped from the new 8582EABI and so tools cannot rely upon their presence. 8583 8584 8585File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 8586 85879.4.7 Unwinding 8588--------------- 8589 8590The ABI for the ARM Architecture specifies a standard format for 8591exception unwind information. This information is used when an 8592exception is thrown to determine where control should be transferred. 8593In particular, the unwind information is used to determine which 8594function called the function that threw the exception, and which 8595function called that one, and so forth. This information is also used 8596to restore the values of callee-saved registers in the function catching 8597the exception. 8598 8599 If you are writing functions in assembly code, and those functions 8600call other functions that throw exceptions, you must use assembly pseudo 8601ops to ensure that appropriate exception unwind information is 8602generated. Otherwise, if one of the functions called by your assembly 8603code throws an exception, the run-time library will be unable to unwind 8604the stack through your assembly code and your program will not behave 8605correctly. 8606 8607 To illustrate the use of these pseudo ops, we will examine the code 8608that G++ generates for the following C++ input: 8609 8610void callee (int *); 8611 8612int 8613caller () 8614{ 8615 int i; 8616 callee (&i); 8617 return i; 8618} 8619 8620 This example does not show how to throw or catch an exception from 8621assembly code. That is a much more complex operation and should always 8622be done in a high-level language, such as C++, that directly supports 8623exceptions. 8624 8625 The code generated by one particular version of G++ when compiling 8626the example above is: 8627 8628_Z6callerv: 8629 .fnstart 8630.LFB2: 8631 @ Function supports interworking. 8632 @ args = 0, pretend = 0, frame = 8 8633 @ frame_needed = 1, uses_anonymous_args = 0 8634 stmfd sp!, {fp, lr} 8635 .save {fp, lr} 8636.LCFI0: 8637 .setfp fp, sp, #4 8638 add fp, sp, #4 8639.LCFI1: 8640 .pad #8 8641 sub sp, sp, #8 8642.LCFI2: 8643 sub r3, fp, #8 8644 mov r0, r3 8645 bl _Z6calleePi 8646 ldr r3, [fp, #-8] 8647 mov r0, r3 8648 sub sp, fp, #4 8649 ldmfd sp!, {fp, lr} 8650 bx lr 8651.LFE2: 8652 .fnend 8653 8654 Of course, the sequence of instructions varies based on the options 8655you pass to GCC and on the version of GCC in use. The exact 8656instructions are not important since we are focusing on the pseudo ops 8657that are used to generate unwind information. 8658 8659 An important assumption made by the unwinder is that the stack frame 8660does not change during the body of the function. In particular, since 8661we assume that the assembly code does not itself throw an exception, the 8662only point where an exception can be thrown is from a call, such as the 8663'bl' instruction above. At each call site, the same saved registers 8664(including 'lr', which indicates the return address) must be located in 8665the same locations relative to the frame pointer. 8666 8667 The '.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op 8668appears immediately before the first instruction of the function while 8669the '.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears 8670immediately after the last instruction of the function. These pseudo 8671ops specify the range of the function. 8672 8673 Only the order of the other pseudos ops (e.g., '.setfp' or '.pad') 8674matters; their exact locations are irrelevant. In the example above, 8675the compiler emits the pseudo ops with particular instructions. That 8676makes it easier to understand the code, but it is not required for 8677correctness. It would work just as well to emit all of the pseudo ops 8678other than '.fnend' in the same order, but immediately after '.fnstart'. 8679 8680 The '.save' (*note .save pseudo op: arm_save.) pseudo op indicates 8681registers that have been saved to the stack so that they can be restored 8682before the function returns. The argument to the '.save' pseudo op is a 8683list of registers to save. If a register is "callee-saved" (as 8684specified by the ABI) and is modified by the function you are writing, 8685then your code must save the value before it is modified and restore the 8686original value before the function returns. If an exception is thrown, 8687the run-time library restores the values of these registers from their 8688locations on the stack before returning control to the exception 8689handler. (Of course, if an exception is not thrown, the function that 8690contains the '.save' pseudo op restores these registers in the function 8691epilogue, as is done with the 'ldmfd' instruction above.) 8692 8693 You do not have to save callee-saved registers at the very beginning 8694of the function and you do not need to use the '.save' pseudo op 8695immediately following the point at which the registers are saved. 8696However, if you modify a callee-saved register, you must save it on the 8697stack before modifying it and before calling any functions which might 8698throw an exception. And, you must use the '.save' pseudo op to indicate 8699that you have done so. 8700 8701 The '.pad' (*note .pad: arm_pad.) pseudo op indicates a modification 8702of the stack pointer that does not save any registers. The argument is 8703the number of bytes (in decimal) that are subtracted from the stack 8704pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 8705the stack pointer increases the size of the stack.) 8706 8707 The '.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op indicates 8708the register that contains the frame pointer. The first argument is the 8709register that is set, which is typically 'fp'. The second argument 8710indicates the register from which the frame pointer takes its value. 8711The third argument, if present, is the value (in decimal) added to the 8712register specified by the second argument to compute the value of the 8713frame pointer. You should not modify the frame pointer in the body of 8714the function. 8715 8716 If you do not use a frame pointer, then you should not use the 8717'.setfp' pseudo op. If you do not use a frame pointer, then you should 8718avoid modifying the stack pointer outside of the function prologue. 8719Otherwise, the run-time library will be unable to find saved registers 8720when it is unwinding the stack. 8721 8722 The pseudo ops described above are sufficient for writing assembly 8723code that calls functions which may throw exceptions. If you need to 8724know more about the object-file format used to represent unwind 8725information, you may consult the 'Exception Handling ABI for the ARM 8726Architecture' available from <http://infocenter.arm.com>. 8727 8728 8729File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 8730 87319.5 AVR Dependent Features 8732========================== 8733 8734* Menu: 8735 8736* AVR Options:: Options 8737* AVR Syntax:: Syntax 8738* AVR Opcodes:: Opcodes 8739* AVR Pseudo Instructions:: Pseudo Instructions 8740 8741 8742File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 8743 87449.5.1 Options 8745------------- 8746 8747'-mmcu=MCU' 8748 Specify ATMEL AVR instruction set or MCU type. 8749 8750 Instruction set avr1 is for the minimal AVR core, not supported by 8751 the C compiler, only for assembler programs (MCU types: at90s1200, 8752 attiny11, attiny12, attiny15, attiny28). 8753 8754 Instruction set avr2 (default) is for the classic AVR core with up 8755 to 8K program memory space (MCU types: at90s2313, at90s2323, 8756 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 8757 at90s4434, at90s8515, at90c8534, at90s8535). 8758 8759 Instruction set avr25 is for the classic AVR core with up to 8K 8760 program memory space plus the MOVW instruction (MCU types: 8761 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 8762 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 8763 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 8764 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 8765 attiny828, at86rf401, ata6289, ata5272). 8766 8767 Instruction set avr3 is for the classic AVR core with up to 128K 8768 program memory space (MCU types: at43usb355, at76c711). 8769 8770 Instruction set avr31 is for the classic AVR core with exactly 128K 8771 program memory space (MCU types: atmega103, at43usb320). 8772 8773 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 8774 JMP instructions (MCU types: attiny167, attiny1634, at90usb82, 8775 at90usb162, atmega8u2, atmega16u2, atmega32u2, ata5505). 8776 8777 Instruction set avr4 is for the enhanced AVR core with up to 8K 8778 program memory space (MCU types: atmega48, atmega48a, atmega48pa, 8779 atmega48p, atmega8, atmega8a, atmega88, atmega88a, atmega88p, 8780 atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, 8781 at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6285, ata6286). 8782 8783 Instruction set avr5 is for the enhanced AVR core with up to 128K 8784 program memory space (MCU types: at90pwm161, atmega16, atmega16a, 8785 atmega161, atmega162, atmega163, atmega164a, atmega164p, 8786 atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, 8787 atmega168, atmega168a, atmega168p, atmega168pa, atmega169, 8788 atmega169a, atmega169p, atmega169pa, atmega32, atmega323, 8789 atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, 8790 atmega32, atmega32a, atmega323, atmega324a, atmega324p, 8791 atmega324pa, atmega325, atmega325a, atmega325p, atmega325p, 8792 atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, 8793 atmega328, atmega328p, atmega329, atmega329a, atmega329p, 8794 atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406, 8795 atmega64, atmega64a, atmega64rfr2, atmega644rfr2, atmega640, 8796 atmega644, atmega644a, atmega644p, atmega644pa, atmega645, 8797 atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, 8798 atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, 8799 atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, 8800 atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, 8801 at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, 8802 atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, 8803 atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, 8804 at90scr100, ata5790, ata5795). 8805 8806 Instruction set avr51 is for the enhanced AVR core with exactly 8807 128K program memory space (MCU types: atmega128, atmega128a, 8808 atmega1280, atmega1281, atmega1284, atmega1284p, atmega128rfa1, 8809 atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 8810 at90usb1287, m3000). 8811 8812 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 8813 (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). 8814 8815 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 8816 program memory space and less than 64K data space (MCU types: 8817 atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, 8818 atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5, 8819 atxmega8e5, atxmega32e5, atxmega32x1). 8820 8821 Instruction set avrxmega3 is for the XMEGA AVR core with up to 64K 8822 of combined program memory and RAM, and with program memory visible 8823 in the RAM address space (MCU types: attiny212, attiny214, 8824 attiny412, attiny414, attiny416, attiny417, attiny814, attiny816, 8825 attiny817, attiny1614, attiny1616, attiny1617, attiny3214, 8826 attiny3216, attiny3217). 8827 8828 Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 8829 program memory space and less than 64K data space (MCU types: 8830 atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, 8831 atxmega64c3, atxmega64d3, atxmega64d4). 8832 8833 Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 8834 program memory space and greater than 64K data space (MCU types: 8835 atxmega64a1, atxmega64a1u). 8836 8837 Instruction set avrxmega6 is for the XMEGA AVR core with larger 8838 than 64K program memory space and less than 64K data space (MCU 8839 types: atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, 8840 atxmega128d4, atxmega192a3, atxmega192a3u, atxmega128b1, 8841 atxmega128b3, atxmega192c3, atxmega192d3, atxmega256a3, 8842 atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, 8843 atxmega256d3, atxmega384c3, atxmega256d3). 8844 8845 Instruction set avrxmega7 is for the XMEGA AVR core with larger 8846 than 64K program memory space and greater than 64K data space (MCU 8847 types: atxmega128a1, atxmega128a1u, atxmega128a4u). 8848 8849 Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 8850 microcontrollers. 8851 8852'-mall-opcodes' 8853 Accept all AVR opcodes, even if not supported by '-mmcu'. 8854 8855'-mno-skip-bug' 8856 This option disable warnings for skipping two-word instructions. 8857 8858'-mno-wrap' 8859 This option reject 'rjmp/rcall' instructions with 8K wrap-around. 8860 8861'-mrmw' 8862 Accept Read-Modify-Write ('XCH,LAC,LAS,LAT') instructions. 8863 8864'-mlink-relax' 8865 Enable support for link-time relaxation. This is now on by default 8866 and this flag no longer has any effect. 8867 8868'-mno-link-relax' 8869 Disable support for link-time relaxation. The assembler will 8870 resolve relocations when it can, and may be able to better compress 8871 some debug information. 8872 8873'-mgcc-isr' 8874 Enable the '__gcc_isr' pseudo instruction. 8875 8876 8877File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 8878 88799.5.2 Syntax 8880------------ 8881 8882* Menu: 8883 8884* AVR-Chars:: Special Characters 8885* AVR-Regs:: Register Names 8886* AVR-Modifiers:: Relocatable Expression Modifiers 8887 8888 8889File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 8890 88919.5.2.1 Special Characters 8892.......................... 8893 8894The presence of a ';' anywhere on a line indicates the start of a 8895comment that extends to the end of that line. 8896 8897 If a '#' appears as the first character of a line, the whole line is 8898treated as a comment, but in this case the line can also be a logical 8899line number directive (*note Comments::) or a preprocessor control 8900command (*note Preprocessing::). 8901 8902 The '$' character can be used instead of a newline to separate 8903statements. 8904 8905 8906File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 8907 89089.5.2.2 Register Names 8909...................... 8910 8911The AVR has 32 x 8-bit general purpose working registers 'r0', 'r1', ... 8912'r31'. Six of the 32 registers can be used as three 16-bit indirect 8913address register pointers for Data Space addressing. One of the these 8914address pointers can also be used as an address pointer for look up 8915tables in Flash program memory. These added function registers are the 891616-bit 'X', 'Y' and 'Z' - registers. 8917 8918 X = r26:r27 8919 Y = r28:r29 8920 Z = r30:r31 8921 8922 8923File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 8924 89259.5.2.3 Relocatable Expression Modifiers 8926........................................ 8927 8928The assembler supports several modifiers when using relocatable 8929addresses in AVR instruction operands. The general syntax is the 8930following: 8931 8932 modifier(relocatable-expression) 8933 8934'lo8' 8935 8936 This modifier allows you to use bits 0 through 7 of an address 8937 expression as 8 bit relocatable expression. 8938 8939'hi8' 8940 8941 This modifier allows you to use bits 7 through 15 of an address 8942 expression as 8 bit relocatable expression. This is useful with, 8943 for example, the AVR 'ldi' instruction and 'lo8' modifier. 8944 8945 For example 8946 8947 ldi r26, lo8(sym+10) 8948 ldi r27, hi8(sym+10) 8949 8950'hh8' 8951 8952 This modifier allows you to use bits 16 through 23 of an address 8953 expression as 8 bit relocatable expression. Also, can be useful 8954 for loading 32 bit constants. 8955 8956'hlo8' 8957 8958 Synonym of 'hh8'. 8959 8960'hhi8' 8961 8962 This modifier allows you to use bits 24 through 31 of an expression 8963 as 8 bit expression. This is useful with, for example, the AVR 8964 'ldi' instruction and 'lo8', 'hi8', 'hlo8', 'hhi8', modifier. 8965 8966 For example 8967 8968 ldi r26, lo8(285774925) 8969 ldi r27, hi8(285774925) 8970 ldi r28, hlo8(285774925) 8971 ldi r29, hhi8(285774925) 8972 ; r29,r28,r27,r26 = 285774925 8973 8974'pm_lo8' 8975 8976 This modifier allows you to use bits 0 through 7 of an address 8977 expression as 8 bit relocatable expression. This modifier useful 8978 for addressing data or code from Flash/Program memory. The using 8979 of 'pm_lo8' similar to 'lo8'. 8980 8981'pm_hi8' 8982 8983 This modifier allows you to use bits 8 through 15 of an address 8984 expression as 8 bit relocatable expression. This modifier useful 8985 for addressing data or code from Flash/Program memory. 8986 8987'pm_hh8' 8988 8989 This modifier allows you to use bits 15 through 23 of an address 8990 expression as 8 bit relocatable expression. This modifier useful 8991 for addressing data or code from Flash/Program memory. 8992 8993 8994File: as.info, Node: AVR Opcodes, Next: AVR Pseudo Instructions, Prev: AVR Syntax, Up: AVR-Dependent 8995 89969.5.3 Opcodes 8997------------- 8998 8999For detailed information on the AVR machine instruction set, see 9000<www.atmel.com/products/AVR>. 9001 9002 'as' implements all the standard AVR opcodes. The following table 9003summarizes the AVR opcodes, and their arguments. 9004 9005 Legend: 9006 r any register 9007 d 'ldi' register (r16-r31) 9008 v 'movw' even register (r0, r2, ..., r28, r30) 9009 a 'fmul' register (r16-r23) 9010 w 'adiw' register (r24,r26,r28,r30) 9011 e pointer registers (X,Y,Z) 9012 b base pointer register and displacement ([YZ]+disp) 9013 z Z pointer register (for [e]lpm Rd,Z[+]) 9014 M immediate value from 0 to 255 9015 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 9016 s immediate value from 0 to 7 9017 P Port address value from 0 to 63. (in, out) 9018 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 9019 K immediate value from 0 to 63 (used in 'adiw', 'sbiw') 9020 i immediate value 9021 l signed pc relative offset from -64 to 63 9022 L signed pc relative offset from -2048 to 2047 9023 h absolute code address (call, jmp) 9024 S immediate value from 0 to 7 (S = s << 4) 9025 ? use this opcode entry if no parameters, else use next opcode entry 9026 9027 1001010010001000 clc 9028 1001010011011000 clh 9029 1001010011111000 cli 9030 1001010010101000 cln 9031 1001010011001000 cls 9032 1001010011101000 clt 9033 1001010010111000 clv 9034 1001010010011000 clz 9035 1001010000001000 sec 9036 1001010001011000 seh 9037 1001010001111000 sei 9038 1001010000101000 sen 9039 1001010001001000 ses 9040 1001010001101000 set 9041 1001010000111000 sev 9042 1001010000011000 sez 9043 100101001SSS1000 bclr S 9044 100101000SSS1000 bset S 9045 1001010100001001 icall 9046 1001010000001001 ijmp 9047 1001010111001000 lpm ? 9048 1001000ddddd010+ lpm r,z 9049 1001010111011000 elpm ? 9050 1001000ddddd011+ elpm r,z 9051 0000000000000000 nop 9052 1001010100001000 ret 9053 1001010100011000 reti 9054 1001010110001000 sleep 9055 1001010110011000 break 9056 1001010110101000 wdr 9057 1001010111101000 spm 9058 000111rdddddrrrr adc r,r 9059 000011rdddddrrrr add r,r 9060 001000rdddddrrrr and r,r 9061 000101rdddddrrrr cp r,r 9062 000001rdddddrrrr cpc r,r 9063 000100rdddddrrrr cpse r,r 9064 001001rdddddrrrr eor r,r 9065 001011rdddddrrrr mov r,r 9066 100111rdddddrrrr mul r,r 9067 001010rdddddrrrr or r,r 9068 000010rdddddrrrr sbc r,r 9069 000110rdddddrrrr sub r,r 9070 001001rdddddrrrr clr r 9071 000011rdddddrrrr lsl r 9072 000111rdddddrrrr rol r 9073 001000rdddddrrrr tst r 9074 0111KKKKddddKKKK andi d,M 9075 0111KKKKddddKKKK cbr d,n 9076 1110KKKKddddKKKK ldi d,M 9077 11101111dddd1111 ser d 9078 0110KKKKddddKKKK ori d,M 9079 0110KKKKddddKKKK sbr d,M 9080 0011KKKKddddKKKK cpi d,M 9081 0100KKKKddddKKKK sbci d,M 9082 0101KKKKddddKKKK subi d,M 9083 1111110rrrrr0sss sbrc r,s 9084 1111111rrrrr0sss sbrs r,s 9085 1111100ddddd0sss bld r,s 9086 1111101ddddd0sss bst r,s 9087 10110PPdddddPPPP in r,P 9088 10111PPrrrrrPPPP out P,r 9089 10010110KKddKKKK adiw w,K 9090 10010111KKddKKKK sbiw w,K 9091 10011000pppppsss cbi p,s 9092 10011010pppppsss sbi p,s 9093 10011001pppppsss sbic p,s 9094 10011011pppppsss sbis p,s 9095 111101lllllll000 brcc l 9096 111100lllllll000 brcs l 9097 111100lllllll001 breq l 9098 111101lllllll100 brge l 9099 111101lllllll101 brhc l 9100 111100lllllll101 brhs l 9101 111101lllllll111 brid l 9102 111100lllllll111 brie l 9103 111100lllllll000 brlo l 9104 111100lllllll100 brlt l 9105 111100lllllll010 brmi l 9106 111101lllllll001 brne l 9107 111101lllllll010 brpl l 9108 111101lllllll000 brsh l 9109 111101lllllll110 brtc l 9110 111100lllllll110 brts l 9111 111101lllllll011 brvc l 9112 111100lllllll011 brvs l 9113 111101lllllllsss brbc s,l 9114 111100lllllllsss brbs s,l 9115 1101LLLLLLLLLLLL rcall L 9116 1100LLLLLLLLLLLL rjmp L 9117 1001010hhhhh111h call h 9118 1001010hhhhh110h jmp h 9119 1001010rrrrr0101 asr r 9120 1001010rrrrr0000 com r 9121 1001010rrrrr1010 dec r 9122 1001010rrrrr0011 inc r 9123 1001010rrrrr0110 lsr r 9124 1001010rrrrr0001 neg r 9125 1001000rrrrr1111 pop r 9126 1001001rrrrr1111 push r 9127 1001010rrrrr0111 ror r 9128 1001010rrrrr0010 swap r 9129 00000001ddddrrrr movw v,v 9130 00000010ddddrrrr muls d,d 9131 000000110ddd0rrr mulsu a,a 9132 000000110ddd1rrr fmul a,a 9133 000000111ddd0rrr fmuls a,a 9134 000000111ddd1rrr fmulsu a,a 9135 1001001ddddd0000 sts i,r 9136 1001000ddddd0000 lds r,i 9137 10o0oo0dddddbooo ldd r,b 9138 100!000dddddee-+ ld r,e 9139 10o0oo1rrrrrbooo std b,r 9140 100!001rrrrree-+ st e,r 9141 1001010100011001 eicall 9142 1001010000011001 eijmp 9143 9144 9145File: as.info, Node: AVR Pseudo Instructions, Prev: AVR Opcodes, Up: AVR-Dependent 9146 91479.5.4 Pseudo Instructions 9148------------------------- 9149 9150The only available pseudo-instruction '__gcc_isr' can be activated by 9151option '-mgcc-isr'. 9152 9153'__gcc_isr 1' 9154 Emit code chunk to be used in avr-gcc ISR prologue. It will expand 9155 to at most six 1-word instructions, all optional: push of 9156 'tmp_reg', push of 'SREG', push and clear of 'zero_reg', push of 9157 REG. 9158 9159'__gcc_isr 2' 9160 Emit code chunk to be used in an avr-gcc ISR epilogue. It will 9161 expand to at most five 1-word instructions, all optional: pop of 9162 REG, pop of 'zero_reg', pop of 'SREG', pop of 'tmp_reg'. 9163 9164'__gcc_isr 0, REG' 9165 Finish avr-gcc ISR function. Scan code since the last prologue for 9166 usage of: 'SREG', 'tmp_reg', 'zero_reg'. Prologue chunk and 9167 epilogue chunks will be replaced by appropriate code to save / 9168 restore 'SREG', 'tmp_reg', 'zero_reg' and REG. 9169 9170 Example input: 9171 9172 __vector1: 9173 __gcc_isr 1 9174 lds r24, var 9175 inc r24 9176 sts var, r24 9177 __gcc_isr 2 9178 reti 9179 __gcc_isr 0, r24 9180 9181 Example output: 9182 9183 00000000 <__vector1>: 9184 0: 8f 93 push r24 9185 2: 8f b7 in r24, 0x3f 9186 4: 8f 93 push r24 9187 6: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <var> 9188 a: 83 95 inc r24 9189 c: 80 93 60 00 sts 0x0060, r24 ; 0x800060 <var> 9190 10: 8f 91 pop r24 9191 12: 8f bf out 0x3f, r24 9192 14: 8f 91 pop r24 9193 16: 18 95 reti 9194 9195 9196File: as.info, Node: Blackfin-Dependent, Next: BPF-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 9197 91989.6 Blackfin Dependent Features 9199=============================== 9200 9201* Menu: 9202 9203* Blackfin Options:: Blackfin Options 9204* Blackfin Syntax:: Blackfin Syntax 9205* Blackfin Directives:: Blackfin Directives 9206 9207 9208File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 9209 92109.6.1 Options 9211------------- 9212 9213'-mcpu=PROCESSOR[-SIREVISION]' 9214 This option specifies the target processor. The optional 9215 SIREVISION is not used in assembler. It's here such that GCC can 9216 easily pass down its '-mcpu=' option. The assembler will issue an 9217 error message if an attempt is made to assemble an instruction 9218 which will not execute on the target processor. The following 9219 processor names are recognized: 'bf504', 'bf506', 'bf512', 'bf514', 9220 'bf516', 'bf518', 'bf522', 'bf523', 'bf524', 'bf525', 'bf526', 9221 'bf527', 'bf531', 'bf532', 'bf533', 'bf534', 'bf535' (not 9222 implemented yet), 'bf536', 'bf537', 'bf538', 'bf539', 'bf542', 9223 'bf542m', 'bf544', 'bf544m', 'bf547', 'bf547m', 'bf548', 'bf548m', 9224 'bf549', 'bf549m', 'bf561', and 'bf592'. 9225 9226'-mfdpic' 9227 Assemble for the FDPIC ABI. 9228 9229'-mno-fdpic' 9230'-mnopic' 9231 Disable -mfdpic. 9232 9233 9234File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 9235 92369.6.2 Syntax 9237------------ 9238 9239'Special Characters' 9240 Assembler input is free format and may appear anywhere on the line. 9241 One instruction may extend across multiple lines or more than one 9242 instruction may appear on the same line. White space (space, tab, 9243 comments or newline) may appear anywhere between tokens. A token 9244 must not have embedded spaces. Tokens include numbers, register 9245 names, keywords, user identifiers, and also some multicharacter 9246 special symbols like "+=", "/*" or "||". 9247 9248 Comments are introduced by the '#' character and extend to the end 9249 of the current line. If the '#' appears as the first character of 9250 a line, the whole line is treated as a comment, but in this case 9251 the line can also be a logical line number directive (*note 9252 Comments::) or a preprocessor control command (*note 9253 Preprocessing::). 9254 9255'Instruction Delimiting' 9256 A semicolon must terminate every instruction. Sometimes a complete 9257 instruction will consist of more than one operation. There are two 9258 cases where this occurs. The first is when two general operations 9259 are combined. Normally a comma separates the different parts, as 9260 in 9261 9262 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 9263 9264 The second case occurs when a general instruction is combined with 9265 one or two memory references for joint issue. The latter portions 9266 are set off by a "||" token. 9267 9268 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 9269 9270 Multiple instructions can occur on the same line. Each must be 9271 terminated by a semicolon character. 9272 9273'Register Names' 9274 9275 The assembler treats register names and instruction keywords in a 9276 case insensitive manner. User identifiers are case sensitive. 9277 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 9278 assembler. 9279 9280 Register names are reserved and may not be used as program 9281 identifiers. 9282 9283 Some operations (such as "Move Register") require a register pair. 9284 Register pairs are always data registers and are denoted using a 9285 colon, eg., R3:2. The larger number must be written firsts. Note 9286 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 9287 R3:2, and R1:0. 9288 9289 Some instructions (such as -SP (Push Multiple)) require a group of 9290 adjacent registers. Adjacent registers are denoted in the syntax 9291 by the range enclosed in parentheses and separated by a colon, eg., 9292 (R7:3). Again, the larger number appears first. 9293 9294 Portions of a particular register may be individually specified. 9295 This is written with a dot (".") following the register name and 9296 then a letter denoting the desired portion. For 32-bit registers, 9297 ".H" denotes the most significant ("High") portion. ".L" denotes 9298 the least-significant portion. The subdivisions of the 40-bit 9299 registers are described later. 9300 9301'Accumulators' 9302 The set of 40-bit registers A1 and A0 that normally contain data 9303 that is being manipulated. Each accumulator can be accessed in 9304 four ways. 9305 9306 'one 40-bit register' 9307 The register will be referred to as A1 or A0. 9308 'one 32-bit register' 9309 The registers are designated as A1.W or A0.W. 9310 'two 16-bit registers' 9311 The registers are designated as A1.H, A1.L, A0.H or A0.L. 9312 'one 8-bit register' 9313 The registers are designated as A1.X or A0.X for the bits that 9314 extend beyond bit 31. 9315 9316'Data Registers' 9317 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 9318 that normally contain data for manipulation. These are abbreviated 9319 as D-register or Dreg. Data registers can be accessed as 32-bit 9320 registers or as two independent 16-bit registers. The least 9321 significant 16 bits of each register is called the "low" half and 9322 is designated with ".L" following the register name. The most 9323 significant 16 bits are called the "high" half and is designated 9324 with ".H" following the name. 9325 9326 R7.L, r2.h, r4.L, R0.H 9327 9328'Pointer Registers' 9329 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 9330 that normally contain byte addresses of data structures. These are 9331 abbreviated as P-register or Preg. 9332 9333 p2, p5, fp, sp 9334 9335'Stack Pointer SP' 9336 The stack pointer contains the 32-bit address of the last occupied 9337 byte location in the stack. The stack grows by decrementing the 9338 stack pointer. 9339 9340'Frame Pointer FP' 9341 The frame pointer contains the 32-bit address of the previous frame 9342 pointer in the stack. It is located at the top of a frame. 9343 9344'Loop Top' 9345 LT0 and LT1. These registers contain the 32-bit address of the top 9346 of a zero overhead loop. 9347 9348'Loop Count' 9349 LC0 and LC1. These registers contain the 32-bit counter of the 9350 zero overhead loop executions. 9351 9352'Loop Bottom' 9353 LB0 and LB1. These registers contain the 32-bit address of the 9354 bottom of a zero overhead loop. 9355 9356'Index Registers' 9357 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 9358 byte addresses of data structures. Abbreviated I-register or Ireg. 9359 9360'Modify Registers' 9361 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 9362 offset values that are added and subtracted to one of the index 9363 registers. Abbreviated as Mreg. 9364 9365'Length Registers' 9366 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 9367 the length in bytes of the circular buffer. Abbreviated as Lreg. 9368 Clear the Lreg to disable circular addressing for the corresponding 9369 Ireg. 9370 9371'Base Registers' 9372 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 9373 the base address in bytes of the circular buffer. Abbreviated as 9374 Breg. 9375 9376'Floating Point' 9377 The Blackfin family has no hardware floating point but the .float 9378 directive generates ieee floating point numbers for use with 9379 software floating point libraries. 9380 9381'Blackfin Opcodes' 9382 For detailed information on the Blackfin machine instruction set, 9383 see the Blackfin Processor Instruction Set Reference. 9384 9385 9386File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 9387 93889.6.3 Directives 9389---------------- 9390 9391The following directives are provided for compatibility with the VDSP 9392assembler. 9393 9394'.byte2' 9395 Initializes a two byte data object. 9396 9397 This maps to the '.short' directive. 9398'.byte4' 9399 Initializes a four byte data object. 9400 9401 This maps to the '.int' directive. 9402'.db' 9403 Initializes a single byte data object. 9404 9405 This directive is a synonym for '.byte'. 9406'.dw' 9407 Initializes a two byte data object. 9408 9409 This directive is a synonym for '.byte2'. 9410'.dd' 9411 Initializes a four byte data object. 9412 9413 This directive is a synonym for '.byte4'. 9414'.var' 9415 Define and initialize a 32 bit data object. 9416 9417 9418File: as.info, Node: BPF-Dependent, Next: CR16-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 9419 94209.7 BPF Dependent Features 9421========================== 9422 9423* Menu: 9424 9425* BPF Options:: Options 9426* BPF Syntax:: Syntax 9427* BPF Directives:: Machine Directives 9428* BPF Opcodes:: Opcodes 9429 9430 9431File: as.info, Node: BPF Options, Next: BPF Syntax, Up: BPF-Dependent 9432 94339.7.1 Options 9434------------- 9435 9436'-EB' 9437 This option specifies that the assembler should emit big-endian 9438 eBPF. 9439 9440'-EL' 9441 This option specifies that the assembler should emit little-endian 9442 eBPF. 9443 9444 Note that if no endianness option is specified in the command line, 9445the host endianness is used. 9446 9447 9448File: as.info, Node: BPF Syntax, Next: BPF Directives, Prev: BPF Options, Up: BPF-Dependent 9449 94509.7.2 Syntax 9451------------ 9452 9453* Menu: 9454 9455* BPF-Chars:: Special Characters 9456* BPF-Regs:: Register Names 9457* BPF-Pseudo-Maps:: Pseudo map fds 9458 9459 9460File: as.info, Node: BPF-Chars, Next: BPF-Regs, Up: BPF Syntax 9461 94629.7.2.1 Special Characters 9463.......................... 9464 9465The presence of a ';' on a line indicates the start of a comment that 9466extends to the end of the current line. If a '#' appears as the first 9467character of a line, the whole line is treated as a comment. 9468 9469 Statements and assembly directives are separated by newlines. 9470 9471 9472File: as.info, Node: BPF-Regs, Next: BPF-Pseudo-Maps, Prev: BPF-Chars, Up: BPF Syntax 9473 94749.7.2.2 Register Names 9475...................... 9476 9477The eBPF processor provides ten general-purpose 64-bit registers, which 9478are read-write, and a read-only frame pointer register: 9479 9480'%r0 .. %r9' 9481 General-purpose registers. 9482'%r10' 9483 Frame pointer register. 9484 9485 Some registers have additional names, to reflect their role in the 9486eBPF ABI: 9487 9488'%a' 9489 This is '%r0'. 9490'%ctx' 9491 This is '%r6'. 9492'%fp' 9493 This is '%r10'. 9494 9495 9496File: as.info, Node: BPF-Pseudo-Maps, Prev: BPF-Regs, Up: BPF Syntax 9497 94989.7.2.3 Pseudo Maps 9499................... 9500 9501The 'LDDW' instruction can take a literal pseudo map file descriptor as 9502its second argument. This uses the syntax '%map_fd(N)' where 'N' is a 9503signed number. 9504 9505 For example, to load the address of the pseudo map with file 9506descriptor '2' in register 'r1' we would do: 9507 9508 lddw %r1, %map_fd(2) 9509 9510 9511File: as.info, Node: BPF Directives, Next: BPF Opcodes, Prev: BPF Syntax, Up: BPF-Dependent 9512 95139.7.3 Machine Directives 9514------------------------ 9515 9516The BPF version of 'as' supports the following additional machine 9517directives: 9518 9519'.word' 9520 The '.half' directive produces a 16 bit value. 9521 9522'.word' 9523 The '.word' directive produces a 32 bit value. 9524 9525'.dword' 9526 The '.dword' directive produces a 64 bit value. 9527 9528 9529File: as.info, Node: BPF Opcodes, Prev: BPF Directives, Up: BPF-Dependent 9530 95319.7.4 Opcodes 9532------------- 9533 9534In the instruction descriptions below the following field descriptors 9535are used: 9536 9537'%d' 9538 Destination general-purpose register whose role is to be 9539 destination of an operation. 9540'%s' 9541 Source general-purpose register whose role is to be the source of 9542 an operation. 9543'disp16' 9544 16-bit signed PC-relative offset, measured in number of 64-bit 9545 words, minus one. 9546'disp32' 9547 32-bit signed PC-relative offset, measured in number of 64-bit 9548 words, minus one. 9549'offset16' 9550 Signed 16-bit immediate. 9551'imm32' 9552 Signed 32-bit immediate. 9553'imm64' 9554 Signed 64-bit immediate. 9555 95569.7.4.1 Arithmetic instructions 9557............................... 9558 9559The destination register in these instructions act like an accumulator. 9560 9561'add %d, (%s|imm32)' 9562 64-bit arithmetic addition. 9563'sub %d, (%s|imm32)' 9564 64-bit arithmetic subtraction. 9565'mul %d, (%s|imm32)' 9566 64-bit arithmetic multiplication. 9567'div %d, (%s|imm32)' 9568 64-bit arithmetic integer division. 9569'mod %d, (%s|imm32)' 9570 64-bit integer remainder. 9571'and %d, (%s|imm32)' 9572 64-bit bit-wise "and" operation. 9573'or %d, (%s|imm32)' 9574 64-bit bit-wise "or" operation. 9575'xor %d, (%s|imm32)' 9576 64-bit bit-wise exclusive-or operation. 9577'lsh %d, (%s|imm32)' 9578 64-bit left shift, by '%s' or 'imm32' bits. 9579'rsh %d, (%s|imm32)' 9580 64-bit right logical shift, by '%s' or 'imm32' bits. 9581'arsh %d, (%s|imm32)' 9582 64-bit right arithmetic shift, by '%s' or 'imm32' bits. 9583'neg %d' 9584 64-bit arithmetic negation. 9585'mov %d, (%s|imm32)' 9586 Move the 64-bit value of '%s' in '%d', or load 'imm32' in '%d'. 9587 95889.7.4.2 32-bit arithmetic instructions 9589...................................... 9590 9591The destination register in these instructions act as an accumulator. 9592 9593'add32 %d, (%s|imm32)' 9594 32-bit arithmetic addition. 9595'sub32 %d, (%s|imm32)' 9596 32-bit arithmetic subtraction. 9597'mul32 %d, (%s|imm32)' 9598 32-bit arithmetic multiplication. 9599'div32 %d, (%s|imm32)' 9600 32-bit arithmetic integer division. 9601'mod32 %d, (%s|imm32)' 9602 32-bit integer remainder. 9603'and32 %d, (%s|imm32)' 9604 32-bit bit-wise "and" operation. 9605'or32 %d, (%s|imm32)' 9606 32-bit bit-wise "or" operation. 9607'xor32 %d, (%s|imm32)' 9608 32-bit bit-wise exclusive-or operation. 9609'lsh32 %d, (%s|imm32)' 9610 32-bit left shift, by '%s' or 'imm32' bits. 9611'rsh32 %d, (%s|imm32)' 9612 32-bit right logical shift, by '%s' or 'imm32' bits. 9613'arsh32 %d, (%s|imm32)' 9614 32-bit right arithmetic shift, by '%s' or 'imm32' bits. 9615'neg32 %d' 9616 32-bit arithmetic negation. 9617'mov32 %d, (%s|imm32)' 9618 Move the 32-bit value of '%s' in '%d', or load 'imm32' in '%d'. 9619 96209.7.4.3 Endianness conversion instructions 9621.......................................... 9622 9623'endle %d, (8|16|32)' 9624 Convert the 8-bit, 16-bit or 32-bit value in '%d' to little-endian. 9625'endbe %d, (8|16|32)' 9626 Convert the 8-bit, 16-bit or 32-bit value in '%d' to big-endian. 9627 96289.7.4.4 64-bit load and pseudo maps 9629................................... 9630 9631'lddw %d, imm64' 9632 Load the given signed 64-bit immediate, or pseudo map descriptor, 9633 to the destination register '%d'. 9634'lddw %d, %map_fd(N)' 9635 Load the address of the given pseudo map fd _N_ to the destination 9636 register '%d'. 9637 96389.7.4.5 Load instructions for socket filters 9639............................................ 9640 9641The following instructions are intended to be used in socket filters, 9642and are therefore not general-purpose: they make assumptions on the 9643contents of several registers. See the file 9644'Documentation/networking/filter.txt' in the Linux kernel source tree 9645for more information. 9646 9647 Absolute loads: 9648 9649'ldabsdw imm32' 9650 Absolute 64-bit load. 9651'ldabsw imm32' 9652 Absolute 32-bit load. 9653'ldabsh imm32' 9654 Absolute 16-bit load. 9655'ldabsb imm32' 9656 Absolute 8-bit load. 9657 9658 Indirect loads: 9659 9660'ldinddw %s, imm32' 9661 Indirect 64-bit load. 9662'ldindw %s, imm32' 9663 Indirect 32-bit load. 9664'ldindh %s, imm32' 9665 Indirect 16-bit load. 9666'ldindb %s, imm32' 9667 Indirect 8-bit load. 9668 96699.7.4.6 Generic load/store instructions 9670....................................... 9671 9672General-purpose load and store instructions are provided for several 9673word sizes. 9674 9675 Load to register instructions: 9676 9677'ldxdw %d, [%s+offset16]' 9678 Generic 64-bit load. 9679'ldxw %d, [%s+offset16]' 9680 Generic 32-bit load. 9681'ldxh %d, [%s+offset16]' 9682 Generic 16-bit load. 9683'ldxb %d, [%s+offset16]' 9684 Generic 8-bit load. 9685 9686 Store from register instructions: 9687 9688'stxdw [%d+offset16], %s' 9689 Generic 64-bit store. 9690'stxw [%d+offset16], %s' 9691 Generic 32-bit store. 9692'stxh [%d+offset16], %s' 9693 Generic 16-bit store. 9694'stxb [%d+offset16], %s' 9695 Generic 8-bit store. 9696 9697 Store from immediates instructions: 9698 9699'stddw [%d+offset16], imm32' 9700 Store immediate as 64-bit. 9701'stdw [%d+offset16], imm32' 9702 Store immediate as 32-bit. 9703'stdh [%d+offset16], imm32' 9704 Store immediate as 16-bit. 9705'stdb [%d+offset16], imm32' 9706 Store immediate as 8-bit. 9707 97089.7.4.7 Jump instructions 9709......................... 9710 9711eBPF provides the following compare-and-jump instructions, which compare 9712the values of the two given registers, or the values of a register and 9713an immediate, and perform a branch in case the comparison holds true. 9714 9715'ja %d,(%s|imm32),disp16' 9716 Jump-always. 9717'jeq %d,(%s|imm32),disp16' 9718 Jump if equal. 9719'jgt %d,(%s|imm32),disp16' 9720 Jump if greater. 9721'jge %d,(%s|imm32),disp16' 9722 Jump if greater or equal. 9723'jlt %d,(%s|imm32),disp16' 9724 Jump if lesser. 9725'jle %d,(%s|imm32),disp16' 9726 Jump if lesser or equal. 9727'jset %d,(%s|imm32),disp16' 9728 Jump if signed equal. 9729'jne %d,(%s|imm32),disp16' 9730 Jump if not equal. 9731'jsgt %d,(%s|imm32),disp16' 9732 Jump if signed greater. 9733'jsge %d,(%s|imm32),disp16' 9734 Jump if signed greater or equal. 9735'jslt %d,(%s|imm32),disp16' 9736 Jump if signed lesser. 9737'jsle %d,(%s|imm32),disp16' 9738 Jump if signed lesser or equal. 9739 9740 A call instruction is provided in order to perform calls to other 9741eBPF functions, or to external kernel helpers: 9742 9743'call (disp32|imm32)' 9744 Jump and link to the offset _disp32_, or to the kernel helper 9745 function identified by _imm32_. 9746 9747 Finally: 9748 9749'exit' 9750 Terminate the eBPF program. 9751 97529.7.4.8 Atomic instructions 9753........................... 9754 9755Atomic exchange-and-add instructions are provided in two flavors: one 9756for swapping 64-bit quantities and another for 32-bit quantities. 9757 9758'xadddw [%d+offset16],%s' 9759 Exchange-and-add a 64-bit value at the specified location. 9760'xaddw [%d+offset16],%s' 9761 Exchange-and-add a 32-bit value at the specified location. 9762 9763 9764File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: BPF-Dependent, Up: Machine Dependencies 9765 97669.8 CR16 Dependent Features 9767=========================== 9768 9769* Menu: 9770 9771* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 9772* CR16 Syntax:: Syntax for the CR16 9773 9774 9775File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent 9776 97779.8.1 CR16 Operand Qualifiers 9778----------------------------- 9779 9780The National Semiconductor CR16 target of 'as' has a few machine 9781dependent operand qualifiers. 9782 9783 Operand expression type qualifier is an optional field in the 9784instruction operand, to determines the type of the expression field of 9785an operand. The '@' is required. CR16 architecture uses one of the 9786following expression qualifiers: 9787 9788's' 9789 - 'Specifies expression operand type as small' 9790'm' 9791 - 'Specifies expression operand type as medium' 9792'l' 9793 - 'Specifies expression operand type as large' 9794'c' 9795 - 'Specifies the CR16 Assembler generates a relocation entry for 9796 the operand, where pc has implied bit, the expression is adjusted 9797 accordingly. The linker uses the relocation entry to update the 9798 operand address at link time.' 9799'got/GOT' 9800 - 'Specifies the CR16 Assembler generates a relocation entry for 9801 the operand, offset from Global Offset Table. The linker uses this 9802 relocation entry to update the operand address at link time' 9803'cgot/cGOT' 9804 - 'Specifies the CompactRISC Assembler generates a relocation entry 9805 for the operand, where pc has implied bit, the expression is 9806 adjusted accordingly. The linker uses the relocation entry to 9807 update the operand address at link time.' 9808 9809 CR16 target operand qualifiers and its size (in bits): 9810 9811'Immediate Operand: s' 9812 4 bits. 9813 9814'Immediate Operand: m' 9815 16 bits, for movb and movw instructions. 9816 9817'Immediate Operand: m' 9818 20 bits, movd instructions. 9819 9820'Immediate Operand: l' 9821 32 bits. 9822 9823'Absolute Operand: s' 9824 Illegal specifier for this operand. 9825 9826'Absolute Operand: m' 9827 20 bits, movd instructions. 9828 9829'Displacement Operand: s' 9830 8 bits. 9831 9832'Displacement Operand: m' 9833 16 bits. 9834 9835'Displacement Operand: l' 9836 24 bits. 9837 9838 For example: 9839 1 movw $_myfun@c,r1 9840 9841 This loads the address of _myfun, shifted right by 1, into r1. 9842 9843 2 movd $_myfun@c,(r2,r1) 9844 9845 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 9846 9847 3 _myfun_ptr: 9848 .long _myfun@c 9849 loadd _myfun_ptr, (r1,r0) 9850 jal (r1,r0) 9851 9852 This .long directive, the address of _myfunc, shifted right by 1 at link time. 9853 9854 4 loadd _data1@GOT(r12), (r1,r0) 9855 9856 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 9857 9858 5 loadd _myfunc@cGOT(r12), (r1,r0) 9859 9860 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 9861 9862 9863File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent 9864 98659.8.2 CR16 Syntax 9866----------------- 9867 9868* Menu: 9869 9870* CR16-Chars:: Special Characters 9871 9872 9873File: as.info, Node: CR16-Chars, Up: CR16 Syntax 9874 98759.8.2.1 Special Characters 9876.......................... 9877 9878The presence of a '#' on a line indicates the start of a comment that 9879extends to the end of the current line. If the '#' appears as the first 9880character of a line, the whole line is treated as a comment, but in this 9881case the line can also be a logical line number directive (*note 9882Comments::) or a preprocessor control command (*note Preprocessing::). 9883 9884 The ';' character can be used to separate statements on the same 9885line. 9886 9887 9888File: as.info, Node: CRIS-Dependent, Next: C-SKY-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 9889 98909.9 CRIS Dependent Features 9891=========================== 9892 9893* Menu: 9894 9895* CRIS-Opts:: Command-line Options 9896* CRIS-Expand:: Instruction expansion 9897* CRIS-Symbols:: Symbols 9898* CRIS-Syntax:: Syntax 9899 9900 9901File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 9902 99039.9.1 Command-line Options 9904-------------------------- 9905 9906The CRIS version of 'as' has these machine-dependent command-line 9907options. 9908 9909 The format of the generated object files can be either ELF or a.out, 9910specified by the command-line options '--emulation=crisaout' and 9911'--emulation=criself'. The default is ELF (criself), unless 'as' has 9912been configured specifically for a.out by using the configuration name 9913'cris-axis-aout'. 9914 9915 There are two different link-incompatible ELF object file variants 9916for CRIS, for use in environments where symbols are expected to be 9917prefixed by a leading '_' character and for environments without such a 9918symbol prefix. The variant used for GNU/Linux port has no symbol 9919prefix. Which variant to produce is specified by either of the options 9920'--underscore' and '--no-underscore'. The default is '--underscore'. 9921Since symbols in CRIS a.out objects are expected to have a '_' prefix, 9922specifying '--no-underscore' when generating a.out objects is an error. 9923Besides the object format difference, the effect of this option is to 9924parse register names differently (*note crisnous::). The 9925'--no-underscore' option makes a '$' register prefix mandatory. 9926 9927 The option '--pic' must be passed to 'as' in order to recognize the 9928symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 9929crispic::). This will also affect expansion of instructions. The 9930expansion with '--pic' will use PC-relative rather than (slightly 9931faster) absolute addresses in those expansions. This option is only 9932valid when generating ELF format object files. 9933 9934 The option '--march=ARCHITECTURE' specifies the recognized 9935instruction set and recognized register names. It also controls the 9936architecture type of the object file. Valid values for ARCHITECTURE 9937are: 9938 9939'v0_v10' 9940 All instructions and register names for any architecture variant in 9941 the set v0...v10 are recognized. This is the default if the target 9942 is configured as cris-*. 9943 9944'v10' 9945 Only instructions and register names for CRIS v10 (as found in 9946 ETRAX 100 LX) are recognized. This is the default if the target is 9947 configured as crisv10-*. 9948 9949'v32' 9950 Only instructions and register names for CRIS v32 (code name 9951 Guinness) are recognized. This is the default if the target is 9952 configured as crisv32-*. This value implies '--no-mul-bug-abort'. 9953 (A subsequent '--mul-bug-abort' will turn it back on.) 9954 9955'common_v10_v32' 9956 Only instructions with register names and addressing modes with 9957 opcodes common to the v10 and v32 are recognized. 9958 9959 When '-N' is specified, 'as' will emit a warning when a 16-bit branch 9960instruction is expanded into a 32-bit multiple-instruction construct 9961(*note CRIS-Expand::). 9962 9963 Some versions of the CRIS v10, for example in the Etrax 100 LX, 9964contain a bug that causes destabilizing memory accesses when a multiply 9965instruction is executed with certain values in the first operand just 9966before a cache-miss. When the '--mul-bug-abort' command-line option is 9967active (the default value), 'as' will refuse to assemble a file 9968containing a multiply instruction at a dangerous offset, one that could 9969be the last on a cache-line, or is in a section with insufficient 9970alignment. This placement checking does not catch any case where the 9971multiply instruction is dangerously placed because it is located in a 9972delay-slot. The '--mul-bug-abort' command-line option turns off the 9973checking. 9974 9975 9976File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 9977 99789.9.2 Instruction expansion 9979--------------------------- 9980 9981'as' will silently choose an instruction that fits the operand size for 9982'[register+constant]' operands. For example, the offset '127' in 9983'move.d [r3+127],r4' fits in an instruction using a signed-byte offset. 9984Similarly, 'move.d [r2+32767],r1' will generate an instruction using a 998516-bit offset. For symbolic expressions and constants that do not fit 9986in 16 bits including the sign bit, a 32-bit offset is generated. 9987 9988 For branches, 'as' will expand from a 16-bit branch instruction into 9989a sequence of instructions that can reach a full 32-bit address. Since 9990this does not correspond to a single instruction, such expansions can 9991optionally be warned about. *Note CRIS-Opts::. 9992 9993 If the operand is found to fit the range, a 'lapc' mnemonic will 9994translate to a 'lapcq' instruction. Use 'lapc.d' to force the 32-bit 9995'lapc' instruction. 9996 9997 Similarly, the 'addo' mnemonic will translate to the shortest fitting 9998instruction of 'addoq', 'addo.w' and 'addo.d', when used with a operand 9999that is a constant known at assembly time. 10000 10001 10002File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 10003 100049.9.3 Symbols 10005------------- 10006 10007Some symbols are defined by the assembler. They're intended to be used 10008in conditional assembly, for example: 10009 .if ..asm.arch.cris.v32 10010 CODE FOR CRIS V32 10011 .elseif ..asm.arch.cris.common_v10_v32 10012 CODE COMMON TO CRIS V32 AND CRIS V10 10013 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 10014 CODE FOR V10 10015 .else 10016 .error "Code needs to be added here." 10017 .endif 10018 10019 These symbols are defined in the assembler, reflecting command-line 10020options, either when specified or the default. They are always defined, 10021to 0 or 1. 10022 10023'..asm.arch.cris.any_v0_v10' 10024 This symbol is non-zero when '--march=v0_v10' is specified or the 10025 default. 10026 10027'..asm.arch.cris.common_v10_v32' 10028 Set according to the option '--march=common_v10_v32'. 10029 10030'..asm.arch.cris.v10' 10031 Reflects the option '--march=v10'. 10032 10033'..asm.arch.cris.v32' 10034 Corresponds to '--march=v10'. 10035 10036 Speaking of symbols, when a symbol is used in code, it can have a 10037suffix modifying its value for use in position-independent code. *Note 10038CRIS-Pic::. 10039 10040 10041File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 10042 100439.9.4 Syntax 10044------------ 10045 10046There are different aspects of the CRIS assembly syntax. 10047 10048* Menu: 10049 10050* CRIS-Chars:: Special Characters 10051* CRIS-Pic:: Position-Independent Code Symbols 10052* CRIS-Regs:: Register Names 10053* CRIS-Pseudos:: Assembler Directives 10054 10055 10056File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 10057 100589.9.4.1 Special Characters 10059.......................... 10060 10061The character '#' is a line comment character. It starts a comment if 10062and only if it is placed at the beginning of a line. 10063 10064 A ';' character starts a comment anywhere on the line, causing all 10065characters up to the end of the line to be ignored. 10066 10067 A '@' character is handled as a line separator equivalent to a 10068logical new-line character (except in a comment), so separate 10069instructions can be specified on a single line. 10070 10071 10072File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 10073 100749.9.4.2 Symbols in position-independent code 10075............................................ 10076 10077When generating position-independent code (SVR4 PIC) for use in 10078cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 10079suffixes are used to specify what kind of run-time symbol lookup will be 10080used, expressed in the object as different _relocation types_. Usually, 10081all absolute symbol values must be located in a table, the _global 10082offset table_, leaving the code position-independent; independent of 10083values of global symbols and independent of the address of the code. 10084The suffix modifies the value of the symbol, into for example an index 10085into the global offset table where the real symbol value is entered, or 10086a PC-relative value, or a value relative to the start of the global 10087offset table. All symbol suffixes start with the character ':' (omitted 10088in the list below). Every symbol use in code or a read-only section 10089must therefore have a PIC suffix to enable a useful shared library to be 10090created. Usually, these constructs must not be used with an additive 10091constant offset as is usually allowed, i.e. no 4 as in 'symbol + 4' is 10092allowed. This restriction is checked at link-time, not at 10093assembly-time. 10094 10095'GOT' 10096 10097 Attaching this suffix to a symbol in an instruction causes the 10098 symbol to be entered into the global offset table. The value is a 10099 32-bit index for that symbol into the global offset table. The 10100 name of the corresponding relocation is 'R_CRIS_32_GOT'. Example: 10101 'move.d [$r0+extsym:GOT],$r9' 10102 10103'GOT16' 10104 10105 Same as for 'GOT', but the value is a 16-bit index into the global 10106 offset table. The corresponding relocation is 'R_CRIS_16_GOT'. 10107 Example: 'move.d [$r0+asymbol:GOT16],$r10' 10108 10109'PLT' 10110 10111 This suffix is used for function symbols. It causes a _procedure 10112 linkage table_, an array of code stubs, to be created at the time 10113 the shared object is created or linked against, together with a 10114 global offset table entry. The value is a pc-relative offset to 10115 the corresponding stub code in the procedure linkage table. This 10116 arrangement causes the run-time symbol resolver to be called to 10117 look up and set the value of the symbol the first time the function 10118 is called (at latest; depending environment variables). It is only 10119 safe to leave the symbol unresolved this way if all references are 10120 function calls. The name of the relocation is 10121 'R_CRIS_32_PLT_PCREL'. Example: 'add.d fnname:PLT,$pc' 10122 10123'PLTG' 10124 10125 Like PLT, but the value is relative to the beginning of the global 10126 offset table. The relocation is 'R_CRIS_32_PLT_GOTREL'. Example: 10127 'move.d fnname:PLTG,$r3' 10128 10129'GOTPLT' 10130 10131 Similar to 'PLT', but the value of the symbol is a 32-bit index 10132 into the global offset table. This is somewhat of a mix between 10133 the effect of the 'GOT' and the 'PLT' suffix; the difference to 10134 'GOT' is that there will be a procedure linkage table entry 10135 created, and that the symbol is assumed to be a function entry and 10136 will be resolved by the run-time resolver as with 'PLT'. The 10137 relocation is 'R_CRIS_32_GOTPLT'. Example: 'jsr 10138 [$r0+fnname:GOTPLT]' 10139 10140'GOTPLT16' 10141 10142 A variant of 'GOTPLT' giving a 16-bit value. Its relocation name 10143 is 'R_CRIS_16_GOTPLT'. Example: 'jsr [$r0+fnname:GOTPLT16]' 10144 10145'GOTOFF' 10146 10147 This suffix must only be attached to a local symbol, but may be 10148 used in an expression adding an offset. The value is the address 10149 of the symbol relative to the start of the global offset table. 10150 The relocation name is 'R_CRIS_32_GOTREL'. Example: 'move.d 10151 [$r0+localsym:GOTOFF],r3' 10152 10153 10154File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 10155 101569.9.4.3 Register names 10157...................... 10158 10159A '$' character may always prefix a general or special register name in 10160an instruction operand but is mandatory when the option 10161'--no-underscore' is specified or when the '.syntax register_prefix' 10162directive is in effect (*note crisnous::). Register names are 10163case-insensitive. 10164 10165 10166File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 10167 101689.9.4.4 Assembler Directives 10169............................ 10170 10171There are a few CRIS-specific pseudo-directives in addition to the 10172generic ones. *Note Pseudo Ops::. Constants emitted by 10173pseudo-directives are in little-endian order for CRIS. There is no 10174support for floating-point-specific directives for CRIS. 10175 10176'.dword EXPRESSIONS' 10177 10178 The '.dword' directive is a synonym for '.int', expecting zero or 10179 more EXPRESSIONS, separated by commas. For each expression, a 10180 32-bit little-endian constant is emitted. 10181 10182'.syntax ARGUMENT' 10183 The '.syntax' directive takes as ARGUMENT one of the following 10184 case-sensitive choices. 10185 10186 'no_register_prefix' 10187 10188 The '.syntax no_register_prefix' directive makes a '$' 10189 character prefix on all registers optional. It overrides a 10190 previous setting, including the corresponding effect of the 10191 option '--no-underscore'. If this directive is used when 10192 ordinary symbols do not have a '_' character prefix, care must 10193 be taken to avoid ambiguities whether an operand is a register 10194 or a symbol; using symbols with names the same as general or 10195 special registers then invoke undefined behavior. 10196 10197 'register_prefix' 10198 10199 This directive makes a '$' character prefix on all registers 10200 mandatory. It overrides a previous setting, including the 10201 corresponding effect of the option '--underscore'. 10202 10203 'leading_underscore' 10204 10205 This is an assertion directive, emitting an error if the 10206 '--no-underscore' option is in effect. 10207 10208 'no_leading_underscore' 10209 10210 This is the opposite of the '.syntax leading_underscore' 10211 directive and emits an error if the option '--underscore' is 10212 in effect. 10213 10214'.arch ARGUMENT' 10215 This is an assertion directive, giving an error if the specified 10216 ARGUMENT is not the same as the specified or default value for the 10217 '--march=ARCHITECTURE' option (*note march-option::). 10218 10219 10220File: as.info, Node: C-SKY-Dependent, Next: D10V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 10221 102229.10 C-SKY Dependent Features 10223============================= 10224 10225* Menu: 10226 10227* C-SKY Options:: Options 10228* C-SKY Syntax:: Syntax 10229 10230 10231File: as.info, Node: C-SKY Options, Next: C-SKY Syntax, Up: C-SKY-Dependent 10232 102339.10.1 Options 10234-------------- 10235 10236'-march=ARCHNAME' 10237 Assemble for architecture ARCHNAME. The '--help' option lists 10238 valid values for ARCHNAME. 10239 10240'-mcpu=CPUNAME' 10241 Assemble for architecture CPUNAME. The '--help' option lists valid 10242 values for CPUNAME. 10243 10244'-EL' 10245'-mlittle-endian' 10246 Generate little-endian output. 10247 10248'-EB' 10249'-mbig-endian' 10250 Generate big-endian output. 10251 10252'-fpic' 10253'-pic' 10254 Generate position-independent code. 10255 10256'-mljump' 10257'-mno-ljump' 10258 Enable/disable transformation of the short branch instructions 10259 'jbf', 'jbt', and 'jbr' to 'jmpi'. This option is for V2 10260 processors only. It is ignored on CK801 and CK802 targets, which 10261 do not support the 'jmpi' instruction, and is enabled by default 10262 for other processors. 10263 10264'-mbranch-stub' 10265'-mno-branch-stub' 10266 Pass through 'R_CKCORE_PCREL_IMM26BY2' relocations for 'bsr' 10267 instructions to the linker. 10268 10269 This option is only available for bare-metal C-SKY V2 ELF targets, 10270 where it is enabled by default. It cannot be used in code that 10271 will be dynamically linked against shared libraries. 10272 10273'-force2bsr' 10274'-mforce2bsr' 10275'-no-force2bsr' 10276'-mno-force2bsr' 10277 Enable/disable transformation of 'jbsr' instructions to 'bsr'. 10278 This option is always enabled (and '-mno-force2bsr' is ignored) for 10279 CK801/CK802 targets. It is also always enabled when 10280 '-mbranch-stub' is in effect. 10281 10282'-jsri2bsr' 10283'-mjsri2bsr' 10284'-no-jsri2bsr' 10285'-mno-jsri2bsr' 10286 Enable/disable transformation of 'jsri' instructions to 'bsr'. 10287 This option is enabled by default. 10288 10289'-mnolrw' 10290'-mno-lrw' 10291 Enable/disable transformation of 'lrw' instructions into a 10292 'movih'/'ori' pair. 10293 10294'-melrw' 10295'-mno-elrw' 10296 Enable/disable extended 'lrw' instructions. This option is enabled 10297 by default for CK800-series processors. 10298 10299'-mlaf' 10300'-mliterals-after-func' 10301'-mno-laf' 10302'-mno-literals-after-func' 10303 Enable/disable placement of literal pools after each function. 10304 10305'-mlabr' 10306'-mliterals-after-br' 10307'-mno-labr' 10308'-mnoliterals-after-br' 10309 Enable/disable placement of literal pools after unconditional 10310 branches. This option is enabled by default. 10311 10312'-mistack' 10313'-mno-istack' 10314 Enable/disable interrupt stack instructions. This option is 10315 enabled by default on CK801, CK802, and CK802 processors. 10316 10317 The following options explicitly enable certain optional 10318instructions. These features are also enabled implicitly by using 10319'-mcpu=' to specify a processor that supports it. 10320 10321'-mhard-float' 10322 Enable hard float instructions. 10323 10324'-mmp' 10325 Enable multiprocessor instructions. 10326 10327'-mcp' 10328 Enable coprocessor instructions. 10329 10330'-mcache' 10331 Enable cache prefetch instruction. 10332 10333'-msecurity' 10334 Enable C-SKY security instructions. 10335 10336'-mtrust' 10337 Enable C-SKY trust instructions. 10338 10339'-mdsp' 10340 Enable DSP instructions. 10341 10342'-medsp' 10343 Enable enhanced DSP instructions. 10344 10345'-mvdsp' 10346 Enable vector DSP instructions. 10347 10348 10349File: as.info, Node: C-SKY Syntax, Prev: C-SKY Options, Up: C-SKY-Dependent 10350 103519.10.2 Syntax 10352------------- 10353 10354'as' implements the standard C-SKY assembler syntax documented in the 10355'C-SKY V2 CPU Applications Binary Interface Standards Manual'. 10356 10357 10358File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: C-SKY-Dependent, Up: Machine Dependencies 10359 103609.11 D10V Dependent Features 10361============================ 10362 10363* Menu: 10364 10365* D10V-Opts:: D10V Options 10366* D10V-Syntax:: Syntax 10367* D10V-Float:: Floating Point 10368* D10V-Opcodes:: Opcodes 10369 10370 10371File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 10372 103739.11.1 D10V Options 10374------------------- 10375 10376The Mitsubishi D10V version of 'as' has a few machine dependent options. 10377 10378'-O' 10379 The D10V can often execute two sub-instructions in parallel. When 10380 this option is used, 'as' will attempt to optimize its output by 10381 detecting when instructions can be executed in parallel. 10382'--nowarnswap' 10383 To optimize execution performance, 'as' will sometimes swap the 10384 order of instructions. Normally this generates a warning. When 10385 this option is used, no warning will be generated when instructions 10386 are swapped. 10387'--gstabs-packing' 10388'--no-gstabs-packing' 10389 'as' packs adjacent short instructions into a single packed 10390 instruction. '--no-gstabs-packing' turns instruction packing off 10391 if '--gstabs' is specified as well; '--gstabs-packing' (the 10392 default) turns instruction packing on even when '--gstabs' is 10393 specified. 10394 10395 10396File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 10397 103989.11.2 Syntax 10399------------- 10400 10401The D10V syntax is based on the syntax in Mitsubishi's D10V architecture 10402manual. The differences are detailed below. 10403 10404* Menu: 10405 10406* D10V-Size:: Size Modifiers 10407* D10V-Subs:: Sub-Instructions 10408* D10V-Chars:: Special Characters 10409* D10V-Regs:: Register Names 10410* D10V-Addressing:: Addressing Modes 10411* D10V-Word:: @WORD Modifier 10412 10413 10414File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 10415 104169.11.2.1 Size Modifiers 10417....................... 10418 10419The D10V version of 'as' uses the instruction names in the D10V 10420Architecture Manual. However, the names in the manual are sometimes 10421ambiguous. There are instruction names that can assemble to a short or 10422long form opcode. How does the assembler pick the correct form? 'as' 10423will always pick the smallest form if it can. When dealing with a 10424symbol that is not defined yet when a line is being assembled, it will 10425always use the long form. If you need to force the assembler to use 10426either the short or long form of the instruction, you can append either 10427'.s' (short) or '.l' (long) to it. For example, if you are writing an 10428assembly program and you want to do a branch to a symbol that is defined 10429later in your program, you can write 'bra.s foo'. Objdump and GDB will 10430always append '.s' or '.l' to instructions which have both short and 10431long forms. 10432 10433 10434File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 10435 104369.11.2.2 Sub-Instructions 10437......................... 10438 10439The D10V assembler takes as input a series of instructions, either 10440one-per-line, or in the special two-per-line format described in the 10441next section. Some of these instructions will be short-form or 10442sub-instructions. These sub-instructions can be packed into a single 10443instruction. The assembler will do this automatically. It will also 10444detect when it should not pack instructions. For example, when a label 10445is defined, the next instruction will never be packaged with the 10446previous one. Whenever a branch and link instruction is called, it will 10447not be packaged with the next instruction so the return address will be 10448valid. Nops are automatically inserted when necessary. 10449 10450 If you do not want the assembler automatically making these 10451decisions, you can control the packaging and execution type (parallel or 10452sequential) with the special execution symbols described in the next 10453section. 10454 10455 10456File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 10457 104589.11.2.3 Special Characters 10459........................... 10460 10461A semicolon (';') can be used anywhere on a line to start a comment that 10462extends to the end of the line. 10463 10464 If a '#' appears as the first character of a line, the whole line is 10465treated as a comment, but in this case the line could also be a logical 10466line number directive (*note Comments::) or a preprocessor control 10467command (*note Preprocessing::). 10468 10469 Sub-instructions may be executed in order, in reverse-order, or in 10470parallel. Instructions listed in the standard one-per-line format will 10471be executed sequentially. To specify the executing order, use the 10472following symbols: 10473'->' 10474 Sequential with instruction on the left first. 10475'<-' 10476 Sequential with instruction on the right first. 10477'||' 10478 Parallel 10479 The D10V syntax allows either one instruction per line, one 10480instruction per line with the execution symbol, or two instructions per 10481line. For example 10482'abs a1 -> abs r0' 10483 Execute these sequentially. The instruction on the right is in the 10484 right container and is executed second. 10485'abs r0 <- abs a1' 10486 Execute these reverse-sequentially. The instruction on the right 10487 is in the right container, and is executed first. 10488'ld2w r2,@r8+ || mac a0,r0,r7' 10489 Execute these in parallel. 10490'ld2w r2,@r8+ ||' 10491'mac a0,r0,r7' 10492 Two-line format. Execute these in parallel. 10493'ld2w r2,@r8+' 10494'mac a0,r0,r7' 10495 Two-line format. Execute these sequentially. Assembler will put 10496 them in the proper containers. 10497'ld2w r2,@r8+ ->' 10498'mac a0,r0,r7' 10499 Two-line format. Execute these sequentially. Same as above but 10500 second instruction will always go into right container. 10501 Since '$' has no special meaning, you may use it in symbol names. 10502 10503 10504File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 10505 105069.11.2.4 Register Names 10507....................... 10508 10509You can use the predefined symbols 'r0' through 'r15' to refer to the 10510D10V registers. You can also use 'sp' as an alias for 'r15'. The 10511accumulators are 'a0' and 'a1'. There are special register-pair names 10512that may optionally be used in opcodes that require even-numbered 10513registers. Register names are not case sensitive. 10514 10515 Register Pairs 10516'r0-r1' 10517'r2-r3' 10518'r4-r5' 10519'r6-r7' 10520'r8-r9' 10521'r10-r11' 10522'r12-r13' 10523'r14-r15' 10524 10525 The D10V also has predefined symbols for these control registers and 10526status bits: 10527'psw' 10528 Processor Status Word 10529'bpsw' 10530 Backup Processor Status Word 10531'pc' 10532 Program Counter 10533'bpc' 10534 Backup Program Counter 10535'rpt_c' 10536 Repeat Count 10537'rpt_s' 10538 Repeat Start address 10539'rpt_e' 10540 Repeat End address 10541'mod_s' 10542 Modulo Start address 10543'mod_e' 10544 Modulo End address 10545'iba' 10546 Instruction Break Address 10547'f0' 10548 Flag 0 10549'f1' 10550 Flag 1 10551'c' 10552 Carry flag 10553 10554 10555File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 10556 105579.11.2.5 Addressing Modes 10558......................... 10559 10560'as' understands the following addressing modes for the D10V. 'RN' in 10561the following refers to any of the numbered registers, but _not_ the 10562control registers. 10563'RN' 10564 Register direct 10565'@RN' 10566 Register indirect 10567'@RN+' 10568 Register indirect with post-increment 10569'@RN-' 10570 Register indirect with post-decrement 10571'@-SP' 10572 Register indirect with pre-decrement 10573'@(DISP, RN)' 10574 Register indirect with displacement 10575'ADDR' 10576 PC relative address (for branch or rep). 10577'#IMM' 10578 Immediate data (the '#' is optional and ignored) 10579 10580 10581File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 10582 105839.11.2.6 @WORD Modifier 10584....................... 10585 10586Any symbol followed by '@word' will be replaced by the symbol's value 10587shifted right by 2. This is used in situations such as loading a 10588register with the address of a function (or any other code fragment). 10589For example, if you want to load a register with the location of the 10590function 'main' then jump to that function, you could do it as follows: 10591 ldi r2, main@word 10592 jmp r2 10593 10594 10595File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 10596 105979.11.3 Floating Point 10598--------------------- 10599 10600The D10V has no hardware floating point, but the '.float' and '.double' 10601directives generates IEEE floating-point numbers for compatibility with 10602other development tools. 10603 10604 10605File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 10606 106079.11.4 Opcodes 10608-------------- 10609 10610For detailed information on the D10V machine instruction set, see 'D10V 10611Architecture: A VLIW Microprocessor for Multimedia Applications' 10612(Mitsubishi Electric Corp.). 'as' implements all the standard D10V 10613opcodes. The only changes are those described in the section on size 10614modifiers 10615 10616 10617File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 10618 106199.12 D30V Dependent Features 10620============================ 10621 10622* Menu: 10623 10624* D30V-Opts:: D30V Options 10625* D30V-Syntax:: Syntax 10626* D30V-Float:: Floating Point 10627* D30V-Opcodes:: Opcodes 10628 10629 10630File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 10631 106329.12.1 D30V Options 10633------------------- 10634 10635The Mitsubishi D30V version of 'as' has a few machine dependent options. 10636 10637'-O' 10638 The D30V can often execute two sub-instructions in parallel. When 10639 this option is used, 'as' will attempt to optimize its output by 10640 detecting when instructions can be executed in parallel. 10641 10642'-n' 10643 When this option is used, 'as' will issue a warning every time it 10644 adds a nop instruction. 10645 10646'-N' 10647 When this option is used, 'as' will issue a warning if it needs to 10648 insert a nop after a 32-bit multiply before a load or 16-bit 10649 multiply instruction. 10650 10651 10652File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 10653 106549.12.2 Syntax 10655------------- 10656 10657The D30V syntax is based on the syntax in Mitsubishi's D30V architecture 10658manual. The differences are detailed below. 10659 10660* Menu: 10661 10662* D30V-Size:: Size Modifiers 10663* D30V-Subs:: Sub-Instructions 10664* D30V-Chars:: Special Characters 10665* D30V-Guarded:: Guarded Execution 10666* D30V-Regs:: Register Names 10667* D30V-Addressing:: Addressing Modes 10668 10669 10670File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 10671 106729.12.2.1 Size Modifiers 10673....................... 10674 10675The D30V version of 'as' uses the instruction names in the D30V 10676Architecture Manual. However, the names in the manual are sometimes 10677ambiguous. There are instruction names that can assemble to a short or 10678long form opcode. How does the assembler pick the correct form? 'as' 10679will always pick the smallest form if it can. When dealing with a 10680symbol that is not defined yet when a line is being assembled, it will 10681always use the long form. If you need to force the assembler to use 10682either the short or long form of the instruction, you can append either 10683'.s' (short) or '.l' (long) to it. For example, if you are writing an 10684assembly program and you want to do a branch to a symbol that is defined 10685later in your program, you can write 'bra.s foo'. Objdump and GDB will 10686always append '.s' or '.l' to instructions which have both short and 10687long forms. 10688 10689 10690File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 10691 106929.12.2.2 Sub-Instructions 10693......................... 10694 10695The D30V assembler takes as input a series of instructions, either 10696one-per-line, or in the special two-per-line format described in the 10697next section. Some of these instructions will be short-form or 10698sub-instructions. These sub-instructions can be packed into a single 10699instruction. The assembler will do this automatically. It will also 10700detect when it should not pack instructions. For example, when a label 10701is defined, the next instruction will never be packaged with the 10702previous one. Whenever a branch and link instruction is called, it will 10703not be packaged with the next instruction so the return address will be 10704valid. Nops are automatically inserted when necessary. 10705 10706 If you do not want the assembler automatically making these 10707decisions, you can control the packaging and execution type (parallel or 10708sequential) with the special execution symbols described in the next 10709section. 10710 10711 10712File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 10713 107149.12.2.3 Special Characters 10715........................... 10716 10717A semicolon (';') can be used anywhere on a line to start a comment that 10718extends to the end of the line. 10719 10720 If a '#' appears as the first character of a line, the whole line is 10721treated as a comment, but in this case the line could also be a logical 10722line number directive (*note Comments::) or a preprocessor control 10723command (*note Preprocessing::). 10724 10725 Sub-instructions may be executed in order, in reverse-order, or in 10726parallel. Instructions listed in the standard one-per-line format will 10727be executed sequentially unless you use the '-O' option. 10728 10729 To specify the executing order, use the following symbols: 10730'->' 10731 Sequential with instruction on the left first. 10732 10733'<-' 10734 Sequential with instruction on the right first. 10735 10736'||' 10737 Parallel 10738 10739 The D30V syntax allows either one instruction per line, one 10740instruction per line with the execution symbol, or two instructions per 10741line. For example 10742'abs r2,r3 -> abs r4,r5' 10743 Execute these sequentially. The instruction on the right is in the 10744 right container and is executed second. 10745 10746'abs r2,r3 <- abs r4,r5' 10747 Execute these reverse-sequentially. The instruction on the right 10748 is in the right container, and is executed first. 10749 10750'abs r2,r3 || abs r4,r5' 10751 Execute these in parallel. 10752 10753'ldw r2,@(r3,r4) ||' 10754'mulx r6,r8,r9' 10755 Two-line format. Execute these in parallel. 10756 10757'mulx a0,r8,r9' 10758'stw r2,@(r3,r4)' 10759 Two-line format. Execute these sequentially unless '-O' option is 10760 used. If the '-O' option is used, the assembler will determine if 10761 the instructions could be done in parallel (the above two 10762 instructions can be done in parallel), and if so, emit them as 10763 parallel instructions. The assembler will put them in the proper 10764 containers. In the above example, the assembler will put the 'stw' 10765 instruction in left container and the 'mulx' instruction in the 10766 right container. 10767 10768'stw r2,@(r3,r4) ->' 10769'mulx a0,r8,r9' 10770 Two-line format. Execute the 'stw' instruction followed by the 10771 'mulx' instruction sequentially. The first instruction goes in the 10772 left container and the second instruction goes into right 10773 container. The assembler will give an error if the machine 10774 ordering constraints are violated. 10775 10776'stw r2,@(r3,r4) <-' 10777'mulx a0,r8,r9' 10778 Same as previous example, except that the 'mulx' instruction is 10779 executed before the 'stw' instruction. 10780 10781 Since '$' has no special meaning, you may use it in symbol names. 10782 10783 10784File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 10785 107869.12.2.4 Guarded Execution 10787.......................... 10788 10789'as' supports the full range of guarded execution directives for each 10790instruction. Just append the directive after the instruction proper. 10791The directives are: 10792 10793'/tx' 10794 Execute the instruction if flag f0 is true. 10795'/fx' 10796 Execute the instruction if flag f0 is false. 10797'/xt' 10798 Execute the instruction if flag f1 is true. 10799'/xf' 10800 Execute the instruction if flag f1 is false. 10801'/tt' 10802 Execute the instruction if both flags f0 and f1 are true. 10803'/tf' 10804 Execute the instruction if flag f0 is true and flag f1 is false. 10805 10806 10807File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 10808 108099.12.2.5 Register Names 10810....................... 10811 10812You can use the predefined symbols 'r0' through 'r63' to refer to the 10813D30V registers. You can also use 'sp' as an alias for 'r63' and 'link' 10814as an alias for 'r62'. The accumulators are 'a0' and 'a1'. 10815 10816 The D30V also has predefined symbols for these control registers and 10817status bits: 10818'psw' 10819 Processor Status Word 10820'bpsw' 10821 Backup Processor Status Word 10822'pc' 10823 Program Counter 10824'bpc' 10825 Backup Program Counter 10826'rpt_c' 10827 Repeat Count 10828'rpt_s' 10829 Repeat Start address 10830'rpt_e' 10831 Repeat End address 10832'mod_s' 10833 Modulo Start address 10834'mod_e' 10835 Modulo End address 10836'iba' 10837 Instruction Break Address 10838'f0' 10839 Flag 0 10840'f1' 10841 Flag 1 10842'f2' 10843 Flag 2 10844'f3' 10845 Flag 3 10846'f4' 10847 Flag 4 10848'f5' 10849 Flag 5 10850'f6' 10851 Flag 6 10852'f7' 10853 Flag 7 10854's' 10855 Same as flag 4 (saturation flag) 10856'v' 10857 Same as flag 5 (overflow flag) 10858'va' 10859 Same as flag 6 (sticky overflow flag) 10860'c' 10861 Same as flag 7 (carry/borrow flag) 10862'b' 10863 Same as flag 7 (carry/borrow flag) 10864 10865 10866File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 10867 108689.12.2.6 Addressing Modes 10869......................... 10870 10871'as' understands the following addressing modes for the D30V. 'RN' in 10872the following refers to any of the numbered registers, but _not_ the 10873control registers. 10874'RN' 10875 Register direct 10876'@RN' 10877 Register indirect 10878'@RN+' 10879 Register indirect with post-increment 10880'@RN-' 10881 Register indirect with post-decrement 10882'@-SP' 10883 Register indirect with pre-decrement 10884'@(DISP, RN)' 10885 Register indirect with displacement 10886'ADDR' 10887 PC relative address (for branch or rep). 10888'#IMM' 10889 Immediate data (the '#' is optional and ignored) 10890 10891 10892File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 10893 108949.12.3 Floating Point 10895--------------------- 10896 10897The D30V has no hardware floating point, but the '.float' and '.double' 10898directives generates IEEE floating-point numbers for compatibility with 10899other development tools. 10900 10901 10902File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 10903 109049.12.4 Opcodes 10905-------------- 10906 10907For detailed information on the D30V machine instruction set, see 'D30V 10908Architecture: A VLIW Microprocessor for Multimedia Applications' 10909(Mitsubishi Electric Corp.). 'as' implements all the standard D30V 10910opcodes. The only changes are those described in the section on size 10911modifiers 10912 10913 10914File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 10915 109169.13 Epiphany Dependent Features 10917================================ 10918 10919* Menu: 10920 10921* Epiphany Options:: Options 10922* Epiphany Syntax:: Epiphany Syntax 10923 10924 10925File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent 10926 109279.13.1 Options 10928-------------- 10929 10930'as' has two additional command-line options for the Epiphany 10931architecture. 10932 10933'-mepiphany' 10934 Specifies that the both 32 and 16 bit instructions are allowed. 10935 This is the default behavior. 10936 10937'-mepiphany16' 10938 Restricts the permitted instructions to just the 16 bit set. 10939 10940 10941File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent 10942 109439.13.2 Epiphany Syntax 10944---------------------- 10945 10946* Menu: 10947 10948* Epiphany-Chars:: Special Characters 10949 10950 10951File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax 10952 109539.13.2.1 Special Characters 10954........................... 10955 10956The presence of a ';' on a line indicates the start of a comment that 10957extends to the end of the current line. 10958 10959 If a '#' appears as the first character of a line then the whole line 10960is treated as a comment, but in this case the line could also be a 10961logical line number directive (*note Comments::) or a preprocessor 10962control command (*note Preprocessing::). 10963 10964 The '`' character can be used to separate statements on the same 10965line. 10966 10967 10968File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies 10969 109709.14 H8/300 Dependent Features 10971============================== 10972 10973* Menu: 10974 10975* H8/300 Options:: Options 10976* H8/300 Syntax:: Syntax 10977* H8/300 Floating Point:: Floating Point 10978* H8/300 Directives:: H8/300 Machine Directives 10979* H8/300 Opcodes:: Opcodes 10980 10981 10982File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 10983 109849.14.1 Options 10985-------------- 10986 10987The Renesas H8/300 version of 'as' has one machine-dependent option: 10988 10989'-h-tick-hex' 10990 Support H'00 style hex constants in addition to 0x00 style. 10991 10992'-mach=NAME' 10993 Sets the H8300 machine variant. The following machine names are 10994 recognised: 'h8300h', 'h8300hn', 'h8300s', 'h8300sn', 'h8300sx' and 10995 'h8300sxn'. 10996 10997 10998File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 10999 110009.14.2 Syntax 11001------------- 11002 11003* Menu: 11004 11005* H8/300-Chars:: Special Characters 11006* H8/300-Regs:: Register Names 11007* H8/300-Addressing:: Addressing Modes 11008 11009 11010File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 11011 110129.14.2.1 Special Characters 11013........................... 11014 11015';' is the line comment character. 11016 11017 '$' can be used instead of a newline to separate statements. 11018Therefore _you may not use '$' in symbol names_ on the H8/300. 11019 11020 11021File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 11022 110239.14.2.2 Register Names 11024....................... 11025 11026You can use predefined symbols of the form 'rNh' and 'rNl' to refer to 11027the H8/300 registers as sixteen 8-bit general-purpose registers. N is a 11028digit from '0' to '7'); for instance, both 'r0h' and 'r7l' are valid 11029register names. 11030 11031 You can also use the eight predefined symbols 'rN' to refer to the 11032H8/300 registers as 16-bit registers (you must use this form for 11033addressing). 11034 11035 On the H8/300H, you can also use the eight predefined symbols 'erN' 11036('er0' ... 'er7') to refer to the 32-bit general purpose registers. 11037 11038 The two control registers are called 'pc' (program counter; a 16-bit 11039register, except on the H8/300H where it is 24 bits) and 'ccr' 11040(condition code register; an 8-bit register). 'r7' is used as the stack 11041pointer, and can also be called 'sp'. 11042 11043 11044File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 11045 110469.14.2.3 Addressing Modes 11047......................... 11048 11049as understands the following addressing modes for the H8/300: 11050'rN' 11051 Register direct 11052 11053'@rN' 11054 Register indirect 11055 11056'@(D, rN)' 11057'@(D:16, rN)' 11058'@(D:24, rN)' 11059 Register indirect: 16-bit or 24-bit displacement D from register N. 11060 (24-bit displacements are only meaningful on the H8/300H.) 11061 11062'@rN+' 11063 Register indirect with post-increment 11064 11065'@-rN' 11066 Register indirect with pre-decrement 11067 11068'@AA' 11069'@AA:8' 11070'@AA:16' 11071'@AA:24' 11072 Absolute address 'aa'. (The address size ':24' only makes sense on 11073 the H8/300H.) 11074 11075'#XX' 11076'#XX:8' 11077'#XX:16' 11078'#XX:32' 11079 Immediate data XX. You may specify the ':8', ':16', or ':32' for 11080 clarity, if you wish; but 'as' neither requires this nor uses 11081 it--the data size required is taken from context. 11082 11083'@@AA' 11084'@@AA:8' 11085 Memory indirect. You may specify the ':8' for clarity, if you 11086 wish; but 'as' neither requires this nor uses it. 11087 11088 11089File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 11090 110919.14.3 Floating Point 11092--------------------- 11093 11094The H8/300 family has no hardware floating point, but the '.float' 11095directive generates IEEE floating-point numbers for compatibility with 11096other development tools. 11097 11098 11099File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 11100 111019.14.4 H8/300 Machine Directives 11102-------------------------------- 11103 11104'as' has the following machine-dependent directives for the H8/300: 11105 11106'.h8300h' 11107 Recognize and emit additional instructions for the H8/300H variant, 11108 and also make '.int' emit 32-bit numbers rather than the usual 11109 (16-bit) for the H8/300 family. 11110 11111'.h8300s' 11112 Recognize and emit additional instructions for the H8S variant, and 11113 also make '.int' emit 32-bit numbers rather than the usual (16-bit) 11114 for the H8/300 family. 11115 11116'.h8300hn' 11117 Recognize and emit additional instructions for the H8/300H variant 11118 in normal mode, and also make '.int' emit 32-bit numbers rather 11119 than the usual (16-bit) for the H8/300 family. 11120 11121'.h8300sn' 11122 Recognize and emit additional instructions for the H8S variant in 11123 normal mode, and also make '.int' emit 32-bit numbers rather than 11124 the usual (16-bit) for the H8/300 family. 11125 11126 On the H8/300 family (including the H8/300H) '.word' directives 11127generate 16-bit numbers. 11128 11129 11130File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 11131 111329.14.5 Opcodes 11133-------------- 11134 11135For detailed information on the H8/300 machine instruction set, see 11136'H8/300 Series Programming Manual'. For information specific to the 11137H8/300H, see 'H8/300H Series Programming Manual' (Renesas). 11138 11139 'as' implements all the standard H8/300 opcodes. No additional 11140pseudo-instructions are needed on this family. 11141 11142 The following table summarizes the H8/300 opcodes, and their 11143arguments. Entries marked '*' are opcodes used only on the H8/300H. 11144 11145 Legend: 11146 Rs source register 11147 Rd destination register 11148 abs absolute address 11149 imm immediate data 11150 disp:N N-bit displacement from a register 11151 pcrel:N N-bit displacement relative to program counter 11152 11153 add.b #imm,rd * andc #imm,ccr 11154 add.b rs,rd band #imm,rd 11155 add.w rs,rd band #imm,@rd 11156 * add.w #imm,rd band #imm,@abs:8 11157 * add.l rs,rd bra pcrel:8 11158 * add.l #imm,rd * bra pcrel:16 11159 adds #imm,rd bt pcrel:8 11160 addx #imm,rd * bt pcrel:16 11161 addx rs,rd brn pcrel:8 11162 and.b #imm,rd * brn pcrel:16 11163 and.b rs,rd bf pcrel:8 11164 * and.w rs,rd * bf pcrel:16 11165 * and.w #imm,rd bhi pcrel:8 11166 * and.l #imm,rd * bhi pcrel:16 11167 * and.l rs,rd bls pcrel:8 11168 * bls pcrel:16 bld #imm,rd 11169 bcc pcrel:8 bld #imm,@rd 11170 * bcc pcrel:16 bld #imm,@abs:8 11171 bhs pcrel:8 bnot #imm,rd 11172 * bhs pcrel:16 bnot #imm,@rd 11173 bcs pcrel:8 bnot #imm,@abs:8 11174 * bcs pcrel:16 bnot rs,rd 11175 blo pcrel:8 bnot rs,@rd 11176 * blo pcrel:16 bnot rs,@abs:8 11177 bne pcrel:8 bor #imm,rd 11178 * bne pcrel:16 bor #imm,@rd 11179 beq pcrel:8 bor #imm,@abs:8 11180 * beq pcrel:16 bset #imm,rd 11181 bvc pcrel:8 bset #imm,@rd 11182 * bvc pcrel:16 bset #imm,@abs:8 11183 bvs pcrel:8 bset rs,rd 11184 * bvs pcrel:16 bset rs,@rd 11185 bpl pcrel:8 bset rs,@abs:8 11186 * bpl pcrel:16 bsr pcrel:8 11187 bmi pcrel:8 bsr pcrel:16 11188 * bmi pcrel:16 bst #imm,rd 11189 bge pcrel:8 bst #imm,@rd 11190 * bge pcrel:16 bst #imm,@abs:8 11191 blt pcrel:8 btst #imm,rd 11192 * blt pcrel:16 btst #imm,@rd 11193 bgt pcrel:8 btst #imm,@abs:8 11194 * bgt pcrel:16 btst rs,rd 11195 ble pcrel:8 btst rs,@rd 11196 * ble pcrel:16 btst rs,@abs:8 11197 bclr #imm,rd bxor #imm,rd 11198 bclr #imm,@rd bxor #imm,@rd 11199 bclr #imm,@abs:8 bxor #imm,@abs:8 11200 bclr rs,rd cmp.b #imm,rd 11201 bclr rs,@rd cmp.b rs,rd 11202 bclr rs,@abs:8 cmp.w rs,rd 11203 biand #imm,rd cmp.w rs,rd 11204 biand #imm,@rd * cmp.w #imm,rd 11205 biand #imm,@abs:8 * cmp.l #imm,rd 11206 bild #imm,rd * cmp.l rs,rd 11207 bild #imm,@rd daa rs 11208 bild #imm,@abs:8 das rs 11209 bior #imm,rd dec.b rs 11210 bior #imm,@rd * dec.w #imm,rd 11211 bior #imm,@abs:8 * dec.l #imm,rd 11212 bist #imm,rd divxu.b rs,rd 11213 bist #imm,@rd * divxu.w rs,rd 11214 bist #imm,@abs:8 * divxs.b rs,rd 11215 bixor #imm,rd * divxs.w rs,rd 11216 bixor #imm,@rd eepmov 11217 bixor #imm,@abs:8 * eepmovw 11218 * exts.w rd mov.w rs,@abs:16 11219 * exts.l rd * mov.l #imm,rd 11220 * extu.w rd * mov.l rs,rd 11221 * extu.l rd * mov.l @rs,rd 11222 inc rs * mov.l @(disp:16,rs),rd 11223 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 11224 * inc.l #imm,rd * mov.l @rs+,rd 11225 jmp @rs * mov.l @abs:16,rd 11226 jmp abs * mov.l @abs:24,rd 11227 jmp @@abs:8 * mov.l rs,@rd 11228 jsr @rs * mov.l rs,@(disp:16,rd) 11229 jsr abs * mov.l rs,@(disp:24,rd) 11230 jsr @@abs:8 * mov.l rs,@-rd 11231 ldc #imm,ccr * mov.l rs,@abs:16 11232 ldc rs,ccr * mov.l rs,@abs:24 11233 * ldc @abs:16,ccr movfpe @abs:16,rd 11234 * ldc @abs:24,ccr movtpe rs,@abs:16 11235 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 11236 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 11237 * ldc @rs+,ccr * mulxs.b rs,rd 11238 * ldc @rs,ccr * mulxs.w rs,rd 11239 * mov.b @(disp:24,rs),rd neg.b rs 11240 * mov.b rs,@(disp:24,rd) * neg.w rs 11241 mov.b @abs:16,rd * neg.l rs 11242 mov.b rs,rd nop 11243 mov.b @abs:8,rd not.b rs 11244 mov.b rs,@abs:8 * not.w rs 11245 mov.b rs,rd * not.l rs 11246 mov.b #imm,rd or.b #imm,rd 11247 mov.b @rs,rd or.b rs,rd 11248 mov.b @(disp:16,rs),rd * or.w #imm,rd 11249 mov.b @rs+,rd * or.w rs,rd 11250 mov.b @abs:8,rd * or.l #imm,rd 11251 mov.b rs,@rd * or.l rs,rd 11252 mov.b rs,@(disp:16,rd) orc #imm,ccr 11253 mov.b rs,@-rd pop.w rs 11254 mov.b rs,@abs:8 * pop.l rs 11255 mov.w rs,@rd push.w rs 11256 * mov.w @(disp:24,rs),rd * push.l rs 11257 * mov.w rs,@(disp:24,rd) rotl.b rs 11258 * mov.w @abs:24,rd * rotl.w rs 11259 * mov.w rs,@abs:24 * rotl.l rs 11260 mov.w rs,rd rotr.b rs 11261 mov.w #imm,rd * rotr.w rs 11262 mov.w @rs,rd * rotr.l rs 11263 mov.w @(disp:16,rs),rd rotxl.b rs 11264 mov.w @rs+,rd * rotxl.w rs 11265 mov.w @abs:16,rd * rotxl.l rs 11266 mov.w rs,@(disp:16,rd) rotxr.b rs 11267 mov.w rs,@-rd * rotxr.w rs 11268 * rotxr.l rs * stc ccr,@(disp:24,rd) 11269 bpt * stc ccr,@-rd 11270 rte * stc ccr,@abs:16 11271 rts * stc ccr,@abs:24 11272 shal.b rs sub.b rs,rd 11273 * shal.w rs sub.w rs,rd 11274 * shal.l rs * sub.w #imm,rd 11275 shar.b rs * sub.l rs,rd 11276 * shar.w rs * sub.l #imm,rd 11277 * shar.l rs subs #imm,rd 11278 shll.b rs subx #imm,rd 11279 * shll.w rs subx rs,rd 11280 * shll.l rs * trapa #imm 11281 shlr.b rs xor #imm,rd 11282 * shlr.w rs xor rs,rd 11283 * shlr.l rs * xor.w #imm,rd 11284 sleep * xor.w rs,rd 11285 stc ccr,rd * xor.l #imm,rd 11286 * stc ccr,@rs * xor.l rs,rd 11287 * stc ccr,@(disp:16,rd) xorc #imm,ccr 11288 11289 Four H8/300 instructions ('add', 'cmp', 'mov', 'sub') are defined 11290with variants using the suffixes '.b', '.w', and '.l' to specify the 11291size of a memory operand. 'as' supports these suffixes, but does not 11292require them; since one of the operands is always a register, 'as' can 11293deduce the correct size. 11294 11295 For example, since 'r0' refers to a 16-bit register, 11296 mov r0,@foo 11297is equivalent to 11298 mov.w r0,@foo 11299 11300 If you use the size suffixes, 'as' issues a warning when the suffix 11301and the register size do not match. 11302 11303 11304File: as.info, Node: HPPA-Dependent, Next: i386-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 11305 113069.15 HPPA Dependent Features 11307============================ 11308 11309* Menu: 11310 11311* HPPA Notes:: Notes 11312* HPPA Options:: Options 11313* HPPA Syntax:: Syntax 11314* HPPA Floating Point:: Floating Point 11315* HPPA Directives:: HPPA Machine Directives 11316* HPPA Opcodes:: Opcodes 11317 11318 11319File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 11320 113219.15.1 Notes 11322------------ 11323 11324As a back end for GNU CC 'as' has been thoroughly tested and should work 11325extremely well. We have tested it only minimally on hand written 11326assembly code and no one has tested it much on the assembly output from 11327the HP compilers. 11328 11329 The format of the debugging sections has changed since the original 11330'as' port (version 1.3X) was released; therefore, you must rebuild all 11331HPPA objects and libraries with the new assembler so that you can debug 11332the final executable. 11333 11334 The HPPA 'as' port generates a small subset of the relocations 11335available in the SOM and ELF object file formats. Additional relocation 11336support will be added as it becomes necessary. 11337 11338 11339File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 11340 113419.15.2 Options 11342-------------- 11343 11344'as' has no machine-dependent command-line options for the HPPA. 11345 11346 11347File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 11348 113499.15.3 Syntax 11350------------- 11351 11352The assembler syntax closely follows the HPPA instruction set reference 11353manual; assembler directives and general syntax closely follow the HPPA 11354assembly language reference manual, with a few noteworthy differences. 11355 11356 First, a colon may immediately follow a label definition. This is 11357simply for compatibility with how most assembly language programmers 11358write code. 11359 11360 Some obscure expression parsing problems may affect hand written code 11361which uses the 'spop' instructions, or code which makes significant use 11362of the '!' line separator. 11363 11364 'as' is much less forgiving about missing arguments and other similar 11365oversights than the HP assembler. 'as' notifies you of missing 11366arguments as syntax errors; this is regarded as a feature, not a bug. 11367 11368 Finally, 'as' allows you to use an external symbol without explicitly 11369importing the symbol. _Warning:_ in the future this will be an error 11370for HPPA targets. 11371 11372 Special characters for HPPA targets include: 11373 11374 ';' is the line comment character. 11375 11376 '!' can be used instead of a newline to separate statements. 11377 11378 Since '$' has no special meaning, you may use it in symbol names. 11379 11380 11381File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 11382 113839.15.4 Floating Point 11384--------------------- 11385 11386The HPPA family uses IEEE floating-point numbers. 11387 11388 11389File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 11390 113919.15.5 HPPA Assembler Directives 11392-------------------------------- 11393 11394'as' for the HPPA supports many additional directives for compatibility 11395with the native assembler. This section describes them only briefly. 11396For detailed information on HPPA-specific assembler directives, see 11397'HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). 11398 11399 'as' does _not_ support the following assembler directives described 11400in the HP manual: 11401 11402 .endm .liston 11403 .enter .locct 11404 .leave .macro 11405 .listoff 11406 11407 Beyond those implemented for compatibility, 'as' supports one 11408additional assembler directive for the HPPA: '.param'. It conveys 11409register argument locations for static functions. Its syntax closely 11410follows the '.export' directive. 11411 11412 These are the additional directives in 'as' for the HPPA: 11413 11414'.block N' 11415'.blockz N' 11416 Reserve N bytes of storage, and initialize them to zero. 11417 11418'.call' 11419 Mark the beginning of a procedure call. Only the special case with 11420 _no arguments_ is allowed. 11421 11422'.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' 11423 Specify a number of parameters and flags that define the 11424 environment for a procedure. 11425 11426 PARAM may be any of 'frame' (frame size), 'entry_gr' (end of 11427 general register range), 'entry_fr' (end of float register range), 11428 'entry_sr' (end of space register range). 11429 11430 The values for FLAG are 'calls' or 'caller' (proc has subroutines), 11431 'no_calls' (proc does not call subroutines), 'save_rp' (preserve 11432 return pointer), 'save_sp' (proc preserves stack pointer), 11433 'no_unwind' (do not unwind this proc), 'hpux_int' (proc is 11434 interrupt routine). 11435 11436'.code' 11437 Assemble into the standard section called '$TEXT$', subsection 11438 '$CODE$'. 11439 11440'.copyright "STRING"' 11441 In the SOM object format, insert STRING into the object code, 11442 marked as a copyright string. 11443 11444'.copyright "STRING"' 11445 In the ELF object format, insert STRING into the object code, 11446 marked as a version string. 11447 11448'.enter' 11449 Not yet supported; the assembler rejects programs containing this 11450 directive. 11451 11452'.entry' 11453 Mark the beginning of a procedure. 11454 11455'.exit' 11456 Mark the end of a procedure. 11457 11458'.export NAME [ ,TYP ] [ ,PARAM=R ]' 11459 Make a procedure NAME available to callers. TYP, if present, must 11460 be one of 'absolute', 'code' (ELF only, not SOM), 'data', 'entry', 11461 'data', 'entry', 'millicode', 'plabel', 'pri_prog', or 'sec_prog'. 11462 11463 PARAM, if present, provides either relocation information for the 11464 procedure arguments and result, or a privilege level. PARAM may be 11465 'argwN' (where N ranges from '0' to '3', and indicates one of four 11466 one-word arguments); 'rtnval' (the procedure's result); or 11467 'priv_lev' (privilege level). For arguments or the result, R 11468 specifies how to relocate, and must be one of 'no' (not 11469 relocatable), 'gr' (argument is in general register), 'fr' (in 11470 floating point register), or 'fu' (upper half of float register). 11471 For 'priv_lev', R is an integer. 11472 11473'.half N' 11474 Define a two-byte integer constant N; synonym for the portable 'as' 11475 directive '.short'. 11476 11477'.import NAME [ ,TYP ]' 11478 Converse of '.export'; make a procedure available to call. The 11479 arguments use the same conventions as the first two arguments for 11480 '.export'. 11481 11482'.label NAME' 11483 Define NAME as a label for the current assembly location. 11484 11485'.leave' 11486 Not yet supported; the assembler rejects programs containing this 11487 directive. 11488 11489'.origin LC' 11490 Advance location counter to LC. Synonym for the 'as' portable 11491 directive '.org'. 11492 11493'.param NAME [ ,TYP ] [ ,PARAM=R ]' 11494 Similar to '.export', but used for static procedures. 11495 11496'.proc' 11497 Use preceding the first statement of a procedure. 11498 11499'.procend' 11500 Use following the last statement of a procedure. 11501 11502'LABEL .reg EXPR' 11503 Synonym for '.equ'; define LABEL with the absolute expression EXPR 11504 as its value. 11505 11506'.space SECNAME [ ,PARAMS ]' 11507 Switch to section SECNAME, creating a new section by that name if 11508 necessary. You may only use PARAMS when creating a new section, 11509 not when switching to an existing one. SECNAME may identify a 11510 section by number rather than by name. 11511 11512 If specified, the list PARAMS declares attributes of the section, 11513 identified by keywords. The keywords recognized are 'spnum=EXP' 11514 (identify this section by the number EXP, an absolute expression), 11515 'sort=EXP' (order sections according to this sort key when linking; 11516 EXP is an absolute expression), 'unloadable' (section contains no 11517 loadable data), 'notdefined' (this section defined elsewhere), and 11518 'private' (data in this section not available to other programs). 11519 11520'.spnum SECNAM' 11521 Allocate four bytes of storage, and initialize them with the 11522 section number of the section named SECNAM. (You can define the 11523 section number with the HPPA '.space' directive.) 11524 11525'.string "STR"' 11526 Copy the characters in the string STR to the object file. *Note 11527 Strings: Strings, for information on escape sequences you can use 11528 in 'as' strings. 11529 11530 _Warning!_ The HPPA version of '.string' differs from the usual 11531 'as' definition: it does _not_ write a zero byte after copying STR. 11532 11533'.stringz "STR"' 11534 Like '.string', but appends a zero byte after copying STR to object 11535 file. 11536 11537'.subspa NAME [ ,PARAMS ]' 11538'.nsubspa NAME [ ,PARAMS ]' 11539 Similar to '.space', but selects a subsection NAME within the 11540 current section. You may only specify PARAMS when you create a 11541 subsection (in the first instance of '.subspa' for this NAME). 11542 11543 If specified, the list PARAMS declares attributes of the 11544 subsection, identified by keywords. The keywords recognized are 11545 'quad=EXPR' ("quadrant" for this subsection), 'align=EXPR' 11546 (alignment for beginning of this subsection; a power of two), 11547 'access=EXPR' (value for "access rights" field), 'sort=EXPR' 11548 (sorting order for this subspace in link), 'code_only' (subsection 11549 contains only code), 'unloadable' (subsection cannot be loaded into 11550 memory), 'comdat' (subsection is comdat), 'common' (subsection is 11551 common block), 'dup_comm' (subsection may have duplicate names), or 11552 'zero' (subsection is all zeros, do not write in object file). 11553 11554 '.nsubspa' always creates a new subspace with the given name, even 11555 if one with the same name already exists. 11556 11557 'comdat', 'common' and 'dup_comm' can be used to implement various 11558 flavors of one-only support when using the SOM linker. The SOM 11559 linker only supports specific combinations of these flags. The 11560 details are not documented. A brief description is provided here. 11561 11562 'comdat' provides a form of linkonce support. It is useful for 11563 both code and data subspaces. A 'comdat' subspace has a key symbol 11564 marked by the 'is_comdat' flag or 'ST_COMDAT'. Only the first 11565 subspace for any given key is selected. The key symbol becomes 11566 universal in shared links. This is similar to the behavior of 11567 'secondary_def' symbols. 11568 11569 'common' provides Fortran named common support. It is only useful 11570 for data subspaces. Symbols with the flag 'is_common' retain this 11571 flag in shared links. Referencing a 'is_common' symbol in a shared 11572 library from outside the library doesn't work. Thus, 'is_common' 11573 symbols must be output whenever they are needed. 11574 11575 'common' and 'dup_comm' together provide Cobol common support. The 11576 subspaces in this case must all be the same length. Otherwise, 11577 this support is similar to the Fortran common support. 11578 11579 'dup_comm' by itself provides a type of one-only support for code. 11580 Only the first 'dup_comm' subspace is selected. There is a rather 11581 complex algorithm to compare subspaces. Code symbols marked with 11582 the 'dup_common' flag are hidden. This support was intended for 11583 "C++ duplicate inlines". 11584 11585 A simplified technique is used to mark the flags of symbols based 11586 on the flags of their subspace. A symbol with the scope 11587 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 11588 the corresponding settings of 'comdat', 'common' and 'dup_comm' 11589 from the subspace, respectively. This avoids having to introduce 11590 additional directives to mark these symbols. The HP assembler sets 11591 'is_common' from 'common'. However, it doesn't set the 11592 'dup_common' from 'dup_comm'. It doesn't have 'comdat' support. 11593 11594'.version "STR"' 11595 Write STR as version identifier in object code. 11596 11597 11598File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 11599 116009.15.6 Opcodes 11601-------------- 11602 11603For detailed information on the HPPA machine instruction set, see 11604'PA-RISC Architecture and Instruction Set Reference Manual' (HP 1160509740-90039). 11606 11607 11608File: as.info, Node: i386-Dependent, Next: IA-64-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 11609 116109.16 80386 Dependent Features 11611============================= 11612 11613The i386 version 'as' supports both the original Intel 386 architecture 11614in both 16 and 32-bit mode as well as AMD x86-64 architecture extending 11615the Intel architecture to 64-bits. 11616 11617* Menu: 11618 11619* i386-Options:: Options 11620* i386-Directives:: X86 specific directives 11621* i386-Syntax:: Syntactical considerations 11622* i386-Mnemonics:: Instruction Naming 11623* i386-Regs:: Register Naming 11624* i386-Prefixes:: Instruction Prefixes 11625* i386-Memory:: Memory References 11626* i386-Jumps:: Handling of Jump Instructions 11627* i386-Float:: Floating Point 11628* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 11629* i386-LWP:: AMD's Lightweight Profiling Instructions 11630* i386-BMI:: Bit Manipulation Instruction 11631* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 11632* i386-16bit:: Writing 16-bit Code 11633* i386-Arch:: Specifying an x86 CPU architecture 11634* i386-Bugs:: AT&T Syntax bugs 11635* i386-Notes:: Notes 11636 11637 11638File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 11639 116409.16.1 Options 11641-------------- 11642 11643The i386 version of 'as' has a few machine dependent options: 11644 11645'--32 | --x32 | --64' 11646 Select the word size, either 32 bits or 64 bits. '--32' implies 11647 Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64 11648 architecture with 32-bit or 64-bit word-size respectively. 11649 11650 These options are only available with the ELF object file format, 11651 and require that the necessary BFD support has been included (on a 11652 32-bit platform you have to add -enable-64-bit-bfd to configure 11653 enable 64-bit usage and use x86-64 as target platform). 11654 11655'-n' 11656 By default, x86 GAS replaces multiple nop instructions used for 11657 alignment within code sections with multi-byte nop instructions 11658 such as leal 0(%esi,1),%esi. This switch disables the optimization 11659 if a single byte nop (0x90) is explicitly specified as the fill 11660 byte for alignment. 11661 11662'--divide' 11663 On SVR4-derived platforms, the character '/' is treated as a 11664 comment character, which means that it cannot be used in 11665 expressions. The '--divide' option turns '/' into a normal 11666 character. This does not disable '/' at the beginning of a line 11667 starting a comment, or affect using '#' for starting a comment. 11668 11669'-march=CPU[+EXTENSION...]' 11670 This option specifies the target processor. The assembler will 11671 issue an error message if an attempt is made to assemble an 11672 instruction which will not execute on the target processor. The 11673 following processor names are recognized: 'i8086', 'i186', 'i286', 11674 'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro', 11675 'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona', 11676 'core', 'core2', 'corei7', 'l1om', 'k1om', 'iamcu', 'k6', 'k6_2', 11677 'athlon', 'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2', 11678 'bdver3', 'bdver4', 'znver1', 'znver2', 'btver1', 'btver2', 11679 'generic32' and 'generic64'. 11680 11681 In addition to the basic instruction set, the assembler can be told 11682 to accept various extension mnemonics. For example, 11683 '-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The 11684 following extensions are currently supported: '8087', '287', '387', 11685 '687', 'no87', 'no287', 'no387', 'no687', 'cmov', 'nocmov', 'fxsr', 11686 'nofxsr', 'mmx', 'nommx', 'sse', 'sse2', 'sse3', 'ssse3', 'sse4.1', 11687 'sse4.2', 'sse4', 'nosse', 'nosse2', 'nosse3', 'nossse3', 11688 'nosse4.1', 'nosse4.2', 'nosse4', 'avx', 'avx2', 'noavx', 'noavx2', 11689 'adx', 'rdseed', 'prfchw', 'smap', 'mpx', 'sha', 'rdpid', 11690 'ptwrite', 'cet', 'gfni', 'vaes', 'vpclmulqdq', 'prefetchwt1', 11691 'clflushopt', 'se1', 'clwb', 'movdiri', 'movdir64b', 'enqcmd', 11692 'avx512f', 'avx512cd', 'avx512er', 'avx512pf', 'avx512vl', 11693 'avx512bw', 'avx512dq', 'avx512ifma', 'avx512vbmi', 11694 'avx512_4fmaps', 'avx512_4vnniw', 'avx512_vpopcntdq', 11695 'avx512_vbmi2', 'avx512_vnni', 'avx512_bitalg', 'avx512_bf16', 11696 'noavx512f', 'noavx512cd', 'noavx512er', 'noavx512pf', 11697 'noavx512vl', 'noavx512bw', 'noavx512dq', 'noavx512ifma', 11698 'noavx512vbmi', 'noavx512_4fmaps', 'noavx512_4vnniw', 11699 'noavx512_vpopcntdq', 'noavx512_vbmi2', 'noavx512_vnni', 11700 'noavx512_bitalg', 'noavx512_vp2intersect', 'noavx512_bf16', 11701 'noenqcmd', 'vmx', 'vmfunc', 'smx', 'xsave', 'xsaveopt', 'xsavec', 11702 'xsaves', 'aes', 'pclmul', 'fsgsbase', 'rdrnd', 'f16c', 'bmi2', 11703 'fma', 'movbe', 'ept', 'lzcnt', 'hle', 'rtm', 'invpcid', 'clflush', 11704 'mwaitx', 'clzero', 'wbnoinvd', 'pconfig', 'waitpkg', 'cldemote', 11705 'rdpru', 'mcommit', 'lwp', 'fma4', 'xop', 'cx16', 'syscall', 11706 'rdtscp', '3dnow', '3dnowa', 'sse4a', 'sse5', 'svme', 'abm' and 11707 'padlock'. Note that rather than extending a basic instruction 11708 set, the extension mnemonics starting with 'no' revoke the 11709 respective functionality. 11710 11711 When the '.arch' directive is used with '-march', the '.arch' 11712 directive will take precedent. 11713 11714'-mtune=CPU' 11715 This option specifies a processor to optimize for. When used in 11716 conjunction with the '-march' option, only instructions of the 11717 processor specified by the '-march' option will be generated. 11718 11719 Valid CPU values are identical to the processor list of 11720 '-march=CPU'. 11721 11722'-msse2avx' 11723 This option specifies that the assembler should encode SSE 11724 instructions with VEX prefix. 11725 11726'-msse-check=NONE' 11727'-msse-check=WARNING' 11728'-msse-check=ERROR' 11729 These options control if the assembler should check SSE 11730 instructions. '-msse-check=NONE' will make the assembler not to 11731 check SSE instructions, which is the default. 11732 '-msse-check=WARNING' will make the assembler issue a warning for 11733 any SSE instruction. '-msse-check=ERROR' will make the assembler 11734 issue an error for any SSE instruction. 11735 11736'-mavxscalar=128' 11737'-mavxscalar=256' 11738 These options control how the assembler should encode scalar AVX 11739 instructions. '-mavxscalar=128' will encode scalar AVX 11740 instructions with 128bit vector length, which is the default. 11741 '-mavxscalar=256' will encode scalar AVX instructions with 256bit 11742 vector length. 11743 11744 WARNING: Don't use this for production code - due to CPU errata the 11745 resulting code may not work on certain models. 11746 11747'-mvexwig=0' 11748'-mvexwig=1' 11749 These options control how the assembler should encode VEX.W-ignored 11750 (WIG) VEX instructions. '-mvexwig=0' will encode WIG VEX 11751 instructions with vex.w = 0, which is the default. '-mvexwig=1' 11752 will encode WIG EVEX instructions with vex.w = 1. 11753 11754 WARNING: Don't use this for production code - due to CPU errata the 11755 resulting code may not work on certain models. 11756 11757'-mevexlig=128' 11758'-mevexlig=256' 11759'-mevexlig=512' 11760 These options control how the assembler should encode 11761 length-ignored (LIG) EVEX instructions. '-mevexlig=128' will 11762 encode LIG EVEX instructions with 128bit vector length, which is 11763 the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG 11764 EVEX instructions with 256bit and 512bit vector length, 11765 respectively. 11766 11767'-mevexwig=0' 11768'-mevexwig=1' 11769 These options control how the assembler should encode w-ignored 11770 (WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX 11771 instructions with evex.w = 0, which is the default. '-mevexwig=1' 11772 will encode WIG EVEX instructions with evex.w = 1. 11773 11774'-mmnemonic=ATT' 11775'-mmnemonic=INTEL' 11776 This option specifies instruction mnemonic for matching 11777 instructions. The '.att_mnemonic' and '.intel_mnemonic' directives 11778 will take precedent. 11779 11780'-msyntax=ATT' 11781'-msyntax=INTEL' 11782 This option specifies instruction syntax when processing 11783 instructions. The '.att_syntax' and '.intel_syntax' directives 11784 will take precedent. 11785 11786'-mnaked-reg' 11787 This option specifies that registers don't require a '%' prefix. 11788 The '.att_syntax' and '.intel_syntax' directives will take 11789 precedent. 11790 11791'-madd-bnd-prefix' 11792 This option forces the assembler to add BND prefix to all branches, 11793 even if such prefix was not explicitly specified in the source 11794 code. 11795 11796'-mno-shared' 11797 On ELF target, the assembler normally optimizes out non-PLT 11798 relocations against defined non-weak global branch targets with 11799 default visibility. The '-mshared' option tells the assembler to 11800 generate code which may go into a shared library where all non-weak 11801 global branch targets with default visibility can be preempted. 11802 The resulting code is slightly bigger. This option only affects 11803 the handling of branch instructions. 11804 11805'-mbig-obj' 11806 On x86-64 PE/COFF target this option forces the use of big object 11807 file format, which allows more than 32768 sections. 11808 11809'-momit-lock-prefix=NO' 11810'-momit-lock-prefix=YES' 11811 These options control how the assembler should encode lock prefix. 11812 This option is intended as a workaround for processors, that fail 11813 on lock prefix. This option can only be safely used with 11814 single-core, single-thread computers '-momit-lock-prefix=YES' will 11815 omit all lock prefixes. '-momit-lock-prefix=NO' will encode lock 11816 prefix as usual, which is the default. 11817 11818'-mfence-as-lock-add=NO' 11819'-mfence-as-lock-add=YES' 11820 These options control how the assembler should encode lfence, 11821 mfence and sfence. '-mfence-as-lock-add=YES' will encode lfence, 11822 mfence and sfence as 'lock addl $0x0, (%rsp)' in 64-bit mode and 11823 'lock addl $0x0, (%esp)' in 32-bit mode. '-mfence-as-lock-add=NO' 11824 will encode lfence, mfence and sfence as usual, which is the 11825 default. 11826 11827'-mrelax-relocations=NO' 11828'-mrelax-relocations=YES' 11829 These options control whether the assembler should generate relax 11830 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX 11831 and R_X86_64_REX_GOTPCRELX, in 64-bit mode. 11832 '-mrelax-relocations=YES' will generate relax relocations. 11833 '-mrelax-relocations=NO' will not generate relax relocations. The 11834 default can be controlled by a configure option 11835 '--enable-x86-relax-relocations'. 11836 11837'-malign-branch-boundary=NUM' 11838 This option controls how the assembler should align branches with 11839 segment prefixes or NOP. NUM must be a power of 2. It should be 0 11840 or no less than 16. Branches will be aligned within NUM byte 11841 boundary. '-malign-branch-boundary=0', which is the default, 11842 doesn't align branches. 11843 11844'-malign-branch=TYPE[+TYPE...]' 11845 This option specifies types of branches to align. TYPE is 11846 combination of 'jcc', which aligns conditional jumps, 'fused', 11847 which aligns fused conditional jumps, 'jmp', which aligns 11848 unconditional jumps, 'call' which aligns calls, 'ret', which aligns 11849 rets, 'indirect', which aligns indirect jumps and calls. The 11850 default is '-malign-branch=jcc+fused+jmp'. 11851 11852'-malign-branch-prefix-size=NUM' 11853 This option specifies the maximum number of prefixes on an 11854 instruction to align branches. NUM should be between 0 and 5. The 11855 default NUM is 5. 11856 11857'-mbranches-within-32B-boundaries' 11858 This option aligns conditional jumps, fused conditional jumps and 11859 unconditional jumps within 32 byte boundary with up to 5 segment 11860 prefixes on an instruction. It is equivalent to 11861 '-malign-branch-boundary=32' '-malign-branch=jcc+fused+jmp' 11862 '-malign-branch-prefix-size=5'. The default doesn't align 11863 branches. 11864 11865'-mx86-used-note=NO' 11866'-mx86-used-note=YES' 11867 These options control whether the assembler should generate 11868 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU 11869 property notes. The default can be controlled by the 11870 '--enable-x86-used-note' configure option. 11871 11872'-mevexrcig=RNE' 11873'-mevexrcig=RD' 11874'-mevexrcig=RU' 11875'-mevexrcig=RZ' 11876 These options control how the assembler should encode SAE-only EVEX 11877 instructions. '-mevexrcig=RNE' will encode RC bits of EVEX 11878 instruction with 00, which is the default. '-mevexrcig=RD', 11879 '-mevexrcig=RU' and '-mevexrcig=RZ' will encode SAE-only EVEX 11880 instructions with 01, 10 and 11 RC bits, respectively. 11881 11882'-mamd64' 11883'-mintel64' 11884 This option specifies that the assembler should accept only AMD64 11885 or Intel64 ISA in 64-bit mode. The default is to accept both. 11886 11887'-O0 | -O | -O1 | -O2 | -Os' 11888 Optimize instruction encoding with smaller instruction size. '-O' 11889 and '-O1' encode 64-bit register load instructions with 64-bit 11890 immediate as 32-bit register load instructions with 31-bit or 11891 32-bits immediates, encode 64-bit register clearing instructions 11892 with 32-bit register clearing instructions, encode 256-bit/512-bit 11893 VEX/EVEX vector register clearing instructions with 128-bit VEX 11894 vector register clearing instructions, encode 128-bit/256-bit EVEX 11895 vector register load/store instructions with VEX vector register 11896 load/store instructions, and encode 128-bit/256-bit EVEX packed 11897 integer logical instructions with 128-bit/256-bit VEX packed 11898 integer logical. 11899 11900 '-O2' includes '-O1' optimization plus encodes 256-bit/512-bit EVEX 11901 vector register clearing instructions with 128-bit EVEX vector 11902 register clearing instructions. In 64-bit mode VEX encoded 11903 instructions with commutative source operands will also have their 11904 source operands swapped if this allows using the 2-byte VEX prefix 11905 form instead of the 3-byte one. Certain forms of AND as well as OR 11906 with the same (register) operand specified twice will also be 11907 changed to TEST. 11908 11909 '-Os' includes '-O2' optimization plus encodes 16-bit, 32-bit and 11910 64-bit register tests with immediate as 8-bit register test with 11911 immediate. '-O0' turns off this optimization. 11912 11913 11914File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 11915 119169.16.2 x86 specific Directives 11917------------------------------ 11918 11919'.lcomm SYMBOL , LENGTH[, ALIGNMENT]' 11920 Reserve LENGTH (an absolute expression) bytes for a local common 11921 denoted by SYMBOL. The section and value of SYMBOL are those of 11922 the new local common. The addresses are allocated in the bss 11923 section, so that at run-time the bytes start off zeroed. Since 11924 SYMBOL is not declared global, it is normally not visible to 'ld'. 11925 The optional third parameter, ALIGNMENT, specifies the desired 11926 alignment of the symbol in the bss section. 11927 11928 This directive is only available for COFF based x86 targets. 11929 11930'.largecomm SYMBOL , LENGTH[, ALIGNMENT]' 11931 This directive behaves in the same way as the 'comm' directive 11932 except that the data is placed into the .LBSS section instead of 11933 the .BSS section *note Comm::. 11934 11935 The directive is intended to be used for data which requires a 11936 large amount of space, and it is only available for ELF based 11937 x86_64 targets. 11938 11939'.value EXPRESSION [, EXPRESSION]' 11940 This directive behaves in the same way as the '.short' directive, 11941 taking a series of comma separated expressions and storing them as 11942 two-byte wide values into the current section. 11943 11944 11945File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 11946 119479.16.3 i386 Syntactical Considerations 11948-------------------------------------- 11949 11950* Menu: 11951 11952* i386-Variations:: AT&T Syntax versus Intel Syntax 11953* i386-Chars:: Special Characters 11954 11955 11956File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax 11957 119589.16.3.1 AT&T Syntax versus Intel Syntax 11959........................................ 11960 11961'as' now supports assembly using Intel assembler syntax. 11962'.intel_syntax' selects Intel mode, and '.att_syntax' switches back to 11963the usual AT&T mode for compatibility with the output of 'gcc'. Either 11964of these directives may have an optional argument, 'prefix', or 11965'noprefix' specifying whether registers require a '%' prefix. AT&T 11966System V/386 assembler syntax is quite different from Intel syntax. We 11967mention these differences because almost all 80386 documents use Intel 11968syntax. Notable differences between the two syntaxes are: 11969 11970 * AT&T immediate operands are preceded by '$'; Intel immediate 11971 operands are undelimited (Intel 'push 4' is AT&T 'pushl $4'). AT&T 11972 register operands are preceded by '%'; Intel register operands are 11973 undelimited. AT&T absolute (as opposed to PC relative) jump/call 11974 operands are prefixed by '*'; they are undelimited in Intel syntax. 11975 11976 * AT&T and Intel syntax use the opposite order for source and 11977 destination operands. Intel 'add eax, 4' is 'addl $4, %eax'. The 11978 'source, dest' convention is maintained for compatibility with 11979 previous Unix assemblers. Note that 'bound', 'invlpga', and 11980 instructions with 2 immediate operands, such as the 'enter' 11981 instruction, do _not_ have reversed order. *note i386-Bugs::. 11982 11983 * In AT&T syntax the size of memory operands is determined from the 11984 last character of the instruction mnemonic. Mnemonic suffixes of 11985 'b', 'w', 'l' and 'q' specify byte (8-bit), word (16-bit), long 11986 (32-bit) and quadruple word (64-bit) memory references. Mnemonic 11987 suffixes of 'x', 'y' and 'z' specify xmm (128-bit vector), ymm 11988 (256-bit vector) and zmm (512-bit vector) memory references, only 11989 when there's no other way to disambiguate an instruction. Intel 11990 syntax accomplishes this by prefixing memory operands (_not_ the 11991 instruction mnemonics) with 'byte ptr', 'word ptr', 'dword ptr', 11992 'qword ptr', 'xmmword ptr', 'ymmword ptr' and 'zmmword ptr'. Thus, 11993 Intel syntax 'mov al, byte ptr FOO' is 'movb FOO, %al' in AT&T 11994 syntax. In Intel syntax, 'fword ptr', 'tbyte ptr' and 'oword ptr' 11995 specify 48-bit, 80-bit and 128-bit memory references. 11996 11997 In 64-bit code, 'movabs' can be used to encode the 'mov' 11998 instruction with the 64-bit displacement or immediate operand. 11999 12000 * Immediate form long jumps and calls are 'lcall/ljmp $SECTION, 12001 $OFFSET' in AT&T syntax; the Intel syntax is 'call/jmp far 12002 SECTION:OFFSET'. Also, the far return instruction is 'lret 12003 $STACK-ADJUST' in AT&T syntax; Intel syntax is 'ret far 12004 STACK-ADJUST'. 12005 12006 * The AT&T assembler does not provide support for multiple section 12007 programs. Unix style systems expect all programs to be single 12008 sections. 12009 12010 12011File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax 12012 120139.16.3.2 Special Characters 12014........................... 12015 12016The presence of a '#' appearing anywhere on a line indicates the start 12017of a comment that extends to the end of that line. 12018 12019 If a '#' appears as the first character of a line then the whole line 12020is treated as a comment, but in this case the line can also be a logical 12021line number directive (*note Comments::) or a preprocessor control 12022command (*note Preprocessing::). 12023 12024 If the '--divide' command-line option has not been specified then the 12025'/' character appearing anywhere on a line also introduces a line 12026comment. 12027 12028 The ';' character can be used to separate statements on the same 12029line. 12030 12031 12032File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 12033 120349.16.4 i386-Mnemonics 12035--------------------- 12036 120379.16.4.1 Instruction Naming 12038........................... 12039 12040Instruction mnemonics are suffixed with one character modifiers which 12041specify the size of operands. The letters 'b', 'w', 'l' and 'q' specify 12042byte, word, long and quadruple word operands. If no suffix is specified 12043by an instruction then 'as' tries to fill in the missing suffix based on 12044the destination register operand (the last one by convention). Thus, 12045'mov %ax, %bx' is equivalent to 'movw %ax, %bx'; also, 'mov $1, %bx' is 12046equivalent to 'movw $1, bx'. Note that this is incompatible with the 12047AT&T Unix assembler which assumes that a missing mnemonic suffix implies 12048long operand size. (This incompatibility does not affect compiler 12049output since compilers always explicitly specify the mnemonic suffix.) 12050 12051 Almost all instructions have the same names in AT&T and Intel format. 12052There are a few exceptions. The sign extend and zero extend 12053instructions need two sizes to specify them. They need a size to 12054sign/zero extend _from_ and a size to zero extend _to_. This is 12055accomplished by using two instruction mnemonic suffixes in AT&T syntax. 12056Base names for sign extend and zero extend are 'movs...' and 'movz...' 12057in AT&T syntax ('movsx' and 'movzx' in Intel syntax). The instruction 12058mnemonic suffixes are tacked on to this base name, the _from_ suffix 12059before the _to_ suffix. Thus, 'movsbl %al, %edx' is AT&T syntax for 12060"move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are 12061'bl' (from byte to long), 'bw' (from byte to word), 'wl' (from word to 12062long), 'bq' (from byte to quadruple word), 'wq' (from word to quadruple 12063word), and 'lq' (from long to quadruple word). 12064 12065 Different encoding options can be specified via pseudo prefixes: 12066 12067 * '{disp8}' - prefer 8-bit displacement. 12068 12069 * '{disp32}' - prefer 32-bit displacement. 12070 12071 * '{load}' - prefer load-form instruction. 12072 12073 * '{store}' - prefer store-form instruction. 12074 12075 * '{vex}' - encode with VEX prefix. 12076 12077 * '{vex3}' - encode with 3-byte VEX prefix. 12078 12079 * '{evex}' - encode with EVEX prefix. 12080 12081 * '{rex}' - prefer REX prefix for integer and legacy vector 12082 instructions (x86-64 only). Note that this differs from the 'rex' 12083 prefix which generates REX prefix unconditionally. 12084 12085 * '{nooptimize}' - disable instruction size optimization. 12086 12087 The Intel-syntax conversion instructions 12088 12089 * 'cbw' -- sign-extend byte in '%al' to word in '%ax', 12090 12091 * 'cwde' -- sign-extend word in '%ax' to long in '%eax', 12092 12093 * 'cwd' -- sign-extend word in '%ax' to long in '%dx:%ax', 12094 12095 * 'cdq' -- sign-extend dword in '%eax' to quad in '%edx:%eax', 12096 12097 * 'cdqe' -- sign-extend dword in '%eax' to quad in '%rax' (x86-64 12098 only), 12099 12100 * 'cqo' -- sign-extend quad in '%rax' to octuple in '%rdx:%rax' 12101 (x86-64 only), 12102 12103are called 'cbtw', 'cwtl', 'cwtd', 'cltd', 'cltq', and 'cqto' in AT&T 12104naming. 'as' accepts either naming for these instructions. 12105 12106 Far call/jump instructions are 'lcall' and 'ljmp' in AT&T syntax, but 12107are 'call far' and 'jump far' in Intel convention. 12108 121099.16.4.2 AT&T Mnemonic versus Intel Mnemonic 12110............................................ 12111 12112'as' supports assembly using Intel mnemonic. '.intel_mnemonic' selects 12113Intel mnemonic with Intel syntax, and '.att_mnemonic' switches back to 12114the usual AT&T mnemonic with AT&T syntax for compatibility with the 12115output of 'gcc'. Several x87 instructions, 'fadd', 'fdiv', 'fdivp', 12116'fdivr', 'fdivrp', 'fmul', 'fsub', 'fsubp', 'fsubr' and 'fsubrp', are 12117implemented in AT&T System V/386 assembler with different mnemonics from 12118those in Intel IA32 specification. 'gcc' generates those instructions 12119with AT&T mnemonic. 12120 12121 12122File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 12123 121249.16.5 Register Naming 12125---------------------- 12126 12127Register operands are always prefixed with '%'. The 80386 registers 12128consist of 12129 12130 * the 8 32-bit registers '%eax' (the accumulator), '%ebx', '%ecx', 12131 '%edx', '%edi', '%esi', '%ebp' (the frame pointer), and '%esp' (the 12132 stack pointer). 12133 12134 * the 8 16-bit low-ends of these: '%ax', '%bx', '%cx', '%dx', '%di', 12135 '%si', '%bp', and '%sp'. 12136 12137 * the 8 8-bit registers: '%ah', '%al', '%bh', '%bl', '%ch', '%cl', 12138 '%dh', and '%dl' (These are the high-bytes and low-bytes of '%ax', 12139 '%bx', '%cx', and '%dx') 12140 12141 * the 6 section registers '%cs' (code section), '%ds' (data section), 12142 '%ss' (stack section), '%es', '%fs', and '%gs'. 12143 12144 * the 5 processor control registers '%cr0', '%cr2', '%cr3', '%cr4', 12145 and '%cr8'. 12146 12147 * the 6 debug registers '%db0', '%db1', '%db2', '%db3', '%db6', and 12148 '%db7'. 12149 12150 * the 2 test registers '%tr6' and '%tr7'. 12151 12152 * the 8 floating point register stack '%st' or equivalently '%st(0)', 12153 '%st(1)', '%st(2)', '%st(3)', '%st(4)', '%st(5)', '%st(6)', and 12154 '%st(7)'. These registers are overloaded by 8 MMX registers 12155 '%mm0', '%mm1', '%mm2', '%mm3', '%mm4', '%mm5', '%mm6' and '%mm7'. 12156 12157 * the 8 128-bit SSE registers registers '%xmm0', '%xmm1', '%xmm2', 12158 '%xmm3', '%xmm4', '%xmm5', '%xmm6' and '%xmm7'. 12159 12160 The AMD x86-64 architecture extends the register set by: 12161 12162 * enhancing the 8 32-bit registers to 64-bit: '%rax' (the 12163 accumulator), '%rbx', '%rcx', '%rdx', '%rdi', '%rsi', '%rbp' (the 12164 frame pointer), '%rsp' (the stack pointer) 12165 12166 * the 8 extended registers '%r8'-'%r15'. 12167 12168 * the 8 32-bit low ends of the extended registers: '%r8d'-'%r15d'. 12169 12170 * the 8 16-bit low ends of the extended registers: '%r8w'-'%r15w'. 12171 12172 * the 8 8-bit low ends of the extended registers: '%r8b'-'%r15b'. 12173 12174 * the 4 8-bit registers: '%sil', '%dil', '%bpl', '%spl'. 12175 12176 * the 8 debug registers: '%db8'-'%db15'. 12177 12178 * the 8 128-bit SSE registers: '%xmm8'-'%xmm15'. 12179 12180 With the AVX extensions more registers were made available: 12181 12182 * the 16 256-bit SSE '%ymm0'-'%ymm15' (only the first 8 available in 12183 32-bit mode). The bottom 128 bits are overlaid with the 12184 'xmm0'-'xmm15' registers. 12185 12186 The AVX2 extensions made in 64-bit mode more registers available: 12187 12188 * the 16 128-bit registers '%xmm16'-'%xmm31' and the 16 256-bit 12189 registers '%ymm16'-'%ymm31'. 12190 12191 The AVX512 extensions added the following registers: 12192 12193 * the 32 512-bit registers '%zmm0'-'%zmm31' (only the first 8 12194 available in 32-bit mode). The bottom 128 bits are overlaid with 12195 the '%xmm0'-'%xmm31' registers and the first 256 bits are overlaid 12196 with the '%ymm0'-'%ymm31' registers. 12197 12198 * the 8 mask registers '%k0'-'%k7'. 12199 12200 12201File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 12202 122039.16.6 Instruction Prefixes 12204--------------------------- 12205 12206Instruction prefixes are used to modify the following instruction. They 12207are used to repeat string instructions, to provide section overrides, to 12208perform bus lock operations, and to change operand and address sizes. 12209(Most instructions that normally operate on 32-bit operands will use 1221016-bit operands if the instruction has an "operand size" prefix.) 12211Instruction prefixes are best written on the same line as the 12212instruction they act upon. For example, the 'scas' (scan string) 12213instruction is repeated with: 12214 12215 repne scas %es:(%edi),%al 12216 12217 You may also place prefixes on the lines immediately preceding the 12218instruction, but this circumvents checks that 'as' does with prefixes, 12219and will not work with all prefixes. 12220 12221 Here is a list of instruction prefixes: 12222 12223 * Section override prefixes 'cs', 'ds', 'ss', 'es', 'fs', 'gs'. 12224 These are automatically added by specifying using the 12225 SECTION:MEMORY-OPERAND form for memory references. 12226 12227 * Operand/Address size prefixes 'data16' and 'addr16' change 32-bit 12228 operands/addresses into 16-bit operands/addresses, while 'data32' 12229 and 'addr32' change 16-bit ones (in a '.code16' section) into 12230 32-bit operands/addresses. These prefixes _must_ appear on the 12231 same line of code as the instruction they modify. For example, in 12232 a 16-bit '.code16' section, you might write: 12233 12234 addr32 jmpl *(%ebx) 12235 12236 * The bus lock prefix 'lock' inhibits interrupts during execution of 12237 the instruction it precedes. (This is only valid with certain 12238 instructions; see a 80386 manual for details). 12239 12240 * The wait for coprocessor prefix 'wait' waits for the coprocessor to 12241 complete the current instruction. This should never be needed for 12242 the 80386/80387 combination. 12243 12244 * The 'rep', 'repe', and 'repne' prefixes are added to string 12245 instructions to make them repeat '%ecx' times ('%cx' times if the 12246 current address size is 16-bits). 12247 * The 'rex' family of prefixes is used by x86-64 to encode extensions 12248 to i386 instruction set. The 'rex' prefix has four bits -- an 12249 operand size overwrite ('64') used to change operand size from 12250 32-bit to 64-bit and X, Y and Z extensions bits used to extend the 12251 register set. 12252 12253 You may write the 'rex' prefixes directly. The 'rex64xyz' 12254 instruction emits 'rex' prefix with all the bits set. By omitting 12255 the '64', 'x', 'y' or 'z' you may write other prefixes as well. 12256 Normally, there is no need to write the prefixes explicitly, since 12257 gas will automatically generate them based on the instruction 12258 operands. 12259 12260 12261File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 12262 122639.16.7 Memory References 12264------------------------ 12265 12266An Intel syntax indirect memory reference of the form 12267 12268 SECTION:[BASE + INDEX*SCALE + DISP] 12269 12270is translated into the AT&T syntax 12271 12272 SECTION:DISP(BASE, INDEX, SCALE) 12273 12274where BASE and INDEX are the optional 32-bit base and index registers, 12275DISP is the optional displacement, and SCALE, taking the values 1, 2, 4, 12276and 8, multiplies INDEX to calculate the address of the operand. If no 12277SCALE is specified, SCALE is taken to be 1. SECTION specifies the 12278optional section register for the memory operand, and may override the 12279default section register (see a 80386 manual for section register 12280defaults). Note that section overrides in AT&T syntax _must_ be 12281preceded by a '%'. If you specify a section override which coincides 12282with the default section register, 'as' does _not_ output any section 12283register override prefixes to assemble the given instruction. Thus, 12284section overrides can be specified to emphasize which section register 12285is used for a given memory operand. 12286 12287 Here are some examples of Intel and AT&T style memory references: 12288 12289AT&T: '-4(%ebp)', Intel: '[ebp - 4]' 12290 BASE is '%ebp'; DISP is '-4'. SECTION is missing, and the default 12291 section is used ('%ss' for addressing with '%ebp' as the base 12292 register). INDEX, SCALE are both missing. 12293 12294AT&T: 'foo(,%eax,4)', Intel: '[foo + eax*4]' 12295 INDEX is '%eax' (scaled by a SCALE 4); DISP is 'foo'. All other 12296 fields are missing. The section register here defaults to '%ds'. 12297 12298AT&T: 'foo(,1)'; Intel '[foo]' 12299 This uses the value pointed to by 'foo' as a memory operand. Note 12300 that BASE and INDEX are both missing, but there is only _one_ ','. 12301 This is a syntactic exception. 12302 12303AT&T: '%gs:foo'; Intel 'gs:foo' 12304 This selects the contents of the variable 'foo' with section 12305 register SECTION being '%gs'. 12306 12307 Absolute (as opposed to PC relative) call and jump operands must be 12308prefixed with '*'. If no '*' is specified, 'as' always chooses PC 12309relative addressing for jump/call labels. 12310 12311 Any instruction that has a memory operand, but no register operand, 12312_must_ specify its size (byte, word, long, or quadruple) with an 12313instruction mnemonic suffix ('b', 'w', 'l' or 'q', respectively). 12314 12315 The x86-64 architecture adds an RIP (instruction pointer relative) 12316addressing. This addressing mode is specified by using 'rip' as a base 12317register. Only constant offsets are valid. For example: 12318 12319AT&T: '1234(%rip)', Intel: '[rip + 1234]' 12320 Points to the address 1234 bytes past the end of the current 12321 instruction. 12322 12323AT&T: 'symbol(%rip)', Intel: '[rip + symbol]' 12324 Points to the 'symbol' in RIP relative way, this is shorter than 12325 the default absolute addressing. 12326 12327 Other addressing modes remain unchanged in x86-64 architecture, 12328except registers used are 64-bit instead of 32-bit. 12329 12330 12331File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 12332 123339.16.8 Handling of Jump Instructions 12334------------------------------------ 12335 12336Jump instructions are always optimized to use the smallest possible 12337displacements. This is accomplished by using byte (8-bit) displacement 12338jumps whenever the target is sufficiently close. If a byte displacement 12339is insufficient a long displacement is used. We do not support word 12340(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 12341instruction with the 'data16' instruction prefix), since the 80386 12342insists upon masking '%eip' to 16 bits after the word displacement is 12343added. (See also *note i386-Arch::) 12344 12345 Note that the 'jcxz', 'jecxz', 'loop', 'loopz', 'loope', 'loopnz' and 12346'loopne' instructions only come in byte displacements, so that if you 12347use these instructions ('gcc' does not use them) you may get an error 12348message (and incorrect code). The AT&T 80386 assembler tries to get 12349around this problem by expanding 'jcxz foo' to 12350 12351 jcxz cx_zero 12352 jmp cx_nonzero 12353 cx_zero: jmp foo 12354 cx_nonzero: 12355 12356 12357File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 12358 123599.16.9 Floating Point 12360--------------------- 12361 12362All 80387 floating point types except packed BCD are supported. (BCD 12363support may be added without much difficulty). These data types are 1236416-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 12365and extended (80-bit) precision floating point. Each supported type has 12366an instruction mnemonic suffix and a constructor associated with it. 12367Instruction mnemonic suffixes specify the operand's data type. 12368Constructors build these data types into memory. 12369 12370 * Floating point constructors are '.float' or '.single', '.double', 12371 and '.tfloat' for 32-, 64-, and 80-bit formats. These correspond 12372 to instruction mnemonic suffixes 's', 'l', and 't'. 't' stands for 12373 80-bit (ten byte) real. The 80387 only supports this format via 12374 the 'fldt' (load 80-bit real to stack top) and 'fstpt' (store 12375 80-bit real and pop stack) instructions. 12376 12377 * Integer constructors are '.word', '.long' or '.int', and '.quad' 12378 for the 16-, 32-, and 64-bit integer formats. The corresponding 12379 instruction mnemonic suffixes are 's' (single), 'l' (long), and 'q' 12380 (quad). As with the 80-bit real format, the 64-bit 'q' format is 12381 only present in the 'fildq' (load quad integer to stack top) and 12382 'fistpq' (store quad integer and pop stack) instructions. 12383 12384 Register to register operations should not use instruction mnemonic 12385suffixes. 'fstl %st, %st(1)' will give a warning, and be assembled as 12386if you wrote 'fst %st, %st(1)', since all register to register 12387operations use 80-bit floating point operands. (Contrast this with 12388'fstl %st, mem', which converts '%st' from 80-bit to 64-bit floating 12389point format, then stores the result in the 4 byte location 'mem') 12390 12391 12392File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 12393 123949.16.10 Intel's MMX and AMD's 3DNow! SIMD Operations 12395---------------------------------------------------- 12396 12397'as' supports Intel's MMX instruction set (SIMD instructions for integer 12398data), available on Intel's Pentium MMX processors and Pentium II 12399processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 12400probably others. It also supports AMD's 3DNow! instruction set (SIMD 12401instructions for 32-bit floating point data) available on AMD's K6-2 12402processor and possibly others in the future. 12403 12404 Currently, 'as' does not support Intel's floating point SIMD, Katmai 12405(KNI). 12406 12407 The eight 64-bit MMX operands, also used by 3DNow!, are called 12408'%mm0', '%mm1', ... '%mm7'. They contain eight 8-bit integers, four 1240916-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 12410floating point values. The MMX registers cannot be used at the same 12411time as the floating point stack. 12412 12413 See Intel and AMD documentation, keeping in mind that the operand 12414order in instructions is reversed from the Intel syntax. 12415 12416 12417File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent 12418 124199.16.11 AMD's Lightweight Profiling Instructions 12420------------------------------------------------ 12421 12422'as' supports AMD's Lightweight Profiling (LWP) instruction set, 12423available on AMD's Family 15h (Orochi) processors. 12424 12425 LWP enables applications to collect and manage performance data, and 12426react to performance events. The collection of performance data 12427requires no context switches. LWP runs in the context of a thread and 12428so several counters can be used independently across multiple threads. 12429LWP can be used in both 64-bit and legacy 32-bit modes. 12430 12431 For detailed information on the LWP instruction set, see the 'AMD 12432Lightweight Profiling Specification' available at Lightweight Profiling 12433Specification (http://developer.amd.com/cpu/LWP). 12434 12435 12436File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent 12437 124389.16.12 Bit Manipulation Instructions 12439------------------------------------- 12440 12441'as' supports the Bit Manipulation (BMI) instruction set. 12442 12443 BMI instructions provide several instructions implementing individual 12444bit manipulation operations such as isolation, masking, setting, or 12445resetting. 12446 12447 12448File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent 12449 124509.16.13 AMD's Trailing Bit Manipulation Instructions 12451---------------------------------------------------- 12452 12453'as' supports AMD's Trailing Bit Manipulation (TBM) instruction set, 12454available on AMD's BDVER2 processors (Trinity and Viperfish). 12455 12456 TBM instructions provide instructions implementing individual bit 12457manipulation operations such as isolating, masking, setting, resetting, 12458complementing, and operations on trailing zeros and ones. 12459 12460 12461File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent 12462 124639.16.14 Writing 16-bit Code 12464--------------------------- 12465 12466While 'as' normally writes only "pure" 32-bit i386 code or 64-bit x86-64 12467code depending on the default configuration, it also supports writing 12468code to run in real mode or in 16-bit protected mode code segments. To 12469do this, put a '.code16' or '.code16gcc' directive before the assembly 12470language instructions to be run in 16-bit mode. You can switch 'as' to 12471writing 32-bit code with the '.code32' directive or 64-bit code with the 12472'.code64' directive. 12473 12474 '.code16gcc' provides experimental support for generating 16-bit code 12475from gcc, and differs from '.code16' in that 'call', 'ret', 'enter', 12476'leave', 'push', 'pop', 'pusha', 'popa', 'pushf', and 'popf' 12477instructions default to 32-bit size. This is so that the stack pointer 12478is manipulated in the same way over function calls, allowing access to 12479function parameters at the same stack offsets as in 32-bit mode. 12480'.code16gcc' also automatically adds address size prefixes where 12481necessary to use the 32-bit addressing modes that gcc generates. 12482 12483 The code which 'as' generates in 16-bit mode will not necessarily run 12484on a 16-bit pre-80386 processor. To write code that runs on such a 12485processor, you must refrain from using _any_ 32-bit constructs which 12486require 'as' to output address or operand size prefixes. 12487 12488 Note that writing 16-bit code instructions by explicitly specifying a 12489prefix or an instruction mnemonic suffix within a 32-bit code section 12490generates different machine instructions than those generated for a 1249116-bit code segment. In a 32-bit code section, the following code 12492generates the machine opcode bytes '66 6a 04', which pushes the value 12493'4' onto the stack, decrementing '%esp' by 2. 12494 12495 pushw $4 12496 12497 The same code in a 16-bit code section would generate the machine 12498opcode bytes '6a 04' (i.e., without the operand size prefix), which is 12499correct since the processor default operand size is assumed to be 16 12500bits in a 16-bit code section. 12501 12502 12503File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent 12504 125059.16.15 Specifying CPU Architecture 12506----------------------------------- 12507 12508'as' may be told to assemble for a particular CPU (sub-)architecture 12509with the '.arch CPU_TYPE' directive. This directive enables a warning 12510when gas detects an instruction that is not supported on the CPU 12511specified. The choices for CPU_TYPE are: 12512 12513'i8086' 'i186' 'i286' 'i386' 12514'i486' 'i586' 'i686' 'pentium' 12515'pentiumpro' 'pentiumii' 'pentiumiii' 'pentium4' 12516'prescott' 'nocona' 'core' 'core2' 12517'corei7' 'l1om' 'k1om' 'iamcu' 12518'k6' 'k6_2' 'athlon' 'k8' 12519'amdfam10' 'bdver1' 'bdver2' 'bdver3' 12520'bdver4' 'znver1' 'znver2' 'btver1' 12521'btver2' 'generic32' 'generic64' 12522'.cmov' '.fxsr' '.mmx' 12523'.sse' '.sse2' '.sse3' 12524'.ssse3' '.sse4.1' '.sse4.2' '.sse4' 12525'.avx' '.vmx' '.smx' '.ept' 12526'.clflush' '.movbe' '.xsave' '.xsaveopt' 12527'.aes' '.pclmul' '.fma' '.fsgsbase' 12528'.rdrnd' '.f16c' '.avx2' '.bmi2' 12529'.lzcnt' '.invpcid' '.vmfunc' '.hle' 12530'.rtm' '.adx' '.rdseed' '.prfchw' 12531'.smap' '.mpx' '.sha' '.prefetchwt1' 12532'.clflushopt' '.xsavec' '.xsaves' '.se1' 12533'.avx512f' '.avx512cd' '.avx512er' '.avx512pf' 12534'.avx512vl' '.avx512bw' '.avx512dq' '.avx512ifma' 12535'.avx512vbmi' '.avx512_4fmaps''.avx512_4vnniw' 12536'.avx512_vpopcntdq''.avx512_vbmi2''.avx512_vnni' 12537'.avx512_bitalg''.avx512_bf16''.avx512_vp2intersect' 12538'.clwb' '.rdpid' '.ptwrite' 12539'.ibt' 12540'.wbnoinvd' '.pconfig' '.waitpkg' '.cldemote' 12541'.shstk' '.gfni' '.vaes' '.vpclmulqdq' 12542'.movdiri' '.movdir64b' '.enqcmd' 12543'.3dnow' '.3dnowa' '.sse4a' '.sse5' 12544'.syscall' '.rdtscp' '.svme' '.abm' 12545'.lwp' '.fma4' '.xop' '.cx16' 12546'.padlock' '.clzero' '.mwaitx' '.rdpru' 12547'.mcommit' 12548 12549 Apart from the warning, there are only two other effects on 'as' 12550operation; Firstly, if you specify a CPU other than 'i486', then shift 12551by one instructions such as 'sarl $1, %eax' will automatically use a two 12552byte opcode sequence. The larger three byte opcode sequence is used on 12553the 486 (and when no architecture is specified) because it executes 12554faster on the 486. Note that you can explicitly request the two byte 12555opcode by writing 'sarl %eax'. Secondly, if you specify 'i8086', 12556'i186', or 'i286', _and_ '.code16' or '.code16gcc' then byte offset 12557conditional jumps will be promoted when necessary to a two instruction 12558sequence consisting of a conditional jump of the opposite sense around 12559an unconditional jump to the target. 12560 12561 Following the CPU architecture (but not a sub-architecture, which are 12562those starting with a dot), you may specify 'jumps' or 'nojumps' to 12563control automatic promotion of conditional jumps. 'jumps' is the 12564default, and enables jump promotion; All external jumps will be of the 12565long variety, and file-local jumps will be promoted as necessary. 12566(*note i386-Jumps::) 'nojumps' leaves external conditional jumps as byte 12567offset jumps, and warns about file-local conditional jumps that 'as' 12568promotes. Unconditional jumps are treated as for 'jumps'. 12569 12570 For example 12571 12572 .arch i8086,nojumps 12573 12574 12575File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 12576 125779.16.16 AT&T Syntax bugs 12578------------------------ 12579 12580The UnixWare assembler, and probably other AT&T derived ix86 Unix 12581assemblers, generate floating point instructions with reversed source 12582and destination registers in certain cases. Unfortunately, gcc and 12583possibly many other programs use this reversed syntax, so we're stuck 12584with it. 12585 12586 For example 12587 12588 fsub %st,%st(3) 12589results in '%st(3)' being updated to '%st - %st(3)' rather than the 12590expected '%st(3) - %st'. This happens with all the non-commutative 12591arithmetic floating point operations with two register operands where 12592the source register is '%st' and the destination register is '%st(i)'. 12593 12594 12595File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 12596 125979.16.17 Notes 12598------------- 12599 12600There is some trickery concerning the 'mul' and 'imul' instructions that 12601deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies 12602(base opcode '0xf6'; extension 4 for 'mul' and 5 for 'imul') can be 12603output only in the one operand form. Thus, 'imul %ebx, %eax' does _not_ 12604select the expanding multiply; the expanding multiply would clobber the 12605'%edx' register, and this would confuse 'gcc' output. Use 'imul %ebx' 12606to get the 64-bit product in '%edx:%eax'. 12607 12608 We have added a two operand form of 'imul' when the first operand is 12609an immediate mode expression and the second operand is a register. This 12610is just a shorthand, so that, multiplying '%eax' by 69, for example, can 12611be done with 'imul $69, %eax' rather than 'imul $69, %eax, %eax'. 12612 12613 12614File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 12615 126169.17 IA-64 Dependent Features 12617============================= 12618 12619* Menu: 12620 12621* IA-64 Options:: Options 12622* IA-64 Syntax:: Syntax 12623* IA-64 Opcodes:: Opcodes 12624 12625 12626File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 12627 126289.17.1 Options 12629-------------- 12630 12631'-mconstant-gp' 12632 This option instructs the assembler to mark the resulting object 12633 file as using the "constant GP" model. With this model, it is 12634 assumed that the entire program uses a single global pointer (GP) 12635 value. Note that this option does not in any fashion affect the 12636 machine code emitted by the assembler. All it does is turn on the 12637 EF_IA_64_CONS_GP flag in the ELF file header. 12638 12639'-mauto-pic' 12640 This option instructs the assembler to mark the resulting object 12641 file as using the "constant GP without function descriptor" data 12642 model. This model is like the "constant GP" model, except that it 12643 additionally does away with function descriptors. What this means 12644 is that the address of a function refers directly to the function's 12645 code entry-point. Normally, such an address would refer to a 12646 function descriptor, which contains both the code entry-point and 12647 the GP-value needed by the function. Note that this option does 12648 not in any fashion affect the machine code emitted by the 12649 assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP 12650 flag in the ELF file header. 12651 12652'-milp32' 12653'-milp64' 12654'-mlp64' 12655'-mp64' 12656 These options select the data model. The assembler defaults to 12657 '-mlp64' (LP64 data model). 12658 12659'-mle' 12660'-mbe' 12661 These options select the byte order. The '-mle' option selects 12662 little-endian byte order (default) and '-mbe' selects big-endian 12663 byte order. Note that IA-64 machine code always uses little-endian 12664 byte order. 12665 12666'-mtune=itanium1' 12667'-mtune=itanium2' 12668 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 12669 is ITANIUM2. 12670 12671'-munwind-check=warning' 12672'-munwind-check=error' 12673 These options control what the assembler will do when performing 12674 consistency checks on unwind directives. '-munwind-check=warning' 12675 will make the assembler issue a warning when an unwind directive 12676 check fails. This is the default. '-munwind-check=error' will 12677 make the assembler issue an error when an unwind directive check 12678 fails. 12679 12680'-mhint.b=ok' 12681'-mhint.b=warning' 12682'-mhint.b=error' 12683 These options control what the assembler will do when the 'hint.b' 12684 instruction is used. '-mhint.b=ok' will make the assembler accept 12685 'hint.b'. '-mint.b=warning' will make the assembler issue a 12686 warning when 'hint.b' is used. '-mhint.b=error' will make the 12687 assembler treat 'hint.b' as an error, which is the default. 12688 12689'-x' 12690'-xexplicit' 12691 These options turn on dependency violation checking. 12692 12693'-xauto' 12694 This option instructs the assembler to automatically insert stop 12695 bits where necessary to remove dependency violations. This is the 12696 default mode. 12697 12698'-xnone' 12699 This option turns off dependency violation checking. 12700 12701'-xdebug' 12702 This turns on debug output intended to help tracking down bugs in 12703 the dependency violation checker. 12704 12705'-xdebugn' 12706 This is a shortcut for -xnone -xdebug. 12707 12708'-xdebugx' 12709 This is a shortcut for -xexplicit -xdebug. 12710 12711 12712File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 12713 127149.17.2 Syntax 12715------------- 12716 12717The assembler syntax closely follows the IA-64 Assembly Language 12718Reference Guide. 12719 12720* Menu: 12721 12722* IA-64-Chars:: Special Characters 12723* IA-64-Regs:: Register Names 12724* IA-64-Bits:: Bit Names 12725* IA-64-Relocs:: Relocations 12726 12727 12728File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 12729 127309.17.2.1 Special Characters 12731........................... 12732 12733'//' is the line comment token. 12734 12735 ';' can be used instead of a newline to separate statements. 12736 12737 12738File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 12739 127409.17.2.2 Register Names 12741....................... 12742 12743The 128 integer registers are referred to as 'rN'. The 128 12744floating-point registers are referred to as 'fN'. The 128 application 12745registers are referred to as 'arN'. The 128 control registers are 12746referred to as 'crN'. The 64 one-bit predicate registers are referred 12747to as 'pN'. The 8 branch registers are referred to as 'bN'. In 12748addition, the assembler defines a number of aliases: 'gp' ('r1'), 'sp' 12749('r12'), 'rp' ('b0'), 'ret0' ('r8'), 'ret1' ('r9'), 'ret2' ('r10'), 12750'ret3' ('r9'), 'fargN' ('f8+N'), and 'fretN' ('f8+N'). 12751 12752 For convenience, the assembler also defines aliases for all named 12753application and control registers. For example, 'ar.bsp' refers to the 12754register backing store pointer ('ar17'). Similarly, 'cr.eoi' refers to 12755the end-of-interrupt register ('cr67'). 12756 12757 12758File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 12759 127609.17.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 12761........................................................ 12762 12763The assembler defines bit masks for each of the bits in the IA-64 12764processor status register. For example, 'psr.ic' corresponds to a value 12765of 0x2000. These masks are primarily intended for use with the 12766'ssm'/'sum' and 'rsm'/'rum' instructions, but they can be used anywhere 12767else where an integer constant is expected. 12768 12769 12770File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 12771 127729.17.2.4 Relocations 12773.................... 12774 12775In addition to the standard IA-64 relocations, the following relocations 12776are implemented by 'as': 12777 12778'@slotcount(V)' 12779 Convert the address offset V into a slot count. This pseudo 12780 function is available only on VMS. The expression V must be known 12781 at assembly time: it can't reference undefined symbols or symbols 12782 in different sections. 12783 12784 12785File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 12786 127879.17.3 Opcodes 12788-------------- 12789 12790For detailed information on the IA-64 machine instruction set, see the 12791IA-64 Architecture Handbook 12792(http://developer.intel.com/design/itanium/arch_spec.htm). 12793 12794 12795File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 12796 127979.18 IP2K Dependent Features 12798============================ 12799 12800* Menu: 12801 12802* IP2K-Opts:: IP2K Options 12803* IP2K-Syntax:: IP2K Syntax 12804 12805 12806File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent 12807 128089.18.1 IP2K Options 12809------------------- 12810 12811The Ubicom IP2K version of 'as' has a few machine dependent options: 12812 12813'-mip2022ext' 12814 'as' can assemble the extended IP2022 instructions, but it will 12815 only do so if this is specifically allowed via this command line 12816 option. 12817 12818'-mip2022' 12819 This option restores the assembler's default behaviour of not 12820 permitting the extended IP2022 instructions to be assembled. 12821 12822 12823File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent 12824 128259.18.2 IP2K Syntax 12826------------------ 12827 12828* Menu: 12829 12830* IP2K-Chars:: Special Characters 12831 12832 12833File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax 12834 128359.18.2.1 Special Characters 12836........................... 12837 12838The presence of a ';' on a line indicates the start of a comment that 12839extends to the end of the current line. 12840 12841 If a '#' appears as the first character of a line, the whole line is 12842treated as a comment, but in this case the line can also be a logical 12843line number directive (*note Comments::) or a preprocessor control 12844command (*note Preprocessing::). 12845 12846 The IP2K assembler does not currently support a line separator 12847character. 12848 12849 12850File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 12851 128529.19 LM32 Dependent Features 12853============================ 12854 12855* Menu: 12856 12857* LM32 Options:: Options 12858* LM32 Syntax:: Syntax 12859* LM32 Opcodes:: Opcodes 12860 12861 12862File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 12863 128649.19.1 Options 12865-------------- 12866 12867'-mmultiply-enabled' 12868 Enable multiply instructions. 12869 12870'-mdivide-enabled' 12871 Enable divide instructions. 12872 12873'-mbarrel-shift-enabled' 12874 Enable barrel-shift instructions. 12875 12876'-msign-extend-enabled' 12877 Enable sign extend instructions. 12878 12879'-muser-enabled' 12880 Enable user defined instructions. 12881 12882'-micache-enabled' 12883 Enable instruction cache related CSRs. 12884 12885'-mdcache-enabled' 12886 Enable data cache related CSRs. 12887 12888'-mbreak-enabled' 12889 Enable break instructions. 12890 12891'-mall-enabled' 12892 Enable all instructions and CSRs. 12893 12894 12895File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 12896 128979.19.2 Syntax 12898------------- 12899 12900* Menu: 12901 12902* LM32-Regs:: Register Names 12903* LM32-Modifiers:: Relocatable Expression Modifiers 12904* LM32-Chars:: Special Characters 12905 12906 12907File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 12908 129099.19.2.1 Register Names 12910....................... 12911 12912LM32 has 32 x 32-bit general purpose registers 'r0', 'r1', ... 'r31'. 12913 12914 The following aliases are defined: 'gp' - 'r26', 'fp' - 'r27', 'sp' - 12915'r28', 'ra' - 'r29', 'ea' - 'r30', 'ba' - 'r31'. 12916 12917 LM32 has the following Control and Status Registers (CSRs). 12918 12919'IE' 12920 Interrupt enable. 12921'IM' 12922 Interrupt mask. 12923'IP' 12924 Interrupt pending. 12925'ICC' 12926 Instruction cache control. 12927'DCC' 12928 Data cache control. 12929'CC' 12930 Cycle counter. 12931'CFG' 12932 Configuration. 12933'EBA' 12934 Exception base address. 12935'DC' 12936 Debug control. 12937'DEBA' 12938 Debug exception base address. 12939'JTX' 12940 JTAG transmit. 12941'JRX' 12942 JTAG receive. 12943'BP0' 12944 Breakpoint 0. 12945'BP1' 12946 Breakpoint 1. 12947'BP2' 12948 Breakpoint 2. 12949'BP3' 12950 Breakpoint 3. 12951'WP0' 12952 Watchpoint 0. 12953'WP1' 12954 Watchpoint 1. 12955'WP2' 12956 Watchpoint 2. 12957'WP3' 12958 Watchpoint 3. 12959 12960 12961File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax 12962 129639.19.2.2 Relocatable Expression Modifiers 12964......................................... 12965 12966The assembler supports several modifiers when using relocatable 12967addresses in LM32 instruction operands. The general syntax is the 12968following: 12969 12970 modifier(relocatable-expression) 12971 12972'lo' 12973 12974 This modifier allows you to use bits 0 through 15 of an address 12975 expression as 16 bit relocatable expression. 12976 12977'hi' 12978 12979 This modifier allows you to use bits 16 through 23 of an address 12980 expression as 16 bit relocatable expression. 12981 12982 For example 12983 12984 ori r4, r4, lo(sym+10) 12985 orhi r4, r4, hi(sym+10) 12986 12987'gp' 12988 12989 This modified creates a 16-bit relocatable expression that is the 12990 offset of the symbol from the global pointer. 12991 12992 mva r4, gp(sym) 12993 12994'got' 12995 12996 This modifier places a symbol in the GOT and creates a 16-bit 12997 relocatable expression that is the offset into the GOT of this 12998 symbol. 12999 13000 lw r4, (gp+got(sym)) 13001 13002'gotofflo16' 13003 13004 This modifier allows you to use the bits 0 through 15 of an address 13005 which is an offset from the GOT. 13006 13007'gotoffhi16' 13008 13009 This modifier allows you to use the bits 16 through 31 of an 13010 address which is an offset from the GOT. 13011 13012 orhi r4, r4, gotoffhi16(lsym) 13013 addi r4, r4, gotofflo16(lsym) 13014 13015 13016File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax 13017 130189.19.2.3 Special Characters 13019........................... 13020 13021The presence of a '#' on a line indicates the start of a comment that 13022extends to the end of the current line. Note that if a line starts with 13023a '#' character then it can also be a logical line number directive 13024(*note Comments::) or a preprocessor control command (*note 13025Preprocessing::). 13026 13027 A semicolon (';') can be used to separate multiple statements on the 13028same line. 13029 13030 13031File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 13032 130339.19.3 Opcodes 13034-------------- 13035 13036For detailed information on the LM32 machine instruction set, see 13037<http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/>. 13038 13039 'as' implements all the standard LM32 opcodes. 13040 13041 13042File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 13043 130449.20 M32C Dependent Features 13045============================ 13046 13047'as' can assemble code for several different members of the Renesas M32C 13048family. Normally the default is to assemble code for the M16C 13049microprocessor. The '-m32c' option may be used to change the default to 13050the M32C microprocessor. 13051 13052* Menu: 13053 13054* M32C-Opts:: M32C Options 13055* M32C-Syntax:: M32C Syntax 13056 13057 13058File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent 13059 130609.20.1 M32C Options 13061------------------- 13062 13063The Renesas M32C version of 'as' has these machine-dependent options: 13064 13065'-m32c' 13066 Assemble M32C instructions. 13067 13068'-m16c' 13069 Assemble M16C instructions (default). 13070 13071'-relax' 13072 Enable support for link-time relaxations. 13073 13074'-h-tick-hex' 13075 Support H'00 style hex constants in addition to 0x00 style. 13076 13077 13078File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent 13079 130809.20.2 M32C Syntax 13081------------------ 13082 13083* Menu: 13084 13085* M32C-Modifiers:: Symbolic Operand Modifiers 13086* M32C-Chars:: Special Characters 13087 13088 13089File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax 13090 130919.20.2.1 Symbolic Operand Modifiers 13092................................... 13093 13094The assembler supports several modifiers when using symbol addresses in 13095M32C instruction operands. The general syntax is the following: 13096 13097 %modifier(symbol) 13098 13099'%dsp8' 13100'%dsp16' 13101 13102 These modifiers override the assembler's assumptions about how big 13103 a symbol's address is. Normally, when it sees an operand like 13104 'sym[a0]' it assumes 'sym' may require the widest displacement 13105 field (16 bits for '-m16c', 24 bits for '-m32c'). These modifiers 13106 tell it to assume the address will fit in an 8 or 16 bit 13107 (respectively) unsigned displacement. Note that, of course, if it 13108 doesn't actually fit you will get linker errors. Example: 13109 13110 mov.w %dsp8(sym)[a0],r1 13111 mov.b #0,%dsp8(sym)[a0] 13112 13113'%hi8' 13114 13115 This modifier allows you to load bits 16 through 23 of a 24 bit 13116 address into an 8 bit register. This is useful with, for example, 13117 the M16C 'smovf' instruction, which expects a 20 bit address in 13118 'r1h' and 'a0'. Example: 13119 13120 mov.b #%hi8(sym),r1h 13121 mov.w #%lo16(sym),a0 13122 smovf.b 13123 13124'%lo16' 13125 13126 Likewise, this modifier allows you to load bits 0 through 15 of a 13127 24 bit address into a 16 bit register. 13128 13129'%hi16' 13130 13131 This modifier allows you to load bits 16 through 31 of a 32 bit 13132 address into a 16 bit register. While the M32C family only has 24 13133 bits of address space, it does support addresses in pairs of 16 bit 13134 registers (like 'a1a0' for the 'lde' instruction). This modifier 13135 is for loading the upper half in such cases. Example: 13136 13137 mov.w #%hi16(sym),a1 13138 mov.w #%lo16(sym),a0 13139 ... 13140 lde.w [a1a0],r1 13141 13142 13143File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax 13144 131459.20.2.2 Special Characters 13146........................... 13147 13148The presence of a ';' character on a line indicates the start of a 13149comment that extends to the end of that line. 13150 13151 If a '#' appears as the first character of a line, the whole line is 13152treated as a comment, but in this case the line can also be a logical 13153line number directive (*note Comments::) or a preprocessor control 13154command (*note Preprocessing::). 13155 13156 The '|' character can be used to separate statements on the same 13157line. 13158 13159 13160File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 13161 131629.21 M32R Dependent Features 13163============================ 13164 13165* Menu: 13166 13167* M32R-Opts:: M32R Options 13168* M32R-Directives:: M32R Directives 13169* M32R-Warnings:: M32R Warnings 13170 13171 13172File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 13173 131749.21.1 M32R Options 13175------------------- 13176 13177The Renesas M32R version of 'as' has a few machine dependent options: 13178 13179'-m32rx' 13180 'as' can assemble code for several different members of the Renesas 13181 M32R family. Normally the default is to assemble code for the M32R 13182 microprocessor. This option may be used to change the default to 13183 the M32RX microprocessor, which adds some more instructions to the 13184 basic M32R instruction set, and some additional parameters to some 13185 of the original instructions. 13186 13187'-m32r2' 13188 This option changes the target processor to the M32R2 13189 microprocessor. 13190 13191'-m32r' 13192 This option can be used to restore the assembler's default 13193 behaviour of assembling for the M32R microprocessor. This can be 13194 useful if the default has been changed by a previous command-line 13195 option. 13196 13197'-little' 13198 This option tells the assembler to produce little-endian code and 13199 data. The default is dependent upon how the toolchain was 13200 configured. 13201 13202'-EL' 13203 This is a synonym for _-little_. 13204 13205'-big' 13206 This option tells the assembler to produce big-endian code and 13207 data. 13208 13209'-EB' 13210 This is a synonym for _-big_. 13211 13212'-KPIC' 13213 This option specifies that the output of the assembler should be 13214 marked as position-independent code (PIC). 13215 13216'-parallel' 13217 This option tells the assembler to attempts to combine two 13218 sequential instructions into a single, parallel instruction, where 13219 it is legal to do so. 13220 13221'-no-parallel' 13222 This option disables a previously enabled _-parallel_ option. 13223 13224'-no-bitinst' 13225 This option disables the support for the extended bit-field 13226 instructions provided by the M32R2. If this support needs to be 13227 re-enabled the _-bitinst_ switch can be used to restore it. 13228 13229'-O' 13230 This option tells the assembler to attempt to optimize the 13231 instructions that it produces. This includes filling delay slots 13232 and converting sequential instructions into parallel ones. This 13233 option implies _-parallel_. 13234 13235'-warn-explicit-parallel-conflicts' 13236 Instructs 'as' to produce warning messages when questionable 13237 parallel instructions are encountered. This option is enabled by 13238 default, but 'gcc' disables it when it invokes 'as' directly. 13239 Questionable instructions are those whose behaviour would be 13240 different if they were executed sequentially. For example the code 13241 fragment 'mv r1, r2 || mv r3, r1' produces a different result from 13242 'mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then 13243 r2 into r1, whereas the later moves r2 into r1 and r3. 13244 13245'-Wp' 13246 This is a shorter synonym for the 13247 _-warn-explicit-parallel-conflicts_ option. 13248 13249'-no-warn-explicit-parallel-conflicts' 13250 Instructs 'as' not to produce warning messages when questionable 13251 parallel instructions are encountered. 13252 13253'-Wnp' 13254 This is a shorter synonym for the 13255 _-no-warn-explicit-parallel-conflicts_ option. 13256 13257'-ignore-parallel-conflicts' 13258 This option tells the assembler's to stop checking parallel 13259 instructions for constraint violations. This ability is provided 13260 for hardware vendors testing chip designs and should not be used 13261 under normal circumstances. 13262 13263'-no-ignore-parallel-conflicts' 13264 This option restores the assembler's default behaviour of checking 13265 parallel instructions to detect constraint violations. 13266 13267'-Ip' 13268 This is a shorter synonym for the _-ignore-parallel-conflicts_ 13269 option. 13270 13271'-nIp' 13272 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 13273 option. 13274 13275'-warn-unmatched-high' 13276 This option tells the assembler to produce a warning message if a 13277 '.high' pseudo op is encountered without a matching '.low' pseudo 13278 op. The presence of such an unmatched pseudo op usually indicates 13279 a programming error. 13280 13281'-no-warn-unmatched-high' 13282 Disables a previously enabled _-warn-unmatched-high_ option. 13283 13284'-Wuh' 13285 This is a shorter synonym for the _-warn-unmatched-high_ option. 13286 13287'-Wnuh' 13288 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 13289 13290 13291File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 13292 132939.21.2 M32R Directives 13294---------------------- 13295 13296The Renesas M32R version of 'as' has a few architecture specific 13297directives: 13298 13299'low EXPRESSION' 13300 The 'low' directive computes the value of its expression and places 13301 the lower 16-bits of the result into the immediate-field of the 13302 instruction. For example: 13303 13304 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 13305 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 13306 13307'high EXPRESSION' 13308 The 'high' directive computes the value of its expression and 13309 places the upper 16-bits of the result into the immediate-field of 13310 the instruction. For example: 13311 13312 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 13313 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 13314 13315'shigh EXPRESSION' 13316 The 'shigh' directive is very similar to the 'high' directive. It 13317 also computes the value of its expression and places the upper 13318 16-bits of the result into the immediate-field of the instruction. 13319 The difference is that 'shigh' also checks to see if the lower 13320 16-bits could be interpreted as a signed number, and if so it 13321 assumes that a borrow will occur from the upper-16 bits. To 13322 compensate for this the 'shigh' directive pre-biases the upper 16 13323 bit value by adding one to it. For example: 13324 13325 For example: 13326 13327 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 13328 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 13329 13330 In the second example the lower 16-bits are 0x8000. If these are 13331 treated as a signed value and sign extended to 32-bits then the 13332 value becomes 0xffff8000. If this value is then added to 13333 0x00010000 then the result is 0x00008000. 13334 13335 This behaviour is to allow for the different semantics of the 'or3' 13336 and 'add3' instructions. The 'or3' instruction treats its 16-bit 13337 immediate argument as unsigned whereas the 'add3' treats its 16-bit 13338 immediate as a signed value. So for example: 13339 13340 seth r0, #shigh(0x00008000) 13341 add3 r0, r0, #low(0x00008000) 13342 13343 Produces the correct result in r0, whereas: 13344 13345 seth r0, #shigh(0x00008000) 13346 or3 r0, r0, #low(0x00008000) 13347 13348 Stores 0xffff8000 into r0. 13349 13350 Note - the 'shigh' directive does not know where in the assembly 13351 source code the lower 16-bits of the value are going set, so it 13352 cannot check to make sure that an 'or3' instruction is being used 13353 rather than an 'add3' instruction. It is up to the programmer to 13354 make sure that correct directives are used. 13355 13356'.m32r' 13357 The directive performs a similar thing as the _-m32r_ command line 13358 option. It tells the assembler to only accept M32R instructions 13359 from now on. An instructions from later M32R architectures are 13360 refused. 13361 13362'.m32rx' 13363 The directive performs a similar thing as the _-m32rx_ command line 13364 option. It tells the assembler to start accepting the extra 13365 instructions in the M32RX ISA as well as the ordinary M32R ISA. 13366 13367'.m32r2' 13368 The directive performs a similar thing as the _-m32r2_ command line 13369 option. It tells the assembler to start accepting the extra 13370 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 13371 13372'.little' 13373 The directive performs a similar thing as the _-little_ command 13374 line option. It tells the assembler to start producing 13375 little-endian code and data. This option should be used with care 13376 as producing mixed-endian binary files is fraught with danger. 13377 13378'.big' 13379 The directive performs a similar thing as the _-big_ command line 13380 option. It tells the assembler to start producing big-endian code 13381 and data. This option should be used with care as producing 13382 mixed-endian binary files is fraught with danger. 13383 13384 13385File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 13386 133879.21.3 M32R Warnings 13388-------------------- 13389 13390There are several warning and error messages that can be produced by 13391'as' which are specific to the M32R: 13392 13393'output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 13394 This message is only produced if warnings for explicit parallel 13395 conflicts have been enabled. It indicates that the assembler has 13396 encountered a parallel instruction in which the destination 13397 register of the left hand instruction is used as an input register 13398 in the right hand instruction. For example in this code fragment 13399 'mv r1, r2 || neg r3, r1' register r1 is the destination of the 13400 move instruction and the input to the neg instruction. 13401 13402'output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 13403 This message is only produced if warnings for explicit parallel 13404 conflicts have been enabled. It indicates that the assembler has 13405 encountered a parallel instruction in which the destination 13406 register of the right hand instruction is used as an input register 13407 in the left hand instruction. For example in this code fragment 13408 'mv r1, r2 || neg r2, r3' register r2 is the destination of the neg 13409 instruction and the input to the move instruction. 13410 13411'instruction '...' is for the M32RX only' 13412 This message is produced when the assembler encounters an 13413 instruction which is only supported by the M32Rx processor, and the 13414 '-m32rx' command-line flag has not been specified to allow assembly 13415 of such instructions. 13416 13417'unknown instruction '...'' 13418 This message is produced when the assembler encounters an 13419 instruction which it does not recognize. 13420 13421'only the NOP instruction can be issued in parallel on the m32r' 13422 This message is produced when the assembler encounters a parallel 13423 instruction which does not involve a NOP instruction and the 13424 '-m32rx' command-line flag has not been specified. Only the M32Rx 13425 processor is able to execute two instructions in parallel. 13426 13427'instruction '...' cannot be executed in parallel.' 13428 This message is produced when the assembler encounters a parallel 13429 instruction which is made up of one or two instructions which 13430 cannot be executed in parallel. 13431 13432'Instructions share the same execution pipeline' 13433 This message is produced when the assembler encounters a parallel 13434 instruction whose components both use the same execution pipeline. 13435 13436'Instructions write to the same destination register.' 13437 This message is produced when the assembler encounters a parallel 13438 instruction where both components attempt to modify the same 13439 register. For example these code fragments will produce this 13440 message: 'mv r1, r2 || neg r1, r3' 'jl r0 || mv r14, r1' 'st r2, 13441 @-r1 || mv r1, r3' 'mv r1, r2 || ld r0, @r1+' 'cmp r1, r2 || addx 13442 r3, r4' (Both write to the condition bit) 13443 13444 13445File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 13446 134479.22 M680x0 Dependent Features 13448============================== 13449 13450* Menu: 13451 13452* M68K-Opts:: M680x0 Options 13453* M68K-Syntax:: Syntax 13454* M68K-Moto-Syntax:: Motorola Syntax 13455* M68K-Float:: Floating Point 13456* M68K-Directives:: 680x0 Machine Directives 13457* M68K-opcodes:: Opcodes 13458 13459 13460File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 13461 134629.22.1 M680x0 Options 13463--------------------- 13464 13465The Motorola 680x0 version of 'as' has a few machine dependent options: 13466 13467'-march=ARCHITECTURE' 13468 This option specifies a target architecture. The following 13469 architectures are recognized: '68000', '68010', '68020', '68030', 13470 '68040', '68060', 'cpu32', 'isaa', 'isaaplus', 'isab', 'isac' and 13471 'cfv4e'. 13472 13473'-mcpu=CPU' 13474 This option specifies a target cpu. When used in conjunction with 13475 the '-march' option, the cpu must be within the specified 13476 architecture. Also, the generic features of the architecture are 13477 used for instruction generation, rather than those of the specific 13478 chip. 13479 13480'-m[no-]68851' 13481'-m[no-]68881' 13482'-m[no-]div' 13483'-m[no-]usp' 13484'-m[no-]float' 13485'-m[no-]mac' 13486'-m[no-]emac' 13487 13488 Enable or disable various architecture specific features. If a 13489 chip or architecture by default supports an option (for instance 13490 '-march=isaaplus' includes the '-mdiv' option), explicitly 13491 disabling the option will override the default. 13492 13493'-l' 13494 You can use the '-l' option to shorten the size of references to 13495 undefined symbols. If you do not use the '-l' option, references 13496 to undefined symbols are wide enough for a full 'long' (32 bits). 13497 (Since 'as' cannot know where these symbols end up, 'as' can only 13498 allocate space for the linker to fill in later. Since 'as' does 13499 not know how far away these symbols are, it allocates as much space 13500 as it can.) If you use this option, the references are only one 13501 word wide (16 bits). This may be useful if you want the object 13502 file to be as small as possible, and you know that the relevant 13503 symbols are always less than 17 bits away. 13504 13505'--register-prefix-optional' 13506 For some configurations, especially those where the compiler 13507 normally does not prepend an underscore to the names of user 13508 variables, the assembler requires a '%' before any use of a 13509 register name. This is intended to let the assembler distinguish 13510 between C variables and functions named 'a0' through 'a7', and so 13511 on. The '%' is always accepted, but is not required for certain 13512 configurations, notably 'sun3'. The '--register-prefix-optional' 13513 option may be used to permit omitting the '%' even for 13514 configurations for which it is normally required. If this is done, 13515 it will generally be impossible to refer to C variables and 13516 functions with the same names as register names. 13517 13518'--bitwise-or' 13519 Normally the character '|' is treated as a comment character, which 13520 means that it can not be used in expressions. The '--bitwise-or' 13521 option turns '|' into a normal character. In this mode, you must 13522 either use C style comments, or start comments with a '#' character 13523 at the beginning of a line. 13524 13525'--base-size-default-16 --base-size-default-32' 13526 If you use an addressing mode with a base register without 13527 specifying the size, 'as' will normally use the full 32 bit value. 13528 For example, the addressing mode '%a0@(%d0)' is equivalent to 13529 '%a0@(%d0:l)'. You may use the '--base-size-default-16' option to 13530 tell 'as' to default to using the 16 bit value. In this case, 13531 '%a0@(%d0)' is equivalent to '%a0@(%d0:w)'. You may use the 13532 '--base-size-default-32' option to restore the default behaviour. 13533 13534'--disp-size-default-16 --disp-size-default-32' 13535 If you use an addressing mode with a displacement, and the value of 13536 the displacement is not known, 'as' will normally assume that the 13537 value is 32 bits. For example, if the symbol 'disp' has not been 13538 defined, 'as' will assemble the addressing mode '%a0@(disp,%d0)' as 13539 though 'disp' is a 32 bit value. You may use the 13540 '--disp-size-default-16' option to tell 'as' to instead assume that 13541 the displacement is 16 bits. In this case, 'as' will assemble 13542 '%a0@(disp,%d0)' as though 'disp' is a 16 bit value. You may use 13543 the '--disp-size-default-32' option to restore the default 13544 behaviour. 13545 13546'--pcrel' 13547 Always keep branches PC-relative. In the M680x0 architecture all 13548 branches are defined as PC-relative. However, on some processors 13549 they are limited to word displacements maximum. When 'as' needs a 13550 long branch that is not available, it normally emits an absolute 13551 jump instead. This option disables this substitution. When this 13552 option is given and no long branches are available, only word 13553 branches will be emitted. An error message will be generated if a 13554 word branch cannot reach its target. This option has no effect on 13555 68020 and other processors that have long branches. *note Branch 13556 Improvement: M68K-Branch. 13557 13558'-m68000' 13559 'as' can assemble code for several different members of the 13560 Motorola 680x0 family. The default depends upon how 'as' was 13561 configured when it was built; normally, the default is to assemble 13562 code for the 68020 microprocessor. The following options may be 13563 used to change the default. These options control which 13564 instructions and addressing modes are permitted. The members of 13565 the 680x0 family are very similar. For detailed information about 13566 the differences, see the Motorola manuals. 13567 13568 '-m68000' 13569 '-m68ec000' 13570 '-m68hc000' 13571 '-m68hc001' 13572 '-m68008' 13573 '-m68302' 13574 '-m68306' 13575 '-m68307' 13576 '-m68322' 13577 '-m68356' 13578 Assemble for the 68000. '-m68008', '-m68302', and so on are 13579 synonyms for '-m68000', since the chips are the same from the 13580 point of view of the assembler. 13581 13582 '-m68010' 13583 Assemble for the 68010. 13584 13585 '-m68020' 13586 '-m68ec020' 13587 Assemble for the 68020. This is normally the default. 13588 13589 '-m68030' 13590 '-m68ec030' 13591 Assemble for the 68030. 13592 13593 '-m68040' 13594 '-m68ec040' 13595 Assemble for the 68040. 13596 13597 '-m68060' 13598 '-m68ec060' 13599 Assemble for the 68060. 13600 13601 '-mcpu32' 13602 '-m68330' 13603 '-m68331' 13604 '-m68332' 13605 '-m68333' 13606 '-m68334' 13607 '-m68336' 13608 '-m68340' 13609 '-m68341' 13610 '-m68349' 13611 '-m68360' 13612 Assemble for the CPU32 family of chips. 13613 13614 '-m5200' 13615 '-m5202' 13616 '-m5204' 13617 '-m5206' 13618 '-m5206e' 13619 '-m521x' 13620 '-m5249' 13621 '-m528x' 13622 '-m5307' 13623 '-m5407' 13624 '-m547x' 13625 '-m548x' 13626 '-mcfv4' 13627 '-mcfv4e' 13628 Assemble for the ColdFire family of chips. 13629 13630 '-m68881' 13631 '-m68882' 13632 Assemble 68881 floating point instructions. This is the 13633 default for the 68020, 68030, and the CPU32. The 68040 and 13634 68060 always support floating point instructions. 13635 13636 '-mno-68881' 13637 Do not assemble 68881 floating point instructions. This is 13638 the default for 68000 and the 68010. The 68040 and 68060 13639 always support floating point instructions, even if this 13640 option is used. 13641 13642 '-m68851' 13643 Assemble 68851 MMU instructions. This is the default for the 13644 68020, 68030, and 68060. The 68040 accepts a somewhat 13645 different set of MMU instructions; '-m68851' and '-m68040' 13646 should not be used together. 13647 13648 '-mno-68851' 13649 Do not assemble 68851 MMU instructions. This is the default 13650 for the 68000, 68010, and the CPU32. The 68040 accepts a 13651 somewhat different set of MMU instructions. 13652 13653 13654File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 13655 136569.22.2 Syntax 13657------------- 13658 13659This syntax for the Motorola 680x0 was developed at MIT. 13660 13661 The 680x0 version of 'as' uses instructions names and syntax 13662compatible with the Sun assembler. Intervening periods are ignored; for 13663example, 'movl' is equivalent to 'mov.l'. 13664 13665 In the following table APC stands for any of the address registers 13666('%a0' through '%a7'), the program counter ('%pc'), the zero-address 13667relative to the program counter ('%zpc'), a suppressed address register 13668('%za0' through '%za7'), or it may be omitted entirely. The use of SIZE 13669means one of 'w' or 'l', and it may be omitted, along with the leading 13670colon, unless a scale is also specified. The use of SCALE means one of 13671'1', '2', '4', or '8', and it may always be omitted along with the 13672leading colon. 13673 13674 The following addressing modes are understood: 13675"Immediate" 13676 '#NUMBER' 13677 13678"Data Register" 13679 '%d0' through '%d7' 13680 13681"Address Register" 13682 '%a0' through '%a7' 13683 '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is 13684 also known as '%fp', the Frame Pointer. 13685 13686"Address Register Indirect" 13687 '%a0@' through '%a7@' 13688 13689"Address Register Postincrement" 13690 '%a0@+' through '%a7@+' 13691 13692"Address Register Predecrement" 13693 '%a0@-' through '%a7@-' 13694 13695"Indirect Plus Offset" 13696 'APC@(NUMBER)' 13697 13698"Index" 13699 'APC@(NUMBER,REGISTER:SIZE:SCALE)' 13700 13701 The NUMBER may be omitted. 13702 13703"Postindex" 13704 'APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 13705 13706 The ONUMBER or the REGISTER, but not both, may be omitted. 13707 13708"Preindex" 13709 'APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 13710 13711 The NUMBER may be omitted. Omitting the REGISTER produces the 13712 Postindex addressing mode. 13713 13714"Absolute" 13715 'SYMBOL', or 'DIGITS', optionally followed by ':b', ':w', or ':l'. 13716 13717 13718File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 13719 137209.22.3 Motorola Syntax 13721---------------------- 13722 13723The standard Motorola syntax for this chip differs from the syntax 13724already discussed (*note Syntax: M68K-Syntax.). 'as' can accept 13725Motorola syntax for operands, even if MIT syntax is used for other 13726operands in the same instruction. The two kinds of syntax are fully 13727compatible. 13728 13729 In the following table APC stands for any of the address registers 13730('%a0' through '%a7'), the program counter ('%pc'), the zero-address 13731relative to the program counter ('%zpc'), or a suppressed address 13732register ('%za0' through '%za7'). The use of SIZE means one of 'w' or 13733'l', and it may always be omitted along with the leading dot. The use 13734of SCALE means one of '1', '2', '4', or '8', and it may always be 13735omitted along with the leading asterisk. 13736 13737 The following additional addressing modes are understood: 13738 13739"Address Register Indirect" 13740 '(%a0)' through '(%a7)' 13741 '%a7' is also known as '%sp', i.e., the Stack Pointer. '%a6' is 13742 also known as '%fp', the Frame Pointer. 13743 13744"Address Register Postincrement" 13745 '(%a0)+' through '(%a7)+' 13746 13747"Address Register Predecrement" 13748 '-(%a0)' through '-(%a7)' 13749 13750"Indirect Plus Offset" 13751 'NUMBER(%A0)' through 'NUMBER(%A7)', or 'NUMBER(%PC)'. 13752 13753 The NUMBER may also appear within the parentheses, as in 13754 '(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 13755 (with an address register, omitting the NUMBER produces Address 13756 Register Indirect mode). 13757 13758"Index" 13759 'NUMBER(APC,REGISTER.SIZE*SCALE)' 13760 13761 The NUMBER may be omitted, or it may appear within the parentheses. 13762 The APC may be omitted. The REGISTER and the APC may appear in 13763 either order. If both APC and REGISTER are address registers, and 13764 the SIZE and SCALE are omitted, then the first register is taken as 13765 the base register, and the second as the index register. 13766 13767"Postindex" 13768 '([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 13769 13770 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 13771 NUMBER or the APC may be omitted, but not both. 13772 13773"Preindex" 13774 '([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 13775 13776 The NUMBER, or the APC, or the REGISTER, or any two of them, may be 13777 omitted. The ONUMBER may be omitted. The REGISTER and the APC may 13778 appear in either order. If both APC and REGISTER are address 13779 registers, and the SIZE and SCALE are omitted, then the first 13780 register is taken as the base register, and the second as the index 13781 register. 13782 13783 13784File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 13785 137869.22.4 Floating Point 13787--------------------- 13788 13789Packed decimal (P) format floating literals are not supported. Feel 13790free to add the code! 13791 13792 The floating point formats generated by directives are these. 13793 13794'.float' 13795 'Single' precision floating point constants. 13796 13797'.double' 13798 'Double' precision floating point constants. 13799 13800'.extend' 13801'.ldouble' 13802 'Extended' precision ('long double') floating point constants. 13803 13804 13805File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 13806 138079.22.5 680x0 Machine Directives 13808------------------------------- 13809 13810In order to be compatible with the Sun assembler the 680x0 assembler 13811understands the following directives. 13812 13813'.data1' 13814 This directive is identical to a '.data 1' directive. 13815 13816'.data2' 13817 This directive is identical to a '.data 2' directive. 13818 13819'.even' 13820 This directive is a special case of the '.align' directive; it 13821 aligns the output to an even byte boundary. 13822 13823'.skip' 13824 This directive is identical to a '.space' directive. 13825 13826'.arch NAME' 13827 Select the target architecture and extension features. Valid 13828 values for NAME are the same as for the '-march' command-line 13829 option. This directive cannot be specified after any instructions 13830 have been assembled. If it is given multiple times, or in 13831 conjunction with the '-march' option, all uses must be for the same 13832 architecture and extension set. 13833 13834'.cpu NAME' 13835 Select the target cpu. Valid values for NAME are the same as for 13836 the '-mcpu' command-line option. This directive cannot be 13837 specified after any instructions have been assembled. If it is 13838 given multiple times, or in conjunction with the '-mopt' option, 13839 all uses must be for the same cpu. 13840 13841 13842File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 13843 138449.22.6 Opcodes 13845-------------- 13846 13847* Menu: 13848 13849* M68K-Branch:: Branch Improvement 13850* M68K-Chars:: Special Characters 13851 13852 13853File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 13854 138559.22.6.1 Branch Improvement 13856........................... 13857 13858Certain pseudo opcodes are permitted for branch instructions. They 13859expand to the shortest branch instruction that reach the target. 13860Generally these mnemonics are made by substituting 'j' for 'b' at the 13861start of a Motorola mnemonic. 13862 13863 The following table summarizes the pseudo-operations. A '*' flags 13864cases that are more fully described after the table: 13865 13866 Displacement 13867 +------------------------------------------------------------ 13868 | 68020 68000/10, not PC-relative OK 13869 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 13870 +------------------------------------------------------------ 13871 jbsr |bsrs bsrw bsrl jsr 13872 jra |bras braw bral jmp 13873 * jXX |bXXs bXXw bXXl bNXs;jmp 13874 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 13875 fjXX | N/A fbXXw fbXXl N/A 13876 13877 XX: condition 13878 NX: negative of condition XX 13879 13880 '*'--see full description below 13881 '**'--this expansion mode is disallowed by '--pcrel' 13882 13883'jbsr' 13884'jra' 13885 These are the simplest jump pseudo-operations; they always map to 13886 one particular machine instruction, depending on the displacement 13887 to the branch target. This instruction will be a byte or word 13888 branch is that is sufficient. Otherwise, a long branch will be 13889 emitted if available. If no long branches are available and the 13890 '--pcrel' option is not given, an absolute long jump will be 13891 emitted instead. If no long branches are available, the '--pcrel' 13892 option is given, and a word branch cannot reach the target, an 13893 error message is generated. 13894 13895 In addition to standard branch operands, 'as' allows these 13896 pseudo-operations to have all operands that are allowed for jsr and 13897 jmp, substituting these instructions if the operand given is not 13898 valid for a branch instruction. 13899 13900'jXX' 13901 Here, 'jXX' stands for an entire family of pseudo-operations, where 13902 XX is a conditional branch or condition-code test. The full list 13903 of pseudo-ops in this family is: 13904 jhi jls jcc jcs jne jeq jvc 13905 jvs jpl jmi jge jlt jgt jle 13906 13907 Usually, each of these pseudo-operations expands to a single branch 13908 instruction. However, if a word branch is not sufficient, no long 13909 branches are available, and the '--pcrel' option is not given, 'as' 13910 issues a longer code fragment in terms of NX, the opposite 13911 condition to XX. For example, under these conditions: 13912 jXX foo 13913 gives 13914 bNXs oof 13915 jmp foo 13916 oof: 13917 13918'dbXX' 13919 The full family of pseudo-operations covered here is 13920 dbhi dbls dbcc dbcs dbne dbeq dbvc 13921 dbvs dbpl dbmi dbge dblt dbgt dble 13922 dbf dbra dbt 13923 13924 Motorola 'dbXX' instructions allow word displacements only. When a 13925 word displacement is sufficient, each of these pseudo-operations 13926 expands to the corresponding Motorola instruction. When a word 13927 displacement is not sufficient and long branches are available, 13928 when the source reads 'dbXX foo', 'as' emits 13929 dbXX oo1 13930 bras oo2 13931 oo1:bral foo 13932 oo2: 13933 13934 If, however, long branches are not available and the '--pcrel' 13935 option is not given, 'as' emits 13936 dbXX oo1 13937 bras oo2 13938 oo1:jmp foo 13939 oo2: 13940 13941'fjXX' 13942 This family includes 13943 fjne fjeq fjge fjlt fjgt fjle fjf 13944 fjt fjgl fjgle fjnge fjngl fjngle fjngt 13945 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 13946 fjor fjseq fjsf fjsne fjst fjueq fjuge 13947 fjugt fjule fjult fjun 13948 13949 Each of these pseudo-operations always expands to a single Motorola 13950 coprocessor branch instruction, word or long. All Motorola 13951 coprocessor branch instructions allow both word and long 13952 displacements. 13953 13954 13955File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 13956 139579.22.6.2 Special Characters 13958........................... 13959 13960Line comments are introduced by the '|' character appearing anywhere on 13961a line, unless the '--bitwise-or' command-line option has been 13962specified. 13963 13964 An asterisk ('*') as the first character on a line marks the start of 13965a line comment as well. 13966 13967 A hash character ('#') as the first character on a line also marks 13968the start of a line comment, but in this case it could also be a logical 13969line number directive (*note Comments::) or a preprocessor control 13970command (*note Preprocessing::). If the hash character appears 13971elsewhere on a line it is used to introduce an immediate value. (This 13972is for compatibility with Sun's assembler). 13973 13974 Multiple statements on the same line can appear if they are separated 13975by the ';' character. 13976 13977 13978File: as.info, Node: M68HC11-Dependent, Next: S12Z-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 13979 139809.23 M68HC11 and M68HC12 Dependent Features 13981=========================================== 13982 13983* Menu: 13984 13985* M68HC11-Opts:: M68HC11 and M68HC12 Options 13986* M68HC11-Syntax:: Syntax 13987* M68HC11-Modifiers:: Symbolic Operand Modifiers 13988* M68HC11-Directives:: Assembler Directives 13989* M68HC11-Float:: Floating Point 13990* M68HC11-opcodes:: Opcodes 13991 13992 13993File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 13994 139959.23.1 M68HC11 and M68HC12 Options 13996---------------------------------- 13997 13998The Motorola 68HC11 and 68HC12 version of 'as' have a few machine 13999dependent options. 14000 14001'-m68hc11' 14002 This option switches the assembler into the M68HC11 mode. In this 14003 mode, the assembler only accepts 68HC11 operands and mnemonics. It 14004 produces code for the 68HC11. 14005 14006'-m68hc12' 14007 This option switches the assembler into the M68HC12 mode. In this 14008 mode, the assembler also accepts 68HC12 operands and mnemonics. It 14009 produces code for the 68HC12. A few 68HC11 instructions are 14010 replaced by some 68HC12 instructions as recommended by Motorola 14011 specifications. 14012 14013'-m68hcs12' 14014 This option switches the assembler into the M68HCS12 mode. This 14015 mode is similar to '-m68hc12' but specifies to assemble for the 14016 68HCS12 series. The only difference is on the assembling of the 14017 'movb' and 'movw' instruction when a PC-relative operand is used. 14018 14019'-mm9s12x' 14020 This option switches the assembler into the M9S12X mode. This mode 14021 is similar to '-m68hc12' but specifies to assemble for the S12X 14022 series which is a superset of the HCS12. 14023 14024'-mm9s12xg' 14025 This option switches the assembler into the XGATE mode for the RISC 14026 co-processor featured on some S12X-family chips. 14027 14028'--xgate-ramoffset' 14029 This option instructs the linker to offset RAM addresses from S12X 14030 address space into XGATE address space. 14031 14032'-mshort' 14033 This option controls the ABI and indicates to use a 16-bit integer 14034 ABI. It has no effect on the assembled instructions. This is the 14035 default. 14036 14037'-mlong' 14038 This option controls the ABI and indicates to use a 32-bit integer 14039 ABI. 14040 14041'-mshort-double' 14042 This option controls the ABI and indicates to use a 32-bit float 14043 ABI. This is the default. 14044 14045'-mlong-double' 14046 This option controls the ABI and indicates to use a 64-bit float 14047 ABI. 14048 14049'--strict-direct-mode' 14050 You can use the '--strict-direct-mode' option to disable the 14051 automatic translation of direct page mode addressing into extended 14052 mode when the instruction does not support direct mode. For 14053 example, the 'clr' instruction does not support direct page mode 14054 addressing. When it is used with the direct page mode, 'as' will 14055 ignore it and generate an absolute addressing. This option 14056 prevents 'as' from doing this, and the wrong usage of the direct 14057 page mode will raise an error. 14058 14059'--short-branches' 14060 The '--short-branches' option turns off the translation of relative 14061 branches into absolute branches when the branch offset is out of 14062 range. By default 'as' transforms the relative branch ('bsr', 14063 'bgt', 'bge', 'beq', 'bne', 'ble', 'blt', 'bhi', 'bcc', 'bls', 14064 'bcs', 'bmi', 'bvs', 'bvs', 'bra') into an absolute branch when the 14065 offset is out of the -128 .. 127 range. In that case, the 'bsr' 14066 instruction is translated into a 'jsr', the 'bra' instruction is 14067 translated into a 'jmp' and the conditional branches instructions 14068 are inverted and followed by a 'jmp'. This option disables these 14069 translations and 'as' will generate an error if a relative branch 14070 is out of range. This option does not affect the optimization 14071 associated to the 'jbra', 'jbsr' and 'jbXX' pseudo opcodes. 14072 14073'--force-long-branches' 14074 The '--force-long-branches' option forces the translation of 14075 relative branches into absolute branches. This option does not 14076 affect the optimization associated to the 'jbra', 'jbsr' and 'jbXX' 14077 pseudo opcodes. 14078 14079'--print-insn-syntax' 14080 You can use the '--print-insn-syntax' option to obtain the syntax 14081 description of the instruction when an error is detected. 14082 14083'--print-opcodes' 14084 The '--print-opcodes' option prints the list of all the 14085 instructions with their syntax. The first item of each line 14086 represents the instruction name and the rest of the line indicates 14087 the possible operands for that instruction. The list is printed in 14088 alphabetical order. Once the list is printed 'as' exits. 14089 14090'--generate-example' 14091 The '--generate-example' option is similar to '--print-opcodes' but 14092 it generates an example for each instruction instead. 14093 14094 14095File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 14096 140979.23.2 Syntax 14098------------- 14099 14100In the M68HC11 syntax, the instruction name comes first and it may be 14101followed by one or several operands (up to three). Operands are 14102separated by comma (','). In the normal mode, 'as' will complain if too 14103many operands are specified for a given instruction. In the MRI mode 14104(turned on with '-M' option), it will treat them as comments. Example: 14105 14106 inx 14107 lda #23 14108 bset 2,x #4 14109 brclr *bot #8 foo 14110 14111 The presence of a ';' character or a '!' character anywhere on a line 14112indicates the start of a comment that extends to the end of that line. 14113 14114 A '*' or a '#' character at the start of a line also introduces a 14115line comment, but these characters do not work elsewhere on the line. 14116If the first character of the line is a '#' then as well as starting a 14117comment, the line could also be logical line number directive (*note 14118Comments::) or a preprocessor control command (*note Preprocessing::). 14119 14120 The M68HC11 assembler does not currently support a line separator 14121character. 14122 14123 The following addressing modes are understood for 68HC11 and 68HC12: 14124"Immediate" 14125 '#NUMBER' 14126 14127"Address Register" 14128 'NUMBER,X', 'NUMBER,Y' 14129 14130 The NUMBER may be omitted in which case 0 is assumed. 14131 14132"Direct Addressing mode" 14133 '*SYMBOL', or '*DIGITS' 14134 14135"Absolute" 14136 'SYMBOL', or 'DIGITS' 14137 14138 The M68HC12 has other more complex addressing modes. All of them are 14139supported and they are represented below: 14140 14141"Constant Offset Indexed Addressing Mode" 14142 'NUMBER,REG' 14143 14144 The NUMBER may be omitted in which case 0 is assumed. The register 14145 can be either 'X', 'Y', 'SP' or 'PC'. The assembler will use the 14146 smaller post-byte definition according to the constant value (5-bit 14147 constant offset, 9-bit constant offset or 16-bit constant offset). 14148 If the constant is not known by the assembler it will use the 14149 16-bit constant offset post-byte and the value will be resolved at 14150 link time. 14151 14152"Offset Indexed Indirect" 14153 '[NUMBER,REG]' 14154 14155 The register can be either 'X', 'Y', 'SP' or 'PC'. 14156 14157"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 14158 'NUMBER,-REG' 'NUMBER,+REG' 'NUMBER,REG-' 'NUMBER,REG+' 14159 14160 The number must be in the range '-8'..'+8' and must not be 0. The 14161 register can be either 'X', 'Y', 'SP' or 'PC'. 14162 14163"Accumulator Offset" 14164 'ACC,REG' 14165 14166 The accumulator register can be either 'A', 'B' or 'D'. The 14167 register can be either 'X', 'Y', 'SP' or 'PC'. 14168 14169"Accumulator D offset indexed-indirect" 14170 '[D,REG]' 14171 14172 The register can be either 'X', 'Y', 'SP' or 'PC'. 14173 14174 For example: 14175 14176 ldab 1024,sp 14177 ldd [10,x] 14178 orab 3,+x 14179 stab -2,y- 14180 ldx a,pc 14181 sty [d,sp] 14182 14183 14184File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 14185 141869.23.3 Symbolic Operand Modifiers 14187--------------------------------- 14188 14189The assembler supports several modifiers when using symbol addresses in 1419068HC11 and 68HC12 instruction operands. The general syntax is the 14191following: 14192 14193 %modifier(symbol) 14194 14195'%addr' 14196 This modifier indicates to the assembler and linker to use the 14197 16-bit physical address corresponding to the symbol. This is 14198 intended to be used on memory window systems to map a symbol in the 14199 memory bank window. If the symbol is in a memory expansion part, 14200 the physical address corresponds to the symbol address within the 14201 memory bank window. If the symbol is not in a memory expansion 14202 part, this is the symbol address (using or not using the %addr 14203 modifier has no effect in that case). 14204 14205'%page' 14206 This modifier indicates to use the memory page number corresponding 14207 to the symbol. If the symbol is in a memory expansion part, its 14208 page number is computed by the linker as a number used to map the 14209 page containing the symbol in the memory bank window. If the 14210 symbol is not in a memory expansion part, the page number is 0. 14211 14212'%hi' 14213 This modifier indicates to use the 8-bit high part of the physical 14214 address of the symbol. 14215 14216'%lo' 14217 This modifier indicates to use the 8-bit low part of the physical 14218 address of the symbol. 14219 14220 For example a 68HC12 call to a function 'foo_example' stored in 14221memory expansion part could be written as follows: 14222 14223 call %addr(foo_example),%page(foo_example) 14224 14225 and this is equivalent to 14226 14227 call foo_example 14228 14229 And for 68HC11 it could be written as follows: 14230 14231 ldab #%page(foo_example) 14232 stab _page_switch 14233 jsr %addr(foo_example) 14234 14235 14236File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 14237 142389.23.4 Assembler Directives 14239--------------------------- 14240 14241The 68HC11 and 68HC12 version of 'as' have the following specific 14242assembler directives: 14243 14244'.relax' 14245 The relax directive is used by the 'GNU Compiler' to emit a 14246 specific relocation to mark a group of instructions for linker 14247 relaxation. The sequence of instructions within the group must be 14248 known to the linker so that relaxation can be performed. 14249 14250'.mode [mshort|mlong|mshort-double|mlong-double]' 14251 This directive specifies the ABI. It overrides the '-mshort', 14252 '-mlong', '-mshort-double' and '-mlong-double' options. 14253 14254'.far SYMBOL' 14255 This directive marks the symbol as a 'far' symbol meaning that it 14256 uses a 'call/rtc' calling convention as opposed to 'jsr/rts'. 14257 During a final link, the linker will identify references to the 14258 'far' symbol and will verify the proper calling convention. 14259 14260'.interrupt SYMBOL' 14261 This directive marks the symbol as an interrupt entry point. This 14262 information is then used by the debugger to correctly unwind the 14263 frame across interrupts. 14264 14265'.xrefb SYMBOL' 14266 This directive is defined for compatibility with the 'Specification 14267 for Motorola 8 and 16-Bit Assembly Language Input Standard' and is 14268 ignored. 14269 14270 14271File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 14272 142739.23.5 Floating Point 14274--------------------- 14275 14276Packed decimal (P) format floating literals are not supported. Feel 14277free to add the code! 14278 14279 The floating point formats generated by directives are these. 14280 14281'.float' 14282 'Single' precision floating point constants. 14283 14284'.double' 14285 'Double' precision floating point constants. 14286 14287'.extend' 14288'.ldouble' 14289 'Extended' precision ('long double') floating point constants. 14290 14291 14292File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 14293 142949.23.6 Opcodes 14295-------------- 14296 14297* Menu: 14298 14299* M68HC11-Branch:: Branch Improvement 14300 14301 14302File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 14303 143049.23.6.1 Branch Improvement 14305........................... 14306 14307Certain pseudo opcodes are permitted for branch instructions. They 14308expand to the shortest branch instruction that reach the target. 14309Generally these mnemonics are made by prepending 'j' to the start of 14310Motorola mnemonic. These pseudo opcodes are not affected by the 14311'--short-branches' or '--force-long-branches' options. 14312 14313 The following table summarizes the pseudo-operations. 14314 14315 Displacement Width 14316 +-------------------------------------------------------------+ 14317 | Options | 14318 | --short-branches --force-long-branches | 14319 +--------------------------+----------------------------------+ 14320 Op |BYTE WORD | BYTE WORD | 14321 +--------------------------+----------------------------------+ 14322 bsr | bsr <pc-rel> <error> | jsr <abs> | 14323 bra | bra <pc-rel> <error> | jmp <abs> | 14324 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 14325 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 14326 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 14327 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 14328 | jmp <abs> | | 14329 +--------------------------+----------------------------------+ 14330 XX: condition 14331 NX: negative of condition XX 14332 14333 14334'jbsr' 14335'jbra' 14336 These are the simplest jump pseudo-operations; they always map to 14337 one particular machine instruction, depending on the displacement 14338 to the branch target. 14339 14340'jbXX' 14341 Here, 'jbXX' stands for an entire family of pseudo-operations, 14342 where XX is a conditional branch or condition-code test. The full 14343 list of pseudo-ops in this family is: 14344 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 14345 jbcs jbne jblt jble jbls jbvc jbmi 14346 14347 For the cases of non-PC relative displacements and long 14348 displacements, 'as' issues a longer code fragment in terms of NX, 14349 the opposite condition to XX. For example, for the non-PC relative 14350 case: 14351 jbXX foo 14352 gives 14353 bNXs oof 14354 jmp foo 14355 oof: 14356 14357 14358File: as.info, Node: S12Z-Dependent, Next: Meta-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 14359 143609.24 S12Z Dependent Features 14361============================ 14362 14363The Freescale S12Z version of 'as' has a few machine dependent features. 14364 14365* Menu: 14366 14367* S12Z Options:: S12Z Options 14368* S12Z Syntax:: Syntax 14369 14370 14371File: as.info, Node: S12Z Options, Next: S12Z Syntax, Up: S12Z-Dependent 14372 143739.24.1 S12Z Options 14374------------------- 14375 14376The S12Z version of 'as' recognizes the following options: 14377 14378'-mreg-prefix=PREFIX' 14379 You can use the '-mreg-prefix=PFX' option to indicate that the 14380 assembler should expect all register names to be prefixed with the 14381 string PFX. 14382 14383 For an explanation of what this means and why it might be needed, 14384 see *note S12Z Register Notation::. 14385 14386'-mdollar-hex' 14387 The '-mdollar-hex' option affects the way that literal hexadecimal 14388 constants are represented. When this option is specified, the 14389 assembler will consider the '$' character as the start of a 14390 hexadecimal integer constant. Without this option, the standard 14391 value of '0x' is expected. 14392 14393 If you use this option, then you cannot have symbol names starting 14394 with '$'. '-mdollar-hex' is implied if the '--traditional-format' 14395 (*note traditional-format::) is used. 14396 14397 14398File: as.info, Node: S12Z Syntax, Prev: S12Z Options, Up: S12Z-Dependent 14399 144009.24.2 Syntax 14401------------- 14402 14403* Menu: 14404 14405* S12Z Syntax Overview:: General description 14406* S12Z Addressing Modes:: Operands and their semantics 14407* S12Z Register Notation:: How to refer to registers 14408 14409 14410File: as.info, Node: S12Z Syntax Overview, Next: S12Z Addressing Modes, Up: S12Z Syntax 14411 144129.24.2.1 Overview 14413................. 14414 14415In the S12Z syntax, the instruction name comes first and it may be 14416followed by one, or by several operands. In most cases the maximum 14417number of operands is three. Operands are separated by a comma (','). 14418A comma however does not act as a separator if it appears within 14419parentheses ('()') or within square brackets ('[]'). 'as' will complain 14420if too many, too few or inappropriate operands are specified for a given 14421instruction. 14422 14423 Some instructions accept and (in certain situations require) a suffix 14424indicating the size of the operand. The suffix is separated from the 14425instruction name by a period ('.') and may be one of 'b', 'w', 'p' or 14426'l' indicating 'byte' (a single byte), 'word' (2 bytes), 'pointer' (3 14427bytes) or 'long' (4 bytes) respectively. 14428 14429 Example: 14430 14431 bset.b 0xA98, #5 14432 mov.b #6, 0x2409 14433 ld d0, #4 14434 mov.l (d0, x), 0x2409 14435 inc d0 14436 cmp d0, #12 14437 blt *-4 14438 lea x, 0x2409 14439 st y, (1, x) 14440 14441 The presence of a ';' character anywhere on a line indicates the 14442start of a comment that extends to the end of that line. 14443 14444 A '*' or a '#' character at the start of a line also introduces a 14445line comment, but these characters do not work elsewhere on the line. 14446If the first character of the line is a '#' then as well as starting a 14447comment, the line could also be logical line number directive (*note 14448Comments::) or a preprocessor control command (*note Preprocessing::). 14449 14450 The S12Z assembler does not currently support a line separator 14451character. 14452 14453 14454File: as.info, Node: S12Z Addressing Modes, Next: S12Z Register Notation, Prev: S12Z Syntax Overview, Up: S12Z Syntax 14455 144569.24.2.2 Addressing Modes 14457......................... 14458 14459The following addressing modes are understood for the S12Z. 14460"Immediate" 14461 '#NUMBER' 14462 14463"Immediate Bit Field" 14464 '#WIDTH:OFFSET' 14465 14466 Bit field instructions in the immediate mode require the width and 14467 offset to be specified. The WIDTH parameter specifies the number 14468 of bits in the field. It should be a number in the range [1,32]. 14469 OFFSET determines the position within the field where the operation 14470 should start. It should be a number in the range [0,31]. 14471 14472"Relative" 14473 '*SYMBOL', or '*[+-]DIGITS' 14474 14475 Program counter relative addresses have a width of 15 bits. Thus, 14476 they must be within the range [-32768, 32767]. 14477 14478"Register" 14479 'REG' 14480 14481 Some instructions accept a register as an operand. In general, REG 14482 may be a data register ('D0', 'D1' ... 'D7'), the 'X' register or 14483 the 'Y' register. 14484 14485 A few instructions accept as an argument the stack pointer register 14486 ('S'), and/or the program counter ('P'). 14487 14488 Some very special instructions accept arguments which refer to the 14489 condition code register. For these arguments the syntax is 'CCR', 14490 'CCH' or 'CCL' which refer to the complete condition code register, 14491 the condition code register high byte and the condition code 14492 register low byte respectively. 14493 14494"Absolute Direct" 14495 'SYMBOL', or 'DIGITS' 14496 14497"Absolute Indirect" 14498 '[SYMBOL', or 'DIGITS]' 14499 14500"Constant Offset Indexed" 14501 '(NUMBER,REG)' 14502 14503 REG may be either 'X', 'Y', 'S' or 'P' or one of the data registers 14504 'D0', 'D1' ... 'D7'. If any of the registers 'D2' ... 'D5' are 14505 specified, then the register value is treated as a signed value. 14506 Otherwise it is treated as unsigned. NUMBER may be any integer in 14507 the range [-8388608,8388607]. 14508 14509"Offset Indexed Indirect" 14510 '[NUMBER,REG]' 14511 14512 REG may be either 'X', 'Y', 'S' or 'P'. NUMBER may be any integer 14513 in the range [-8388608,8388607]. 14514 14515"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 14516 '-REG', '+REG', 'REG-' or 'REG+' 14517 14518 This addressing mode is typically used to access a value at an 14519 address, and simultaneously to increment/decrement the register 14520 pointing to that address. Thus REG may be any of the 24 bit 14521 registers 'X', 'Y', or 'S'. Pre-increment and post-decrement are 14522 not available for register 'S' (only post-increment and 14523 pre-decrement are available). 14524 14525"Register Offset Direct" 14526 '(DATA-REG,REG)' 14527 14528 REG can be either 'X', 'Y', or 'S'. DATA-REG must be one of the 14529 data registers 'D0', 'D1' ... 'D7'. If any of the registers 'D2' 14530 ... 'D5' are specified, then the register value is treated as a 14531 signed value. Otherwise it is treated as unsigned. 14532 14533"Register Offset Indirect" 14534 '[DATA-REG,REG]' 14535 14536 REG can be either 'X' or 'Y'. DATA-REG must be one of the data 14537 registers 'D0', 'D1' ... 'D7'. If any of the registers 'D2' ... 14538 'D5' are specified, then the register value is treated as a signed 14539 value. Otherwise it is treated as unsigned. 14540 14541 For example: 14542 14543 trap #197 ;; Immediate mode 14544 bra *+49 ;; Relative mode 14545 bra .L0 ;; ditto 14546 jmp 0xFE0034 ;; Absolute direct mode 14547 jmp [0xFD0012] ;; Absolute indirect mode 14548 inc.b (4,x) ;; Constant offset indexed mode 14549 jsr (45, d0) ;; ditto 14550 dec.w [4,y] ;; Constant offset indexed indirect mode 14551 clr.p (-s) ;; Pre-decrement mode 14552 neg.l (d0, s) ;; Register offset direct mode 14553 com.b [d1, x] ;; Register offset indirect mode 14554 psh cch ;; Register mode 14555 14556 14557File: as.info, Node: S12Z Register Notation, Prev: S12Z Addressing Modes, Up: S12Z Syntax 14558 145599.24.2.3 Register Notation 14560.......................... 14561 14562Without a register prefix (*note S12Z Options::), S12Z assembler code is 14563expected in the traditional format like this: 14564 lea s, (-2,s) 14565 st d2, (0,s) 14566 ld x, symbol 14567 tfr d2, d6 14568 cmp d6, #1532 14569 14570However, if 'as' is started with (for example) '-mreg-prefix=%' then all 14571register names must be prefixed with '%' as follows: 14572 lea %s, (-2,%s) 14573 st %d2, (0,%s) 14574 ld %x, symbol 14575 tfr %d2, %d6 14576 cmp %d6, #1532 14577 14578 The register prefix feature is intended to be used by compilers to 14579avoid ambiguity between symbols and register names. Consider the 14580following assembler instruction: 14581 st d0, d1 14582The destination operand of this instruction could either refer to the 14583register 'D1', or it could refer to the symbol named "d1". If the 14584latter is intended then 'as' must be invoked with '-mreg-prefix=PFX' and 14585the code written as 14586 st PFXd0, d1 14587where PFX is the chosen register prefix. For this reason, compiler 14588back-ends should choose a register prefix which cannot be confused with 14589a symbol name. 14590 14591 14592File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: S12Z-Dependent, Up: Machine Dependencies 14593 145949.25 Meta Dependent Features 14595============================ 14596 14597* Menu: 14598 14599* Meta Options:: Options 14600* Meta Syntax:: Meta Assembler Syntax 14601 14602 14603File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent 14604 146059.25.1 Options 14606-------------- 14607 14608The Imagination Technologies Meta architecture is implemented in a 14609number of versions, with each new version adding new features such as 14610instructions and registers. For precise details of what instructions 14611each core supports, please see the chip's technical reference manual. 14612 14613 The following table lists all available Meta options. 14614 14615'-mcpu=metac11' 14616 Generate code for Meta 1.1. 14617 14618'-mcpu=metac12' 14619 Generate code for Meta 1.2. 14620 14621'-mcpu=metac21' 14622 Generate code for Meta 2.1. 14623 14624'-mfpu=metac21' 14625 Allow code to use FPU hardware of Meta 2.1. 14626 14627 14628File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent 14629 146309.25.2 Syntax 14631------------- 14632 14633* Menu: 14634 14635* Meta-Chars:: Special Characters 14636* Meta-Regs:: Register Names 14637 14638 14639File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax 14640 146419.25.2.1 Special Characters 14642........................... 14643 14644'!' is the line comment character. 14645 14646 You can use ';' instead of a newline to separate statements. 14647 14648 Since '$' has no special meaning, you may use it in symbol names. 14649 14650 14651File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax 14652 146539.25.2.2 Register Names 14654....................... 14655 14656Registers can be specified either using their mnemonic names, such as 14657'D0Re0', or using the unit plus register number separated by a '.', such 14658as 'D0.0'. 14659 14660 14661File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies 14662 146639.26 MicroBlaze Dependent Features 14664================================== 14665 14666The Xilinx MicroBlaze processor family includes several variants, all 14667using the same core instruction set. This chapter covers features of 14668the GNU assembler that are specific to the MicroBlaze architecture. For 14669details about the MicroBlaze instruction set, please see the 'MicroBlaze 14670Processor Reference Guide (UG081)' available at www.xilinx.com. 14671 14672* Menu: 14673 14674* MicroBlaze Directives:: Directives for MicroBlaze Processors. 14675* MicroBlaze Syntax:: Syntax for the MicroBlaze 14676 14677 14678File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent 14679 146809.26.1 Directives 14681----------------- 14682 14683A number of assembler directives are available for MicroBlaze. 14684 14685'.data8 EXPRESSION,...' 14686 This directive is an alias for '.byte'. Each expression is 14687 assembled into an eight-bit value. 14688 14689'.data16 EXPRESSION,...' 14690 This directive is an alias for '.hword'. Each expression is 14691 assembled into an 16-bit value. 14692 14693'.data32 EXPRESSION,...' 14694 This directive is an alias for '.word'. Each expression is 14695 assembled into an 32-bit value. 14696 14697'.ent NAME[,LABEL]' 14698 This directive is an alias for '.func' denoting the start of 14699 function NAME at (optional) LABEL. 14700 14701'.end NAME[,LABEL]' 14702 This directive is an alias for '.endfunc' denoting the end of 14703 function NAME. 14704 14705'.gpword LABEL,...' 14706 This directive is an alias for '.rva'. The resolved address of 14707 LABEL is stored in the data section. 14708 14709'.weakext LABEL' 14710 Declare that LABEL is a weak external symbol. 14711 14712'.rodata' 14713 Switch to .rodata section. Equivalent to '.section .rodata' 14714 14715'.sdata2' 14716 Switch to .sdata2 section. Equivalent to '.section .sdata2' 14717 14718'.sdata' 14719 Switch to .sdata section. Equivalent to '.section .sdata' 14720 14721'.bss' 14722 Switch to .bss section. Equivalent to '.section .bss' 14723 14724'.sbss' 14725 Switch to .sbss section. Equivalent to '.section .sbss' 14726 14727 14728File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent 14729 147309.26.2 Syntax for the MicroBlaze 14731-------------------------------- 14732 14733* Menu: 14734 14735* MicroBlaze-Chars:: Special Characters 14736 14737 14738File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax 14739 147409.26.2.1 Special Characters 14741........................... 14742 14743The presence of a '#' on a line indicates the start of a comment that 14744extends to the end of the current line. 14745 14746 If a '#' appears as the first character of a line, the whole line is 14747treated as a comment, but in this case the line can also be a logical 14748line number directive (*note Comments::) or a preprocessor control 14749command (*note Preprocessing::). 14750 14751 The ';' character can be used to separate statements on the same 14752line. 14753 14754 14755File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 14756 147579.27 MIPS Dependent Features 14758============================ 14759 14760GNU 'as' for MIPS architectures supports several different MIPS 14761processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 14762information about the MIPS instruction set, see 'MIPS RISC 14763Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 14764of MIPS assembly conventions, see "Appendix D: Assembly Language 14765Programming" in the same work. 14766 14767* Menu: 14768 14769* MIPS Options:: Assembler options 14770* MIPS Macros:: High-level assembly macros 14771* MIPS Symbol Sizes:: Directives to override the size of symbols 14772* MIPS Small Data:: Controlling the use of small data accesses 14773* MIPS ISA:: Directives to override the ISA level 14774* MIPS assembly options:: Directives to control code generation 14775* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 14776* MIPS insn:: Directive to mark data as an instruction 14777* MIPS FP ABIs:: Marking which FP ABI is in use 14778* MIPS NaN Encodings:: Directives to record which NaN encoding is being used 14779* MIPS Option Stack:: Directives to save and restore options 14780* MIPS ASE Instruction Generation Overrides:: Directives to control 14781 generation of MIPS ASE instructions 14782* MIPS Floating-Point:: Directives to override floating-point options 14783* MIPS Syntax:: MIPS specific syntactical considerations 14784 14785 14786File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent 14787 147889.27.1 Assembler options 14789------------------------ 14790 14791The MIPS configurations of GNU 'as' support these special options: 14792 14793'-G NUM' 14794 Set the "small data" limit to N bytes. The default limit is 8 14795 bytes. *Note Controlling the use of small data accesses: MIPS 14796 Small Data. 14797 14798'-EB' 14799'-EL' 14800 Any MIPS configuration of 'as' can select big-endian or 14801 little-endian output at run time (unlike the other GNU development 14802 tools, which must be configured for one or the other). Use '-EB' 14803 to select big-endian output, and '-EL' for little-endian. 14804 14805'-KPIC' 14806 Generate SVR4-style PIC. This option tells the assembler to 14807 generate SVR4-style position-independent macro expansions. It also 14808 tells the assembler to mark the output file as PIC. 14809 14810'-mvxworks-pic' 14811 Generate VxWorks PIC. This option tells the assembler to generate 14812 VxWorks-style position-independent macro expansions. 14813 14814'-mips1' 14815'-mips2' 14816'-mips3' 14817'-mips4' 14818'-mips5' 14819'-mips32' 14820'-mips32r2' 14821'-mips32r3' 14822'-mips32r5' 14823'-mips32r6' 14824'-mips64' 14825'-mips64r2' 14826'-mips64r3' 14827'-mips64r5' 14828'-mips64r6' 14829 Generate code for a particular MIPS Instruction Set Architecture 14830 level. '-mips1' corresponds to the R2000 and R3000 processors, 14831 '-mips2' to the R6000 processor, '-mips3' to the R4000 processor, 14832 and '-mips4' to the R8000 and R10000 processors. '-mips5', 14833 '-mips32', '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6', 14834 '-mips64', '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6' 14835 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 14836 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 14837 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 14838 ISA processors, respectively. You can also switch instruction sets 14839 during the assembly; see *note Directives to override the ISA 14840 level: MIPS ISA. 14841 14842'-mgp32' 14843'-mfp32' 14844 Some macros have different expansions for 32-bit and 64-bit 14845 registers. The register sizes are normally inferred from the ISA 14846 and ABI, but these flags force a certain group of registers to be 14847 treated as 32 bits wide at all times. '-mgp32' controls the size 14848 of general-purpose registers and '-mfp32' controls the size of 14849 floating-point registers. 14850 14851 The '.set gp=32' and '.set fp=32' directives allow the size of 14852 registers to be changed for parts of an object. The default value 14853 is restored by '.set gp=default' and '.set fp=default'. 14854 14855 On some MIPS variants there is a 32-bit mode flag; when this flag 14856 is set, 64-bit instructions generate a trap. Also, some 32-bit 14857 OSes only save the 32-bit registers on a context switch, so it is 14858 essential never to use the 64-bit registers. 14859 14860'-mgp64' 14861'-mfp64' 14862 Assume that 64-bit registers are available. This is provided in 14863 the interests of symmetry with '-mgp32' and '-mfp32'. 14864 14865 The '.set gp=64' and '.set fp=64' directives allow the size of 14866 registers to be changed for parts of an object. The default value 14867 is restored by '.set gp=default' and '.set fp=default'. 14868 14869'-mfpxx' 14870 Make no assumptions about whether 32-bit or 64-bit floating-point 14871 registers are available. This is provided to support having 14872 modules compatible with either '-mfp32' or '-mfp64'. This option 14873 can only be used with MIPS II and above. 14874 14875 The '.set fp=xx' directive allows a part of an object to be marked 14876 as not making assumptions about 32-bit or 64-bit FP registers. The 14877 default value is restored by '.set fp=default'. 14878 14879'-modd-spreg' 14880'-mno-odd-spreg' 14881 Enable use of floating-point operations on odd-numbered 14882 single-precision registers when supported by the ISA. '-mfpxx' 14883 implies '-mno-odd-spreg', otherwise the default is '-modd-spreg' 14884 14885'-mips16' 14886'-no-mips16' 14887 Generate code for the MIPS 16 processor. This is equivalent to 14888 putting '.module mips16' at the start of the assembly file. 14889 '-no-mips16' turns off this option. 14890 14891'-mmips16e2' 14892'-mno-mips16e2' 14893 Enable the use of MIPS16e2 instructions in MIPS16 mode. This is 14894 equivalent to putting '.module mips16e2' at the start of the 14895 assembly file. '-mno-mips16e2' turns off this option. 14896 14897'-mmicromips' 14898'-mno-micromips' 14899 Generate code for the microMIPS processor. This is equivalent to 14900 putting '.module micromips' at the start of the assembly file. 14901 '-mno-micromips' turns off this option. This is equivalent to 14902 putting '.module nomicromips' at the start of the assembly file. 14903 14904'-msmartmips' 14905'-mno-smartmips' 14906 Enables the SmartMIPS extensions to the MIPS32 instruction set, 14907 which provides a number of new instructions which target smartcard 14908 and cryptographic applications. This is equivalent to putting 14909 '.module smartmips' at the start of the assembly file. 14910 '-mno-smartmips' turns off this option. 14911 14912'-mips3d' 14913'-no-mips3d' 14914 Generate code for the MIPS-3D Application Specific Extension. This 14915 tells the assembler to accept MIPS-3D instructions. '-no-mips3d' 14916 turns off this option. 14917 14918'-mdmx' 14919'-no-mdmx' 14920 Generate code for the MDMX Application Specific Extension. This 14921 tells the assembler to accept MDMX instructions. '-no-mdmx' turns 14922 off this option. 14923 14924'-mdsp' 14925'-mno-dsp' 14926 Generate code for the DSP Release 1 Application Specific Extension. 14927 This tells the assembler to accept DSP Release 1 instructions. 14928 '-mno-dsp' turns off this option. 14929 14930'-mdspr2' 14931'-mno-dspr2' 14932 Generate code for the DSP Release 2 Application Specific Extension. 14933 This option implies '-mdsp'. This tells the assembler to accept 14934 DSP Release 2 instructions. '-mno-dspr2' turns off this option. 14935 14936'-mdspr3' 14937'-mno-dspr3' 14938 Generate code for the DSP Release 3 Application Specific Extension. 14939 This option implies '-mdsp' and '-mdspr2'. This tells the 14940 assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns 14941 off this option. 14942 14943'-mmt' 14944'-mno-mt' 14945 Generate code for the MT Application Specific Extension. This 14946 tells the assembler to accept MT instructions. '-mno-mt' turns off 14947 this option. 14948 14949'-mmcu' 14950'-mno-mcu' 14951 Generate code for the MCU Application Specific Extension. This 14952 tells the assembler to accept MCU instructions. '-mno-mcu' turns 14953 off this option. 14954 14955'-mmsa' 14956'-mno-msa' 14957 Generate code for the MIPS SIMD Architecture Extension. This tells 14958 the assembler to accept MSA instructions. '-mno-msa' turns off 14959 this option. 14960 14961'-mxpa' 14962'-mno-xpa' 14963 Generate code for the MIPS eXtended Physical Address (XPA) 14964 Extension. This tells the assembler to accept XPA instructions. 14965 '-mno-xpa' turns off this option. 14966 14967'-mvirt' 14968'-mno-virt' 14969 Generate code for the Virtualization Application Specific 14970 Extension. This tells the assembler to accept Virtualization 14971 instructions. '-mno-virt' turns off this option. 14972 14973'-mcrc' 14974'-mno-crc' 14975 Generate code for the cyclic redundancy check (CRC) Application 14976 Specific Extension. This tells the assembler to accept CRC 14977 instructions. '-mno-crc' turns off this option. 14978 14979'-mginv' 14980'-mno-ginv' 14981 Generate code for the Global INValidate (GINV) Application Specific 14982 Extension. This tells the assembler to accept GINV instructions. 14983 '-mno-ginv' turns off this option. 14984 14985'-mloongson-mmi' 14986'-mno-loongson-mmi' 14987 Generate code for the Loongson MultiMedia extensions Instructions 14988 (MMI) Application Specific Extension. This tells the assembler to 14989 accept MMI instructions. '-mno-loongson-mmi' turns off this 14990 option. 14991 14992'-mloongson-cam' 14993'-mno-loongson-cam' 14994 Generate code for the Loongson Content Address Memory (CAM) 14995 Application Specific Extension. This tells the assembler to accept 14996 CAM instructions. '-mno-loongson-cam' turns off this option. 14997 14998'-mloongson-ext' 14999'-mno-loongson-ext' 15000 Generate code for the Loongson EXTensions (EXT) instructions 15001 Application Specific Extension. This tells the assembler to accept 15002 EXT instructions. '-mno-loongson-ext' turns off this option. 15003 15004'-mloongson-ext2' 15005'-mno-loongson-ext2' 15006 Generate code for the Loongson EXTensions R2 (EXT2) instructions 15007 Application Specific Extension. This tells the assembler to accept 15008 EXT2 instructions. '-mno-loongson-ext2' turns off this option. 15009 15010'-minsn32' 15011'-mno-insn32' 15012 Only use 32-bit instruction encodings when generating code for the 15013 microMIPS processor. This option inhibits the use of any 16-bit 15014 instructions. This is equivalent to putting '.set insn32' at the 15015 start of the assembly file. '-mno-insn32' turns off this option. 15016 This is equivalent to putting '.set noinsn32' at the start of the 15017 assembly file. By default '-mno-insn32' is selected, allowing all 15018 instructions to be used. 15019 15020'-mfix7000' 15021'-mno-fix7000' 15022 Cause nops to be inserted if the read of the destination register 15023 of an mfhi or mflo instruction occurs in the following two 15024 instructions. 15025 15026'-mfix-rm7000' 15027'-mno-fix-rm7000' 15028 Cause nops to be inserted if a dmult or dmultu instruction is 15029 followed by a load instruction. 15030 15031'-mfix-loongson2f-jump' 15032'-mno-fix-loongson2f-jump' 15033 Eliminate instruction fetch from outside 256M region to work around 15034 the Loongson2F 'jump' instructions. Without it, under extreme 15035 cases, the kernel may crash. The issue has been solved in latest 15036 processor batches, but this fix has no side effect to them. 15037 15038'-mfix-loongson2f-nop' 15039'-mno-fix-loongson2f-nop' 15040 Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop' 15041 errata. Without it, under extreme cases, the CPU might deadlock. 15042 The issue has been solved in later Loongson2F batches, but this fix 15043 has no side effect to them. 15044 15045'-mfix-loongson3-llsc' 15046'-mno-fix-loongson3-llsc' 15047 Insert 'sync' before 'll' and 'lld' to work around Loongson3 LLSC 15048 errata. Without it, under extrame cases, the CPU might deadlock. 15049 The default can be controlled by the 15050 '--enable-mips-fix-loongson3-llsc=[yes|no]' configure option. 15051 15052'-mfix-vr4120' 15053'-mno-fix-vr4120' 15054 Insert nops to work around certain VR4120 errata. This option is 15055 intended to be used on GCC-generated code: it is not designed to 15056 catch all problems in hand-written assembler code. 15057 15058'-mfix-vr4130' 15059'-mno-fix-vr4130' 15060 Insert nops to work around the VR4130 'mflo'/'mfhi' errata. 15061 15062'-mfix-24k' 15063'-mno-fix-24k' 15064 Insert nops to work around the 24K 'eret'/'deret' errata. 15065 15066'-mfix-cn63xxp1' 15067'-mno-fix-cn63xxp1' 15068 Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around 15069 certain CN63XXP1 errata. 15070 15071'-mfix-r5900' 15072'-mno-fix-r5900' 15073 Do not attempt to schedule the preceding instruction into the delay 15074 slot of a branch instruction placed at the end of a short loop of 15075 six instructions or fewer and always schedule a 'nop' instruction 15076 there instead. The short loop bug under certain conditions causes 15077 loops to execute only once or twice, due to a hardware bug in the 15078 R5900 chip. 15079 15080'-m4010' 15081'-no-m4010' 15082 Generate code for the LSI R4010 chip. This tells the assembler to 15083 accept the R4010-specific instructions ('addciu', 'ffc', etc.), and 15084 to not schedule 'nop' instructions around accesses to the 'HI' and 15085 'LO' registers. '-no-m4010' turns off this option. 15086 15087'-m4650' 15088'-no-m4650' 15089 Generate code for the MIPS R4650 chip. This tells the assembler to 15090 accept the 'mad' and 'madu' instruction, and to not schedule 'nop' 15091 instructions around accesses to the 'HI' and 'LO' registers. 15092 '-no-m4650' turns off this option. 15093 15094'-m3900' 15095'-no-m3900' 15096'-m4100' 15097'-no-m4100' 15098 For each option '-mNNNN', generate code for the MIPS RNNNN chip. 15099 This tells the assembler to accept instructions specific to that 15100 chip, and to schedule for that chip's hazards. 15101 15102'-march=CPU' 15103 Generate code for a particular MIPS CPU. It is exactly equivalent 15104 to '-mCPU', except that there are more value of CPU understood. 15105 Valid CPU value are: 15106 15107 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 15108 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 15109 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 15110 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 15111 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 15112 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 15113 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 15114 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 15115 interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf, 15116 20kc, 25kf, sb1, sb1a, i6400, i6500, p6600, loongson2e, 15117 loongson2f, gs464, gs464e, gs264e, octeon, octeon+, octeon2, 15118 octeon3, xlr, xlp 15119 15120 For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms 15121 for 'Nf1_1'. These values are deprecated. 15122 15123'-mtune=CPU' 15124 Schedule and tune for a particular MIPS CPU. Valid CPU values are 15125 identical to '-march=CPU'. 15126 15127'-mabi=ABI' 15128 Record which ABI the source code uses. The recognized arguments 15129 are: '32', 'n32', 'o64', '64' and 'eabi'. 15130 15131'-msym32' 15132'-mno-sym32' 15133 Equivalent to adding '.set sym32' or '.set nosym32' to the 15134 beginning of the assembler input. *Note MIPS Symbol Sizes::. 15135 15136'-nocpp' 15137 This option is ignored. It is accepted for command-line 15138 compatibility with other assemblers, which use it to turn off C 15139 style preprocessing. With GNU 'as', there is no need for '-nocpp', 15140 because the GNU assembler itself never runs the C preprocessor. 15141 15142'-msoft-float' 15143'-mhard-float' 15144 Disable or enable floating-point instructions. Note that by 15145 default floating-point instructions are always allowed even with 15146 CPU targets that don't have support for these instructions. 15147 15148'-msingle-float' 15149'-mdouble-float' 15150 Disable or enable double-precision floating-point operations. Note 15151 that by default double-precision floating-point operations are 15152 always allowed even with CPU targets that don't have support for 15153 these operations. 15154 15155'--construct-floats' 15156'--no-construct-floats' 15157 The '--no-construct-floats' option disables the construction of 15158 double width floating point constants by loading the two halves of 15159 the value into the two single width floating point registers that 15160 make up the double width register. This feature is useful if the 15161 processor support the FR bit in its status register, and this bit 15162 is known (by the programmer) to be set. This bit prevents the 15163 aliasing of the double width register by the single width 15164 registers. 15165 15166 By default '--construct-floats' is selected, allowing construction 15167 of these floating point constants. 15168 15169'--relax-branch' 15170'--no-relax-branch' 15171 The '--relax-branch' option enables the relaxation of out-of-range 15172 branches. Any branches whose target cannot be reached directly are 15173 converted to a small instruction sequence including an 15174 inverse-condition branch to the physically next instruction, and a 15175 jump to the original target is inserted between the two 15176 instructions. In PIC code the jump will involve further 15177 instructions for address calculation. 15178 15179 The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and 15180 'BPOSGE64' instructions are excluded from relaxation, because they 15181 have no complementing counterparts. They could be relaxed with the 15182 use of a longer sequence involving another branch, however this has 15183 not been implemented and if their target turns out of reach, they 15184 produce an error even if branch relaxation is enabled. 15185 15186 Also no MIPS16 branches are ever relaxed. 15187 15188 By default '--no-relax-branch' is selected, causing any 15189 out-of-range branches to produce an error. 15190 15191'-mignore-branch-isa' 15192'-mno-ignore-branch-isa' 15193 Ignore branch checks for invalid transitions between ISA modes. 15194 15195 The semantics of branches does not provide for an ISA mode switch, 15196 so in most cases the ISA mode a branch has been encoded for has to 15197 be the same as the ISA mode of the branch's target label. If the 15198 ISA modes do not match, then such a branch, if taken, will cause 15199 the ISA mode to remain unchanged and instructions that follow will 15200 be executed in the wrong ISA mode causing the program to misbehave 15201 or crash. 15202 15203 In the case of the 'BAL' instruction it may be possible to relax it 15204 to an equivalent 'JALX' instruction so that the ISA mode is 15205 switched at the run time as required. For other branches no 15206 relaxation is possible and therefore GAS has checks implemented 15207 that verify in branch assembly that the two ISA modes match, and 15208 report an error otherwise so that the problem with code can be 15209 diagnosed at the assembly time rather than at the run time. 15210 15211 However some assembly code, including generated code produced by 15212 some versions of GCC, may incorrectly include branches to data 15213 labels, which appear to require a mode switch but are either dead 15214 or immediately followed by valid instructions encoded for the same 15215 ISA the branch has been encoded for. While not strictly correct at 15216 the source level such code will execute as intended, so to help 15217 with these cases '-mignore-branch-isa' is supported which disables 15218 ISA mode checks for branches. 15219 15220 By default '-mno-ignore-branch-isa' is selected, causing any 15221 invalid branch requiring a transition between ISA modes to produce 15222 an error. 15223 15224'-mnan=ENCODING' 15225 This option indicates whether the source code uses the IEEE 2008 15226 NaN encoding ('-mnan=2008') or the original MIPS encoding 15227 ('-mnan=legacy'). It is equivalent to adding a '.nan' directive to 15228 the beginning of the source file. *Note MIPS NaN Encodings::. 15229 15230 '-mnan=legacy' is the default if no '-mnan' option or '.nan' 15231 directive is used. 15232 15233'--trap' 15234'--no-break' 15235 'as' automatically macro expands certain division and 15236 multiplication instructions to check for overflow and division by 15237 zero. This option causes 'as' to generate code to take a trap 15238 exception rather than a break exception when an error is detected. 15239 The trap instructions are only supported at Instruction Set 15240 Architecture level 2 and higher. 15241 15242'--break' 15243'--no-trap' 15244 Generate code to take a break exception rather than a trap 15245 exception when an error is detected. This is the default. 15246 15247'-mpdr' 15248'-mno-pdr' 15249 Control generation of '.pdr' sections. Off by default on IRIX, on 15250 elsewhere. 15251 15252'-mshared' 15253'-mno-shared' 15254 When generating code using the Unix calling conventions (selected 15255 by '-KPIC' or '-mcall_shared'), gas will normally generate code 15256 which can go into a shared library. The '-mno-shared' option tells 15257 gas to generate code which uses the calling convention, but can not 15258 go into a shared library. The resulting code is slightly more 15259 efficient. This option only affects the handling of the '.cpload' 15260 and '.cpsetup' pseudo-ops. 15261 15262 15263File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent 15264 152659.27.2 High-level assembly macros 15266--------------------------------- 15267 15268MIPS assemblers have traditionally provided a wider range of 15269instructions than the MIPS architecture itself. These extra 15270instructions are usually referred to as "macro" instructions (1). 15271 15272 Some MIPS macro instructions extend an underlying architectural 15273instruction while others are entirely new. An example of the former 15274type is 'and', which allows the third operand to be either a register or 15275an arbitrary immediate value. Examples of the latter type include 15276'bgt', which branches to the third operand when the first operand is 15277greater than the second operand, and 'ulh', which implements an 15278unaligned 2-byte load. 15279 15280 One of the most common extensions provided by macros is to expand 15281memory offsets to the full address range (32 or 64 bits) and to allow 15282symbolic offsets such as 'my_data + 4' to be used in place of integer 15283constants. For example, the architectural instruction 'lbu' allows only 15284a signed 16-bit offset, whereas the macro 'lbu' allows code such as 'lbu 15285$4,array+32769($5)'. The implementation of these symbolic offsets 15286depends on several factors, such as whether the assembler is generating 15287SVR4-style PIC (selected by '-KPIC', *note Assembler options: MIPS 15288Options.), the size of symbols (*note Directives to override the size of 15289symbols: MIPS Symbol Sizes.), and the small data limit (*note 15290Controlling the use of small data accesses: MIPS Small Data.). 15291 15292 Sometimes it is undesirable to have one assembly instruction expand 15293to several machine instructions. The directive '.set nomacro' tells the 15294assembler to warn when this happens. '.set macro' restores the default 15295behavior. 15296 15297 Some macro instructions need a temporary register to store 15298intermediate results. This register is usually '$1', also known as 15299'$at', but it can be changed to any core register REG using '.set 15300at=REG'. Note that '$at' always refers to '$1' regardless of which 15301register is being used as the temporary register. 15302 15303 Implicit uses of the temporary register in macros could interfere 15304with explicit uses in the assembly code. The assembler therefore warns 15305whenever it sees an explicit use of the temporary register. The 15306directive '.set noat' silences this warning while '.set at' restores the 15307default behavior. It is safe to use '.set noat' while '.set nomacro' is 15308in effect since single-instruction macros never need a temporary 15309register. 15310 15311 Note that while the GNU assembler provides these macros for 15312compatibility, it does not make any attempt to optimize them with the 15313surrounding code. 15314 15315 ---------- Footnotes ---------- 15316 15317 (1) The term "macro" is somewhat overloaded here, since these macros 15318have no relation to those defined by '.macro', *note '.macro': Macro. 15319 15320 15321File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent 15322 153239.27.3 Directives to override the size of symbols 15324------------------------------------------------- 15325 15326The n64 ABI allows symbols to have any 64-bit value. Although this 15327provides a great deal of flexibility, it means that some macros have 15328much longer expansions than their 32-bit counterparts. For example, the 15329non-PIC expansion of 'dla $4,sym' is usually: 15330 15331 lui $4,%highest(sym) 15332 lui $1,%hi(sym) 15333 daddiu $4,$4,%higher(sym) 15334 daddiu $1,$1,%lo(sym) 15335 dsll32 $4,$4,0 15336 daddu $4,$4,$1 15337 15338 whereas the 32-bit expansion is simply: 15339 15340 lui $4,%hi(sym) 15341 daddiu $4,$4,%lo(sym) 15342 15343 n64 code is sometimes constructed in such a way that all symbolic 15344constants are known to have 32-bit values, and in such cases, it's 15345preferable to use the 32-bit expansion instead of the 64-bit expansion. 15346 15347 You can use the '.set sym32' directive to tell the assembler that, 15348from this point on, all expressions of the form 'SYMBOL' or 'SYMBOL + 15349OFFSET' have 32-bit values. For example: 15350 15351 .set sym32 15352 dla $4,sym 15353 lw $4,sym+16 15354 sw $4,sym+0x8000($4) 15355 15356 will cause the assembler to treat 'sym', 'sym+16' and 'sym+0x8000' as 1535732-bit values. The handling of non-symbolic addresses is not affected. 15358 15359 The directive '.set nosym32' ends a '.set sym32' block and reverts to 15360the normal behavior. It is also possible to change the symbol size 15361using the command-line options '-msym32' and '-mno-sym32'. 15362 15363 These options and directives are always accepted, but at present, 15364they have no effect for anything other than n64. 15365 15366 15367File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent 15368 153699.27.4 Controlling the use of small data accesses 15370------------------------------------------------- 15371 15372It often takes several instructions to load the address of a symbol. 15373For example, when 'addr' is a 32-bit symbol, the non-PIC expansion of 15374'dla $4,addr' is usually: 15375 15376 lui $4,%hi(addr) 15377 daddiu $4,$4,%lo(addr) 15378 15379 The sequence is much longer when 'addr' is a 64-bit symbol. *Note 15380Directives to override the size of symbols: MIPS Symbol Sizes. 15381 15382 In order to cut down on this overhead, most embedded MIPS systems set 15383aside a 64-kilobyte "small data" area and guarantee that all data of 15384size N and smaller will be placed in that area. The limit N is passed 15385to both the assembler and the linker using the command-line option '-G 15386N', *note Assembler options: MIPS Options. Note that the same value of 15387N must be used when linking and when assembling all input files to the 15388link; any inconsistency could cause a relocation overflow error. 15389 15390 The size of an object in the '.bss' section is set by the '.comm' or 15391'.lcomm' directive that defines it. The size of an external object may 15392be set with the '.extern' directive. For example, '.extern sym,4' 15393declares that the object at 'sym' is 4 bytes in length, while leaving 15394'sym' otherwise undefined. 15395 15396 When no '-G' option is given, the default limit is 8 bytes. The 15397option '-G 0' prevents any data from being automatically classified as 15398small. 15399 15400 It is also possible to mark specific objects as small by putting them 15401in the special sections '.sdata' and '.sbss', which are "small" 15402counterparts of '.data' and '.bss' respectively. The toolchain will 15403treat such data as small regardless of the '-G' setting. 15404 15405 On startup, systems that support a small data area are expected to 15406initialize register '$28', also known as '$gp', in such a way that small 15407data can be accessed using a 16-bit offset from that register. For 15408example, when 'addr' is small data, the 'dla $4,addr' instruction above 15409is equivalent to: 15410 15411 daddiu $4,$28,%gp_rel(addr) 15412 15413 Small data is not supported for SVR4-style PIC. 15414 15415 15416File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent 15417 154189.27.5 Directives to override the ISA level 15419------------------------------------------- 15420 15421GNU 'as' supports an additional directive to change the MIPS Instruction 15422Set Architecture level on the fly: '.set mipsN'. N should be a number 15423from 0 to 5, or 32, 32r2, 32r3, 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 1542464r6. The values other than 0 make the assembler accept instructions 15425for the corresponding ISA level, from that point on in the assembly. 15426'.set mipsN' affects not only which instructions are permitted, but also 15427how certain macros are expanded. '.set mips0' restores the ISA level to 15428its original level: either the level you selected with command-line 15429options, or the default for your configuration. You can use this 15430feature to permit specific MIPS III instructions while assembling in 32 15431bit mode. Use this directive with care! 15432 15433 The '.set arch=CPU' directive provides even finer control. It 15434changes the effective CPU target and allows the assembler to use 15435instructions specific to a particular CPU. All CPUs supported by the 15436'-march' command-line option are also selectable by this directive. The 15437original value is restored by '.set arch=default'. 15438 15439 The directive '.set mips16' puts the assembler into MIPS 16 mode, in 15440which it will assemble instructions for the MIPS 16 processor. Use 15441'.set nomips16' to return to normal 32 bit mode. 15442 15443 Traditional MIPS assemblers do not support this directive. 15444 15445 The directive '.set micromips' puts the assembler into microMIPS 15446mode, in which it will assemble instructions for the microMIPS 15447processor. Use '.set nomicromips' to return to normal 32 bit mode. 15448 15449 Traditional MIPS assemblers do not support this directive. 15450 15451 15452File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 15453 154549.27.6 Directives to control code generation 15455-------------------------------------------- 15456 15457The '.module' directive allows command-line options to be set directly 15458from assembly. The format of the directive matches the '.set' directive 15459but only those options which are relevant to a whole module are 15460supported. The effect of a '.module' directive is the same as the 15461corresponding command-line option. Where '.set' directives support 15462returning to a default then the '.module' directives do not as they 15463define the defaults. 15464 15465 These module-level directives must appear first in assembly. 15466 15467 Traditional MIPS assemblers do not support this directive. 15468 15469 The directive '.set insn32' makes the assembler only use 32-bit 15470instruction encodings when generating code for the microMIPS processor. 15471This directive inhibits the use of any 16-bit instructions from that 15472point on in the assembly. The '.set noinsn32' directive allows 16-bit 15473instructions to be accepted. 15474 15475 Traditional MIPS assemblers do not support this directive. 15476 15477 15478File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent 15479 154809.27.7 Directives for extending MIPS 16 bit instructions 15481-------------------------------------------------------- 15482 15483By default, MIPS 16 instructions are automatically extended to 32 bits 15484when necessary. The directive '.set noautoextend' will turn this off. 15485When '.set noautoextend' is in effect, any 32 bit instruction must be 15486explicitly extended with the '.e' modifier (e.g., 'li.e $4,1000'). The 15487directive '.set autoextend' may be used to once again automatically 15488extend instructions when necessary. 15489 15490 This directive is only meaningful when in MIPS 16 mode. Traditional 15491MIPS assemblers do not support this directive. 15492 15493 15494File: as.info, Node: MIPS insn, Next: MIPS FP ABIs, Prev: MIPS autoextend, Up: MIPS-Dependent 15495 154969.27.8 Directive to mark data as an instruction 15497----------------------------------------------- 15498 15499The '.insn' directive tells 'as' that the following data is actually 15500instructions. This makes a difference in MIPS 16 and microMIPS modes: 15501when loading the address of a label which precedes instructions, 'as' 15502automatically adds 1 to the value, so that jumping to the loaded address 15503will do the right thing. 15504 15505 The '.global' and '.globl' directives supported by 'as' will by 15506default mark the symbol as pointing to a region of data not code. This 15507means that, for example, any instructions following such a symbol will 15508not be disassembled by 'objdump' as it will regard them as data. To 15509change this behavior an optional section name can be placed after the 15510symbol name in the '.global' directive. If this section exists and is 15511known to be a code section, then the symbol will be marked as pointing 15512at code not data. Ie the syntax for the directive is: 15513 15514 '.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', 15515 15516 Here is a short example: 15517 15518 .global foo .text, bar, baz .data 15519 foo: 15520 nop 15521 bar: 15522 .word 0x0 15523 baz: 15524 .word 0x1 15525 15526 15527 15528File: as.info, Node: MIPS FP ABIs, Next: MIPS NaN Encodings, Prev: MIPS insn, Up: MIPS-Dependent 15529 155309.27.9 Directives to control the FP ABI 15531--------------------------------------- 15532 15533* Menu: 15534 15535* MIPS FP ABI History:: History of FP ABIs 15536* MIPS FP ABI Variants:: Supported FP ABIs 15537* MIPS FP ABI Selection:: Automatic selection of FP ABI 15538* MIPS FP ABI Compatibility:: Linking different FP ABI variants 15539 15540 15541File: as.info, Node: MIPS FP ABI History, Next: MIPS FP ABI Variants, Up: MIPS FP ABIs 15542 155439.27.9.1 History of FP ABIs 15544........................... 15545 15546The MIPS ABIs support a variety of different floating-point extensions 15547where calling-convention and register sizes vary for floating-point 15548data. The extensions exist to support a wide variety of optional 15549architecture features. The resulting ABI variants are generally 15550incompatible with each other and must be tracked carefully. 15551 15552 Traditionally the use of an explicit '.gnu_attribute 4, N' directive 15553is used to indicate which ABI is in use by a specific module. It was 15554then left to the user to ensure that command-line options and the 15555selected ABI were compatible with some potential for inconsistencies. 15556 15557 15558File: as.info, Node: MIPS FP ABI Variants, Next: MIPS FP ABI Selection, Prev: MIPS FP ABI History, Up: MIPS FP ABIs 15559 155609.27.9.2 Supported FP ABIs 15561.......................... 15562 15563The supported floating-point ABI variants are: 15564 15565'0 - No floating-point' 15566 This variant is used to indicate that floating-point is not used 15567 within the module at all and therefore has no impact on the ABI. 15568 This is the default. 15569 15570'1 - Double-precision' 15571 This variant indicates that double-precision support is used. For 15572 64-bit ABIs this means that 64-bit wide floating-point registers 15573 are required. For 32-bit ABIs this means that 32-bit wide 15574 floating-point registers are required and double-precision 15575 operations use pairs of registers. 15576 15577'2 - Single-precision' 15578 This variant indicates that single-precision support is used. 15579 Double precision operations will be supported via soft-float 15580 routines. 15581 15582'3 - Soft-float' 15583 This variant indicates that although floating-point support is used 15584 all operations are emulated in software. This means the ABI is 15585 modified to pass all floating-point data in general-purpose 15586 registers. 15587 15588'4 - Deprecated' 15589 This variant existed as an initial attempt at supporting 64-bit 15590 wide floating-point registers for O32 ABI on a MIPS32r2 CPU. This 15591 has been superseded by 5, 6 and 7. 15592 15593'5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU' 15594 This variant is used by 32-bit ABIs to indicate that the 15595 floating-point code in the module has been designed to operate 15596 correctly with either 32-bit wide or 64-bit wide floating-point 15597 registers. Double-precision support is used. Only O32 currently 15598 supports this variant and requires a minimum architecture of MIPS 15599 II. 15600 15601'6 - Double-precision 32-bit FPU, 64-bit FPU' 15602 This variant is used by 32-bit ABIs to indicate that the 15603 floating-point code in the module requires 64-bit wide 15604 floating-point registers. Double-precision support is used. Only 15605 O32 currently supports this variant and requires a minimum 15606 architecture of MIPS32r2. 15607 15608'7 - Double-precision compat 32-bit FPU, 64-bit FPU' 15609 This variant is used by 32-bit ABIs to indicate that the 15610 floating-point code in the module requires 64-bit wide 15611 floating-point registers. Double-precision support is used. This 15612 differs from the previous ABI as it restricts use of odd-numbered 15613 single-precision registers. Only O32 currently supports this 15614 variant and requires a minimum architecture of MIPS32r2. 15615 15616 15617File: as.info, Node: MIPS FP ABI Selection, Next: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Variants, Up: MIPS FP ABIs 15618 156199.27.9.3 Automatic selection of FP ABI 15620...................................... 15621 15622In order to simplify and add safety to the process of selecting the 15623correct floating-point ABI, the assembler will automatically infer the 15624correct '.gnu_attribute 4, N' directive based on command-line options 15625and '.module' overrides. Where an explicit '.gnu_attribute 4, N' 15626directive has been seen then a warning will be raised if it does not 15627match an inferred setting. 15628 15629 The floating-point ABI is inferred as follows. If '-msoft-float' has 15630been used the module will be marked as soft-float. If '-msingle-float' 15631has been used then the module will be marked as single-precision. The 15632remaining ABIs are then selected based on the FP register width. 15633Double-precision is selected if the width of GP and FP registers match 15634and the special double-precision variants for 32-bit ABIs are then 15635selected depending on '-mfpxx', '-mfp64' and '-mno-odd-spreg'. 15636 15637 15638File: as.info, Node: MIPS FP ABI Compatibility, Prev: MIPS FP ABI Selection, Up: MIPS FP ABIs 15639 156409.27.9.4 Linking different FP ABI variants 15641.......................................... 15642 15643Modules using the default FP ABI (no floating-point) can be linked with 15644any other (singular) FP ABI variant. 15645 15646 Special compatibility support exists for O32 with the four 15647double-precision FP ABI variants. The '-mfpxx' FP ABI is specifically 15648designed to be compatible with the standard double-precision ABI and the 15649'-mfp64' FP ABIs. This makes it desirable for O32 modules to be built 15650as '-mfpxx' to ensure the maximum compatibility with other modules 15651produced for more specific needs. The only FP ABIs which cannot be 15652linked together are the standard double-precision ABI and the full 15653'-mfp64' ABI with '-modd-spreg'. 15654 15655 15656File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS FP ABIs, Up: MIPS-Dependent 15657 156589.27.10 Directives to record which NaN encoding is being used 15659------------------------------------------------------------- 15660 15661The IEEE 754 floating-point standard defines two types of not-a-number 15662(NaN) data: "signalling" NaNs and "quiet" NaNs. The original version of 15663the standard did not specify how these two types should be 15664distinguished. Most implementations followed the i387 model, in which 15665the first bit of the significand is set for quiet NaNs and clear for 15666signalling NaNs. However, the original MIPS implementation assigned the 15667opposite meaning to the bit, so that it was set for signalling NaNs and 15668clear for quiet NaNs. 15669 15670 The 2008 revision of the standard formally suggested the i387 choice 15671and as from Sep 2012 the current release of the MIPS architecture 15672therefore optionally supports that form. Code that uses one NaN 15673encoding would usually be incompatible with code that uses the other NaN 15674encoding, so MIPS ELF objects have a flag ('EF_MIPS_NAN2008') to record 15675which encoding is being used. 15676 15677 Assembly files can use the '.nan' directive to select between the two 15678encodings. '.nan 2008' says that the assembly file uses the IEEE 15679754-2008 encoding while '.nan legacy' says that the file uses the 15680original MIPS encoding. If several '.nan' directives are given, the 15681final setting is the one that is used. 15682 15683 The command-line options '-mnan=legacy' and '-mnan=2008' can be used 15684instead of '.nan legacy' and '.nan 2008' respectively. However, any 15685'.nan' directive overrides the command-line setting. 15686 15687 '.nan legacy' is the default if no '.nan' directive or '-mnan' option 15688is given. 15689 15690 Note that GNU 'as' does not produce NaNs itself and therefore these 15691directives do not affect code generation. They simply control the 15692setting of the 'EF_MIPS_NAN2008' flag. 15693 15694 Traditional MIPS assemblers do not support these directives. 15695 15696 15697File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent 15698 156999.27.11 Directives to save and restore options 15700---------------------------------------------- 15701 15702The directives '.set push' and '.set pop' may be used to save and 15703restore the current settings for all the options which are controlled by 15704'.set'. The '.set push' directive saves the current settings on a 15705stack. The '.set pop' directive pops the stack and restores the 15706settings. 15707 15708 These directives can be useful inside an macro which must change an 15709option such as the ISA level or instruction reordering but does not want 15710to change the state of the code which invoked the macro. 15711 15712 Traditional MIPS assemblers do not support these directives. 15713 15714 15715File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent 15716 157179.27.12 Directives to control generation of MIPS ASE instructions 15718----------------------------------------------------------------- 15719 15720The directive '.set mips3d' makes the assembler accept instructions from 15721the MIPS-3D Application Specific Extension from that point on in the 15722assembly. The '.set nomips3d' directive prevents MIPS-3D instructions 15723from being accepted. 15724 15725 The directive '.set smartmips' makes the assembler accept 15726instructions from the SmartMIPS Application Specific Extension to the 15727MIPS32 ISA from that point on in the assembly. The '.set nosmartmips' 15728directive prevents SmartMIPS instructions from being accepted. 15729 15730 The directive '.set mdmx' makes the assembler accept instructions 15731from the MDMX Application Specific Extension from that point on in the 15732assembly. The '.set nomdmx' directive prevents MDMX instructions from 15733being accepted. 15734 15735 The directive '.set dsp' makes the assembler accept instructions from 15736the DSP Release 1 Application Specific Extension from that point on in 15737the assembly. The '.set nodsp' directive prevents DSP Release 1 15738instructions from being accepted. 15739 15740 The directive '.set dspr2' makes the assembler accept instructions 15741from the DSP Release 2 Application Specific Extension from that point on 15742in the assembly. This directive implies '.set dsp'. The '.set nodspr2' 15743directive prevents DSP Release 2 instructions from being accepted. 15744 15745 The directive '.set dspr3' makes the assembler accept instructions 15746from the DSP Release 3 Application Specific Extension from that point on 15747in the assembly. This directive implies '.set dsp' and '.set dspr2'. 15748The '.set nodspr3' directive prevents DSP Release 3 instructions from 15749being accepted. 15750 15751 The directive '.set mt' makes the assembler accept instructions from 15752the MT Application Specific Extension from that point on in the 15753assembly. The '.set nomt' directive prevents MT instructions from being 15754accepted. 15755 15756 The directive '.set mcu' makes the assembler accept instructions from 15757the MCU Application Specific Extension from that point on in the 15758assembly. The '.set nomcu' directive prevents MCU instructions from 15759being accepted. 15760 15761 The directive '.set msa' makes the assembler accept instructions from 15762the MIPS SIMD Architecture Extension from that point on in the assembly. 15763The '.set nomsa' directive prevents MSA instructions from being 15764accepted. 15765 15766 The directive '.set virt' makes the assembler accept instructions 15767from the Virtualization Application Specific Extension from that point 15768on in the assembly. The '.set novirt' directive prevents Virtualization 15769instructions from being accepted. 15770 15771 The directive '.set xpa' makes the assembler accept instructions from 15772the XPA Extension from that point on in the assembly. The '.set noxpa' 15773directive prevents XPA instructions from being accepted. 15774 15775 The directive '.set mips16e2' makes the assembler accept instructions 15776from the MIPS16e2 Application Specific Extension from that point on in 15777the assembly, whenever in MIPS16 mode. The '.set nomips16e2' directive 15778prevents MIPS16e2 instructions from being accepted, in MIPS16 mode. 15779Neither directive affects the state of MIPS16 mode being active itself 15780which has separate controls. 15781 15782 The directive '.set crc' makes the assembler accept instructions from 15783the CRC Extension from that point on in the assembly. The '.set nocrc' 15784directive prevents CRC instructions from being accepted. 15785 15786 The directive '.set ginv' makes the assembler accept instructions 15787from the GINV Extension from that point on in the assembly. The '.set 15788noginv' directive prevents GINV instructions from being accepted. 15789 15790 The directive '.set loongson-mmi' makes the assembler accept 15791instructions from the MMI Extension from that point on in the assembly. 15792The '.set noloongson-mmi' directive prevents MMI instructions from being 15793accepted. 15794 15795 The directive '.set loongson-cam' makes the assembler accept 15796instructions from the Loongson CAM from that point on in the assembly. 15797The '.set noloongson-cam' directive prevents Loongson CAM instructions 15798from being accepted. 15799 15800 The directive '.set loongson-ext' makes the assembler accept 15801instructions from the Loongson EXT from that point on in the assembly. 15802The '.set noloongson-ext' directive prevents Loongson EXT instructions 15803from being accepted. 15804 15805 The directive '.set loongson-ext2' makes the assembler accept 15806instructions from the Loongson EXT2 from that point on in the assembly. 15807This directive implies '.set loognson-ext'. The '.set noloongson-ext2' 15808directive prevents Loongson EXT2 instructions from being accepted. 15809 15810 Traditional MIPS assemblers do not support these directives. 15811 15812 15813File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent 15814 158159.27.13 Directives to override floating-point options 15816----------------------------------------------------- 15817 15818The directives '.set softfloat' and '.set hardfloat' provide finer 15819control of disabling and enabling float-point instructions. These 15820directives always override the default (that hard-float instructions are 15821accepted) or the command-line options ('-msoft-float' and 15822'-mhard-float'). 15823 15824 The directives '.set singlefloat' and '.set doublefloat' provide 15825finer control of disabling and enabling double-precision float-point 15826operations. These directives always override the default (that 15827double-precision operations are accepted) or the command-line options 15828('-msingle-float' and '-mdouble-float'). 15829 15830 Traditional MIPS assemblers do not support these directives. 15831 15832 15833File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent 15834 158359.27.14 Syntactical considerations for the MIPS assembler 15836--------------------------------------------------------- 15837 15838* Menu: 15839 15840* MIPS-Chars:: Special Characters 15841 15842 15843File: as.info, Node: MIPS-Chars, Up: MIPS Syntax 15844 158459.27.14.1 Special Characters 15846............................ 15847 15848The presence of a '#' on a line indicates the start of a comment that 15849extends to the end of the current line. 15850 15851 If a '#' appears as the first character of a line, the whole line is 15852treated as a comment, but in this case the line can also be a logical 15853line number directive (*note Comments::) or a preprocessor control 15854command (*note Preprocessing::). 15855 15856 The ';' character can be used to separate statements on the same 15857line. 15858 15859 15860File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 15861 158629.28 MMIX Dependent Features 15863============================ 15864 15865* Menu: 15866 15867* MMIX-Opts:: Command-line Options 15868* MMIX-Expand:: Instruction expansion 15869* MMIX-Syntax:: Syntax 15870* MMIX-mmixal:: Differences to 'mmixal' syntax and semantics 15871 15872 15873File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 15874 158759.28.1 Command-line Options 15876--------------------------- 15877 15878The MMIX version of 'as' has some machine-dependent options. 15879 15880 When '--fixed-special-register-names' is specified, only the register 15881names specified in *note MMIX-Regs:: are recognized in the instructions 15882'PUT' and 'GET'. 15883 15884 You can use the '--globalize-symbols' to make all symbols global. 15885This option is useful when splitting up a 'mmixal' program into several 15886files. 15887 15888 The '--gnu-syntax' turns off most syntax compatibility with 'mmixal'. 15889Its usability is currently doubtful. 15890 15891 The '--relax' option is not fully supported, but will eventually make 15892the object file prepared for linker relaxation. 15893 15894 If you want to avoid inadvertently calling a predefined symbol and 15895would rather get an error, for example when using 'as' with a compiler 15896or other machine-generated code, specify '--no-predefined-syms'. This 15897turns off built-in predefined definitions of all such symbols, including 15898rounding-mode symbols, segment symbols, 'BIT' symbols, and 'TRAP' 15899symbols used in 'mmix' "system calls". It also turns off predefined 15900special-register names, except when used in 'PUT' and 'GET' 15901instructions. 15902 15903 By default, some instructions are expanded to fit the size of the 15904operand or an external symbol (*note MMIX-Expand::). By passing 15905'--no-expand', no such expansion will be done, instead causing errors at 15906link time if the operand does not fit. 15907 15908 The 'mmixal' documentation (*note mmixsite::) specifies that global 15909registers allocated with the 'GREG' directive (*note MMIX-greg::) and 15910initialized to the same non-zero value, will refer to the same global 15911register. This isn't strictly enforceable in 'as' since the final 15912addresses aren't known until link-time, but it will do an effort unless 15913the '--no-merge-gregs' option is specified. (Register merging isn't yet 15914implemented in 'ld'.) 15915 15916 'as' will warn every time it expands an instruction to fit an operand 15917unless the option '-x' is specified. It is believed that this behaviour 15918is more useful than just mimicking 'mmixal''s behaviour, in which 15919instructions are only expanded if the '-x' option is specified, and 15920assembly fails otherwise, when an instruction needs to be expanded. It 15921needs to be kept in mind that 'mmixal' is both an assembler and linker, 15922while 'as' will expand instructions that at link stage can be 15923contracted. (Though linker relaxation isn't yet implemented in 'ld'.) 15924The option '-x' also implies '--linker-allocated-gregs'. 15925 15926 If instruction expansion is enabled, 'as' can expand a 'PUSHJ' 15927instruction into a series of instructions. The shortest expansion is to 15928not expand it, but just mark the call as redirectable to a stub, which 15929'ld' creates at link-time, but only if the original 'PUSHJ' instruction 15930is found not to reach the target. The stub consists of the necessary 15931instructions to form a jump to the target. This happens if 'as' can 15932assert that the 'PUSHJ' instruction can reach such a stub. The option 15933'--no-pushj-stubs' disables this shorter expansion, and the longer 15934series of instructions is then created at assembly-time. The option 15935'--no-stubs' is a synonym, intended for compatibility with future 15936releases, where generation of stubs for other instructions may be 15937implemented. 15938 15939 Usually a two-operand-expression (*note GREG-base::) without a 15940matching 'GREG' directive is treated as an error by 'as'. When the 15941option '--linker-allocated-gregs' is in effect, they are instead passed 15942through to the linker, which will allocate as many global registers as 15943is needed. 15944 15945 15946File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 15947 159489.28.2 Instruction expansion 15949---------------------------- 15950 15951When 'as' encounters an instruction with an operand that is either not 15952known or does not fit the operand size of the instruction, 'as' (and 15953'ld') will expand the instruction into a sequence of instructions 15954semantically equivalent to the operand fitting the instruction. 15955Expansion will take place for the following instructions: 15956 15957'GETA' 15958 Expands to a sequence of four instructions: 'SETL', 'INCML', 15959 'INCMH' and 'INCH'. The operand must be a multiple of four. 15960Conditional branches 15961 A branch instruction is turned into a branch with the complemented 15962 condition and prediction bit over five instructions; four 15963 instructions setting '$255' to the operand value, which like with 15964 'GETA' must be a multiple of four, and a final 'GO $255,$255,0'. 15965'PUSHJ' 15966 Similar to expansion for conditional branches; four instructions 15967 set '$255' to the operand value, followed by a 'PUSHGO 15968 $255,$255,0'. 15969'JMP' 15970 Similar to conditional branches and 'PUSHJ'. The final instruction 15971 is 'GO $255,$255,0'. 15972 15973 The linker 'ld' is expected to shrink these expansions for code 15974assembled with '--relax' (though not currently implemented). 15975 15976 15977File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 15978 159799.28.3 Syntax 15980------------- 15981 15982The assembly syntax is supposed to be upward compatible with that 15983described in Sections 1.3 and 1.4 of 'The Art of Computer Programming, 15984Volume 1'. Draft versions of those chapters as well as other MMIX 15985information is located at 15986<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>. Most code 15987examples from the mmixal package located there should work unmodified 15988when assembled and linked as single files, with a few noteworthy 15989exceptions (*note MMIX-mmixal::). 15990 15991 Before an instruction is emitted, the current location is aligned to 15992the next four-byte boundary. If a label is defined at the beginning of 15993the line, its value will be the aligned value. 15994 15995 In addition to the traditional hex-prefix '0x', a hexadecimal number 15996can also be specified by the prefix character '#'. 15997 15998 After all operands to an MMIX instruction or directive have been 15999specified, the rest of the line is ignored, treated as a comment. 16000 16001* Menu: 16002 16003* MMIX-Chars:: Special Characters 16004* MMIX-Symbols:: Symbols 16005* MMIX-Regs:: Register Names 16006* MMIX-Pseudos:: Assembler Directives 16007 16008 16009File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 16010 160119.28.3.1 Special Characters 16012........................... 16013 16014The characters '*' and '#' are line comment characters; each start a 16015comment at the beginning of a line, but only at the beginning of a line. 16016A '#' prefixes a hexadecimal number if found elsewhere on a line. If a 16017'#' appears at the start of a line the whole line is treated as a 16018comment, but the line can also act as a logical line number directive 16019(*note Comments::) or a preprocessor control command (*note 16020Preprocessing::). 16021 16022 Two other characters, '%' and '!', each start a comment anywhere on 16023the line. Thus you can't use the 'modulus' and 'not' operators in 16024expressions normally associated with these two characters. 16025 16026 A ';' is a line separator, treated as a new-line, so separate 16027instructions can be specified on a single line. 16028 16029 16030File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 16031 160329.28.3.2 Symbols 16033................ 16034 16035The character ':' is permitted in identifiers. There are two exceptions 16036to it being treated as any other symbol character: if a symbol begins 16037with ':', it means that the symbol is in the global namespace and that 16038the current prefix should not be prepended to that symbol (*note 16039MMIX-prefix::). The ':' is then not considered part of the symbol. For 16040a symbol in the label position (first on a line), a ':' at the end of a 16041symbol is silently stripped off. A label is permitted, but not 16042required, to be followed by a ':', as with many other assembly formats. 16043 16044 The character '@' in an expression, is a synonym for '.', the current 16045location. 16046 16047 In addition to the common forward and backward local symbol formats 16048(*note Symbol Names::), they can be specified with upper-case 'B' and 16049'F', as in '8B' and '9F'. A local label defined for the current 16050position is written with a 'H' appended to the number: 16051 3H LDB $0,$1,2 16052 This and traditional local-label formats cannot be mixed: a label 16053must be defined and referred to using the same format. 16054 16055 There's a minor caveat: just as for the ordinary local symbols, the 16056local symbols are translated into ordinary symbols using control 16057characters are to hide the ordinal number of the symbol. Unfortunately, 16058these symbols are not translated back in error messages. Thus you may 16059see confusing error messages when local symbols are used. Control 16060characters '\003' (control-C) and '\004' (control-D) are used for the 16061MMIX-specific local-symbol syntax. 16062 16063 The symbol 'Main' is handled specially; it is always global. 16064 16065 By defining the symbols '__.MMIX.start..text' and 16066'__.MMIX.start..data', the address of respectively the '.text' and 16067'.data' segments of the final program can be defined, though when 16068linking more than one object file, the code or data in the object file 16069containing the symbol is not guaranteed to be start at that position; 16070just the final executable. *Note MMIX-loc::. 16071 16072 16073File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 16074 160759.28.3.3 Register names 16076....................... 16077 16078Local and global registers are specified as '$0' to '$255'. The 16079recognized special register names are 'rJ', 'rA', 'rB', 'rC', 'rD', 16080'rE', 'rF', 'rG', 'rH', 'rI', 'rK', 'rL', 'rM', 'rN', 'rO', 'rP', 'rQ', 16081'rR', 'rS', 'rT', 'rU', 'rV', 'rW', 'rX', 'rY', 'rZ', 'rBB', 'rTT', 16082'rWW', 'rXX', 'rYY' and 'rZZ'. A leading ':' is optional for special 16083register names. 16084 16085 Local and global symbols can be equated to register names and used in 16086place of ordinary registers. 16087 16088 Similarly for special registers, local and global symbols can be 16089used. Also, symbols equated from numbers and constant expressions are 16090allowed in place of a special register, except when either of the 16091options '--no-predefined-syms' and '--fixed-special-register-names' are 16092specified. Then only the special register names above are allowed for 16093the instructions having a special register operand; 'GET' and 'PUT'. 16094 16095 16096File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 16097 160989.28.3.4 Assembler Directives 16099............................. 16100 16101'LOC' 16102 16103 The 'LOC' directive sets the current location to the value of the 16104 operand field, which may include changing sections. If the operand 16105 is a constant, the section is set to either '.data' if the value is 16106 '0x2000000000000000' or larger, else it is set to '.text'. Within 16107 a section, the current location may only be changed to 16108 monotonically higher addresses. A LOC expression must be a 16109 previously defined symbol or a "pure" constant. 16110 16111 An example, which sets the label PREV to the current location, and 16112 updates the current location to eight bytes forward: 16113 prev LOC @+8 16114 16115 When a LOC has a constant as its operand, a symbol 16116 '__.MMIX.start..text' or '__.MMIX.start..data' is defined depending 16117 on the address as mentioned above. Each such symbol is interpreted 16118 as special by the linker, locating the section at that address. 16119 Note that if multiple files are linked, the first object file with 16120 that section will be mapped to that address (not necessarily the 16121 file with the LOC definition). 16122 16123'LOCAL' 16124 16125 Example: 16126 LOCAL external_symbol 16127 LOCAL 42 16128 .local asymbol 16129 16130 This directive-operation generates a link-time assertion that the 16131 operand does not correspond to a global register. The operand is 16132 an expression that at link-time resolves to a register symbol or a 16133 number. A number is treated as the register having that number. 16134 There is one restriction on the use of this directive: the 16135 pseudo-directive must be placed in a section with contents, code or 16136 data. 16137 16138'IS' 16139 16140 The 'IS' directive: 16141 asymbol IS an_expression 16142 sets the symbol 'asymbol' to 'an_expression'. A symbol may not be 16143 set more than once using this directive. Local labels may be set 16144 using this directive, for example: 16145 5H IS @+4 16146 16147'GREG' 16148 16149 This directive reserves a global register, gives it an initial 16150 value and optionally gives it a symbolic name. Some examples: 16151 16152 areg GREG 16153 breg GREG data_value 16154 GREG data_buffer 16155 .greg creg, another_data_value 16156 16157 The symbolic register name can be used in place of a (non-special) 16158 register. If a value isn't provided, it defaults to zero. Unless 16159 the option '--no-merge-gregs' is specified, non-zero registers 16160 allocated with this directive may be eliminated by 'as'; another 16161 register with the same value used in its place. Any of the 16162 instructions 'CSWAP', 'GO', 'LDA', 'LDBU', 'LDB', 'LDHT', 'LDOU', 16163 'LDO', 'LDSF', 'LDTU', 'LDT', 'LDUNC', 'LDVTS', 'LDWU', 'LDW', 16164 'PREGO', 'PRELD', 'PREST', 'PUSHGO', 'STBU', 'STB', 'STCO', 'STHT', 16165 'STOU', 'STSF', 'STTU', 'STT', 'STUNC', 'SYNCD', 'SYNCID', can have 16166 a value nearby an initial value in place of its second and third 16167 operands. Here, "nearby" is defined as within the range 0...255 16168 from the initial value of such an allocated register. 16169 16170 buffer1 BYTE 0,0,0,0,0 16171 buffer2 BYTE 0,0,0,0,0 16172 ... 16173 GREG buffer1 16174 LDOU $42,buffer2 16175 In the example above, the 'Y' field of the 'LDOUI' instruction 16176 (LDOU with a constant Z) will be replaced with the global register 16177 allocated for 'buffer1', and the 'Z' field will have the value 5, 16178 the offset from 'buffer1' to 'buffer2'. The result is equivalent 16179 to this code: 16180 buffer1 BYTE 0,0,0,0,0 16181 buffer2 BYTE 0,0,0,0,0 16182 ... 16183 tmpreg GREG buffer1 16184 LDOU $42,tmpreg,(buffer2-buffer1) 16185 16186 Global registers allocated with this directive are allocated in 16187 order higher-to-lower within a file. Other than that, the exact 16188 order of register allocation and elimination is undefined. For 16189 example, the order is undefined when more than one file with such 16190 directives are linked together. With the options '-x' and 16191 '--linker-allocated-gregs', 'GREG' directives for two-operand cases 16192 like the one mentioned above can be omitted. Sufficient global 16193 registers will then be allocated by the linker. 16194 16195'BYTE' 16196 16197 The 'BYTE' directive takes a series of operands separated by a 16198 comma. If an operand is a string (*note Strings::), each character 16199 of that string is emitted as a byte. Other operands must be 16200 constant expressions without forward references, in the range 16201 0...255. If you need operands having expressions with forward 16202 references, use '.byte' (*note Byte::). An operand can be omitted, 16203 defaulting to a zero value. 16204 16205'WYDE' 16206'TETRA' 16207'OCTA' 16208 16209 The directives 'WYDE', 'TETRA' and 'OCTA' emit constants of two, 16210 four and eight bytes size respectively. Before anything else 16211 happens for the directive, the current location is aligned to the 16212 respective constant-size boundary. If a label is defined at the 16213 beginning of the line, its value will be that after the alignment. 16214 A single operand can be omitted, defaulting to a zero value emitted 16215 for the directive. Operands can be expressed as strings (*note 16216 Strings::), in which case each character in the string is emitted 16217 as a separate constant of the size indicated by the directive. 16218 16219'PREFIX' 16220 16221 The 'PREFIX' directive sets a symbol name prefix to be prepended to 16222 all symbols (except local symbols, *note MMIX-Symbols::), that are 16223 not prefixed with ':', until the next 'PREFIX' directive. Such 16224 prefixes accumulate. For example, 16225 PREFIX a 16226 PREFIX b 16227 c IS 0 16228 defines a symbol 'abc' with the value 0. 16229 16230'BSPEC' 16231'ESPEC' 16232 16233 A pair of 'BSPEC' and 'ESPEC' directives delimit a section of 16234 special contents (without specified semantics). Example: 16235 BSPEC 42 16236 TETRA 1,2,3 16237 ESPEC 16238 The single operand to 'BSPEC' must be number in the range 0...255. 16239 The 'BSPEC' number 80 is used by the GNU binutils implementation. 16240 16241 16242File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 16243 162449.28.4 Differences to 'mmixal' 16245------------------------------ 16246 16247The binutils 'as' and 'ld' combination has a few differences in function 16248compared to 'mmixal' (*note mmixsite::). 16249 16250 The replacement of a symbol with a GREG-allocated register (*note 16251GREG-base::) is not handled the exactly same way in 'as' as in 'mmixal'. 16252This is apparent in the 'mmixal' example file 'inout.mms', where 16253different registers with different offsets, eventually yielding the same 16254address, are used in the first instruction. This type of difference 16255should however not affect the function of any program unless it has 16256specific assumptions about the allocated register number. 16257 16258 Line numbers (in the 'mmo' object format) are currently not 16259supported. 16260 16261 Expression operator precedence is not that of mmixal: operator 16262precedence is that of the C programming language. It's recommended to 16263use parentheses to explicitly specify wanted operator precedence 16264whenever more than one type of operators are used. 16265 16266 The serialize unary operator '&', the fractional division operator 16267'//', the logical not operator '!' and the modulus operator '%' are not 16268available. 16269 16270 Symbols are not global by default, unless the option 16271'--globalize-symbols' is passed. Use the '.global' directive to 16272globalize symbols (*note Global::). 16273 16274 Operand syntax is a bit stricter with 'as' than 'mmixal'. For 16275example, you can't say 'addu 1,2,3', instead you must write 'addu 16276$1,$2,3'. 16277 16278 You can't LOC to a lower address than those already visited (i.e., 16279"backwards"). 16280 16281 A LOC directive must come before any emitted code. 16282 16283 Predefined symbols are visible as file-local symbols after use. (In 16284the ELF file, that is--the linked mmo file has no notion of a file-local 16285symbol.) 16286 16287 Some mapping of constant expressions to sections in LOC expressions 16288is attempted, but that functionality is easily confused and should be 16289avoided unless compatibility with 'mmixal' is required. A LOC 16290expression to '0x2000000000000000' or higher, maps to the '.data' 16291section and lower addresses map to the '.text' section (*note 16292MMIX-loc::). 16293 16294 The code and data areas are each contiguous. Sparse programs with 16295far-away LOC directives will take up the same amount of space as a 16296contiguous program with zeros filled in the gaps between the LOC 16297directives. If you need sparse programs, you might try and get the 16298wanted effect with a linker script and splitting up the code parts into 16299sections (*note Section::). Assembly code for this, to be compatible 16300with 'mmixal', would look something like: 16301 .if 0 16302 LOC away_expression 16303 .else 16304 .section away,"ax" 16305 .fi 16306 'as' will not execute the LOC directive and 'mmixal' ignores the 16307lines with '.'. This construct can be used generally to help 16308compatibility. 16309 16310 Symbols can't be defined twice-not even to the same value. 16311 16312 Instruction mnemonics are recognized case-insensitive, though the 16313'IS' and 'GREG' pseudo-operations must be specified in upper-case 16314characters. 16315 16316 There's no unicode support. 16317 16318 The following is a list of programs in 'mmix.tar.gz', available at 16319<http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html>, last checked 16320with the version dated 2001-08-25 (md5sum 16321c393470cfc86fac040487d22d2bf0172) that assemble with 'mmixal' but do not 16322assemble with 'as': 16323 16324'silly.mms' 16325 LOC to a previous address. 16326'sim.mms' 16327 Redefines symbol 'Done'. 16328'test.mms' 16329 Uses the serial operator '&'. 16330 16331 16332File: as.info, Node: MSP430-Dependent, Next: NDS32-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 16333 163349.29 MSP 430 Dependent Features 16335=============================== 16336 16337* Menu: 16338 16339* MSP430 Options:: Options 16340* MSP430 Syntax:: Syntax 16341* MSP430 Floating Point:: Floating Point 16342* MSP430 Directives:: MSP 430 Machine Directives 16343* MSP430 Opcodes:: Opcodes 16344* MSP430 Profiling Capability:: Profiling Capability 16345 16346 16347File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 16348 163499.29.1 Options 16350-------------- 16351 16352'-mmcu' 16353 selects the mcu architecture. If the architecture is 430Xv2 then 16354 this also enables NOP generation unless the '-mN' is also 16355 specified. 16356 16357'-mcpu' 16358 selects the cpu architecture. If the architecture is 430Xv2 then 16359 this also enables NOP generation unless the '-mN' is also 16360 specified. 16361 16362'-msilicon-errata=NAME[,NAME...]' 16363 Implements a fixup for named silicon errata. Multiple silicon 16364 errata can be specified by multiple uses of the '-msilicon-errata' 16365 option and/or by including the errata names, separated by commas, 16366 on an individual '-msilicon-errata' option. Errata names currently 16367 recognised by the assembler are: 16368 16369 'cpu4' 16370 'PUSH #4' and 'PUSH #8' need longer encodings on the MSP430. 16371 This option is enabled by default, and cannot be disabled. 16372 'cpu8' 16373 Do not set the 'SP' to an odd value. 16374 'cpu11' 16375 Do not update the 'SR' and the 'PC' in the same instruction. 16376 'cpu12' 16377 Do not use the 'PC' in a 'CMP' or 'BIT' instruction. 16378 'cpu13' 16379 Do not use an arithmetic instruction to modify the 'SR'. 16380 'cpu19' 16381 Insert 'NOP' after 'CPUOFF'. 16382 16383'-msilicon-errata-warn=NAME[,NAME...]' 16384 Like the '-msilicon-errata' option except that instead of fixing 16385 the specified errata, a warning message is issued instead. This 16386 option can be used alongside '-msilicon-errata' to generate 16387 messages whenever a problem is fixed, or on its own in order to 16388 inspect code for potential problems. 16389 16390'-mP' 16391 enables polymorph instructions handler. 16392 16393'-mQ' 16394 enables relaxation at assembly time. DANGEROUS! 16395 16396'-ml' 16397 indicates that the input uses the large code model. 16398 16399'-mn' 16400 enables the generation of a NOP instruction following any 16401 instruction that might change the interrupts enabled/disabled 16402 state. The pipelined nature of the MSP430 core means that any 16403 instruction that changes the interrupt state ('EINT', 'DINT', 'BIC 16404 #8, SR', 'BIS #8, SR' or 'MOV.W <>, SR') must be followed by a NOP 16405 instruction in order to ensure the correct processing of 16406 interrupts. By default it is up to the programmer to supply these 16407 NOP instructions, but this command-line option enables the 16408 automatic insertion by the assembler, if they are missing. 16409 16410'-mN' 16411 disables the generation of a NOP instruction following any 16412 instruction that might change the interrupts enabled/disabled 16413 state. This is the default behaviour. 16414 16415'-my' 16416 tells the assembler to generate a warning message if a NOP does not 16417 immediately follow an instruction that enables or disables 16418 interrupts. This is the default. 16419 16420 Note that this option can be stacked with the '-mn' option so that 16421 the assembler will both warn about missing NOP instructions and 16422 then insert them automatically. 16423 16424'-mY' 16425 disables warnings about missing NOP instructions. 16426 16427'-md' 16428 mark the object file as one that requires data to copied from ROM 16429 to RAM at execution startup. Disabled by default. 16430 16431'-mdata-region=REGION' 16432 Select the region data will be placed in. Region placement is 16433 performed by the compiler and linker. The only effect this option 16434 will have on the assembler is that if UPPER or EITHER is selected, 16435 then the symbols to initialise high data and bss will be defined. 16436 Valid REGION values are: 16437 'none' 16438 'lower' 16439 'upper' 16440 'either' 16441 16442 16443File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 16444 164459.29.2 Syntax 16446------------- 16447 16448* Menu: 16449 16450* MSP430-Macros:: Macros 16451* MSP430-Chars:: Special Characters 16452* MSP430-Regs:: Register Names 16453* MSP430-Ext:: Assembler Extensions 16454 16455 16456File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 16457 164589.29.2.1 Macros 16459............... 16460 16461The macro syntax used on the MSP 430 is like that described in the MSP 16462430 Family Assembler Specification. Normal 'as' macros should still 16463work. 16464 16465 Additional built-in macros are: 16466 16467'llo(exp)' 16468 Extracts least significant word from 32-bit expression 'exp'. 16469 16470'lhi(exp)' 16471 Extracts most significant word from 32-bit expression 'exp'. 16472 16473'hlo(exp)' 16474 Extracts 3rd word from 64-bit expression 'exp'. 16475 16476'hhi(exp)' 16477 Extracts 4rd word from 64-bit expression 'exp'. 16478 16479 They normally being used as an immediate source operand. 16480 mov #llo(1), r10 ; == mov #1, r10 16481 mov #lhi(1), r10 ; == mov #0, r10 16482 16483 16484File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 16485 164869.29.2.2 Special Characters 16487........................... 16488 16489A semicolon (';') appearing anywhere on a line starts a comment that 16490extends to the end of that line. 16491 16492 If a '#' appears as the first character of a line then the whole line 16493is treated as a comment, but it can also be a logical line number 16494directive (*note Comments::) or a preprocessor control command (*note 16495Preprocessing::). 16496 16497 Multiple statements can appear on the same line provided that they 16498are separated by the '{' character. 16499 16500 The character '$' in jump instructions indicates current location and 16501implemented only for TI syntax compatibility. 16502 16503 16504File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 16505 165069.29.2.3 Register Names 16507....................... 16508 16509General-purpose registers are represented by predefined symbols of the 16510form 'rN' (for global registers), where N represents a number between 16511'0' and '15'. The leading letters may be in either upper or lower case; 16512for example, 'r13' and 'R7' are both valid register names. 16513 16514 Register names 'PC', 'SP' and 'SR' cannot be used as register names 16515and will be treated as variables. Use 'r0', 'r1', and 'r2' instead. 16516 16517 16518File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 16519 165209.29.2.4 Assembler Extensions 16521............................. 16522 16523'@rN' 16524 As destination operand being treated as '0(rn)' 16525 16526'0(rN)' 16527 As source operand being treated as '@rn' 16528 16529'jCOND +N' 16530 Skips next N bytes followed by jump instruction and equivalent to 16531 'jCOND $+N+2' 16532 16533 Also, there are some instructions, which cannot be found in other 16534assemblers. These are branch instructions, which has different opcodes 16535upon jump distance. They all got PC relative addressing mode. 16536 16537'beq label' 16538 A polymorph instruction which is 'jeq label' in case if jump 16539 distance within allowed range for cpu's jump instruction. If not, 16540 this unrolls into a sequence of 16541 jne $+6 16542 br label 16543 16544'bne label' 16545 A polymorph instruction which is 'jne label' or 'jeq +4; br label' 16546 16547'blt label' 16548 A polymorph instruction which is 'jl label' or 'jge +4; br label' 16549 16550'bltn label' 16551 A polymorph instruction which is 'jn label' or 'jn +2; jmp +4; br 16552 label' 16553 16554'bltu label' 16555 A polymorph instruction which is 'jlo label' or 'jhs +2; br label' 16556 16557'bge label' 16558 A polymorph instruction which is 'jge label' or 'jl +4; br label' 16559 16560'bgeu label' 16561 A polymorph instruction which is 'jhs label' or 'jlo +4; br label' 16562 16563'bgt label' 16564 A polymorph instruction which is 'jeq +2; jge label' or 'jeq +6; jl 16565 +4; br label' 16566 16567'bgtu label' 16568 A polymorph instruction which is 'jeq +2; jhs label' or 'jeq +6; 16569 jlo +4; br label' 16570 16571'bleu label' 16572 A polymorph instruction which is 'jeq label; jlo label' or 'jeq +2; 16573 jhs +4; br label' 16574 16575'ble label' 16576 A polymorph instruction which is 'jeq label; jl label' or 'jeq +2; 16577 jge +4; br label' 16578 16579'jump label' 16580 A polymorph instruction which is 'jmp label' or 'br label' 16581 16582 16583File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 16584 165859.29.3 Floating Point 16586--------------------- 16587 16588The MSP 430 family uses IEEE 32-bit floating-point numbers. 16589 16590 16591File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 16592 165939.29.4 MSP 430 Machine Directives 16594--------------------------------- 16595 16596'.file' 16597 This directive is ignored; it is accepted for compatibility with 16598 other MSP 430 assemblers. 16599 16600 _Warning:_ in other versions of the GNU assembler, '.file' is 16601 used for the directive called '.app-file' in the MSP 430 16602 support. 16603 16604'.line' 16605 This directive is ignored; it is accepted for compatibility with 16606 other MSP 430 assemblers. 16607 16608'.arch' 16609 Sets the target microcontroller in the same way as the '-mmcu' 16610 command-line option. 16611 16612'.cpu' 16613 Sets the target architecture in the same way as the '-mcpu' 16614 command-line option. 16615 16616'.profiler' 16617 This directive instructs assembler to add new profile entry to the 16618 object file. 16619 16620'.refsym' 16621 This directive instructs assembler to add an undefined reference to 16622 the symbol following the directive. The maximum symbol name length 16623 is 1023 characters. No relocation is created for this symbol; it 16624 will exist purely for pulling in object files from archives. Note 16625 that this reloc is not sufficient to prevent garbage collection; 16626 use a KEEP() directive in the linker file to preserve such objects. 16627 16628'.mspabi_attribute' 16629 This directive tells the assembler what the MSPABI build attributes 16630 for this file are. This is used for validating the command line 16631 options passed to the assembler against the options the original 16632 source file was compiled with. The expected format is: 16633 '.mspabi_attribute tag_name, tag_value' For example, to set the tag 16634 'OFBA_MSPABI_Tag_ISA' to 'MSP430X': '.mspabi_attribute 4, 2' 16635 16636 See the 'MSP430 EABI, document slaa534' for the details on tag 16637 names and values. 16638 16639 16640File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 16641 166429.29.5 Opcodes 16643-------------- 16644 16645'as' implements all the standard MSP 430 opcodes. No additional 16646pseudo-instructions are needed on this family. 16647 16648 For information on the 430 machine instruction set, see 'MSP430 16649User's Manual, document slau049d', Texas Instrument, Inc. 16650 16651 16652File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 16653 166549.29.6 Profiling Capability 16655--------------------------- 16656 16657It is a performance hit to use gcc's profiling approach for this tiny 16658target. Even more - jtag hardware facility does not perform any 16659profiling functions. However we've got gdb's built-in simulator where 16660we can do anything. 16661 16662 We define new section '.profiler' which holds all profiling 16663information. We define new pseudo operation '.profiler' which will 16664instruct assembler to add new profile entry to the object file. Profile 16665should take place at the present address. 16666 16667 Pseudo operation format: 16668 16669 '.profiler flags,function_to_profile [, cycle_corrector, extra]' 16670 16671 where: 16672 16673 'flags' is a combination of the following characters: 16674 16675 's' 16676 function entry 16677 'x' 16678 function exit 16679 'i' 16680 function is in init section 16681 'f' 16682 function is in fini section 16683 'l' 16684 library call 16685 'c' 16686 libc standard call 16687 'd' 16688 stack value demand 16689 'I' 16690 interrupt service routine 16691 'P' 16692 prologue start 16693 'p' 16694 prologue end 16695 'E' 16696 epilogue start 16697 'e' 16698 epilogue end 16699 'j' 16700 long jump / sjlj unwind 16701 'a' 16702 an arbitrary code fragment 16703 't' 16704 extra parameter saved (a constant value like frame size) 16705 16706'function_to_profile' 16707 a function address 16708'cycle_corrector' 16709 a value which should be added to the cycle counter, zero if 16710 omitted. 16711'extra' 16712 any extra parameter, zero if omitted. 16713 16714 For example: 16715 .global fxx 16716 .type fxx,@function 16717 fxx: 16718 .LFrameOffset_fxx=0x08 16719 .profiler "scdP", fxx ; function entry. 16720 ; we also demand stack value to be saved 16721 push r11 16722 push r10 16723 push r9 16724 push r8 16725 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 16726 ; (this is a prologue end) 16727 ; note, that spare var filled with 16728 ; the farme size 16729 mov r15,r8 16730 ... 16731 .profiler cdE,fxx ; check stack 16732 pop r8 16733 pop r9 16734 pop r10 16735 pop r11 16736 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 16737 ret ; cause 'ret' insn takes 3 cycles 16738 16739 16740File: as.info, Node: NDS32-Dependent, Next: NiosII-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 16741 167429.30 NDS32 Dependent Features 16743============================= 16744 16745The NDS32 processors family includes high-performance and low-power 1674632-bit processors for high-end to low-end. GNU 'as' for NDS32 16747architectures supports NDS32 ISA version 3. For detail about NDS32 16748instruction set, please see the AndeStar ISA User Manual which is 16749available at http://www.andestech.com/en/index/index.htm 16750 16751* Menu: 16752 16753* NDS32 Options:: Assembler options 16754* NDS32 Syntax:: High-level assembly macros 16755 16756 16757File: as.info, Node: NDS32 Options, Next: NDS32 Syntax, Up: NDS32-Dependent 16758 167599.30.1 NDS32 Options 16760-------------------- 16761 16762The NDS32 configurations of GNU 'as' support these special options: 16763 16764'-O1' 16765 Optimize for performance. 16766 16767'-Os' 16768 Optimize for space. 16769 16770'-EL' 16771 Produce little endian data output. 16772 16773'-EB' 16774 Produce little endian data output. 16775 16776'-mpic' 16777 Generate PIC. 16778 16779'-mno-fp-as-gp-relax' 16780 Suppress fp-as-gp relaxation for this file. 16781 16782'-mb2bb-relax' 16783 Back-to-back branch optimization. 16784 16785'-mno-all-relax' 16786 Suppress all relaxation for this file. 16787 16788'-march=<arch name>' 16789 Assemble for architecture <arch name> which could be v3, v3j, v3m, 16790 v3f, v3s, v2, v2j, v2f, v2s. 16791 16792'-mbaseline=<baseline>' 16793 Assemble for baseline <baseline> which could be v2, v3, v3m. 16794 16795'-mfpu-freg=FREG' 16796 Specify a FPU configuration. 16797 '0 8 SP / 4 DP registers' 16798 '1 16 SP / 8 DP registers' 16799 '2 32 SP / 16 DP registers' 16800 '3 32 SP / 32 DP registers' 16801 16802'-mabi=ABI' 16803 Specify a abi version <abi> could be v1, v2, v2fp, v2fpp. 16804 16805'-m[no-]mac' 16806 Enable/Disable Multiply instructions support. 16807 16808'-m[no-]div' 16809 Enable/Disable Divide instructions support. 16810 16811'-m[no-]16bit-ext' 16812 Enable/Disable 16-bit extension 16813 16814'-m[no-]dx-regs' 16815 Enable/Disable d0/d1 registers 16816 16817'-m[no-]perf-ext' 16818 Enable/Disable Performance extension 16819 16820'-m[no-]perf2-ext' 16821 Enable/Disable Performance extension 2 16822 16823'-m[no-]string-ext' 16824 Enable/Disable String extension 16825 16826'-m[no-]reduced-regs' 16827 Enable/Disable Reduced Register configuration (GPR16) option 16828 16829'-m[no-]audio-isa-ext' 16830 Enable/Disable AUDIO ISA extension 16831 16832'-m[no-]fpu-sp-ext' 16833 Enable/Disable FPU SP extension 16834 16835'-m[no-]fpu-dp-ext' 16836 Enable/Disable FPU DP extension 16837 16838'-m[no-]fpu-fma' 16839 Enable/Disable FPU fused-multiply-add instructions 16840 16841'-mall-ext' 16842 Turn on all extensions and instructions support 16843 16844 16845File: as.info, Node: NDS32 Syntax, Prev: NDS32 Options, Up: NDS32-Dependent 16846 168479.30.2 Syntax 16848------------- 16849 16850* Menu: 16851 16852* NDS32-Chars:: Special Characters 16853* NDS32-Regs:: Register Names 16854* NDS32-Ops:: Pseudo Instructions 16855 16856 16857File: as.info, Node: NDS32-Chars, Next: NDS32-Regs, Up: NDS32 Syntax 16858 168599.30.2.1 Special Characters 16860........................... 16861 16862Use '#' at column 1 and '!' anywhere in the line except inside quotes. 16863 16864 Multiple instructions in a line are allowed though not recommended 16865and should be separated by ';'. 16866 16867 Assembler is not case-sensitive in general except user defined label. 16868For example, 'jral F1' is different from 'jral f1' while it is the same 16869as 'JRAL F1'. 16870 16871 16872File: as.info, Node: NDS32-Regs, Next: NDS32-Ops, Prev: NDS32-Chars, Up: NDS32 Syntax 16873 168749.30.2.2 Register Names 16875....................... 16876 16877'General purpose registers (GPR)' 16878 There are 32 32-bit general purpose registers $r0 to $r31. 16879 16880'Accumulators d0 and d1' 16881 64-bit accumulators: $d0.hi, $d0.lo, $d1.hi, and $d1.lo. 16882 16883'Assembler reserved register $ta' 16884 Register $ta ($r15) is reserved for assembler using. 16885 16886'Operating system reserved registers $p0 and $p1' 16887 Registers $p0 ($r26) and $p1 ($r27) are used by operating system as 16888 scratch registers. 16889 16890'Frame pointer $fp' 16891 Register $r28 is regarded as the frame pointer. 16892 16893'Global pointer' 16894 Register $r29 is regarded as the global pointer. 16895 16896'Link pointer' 16897 Register $r30 is regarded as the link pointer. 16898 16899'Stack pointer' 16900 Register $r31 is regarded as the stack pointer. 16901 16902 16903File: as.info, Node: NDS32-Ops, Prev: NDS32-Regs, Up: NDS32 Syntax 16904 169059.30.2.3 Pseudo Instructions 16906............................ 16907 16908'li rt5,imm32' 16909 load 32-bit integer into register rt5. 'sethi rt5,hi20(imm32)' and 16910 then 'ori rt5,reg,lo12(imm32)'. 16911 16912'la rt5,var' 16913 Load 32-bit address of var into register rt5. 'sethi 16914 rt5,hi20(var)' and then 'ori reg,rt5,lo12(var)' 16915 16916'l.[bhw] rt5,var' 16917 Load value of var into register rt5. 'sethi $ta,hi20(var)' and 16918 then 'l[bhw]i rt5,[$ta+lo12(var)]' 16919 16920'l.[bh]s rt5,var' 16921 Load value of var into register rt5. 'sethi $ta,hi20(var)' and 16922 then 'l[bh]si rt5,[$ta+lo12(var)]' 16923 16924'l.[bhw]p rt5,var,inc' 16925 Load value of var into register rt5 and increment $ta by amount 16926 inc. 'la $ta,var' and then 'l[bhw]i.bi rt5,[$ta],inc' 16927 16928'l.[bhw]pc rt5,inc' 16929 Continue loading value of var into register rt5 and increment $ta 16930 by amount inc. 'l[bhw]i.bi rt5,[$ta],inc.' 16931 16932'l.[bh]sp rt5,var,inc' 16933 Load value of var into register rt5 and increment $ta by amount 16934 inc. 'la $ta,var' and then 'l[bh]si.bi rt5,[$ta],inc' 16935 16936'l.[bh]spc rt5,inc' 16937 Continue loading value of var into register rt5 and increment $ta 16938 by amount inc. 'l[bh]si.bi rt5,[$ta],inc.' 16939 16940's.[bhw] rt5,var' 16941 Store register rt5 to var. 'sethi $ta,hi20(var)' and then 's[bhw]i 16942 rt5,[$ta+lo12(var)]' 16943 16944's.[bhw]p rt5,var,inc' 16945 Store register rt5 to var and increment $ta by amount inc. 'la 16946 $ta,var' and then 's[bhw]i.bi rt5,[$ta],inc' 16947 16948's.[bhw]pc rt5,inc' 16949 Continue storing register rt5 to var and increment $ta by amount 16950 inc. 's[bhw]i.bi rt5,[$ta],inc.' 16951 16952'not rt5,ra5' 16953 Alias of 'nor rt5,ra5,ra5'. 16954 16955'neg rt5,ra5' 16956 Alias of 'subri rt5,ra5,0'. 16957 16958'br rb5' 16959 Depending on how it is assembled, it is translated into 'r5 rb5' or 16960 'jr rb5'. 16961 16962'b label' 16963 Branch to label depending on how it is assembled, it is translated 16964 into 'j8 label', 'j label', or "'la $ta,label' 'br $ta'". 16965 16966'bral rb5' 16967 Alias of jral br5 depending on how it is assembled, it is 16968 translated into 'jral5 rb5' or 'jral rb5'. 16969 16970'bal fname' 16971 Alias of jal fname depending on how it is assembled, it is 16972 translated into 'jal fname' or "'la $ta,fname' 'bral $ta'". 16973 16974'call fname' 16975 Call function fname same as 'jal fname'. 16976 16977'move rt5,ra5' 16978 For 16-bit, this is 'mov55 rt5,ra5'. For no 16-bit, this is 'ori 16979 rt5,ra5,0'. 16980 16981'move rt5,var' 16982 This is the same as 'l.w rt5,var'. 16983 16984'move rt5,imm32' 16985 This is the same as 'li rt5,imm32'. 16986 16987'pushm ra5,rb5' 16988 Push contents of registers from ra5 to rb5 into stack. 16989 16990'push ra5' 16991 Push content of register ra5 into stack. (same 'pushm ra5,ra5'). 16992 16993'push.d var' 16994 Push value of double-word variable var into stack. 16995 16996'push.w var' 16997 Push value of word variable var into stack. 16998 16999'push.h var' 17000 Push value of half-word variable var into stack. 17001 17002'push.b var' 17003 Push value of byte variable var into stack. 17004 17005'pusha var' 17006 Push 32-bit address of variable var into stack. 17007 17008'pushi imm32' 17009 Push 32-bit immediate value into stack. 17010 17011'popm ra5,rb5' 17012 Pop top of stack values into registers ra5 to rb5. 17013 17014'pop rt5' 17015 Pop top of stack value into register. (same as 'popm rt5,rt5'.) 17016 17017'pop.d var,ra5' 17018 Pop value of double-word variable var from stack using register ra5 17019 as 2nd scratch register. (1st is $ta) 17020 17021'pop.w var,ra5' 17022 Pop value of word variable var from stack using register ra5. 17023 17024'pop.h var,ra5' 17025 Pop value of half-word variable var from stack using register ra5. 17026 17027'pop.b var,ra5' 17028 Pop value of byte variable var from stack using register ra5. 17029 17030 17031File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: NDS32-Dependent, Up: Machine Dependencies 17032 170339.31 Nios II Dependent Features 17034=============================== 17035 17036* Menu: 17037 17038* Nios II Options:: Options 17039* Nios II Syntax:: Syntax 17040* Nios II Relocations:: Relocations 17041* Nios II Directives:: Nios II Machine Directives 17042* Nios II Opcodes:: Opcodes 17043 17044 17045File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent 17046 170479.31.1 Options 17048-------------- 17049 17050'-relax-section' 17051 Replace identified out-of-range branches with PC-relative 'jmp' 17052 sequences when possible. The generated code sequences are suitable 17053 for use in position-independent code, but there is a practical 17054 limit on the extended branch range because of the length of the 17055 sequences. This option is the default. 17056 17057'-relax-all' 17058 Replace branch instructions not determinable to be in range and all 17059 call instructions with 'jmp' and 'callr' sequences (respectively). 17060 This option generates absolute relocations against the target 17061 symbols and is not appropriate for position-independent code. 17062 17063'-no-relax' 17064 Do not replace any branches or calls. 17065 17066'-EB' 17067 Generate big-endian output. 17068 17069'-EL' 17070 Generate little-endian output. This is the default. 17071 17072'-march=ARCHITECTURE' 17073 This option specifies the target architecture. The assembler 17074 issues an error message if an attempt is made to assemble an 17075 instruction which will not execute on the target architecture. The 17076 following architecture names are recognized: 'r1', 'r2'. The 17077 default is 'r1'. 17078 17079 17080File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent 17081 170829.31.2 Syntax 17083------------- 17084 17085* Menu: 17086 17087* Nios II Chars:: Special Characters 17088 17089 17090File: as.info, Node: Nios II Chars, Up: Nios II Syntax 17091 170929.31.2.1 Special Characters 17093........................... 17094 17095'#' is the line comment character. ';' is the line separator character. 17096 17097 17098File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent 17099 171009.31.3 Nios II Machine Relocations 17101---------------------------------- 17102 17103'%hiadj(EXPRESSION)' 17104 Extract the upper 16 bits of EXPRESSION and add one if the 15th bit 17105 is set. 17106 17107 The value of '%hiadj(EXPRESSION)' is: 17108 ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01) 17109 17110 The '%hiadj' relocation is intended to be used with the 'addi', 17111 'ld' or 'st' instructions along with a '%lo', in order to load a 17112 32-bit constant. 17113 17114 movhi r2, %hiadj(symbol) 17115 addi r2, r2, %lo(symbol) 17116 17117'%hi(EXPRESSION)' 17118 Extract the upper 16 bits of EXPRESSION. 17119 17120'%lo(EXPRESSION)' 17121 Extract the lower 16 bits of EXPRESSION. 17122 17123'%gprel(EXPRESSION)' 17124 Subtract the value of the symbol '_gp' from EXPRESSION. 17125 17126 The intention of the '%gprel' relocation is to have a fast small 17127 area of memory which only takes a 16-bit immediate to access. 17128 17129 .section .sdata 17130 fastint: 17131 .int 123 17132 .section .text 17133 ldw r4, %gprel(fastint)(gp) 17134 17135'%call(EXPRESSION)' 17136'%call_lo(EXPRESSION)' 17137'%call_hiadj(EXPRESSION)' 17138'%got(EXPRESSION)' 17139'%got_lo(EXPRESSION)' 17140'%got_hiadj(EXPRESSION)' 17141'%gotoff(EXPRESSION)' 17142'%gotoff_lo(EXPRESSION)' 17143'%gotoff_hiadj(EXPRESSION)' 17144'%tls_gd(EXPRESSION)' 17145'%tls_ie(EXPRESSION)' 17146'%tls_le(EXPRESSION)' 17147'%tls_ldm(EXPRESSION)' 17148'%tls_ldo(EXPRESSION)' 17149 17150 These relocations support the ABI for Linux Systems documented in 17151 the 'Nios II Processor Reference Handbook'. 17152 17153 17154File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent 17155 171569.31.4 Nios II Machine Directives 17157--------------------------------- 17158 17159'.align EXPRESSION [, EXPRESSION]' 17160 This is the generic '.align' directive, however this aligns to a 17161 power of two. 17162 17163'.half EXPRESSION' 17164 Create an aligned constant 2 bytes in size. 17165 17166'.word EXPRESSION' 17167 Create an aligned constant 4 bytes in size. 17168 17169'.dword EXPRESSION' 17170 Create an aligned constant 8 bytes in size. 17171 17172'.2byte EXPRESSION' 17173 Create an unaligned constant 2 bytes in size. 17174 17175'.4byte EXPRESSION' 17176 Create an unaligned constant 4 bytes in size. 17177 17178'.8byte EXPRESSION' 17179 Create an unaligned constant 8 bytes in size. 17180 17181'.16byte EXPRESSION' 17182 Create an unaligned constant 16 bytes in size. 17183 17184'.set noat' 17185 Allows assembly code to use 'at' register without warning. Macro 17186 or relaxation expansions generate warnings. 17187 17188'.set at' 17189 Assembly code using 'at' register generates warnings, and macro 17190 expansion and relaxation are enabled. 17191 17192'.set nobreak' 17193 Allows assembly code to use 'ba' and 'bt' registers without 17194 warning. 17195 17196'.set break' 17197 Turns warnings back on for using 'ba' and 'bt' registers. 17198 17199'.set norelax' 17200 Do not replace any branches or calls. 17201 17202'.set relaxsection' 17203 Replace identified out-of-range branches with 'jmp' sequences 17204 (default). 17205 17206'.set relaxsection' 17207 Replace all branch and call instructions with 'jmp' and 'callr' 17208 sequences. 17209 17210'.set ...' 17211 All other '.set' are the normal use. 17212 17213 17214File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent 17215 172169.31.5 Opcodes 17217-------------- 17218 17219'as' implements all the standard Nios II opcodes documented in the 'Nios 17220II Processor Reference Handbook', including the assembler 17221pseudo-instructions. 17222 17223 17224File: as.info, Node: NS32K-Dependent, Next: OpenRISC-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies 17225 172269.32 NS32K Dependent Features 17227============================= 17228 17229* Menu: 17230 17231* NS32K Syntax:: Syntax 17232 17233 17234File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent 17235 172369.32.1 Syntax 17237------------- 17238 17239* Menu: 17240 17241* NS32K-Chars:: Special Characters 17242 17243 17244File: as.info, Node: NS32K-Chars, Up: NS32K Syntax 17245 172469.32.1.1 Special Characters 17247........................... 17248 17249The presence of a '#' appearing anywhere on a line indicates the start 17250of a comment that extends to the end of that line. 17251 17252 If a '#' appears as the first character of a line then the whole line 17253is treated as a comment, but in this case the line can also be a logical 17254line number directive (*note Comments::) or a preprocessor control 17255command (*note Preprocessing::). 17256 17257 If Sequent compatibility has been configured into the assembler then 17258the '|' character appearing as the first character on a line will also 17259indicate the start of a line comment. 17260 17261 The ';' character can be used to separate statements on the same 17262line. 17263 17264 17265File: as.info, Node: OpenRISC-Dependent, Next: PDP-11-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies 17266 172679.33 OPENRISC Dependent Features 17268================================ 17269 17270* Menu: 17271 17272* OpenRISC-Syntax:: Syntax 17273* OpenRISC-Float:: Floating Point 17274* OpenRISC-Directives:: OpenRISC Machine Directives 17275* OpenRISC-Opcodes:: Opcodes 17276 17277 17278File: as.info, Node: OpenRISC-Syntax, Next: OpenRISC-Float, Up: OpenRISC-Dependent 17279 172809.33.1 OpenRISC Syntax 17281---------------------- 17282 17283The assembler syntax follows the OpenRISC 1000 Architecture Manual. 17284 17285* Menu: 17286 17287* OpenRISC-Chars:: Special Characters 17288* OpenRISC-Regs:: Register Names 17289* OpenRISC-Relocs:: Relocations 17290 17291 17292File: as.info, Node: OpenRISC-Chars, Next: OpenRISC-Regs, Up: OpenRISC-Syntax 17293 172949.33.1.1 Special Characters 17295........................... 17296 17297A '#' character appearing anywhere on a line indicates the start of a 17298comment that extends to the end of that line. 17299 17300 ';' can be used instead of a newline to separate statements. 17301 17302 17303File: as.info, Node: OpenRISC-Regs, Next: OpenRISC-Relocs, Prev: OpenRISC-Chars, Up: OpenRISC-Syntax 17304 173059.33.1.2 Register Names 17306....................... 17307 17308The OpenRISC register file contains 32 general pupose registers. 17309 17310 * The 32 general purpose registers are referred to as 'rN'. 17311 17312 * The stack pointer register 'r1' can be referenced using the alias 17313 'sp'. 17314 17315 * The frame pointer register 'r2' can be referenced using the alias 17316 'fp'. 17317 17318 * The link register 'r9' can be referenced using the alias 'lr'. 17319 17320 Floating point operations use the same general purpose registers. 17321The instructions 'lf.itof.s' (single precision) and 'lf.itof.d' (double 17322precision) can be used to convert integer values to floating point. 17323Likewise, instructions 'lf.ftoi.s' (single precision) and 'lf.ftoi.d' 17324(double precision) can be used to convert floating point to integer. 17325 17326 OpenRISC also contains privileged special purpose registers (SPRs). 17327The SPRs are accessed using the 'l.mfspr' and 'l.mtspr' instructions. 17328 17329 17330File: as.info, Node: OpenRISC-Relocs, Prev: OpenRISC-Regs, Up: OpenRISC-Syntax 17331 173329.33.1.3 Relocations 17333.................... 17334 17335ELF relocations are available as defined in the OpenRISC architecture 17336specification. 17337 17338 'R_OR1K_HI_16_IN_INSN' is obtained using 'hi' and 17339'R_OR1K_LO_16_IN_INSN' and 'R_OR1K_SLO16' are obtained using 'lo'. For 17340signed offsets 'R_OR1K_AHI16' is obtained from 'ha'. For example: 17341 17342 l.movhi r5, hi(symbol) 17343 l.ori r5, r5, lo(symbol) 17344 17345 l.movhi r5, ha(symbol) 17346 l.addi r5, r5, lo(symbol) 17347 17348 These "high" mnemonics extract bits 31:16 of their operand, and the 17349"low" mnemonics extract bits 15:0 of their operand. 17350 17351 The PC relative relocation 'R_OR1K_GOTPC_HI16' can be obtained by 17352enclosing an operand inside of 'gotpchi'. Likewise, the 17353'R_OR1K_GOTPC_LO16' relocation can be obtained using 'gotpclo'. These 17354are mostly used when assembling PIC code. For example, the standard PIC 17355sequence on OpenRISC to get the base of the global offset table, PC 17356relative, into a register, can be performed as: 17357 17358 l.jal 0x8 17359 l.movhi r17, gotpchi(_GLOBAL_OFFSET_TABLE_-4) 17360 l.ori r17, r17, gotpclo(_GLOBAL_OFFSET_TABLE_+0) 17361 l.add r17, r17, r9 17362 17363 Several relocations exist to allow the link editor to perform GOT 17364data references. The 'R_OR1K_GOT16' relocation can obtained by 17365enclosing an operand inside of 'got'. For example, assuming the GOT 17366base is in register 'r17'. 17367 17368 l.lwz r19, got(a)(r17) 17369 l.lwz r21, 0(r19) 17370 17371 Also, several relocations exist for local GOT references. The 17372'R_OR1K_GOTOFF_AHI16' relocation can obtained by enclosing an operand 17373inside of 'gotoffha'. Likewise, 'R_OR1K_GOTOFF_LO16' and 17374'R_OR1K_GOTOFF_SLO16' can be obtained by enclosing an operand inside of 17375'gotofflo'. For example, assuming the GOT base is in register 'rl7': 17376 17377 l.movhi r19, gotoffha(symbol) 17378 l.add r19, r19, r17 17379 l.lwz r19, gotofflo(symbol)(r19) 17380 17381 The above PC relative relocations use a 'l.jal' (jump) instruction 17382and reading of the link register to load the PC. OpenRISC also supports 17383page offset PC relative locations without a jump instruction using the 17384'l.adrp' instruction. By default the 'l.adrp' instruction will create 17385an 'R_OR1K_PCREL_PG21' relocation. Likewise, 'BFD_RELOC_OR1K_LO13' and 17386'BFD_RELOC_OR1K_SLO13' can be obtained by enclosing an operand inside of 17387'po'. For example: 17388 17389 l.adrp r3, symbol 17390 l.ori r4, r3, po(symbol) 17391 l.lbz r5, po(symbol)(r3) 17392 l.sb po(symbol)(r3), r6 17393 17394 Likewise the page offset relocations can be used with GOT references. 17395The relocation 'R_OR1K_GOT_PG21' can be obtained by enclosing an 17396'l.adrp' immediate operand inside of 'got'. Likewise, 'R_OR1K_GOT_LO13' 17397can be obtained by enclosing an operand inside of 'gotpo'. For example 17398to load the value of a GOT symbol into register 'r5' we can do: 17399 17400 l.adrp r17, got(_GLOBAL_OFFSET_TABLE_) 17401 l.lwz r5, gotpo(symbol)(r17) 17402 17403 There are many relocations that can be requested for access to thread 17404local storage variables. All of the OpenRISC TLS mnemonics are 17405supported: 17406 17407 * 'R_OR1K_TLS_GD_HI16' is requested using 'tlsgdhi'. 17408 * 'R_OR1K_TLS_GD_LO16' is requested using 'tlsgdlo'. 17409 * 'R_OR1K_TLS_GD_PG21' is requested using 'tldgd'. 17410 * 'R_OR1K_TLS_GD_LO13' is requested using 'tlsgdpo'. 17411 17412 * 'R_OR1K_TLS_LDM_HI16' is requested using 'tlsldmhi'. 17413 * 'R_OR1K_TLS_LDM_LO16' is requested using 'tlsldmlo'. 17414 * 'R_OR1K_TLS_LDM_PG21' is requested using 'tldldm'. 17415 * 'R_OR1K_TLS_LDM_LO13' is requested using 'tlsldmpo'. 17416 17417 * 'R_OR1K_TLS_LDO_HI16' is requested using 'dtpoffhi'. 17418 * 'R_OR1K_TLS_LDO_LO16' is requested using 'dtpofflo'. 17419 17420 * 'R_OR1K_TLS_IE_HI16' is requested using 'gottpoffhi'. 17421 * 'R_OR1K_TLS_IE_AHI16' is requested using 'gottpoffha'. 17422 * 'R_OR1K_TLS_IE_LO16' is requested using 'gottpofflo'. 17423 * 'R_OR1K_TLS_IE_PG21' is requested using 'gottp'. 17424 * 'R_OR1K_TLS_IE_LO13' is requested using 'gottppo'. 17425 17426 * 'R_OR1K_TLS_LE_HI16' is requested using 'tpoffhi'. 17427 * 'R_OR1K_TLS_LE_AHI16' is requested using 'tpoffha'. 17428 * 'R_OR1K_TLS_LE_LO16' is requested using 'tpofflo'. 17429 * 'R_OR1K_TLS_LE_SLO16' also is requested using 'tpofflo' depending 17430 on the instruction format. 17431 17432 Here are some example TLS model sequences. 17433 17434 First, General Dynamic: 17435 17436 l.movhi r17, tlsgdhi(symbol) 17437 l.ori r17, r17, tlsgdlo(symbol) 17438 l.add r17, r17, r16 17439 l.or r3, r17, r17 17440 l.jal plt(__tls_get_addr) 17441 l.nop 17442 17443 Initial Exec: 17444 17445 l.movhi r17, gottpoffhi(symbol) 17446 l.add r17, r17, r16 17447 l.lwz r17, gottpofflo(symbol)(r17) 17448 l.add r17, r17, r10 17449 l.lbs r17, 0(r17) 17450 17451 And finally, Local Exec: 17452 17453 l.movhi r17, tpoffha(symbol) 17454 l.add r17, r17, r10 17455 l.addi r17, r17, tpofflo(symbol) 17456 l.lbs r17, 0(r17) 17457 17458 17459File: as.info, Node: OpenRISC-Float, Next: OpenRISC-Directives, Prev: OpenRISC-Syntax, Up: OpenRISC-Dependent 17460 174619.33.2 Floating Point 17462--------------------- 17463 17464OpenRISC uses IEEE floating-point numbers. 17465 17466 17467File: as.info, Node: OpenRISC-Directives, Next: OpenRISC-Opcodes, Prev: OpenRISC-Float, Up: OpenRISC-Dependent 17468 174699.33.3 OpenRISC Machine Directives 17470---------------------------------- 17471 17472The OpenRISC version of 'as' supports the following additional machine 17473directives: 17474 17475'.align' 17476 This must be followed by the desired alignment in bytes. 17477 17478'.word' 17479 On the OpenRISC, the '.word' directive produces a 32 bit value. 17480 17481'.nodelay' 17482 On the OpenRISC, the '.nodelay' directive sets a flag in elf 17483 binaries indicating that the binary is generated catering for no 17484 delay slots. 17485 17486'.proc' 17487 This directive is ignored. Any text following it on the same line 17488 is also ignored. 17489 17490'.endproc' 17491 This directive is ignored. Any text following it on the same line 17492 is also ignored. 17493 17494 17495File: as.info, Node: OpenRISC-Opcodes, Prev: OpenRISC-Directives, Up: OpenRISC-Dependent 17496 174979.33.4 Opcodes 17498-------------- 17499 17500For detailed information on the OpenRISC machine instruction set, see 17501<http://www.openrisc.io/architecture/>. 17502 17503 'as' implements all the standard OpenRISC opcodes. 17504 17505 17506File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: OpenRISC-Dependent, Up: Machine Dependencies 17507 175089.34 PDP-11 Dependent Features 17509============================== 17510 17511* Menu: 17512 17513* PDP-11-Options:: Options 17514* PDP-11-Pseudos:: Assembler Directives 17515* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 17516* PDP-11-Mnemonics:: Instruction Naming 17517* PDP-11-Synthetic:: Synthetic Instructions 17518 17519 17520File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 17521 175229.34.1 Options 17523-------------- 17524 17525The PDP-11 version of 'as' has a rich set of machine dependent options. 17526 175279.34.1.1 Code Generation Options 17528................................ 17529 17530'-mpic | -mno-pic' 17531 Generate position-independent (or position-dependent) code. 17532 17533 The default is to generate position-independent code. 17534 175359.34.1.2 Instruction Set Extension Options 17536.......................................... 17537 17538These options enables or disables the use of extensions over the base 17539line instruction set as introduced by the first PDP-11 CPU: the KA11. 17540Most options come in two variants: a '-m'EXTENSION that enables 17541EXTENSION, and a '-mno-'EXTENSION that disables EXTENSION. 17542 17543 The default is to enable all extensions. 17544 17545'-mall | -mall-extensions' 17546 Enable all instruction set extensions. 17547 17548'-mno-extensions' 17549 Disable all instruction set extensions. 17550 17551'-mcis | -mno-cis' 17552 Enable (or disable) the use of the commercial instruction set, 17553 which consists of these instructions: 'ADDNI', 'ADDN', 'ADDPI', 17554 'ADDP', 'ASHNI', 'ASHN', 'ASHPI', 'ASHP', 'CMPCI', 'CMPC', 'CMPNI', 17555 'CMPN', 'CMPPI', 'CMPP', 'CVTLNI', 'CVTLN', 'CVTLPI', 'CVTLP', 17556 'CVTNLI', 'CVTNL', 'CVTNPI', 'CVTNP', 'CVTPLI', 'CVTPL', 'CVTPNI', 17557 'CVTPN', 'DIVPI', 'DIVP', 'L2DR', 'L3DR', 'LOCCI', 'LOCC', 'MATCI', 17558 'MATC', 'MOVCI', 'MOVC', 'MOVRCI', 'MOVRC', 'MOVTCI', 'MOVTC', 17559 'MULPI', 'MULP', 'SCANCI', 'SCANC', 'SKPCI', 'SKPC', 'SPANCI', 17560 'SPANC', 'SUBNI', 'SUBN', 'SUBPI', and 'SUBP'. 17561 17562'-mcsm | -mno-csm' 17563 Enable (or disable) the use of the 'CSM' instruction. 17564 17565'-meis | -mno-eis' 17566 Enable (or disable) the use of the extended instruction set, which 17567 consists of these instructions: 'ASHC', 'ASH', 'DIV', 'MARK', 17568 'MUL', 'RTT', 'SOB' 'SXT', and 'XOR'. 17569 17570'-mfis | -mkev11' 17571'-mno-fis | -mno-kev11' 17572 Enable (or disable) the use of the KEV11 floating-point 17573 instructions: 'FADD', 'FDIV', 'FMUL', and 'FSUB'. 17574 17575'-mfpp | -mfpu | -mfp-11' 17576'-mno-fpp | -mno-fpu | -mno-fp-11' 17577 Enable (or disable) the use of FP-11 floating-point instructions: 17578 'ABSF', 'ADDF', 'CFCC', 'CLRF', 'CMPF', 'DIVF', 'LDCFF', 'LDCIF', 17579 'LDEXP', 'LDF', 'LDFPS', 'MODF', 'MULF', 'NEGF', 'SETD', 'SETF', 17580 'SETI', 'SETL', 'STCFF', 'STCFI', 'STEXP', 'STF', 'STFPS', 'STST', 17581 'SUBF', and 'TSTF'. 17582 17583'-mlimited-eis | -mno-limited-eis' 17584 Enable (or disable) the use of the limited extended instruction 17585 set: 'MARK', 'RTT', 'SOB', 'SXT', and 'XOR'. 17586 17587 The -mno-limited-eis options also implies -mno-eis. 17588 17589'-mmfpt | -mno-mfpt' 17590 Enable (or disable) the use of the 'MFPT' instruction. 17591 17592'-mmultiproc | -mno-multiproc' 17593 Enable (or disable) the use of multiprocessor instructions: 17594 'TSTSET' and 'WRTLCK'. 17595 17596'-mmxps | -mno-mxps' 17597 Enable (or disable) the use of the 'MFPS' and 'MTPS' instructions. 17598 17599'-mspl | -mno-spl' 17600 Enable (or disable) the use of the 'SPL' instruction. 17601 17602 Enable (or disable) the use of the microcode instructions: 'LDUB', 17603 'MED', and 'XFC'. 17604 176059.34.1.3 CPU Model Options 17606.......................... 17607 17608These options enable the instruction set extensions supported by a 17609particular CPU, and disables all other extensions. 17610 17611'-mka11' 17612 KA11 CPU. Base line instruction set only. 17613 17614'-mkb11' 17615 KB11 CPU. Enable extended instruction set and 'SPL'. 17616 17617'-mkd11a' 17618 KD11-A CPU. Enable limited extended instruction set. 17619 17620'-mkd11b' 17621 KD11-B CPU. Base line instruction set only. 17622 17623'-mkd11d' 17624 KD11-D CPU. Base line instruction set only. 17625 17626'-mkd11e' 17627 KD11-E CPU. Enable extended instruction set, 'MFPS', and 'MTPS'. 17628 17629'-mkd11f | -mkd11h | -mkd11q' 17630 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction 17631 set, 'MFPS', and 'MTPS'. 17632 17633'-mkd11k' 17634 KD11-K CPU. Enable extended instruction set, 'LDUB', 'MED', 'MFPS', 17635 'MFPT', 'MTPS', and 'XFC'. 17636 17637'-mkd11z' 17638 KD11-Z CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', 17639 'MTPS', and 'SPL'. 17640 17641'-mf11' 17642 F11 CPU. Enable extended instruction set, 'MFPS', 'MFPT', and 17643 'MTPS'. 17644 17645'-mj11' 17646 J11 CPU. Enable extended instruction set, 'CSM', 'MFPS', 'MFPT', 17647 'MTPS', 'SPL', 'TSTSET', and 'WRTLCK'. 17648 17649'-mt11' 17650 T11 CPU. Enable limited extended instruction set, 'MFPS', and 17651 'MTPS'. 17652 176539.34.1.4 Machine Model Options 17654.............................. 17655 17656These options enable the instruction set extensions supported by a 17657particular machine model, and disables all other extensions. 17658 17659'-m11/03' 17660 Same as '-mkd11f'. 17661 17662'-m11/04' 17663 Same as '-mkd11d'. 17664 17665'-m11/05 | -m11/10' 17666 Same as '-mkd11b'. 17667 17668'-m11/15 | -m11/20' 17669 Same as '-mka11'. 17670 17671'-m11/21' 17672 Same as '-mt11'. 17673 17674'-m11/23 | -m11/24' 17675 Same as '-mf11'. 17676 17677'-m11/34' 17678 Same as '-mkd11e'. 17679 17680'-m11/34a' 17681 Ame as '-mkd11e' '-mfpp'. 17682 17683'-m11/35 | -m11/40' 17684 Same as '-mkd11a'. 17685 17686'-m11/44' 17687 Same as '-mkd11z'. 17688 17689'-m11/45 | -m11/50 | -m11/55 | -m11/70' 17690 Same as '-mkb11'. 17691 17692'-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 17693 Same as '-mj11'. 17694 17695'-m11/60' 17696 Same as '-mkd11k'. 17697 17698 17699File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 17700 177019.34.2 Assembler Directives 17702--------------------------- 17703 17704The PDP-11 version of 'as' has a few machine dependent assembler 17705directives. 17706 17707'.bss' 17708 Switch to the 'bss' section. 17709 17710'.even' 17711 Align the location counter to an even number. 17712 17713 17714File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 17715 177169.34.3 PDP-11 Assembly Language Syntax 17717-------------------------------------- 17718 17719'as' supports both DEC syntax and BSD syntax. The only difference is 17720that in DEC syntax, a '#' character is used to denote an immediate 17721constants, while in BSD syntax the character for this purpose is '$'. 17722 17723 general-purpose registers are named 'r0' through 'r7'. Mnemonic 17724alternatives for 'r6' and 'r7' are 'sp' and 'pc', respectively. 17725 17726 Floating-point registers are named 'ac0' through 'ac3', or 17727alternatively 'fr0' through 'fr3'. 17728 17729 Comments are started with a '#' or a '/' character, and extend to the 17730end of the line. (FIXME: clash with immediates?) 17731 17732 Multiple statements on the same line can be separated by the ';' 17733character. 17734 17735 17736File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 17737 177389.34.4 Instruction Naming 17739------------------------- 17740 17741Some instructions have alternative names. 17742 17743'BCC' 17744 'BHIS' 17745 17746'BCS' 17747 'BLO' 17748 17749'L2DR' 17750 'L2D' 17751 17752'L3DR' 17753 'L3D' 17754 17755'SYS' 17756 'TRAP' 17757 17758 17759File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 17760 177619.34.5 Synthetic Instructions 17762----------------------------- 17763 17764The 'JBR' and 'J'CC synthetic instructions are not supported yet. 17765 17766 17767File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 17768 177699.35 picoJava Dependent Features 17770================================ 17771 17772* Menu: 17773 17774* PJ Options:: Options 17775* PJ Syntax:: PJ Syntax 17776 17777 17778File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent 17779 177809.35.1 Options 17781-------------- 17782 17783'as' has two additional command-line options for the picoJava 17784architecture. 17785'-ml' 17786 This option selects little endian data output. 17787 17788'-mb' 17789 This option selects big endian data output. 17790 17791 17792File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent 17793 177949.35.2 PJ Syntax 17795---------------- 17796 17797* Menu: 17798 17799* PJ-Chars:: Special Characters 17800 17801 17802File: as.info, Node: PJ-Chars, Up: PJ Syntax 17803 178049.35.2.1 Special Characters 17805........................... 17806 17807The presence of a '!' or '/' on a line indicates the start of a comment 17808that extends to the end of the current line. 17809 17810 If a '#' appears as the first character of a line then the whole line 17811is treated as a comment, but in this case the line could also be a 17812logical line number directive (*note Comments::) or a preprocessor 17813control command (*note Preprocessing::). 17814 17815 The ';' character can be used to separate statements on the same 17816line. 17817 17818 17819File: as.info, Node: PPC-Dependent, Next: PRU-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 17820 178219.36 PowerPC Dependent Features 17822=============================== 17823 17824* Menu: 17825 17826* PowerPC-Opts:: Options 17827* PowerPC-Pseudo:: PowerPC Assembler Directives 17828* PowerPC-Syntax:: PowerPC Syntax 17829 17830 17831File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 17832 178339.36.1 Options 17834-------------- 17835 17836The PowerPC chip family includes several successive levels, using the 17837same core instruction set, but including a few additional instructions 17838at each level. There are exceptions to this however. For details on 17839what instructions each variant supports, please see the chip's 17840architecture reference manual. 17841 17842 The following table lists all available PowerPC options. 17843 17844'-a32' 17845 Generate ELF32 or XCOFF32. 17846 17847'-a64' 17848 Generate ELF64 or XCOFF64. 17849 17850'-K PIC' 17851 Set EF_PPC_RELOCATABLE_LIB in ELF flags. 17852 17853'-mpwrx | -mpwr2' 17854 Generate code for POWER/2 (RIOS2). 17855 17856'-mpwr' 17857 Generate code for POWER (RIOS1) 17858 17859'-m601' 17860 Generate code for PowerPC 601. 17861 17862'-mppc, -mppc32, -m603, -m604' 17863 Generate code for PowerPC 603/604. 17864 17865'-m403, -m405' 17866 Generate code for PowerPC 403/405. 17867 17868'-m440' 17869 Generate code for PowerPC 440. BookE and some 405 instructions. 17870 17871'-m464' 17872 Generate code for PowerPC 464. 17873 17874'-m476' 17875 Generate code for PowerPC 476. 17876 17877'-m7400, -m7410, -m7450, -m7455' 17878 Generate code for PowerPC 7400/7410/7450/7455. 17879 17880'-m750cl, -mgekko, -mbroadway' 17881 Generate code for PowerPC 750CL/Gekko/Broadway. 17882 17883'-m821, -m850, -m860' 17884 Generate code for PowerPC 821/850/860. 17885 17886'-mppc64, -m620' 17887 Generate code for PowerPC 620/625/630. 17888 17889'-me500, -me500x2' 17890 Generate code for Motorola e500 core complex. 17891 17892'-me500mc' 17893 Generate code for Freescale e500mc core complex. 17894 17895'-me500mc64' 17896 Generate code for Freescale e500mc64 core complex. 17897 17898'-me5500' 17899 Generate code for Freescale e5500 core complex. 17900 17901'-me6500' 17902 Generate code for Freescale e6500 core complex. 17903 17904'-mspe' 17905 Generate code for Motorola SPE instructions. 17906 17907'-mspe2' 17908 Generate code for Freescale SPE2 instructions. 17909 17910'-mtitan' 17911 Generate code for AppliedMicro Titan core complex. 17912 17913'-mppc64bridge' 17914 Generate code for PowerPC 64, including bridge insns. 17915 17916'-mbooke' 17917 Generate code for 32-bit BookE. 17918 17919'-ma2' 17920 Generate code for A2 architecture. 17921 17922'-me300' 17923 Generate code for PowerPC e300 family. 17924 17925'-maltivec' 17926 Generate code for processors with AltiVec instructions. 17927 17928'-mvle' 17929 Generate code for Freescale PowerPC VLE instructions. 17930 17931'-mvsx' 17932 Generate code for processors with Vector-Scalar (VSX) instructions. 17933 17934'-mhtm' 17935 Generate code for processors with Hardware Transactional Memory 17936 instructions. 17937 17938'-mpower4, -mpwr4' 17939 Generate code for Power4 architecture. 17940 17941'-mpower5, -mpwr5, -mpwr5x' 17942 Generate code for Power5 architecture. 17943 17944'-mpower6, -mpwr6' 17945 Generate code for Power6 architecture. 17946 17947'-mpower7, -mpwr7' 17948 Generate code for Power7 architecture. 17949 17950'-mpower8, -mpwr8' 17951 Generate code for Power8 architecture. 17952 17953'-mpower9, -mpwr9' 17954 Generate code for Power9 architecture. 17955 17956'-mcell' 17957'-mcell' 17958 Generate code for Cell Broadband Engine architecture. 17959 17960'-mcom' 17961 Generate code Power/PowerPC common instructions. 17962 17963'-many' 17964 Generate code for any architecture (PWR/PWRX/PPC). 17965 17966'-mregnames' 17967 Allow symbolic names for registers. 17968 17969'-mno-regnames' 17970 Do not allow symbolic names for registers. 17971 17972'-mrelocatable' 17973 Support for GCC's -mrelocatable option. 17974 17975'-mrelocatable-lib' 17976 Support for GCC's -mrelocatable-lib option. 17977 17978'-memb' 17979 Set PPC_EMB bit in ELF flags. 17980 17981'-mlittle, -mlittle-endian, -le' 17982 Generate code for a little endian machine. 17983 17984'-mbig, -mbig-endian, -be' 17985 Generate code for a big endian machine. 17986 17987'-msolaris' 17988 Generate code for Solaris. 17989 17990'-mno-solaris' 17991 Do not generate code for Solaris. 17992 17993'-nops=COUNT' 17994 If an alignment directive inserts more than COUNT nops, put a 17995 branch at the beginning to skip execution of the nops. 17996 17997 17998File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent 17999 180009.36.2 PowerPC Assembler Directives 18001----------------------------------- 18002 18003A number of assembler directives are available for PowerPC. The 18004following table is far from complete. 18005 18006'.machine "string"' 18007 This directive allows you to change the machine for which code is 18008 generated. '"string"' may be any of the -m cpu selection options 18009 (without the -m) enclosed in double quotes, '"push"', or '"pop"'. 18010 '.machine "push"' saves the currently selected cpu, which may be 18011 restored with '.machine "pop"'. 18012 18013 18014File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent 18015 180169.36.3 PowerPC Syntax 18017--------------------- 18018 18019* Menu: 18020 18021* PowerPC-Chars:: Special Characters 18022 18023 18024File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax 18025 180269.36.3.1 Special Characters 18027........................... 18028 18029The presence of a '#' on a line indicates the start of a comment that 18030extends to the end of the current line. 18031 18032 If a '#' appears as the first character of a line then the whole line 18033is treated as a comment, but in this case the line could also be a 18034logical line number directive (*note Comments::) or a preprocessor 18035control command (*note Preprocessing::). 18036 18037 If the assembler has been configured for the ppc-*-solaris* target 18038then the '!' character also acts as a line comment character. This can 18039be disabled via the '-mno-solaris' command-line option. 18040 18041 The ';' character can be used to separate statements on the same 18042line. 18043 18044 18045File: as.info, Node: PRU-Dependent, Next: RISC-V-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 18046 180479.37 PRU Dependent Features 18048=========================== 18049 18050* Menu: 18051 18052* PRU Options:: Options 18053* PRU Syntax:: Syntax 18054* PRU Relocations:: Relocations 18055* PRU Directives:: PRU Machine Directives 18056* PRU Opcodes:: Opcodes 18057 18058 18059File: as.info, Node: PRU Options, Next: PRU Syntax, Up: PRU-Dependent 18060 180619.37.1 Options 18062-------------- 18063 18064'-mlink-relax' 18065 Assume that LD would optimize LDI32 instructions by checking the 18066 upper 16 bits of the EXPRESSION. If they are all zeros, then LD 18067 would shorten the LDI32 instruction to a single LDI. In such case 18068 'as' will output DIFF relocations for diff expressions. 18069 18070'-mno-link-relax' 18071 Assume that LD would not optimize LDI32 instructions. As a 18072 consequence, DIFF relocations will not be emitted. 18073 18074'-mno-warn-regname-label' 18075 Do not warn if a label name matches a register name. Usually 18076 assembler programmers will want this warning to be emitted. C 18077 compilers may want to turn this off. 18078 18079 18080File: as.info, Node: PRU Syntax, Next: PRU Relocations, Prev: PRU Options, Up: PRU-Dependent 18081 180829.37.2 Syntax 18083------------- 18084 18085* Menu: 18086 18087* PRU Chars:: Special Characters 18088 18089 18090File: as.info, Node: PRU Chars, Up: PRU Syntax 18091 180929.37.2.1 Special Characters 18093........................... 18094 18095'#' and ';' are the line comment characters. 18096 18097 18098File: as.info, Node: PRU Relocations, Next: PRU Directives, Prev: PRU Syntax, Up: PRU-Dependent 18099 181009.37.3 PRU Machine Relocations 18101------------------------------ 18102 18103'%pmem(EXPRESSION)' 18104 Convert EXPRESSION from byte-address to a word-address. In other 18105 words, shift right by two. 18106 18107'%label(EXPRESSION)' 18108 Mark the given operand as a label. This is useful if you need to 18109 jump to a label that matches a register name. 18110 18111 r1: 18112 jmp r1 ; Will jump to register R1 18113 jmp %label(r1) ; Will jump to label r1 18114 18115 18116File: as.info, Node: PRU Directives, Next: PRU Opcodes, Prev: PRU Relocations, Up: PRU-Dependent 18117 181189.37.4 PRU Machine Directives 18119----------------------------- 18120 18121'.align EXPRESSION [, EXPRESSION]' 18122 This is the generic '.align' directive, however this aligns to a 18123 power of two. 18124 18125'.word EXPRESSION' 18126 Create an aligned constant 4 bytes in size. 18127 18128'.dword EXPRESSION' 18129 Create an aligned constant 8 bytes in size. 18130 18131'.2byte EXPRESSION' 18132 Create an unaligned constant 2 bytes in size. 18133 18134'.4byte EXPRESSION' 18135 Create an unaligned constant 4 bytes in size. 18136 18137'.8byte EXPRESSION' 18138 Create an unaligned constant 8 bytes in size. 18139 18140'.16byte EXPRESSION' 18141 Create an unaligned constant 16 bytes in size. 18142 18143'.set no_warn_regname_label' 18144 Do not output warnings when a label name matches a register name. 18145 Equivalent to passing the '-mno-warn-regname-label' command-line 18146 option. 18147 18148 18149File: as.info, Node: PRU Opcodes, Prev: PRU Directives, Up: PRU-Dependent 18150 181519.37.5 Opcodes 18152-------------- 18153 18154'as' implements all the standard PRU core V3 opcodes in the original 18155pasm assembler. Older cores are not supported by 'as'. 18156 18157 GAS also implements the LDI32 pseudo instruction for loading a 32-bit 18158immediate value into a register. 18159 18160 ldi32 sp, __stack_top 18161 ldi32 r14, 0x12345678 18162 18163 18164File: as.info, Node: RISC-V-Dependent, Next: RL78-Dependent, Prev: PRU-Dependent, Up: Machine Dependencies 18165 181669.38 RISC-V Dependent Features 18167============================== 18168 18169* Menu: 18170 18171* RISC-V-Options:: RISC-V Options 18172* RISC-V-Directives:: RISC-V Directives 18173* RISC-V-Formats:: RISC-V Instruction Formats 18174* RISC-V-ATTRIBUTE:: RISC-V Object Attribute 18175 18176 18177File: as.info, Node: RISC-V-Options, Next: RISC-V-Directives, Up: RISC-V-Dependent 18178 181799.38.1 RISC-V Options 18180--------------------- 18181 18182The following table lists all available RISC-V specific options. 18183 18184'-fpic' 18185'-fPIC' 18186 Generate position-independent code 18187 18188'-fno-pic' 18189 Don't generate position-independent code (default) 18190 18191'-march=ISA' 18192 Select the base isa, as specified by ISA. For example 18193 -march=rv32ima. 18194 18195'-mabi=ABI' 18196 Selects the ABI, which is either "ilp32" or "lp64", optionally 18197 followed by "f", "d", or "q" to indicate single-precision, 18198 double-precision, or quad-precision floating-point calling 18199 convention, or none to indicate the soft-float calling convention. 18200 Also, "ilp32" can optionally be followed by "e" to indicate the RVE 18201 ABI, which is always soft-float. 18202 18203'-mrelax' 18204 Take advantage of linker relaxations to reduce the number of 18205 instructions required to materialize symbol addresses. (default) 18206 18207'-mno-relax' 18208 Don't do linker relaxations. 18209 18210 18211File: as.info, Node: RISC-V-Directives, Next: RISC-V-Formats, Prev: RISC-V-Options, Up: RISC-V-Dependent 18212 182139.38.2 RISC-V Directives 18214------------------------ 18215 18216The following table lists all available RISC-V specific directives. 18217 18218'.align SIZE-LOG-2' 18219 Align to the given boundary, with the size given as log2 the number 18220 of bytes to align to. 18221 18222'.half VALUE' 18223'.word VALUE' 18224'.dword VALUE' 18225 Emits a half-word, word, or double-word value at the current 18226 position. 18227 18228'.dtprelword VALUE' 18229'.dtpreldword VALUE' 18230 Emits a DTP-relative word (or double-word) at the current position. 18231 This is meant to be used by the compiler in shared libraries for 18232 DWARF debug info for thread local variables. 18233 18234'.bss' 18235 Sets the current section to the BSS section. 18236 18237'.uleb128 VALUE' 18238'.sleb128 VALUE' 18239 Emits a signed or unsigned LEB128 value at the current position. 18240 This only accepts constant expressions, because symbol addresses 18241 can change with relaxation, and we don't support relocations to 18242 modify LEB128 values at link time. 18243 18244'.option ARGUMENT' 18245 Modifies RISC-V specific assembler options inline with the assembly 18246 code. This is used when particular instruction sequences must be 18247 assembled with a specific set of options. For example, since we 18248 relax addressing sequences to shorter GP-relative sequences when 18249 possible the initial load of GP must not be relaxed and should be 18250 emitted as something like 18251 18252 .option push 18253 .option norelax 18254 la gp, __global_pointer$ 18255 .option pop 18256 18257 in order to produce after linker relaxation the expected 18258 18259 auipc gp, %pcrel_hi(__global_pointer$) 18260 addi gp, gp, %pcrel_lo(__global_pointer$) 18261 18262 instead of just 18263 18264 addi gp, gp, 0 18265 18266 It's not expected that options are changed in this manner during 18267 regular use, but there are a handful of esoteric cases like the one 18268 above where users need to disable particular features of the 18269 assembler for particular code sequences. The complete list of 18270 option arguments is shown below: 18271 18272 'push' 18273 'pop' 18274 Pushes or pops the current option stack. These should be used 18275 whenever changing an option in line with assembly code in 18276 order to ensure the user's command-line options are respected 18277 for the bulk of the file being assembled. 18278 18279 'rvc' 18280 'norvc' 18281 Enables or disables the generation of compressed instructions. 18282 Instructions are opportunistically compressed by the RISC-V 18283 assembler when possible, but sometimes this behavior is not 18284 desirable. 18285 18286 'pic' 18287 'nopic' 18288 Enables or disables position-independent code generation. 18289 Unless you really know what you're doing, this should only be 18290 at the top of a file. 18291 18292 'relax' 18293 'norelax' 18294 Enables or disables relaxation. The RISC-V assembler and 18295 linker opportunistically relax some code sequences, but 18296 sometimes this behavior is not desirable. 18297 18298'.insn VALUE' 18299'.insn VALUE' 18300 This directive permits the numeric representation of an 18301 instructions and makes the assembler insert the operands according 18302 to one of the instruction formats for '.insn' (*note 18303 RISC-V-Formats::). For example, the instruction 'add a0, a1, a2' 18304 could be written as '.insn r 0x33, 0, 0, a0, a1, a2'. 18305 18306'.attribute TAG, VALUE' 18307 Set the object attribute TAG to VALUE. 18308 18309 The TAG is either an attribute number, or one of the following: 18310 'Tag_RISCV_arch', 'Tag_RISCV_stack_align', 18311 'Tag_RISCV_unaligned_access', 'Tag_RISCV_priv_spec', 18312 'Tag_RISCV_priv_spec_minor', 'Tag_RISCV_priv_spec_revision'. 18313 18314 18315File: as.info, Node: RISC-V-Formats, Next: RISC-V-ATTRIBUTE, Prev: RISC-V-Directives, Up: RISC-V-Dependent 18316 183179.38.3 Instruction Formats 18318-------------------------- 18319 18320The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12 18321instruction formats where some of the formats have multiple variants. 18322For the '.insn' pseudo directive the assembler recognizes some of the 18323formats. Typically, the most general variant of the instruction format 18324is used by the '.insn' directive. 18325 18326 The following table lists the abbreviations used in the table of 18327instruction formats: 18328 18329 opcode Unsigned immediate or opcode name for 7-bits opcode. 18330 opcode2 Unsigned immediate or opcode name for 2-bits opcode. 18331 func7 Unsigned immediate for 7-bits function code. 18332 func6 Unsigned immediate for 6-bits function code. 18333 func4 Unsigned immediate for 4-bits function code. 18334 func3 Unsigned immediate for 3-bits function code. 18335 func2 Unsigned immediate for 2-bits function code. 18336 rd Destination register number for operand x, can be GPR or FPR. 18337 rd' Destination register number for operand x, 18338 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 18339 rs1 First source register number for operand x, can be GPR or FPR. 18340 rs1' First source register number for operand x, 18341 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 18342 rs2 Second source register number for operand x, can be GPR or FPR. 18343 rs2' Second source register number for operand x, 18344 only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5. 18345 simm12 Sign-extended 12-bit immediate for operand x. 18346 simm20 Sign-extended 20-bit immediate for operand x. 18347 simm6 Sign-extended 6-bit immediate for operand x. 18348 uimm8 Unsigned 8-bit immediate for operand x. 18349 symbol Symbol or lable reference for operand x. 18350 18351 The following table lists all available opcode name: 18352 18353'C0' 18354'C1' 18355'C2' 18356 Opcode space for compressed instructions. 18357 18358'LOAD' 18359 Opcode space for load instructions. 18360 18361'LOAD_FP' 18362 Opcode space for floating-point load instructions. 18363 18364'STORE' 18365 Opcode space for store instructions. 18366 18367'STORE_FP' 18368 Opcode space for floating-point store instructions. 18369 18370'AUIPC' 18371 Opcode space for auipc instruction. 18372 18373'LUI' 18374 Opcode space for lui instruction. 18375 18376'BRANCH' 18377 Opcode space for branch instructions. 18378 18379'JAL' 18380 Opcode space for jal instruction. 18381 18382'JALR' 18383 Opcode space for jalr instruction. 18384 18385'OP' 18386 Opcode space for ALU instructions. 18387 18388'OP_32' 18389 Opcode space for 32-bits ALU instructions. 18390 18391'OP_IMM' 18392 Opcode space for ALU with immediate instructions. 18393 18394'OP_IMM_32' 18395 Opcode space for 32-bits ALU with immediate instructions. 18396 18397'OP_FP' 18398 Opcode space for floating-point operation instructions. 18399 18400'MADD' 18401 Opcode space for madd instruction. 18402 18403'MSUB' 18404 Opcode space for msub instruction. 18405 18406'NMADD' 18407 Opcode space for nmadd instruction. 18408 18409'NMSUB' 18410 Opcode space for msub instruction. 18411 18412'AMO' 18413 Opcode space for atomic memory operation instructions. 18414 18415'MISC_MEM' 18416 Opcode space for misc instructions. 18417 18418'SYSTEM' 18419 Opcode space for system instructions. 18420 18421'CUSTOM_0' 18422'CUSTOM_1' 18423'CUSTOM_2' 18424'CUSTOM_3' 18425 Opcode space for customize instructions. 18426 18427 An instruction is two or four bytes in length and must be aligned on 18428a 2 byte boundary. The first two bits of the instruction specify the 18429length of the instruction, 00, 01 and 10 indicates a two byte 18430instruction, 11 indicates a four byte instruction. 18431 18432 The following table lists the RISC-V instruction formats that are 18433available with the '.insn' pseudo directive: 18434 18435'R type: .insn r opcode, func3, func7, rd, rs1, rs2' 18436 +-------+-----+-----+-------+----+-------------+ 18437 | func7 | rs2 | rs1 | func3 | rd | opcode | 18438 +-------+-----+-----+-------+----+-------------+ 18439 31 25 20 15 12 7 0 18440 18441'R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3' 18442'R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3' 18443 +-----+-------+-----+-----+-------+----+-------------+ 18444 | rs3 | func2 | rs2 | rs1 | func3 | rd | opcode | 18445 +-----+-------+-----+-----+-------+----+-------------+ 18446 31 27 25 20 15 12 7 0 18447 18448'I type: .insn i opcode, func3, rd, rs1, simm12' 18449 +-------------+-----+-------+----+-------------+ 18450 | simm12 | rs1 | func3 | rd | opcode | 18451 +-------------+-----+-------+----+-------------+ 18452 31 20 15 12 7 0 18453 18454'S type: .insn s opcode, func3, rd, rs1, simm12' 18455 +--------------+-----+-----+-------+-------------+-------------+ 18456 | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode | 18457 +--------------+-----+-----+-------+-------------+-------------+ 18458 31 25 20 15 12 7 0 18459 18460'SB type: .insn sb opcode, func3, rd, rs1, symbol' 18461'SB type: .insn sb opcode, func3, rd, simm12(rs1)' 18462'B type: .insn s opcode, func3, rd, rs1, symbol' 18463'B type: .insn s opcode, func3, rd, simm12(rs1)' 18464 +------------+--------------+-----+-----+-------+-------------+-------------+--------+ 18465 | simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode | 18466 +------------+--------------+-----+-----+-------+-------------+-------------+--------+ 18467 31 30 25 20 15 12 7 0 18468 18469'U type: .insn u opcode, rd, simm20' 18470 +---------------------------+----+-------------+ 18471 | simm20 | rd | opcode | 18472 +---------------------------+----+-------------+ 18473 31 12 7 0 18474 18475'UJ type: .insn uj opcode, rd, symbol' 18476'J type: .insn j opcode, rd, symbol' 18477 +------------+--------------+------------+---------------+----+-------------+ 18478 | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode | 18479 +------------+--------------+------------+---------------+----+-------------+ 18480 31 30 21 20 12 7 0 18481 18482'CR type: .insn cr opcode2, func4, rd, rs2' 18483 +---------+--------+-----+---------+ 18484 | func4 | rd/rs1 | rs2 | opcode2 | 18485 +---------+--------+-----+---------+ 18486 15 12 7 2 0 18487 18488'CI type: .insn ci opcode2, func3, rd, simm6' 18489 +---------+-----+--------+-----+---------+ 18490 | func3 | imm | rd/rs1 | imm | opcode2 | 18491 +---------+-----+--------+-----+---------+ 18492 15 13 12 7 2 0 18493 18494'CIW type: .insn ciw opcode2, func3, rd, uimm8' 18495 +---------+--------------+-----+---------+ 18496 | func3 | imm | rd' | opcode2 | 18497 +---------+--------------+-----+---------+ 18498 15 13 7 2 0 18499 18500'CA type: .insn ca opcode2, func6, func2, rd, rs2' 18501 +---------+----------+-------+------+--------+ 18502 | func6 | rd'/rs1' | func2 | rs2' | opcode | 18503 +---------+----------+-------+------+--------+ 18504 15 10 7 5 2 0 18505 18506'CB type: .insn cb opcode2, func3, rs1, symbol' 18507 +---------+--------+------+--------+---------+ 18508 | func3 | offset | rs1' | offset | opcode2 | 18509 +---------+--------+------+--------+---------+ 18510 15 13 10 7 2 0 18511 18512'CJ type: .insn cj opcode2, symbol' 18513 +---------+--------------------+---------+ 18514 | func3 | jump target | opcode2 | 18515 +---------+--------------------+---------+ 18516 15 13 7 2 0 18517 18518 For the complete list of all instruction format variants see The 18519RISC-V Instruction Set Manual Volume I: User-Level ISA. 18520 18521 18522File: as.info, Node: RISC-V-ATTRIBUTE, Prev: RISC-V-Formats, Up: RISC-V-Dependent 18523 185249.38.4 RISC-V Object Attribute 18525------------------------------ 18526 18527RISC-V attributes have a string value if the tag number is odd and an 18528integer value if the tag number is even. 18529 18530Tag_RISCV_stack_align (4) 18531 Tag_RISCV_strict_align records the N-byte stack alignment for this 18532 object. The default value is 16 for RV32I or RV64I, and 4 for 18533 RV32E. 18534 18535 The smallest value will be used if object files with different 18536 Tag_RISCV_stack_align values are merged. 18537 18538Tag_RISCV_arch (5) 18539 Tag_RISCV_arch contains a string for the target architecture taken 18540 from the option '-march'. Different architectures will be 18541 integrated into a superset when object files are merged. 18542 18543 Note that the version information of the target architecture must 18544 be presented explicitly in the attribute and abbreviations must be 18545 expanded. The version information, if not given by '-march', must 18546 be in accordance with the default specified by the tool. For 18547 example, the architecture 'RV32I' has to be recorded in the 18548 attribute as 'RV32I2P0' in which '2P0' stands for the default 18549 version of its base ISA. On the other hand, the architecture 18550 'RV32G' has to be presented as 'RV32I2P0_M2P0_A2P0_F2P0_D2P0' in 18551 which the abbreviation 'G' is expanded to the 'IMAFD' combination 18552 with default versions of the standard extensions. 18553 18554Tag_RISCV_unaligned_access (6) 18555 Tag_RISCV_unaligned_access is 0 for files that do not allow any 18556 unaligned memory accesses, and 1 for files that do allow unaligned 18557 memory accesses. 18558 18559Tag_RISCV_priv_spec (8) 18560Tag_RISCV_priv_spec_minor (10) 18561Tag_RISCV_priv_spec_revision (12) 18562 Tag_RISCV_priv_spec contains the major/minor/revision version 18563 information of the privileged specification. It will report errors 18564 if object files of different privileged specification versions are 18565 merged. 18566 18567 18568File: as.info, Node: RL78-Dependent, Next: RX-Dependent, Prev: RISC-V-Dependent, Up: Machine Dependencies 18569 185709.39 RL78 Dependent Features 18571============================ 18572 18573* Menu: 18574 18575* RL78-Opts:: RL78 Assembler Command-line Options 18576* RL78-Modifiers:: Symbolic Operand Modifiers 18577* RL78-Directives:: Assembler Directives 18578* RL78-Syntax:: Syntax 18579 18580 18581File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent 18582 185839.39.1 RL78 Options 18584------------------- 18585 18586'relax' 18587 Enable support for link-time relaxation. 18588 18589'norelax' 18590 Disable support for link-time relaxation (default). 18591 18592'mg10' 18593 Mark the generated binary as targeting the G10 variant of the RL78 18594 architecture. 18595 18596'mg13' 18597 Mark the generated binary as targeting the G13 variant of the RL78 18598 architecture. 18599 18600'mg14' 18601'mrl78' 18602 Mark the generated binary as targeting the G14 variant of the RL78 18603 architecture. This is the default. 18604 18605'm32bit-doubles' 18606 Mark the generated binary as one that uses 32-bits to hold the 18607 'double' floating point type. This is the default. 18608 18609'm64bit-doubles' 18610 Mark the generated binary as one that uses 64-bits to hold the 18611 'double' floating point type. 18612 18613 18614File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent 18615 186169.39.2 Symbolic Operand Modifiers 18617--------------------------------- 18618 18619The RL78 has three modifiers that adjust the relocations used by the 18620linker: 18621 18622'%lo16()' 18623 18624 When loading a 20-bit (or wider) address into registers, this 18625 modifier selects the 16 least significant bits. 18626 18627 movw ax,#%lo16(_sym) 18628 18629'%hi16()' 18630 18631 When loading a 20-bit (or wider) address into registers, this 18632 modifier selects the 16 most significant bits. 18633 18634 movw ax,#%hi16(_sym) 18635 18636'%hi8()' 18637 18638 When loading a 20-bit (or wider) address into registers, this 18639 modifier selects the 8 bits that would go into CS or ES (i.e. bits 18640 23..16). 18641 18642 mov es, #%hi8(_sym) 18643 18644 18645File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent 18646 186479.39.3 Assembler Directives 18648--------------------------- 18649 18650In addition to the common directives, the RL78 adds these: 18651 18652'.double' 18653 Output a constant in "double" format, which is either a 32-bit or a 18654 64-bit floating point value, depending upon the setting of the 18655 '-m32bit-doubles'|'-m64bit-doubles' command-line option. 18656 18657'.bss' 18658 Select the BSS section. 18659 18660'.3byte' 18661 Output a constant value in a three byte format. 18662 18663'.int' 18664'.word' 18665 Output a constant value in a four byte format. 18666 18667 18668File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent 18669 186709.39.4 Syntax for the RL78 18671-------------------------- 18672 18673* Menu: 18674 18675* RL78-Chars:: Special Characters 18676 18677 18678File: as.info, Node: RL78-Chars, Up: RL78-Syntax 18679 186809.39.4.1 Special Characters 18681........................... 18682 18683The presence of a ';' appearing anywhere on a line indicates the start 18684of a comment that extends to the end of that line. 18685 18686 If a '#' appears as the first character of a line then the whole line 18687is treated as a comment, but in this case the line can also be a logical 18688line number directive (*note Comments::) or a preprocessor control 18689command (*note Preprocessing::). 18690 18691 The '|' character can be used to separate statements on the same 18692line. 18693 18694 18695File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies 18696 186979.40 RX Dependent Features 18698========================== 18699 18700* Menu: 18701 18702* RX-Opts:: RX Assembler Command-line Options 18703* RX-Modifiers:: Symbolic Operand Modifiers 18704* RX-Directives:: Assembler Directives 18705* RX-Float:: Floating Point 18706* RX-Syntax:: Syntax 18707 18708 18709File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 18710 187119.40.1 RX Options 18712----------------- 18713 18714The Renesas RX port of 'as' has a few target specific command-line 18715options: 18716 18717'-m32bit-doubles' 18718 This option controls the ABI and indicates to use a 32-bit float 18719 ABI. It has no effect on the assembled instructions, but it does 18720 influence the behaviour of the '.double' pseudo-op. This is the 18721 default. 18722 18723'-m64bit-doubles' 18724 This option controls the ABI and indicates to use a 64-bit float 18725 ABI. It has no effect on the assembled instructions, but it does 18726 influence the behaviour of the '.double' pseudo-op. 18727 18728'-mbig-endian' 18729 This option controls the ABI and indicates to use a big-endian data 18730 ABI. It has no effect on the assembled instructions, but it does 18731 influence the behaviour of the '.short', '.hword', '.int', '.word', 18732 '.long', '.quad' and '.octa' pseudo-ops. 18733 18734'-mlittle-endian' 18735 This option controls the ABI and indicates to use a little-endian 18736 data ABI. It has no effect on the assembled instructions, but it 18737 does influence the behaviour of the '.short', '.hword', '.int', 18738 '.word', '.long', '.quad' and '.octa' pseudo-ops. This is the 18739 default. 18740 18741'-muse-conventional-section-names' 18742 This option controls the default names given to the code (.text), 18743 initialised data (.data) and uninitialised data sections (.bss). 18744 18745'-muse-renesas-section-names' 18746 This option controls the default names given to the code (.P), 18747 initialised data (.D_1) and uninitialised data sections (.B_1). 18748 This is the default. 18749 18750'-msmall-data-limit' 18751 This option tells the assembler that the small data limit feature 18752 of the RX port of GCC is being used. This results in the assembler 18753 generating an undefined reference to a symbol called '__gp' for use 18754 by the relocations that are needed to support the small data limit 18755 feature. This option is not enabled by default as it would 18756 otherwise pollute the symbol table. 18757 18758'-mpid' 18759 This option tells the assembler that the position independent data 18760 of the RX port of GCC is being used. This results in the assembler 18761 generating an undefined reference to a symbol called '__pid_base', 18762 and also setting the RX_PID flag bit in the e_flags field of the 18763 ELF header of the object file. 18764 18765'-mint-register=NUM' 18766 This option tells the assembler how many registers have been 18767 reserved for use by interrupt handlers. This is needed in order to 18768 compute the correct values for the '%gpreg' and '%pidreg' meta 18769 registers. 18770 18771'-mgcc-abi' 18772 This option tells the assembler that the old GCC ABI is being used 18773 by the assembled code. With this version of the ABI function 18774 arguments that are passed on the stack are aligned to a 32-bit 18775 boundary. 18776 18777'-mrx-abi' 18778 This option tells the assembler that the official RX ABI is being 18779 used by the assembled code. With this version of the ABI function 18780 arguments that are passed on the stack are aligned to their natural 18781 alignments. This option is the default. 18782 18783'-mcpu=NAME' 18784 This option tells the assembler the target CPU type. Currently the 18785 'rx100', 'rx200', 'rx600', 'rx610', 'rxv2', 'rxv3' and 'rxv3-dfpu' 18786 are recognised as valid cpu names. Attempting to assemble an 18787 instructionnot supported by the indicated cpu type will result in 18788 an error message being generated. 18789 18790'-mno-allow-string-insns' 18791 This option tells the assembler to mark the object file that it is 18792 building as one that does not use the string instructions 'SMOVF', 18793 'SCMPU', 'SMOVB', 'SMOVU', 'SUNTIL' 'SWHILE' or the 'RMPA' 18794 instruction. In addition the mark tells the linker to complain if 18795 an attempt is made to link the binary with another one that does 18796 use any of these instructions. 18797 18798 Note - the inverse of this option, '-mallow-string-insns', is not 18799 needed. The assembler automatically detects the use of the the 18800 instructions in the source code and labels the resulting object 18801 file appropriately. If no string instructions are detected then 18802 the object file is labelled as being one that can be linked with 18803 either string-using or string-banned object files. 18804 18805 18806File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 18807 188089.40.2 Symbolic Operand Modifiers 18809--------------------------------- 18810 18811The assembler supports one modifier when using symbol addresses in RX 18812instruction operands. The general syntax is the following: 18813 18814 %gp(symbol) 18815 18816 The modifier returns the offset from the __GP symbol to the specified 18817symbol as a 16-bit value. The intent is that this offset should be used 18818in a register+offset move instruction when generating references to 18819small data. Ie, like this: 18820 18821 mov.W %gp(_foo)[%gpreg], r1 18822 18823 The assembler also supports two meta register names which can be used 18824to refer to registers whose values may not be known to the programmer. 18825These meta register names are: 18826 18827'%gpreg' 18828 The small data address register. 18829 18830'%pidreg' 18831 The PID base address register. 18832 18833 Both registers normally have the value r13, but this can change if 18834some registers have been reserved for use by interrupt handlers or if 18835both the small data limit and position independent data features are 18836being used at the same time. 18837 18838 18839File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 18840 188419.40.3 Assembler Directives 18842--------------------------- 18843 18844The RX version of 'as' has the following specific assembler directives: 18845 18846'.3byte' 18847 Inserts a 3-byte value into the output file at the current 18848 location. 18849 18850'.fetchalign' 18851 If the next opcode following this directive spans a fetch line 18852 boundary (8 byte boundary), the opcode is aligned to that boundary. 18853 If the next opcode does not span a fetch line, this directive has 18854 no effect. Note that one or more labels may be between this 18855 directive and the opcode; those labels are aligned as well. Any 18856 inserted bytes due to alignment will form a NOP opcode. 18857 18858 18859File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent 18860 188619.40.4 Floating Point 18862--------------------- 18863 18864The floating point formats generated by directives are these. 18865 18866'.float' 18867 'Single' precision (32-bit) floating point constants. 18868 18869'.double' 18870 If the '-m64bit-doubles' command-line option has been specified 18871 then then 'double' directive generates 'double' precision (64-bit) 18872 floating point constants, otherwise it generates 'single' precision 18873 (32-bit) floating point constants. To force the generation of 18874 64-bit floating point constants used the 'dc.d' directive instead. 18875 18876 18877File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent 18878 188799.40.5 Syntax for the RX 18880------------------------ 18881 18882* Menu: 18883 18884* RX-Chars:: Special Characters 18885 18886 18887File: as.info, Node: RX-Chars, Up: RX-Syntax 18888 188899.40.5.1 Special Characters 18890........................... 18891 18892The presence of a ';' appearing anywhere on a line indicates the start 18893of a comment that extends to the end of that line. 18894 18895 If a '#' appears as the first character of a line then the whole line 18896is treated as a comment, but in this case the line can also be a logical 18897line number directive (*note Comments::) or a preprocessor control 18898command (*note Preprocessing::). 18899 18900 The '!' character can be used to separate statements on the same 18901line. 18902 18903 18904File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 18905 189069.41 IBM S/390 Dependent Features 18907================================= 18908 18909The s390 version of 'as' supports two architectures modes and eleven 18910chip levels. The architecture modes are the Enterprise System 18911Architecture (ESA) and the newer z/Architecture mode. The chip levels 18912are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec 18913(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or 18914arch11), z14 (or arch12), and z15 (or arch13). 18915 18916* Menu: 18917 18918* s390 Options:: Command-line Options. 18919* s390 Characters:: Special Characters. 18920* s390 Syntax:: Assembler Instruction syntax. 18921* s390 Directives:: Assembler Directives. 18922* s390 Floating Point:: Floating Point. 18923 18924 18925File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 18926 189279.41.1 Options 18928-------------- 18929 18930The following table lists all available s390 specific options: 18931 18932'-m31 | -m64' 18933 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 18934 18935 These options are only available with the ELF object file format, 18936 and require that the necessary BFD support has been included (on a 18937 31-bit platform you must add -enable-64-bit-bfd on the call to the 18938 configure script to enable 64-bit usage and use s390x as target 18939 platform). 18940 18941'-mesa | -mzarch' 18942 Select the architecture mode, either the Enterprise System 18943 Architecture (esa) mode or the z/Architecture mode (zarch). 18944 18945 The 64-bit instructions are only available with the z/Architecture 18946 mode. The combination of '-m64' and '-mesa' results in a warning 18947 message. 18948 18949'-march=CPU' 18950 This option specifies the target processor. The following 18951 processor names are recognized: 'g5' (or 'arch3'), 'g6', 'z900' (or 18952 'arch5'), 'z990' (or 'arch6'), 'z9-109', 'z9-ec' (or 'arch7'), 18953 'z10' (or 'arch8'), 'z196' (or 'arch9'), 'zEC12' (or 'arch10'), 18954 'z13' (or 'arch11'), 'z14' (or 'arch12'), and 'z15' (or 'arch13'). 18955 18956 Assembling an instruction that is not supported on the target 18957 processor results in an error message. 18958 18959 The processor names starting with 'arch' refer to the edition 18960 number in the Principle of Operations manual. They can be used as 18961 alternate processor names and have been added for compatibility 18962 with the IBM XL compiler. 18963 18964 'arch3', 'g5' and 'g6' cannot be used with the '-mzarch' option 18965 since the z/Architecture mode is not supported on these processor 18966 levels. 18967 18968 There is no 'arch4' option supported. 'arch4' matches 18969 '-march=arch5 -mesa'. 18970 18971'-mregnames' 18972 Allow symbolic names for registers. 18973 18974'-mno-regnames' 18975 Do not allow symbolic names for registers. 18976 18977'-mwarn-areg-zero' 18978 Warn whenever the operand for a base or index register has been 18979 specified but evaluates to zero. This can indicate the misuse of 18980 general purpose register 0 as an address register. 18981 18982 18983File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 18984 189859.41.2 Special Characters 18986------------------------- 18987 18988'#' is the line comment character. 18989 18990 If a '#' appears as the first character of a line then the whole line 18991is treated as a comment, but in this case the line could also be a 18992logical line number directive (*note Comments::) or a preprocessor 18993control command (*note Preprocessing::). 18994 18995 The ';' character can be used instead of a newline to separate 18996statements. 18997 18998 18999File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 19000 190019.41.3 Instruction syntax 19002------------------------- 19003 19004The assembler syntax closely follows the syntax outlined in Enterprise 19005Systems Architecture/390 Principles of Operation (SA22-7201) and the 19006z/Architecture Principles of Operation (SA22-7832). 19007 19008 Each instruction has two major parts, the instruction mnemonic and 19009the instruction operands. The instruction format varies. 19010 19011* Menu: 19012 19013* s390 Register:: Register Naming 19014* s390 Mnemonics:: Instruction Mnemonics 19015* s390 Operands:: Instruction Operands 19016* s390 Formats:: Instruction Formats 19017* s390 Aliases:: Instruction Aliases 19018* s390 Operand Modifier:: Instruction Operand Modifier 19019* s390 Instruction Marker:: Instruction Marker 19020* s390 Literal Pool Entries:: Literal Pool Entries 19021 19022 19023File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 19024 190259.41.3.1 Register naming 19026........................ 19027 19028The 'as' recognizes a number of predefined symbols for the various 19029processor registers. A register specification in one of the instruction 19030formats is an unsigned integer between 0 and 15. The specific 19031instruction and the position of the register in the instruction format 19032denotes the type of the register. The register symbols are prefixed 19033with '%': 19034 19035 %rN the 16 general purpose registers, 0 <= N <= 15 19036 %fN the 16 floating point registers, 0 <= N <= 15 19037 %aN the 16 access registers, 0 <= N <= 15 19038 %cN the 16 control registers, 0 <= N <= 15 19039 %lit an alias for the general purpose register %r13 19040 %sp an alias for the general purpose register %r15 19041 19042 19043File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 19044 190459.41.3.2 Instruction Mnemonics 19046.............................. 19047 19048All instructions documented in the Principles of Operation are supported 19049with the mnemonic and order of operands as described. The instruction 19050mnemonic identifies the instruction format (*note s390 Formats::) and 19051the specific operation code for the instruction. For example, the 'lr' 19052mnemonic denotes the instruction format 'RR' with the operation code 19053'0x18'. 19054 19055 The definition of the various mnemonics follows a scheme, where the 19056first character usually hint at the type of the instruction: 19057 19058 a add instruction, for example 'al' for add logical 32-bit 19059 b branch instruction, for example 'bc' for branch on condition 19060 c compare or convert instruction, for example 'cr' for compare 19061 register 32-bit 19062 d divide instruction, for example 'dlr' devide logical register 19063 64-bit to 32-bit 19064 i insert instruction, for example 'ic' insert character 19065 l load instruction, for example 'ltr' load and test register 19066 mv move instruction, for example 'mvc' move character 19067 m multiply instruction, for example 'mh' multiply halfword 19068 n and instruction, for example 'ni' and immediate 19069 o or instruction, for example 'oc' or character 19070 sla, sll shift left single instruction 19071 sra, srl shift right single instruction 19072 st store instruction, for example 'stm' store multiple 19073 s subtract instruction, for example 'slr' subtract 19074 logical 32-bit 19075 t test or translate instruction, of example 'tm' test under mask 19076 x exclusive or instruction, for example 'xc' exclusive or 19077 character 19078 19079 Certain characters at the end of the mnemonic may describe a property 19080of the instruction: 19081 19082 c the instruction uses a 8-bit character operand 19083 f the instruction extends a 32-bit operand to 64 bit 19084 g the operands are treated as 64-bit values 19085 h the operand uses a 16-bit halfword operand 19086 i the instruction uses an immediate operand 19087 l the instruction uses unsigned, logical operands 19088 m the instruction uses a mask or operates on multiple values 19089 r if r is the last character, the instruction operates on registers 19090 y the instruction uses 20-bit displacements 19091 19092 There are many exceptions to the scheme outlined in the above lists, 19093in particular for the privileged instructions. For non-privileged 19094instruction it works quite well, for example the instruction 'clgfr' c: 19095compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to 1909664-bit extension, r: register operands. The instruction compares an 1909764-bit value in a register with the zero extended 32-bit value from a 19098second register. For a complete list of all mnemonics see appendix B in 19099the Principles of Operation. 19100 19101 19102File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 19103 191049.41.3.3 Instruction Operands 19105............................. 19106 19107Instruction operands can be grouped into three classes, operands located 19108in registers, immediate operands, and operands in storage. 19109 19110 A register operand can be located in general, floating-point, access, 19111or control register. The register is identified by a four-bit field. 19112The field containing the register operand is called the R field. 19113 19114 Immediate operands are contained within the instruction and can have 191158, 16 or 32 bits. The field containing the immediate operand is called 19116the I field. Dependent on the instruction the I field is either signed 19117or unsigned. 19118 19119 A storage operand consists of an address and a length. The address 19120of a storage operands can be specified in any of these ways: 19121 19122 * The content of a single general R 19123 * The sum of the content of a general register called the base 19124 register B plus the content of a displacement field D 19125 * The sum of the contents of two general registers called the index 19126 register X and the base register B plus the content of a 19127 displacement field 19128 * The sum of the current instruction address and a 32-bit signed 19129 immediate field multiplied by two. 19130 19131 The length of a storage operand can be: 19132 19133 * Implied by the instruction 19134 * Specified by a bitmask 19135 * Specified by a four-bit or eight-bit length field L 19136 * Specified by the content of a general register 19137 19138 The notation for storage operand addresses formed from multiple 19139fields is as follows: 19140 19141'Dn(Bn)' 19142 the address for operand number n is formed from the content of 19143 general register Bn called the base register and the displacement 19144 field Dn. 19145'Dn(Xn,Bn)' 19146 the address for operand number n is formed from the content of 19147 general register Xn called the index register, general register Bn 19148 called the base register and the displacement field Dn. 19149'Dn(Ln,Bn)' 19150 the address for operand number n is formed from the content of 19151 general register Bn called the base register and the displacement 19152 field Dn. The length of the operand n is specified by the field 19153 Ln. 19154 19155 The base registers Bn and the index registers Xn of a storage operand 19156can be skipped. If Bn and Xn are skipped, a zero will be stored to the 19157operand field. The notation changes as follows: 19158 19159 full notation short notation 19160 ---------------------------------------------- 19161 Dn(0,Bn) Dn(Bn) 19162 Dn(0,0) Dn 19163 Dn(0) Dn 19164 Dn(Ln,0) Dn(Ln) 19165 19166 19167File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 19168 191699.41.3.4 Instruction Formats 19170............................ 19171 19172The Principles of Operation manuals lists 26 instruction formats where 19173some of the formats have multiple variants. For the '.insn' pseudo 19174directive the assembler recognizes some of the formats. Typically, the 19175most general variant of the instruction format is used by the '.insn' 19176directive. 19177 19178 The following table lists the abbreviations used in the table of 19179instruction formats: 19180 19181 OpCode / OpCd Part of the op code. 19182 Bx Base register number for operand x. 19183 Dx Displacement for operand x. 19184 DLx Displacement lower 12 bits for operand x. 19185 DHx Displacement higher 8-bits for operand x. 19186 Rx Register number for operand x. 19187 Xx Index register number for operand x. 19188 Ix Signed immediate for operand x. 19189 Ux Unsigned immediate for operand x. 19190 19191 An instruction is two, four, or six bytes in length and must be 19192aligned on a 2 byte boundary. The first two bits of the instruction 19193specify the length of the instruction, 00 indicates a two byte 19194instruction, 01 and 10 indicates a four byte instruction, and 11 19195indicates a six byte instruction. 19196 19197 The following table lists the s390 instruction formats that are 19198available with the '.insn' pseudo directive: 19199 19200'E format' 19201 +-------------+ 19202 | OpCode | 19203 +-------------+ 19204 0 15 19205 19206'RI format: <insn> R1,I2' 19207 +--------+----+----+------------------+ 19208 | OpCode | R1 |OpCd| I2 | 19209 +--------+----+----+------------------+ 19210 0 8 12 16 31 19211 19212'RIE format: <insn> R1,R3,I2' 19213 +--------+----+----+------------------+--------+--------+ 19214 | OpCode | R1 | R3 | I2 |////////| OpCode | 19215 +--------+----+----+------------------+--------+--------+ 19216 0 8 12 16 32 40 47 19217 19218'RIL format: <insn> R1,I2' 19219 +--------+----+----+------------------------------------+ 19220 | OpCode | R1 |OpCd| I2 | 19221 +--------+----+----+------------------------------------+ 19222 0 8 12 16 47 19223 19224'RILU format: <insn> R1,U2' 19225 +--------+----+----+------------------------------------+ 19226 | OpCode | R1 |OpCd| U2 | 19227 +--------+----+----+------------------------------------+ 19228 0 8 12 16 47 19229 19230'RIS format: <insn> R1,I2,M3,D4(B4)' 19231 +--------+----+----+----+-------------+--------+--------+ 19232 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 19233 +--------+----+----+----+-------------+--------+--------+ 19234 0 8 12 16 20 32 36 47 19235 19236'RR format: <insn> R1,R2' 19237 +--------+----+----+ 19238 | OpCode | R1 | R2 | 19239 +--------+----+----+ 19240 0 8 12 15 19241 19242'RRE format: <insn> R1,R2' 19243 +------------------+--------+----+----+ 19244 | OpCode |////////| R1 | R2 | 19245 +------------------+--------+----+----+ 19246 0 16 24 28 31 19247 19248'RRF format: <insn> R1,R2,R3,M4' 19249 +------------------+----+----+----+----+ 19250 | OpCode | R3 | M4 | R1 | R2 | 19251 +------------------+----+----+----+----+ 19252 0 16 20 24 28 31 19253 19254'RRS format: <insn> R1,R2,M3,D4(B4)' 19255 +--------+----+----+----+-------------+----+----+--------+ 19256 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 19257 +--------+----+----+----+-------------+----+----+--------+ 19258 0 8 12 16 20 32 36 40 47 19259 19260'RS format: <insn> R1,R3,D2(B2)' 19261 +--------+----+----+----+-------------+ 19262 | OpCode | R1 | R3 | B2 | D2 | 19263 +--------+----+----+----+-------------+ 19264 0 8 12 16 20 31 19265 19266'RSE format: <insn> R1,R3,D2(B2)' 19267 +--------+----+----+----+-------------+--------+--------+ 19268 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 19269 +--------+----+----+----+-------------+--------+--------+ 19270 0 8 12 16 20 32 40 47 19271 19272'RSI format: <insn> R1,R3,I2' 19273 +--------+----+----+------------------------------------+ 19274 | OpCode | R1 | R3 | I2 | 19275 +--------+----+----+------------------------------------+ 19276 0 8 12 16 47 19277 19278'RSY format: <insn> R1,R3,D2(B2)' 19279 +--------+----+----+----+-------------+--------+--------+ 19280 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 19281 +--------+----+----+----+-------------+--------+--------+ 19282 0 8 12 16 20 32 40 47 19283 19284'RX format: <insn> R1,D2(X2,B2)' 19285 +--------+----+----+----+-------------+ 19286 | OpCode | R1 | X2 | B2 | D2 | 19287 +--------+----+----+----+-------------+ 19288 0 8 12 16 20 31 19289 19290'RXE format: <insn> R1,D2(X2,B2)' 19291 +--------+----+----+----+-------------+--------+--------+ 19292 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 19293 +--------+----+----+----+-------------+--------+--------+ 19294 0 8 12 16 20 32 40 47 19295 19296'RXF format: <insn> R1,R3,D2(X2,B2)' 19297 +--------+----+----+----+-------------+----+---+--------+ 19298 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 19299 +--------+----+----+----+-------------+----+---+--------+ 19300 0 8 12 16 20 32 36 40 47 19301 19302'RXY format: <insn> R1,D2(X2,B2)' 19303 +--------+----+----+----+-------------+--------+--------+ 19304 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 19305 +--------+----+----+----+-------------+--------+--------+ 19306 0 8 12 16 20 32 36 40 47 19307 19308'S format: <insn> D2(B2)' 19309 +------------------+----+-------------+ 19310 | OpCode | B2 | D2 | 19311 +------------------+----+-------------+ 19312 0 16 20 31 19313 19314'SI format: <insn> D1(B1),I2' 19315 +--------+---------+----+-------------+ 19316 | OpCode | I2 | B1 | D1 | 19317 +--------+---------+----+-------------+ 19318 0 8 16 20 31 19319 19320'SIY format: <insn> D1(B1),U2' 19321 +--------+---------+----+-------------+--------+--------+ 19322 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 19323 +--------+---------+----+-------------+--------+--------+ 19324 0 8 16 20 32 36 40 47 19325 19326'SIL format: <insn> D1(B1),I2' 19327 +------------------+----+-------------+-----------------+ 19328 | OpCode | B1 | D1 | I2 | 19329 +------------------+----+-------------+-----------------+ 19330 0 16 20 32 47 19331 19332'SS format: <insn> D1(R1,B1),D2(B3),R3' 19333 +--------+----+----+----+-------------+----+------------+ 19334 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 19335 +--------+----+----+----+-------------+----+------------+ 19336 0 8 12 16 20 32 36 47 19337 19338'SSE format: <insn> D1(B1),D2(B2)' 19339 +------------------+----+-------------+----+------------+ 19340 | OpCode | B1 | D1 | B2 | D2 | 19341 +------------------+----+-------------+----+------------+ 19342 0 8 12 16 20 32 36 47 19343 19344'SSF format: <insn> D1(B1),D2(B2),R3' 19345 +--------+----+----+----+-------------+----+------------+ 19346 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 19347 +--------+----+----+----+-------------+----+------------+ 19348 0 8 12 16 20 32 36 47 19349 19350 For the complete list of all instruction format variants see the 19351Principles of Operation manuals. 19352 19353 19354File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 19355 193569.41.3.5 Instruction Aliases 19357............................ 19358 19359A specific bit pattern can have multiple mnemonics, for example the bit 19360pattern '0xa7000000' has the mnemonics 'tmh' and 'tmlh'. In addition, 19361there are a number of mnemonics recognized by 'as' that are not present 19362in the Principles of Operation. These are the short forms of the branch 19363instructions, where the condition code mask operand is encoded in the 19364mnemonic. This is relevant for the branch instructions, the compare and 19365branch instructions, and the compare and trap instructions. 19366 19367 For the branch instructions there are 20 condition code strings that 19368can be used as part of the mnemonic in place of a mask operand in the 19369instruction format: 19370 19371 instruction short form 19372 ---------------------------------------------- 19373 bcr M1,R2 b<m>r R2 19374 bc M1,D2(X2,B2) b<m> D2(X2,B2) 19375 brc M1,I2 j<m> I2 19376 brcl M1,I2 jg<m> I2 19377 19378 In the mnemonic for a branch instruction the condition code string 19379<m> can be any of the following: 19380 19381 o jump on overflow / if ones 19382 h jump on A high 19383 p jump on plus 19384 nle jump on not low or equal 19385 l jump on A low 19386 m jump on minus 19387 nhe jump on not high or equal 19388 lh jump on low or high 19389 ne jump on A not equal B 19390 nz jump on not zero / if not zeros 19391 e jump on A equal B 19392 z jump on zero / if zeroes 19393 nlh jump on not low or high 19394 he jump on high or equal 19395 nl jump on A not low 19396 nm jump on not minus / if not mixed 19397 le jump on low or equal 19398 nh jump on A not high 19399 np jump on not plus 19400 no jump on not overflow / if not ones 19401 19402 For the compare and branch, and compare and trap instructions there 19403are 12 condition code strings that can be used as part of the mnemonic 19404in place of a mask operand in the instruction format: 19405 19406 instruction short form 19407 ------------------------------------------------------------ 19408 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 19409 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 19410 crj R1,R2,M3,I4 crj<m> R1,R2,I4 19411 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 19412 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 19413 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 19414 cij R1,I2,M3,I4 cij<m> R1,I2,I4 19415 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 19416 crt R1,R2,M3 crt<m> R1,R2 19417 cgrt R1,R2,M3 cgrt<m> R1,R2 19418 cit R1,I2,M3 cit<m> R1,I2 19419 cgit R1,I2,M3 cgit<m> R1,I2 19420 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 19421 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 19422 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 19423 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 19424 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 19425 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 19426 clij R1,I2,M3,I4 clij<m> R1,I2,I4 19427 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 19428 clrt R1,R2,M3 clrt<m> R1,R2 19429 clgrt R1,R2,M3 clgrt<m> R1,R2 19430 clfit R1,I2,M3 clfit<m> R1,I2 19431 clgit R1,I2,M3 clgit<m> R1,I2 19432 19433 In the mnemonic for a compare and branch and compare and trap 19434instruction the condition code string <m> can be any of the following: 19435 19436 h jump on A high 19437 nle jump on not low or equal 19438 l jump on A low 19439 nhe jump on not high or equal 19440 ne jump on A not equal B 19441 lh jump on low or high 19442 e jump on A equal B 19443 nlh jump on not low or high 19444 nl jump on A not low 19445 he jump on high or equal 19446 nh jump on A not high 19447 le jump on low or equal 19448 19449 19450File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 19451 194529.41.3.6 Instruction Operand Modifier 19453..................................... 19454 19455If a symbol modifier is attached to a symbol in an expression for an 19456instruction operand field, the symbol term is replaced with a reference 19457to an object in the global offset table (GOT) or the procedure linkage 19458table (PLT). The following expressions are allowed: 'symbol@modifier + 19459constant', 'symbol@modifier + label + constant', and 'symbol@modifier - 19460label + constant'. The term 'symbol' is the symbol that will be entered 19461into the GOT or PLT, 'label' is a local label, and 'constant' is an 19462arbitrary expression that the assembler can evaluate to a constant 19463value. 19464 19465 The term '(symbol + constant1)@modifier +/- label + constant2' is 19466also accepted but a warning message is printed and the term is converted 19467to 'symbol@modifier +/- label + constant1 + constant2'. 19468 19469'@got' 19470'@got12' 19471 The @got modifier can be used for displacement fields, 16-bit 19472 immediate fields and 32-bit pc-relative immediate fields. The 19473 @got12 modifier is synonym to @got. The symbol is added to the 19474 GOT. For displacement fields and 16-bit immediate fields the symbol 19475 term is replaced with the offset from the start of the GOT to the 19476 GOT slot for the symbol. For a 32-bit pc-relative field the 19477 pc-relative offset to the GOT slot from the current instruction 19478 address is used. 19479'@gotent' 19480 The @gotent modifier can be used for 32-bit pc-relative immediate 19481 fields. The symbol is added to the GOT and the symbol term is 19482 replaced with the pc-relative offset from the current instruction 19483 to the GOT slot for the symbol. 19484'@gotoff' 19485 The @gotoff modifier can be used for 16-bit immediate fields. The 19486 symbol term is replaced with the offset from the start of the GOT 19487 to the address of the symbol. 19488'@gotplt' 19489 The @gotplt modifier can be used for displacement fields, 16-bit 19490 immediate fields, and 32-bit pc-relative immediate fields. A 19491 procedure linkage table entry is generated for the symbol and a 19492 jump slot for the symbol is added to the GOT. For displacement 19493 fields and 16-bit immediate fields the symbol term is replaced with 19494 the offset from the start of the GOT to the jump slot for the 19495 symbol. For a 32-bit pc-relative field the pc-relative offset to 19496 the jump slot from the current instruction address is used. 19497'@plt' 19498 The @plt modifier can be used for 16-bit and 32-bit pc-relative 19499 immediate fields. A procedure linkage table entry is generated for 19500 the symbol. The symbol term is replaced with the relative offset 19501 from the current instruction to the PLT entry for the symbol. 19502'@pltoff' 19503 The @pltoff modifier can be used for 16-bit immediate fields. The 19504 symbol term is replaced with the offset from the start of the PLT 19505 to the address of the symbol. 19506'@gotntpoff' 19507 The @gotntpoff modifier can be used for displacement fields. The 19508 symbol is added to the static TLS block and the negated offset to 19509 the symbol in the static TLS block is added to the GOT. The symbol 19510 term is replaced with the offset to the GOT slot from the start of 19511 the GOT. 19512'@indntpoff' 19513 The @indntpoff modifier can be used for 32-bit pc-relative 19514 immediate fields. The symbol is added to the static TLS block and 19515 the negated offset to the symbol in the static TLS block is added 19516 to the GOT. The symbol term is replaced with the pc-relative offset 19517 to the GOT slot from the current instruction address. 19518 19519 For more information about the thread local storage modifiers 19520'gotntpoff' and 'indntpoff' see the ELF extension documentation 'ELF 19521Handling For Thread-Local Storage'. 19522 19523 19524File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 19525 195269.41.3.7 Instruction Marker 19527........................... 19528 19529The thread local storage instruction markers are used by the linker to 19530perform code optimization. 19531 19532':tls_load' 19533 The :tls_load marker is used to flag the load instruction in the 19534 initial exec TLS model that retrieves the offset from the thread 19535 pointer to a thread local storage variable from the GOT. 19536':tls_gdcall' 19537 The :tls_gdcall marker is used to flag the branch-and-save 19538 instruction to the __tls_get_offset function in the global dynamic 19539 TLS model. 19540':tls_ldcall' 19541 The :tls_ldcall marker is used to flag the branch-and-save 19542 instruction to the __tls_get_offset function in the local dynamic 19543 TLS model. 19544 19545 For more information about the thread local storage instruction 19546marker and the linker optimizations see the ELF extension documentation 19547'ELF Handling For Thread-Local Storage'. 19548 19549 19550File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 19551 195529.41.3.8 Literal Pool Entries 19553............................. 19554 19555A literal pool is a collection of values. To access the values a 19556pointer to the literal pool is loaded to a register, the literal pool 19557register. Usually, register %r13 is used as the literal pool register 19558(*note s390 Register::). Literal pool entries are created by adding the 19559suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 19560instruction operand. The expression is added to the literal pool and 19561the operand is replaced with the offset to the literal in the literal 19562pool. 19563 19564':lit1' 19565 The literal pool entry is created as an 8-bit value. An operand 19566 modifier must not be used for the original expression. 19567':lit2' 19568 The literal pool entry is created as a 16 bit value. The operand 19569 modifier @got may be used in the original expression. The term 19570 'x@got:lit2' will put the got offset for the global symbol x to the 19571 literal pool as 16 bit value. 19572':lit4' 19573 The literal pool entry is created as a 32-bit value. The operand 19574 modifier @got and @plt may be used in the original expression. The 19575 term 'x@got:lit4' will put the got offset for the global symbol x 19576 to the literal pool as a 32-bit value. The term 'x@plt:lit4' will 19577 put the plt offset for the global symbol x to the literal pool as a 19578 32-bit value. 19579':lit8' 19580 The literal pool entry is created as a 64-bit value. The operand 19581 modifier @got and @plt may be used in the original expression. The 19582 term 'x@got:lit8' will put the got offset for the global symbol x 19583 to the literal pool as a 64-bit value. The term 'x@plt:lit8' will 19584 put the plt offset for the global symbol x to the literal pool as a 19585 64-bit value. 19586 19587 The assembler directive '.ltorg' is used to emit all literal pool 19588entries to the current position. 19589 19590 19591File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 19592 195939.41.4 Assembler Directives 19594--------------------------- 19595 19596'as' for s390 supports all of the standard ELF assembler directives as 19597outlined in the main part of this document. Some directives have been 19598extended and there are some additional directives, which are only 19599available for the s390 'as'. 19600 19601'.insn' 19602 This directive permits the numeric representation of an 19603 instructions and makes the assembler insert the operands according 19604 to one of the instructions formats for '.insn' (*note s390 19605 Formats::). For example, the instruction 'l %r1,24(%r15)' could be 19606 written as '.insn rx,0x58000000,%r1,24(%r15)'. 19607'.short' 19608'.long' 19609'.quad' 19610 This directive places one or more 16-bit (.short), 32-bit (.long), 19611 or 64-bit (.quad) values into the current section. If an ELF or 19612 TLS modifier is used only the following expressions are allowed: 19613 'symbol@modifier + constant', 'symbol@modifier + label + constant', 19614 and 'symbol@modifier - label + constant'. The following modifiers 19615 are available: 19616 '@got' 19617 '@got12' 19618 The @got modifier can be used for .short, .long and .quad. 19619 The @got12 modifier is synonym to @got. The symbol is added 19620 to the GOT. The symbol term is replaced with offset from the 19621 start of the GOT to the GOT slot for the symbol. 19622 '@gotoff' 19623 The @gotoff modifier can be used for .short, .long and .quad. 19624 The symbol term is replaced with the offset from the start of 19625 the GOT to the address of the symbol. 19626 '@gotplt' 19627 The @gotplt modifier can be used for .long and .quad. A 19628 procedure linkage table entry is generated for the symbol and 19629 a jump slot for the symbol is added to the GOT. The symbol 19630 term is replaced with the offset from the start of the GOT to 19631 the jump slot for the symbol. 19632 '@plt' 19633 The @plt modifier can be used for .long and .quad. A 19634 procedure linkage table entry us generated for the symbol. 19635 The symbol term is replaced with the address of the PLT entry 19636 for the symbol. 19637 '@pltoff' 19638 The @pltoff modifier can be used for .short, .long and .quad. 19639 The symbol term is replaced with the offset from the start of 19640 the PLT to the address of the symbol. 19641 '@tlsgd' 19642 '@tlsldm' 19643 The @tlsgd and @tlsldm modifier can be used for .long and 19644 .quad. A tls_index structure for the symbol is added to the 19645 GOT. The symbol term is replaced with the offset from the 19646 start of the GOT to the tls_index structure. 19647 '@gotntpoff' 19648 '@indntpoff' 19649 The @gotntpoff and @indntpoff modifier can be used for .long 19650 and .quad. The symbol is added to the static TLS block and 19651 the negated offset to the symbol in the static TLS block is 19652 added to the GOT. For @gotntpoff the symbol term is replaced 19653 with the offset from the start of the GOT to the GOT slot, for 19654 @indntpoff the symbol term is replaced with the address of the 19655 GOT slot. 19656 '@dtpoff' 19657 The @dtpoff modifier can be used for .long and .quad. The 19658 symbol term is replaced with the offset of the symbol relative 19659 to the start of the TLS block it is contained in. 19660 '@ntpoff' 19661 The @ntpoff modifier can be used for .long and .quad. The 19662 symbol term is replaced with the offset of the symbol relative 19663 to the TCB pointer. 19664 19665 For more information about the thread local storage modifiers see 19666 the ELF extension documentation 'ELF Handling For Thread-Local 19667 Storage'. 19668 19669'.ltorg' 19670 This directive causes the current contents of the literal pool to 19671 be dumped to the current location (*note s390 Literal Pool 19672 Entries::). 19673 19674'.machine STRING[+EXTENSION]...' 19675 19676 This directive allows changing the machine for which code is 19677 generated. 'string' may be any of the '-march=' selection options, 19678 or 'push', or 'pop'. '.machine push' saves the currently selected 19679 cpu, which may be restored with '.machine pop'. Be aware that the 19680 cpu string has to be put into double quotes in case it contains 19681 characters not appropriate for identifiers. So you have to write 19682 '"z9-109"' instead of just 'z9-109'. Extensions can be specified 19683 after the cpu name, separated by plus characters. Valid extensions 19684 are: 'htm', 'nohtm', 'vx', 'novx'. They extend the basic 19685 instruction set with features from a higher cpu level, or remove 19686 support for a feature from the given cpu level. 19687 19688 Example: 'z13+nohtm' allows all instructions of the z13 cpu except 19689 instructions from the HTM facility. 19690 19691'.machinemode string' 19692 This directive allows to change the architecture mode for which 19693 code is being generated. 'string' may be 'esa', 'zarch', 19694 'zarch_nohighgprs', 'push', or 'pop'. '.machinemode 19695 zarch_nohighgprs' can be used to prevent the 'highgprs' flag from 19696 being set in the ELF header of the output file. This is useful in 19697 situations where the code is gated with a runtime check which makes 19698 sure that the code is only executed on kernels providing the 19699 'highgprs' feature. '.machinemode push' saves the currently 19700 selected mode, which may be restored with '.machinemode pop'. 19701 19702 19703File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 19704 197059.41.5 Floating Point 19706--------------------- 19707 19708The assembler recognizes both the IEEE floating-point instruction and 19709the hexadecimal floating-point instructions. The floating-point 19710constructors '.float', '.single', and '.double' always emit the IEEE 19711format. To assemble hexadecimal floating-point constants the '.long' 19712and '.quad' directives must be used. 19713 19714 19715File: as.info, Node: SCORE-Dependent, Next: SH-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 19716 197179.42 SCORE Dependent Features 19718============================= 19719 19720* Menu: 19721 19722* SCORE-Opts:: Assembler options 19723* SCORE-Pseudo:: SCORE Assembler Directives 19724* SCORE-Syntax:: Syntax 19725 19726 19727File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 19728 197299.42.1 Options 19730-------------- 19731 19732The following table lists all available SCORE options. 19733 19734'-G NUM' 19735 This option sets the largest size of an object that can be 19736 referenced implicitly with the 'gp' register. The default value is 19737 8. 19738 19739'-EB' 19740 Assemble code for a big-endian cpu 19741 19742'-EL' 19743 Assemble code for a little-endian cpu 19744 19745'-FIXDD' 19746 Assemble code for fix data dependency 19747 19748'-NWARN' 19749 Assemble code for no warning message for fix data dependency 19750 19751'-SCORE5' 19752 Assemble code for target is SCORE5 19753 19754'-SCORE5U' 19755 Assemble code for target is SCORE5U 19756 19757'-SCORE7' 19758 Assemble code for target is SCORE7, this is default setting 19759 19760'-SCORE3' 19761 Assemble code for target is SCORE3 19762 19763'-march=score7' 19764 Assemble code for target is SCORE7, this is default setting 19765 19766'-march=score3' 19767 Assemble code for target is SCORE3 19768 19769'-USE_R1' 19770 Assemble code for no warning message when using temp register r1 19771 19772'-KPIC' 19773 Generate code for PIC. This option tells the assembler to generate 19774 score position-independent macro expansions. It also tells the 19775 assembler to mark the output file as PIC. 19776 19777'-O0' 19778 Assembler will not perform any optimizations 19779 19780'-V' 19781 Sunplus release version 19782 19783 19784File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent 19785 197869.42.2 SCORE Assembler Directives 19787--------------------------------- 19788 19789A number of assembler directives are available for SCORE. The following 19790table is far from complete. 19791 19792'.set nwarn' 19793 Let the assembler not to generate warnings if the source machine 19794 language instructions happen data dependency. 19795 19796'.set fixdd' 19797 Let the assembler to insert bubbles (32 bit nop instruction / 16 19798 bit nop! Instruction) if the source machine language instructions 19799 happen data dependency. 19800 19801'.set nofixdd' 19802 Let the assembler to generate warnings if the source machine 19803 language instructions happen data dependency. (Default) 19804 19805'.set r1' 19806 Let the assembler not to generate warnings if the source program 19807 uses r1. allow user to use r1 19808 19809'set nor1' 19810 Let the assembler to generate warnings if the source program uses 19811 r1. (Default) 19812 19813'.sdata' 19814 Tell the assembler to add subsequent data into the sdata section 19815 19816'.rdata' 19817 Tell the assembler to add subsequent data into the rdata section 19818 19819'.frame "frame-register", "offset", "return-pc-register"' 19820 Describe a stack frame. "frame-register" is the frame register, 19821 "offset" is the distance from the frame register to the virtual 19822 frame pointer, "return-pc-register" is the return program register. 19823 You must use ".ent" before ".frame" and only one ".frame" can be 19824 used per ".ent". 19825 19826'.mask "bitmask", "frameoffset"' 19827 Indicate which of the integer registers are saved in the current 19828 function's stack frame, this is for the debugger to explain the 19829 frame chain. 19830 19831'.ent "proc-name"' 19832 Set the beginning of the procedure "proc_name". Use this directive 19833 when you want to generate information for the debugger. 19834 19835'.end proc-name' 19836 Set the end of a procedure. Use this directive to generate 19837 information for the debugger. 19838 19839'.bss' 19840 Switch the destination of following statements into the bss 19841 section, which is used for data that is uninitialized anywhere. 19842 19843 19844File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent 19845 198469.42.3 SCORE Syntax 19847------------------- 19848 19849* Menu: 19850 19851* SCORE-Chars:: Special Characters 19852 19853 19854File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax 19855 198569.42.3.1 Special Characters 19857........................... 19858 19859The presence of a '#' appearing anywhere on a line indicates the start 19860of a comment that extends to the end of that line. 19861 19862 If a '#' appears as the first character of a line then the whole line 19863is treated as a comment, but in this case the line can also be a logical 19864line number directive (*note Comments::) or a preprocessor control 19865command (*note Preprocessing::). 19866 19867 The ';' character can be used to separate statements on the same 19868line. 19869 19870 19871File: as.info, Node: SH-Dependent, Next: Sparc-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 19872 198739.43 Renesas / SuperH SH Dependent Features 19874=========================================== 19875 19876* Menu: 19877 19878* SH Options:: Options 19879* SH Syntax:: Syntax 19880* SH Floating Point:: Floating Point 19881* SH Directives:: SH Machine Directives 19882* SH Opcodes:: Opcodes 19883 19884 19885File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 19886 198879.43.1 Options 19888-------------- 19889 19890'as' has following command-line options for the Renesas (formerly 19891Hitachi) / SuperH SH family. 19892 19893'--little' 19894 Generate little endian code. 19895 19896'--big' 19897 Generate big endian code. 19898 19899'--relax' 19900 Alter jump instructions for long displacements. 19901 19902'--small' 19903 Align sections to 4 byte boundaries, not 16. 19904 19905'--dsp' 19906 Enable sh-dsp insns, and disable sh3e / sh4 insns. 19907 19908'--renesas' 19909 Disable optimization with section symbol for compatibility with 19910 Renesas assembler. 19911 19912'--allow-reg-prefix' 19913 Allow '$' as a register name prefix. 19914 19915'--fdpic' 19916 Generate an FDPIC object file. 19917 19918'--isa=sh4 | sh4a' 19919 Specify the sh4 or sh4a instruction set. 19920'--isa=dsp' 19921 Enable sh-dsp insns, and disable sh3e / sh4 insns. 19922'--isa=fp' 19923 Enable sh2e, sh3e, sh4, and sh4a insn sets. 19924'--isa=all' 19925 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 19926 19927'-h-tick-hex' 19928 Support H'00 style hex constants in addition to 0x00 style. 19929 19930 19931File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 19932 199339.43.2 Syntax 19934------------- 19935 19936* Menu: 19937 19938* SH-Chars:: Special Characters 19939* SH-Regs:: Register Names 19940* SH-Addressing:: Addressing Modes 19941 19942 19943File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 19944 199459.43.2.1 Special Characters 19946........................... 19947 19948'!' is the line comment character. 19949 19950 You can use ';' instead of a newline to separate statements. 19951 19952 If a '#' appears as the first character of a line then the whole line 19953is treated as a comment, but in this case the line could also be a 19954logical line number directive (*note Comments::) or a preprocessor 19955control command (*note Preprocessing::). 19956 19957 Since '$' has no special meaning, you may use it in symbol names. 19958 19959 19960File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 19961 199629.43.2.2 Register Names 19963....................... 19964 19965You can use the predefined symbols 'r0', 'r1', 'r2', 'r3', 'r4', 'r5', 19966'r6', 'r7', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', and 'r15' to 19967refer to the SH registers. 19968 19969 The SH also has these control registers: 19970 19971'pr' 19972 procedure register (holds return address) 19973 19974'pc' 19975 program counter 19976 19977'mach' 19978'macl' 19979 high and low multiply accumulator registers 19980 19981'sr' 19982 status register 19983 19984'gbr' 19985 global base register 19986 19987'vbr' 19988 vector base register (for interrupt vectors) 19989 19990 19991File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 19992 199939.43.2.3 Addressing Modes 19994......................... 19995 19996'as' understands the following addressing modes for the SH. 'RN' in the 19997following refers to any of the numbered registers, but _not_ the control 19998registers. 19999 20000'RN' 20001 Register direct 20002 20003'@RN' 20004 Register indirect 20005 20006'@-RN' 20007 Register indirect with pre-decrement 20008 20009'@RN+' 20010 Register indirect with post-increment 20011 20012'@(DISP, RN)' 20013 Register indirect with displacement 20014 20015'@(R0, RN)' 20016 Register indexed 20017 20018'@(DISP, GBR)' 20019 'GBR' offset 20020 20021'@(R0, GBR)' 20022 GBR indexed 20023 20024'ADDR' 20025'@(DISP, PC)' 20026 PC relative address (for branch or for addressing memory). The 20027 'as' implementation allows you to use the simpler form ADDR 20028 anywhere a PC relative address is called for; the alternate form is 20029 supported for compatibility with other assemblers. 20030 20031'#IMM' 20032 Immediate data 20033 20034 20035File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 20036 200379.43.3 Floating Point 20038--------------------- 20039 20040SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 20041SH groups can use '.float' directive to generate IEEE floating-point 20042numbers. 20043 20044 SH2E and SH3E support single-precision floating point calculations as 20045well as entirely PCAPI compatible emulation of double-precision floating 20046point calculations. SH2E and SH3E instructions are a subset of the 20047floating point calculations conforming to the IEEE754 standard. 20048 20049 In addition to single-precision and double-precision floating-point 20050operation capability, the on-chip FPU of SH4 has a 128-bit graphic 20051engine that enables 32-bit floating-point data to be processed 128 bits 20052at a time. It also supports 4 * 4 array operations and inner product 20053operations. Also, a superscalar architecture is employed that enables 20054simultaneous execution of two instructions (including FPU instructions), 20055providing performance of up to twice that of conventional architectures 20056at the same frequency. 20057 20058 20059File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 20060 200619.43.4 SH Machine Directives 20062---------------------------- 20063 20064'uaword' 20065'ualong' 20066'uaquad' 20067 'as' will issue a warning when a misaligned '.word', '.long', or 20068 '.quad' directive is used. You may use '.uaword', '.ualong', or 20069 '.uaquad' to indicate that the value is intentionally misaligned. 20070 20071 20072File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 20073 200749.43.5 Opcodes 20075-------------- 20076 20077For detailed information on the SH machine instruction set, see 20078'SH-Microcomputer User's Manual' (Renesas) or 'SH-4 32-bit CPU Core 20079Architecture' (SuperH) and 'SuperH (SH) 64-Bit RISC Series' (SuperH). 20080 20081 'as' implements all the standard SH opcodes. No additional 20082pseudo-instructions are needed on this family. Note, however, that 20083because 'as' supports a simpler form of PC-relative addressing, you may 20084simply write (for example) 20085 20086 mov.l bar,r0 20087 20088where other assemblers might require an explicit displacement to 'bar' 20089from the program counter: 20090 20091 mov.l @(DISP, PC) 20092 20093 Here is a summary of SH opcodes: 20094 20095 Legend: 20096 Rn a numbered register 20097 Rm another numbered register 20098 #imm immediate data 20099 disp displacement 20100 disp8 8-bit displacement 20101 disp12 12-bit displacement 20102 20103 add #imm,Rn lds.l @Rn+,PR 20104 add Rm,Rn mac.w @Rm+,@Rn+ 20105 addc Rm,Rn mov #imm,Rn 20106 addv Rm,Rn mov Rm,Rn 20107 and #imm,R0 mov.b Rm,@(R0,Rn) 20108 and Rm,Rn mov.b Rm,@-Rn 20109 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 20110 bf disp8 mov.b @(disp,Rm),R0 20111 bra disp12 mov.b @(disp,GBR),R0 20112 bsr disp12 mov.b @(R0,Rm),Rn 20113 bt disp8 mov.b @Rm+,Rn 20114 clrmac mov.b @Rm,Rn 20115 clrt mov.b R0,@(disp,Rm) 20116 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 20117 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 20118 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 20119 cmp/gt Rm,Rn mov.l Rm,@-Rn 20120 cmp/hi Rm,Rn mov.l Rm,@Rn 20121 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 20122 cmp/pl Rn mov.l @(disp,GBR),R0 20123 cmp/pz Rn mov.l @(disp,PC),Rn 20124 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 20125 div0s Rm,Rn mov.l @Rm+,Rn 20126 div0u mov.l @Rm,Rn 20127 div1 Rm,Rn mov.l R0,@(disp,GBR) 20128 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 20129 exts.w Rm,Rn mov.w Rm,@-Rn 20130 extu.b Rm,Rn mov.w Rm,@Rn 20131 extu.w Rm,Rn mov.w @(disp,Rm),R0 20132 jmp @Rn mov.w @(disp,GBR),R0 20133 jsr @Rn mov.w @(disp,PC),Rn 20134 ldc Rn,GBR mov.w @(R0,Rm),Rn 20135 ldc Rn,SR mov.w @Rm+,Rn 20136 ldc Rn,VBR mov.w @Rm,Rn 20137 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 20138 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 20139 ldc.l @Rn+,VBR mova @(disp,PC),R0 20140 lds Rn,MACH movt Rn 20141 lds Rn,MACL muls Rm,Rn 20142 lds Rn,PR mulu Rm,Rn 20143 lds.l @Rn+,MACH neg Rm,Rn 20144 lds.l @Rn+,MACL negc Rm,Rn 20145 nop stc VBR,Rn 20146 not Rm,Rn stc.l GBR,@-Rn 20147 or #imm,R0 stc.l SR,@-Rn 20148 or Rm,Rn stc.l VBR,@-Rn 20149 or.b #imm,@(R0,GBR) sts MACH,Rn 20150 rotcl Rn sts MACL,Rn 20151 rotcr Rn sts PR,Rn 20152 rotl Rn sts.l MACH,@-Rn 20153 rotr Rn sts.l MACL,@-Rn 20154 rte sts.l PR,@-Rn 20155 rts sub Rm,Rn 20156 sett subc Rm,Rn 20157 shal Rn subv Rm,Rn 20158 shar Rn swap.b Rm,Rn 20159 shll Rn swap.w Rm,Rn 20160 shll16 Rn tas.b @Rn 20161 shll2 Rn trapa #imm 20162 shll8 Rn tst #imm,R0 20163 shlr Rn tst Rm,Rn 20164 shlr16 Rn tst.b #imm,@(R0,GBR) 20165 shlr2 Rn xor #imm,R0 20166 shlr8 Rn xor Rm,Rn 20167 sleep xor.b #imm,@(R0,GBR) 20168 stc GBR,Rn xtrct Rm,Rn 20169 stc SR,Rn 20170 20171 20172File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 20173 201749.44 SPARC Dependent Features 20175============================= 20176 20177* Menu: 20178 20179* Sparc-Opts:: Options 20180* Sparc-Aligned-Data:: Option to enforce aligned data 20181* Sparc-Syntax:: Syntax 20182* Sparc-Float:: Floating Point 20183* Sparc-Directives:: Sparc Machine Directives 20184 20185 20186File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 20187 201889.44.1 Options 20189-------------- 20190 20191The SPARC chip family includes several successive versions, using the 20192same core instruction set, but including a few additional instructions 20193at each version. There are exceptions to this however. For details on 20194what instructions each variant supports, please see the chip's 20195architecture reference manual. 20196 20197 By default, 'as' assumes the core instruction set (SPARC v6), but 20198"bumps" the architecture level as needed: it switches to successively 20199higher architectures as it encounters instructions that only exist in 20200the higher levels. 20201 20202 If not configured for SPARC v9 ('sparc64-*-*') GAS will not bump past 20203sparclite by default, an option must be passed to enable the v9 20204instructions. 20205 20206 GAS treats sparclite as being compatible with v8, unless an 20207architecture is explicitly requested. SPARC v9 is always incompatible 20208with sparclite. 20209 20210'-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite' 20211'-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |' 20212'-Av8plusv | -Av8plusm | -Av8plusm8' 20213'-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8' 20214'-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima' 20215'-Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6' 20216 Use one of the '-A' options to select one of the SPARC 20217 architectures explicitly. If you select an architecture 20218 explicitly, 'as' reports a fatal error if it encounters an 20219 instruction or feature requiring an incompatible or higher level. 20220 20221 '-Av8plus', '-Av8plusa', '-Av8plusb', '-Av8plusc', '-Av8plusd', and 20222 '-Av8plusv' select a 32 bit environment. 20223 20224 '-Av9', '-Av9a', '-Av9b', '-Av9c', '-Av9d', '-Av9e', '-Av9v' and 20225 '-Av9m' select a 64 bit environment and are not available unless 20226 GAS is explicitly configured with 64 bit environment support. 20227 20228 '-Av8plusa' and '-Av9a' enable the SPARC V9 instruction set with 20229 UltraSPARC VIS 1.0 extensions. 20230 20231 '-Av8plusb' and '-Av9b' enable the UltraSPARC VIS 2.0 instructions, 20232 as well as the instructions enabled by '-Av8plusa' and '-Av9a'. 20233 20234 '-Av8plusc' and '-Av9c' enable the UltraSPARC Niagara instructions, 20235 as well as the instructions enabled by '-Av8plusb' and '-Av9b'. 20236 20237 '-Av8plusd' and '-Av9d' enable the floating point fused 20238 multiply-add, VIS 3.0, and HPC extension instructions, as well as 20239 the instructions enabled by '-Av8plusc' and '-Av9c'. 20240 20241 '-Av8pluse' and '-Av9e' enable the cryptographic instructions, as 20242 well as the instructions enabled by '-Av8plusd' and '-Av9d'. 20243 20244 '-Av8plusv' and '-Av9v' enable floating point unfused multiply-add, 20245 and integer multiply-add, as well as the instructions enabled by 20246 '-Av8pluse' and '-Av9e'. 20247 20248 '-Av8plusm' and '-Av9m' enable the VIS 4.0, subtract extended, 20249 xmpmul, xmontmul and xmontsqr instructions, as well as the 20250 instructions enabled by '-Av8plusv' and '-Av9v'. 20251 20252 '-Av8plusm8' and '-Av9m8' enable the instructions introduced in the 20253 Oracle SPARC Architecture 2017 and the M8 processor, as well as the 20254 instructions enabled by '-Av8plusm' and '-Av9m'. 20255 20256 '-Asparc' specifies a v9 environment. It is equivalent to '-Av9' 20257 if the word size is 64-bit, and '-Av8plus' otherwise. 20258 20259 '-Asparcvis' specifies a v9a environment. It is equivalent to 20260 '-Av9a' if the word size is 64-bit, and '-Av8plusa' otherwise. 20261 20262 '-Asparcvis2' specifies a v9b environment. It is equivalent to 20263 '-Av9b' if the word size is 64-bit, and '-Av8plusb' otherwise. 20264 20265 '-Asparcfmaf' specifies a v9b environment with the floating point 20266 fused multiply-add instructions enabled. 20267 20268 '-Asparcima' specifies a v9b environment with the integer 20269 multiply-add instructions enabled. 20270 20271 '-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC , 20272 and floating point fused multiply-add instructions enabled. 20273 20274 '-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC, 20275 and floating point unfused multiply-add instructions enabled. 20276 20277 '-Asparc5' is equivalent to '-Av9m'. 20278 20279 '-Asparc6' is equivalent to '-Av9m8'. 20280 20281'-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc' 20282'-xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |' 20283'-xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b' 20284'-xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v' 20285'-xarch=v9m | -xarch=v9m8' 20286'-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2' 20287'-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3' 20288'-xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6' 20289 For compatibility with the SunOS v9 assembler. These options are 20290 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, 20291 -Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, 20292 -Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2, 20293 -Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and 20294 -Asparc6 respectively. 20295 20296'-bump' 20297 Warn whenever it is necessary to switch to another level. If an 20298 architecture level is explicitly requested, GAS will not issue 20299 warnings until that level is reached, and will then bump the level 20300 as required (except between incompatible levels). 20301 20302'-32 | -64' 20303 Select the word size, either 32 bits or 64 bits. These options are 20304 only available with the ELF object file format, and require that 20305 the necessary BFD support has been included. 20306 20307'--dcti-couples-detect' 20308 Warn if a DCTI (delayed control transfer instruction) couple is 20309 found when generating code for a variant of the SPARC architecture 20310 in which the execution of the couple is unpredictable, or very 20311 slow. This is disabled by default. 20312 20313 20314File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 20315 203169.44.2 Enforcing aligned data 20317----------------------------- 20318 20319SPARC GAS normally permits data to be misaligned. For example, it 20320permits the '.long' pseudo-op to be used on a byte boundary. However, 20321the native SunOS assemblers issue an error when they see misaligned 20322data. 20323 20324 You can use the '--enforce-aligned-data' option to make SPARC GAS 20325also issue an error about misaligned data, just as the SunOS assemblers 20326do. 20327 20328 The '--enforce-aligned-data' option is not the default because gcc 20329issues misaligned data pseudo-ops when it initializes certain packed 20330data structures (structures defined using the 'packed' attribute). You 20331may have to assemble with GAS in order to initialize packed data 20332structures in your own code. 20333 20334 20335File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 20336 203379.44.3 Sparc Syntax 20338------------------- 20339 20340The assembler syntax closely follows The Sparc Architecture Manual, 20341versions 8 and 9, as well as most extensions defined by Sun for their 20342UltraSPARC and Niagara line of processors. 20343 20344* Menu: 20345 20346* Sparc-Chars:: Special Characters 20347* Sparc-Regs:: Register Names 20348* Sparc-Constants:: Constant Names 20349* Sparc-Relocs:: Relocations 20350* Sparc-Size-Translations:: Size Translations 20351 20352 20353File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 20354 203559.44.3.1 Special Characters 20356........................... 20357 20358A '!' character appearing anywhere on a line indicates the start of a 20359comment that extends to the end of that line. 20360 20361 If a '#' appears as the first character of a line then the whole line 20362is treated as a comment, but in this case the line could also be a 20363logical line number directive (*note Comments::) or a preprocessor 20364control command (*note Preprocessing::). 20365 20366 ';' can be used instead of a newline to separate statements. 20367 20368 20369File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 20370 203719.44.3.2 Register Names 20372....................... 20373 20374The Sparc integer register file is broken down into global, outgoing, 20375local, and incoming. 20376 20377 * The 8 global registers are referred to as '%gN'. 20378 20379 * The 8 outgoing registers are referred to as '%oN'. 20380 20381 * The 8 local registers are referred to as '%lN'. 20382 20383 * The 8 incoming registers are referred to as '%iN'. 20384 20385 * The frame pointer register '%i6' can be referenced using the alias 20386 '%fp'. 20387 20388 * The stack pointer register '%o6' can be referenced using the alias 20389 '%sp'. 20390 20391 Floating point registers are simply referred to as '%fN'. When 20392assembling for pre-V9, only 32 floating point registers are available. 20393For V9 and later there are 64, but there are restrictions when 20394referencing the upper 32 registers. They can only be accessed as double 20395or quad, and thus only even or quad numbered accesses are allowed. For 20396example, '%f34' is a legal floating point register, but '%f35' is not. 20397 20398 Floating point registers accessed as double can also be referred 20399using the '%dN' notation, where N is even. Similarly, floating point 20400registers accessed as quad can be referred using the '%qN' notation, 20401where N is a multiple of 4. For example, '%f4' can be denoted as both 20402'%d4' and '%q4'. On the other hand, '%f2' can be denoted as '%d2' but 20403not as '%q2'. 20404 20405 Certain V9 instructions allow access to ancillary state registers. 20406Most simply they can be referred to as '%asrN' where N can be from 16 to 2040731. However, there are some aliases defined to reference ASR registers 20408defined for various UltraSPARC processors: 20409 20410 * The tick compare register is referred to as '%tick_cmpr'. 20411 20412 * The system tick register is referred to as '%stick'. An alias, 20413 '%sys_tick', exists but is deprecated and should not be used by new 20414 software. 20415 20416 * The system tick compare register is referred to as '%stick_cmpr'. 20417 An alias, '%sys_tick_cmpr', exists but is deprecated and should not 20418 be used by new software. 20419 20420 * The software interrupt register is referred to as '%softint'. 20421 20422 * The set software interrupt register is referred to as 20423 '%set_softint'. The mnemonic '%softint_set' is provided as an 20424 alias. 20425 20426 * The clear software interrupt register is referred to as 20427 '%clear_softint'. The mnemonic '%softint_clear' is provided as an 20428 alias. 20429 20430 * The performance instrumentation counters register is referred to as 20431 '%pic'. 20432 20433 * The performance control register is referred to as '%pcr'. 20434 20435 * The graphics status register is referred to as '%gsr'. 20436 20437 * The V9 dispatch control register is referred to as '%dcr'. 20438 20439 Various V9 branch and conditional move instructions allow 20440specification of which set of integer condition codes to test. These 20441are referred to as '%xcc' and '%icc'. 20442 20443 Additionally, GAS supports the so-called "natural" condition codes; 20444these are referred to as '%ncc' and reference to '%icc' if the word size 20445is 32, '%xcc' if the word size is 64. 20446 20447 In V9, there are 4 sets of floating point condition codes which are 20448referred to as '%fccN'. 20449 20450 Several special privileged and non-privileged registers exist: 20451 20452 * The V9 address space identifier register is referred to as '%asi'. 20453 20454 * The V9 restorable windows register is referred to as '%canrestore'. 20455 20456 * The V9 savable windows register is referred to as '%cansave'. 20457 20458 * The V9 clean windows register is referred to as '%cleanwin'. 20459 20460 * The V9 current window pointer register is referred to as '%cwp'. 20461 20462 * The floating-point queue register is referred to as '%fq'. 20463 20464 * The V8 co-processor queue register is referred to as '%cq'. 20465 20466 * The floating point status register is referred to as '%fsr'. 20467 20468 * The other windows register is referred to as '%otherwin'. 20469 20470 * The V9 program counter register is referred to as '%pc'. 20471 20472 * The V9 next program counter register is referred to as '%npc'. 20473 20474 * The V9 processor interrupt level register is referred to as '%pil'. 20475 20476 * The V9 processor state register is referred to as '%pstate'. 20477 20478 * The trap base address register is referred to as '%tba'. 20479 20480 * The V9 tick register is referred to as '%tick'. 20481 20482 * The V9 trap level is referred to as '%tl'. 20483 20484 * The V9 trap program counter is referred to as '%tpc'. 20485 20486 * The V9 trap next program counter is referred to as '%tnpc'. 20487 20488 * The V9 trap state is referred to as '%tstate'. 20489 20490 * The V9 trap type is referred to as '%tt'. 20491 20492 * The V9 condition codes is referred to as '%ccr'. 20493 20494 * The V9 floating-point registers state is referred to as '%fprs'. 20495 20496 * The V9 version register is referred to as '%ver'. 20497 20498 * The V9 window state register is referred to as '%wstate'. 20499 20500 * The Y register is referred to as '%y'. 20501 20502 * The V8 window invalid mask register is referred to as '%wim'. 20503 20504 * The V8 processor state register is referred to as '%psr'. 20505 20506 * The V9 global register level register is referred to as '%gl'. 20507 20508 Several special register names exist for hypervisor mode code: 20509 20510 * The hyperprivileged processor state register is referred to as 20511 '%hpstate'. 20512 20513 * The hyperprivileged trap state register is referred to as 20514 '%htstate'. 20515 20516 * The hyperprivileged interrupt pending register is referred to as 20517 '%hintp'. 20518 20519 * The hyperprivileged trap base address register is referred to as 20520 '%htba'. 20521 20522 * The hyperprivileged implementation version register is referred to 20523 as '%hver'. 20524 20525 * The hyperprivileged system tick offset register is referred to as 20526 '%hstick_offset'. Note that there is no '%hstick' register, the 20527 normal '%stick' is used. 20528 20529 * The hyperprivileged system tick enable register is referred to as 20530 '%hstick_enable'. 20531 20532 * The hyperprivileged system tick compare register is referred to as 20533 '%hstick_cmpr'. 20534 20535 20536File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 20537 205389.44.3.3 Constants 20539.................. 20540 20541Several Sparc instructions take an immediate operand field for which 20542mnemonic names exist. Two such examples are 'membar' and 'prefetch'. 20543Another example are the set of V9 memory access instruction that allow 20544specification of an address space identifier. 20545 20546 The 'membar' instruction specifies a memory barrier that is the 20547defined by the operand which is a bitmask. The supported mask mnemonics 20548are: 20549 20550 * '#Sync' requests that all operations (including nonmemory reference 20551 operations) appearing prior to the 'membar' must have been 20552 performed and the effects of any exceptions become visible before 20553 any instructions after the 'membar' may be initiated. This 20554 corresponds to 'membar' cmask field bit 2. 20555 20556 * '#MemIssue' requests that all memory reference operations appearing 20557 prior to the 'membar' must have been performed before any memory 20558 operation after the 'membar' may be initiated. This corresponds to 20559 'membar' cmask field bit 1. 20560 20561 * '#Lookaside' requests that a store appearing prior to the 'membar' 20562 must complete before any load following the 'membar' referencing 20563 the same address can be initiated. This corresponds to 'membar' 20564 cmask field bit 0. 20565 20566 * '#StoreStore' defines that the effects of all stores appearing 20567 prior to the 'membar' instruction must be visible to all processors 20568 before the effect of any stores following the 'membar'. Equivalent 20569 to the deprecated 'stbar' instruction. This corresponds to 20570 'membar' mmask field bit 3. 20571 20572 * '#LoadStore' defines all loads appearing prior to the 'membar' 20573 instruction must have been performed before the effect of any 20574 stores following the 'membar' is visible to any other processor. 20575 This corresponds to 'membar' mmask field bit 2. 20576 20577 * '#StoreLoad' defines that the effects of all stores appearing prior 20578 to the 'membar' instruction must be visible to all processors 20579 before loads following the 'membar' may be performed. This 20580 corresponds to 'membar' mmask field bit 1. 20581 20582 * '#LoadLoad' defines that all loads appearing prior to the 'membar' 20583 instruction must have been performed before any loads following the 20584 'membar' may be performed. This corresponds to 'membar' mmask 20585 field bit 0. 20586 20587 These values can be ored together, for example: 20588 20589 membar #Sync 20590 membar #StoreLoad | #LoadLoad 20591 membar #StoreLoad | #StoreStore 20592 20593 The 'prefetch' and 'prefetcha' instructions take a prefetch function 20594code. The following prefetch function code constant mnemonics are 20595available: 20596 20597 * '#n_reads' requests a prefetch for several reads, and corresponds 20598 to a prefetch function code of 0. 20599 20600 '#one_read' requests a prefetch for one read, and corresponds to a 20601 prefetch function code of 1. 20602 20603 '#n_writes' requests a prefetch for several writes (and possibly 20604 reads), and corresponds to a prefetch function code of 2. 20605 20606 '#one_write' requests a prefetch for one write, and corresponds to 20607 a prefetch function code of 3. 20608 20609 '#page' requests a prefetch page, and corresponds to a prefetch 20610 function code of 4. 20611 20612 '#invalidate' requests a prefetch invalidate, and corresponds to a 20613 prefetch function code of 16. 20614 20615 '#unified' requests a prefetch to the nearest unified cache, and 20616 corresponds to a prefetch function code of 17. 20617 20618 '#n_reads_strong' requests a strong prefetch for several reads, and 20619 corresponds to a prefetch function code of 20. 20620 20621 '#one_read_strong' requests a strong prefetch for one read, and 20622 corresponds to a prefetch function code of 21. 20623 20624 '#n_writes_strong' requests a strong prefetch for several writes, 20625 and corresponds to a prefetch function code of 22. 20626 20627 '#one_write_strong' requests a strong prefetch for one write, and 20628 corresponds to a prefetch function code of 23. 20629 20630 Onle one prefetch code may be specified. Here are some examples: 20631 20632 prefetch [%l0 + %l2], #one_read 20633 prefetch [%g2 + 8], #n_writes 20634 prefetcha [%g1] 0x8, #unified 20635 prefetcha [%o0 + 0x10] %asi, #n_reads 20636 20637 The actual behavior of a given prefetch function code is processor 20638 specific. If a processor does not implement a given prefetch 20639 function code, it will treat the prefetch instruction as a nop. 20640 20641 For instructions that accept an immediate address space identifier, 20642 'as' provides many mnemonics corresponding to V9 defined as well as 20643 UltraSPARC and Niagara extended values. For example, '#ASI_P' and 20644 '#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor specific 20645 manuals for details. 20646 20647 20648File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 20649 206509.44.3.4 Relocations 20651.................... 20652 20653ELF relocations are available as defined in the 32-bit and 64-bit Sparc 20654ELF specifications. 20655 20656 'R_SPARC_HI22' is obtained using '%hi' and 'R_SPARC_LO10' is obtained 20657using '%lo'. Likewise 'R_SPARC_HIX22' is obtained from '%hix' and 20658'R_SPARC_LOX10' is obtained using '%lox'. For example: 20659 20660 sethi %hi(symbol), %g1 20661 or %g1, %lo(symbol), %g1 20662 20663 sethi %hix(symbol), %g1 20664 xor %g1, %lox(symbol), %g1 20665 20666 These "high" mnemonics extract bits 31:10 of their operand, and the 20667"low" mnemonics extract bits 9:0 of their operand. 20668 20669 V9 code model relocations can be requested as follows: 20670 20671 * 'R_SPARC_HH22' is requested using '%hh'. It can also be generated 20672 using '%uhi'. 20673 * 'R_SPARC_HM10' is requested using '%hm'. It can also be generated 20674 using '%ulo'. 20675 * 'R_SPARC_LM22' is requested using '%lm'. 20676 20677 * 'R_SPARC_H44' is requested using '%h44'. 20678 * 'R_SPARC_M44' is requested using '%m44'. 20679 * 'R_SPARC_L44' is requested using '%l44' or '%l34'. 20680 * 'R_SPARC_H34' is requested using '%h34'. 20681 20682 The '%l34' generates a 'R_SPARC_L44' relocation because it calculates 20683the necessary value, and therefore no explicit 'R_SPARC_L34' relocation 20684needed to be created for this purpose. 20685 20686 The '%h34' and '%l34' relocations are used for the abs34 code model. 20687Here is an example abs34 address generation sequence: 20688 20689 sethi %h34(symbol), %g1 20690 sllx %g1, 2, %g1 20691 or %g1, %l34(symbol), %g1 20692 20693 The PC relative relocation 'R_SPARC_PC22' can be obtained by 20694enclosing an operand inside of '%pc22'. Likewise, the 'R_SPARC_PC10' 20695relocation can be obtained using '%pc10'. These are mostly used when 20696assembling PIC code. For example, the standard PIC sequence on Sparc to 20697get the base of the global offset table, PC relative, into a register, 20698can be performed as: 20699 20700 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 20701 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 20702 20703 Several relocations exist to allow the link editor to potentially 20704optimize GOT data references. The 'R_SPARC_GOTDATA_OP_HIX22' relocation 20705can obtained by enclosing an operand inside of '%gdop_hix22'. The 20706'R_SPARC_GOTDATA_OP_LOX10' relocation can obtained by enclosing an 20707operand inside of '%gdop_lox10'. Likewise, 'R_SPARC_GOTDATA_OP' can be 20708obtained by enclosing an operand inside of '%gdop'. For example, 20709assuming the GOT base is in register '%l7': 20710 20711 sethi %gdop_hix22(symbol), %l1 20712 xor %l1, %gdop_lox10(symbol), %l1 20713 ld [%l7 + %l1], %l2, %gdop(symbol) 20714 20715 There are many relocations that can be requested for access to thread 20716local storage variables. All of the Sparc TLS mnemonics are supported: 20717 20718 * 'R_SPARC_TLS_GD_HI22' is requested using '%tgd_hi22'. 20719 * 'R_SPARC_TLS_GD_LO10' is requested using '%tgd_lo10'. 20720 * 'R_SPARC_TLS_GD_ADD' is requested using '%tgd_add'. 20721 * 'R_SPARC_TLS_GD_CALL' is requested using '%tgd_call'. 20722 20723 * 'R_SPARC_TLS_LDM_HI22' is requested using '%tldm_hi22'. 20724 * 'R_SPARC_TLS_LDM_LO10' is requested using '%tldm_lo10'. 20725 * 'R_SPARC_TLS_LDM_ADD' is requested using '%tldm_add'. 20726 * 'R_SPARC_TLS_LDM_CALL' is requested using '%tldm_call'. 20727 20728 * 'R_SPARC_TLS_LDO_HIX22' is requested using '%tldo_hix22'. 20729 * 'R_SPARC_TLS_LDO_LOX10' is requested using '%tldo_lox10'. 20730 * 'R_SPARC_TLS_LDO_ADD' is requested using '%tldo_add'. 20731 20732 * 'R_SPARC_TLS_IE_HI22' is requested using '%tie_hi22'. 20733 * 'R_SPARC_TLS_IE_LO10' is requested using '%tie_lo10'. 20734 * 'R_SPARC_TLS_IE_LD' is requested using '%tie_ld'. 20735 * 'R_SPARC_TLS_IE_LDX' is requested using '%tie_ldx'. 20736 * 'R_SPARC_TLS_IE_ADD' is requested using '%tie_add'. 20737 20738 * 'R_SPARC_TLS_LE_HIX22' is requested using '%tle_hix22'. 20739 * 'R_SPARC_TLS_LE_LOX10' is requested using '%tle_lox10'. 20740 20741 Here are some example TLS model sequences. 20742 20743 First, General Dynamic: 20744 20745 sethi %tgd_hi22(symbol), %l1 20746 add %l1, %tgd_lo10(symbol), %l1 20747 add %l7, %l1, %o0, %tgd_add(symbol) 20748 call __tls_get_addr, %tgd_call(symbol) 20749 nop 20750 20751 Local Dynamic: 20752 20753 sethi %tldm_hi22(symbol), %l1 20754 add %l1, %tldm_lo10(symbol), %l1 20755 add %l7, %l1, %o0, %tldm_add(symbol) 20756 call __tls_get_addr, %tldm_call(symbol) 20757 nop 20758 20759 sethi %tldo_hix22(symbol), %l1 20760 xor %l1, %tldo_lox10(symbol), %l1 20761 add %o0, %l1, %l1, %tldo_add(symbol) 20762 20763 Initial Exec: 20764 20765 sethi %tie_hi22(symbol), %l1 20766 add %l1, %tie_lo10(symbol), %l1 20767 ld [%l7 + %l1], %o0, %tie_ld(symbol) 20768 add %g7, %o0, %o0, %tie_add(symbol) 20769 20770 sethi %tie_hi22(symbol), %l1 20771 add %l1, %tie_lo10(symbol), %l1 20772 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 20773 add %g7, %o0, %o0, %tie_add(symbol) 20774 20775 And finally, Local Exec: 20776 20777 sethi %tle_hix22(symbol), %l1 20778 add %l1, %tle_lox10(symbol), %l1 20779 add %g7, %l1, %l1 20780 20781 When assembling for 64-bit, and a secondary constant addend is 20782specified in an address expression that would normally generate an 20783'R_SPARC_LO10' relocation, the assembler will emit an 'R_SPARC_OLO10' 20784instead. 20785 20786 20787File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 20788 207899.44.3.5 Size Translations 20790.......................... 20791 20792Often it is desirable to write code in an operand size agnostic manner. 20793'as' provides support for this via operand size opcode translations. 20794Translations are supported for loads, stores, shifts, compare-and-swap 20795atomics, and the 'clr' synthetic instruction. 20796 20797 If generating 32-bit code, 'as' will generate the 32-bit opcode. 20798Whereas if 64-bit code is being generated, the 64-bit opcode will be 20799emitted. For example 'ldn' will be transformed into 'ld' for 32-bit 20800code and 'ldx' for 64-bit code. 20801 20802 Here is an example meant to demonstrate all the supported opcode 20803translations: 20804 20805 ldn [%o0], %o1 20806 ldna [%o0] %asi, %o2 20807 stn %o1, [%o0] 20808 stna %o2, [%o0] %asi 20809 slln %o3, 3, %o3 20810 srln %o4, 8, %o4 20811 sran %o5, 12, %o5 20812 casn [%o0], %o1, %o2 20813 casna [%o0] %asi, %o1, %o2 20814 clrn %g1 20815 20816 In 32-bit mode 'as' will emit: 20817 20818 ld [%o0], %o1 20819 lda [%o0] %asi, %o2 20820 st %o1, [%o0] 20821 sta %o2, [%o0] %asi 20822 sll %o3, 3, %o3 20823 srl %o4, 8, %o4 20824 sra %o5, 12, %o5 20825 cas [%o0], %o1, %o2 20826 casa [%o0] %asi, %o1, %o2 20827 clr %g1 20828 20829 And in 64-bit mode 'as' will emit: 20830 20831 ldx [%o0], %o1 20832 ldxa [%o0] %asi, %o2 20833 stx %o1, [%o0] 20834 stxa %o2, [%o0] %asi 20835 sllx %o3, 3, %o3 20836 srlx %o4, 8, %o4 20837 srax %o5, 12, %o5 20838 casx [%o0], %o1, %o2 20839 casxa [%o0] %asi, %o1, %o2 20840 clrx %g1 20841 20842 Finally, the '.nword' translating directive is supported as well. It 20843is documented in the section on Sparc machine directives. 20844 20845 20846File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 20847 208489.44.4 Floating Point 20849--------------------- 20850 20851The Sparc uses IEEE floating-point numbers. 20852 20853 20854File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 20855 208569.44.5 Sparc Machine Directives 20857------------------------------- 20858 20859The Sparc version of 'as' supports the following additional machine 20860directives: 20861 20862'.align' 20863 This must be followed by the desired alignment in bytes. 20864 20865'.common' 20866 This must be followed by a symbol name, a positive number, and 20867 '"bss"'. This behaves somewhat like '.comm', but the syntax is 20868 different. 20869 20870'.half' 20871 This is functionally identical to '.short'. 20872 20873'.nword' 20874 On the Sparc, the '.nword' directive produces native word sized 20875 value, ie. if assembling with -32 it is equivalent to '.word', if 20876 assembling with -64 it is equivalent to '.xword'. 20877 20878'.proc' 20879 This directive is ignored. Any text following it on the same line 20880 is also ignored. 20881 20882'.register' 20883 This directive declares use of a global application or system 20884 register. It must be followed by a register name %g2, %g3, %g6 or 20885 %g7, comma and the symbol name for that register. If symbol name 20886 is '#scratch', it is a scratch register, if it is '#ignore', it 20887 just suppresses any errors about using undeclared global register, 20888 but does not emit any information about it into the object file. 20889 This can be useful e.g. if you save the register before use and 20890 restore it after. 20891 20892'.reserve' 20893 This must be followed by a symbol name, a positive number, and 20894 '"bss"'. This behaves somewhat like '.lcomm', but the syntax is 20895 different. 20896 20897'.seg' 20898 This must be followed by '"text"', '"data"', or '"data1"'. It 20899 behaves like '.text', '.data', or '.data 1'. 20900 20901'.skip' 20902 This is functionally identical to the '.space' directive. 20903 20904'.word' 20905 On the Sparc, the '.word' directive produces 32 bit values, instead 20906 of the 16 bit values it produces on many other machines. 20907 20908'.xword' 20909 On the Sparc V9 processor, the '.xword' directive produces 64 bit 20910 values. 20911 20912 20913File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 20914 209159.45 TIC54X Dependent Features 20916============================== 20917 20918* Menu: 20919 20920* TIC54X-Opts:: Command-line Options 20921* TIC54X-Block:: Blocking 20922* TIC54X-Env:: Environment Settings 20923* TIC54X-Constants:: Constants Syntax 20924* TIC54X-Subsyms:: String Substitution 20925* TIC54X-Locals:: Local Label Syntax 20926* TIC54X-Builtins:: Builtin Assembler Math Functions 20927* TIC54X-Ext:: Extended Addressing Support 20928* TIC54X-Directives:: Directives 20929* TIC54X-Macros:: Macro Features 20930* TIC54X-MMRegs:: Memory-mapped Registers 20931* TIC54X-Syntax:: Syntax 20932 20933 20934File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 20935 209369.45.1 Options 20937-------------- 20938 20939The TMS320C54X version of 'as' has a few machine-dependent options. 20940 20941 You can use the '-mfar-mode' option to enable extended addressing 20942mode. All addresses will be assumed to be > 16 bits, and the 20943appropriate relocation types will be used. This option is equivalent to 20944using the '.far_mode' directive in the assembly code. If you do not use 20945the '-mfar-mode' option, all references will be assumed to be 16 bits. 20946This option may be abbreviated to '-mf'. 20947 20948 You can use the '-mcpu' option to specify a particular CPU. This 20949option is equivalent to using the '.version' directive in the assembly 20950code. For recognized CPU codes, see *Note '.version': 20951TIC54X-Directives. The default CPU version is '542'. 20952 20953 You can use the '-merrors-to-file' option to redirect error output to 20954a file (this provided for those deficient environments which don't 20955provide adequate output redirection). This option may be abbreviated to 20956'-me'. 20957 20958 20959File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 20960 209619.45.2 Blocking 20962--------------- 20963 20964A blocked section or memory block is guaranteed not to cross the 20965blocking boundary (usually a page, or 128 words) if it is smaller than 20966the blocking size, or to start on a page boundary if it is larger than 20967the blocking size. 20968 20969 20970File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 20971 209729.45.3 Environment Settings 20973--------------------------- 20974 20975'C54XDSP_DIR' and 'A_DIR' are semicolon-separated paths which are added 20976to the list of directories normally searched for source and include 20977files. 'C54XDSP_DIR' will override 'A_DIR'. 20978 20979 20980File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 20981 209829.45.4 Constants Syntax 20983----------------------- 20984 20985The TIC54X version of 'as' allows the following additional constant 20986formats, using a suffix to indicate the radix: 20987 20988 Binary 000000B, 011000b 20989 Octal 10Q, 224q 20990 Hexadecimal 45h, 0FH 20991 20992 20993 20994File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 20995 209969.45.5 String Substitution 20997-------------------------- 20998 20999A subset of allowable symbols (which we'll call subsyms) may be assigned 21000arbitrary string values. This is roughly equivalent to C preprocessor 21001#define macros. When 'as' encounters one of these symbols, the symbol 21002is replaced in the input stream by its string value. Subsym names 21003*must* begin with a letter. 21004 21005 Subsyms may be defined using the '.asg' and '.eval' directives (*Note 21006'.asg': TIC54X-Directives, *Note '.eval': TIC54X-Directives. 21007 21008 Expansion is recursive until a previously encountered symbol is seen, 21009at which point substitution stops. 21010 21011 In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, 21012and SYM1 is replaced with x. At this point, x has already been 21013encountered and the substitution stops. 21014 21015 .asg "x",SYM1 21016 .asg "SYM1",SYM2 21017 .asg "SYM2",x 21018 add x,a ; final code assembled is "add x, a" 21019 21020 Macro parameters are converted to subsyms; a side effect of this is 21021the normal 'as' '\ARG' dereferencing syntax is unnecessary. Subsyms 21022defined within a macro will have global scope, unless the '.var' 21023directive is used to identify the subsym as a local macro variable *note 21024'.var': TIC54X-Directives. 21025 21026 Substitution may be forced in situations where replacement might be 21027ambiguous by placing colons on either side of the subsym. The following 21028code: 21029 21030 .eval "10",x 21031 LAB:X: add #x, a 21032 21033 When assembled becomes: 21034 21035 LAB10 add #10, a 21036 21037 Smaller parts of the string assigned to a subsym may be accessed with 21038the following syntax: 21039 21040':SYMBOL(CHAR_INDEX):' 21041 Evaluates to a single-character string, the character at 21042 CHAR_INDEX. 21043':SYMBOL(START,LENGTH):' 21044 Evaluates to a substring of SYMBOL beginning at START with length 21045 LENGTH. 21046 21047 21048File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 21049 210509.45.6 Local Labels 21051------------------- 21052 21053Local labels may be defined in two ways: 21054 21055 * $N, where N is a decimal number between 0 and 9 21056 * LABEL?, where LABEL is any legal symbol name. 21057 21058 Local labels thus defined may be redefined or automatically 21059generated. The scope of a local label is based on when it may be 21060undefined or reset. This happens when one of the following situations 21061is encountered: 21062 21063 * .newblock directive *note '.newblock': TIC54X-Directives. 21064 * The current section is changed (.sect, .text, or .data) 21065 * Entering or leaving an included file 21066 * The macro scope where the label was defined is exited 21067 21068 21069File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 21070 210719.45.7 Math Builtins 21072-------------------- 21073 21074The following built-in functions may be used to generate a 21075floating-point value. All return a floating-point value except '$cvi', 21076'$int', and '$sgn', which return an integer value. 21077 21078'$acos(EXPR)' 21079 Returns the floating point arccosine of EXPR. 21080 21081'$asin(EXPR)' 21082 Returns the floating point arcsine of EXPR. 21083 21084'$atan(EXPR)' 21085 Returns the floating point arctangent of EXPR. 21086 21087'$atan2(EXPR1,EXPR2)' 21088 Returns the floating point arctangent of EXPR1 / EXPR2. 21089 21090'$ceil(EXPR)' 21091 Returns the smallest integer not less than EXPR as floating point. 21092 21093'$cosh(EXPR)' 21094 Returns the floating point hyperbolic cosine of EXPR. 21095 21096'$cos(EXPR)' 21097 Returns the floating point cosine of EXPR. 21098 21099'$cvf(EXPR)' 21100 Returns the integer value EXPR converted to floating-point. 21101 21102'$cvi(EXPR)' 21103 Returns the floating point value EXPR converted to integer. 21104 21105'$exp(EXPR)' 21106 Returns the floating point value e ^ EXPR. 21107 21108'$fabs(EXPR)' 21109 Returns the floating point absolute value of EXPR. 21110 21111'$floor(EXPR)' 21112 Returns the largest integer that is not greater than EXPR as 21113 floating point. 21114 21115'$fmod(EXPR1,EXPR2)' 21116 Returns the floating point remainder of EXPR1 / EXPR2. 21117 21118'$int(EXPR)' 21119 Returns 1 if EXPR evaluates to an integer, zero otherwise. 21120 21121'$ldexp(EXPR1,EXPR2)' 21122 Returns the floating point value EXPR1 * 2 ^ EXPR2. 21123 21124'$log10(EXPR)' 21125 Returns the base 10 logarithm of EXPR. 21126 21127'$log(EXPR)' 21128 Returns the natural logarithm of EXPR. 21129 21130'$max(EXPR1,EXPR2)' 21131 Returns the floating point maximum of EXPR1 and EXPR2. 21132 21133'$min(EXPR1,EXPR2)' 21134 Returns the floating point minimum of EXPR1 and EXPR2. 21135 21136'$pow(EXPR1,EXPR2)' 21137 Returns the floating point value EXPR1 ^ EXPR2. 21138 21139'$round(EXPR)' 21140 Returns the nearest integer to EXPR as a floating point number. 21141 21142'$sgn(EXPR)' 21143 Returns -1, 0, or 1 based on the sign of EXPR. 21144 21145'$sin(EXPR)' 21146 Returns the floating point sine of EXPR. 21147 21148'$sinh(EXPR)' 21149 Returns the floating point hyperbolic sine of EXPR. 21150 21151'$sqrt(EXPR)' 21152 Returns the floating point square root of EXPR. 21153 21154'$tan(EXPR)' 21155 Returns the floating point tangent of EXPR. 21156 21157'$tanh(EXPR)' 21158 Returns the floating point hyperbolic tangent of EXPR. 21159 21160'$trunc(EXPR)' 21161 Returns the integer value of EXPR truncated towards zero as 21162 floating point. 21163 21164 21165File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 21166 211679.45.8 Extended Addressing 21168-------------------------- 21169 21170The 'LDX' pseudo-op is provided for loading the extended addressing bits 21171of a label or address. For example, if an address '_label' resides in 21172extended program memory, the value of '_label' may be loaded as follows: 21173 ldx #_label,16,a ; loads extended bits of _label 21174 or #_label,a ; loads lower 16 bits of _label 21175 bacc a ; full address is in accumulator A 21176 21177 21178File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 21179 211809.45.9 Directives 21181----------------- 21182 21183'.align [SIZE]' 21184'.even' 21185 Align the section program counter on the next boundary, based on 21186 SIZE. SIZE may be any power of 2. '.even' is equivalent to 21187 '.align' with a SIZE of 2. 21188 '1' 21189 Align SPC to word boundary 21190 '2' 21191 Align SPC to longword boundary (same as .even) 21192 '128' 21193 Align SPC to page boundary 21194 21195'.asg STRING, NAME' 21196 Assign NAME the string STRING. String replacement is performed on 21197 STRING before assignment. 21198 21199'.eval STRING, NAME' 21200 Evaluate the contents of string STRING and assign the result as a 21201 string to the subsym NAME. String replacement is performed on 21202 STRING before assignment. 21203 21204'.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 21205 Reserve space for SYMBOL in the .bss section. SIZE is in words. 21206 If present, BLOCKING_FLAG indicates the allocated space should be 21207 aligned on a page boundary if it would otherwise cross a page 21208 boundary. If present, ALIGNMENT_FLAG causes the assembler to 21209 allocate SIZE on a long word boundary. 21210 21211'.byte VALUE [,...,VALUE_N]' 21212'.ubyte VALUE [,...,VALUE_N]' 21213'.char VALUE [,...,VALUE_N]' 21214'.uchar VALUE [,...,VALUE_N]' 21215 Place one or more bytes into consecutive words of the current 21216 section. The upper 8 bits of each word is zero-filled. If a label 21217 is used, it points to the word allocated for the first byte 21218 encountered. 21219 21220'.clink ["SECTION_NAME"]' 21221 Set STYP_CLINK flag for this section, which indicates to the linker 21222 that if no symbols from this section are referenced, the section 21223 should not be included in the link. If SECTION_NAME is omitted, 21224 the current section is used. 21225 21226'.c_mode' 21227 TBD. 21228 21229'.copy "FILENAME" | FILENAME' 21230'.include "FILENAME" | FILENAME' 21231 Read source statements from FILENAME. The normal include search 21232 path is used. Normally .copy will cause statements from the 21233 included file to be printed in the assembly listing and .include 21234 will not, but this distinction is not currently implemented. 21235 21236'.data' 21237 Begin assembling code into the .data section. 21238 21239'.double VALUE [,...,VALUE_N]' 21240'.ldouble VALUE [,...,VALUE_N]' 21241'.float VALUE [,...,VALUE_N]' 21242'.xfloat VALUE [,...,VALUE_N]' 21243 Place an IEEE single-precision floating-point representation of one 21244 or more floating-point values into the current section. All but 21245 '.xfloat' align the result on a longword boundary. Values are 21246 stored most-significant word first. 21247 21248'.drlist' 21249'.drnolist' 21250 Control printing of directives to the listing file. Ignored. 21251 21252'.emsg STRING' 21253'.mmsg STRING' 21254'.wmsg STRING' 21255 Emit a user-defined error, message, or warning, respectively. 21256 21257'.far_mode' 21258 Use extended addressing when assembling statements. This should 21259 appear only once per file, and is equivalent to the -mfar-mode 21260 option *note '-mfar-mode': TIC54X-Opts. 21261 21262'.fclist' 21263'.fcnolist' 21264 Control printing of false conditional blocks to the listing file. 21265 21266'.field VALUE [,SIZE]' 21267 Initialize a bitfield of SIZE bits in the current section. If 21268 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 21269 bits. If VALUE does not fit into SIZE bits, the value will be 21270 truncated. Successive '.field' directives will pack starting at 21271 the current word, filling the most significant bits first, and 21272 aligning to the start of the next word if the field size does not 21273 fit into the space remaining in the current word. A '.align' 21274 directive with an operand of 1 will force the next '.field' 21275 directive to begin packing into a new word. If a label is used, it 21276 points to the word that contains the specified field. 21277 21278'.global SYMBOL [,...,SYMBOL_N]' 21279'.def SYMBOL [,...,SYMBOL_N]' 21280'.ref SYMBOL [,...,SYMBOL_N]' 21281 '.def' nominally identifies a symbol defined in the current file 21282 and available to other files. '.ref' identifies a symbol used in 21283 the current file but defined elsewhere. Both map to the standard 21284 '.global' directive. 21285 21286'.half VALUE [,...,VALUE_N]' 21287'.uhalf VALUE [,...,VALUE_N]' 21288'.short VALUE [,...,VALUE_N]' 21289'.ushort VALUE [,...,VALUE_N]' 21290'.int VALUE [,...,VALUE_N]' 21291'.uint VALUE [,...,VALUE_N]' 21292'.word VALUE [,...,VALUE_N]' 21293'.uword VALUE [,...,VALUE_N]' 21294 Place one or more values into consecutive words of the current 21295 section. If a label is used, it points to the word allocated for 21296 the first value encountered. 21297 21298'.label SYMBOL' 21299 Define a special SYMBOL to refer to the load time address of the 21300 current section program counter. 21301 21302'.length' 21303'.width' 21304 Set the page length and width of the output listing file. Ignored. 21305 21306'.list' 21307'.nolist' 21308 Control whether the source listing is printed. Ignored. 21309 21310'.long VALUE [,...,VALUE_N]' 21311'.ulong VALUE [,...,VALUE_N]' 21312'.xlong VALUE [,...,VALUE_N]' 21313 Place one or more 32-bit values into consecutive words in the 21314 current section. The most significant word is stored first. 21315 '.long' and '.ulong' align the result on a longword boundary; 21316 'xlong' does not. 21317 21318'.loop [COUNT]' 21319'.break [CONDITION]' 21320'.endloop' 21321 Repeatedly assemble a block of code. '.loop' begins the block, and 21322 '.endloop' marks its termination. COUNT defaults to 1024, and 21323 indicates the number of times the block should be repeated. 21324 '.break' terminates the loop so that assembly begins after the 21325 '.endloop' directive. The optional CONDITION will cause the loop 21326 to terminate only if it evaluates to zero. 21327 21328'MACRO_NAME .macro [PARAM1][,...PARAM_N]' 21329'[.mexit]' 21330'.endm' 21331 See the section on macros for more explanation (*Note 21332 TIC54X-Macros::. 21333 21334'.mlib "FILENAME" | FILENAME' 21335 Load the macro library FILENAME. FILENAME must be an archived 21336 library (BFD ar-compatible) of text files, expected to contain only 21337 macro definitions. The standard include search path is used. 21338 21339'.mlist' 21340'.mnolist' 21341 Control whether to include macro and loop block expansions in the 21342 listing output. Ignored. 21343 21344'.mmregs' 21345 Define global symbolic names for the 'c54x registers. Supposedly 21346 equivalent to executing '.set' directives for each register with 21347 its memory-mapped value, but in reality is provided only for 21348 compatibility and does nothing. 21349 21350'.newblock' 21351 This directive resets any TIC54X local labels currently defined. 21352 Normal 'as' local labels are unaffected. 21353 21354'.option OPTION_LIST' 21355 Set listing options. Ignored. 21356 21357'.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 21358 Designate SECTION_NAME for blocking. Blocking guarantees that a 21359 section will start on a page boundary (128 words) if it would 21360 otherwise cross a page boundary. Only initialized sections may be 21361 designated with this directive. See also *Note TIC54X-Block::. 21362 21363'.sect "SECTION_NAME"' 21364 Define a named initialized section and make it the current section. 21365 21366'SYMBOL .set "VALUE"' 21367'SYMBOL .equ "VALUE"' 21368 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 21369 table. SYMBOL may not be previously defined. 21370 21371'.space SIZE_IN_BITS' 21372'.bes SIZE_IN_BITS' 21373 Reserve the given number of bits in the current section and 21374 zero-fill them. If a label is used with '.space', it points to the 21375 *first* word reserved. With '.bes', the label points to the *last* 21376 word reserved. 21377 21378'.sslist' 21379'.ssnolist' 21380 Controls the inclusion of subsym replacement in the listing output. 21381 Ignored. 21382 21383'.string "STRING" [,...,"STRING_N"]' 21384'.pstring "STRING" [,...,"STRING_N"]' 21385 Place 8-bit characters from STRING into the current section. 21386 '.string' zero-fills the upper 8 bits of each word, while 21387 '.pstring' puts two characters into each word, filling the 21388 most-significant bits first. Unused space is zero-filled. If a 21389 label is used, it points to the first word initialized. 21390 21391'[STAG] .struct [OFFSET]' 21392'[NAME_1] element [COUNT_1]' 21393'[NAME_2] element [COUNT_2]' 21394'[TNAME] .tag STAGX [TCOUNT]' 21395'...' 21396'[NAME_N] element [COUNT_N]' 21397'[SSIZE] .endstruct' 21398'LABEL .tag [STAG]' 21399 Assign symbolic offsets to the elements of a structure. STAG 21400 defines a symbol to use to reference the structure. OFFSET 21401 indicates a starting value to use for the first element 21402 encountered; otherwise it defaults to zero. Each element can have 21403 a named offset, NAME, which is a symbol assigned the value of the 21404 element's offset into the structure. If STAG is missing, these 21405 become global symbols. COUNT adjusts the offset that many times, 21406 as if 'element' were an array. 'element' may be one of '.byte', 21407 '.word', '.long', '.float', or any equivalent of those, and the 21408 structure offset is adjusted accordingly. '.field' and '.string' 21409 are also allowed; the size of '.field' is one bit, and '.string' is 21410 considered to be one word in size. Only element descriptors, 21411 structure/union tags, '.align' and conditional assembly directives 21412 are allowed within '.struct'/'.endstruct'. '.align' aligns member 21413 offsets to word boundaries only. SSIZE, if provided, will always 21414 be assigned the size of the structure. 21415 21416 The '.tag' directive, in addition to being used to define a 21417 structure/union element within a structure, may be used to apply a 21418 structure to a symbol. Once applied to LABEL, the individual 21419 structure elements may be applied to LABEL to produce the desired 21420 offsets using LABEL as the structure base. 21421 21422'.tab' 21423 Set the tab size in the output listing. Ignored. 21424 21425'[UTAG] .union' 21426'[NAME_1] element [COUNT_1]' 21427'[NAME_2] element [COUNT_2]' 21428'[TNAME] .tag UTAGX[,TCOUNT]' 21429'...' 21430'[NAME_N] element [COUNT_N]' 21431'[USIZE] .endstruct' 21432'LABEL .tag [UTAG]' 21433 Similar to '.struct', but the offset after each element is reset to 21434 zero, and the USIZE is set to the maximum of all defined elements. 21435 Starting offset for the union is always zero. 21436 21437'[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 21438 Reserve space for variables in a named, uninitialized section 21439 (similar to .bss). '.usect' allows definitions sections 21440 independent of .bss. SYMBOL points to the first location reserved 21441 by this allocation. The symbol may be used as a variable name. 21442 SIZE is the allocated size in words. BLOCKING_FLAG indicates 21443 whether to block this section on a page boundary (128 words) (*note 21444 TIC54X-Block::). ALIGNMENT FLAG indicates whether the section 21445 should be longword-aligned. 21446 21447'.var SYM[,..., SYM_N]' 21448 Define a subsym to be a local variable within a macro. See *Note 21449 TIC54X-Macros::. 21450 21451'.version VERSION' 21452 Set which processor to build instructions for. Though the 21453 following values are accepted, the op is ignored. 21454 '541' 21455 '542' 21456 '543' 21457 '545' 21458 '545LP' 21459 '546LP' 21460 '548' 21461 '549' 21462 21463 21464File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 21465 214669.45.10 Macros 21467-------------- 21468 21469Macros do not require explicit dereferencing of arguments (i.e., \ARG). 21470 21471 During macro expansion, the macro parameters are converted to 21472subsyms. If the number of arguments passed the macro invocation exceeds 21473the number of parameters defined, the last parameter is assigned the 21474string equivalent of all remaining arguments. If fewer arguments are 21475given than parameters, the missing parameters are assigned empty 21476strings. To include a comma in an argument, you must enclose the 21477argument in quotes. 21478 21479 The following built-in subsym functions allow examination of the 21480string value of subsyms (or ordinary strings). The arguments are 21481strings unless otherwise indicated (subsyms passed as args will be 21482replaced by the strings they represent). 21483'$symlen(STR)' 21484 Returns the length of STR. 21485 21486'$symcmp(STR1,STR2)' 21487 Returns 0 if STR1 == STR2, non-zero otherwise. 21488 21489'$firstch(STR,CH)' 21490 Returns index of the first occurrence of character constant CH in 21491 STR. 21492 21493'$lastch(STR,CH)' 21494 Returns index of the last occurrence of character constant CH in 21495 STR. 21496 21497'$isdefed(SYMBOL)' 21498 Returns zero if the symbol SYMBOL is not in the symbol table, 21499 non-zero otherwise. 21500 21501'$ismember(SYMBOL,LIST)' 21502 Assign the first member of comma-separated string LIST to SYMBOL; 21503 LIST is reassigned the remainder of the list. Returns zero if LIST 21504 is a null string. Both arguments must be subsyms. 21505 21506'$iscons(EXPR)' 21507 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4 21508 if a character, 5 if decimal, and zero if not an integer. 21509 21510'$isname(NAME)' 21511 Returns 1 if NAME is a valid symbol name, zero otherwise. 21512 21513'$isreg(REG)' 21514 Returns 1 if REG is a valid predefined register name (AR0-AR7 21515 only). 21516 21517'$structsz(STAG)' 21518 Returns the size of the structure or union represented by STAG. 21519 21520'$structacc(STAG)' 21521 Returns the reference point of the structure or union represented 21522 by STAG. Always returns zero. 21523 21524 21525File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent 21526 215279.45.11 Memory-mapped Registers 21528------------------------------- 21529 21530The following symbols are recognized as memory-mapped registers: 21531 21532 21533File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent 21534 215359.45.12 TIC54X Syntax 21536--------------------- 21537 21538* Menu: 21539 21540* TIC54X-Chars:: Special Characters 21541 21542 21543File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax 21544 215459.45.12.1 Special Characters 21546............................ 21547 21548The presence of a ';' appearing anywhere on a line indicates the start 21549of a comment that extends to the end of that line. 21550 21551 If a '#' appears as the first character of a line then the whole line 21552is treated as a comment, but in this case the line can also be a logical 21553line number directive (*note Comments::) or a preprocessor control 21554command (*note Preprocessing::). 21555 21556 The presence of an asterisk ('*') at the start of a line also 21557indicates a comment that extends to the end of that line. 21558 21559 The TIC54X assembler does not currently support a line separator 21560character. 21561 21562 21563File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 21564 215659.46 TIC6X Dependent Features 21566============================= 21567 21568* Menu: 21569 21570* TIC6X Options:: Options 21571* TIC6X Syntax:: Syntax 21572* TIC6X Directives:: Directives 21573 21574 21575File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 21576 215779.46.1 TIC6X Options 21578-------------------- 21579 21580'-march=ARCH' 21581 Enable (only) instructions from architecture ARCH. By default, all 21582 instructions are permitted. 21583 21584 The following values of ARCH are accepted: 'c62x', 'c64x', 'c64x+', 21585 'c67x', 'c67x+', 'c674x'. 21586 21587'-mdsbt' 21588'-mno-dsbt' 21589 The '-mdsbt' option causes the assembler to generate the 21590 'Tag_ABI_DSBT' attribute with a value of 1, indicating that the 21591 code is using DSBT addressing. The '-mno-dsbt' option, the 21592 default, causes the tag to have a value of 0, indicating that the 21593 code does not use DSBT addressing. The linker will emit a warning 21594 if objects of different type (DSBT and non-DSBT) are linked 21595 together. 21596 21597'-mpid=no' 21598'-mpid=near' 21599'-mpid=far' 21600 The '-mpid=' option causes the assembler to generate the 21601 'Tag_ABI_PID' attribute with a value indicating the form of data 21602 addressing used by the code. '-mpid=no', the default, indicates 21603 position-dependent data addressing, '-mpid=near' indicates 21604 position-independent addressing with GOT accesses using near DP 21605 addressing, and '-mpid=far' indicates position-independent 21606 addressing with GOT accesses using far DP addressing. The linker 21607 will emit a warning if objects built with different settings of 21608 this option are linked together. 21609 21610'-mpic' 21611'-mno-pic' 21612 The '-mpic' option causes the assembler to generate the 21613 'Tag_ABI_PIC' attribute with a value of 1, indicating that the code 21614 is using position-independent code addressing, The '-mno-pic' 21615 option, the default, causes the tag to have a value of 0, 21616 indicating position-dependent code addressing. The linker will 21617 emit a warning if objects of different type (position-dependent and 21618 position-independent) are linked together. 21619 21620'-mbig-endian' 21621'-mlittle-endian' 21622 Generate code for the specified endianness. The default is 21623 little-endian. 21624 21625 21626File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 21627 216289.46.2 TIC6X Syntax 21629------------------- 21630 21631The presence of a ';' on a line indicates the start of a comment that 21632extends to the end of the current line. If a '#' or '*' appears as the 21633first character of a line, the whole line is treated as a comment. Note 21634that if a line starts with a '#' character then it can also be a logical 21635line number directive (*note Comments::) or a preprocessor control 21636command (*note Preprocessing::). 21637 21638 The '@' character can be used instead of a newline to separate 21639statements. 21640 21641 Instruction, register and functional unit names are case-insensitive. 21642'as' requires fully-specified functional unit names, such as '.S1', 21643'.L1X' or '.D1T2', on all instructions using a functional unit. 21644 21645 For some instructions, there may be syntactic ambiguity between 21646register or functional unit names and the names of labels or other 21647symbols. To avoid this, enclose the ambiguous symbol name in 21648parentheses; register and functional unit names may not be enclosed in 21649parentheses. 21650 21651 21652File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 21653 216549.46.3 TIC6X Directives 21655----------------------- 21656 21657Directives controlling the set of instructions accepted by the assembler 21658have effect for instructions between the directive and any subsequent 21659directive overriding it. 21660 21661'.arch ARCH' 21662 This has the same effect as '-march=ARCH'. 21663 21664'.cantunwind' 21665 Prevents unwinding through the current function. No personality 21666 routine or exception table data is required or permitted. 21667 21668 If this is not specified then frame unwinding information will be 21669 constructed from CFI directives. *note CFI directives::. 21670 21671'.c6xabi_attribute TAG, VALUE' 21672 Set the C6000 EABI build attribute TAG to VALUE. 21673 21674 The TAG is either an attribute number or one of 'Tag_ISA', 21675 'Tag_ABI_wchar_t', 'Tag_ABI_stack_align_needed', 21676 'Tag_ABI_stack_align_preserved', 'Tag_ABI_DSBT', 'Tag_ABI_PID', 21677 'Tag_ABI_PIC', 'TAG_ABI_array_object_alignment', 21678 'TAG_ABI_array_object_align_expected', 'Tag_ABI_compatibility' and 21679 'Tag_ABI_conformance'. The VALUE is either a 'number', '"string"', 21680 or 'number, "string"' depending on the tag. 21681 21682'.ehtype SYMBOL' 21683 Output an exception type table reference to SYMBOL. 21684 21685'.endp' 21686 Marks the end of and exception table or function. If preceded by a 21687 '.handlerdata' directive then this also switched back to the 21688 previous text section. 21689 21690'.handlerdata' 21691 Marks the end of the current function, and the start of the 21692 exception table entry for that function. Anything between this 21693 directive and the '.endp' directive will be added to the exception 21694 table entry. 21695 21696 Must be preceded by a CFI block containing a '.cfi_lsda' directive. 21697 21698'.nocmp' 21699 Disallow use of C64x+ compact instructions in the current text 21700 section. 21701 21702'.personalityindex INDEX' 21703 Sets the personality routine for the current function to the ABI 21704 specified compact routine number INDEX 21705 21706'.personality NAME' 21707 Sets the personality routine for the current function to NAME. 21708 21709'.scomm SYMBOL, SIZE, ALIGN' 21710 Like '.comm', creating a common symbol SYMBOL with size SIZE and 21711 alignment ALIGN, but unlike when using '.comm', this symbol will be 21712 placed into the small BSS section by the linker. 21713 21714 21715File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 21716 217179.47 TILE-Gx Dependent Features 21718=============================== 21719 21720* Menu: 21721 21722* TILE-Gx Options:: TILE-Gx Options 21723* TILE-Gx Syntax:: TILE-Gx Syntax 21724* TILE-Gx Directives:: TILE-Gx Directives 21725 21726 21727File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent 21728 217299.47.1 Options 21730-------------- 21731 21732The following table lists all available TILE-Gx specific options: 21733 21734'-m32 | -m64' 21735 Select the word size, either 32 bits or 64 bits. 21736 21737'-EB | -EL' 21738 Select the endianness, either big-endian (-EB) or little-endian 21739 (-EL). 21740 21741 21742File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent 21743 217449.47.2 Syntax 21745------------- 21746 21747Block comments are delimited by '/*' and '*/'. End of line comments may 21748be introduced by '#'. 21749 21750 Instructions consist of a leading opcode or macro name followed by 21751whitespace and an optional comma-separated list of operands: 21752 21753 OPCODE [OPERAND, ...] 21754 21755 Instructions must be separated by a newline or semicolon. 21756 21757 There are two ways to write code: either write naked instructions, 21758which the assembler is free to combine into VLIW bundles, or specify the 21759VLIW bundles explicitly. 21760 21761 Bundles are specified using curly braces: 21762 21763 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 21764 21765 A bundle can span multiple lines. If you want to put multiple 21766instructions on a line, whether in a bundle or not, you need to separate 21767them with semicolons as in this example. 21768 21769 A bundle may contain one or more instructions, up to the limit 21770specified by the ISA (currently three). If fewer instructions are 21771specified than the hardware supports in a bundle, the assembler inserts 21772'fnop' instructions automatically. 21773 21774 The assembler will prefer to preserve the ordering of instructions 21775within the bundle, putting the first instruction in a lower-numbered 21776pipeline than the next one, etc. This fact, combined with the optional 21777use of explicit 'fnop' or 'nop' instructions, allows precise control 21778over which pipeline executes each instruction. 21779 21780 If the instructions cannot be bundled in the listed order, the 21781assembler will automatically try to find a valid pipeline assignment. 21782If there is no way to bundle the instructions together, the assembler 21783reports an error. 21784 21785 The assembler does not yet auto-bundle (automatically combine 21786multiple instructions into one bundle), but it reserves the right to do 21787so in the future. If you want to force an instruction to run by itself, 21788put it in a bundle explicitly with curly braces and use 'nop' 21789instructions (not 'fnop') to fill the remaining pipeline slots in that 21790bundle. 21791 21792* Menu: 21793 21794* TILE-Gx Opcodes:: Opcode Naming Conventions. 21795* TILE-Gx Registers:: Register Naming. 21796* TILE-Gx Modifiers:: Symbolic Operand Modifiers. 21797 21798 21799File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax 21800 218019.47.2.1 Opcode Names 21802..................... 21803 21804For a complete list of opcodes and descriptions of their semantics, see 21805'TILE-Gx Instruction Set Architecture', available upon request at 21806www.tilera.com. 21807 21808 21809File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax 21810 218119.47.2.2 Register Names 21812....................... 21813 21814General-purpose registers are represented by predefined symbols of the 21815form 'rN', where N represents a number between '0' and '63'. However, 21816the following registers have canonical names that must be used instead: 21817 21818'r54' 21819 sp 21820 21821'r55' 21822 lr 21823 21824'r56' 21825 sn 21826 21827'r57' 21828 idn0 21829 21830'r58' 21831 idn1 21832 21833'r59' 21834 udn0 21835 21836'r60' 21837 udn1 21838 21839'r61' 21840 udn2 21841 21842'r62' 21843 udn3 21844 21845'r63' 21846 zero 21847 21848 The assembler will emit a warning if a numeric name is used instead 21849of the non-numeric name. The '.no_require_canonical_reg_names' 21850assembler pseudo-op turns off this warning. 21851'.require_canonical_reg_names' turns it back on. 21852 21853 21854File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax 21855 218569.47.2.3 Symbolic Operand Modifiers 21857................................... 21858 21859The assembler supports several modifiers when using symbol addresses in 21860TILE-Gx instruction operands. The general syntax is the following: 21861 21862 modifier(symbol) 21863 21864 The following modifiers are supported: 21865 21866'hw0' 21867 21868 This modifier is used to load bits 0-15 of the symbol's address. 21869 21870'hw1' 21871 21872 This modifier is used to load bits 16-31 of the symbol's address. 21873 21874'hw2' 21875 21876 This modifier is used to load bits 32-47 of the symbol's address. 21877 21878'hw3' 21879 21880 This modifier is used to load bits 48-63 of the symbol's address. 21881 21882'hw0_last' 21883 21884 This modifier yields the same value as 'hw0', but it also checks 21885 that the value does not overflow. 21886 21887'hw1_last' 21888 21889 This modifier yields the same value as 'hw1', but it also checks 21890 that the value does not overflow. 21891 21892'hw2_last' 21893 21894 This modifier yields the same value as 'hw2', but it also checks 21895 that the value does not overflow. 21896 21897 A 48-bit symbolic value is constructed by using the following 21898 idiom: 21899 21900 moveli r0, hw2_last(sym) 21901 shl16insli r0, r0, hw1(sym) 21902 shl16insli r0, r0, hw0(sym) 21903 21904'hw0_got' 21905 21906 This modifier is used to load bits 0-15 of the symbol's offset in 21907 the GOT entry corresponding to the symbol. 21908 21909'hw0_last_got' 21910 21911 This modifier yields the same value as 'hw0_got', but it also 21912 checks that the value does not overflow. 21913 21914'hw1_last_got' 21915 21916 This modifier is used to load bits 16-31 of the symbol's offset in 21917 the GOT entry corresponding to the symbol, and it also checks that 21918 the value does not overflow. 21919 21920'plt' 21921 21922 This modifier is used for function symbols. It causes a _procedure 21923 linkage table_, an array of code stubs, to be created at the time 21924 the shared object is created or linked against, together with a 21925 global offset table entry. The value is a pc-relative offset to 21926 the corresponding stub code in the procedure linkage table. This 21927 arrangement causes the run-time symbol resolver to be called to 21928 look up and set the value of the symbol the first time the function 21929 is called (at latest; depending environment variables). It is only 21930 safe to leave the symbol unresolved this way if all references are 21931 function calls. 21932 21933'hw0_plt' 21934 21935 This modifier is used to load bits 0-15 of the pc-relative address 21936 of a plt entry. 21937 21938'hw1_plt' 21939 21940 This modifier is used to load bits 16-31 of the pc-relative address 21941 of a plt entry. 21942 21943'hw1_last_plt' 21944 21945 This modifier yields the same value as 'hw1_plt', but it also 21946 checks that the value does not overflow. 21947 21948'hw2_last_plt' 21949 21950 This modifier is used to load bits 32-47 of the pc-relative address 21951 of a plt entry, and it also checks that the value does not 21952 overflow. 21953 21954'hw0_tls_gd' 21955 21956 This modifier is used to load bits 0-15 of the offset of the GOT 21957 entry of the symbol's TLS descriptor, to be used for 21958 general-dynamic TLS accesses. 21959 21960'hw0_last_tls_gd' 21961 21962 This modifier yields the same value as 'hw0_tls_gd', but it also 21963 checks that the value does not overflow. 21964 21965'hw1_last_tls_gd' 21966 21967 This modifier is used to load bits 16-31 of the offset of the GOT 21968 entry of the symbol's TLS descriptor, to be used for 21969 general-dynamic TLS accesses. It also checks that the value does 21970 not overflow. 21971 21972'hw0_tls_ie' 21973 21974 This modifier is used to load bits 0-15 of the offset of the GOT 21975 entry containing the offset of the symbol's address from the TCB, 21976 to be used for initial-exec TLS accesses. 21977 21978'hw0_last_tls_ie' 21979 21980 This modifier yields the same value as 'hw0_tls_ie', but it also 21981 checks that the value does not overflow. 21982 21983'hw1_last_tls_ie' 21984 21985 This modifier is used to load bits 16-31 of the offset of the GOT 21986 entry containing the offset of the symbol's address from the TCB, 21987 to be used for initial-exec TLS accesses. It also checks that the 21988 value does not overflow. 21989 21990'hw0_tls_le' 21991 21992 This modifier is used to load bits 0-15 of the offset of the 21993 symbol's address from the TCB, to be used for local-exec TLS 21994 accesses. 21995 21996'hw0_last_tls_le' 21997 21998 This modifier yields the same value as 'hw0_tls_le', but it also 21999 checks that the value does not overflow. 22000 22001'hw1_last_tls_le' 22002 22003 This modifier is used to load bits 16-31 of the offset of the 22004 symbol's address from the TCB, to be used for local-exec TLS 22005 accesses. It also checks that the value does not overflow. 22006 22007'tls_gd_call' 22008 22009 This modifier is used to tag an instruction as the "call" part of a 22010 calling sequence for a TLS GD reference of its operand. 22011 22012'tls_gd_add' 22013 22014 This modifier is used to tag an instruction as the "add" part of a 22015 calling sequence for a TLS GD reference of its operand. 22016 22017'tls_ie_load' 22018 22019 This modifier is used to tag an instruction as the "load" part of a 22020 calling sequence for a TLS IE reference of its operand. 22021 22022 22023File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent 22024 220259.47.3 TILE-Gx Directives 22026------------------------- 22027 22028'.align EXPRESSION [, EXPRESSION]' 22029 This is the generic .ALIGN directive. The first argument is the 22030 requested alignment in bytes. 22031 22032'.allow_suspicious_bundles' 22033 Turns on error checking for combinations of instructions in a 22034 bundle that probably indicate a programming error. This is on by 22035 default. 22036 22037'.no_allow_suspicious_bundles' 22038 Turns off error checking for combinations of instructions in a 22039 bundle that probably indicate a programming error. 22040 22041'.require_canonical_reg_names' 22042 Require that canonical register names be used, and emit a warning 22043 if the numeric names are used. This is on by default. 22044 22045'.no_require_canonical_reg_names' 22046 Permit the use of numeric names for registers that have canonical 22047 names. 22048 22049 22050File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies 22051 220529.48 TILEPro Dependent Features 22053=============================== 22054 22055* Menu: 22056 22057* TILEPro Options:: TILEPro Options 22058* TILEPro Syntax:: TILEPro Syntax 22059* TILEPro Directives:: TILEPro Directives 22060 22061 22062File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent 22063 220649.48.1 Options 22065-------------- 22066 22067'as' has no machine-dependent command-line options for TILEPro. 22068 22069 22070File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent 22071 220729.48.2 Syntax 22073------------- 22074 22075Block comments are delimited by '/*' and '*/'. End of line comments may 22076be introduced by '#'. 22077 22078 Instructions consist of a leading opcode or macro name followed by 22079whitespace and an optional comma-separated list of operands: 22080 22081 OPCODE [OPERAND, ...] 22082 22083 Instructions must be separated by a newline or semicolon. 22084 22085 There are two ways to write code: either write naked instructions, 22086which the assembler is free to combine into VLIW bundles, or specify the 22087VLIW bundles explicitly. 22088 22089 Bundles are specified using curly braces: 22090 22091 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 22092 22093 A bundle can span multiple lines. If you want to put multiple 22094instructions on a line, whether in a bundle or not, you need to separate 22095them with semicolons as in this example. 22096 22097 A bundle may contain one or more instructions, up to the limit 22098specified by the ISA (currently three). If fewer instructions are 22099specified than the hardware supports in a bundle, the assembler inserts 22100'fnop' instructions automatically. 22101 22102 The assembler will prefer to preserve the ordering of instructions 22103within the bundle, putting the first instruction in a lower-numbered 22104pipeline than the next one, etc. This fact, combined with the optional 22105use of explicit 'fnop' or 'nop' instructions, allows precise control 22106over which pipeline executes each instruction. 22107 22108 If the instructions cannot be bundled in the listed order, the 22109assembler will automatically try to find a valid pipeline assignment. 22110If there is no way to bundle the instructions together, the assembler 22111reports an error. 22112 22113 The assembler does not yet auto-bundle (automatically combine 22114multiple instructions into one bundle), but it reserves the right to do 22115so in the future. If you want to force an instruction to run by itself, 22116put it in a bundle explicitly with curly braces and use 'nop' 22117instructions (not 'fnop') to fill the remaining pipeline slots in that 22118bundle. 22119 22120* Menu: 22121 22122* TILEPro Opcodes:: Opcode Naming Conventions. 22123* TILEPro Registers:: Register Naming. 22124* TILEPro Modifiers:: Symbolic Operand Modifiers. 22125 22126 22127File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax 22128 221299.48.2.1 Opcode Names 22130..................... 22131 22132For a complete list of opcodes and descriptions of their semantics, see 22133'TILE Processor User Architecture Manual', available upon request at 22134www.tilera.com. 22135 22136 22137File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax 22138 221399.48.2.2 Register Names 22140....................... 22141 22142General-purpose registers are represented by predefined symbols of the 22143form 'rN', where N represents a number between '0' and '63'. However, 22144the following registers have canonical names that must be used instead: 22145 22146'r54' 22147 sp 22148 22149'r55' 22150 lr 22151 22152'r56' 22153 sn 22154 22155'r57' 22156 idn0 22157 22158'r58' 22159 idn1 22160 22161'r59' 22162 udn0 22163 22164'r60' 22165 udn1 22166 22167'r61' 22168 udn2 22169 22170'r62' 22171 udn3 22172 22173'r63' 22174 zero 22175 22176 The assembler will emit a warning if a numeric name is used instead 22177of the canonical name. The '.no_require_canonical_reg_names' assembler 22178pseudo-op turns off this warning. '.require_canonical_reg_names' turns 22179it back on. 22180 22181 22182File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax 22183 221849.48.2.3 Symbolic Operand Modifiers 22185................................... 22186 22187The assembler supports several modifiers when using symbol addresses in 22188TILEPro instruction operands. The general syntax is the following: 22189 22190 modifier(symbol) 22191 22192 The following modifiers are supported: 22193 22194'lo16' 22195 22196 This modifier is used to load the low 16 bits of the symbol's 22197 address, sign-extended to a 32-bit value (sign-extension allows it 22198 to be range-checked against signed 16 bit immediate operands 22199 without complaint). 22200 22201'hi16' 22202 22203 This modifier is used to load the high 16 bits of the symbol's 22204 address, also sign-extended to a 32-bit value. 22205 22206'ha16' 22207 22208 'ha16(N)' is identical to 'hi16(N)', except if 'lo16(N)' is 22209 negative it adds one to the 'hi16(N)' value. This way 'lo16' and 22210 'ha16' can be added to create any 32-bit value using 'auli'. For 22211 example, here is how you move an arbitrary 32-bit address into r3: 22212 22213 moveli r3, lo16(sym) 22214 auli r3, r3, ha16(sym) 22215 22216'got' 22217 22218 This modifier is used to load the offset of the GOT entry 22219 corresponding to the symbol. 22220 22221'got_lo16' 22222 22223 This modifier is used to load the sign-extended low 16 bits of the 22224 offset of the GOT entry corresponding to the symbol. 22225 22226'got_hi16' 22227 22228 This modifier is used to load the sign-extended high 16 bits of the 22229 offset of the GOT entry corresponding to the symbol. 22230 22231'got_ha16' 22232 22233 This modifier is like 'got_hi16', but it adds one if 'got_lo16' of 22234 the input value is negative. 22235 22236'plt' 22237 22238 This modifier is used for function symbols. It causes a _procedure 22239 linkage table_, an array of code stubs, to be created at the time 22240 the shared object is created or linked against, together with a 22241 global offset table entry. The value is a pc-relative offset to 22242 the corresponding stub code in the procedure linkage table. This 22243 arrangement causes the run-time symbol resolver to be called to 22244 look up and set the value of the symbol the first time the function 22245 is called (at latest; depending environment variables). It is only 22246 safe to leave the symbol unresolved this way if all references are 22247 function calls. 22248 22249'tls_gd' 22250 22251 This modifier is used to load the offset of the GOT entry of the 22252 symbol's TLS descriptor, to be used for general-dynamic TLS 22253 accesses. 22254 22255'tls_gd_lo16' 22256 22257 This modifier is used to load the sign-extended low 16 bits of the 22258 offset of the GOT entry of the symbol's TLS descriptor, to be used 22259 for general dynamic TLS accesses. 22260 22261'tls_gd_hi16' 22262 22263 This modifier is used to load the sign-extended high 16 bits of the 22264 offset of the GOT entry of the symbol's TLS descriptor, to be used 22265 for general dynamic TLS accesses. 22266 22267'tls_gd_ha16' 22268 22269 This modifier is like 'tls_gd_hi16', but it adds one to the value 22270 if 'tls_gd_lo16' of the input value is negative. 22271 22272'tls_ie' 22273 22274 This modifier is used to load the offset of the GOT entry 22275 containing the offset of the symbol's address from the TCB, to be 22276 used for initial-exec TLS accesses. 22277 22278'tls_ie_lo16' 22279 22280 This modifier is used to load the low 16 bits of the offset of the 22281 GOT entry containing the offset of the symbol's address from the 22282 TCB, to be used for initial-exec TLS accesses. 22283 22284'tls_ie_hi16' 22285 22286 This modifier is used to load the high 16 bits of the offset of the 22287 GOT entry containing the offset of the symbol's address from the 22288 TCB, to be used for initial-exec TLS accesses. 22289 22290'tls_ie_ha16' 22291 22292 This modifier is like 'tls_ie_hi16', but it adds one to the value 22293 if 'tls_ie_lo16' of the input value is negative. 22294 22295'tls_le' 22296 22297 This modifier is used to load the offset of the symbol's address 22298 from the TCB, to be used for local-exec TLS accesses. 22299 22300'tls_le_lo16' 22301 22302 This modifier is used to load the low 16 bits of the offset of the 22303 symbol's address from the TCB, to be used for local-exec TLS 22304 accesses. 22305 22306'tls_le_hi16' 22307 22308 This modifier is used to load the high 16 bits of the offset of the 22309 symbol's address from the TCB, to be used for local-exec TLS 22310 accesses. 22311 22312'tls_le_ha16' 22313 22314 This modifier is like 'tls_le_hi16', but it adds one to the value 22315 if 'tls_le_lo16' of the input value is negative. 22316 22317'tls_gd_call' 22318 22319 This modifier is used to tag an instruction as the "call" part of a 22320 calling sequence for a TLS GD reference of its operand. 22321 22322'tls_gd_add' 22323 22324 This modifier is used to tag an instruction as the "add" part of a 22325 calling sequence for a TLS GD reference of its operand. 22326 22327'tls_ie_load' 22328 22329 This modifier is used to tag an instruction as the "load" part of a 22330 calling sequence for a TLS IE reference of its operand. 22331 22332 22333File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent 22334 223359.48.3 TILEPro Directives 22336------------------------- 22337 22338'.align EXPRESSION [, EXPRESSION]' 22339 This is the generic .ALIGN directive. The first argument is the 22340 requested alignment in bytes. 22341 22342'.allow_suspicious_bundles' 22343 Turns on error checking for combinations of instructions in a 22344 bundle that probably indicate a programming error. This is on by 22345 default. 22346 22347'.no_allow_suspicious_bundles' 22348 Turns off error checking for combinations of instructions in a 22349 bundle that probably indicate a programming error. 22350 22351'.require_canonical_reg_names' 22352 Require that canonical register names be used, and emit a warning 22353 if the numeric names are used. This is on by default. 22354 22355'.no_require_canonical_reg_names' 22356 Permit the use of numeric names for registers that have canonical 22357 names. 22358 22359 22360File: as.info, Node: V850-Dependent, Next: Vax-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies 22361 223629.49 v850 Dependent Features 22363============================ 22364 22365* Menu: 22366 22367* V850 Options:: Options 22368* V850 Syntax:: Syntax 22369* V850 Floating Point:: Floating Point 22370* V850 Directives:: V850 Machine Directives 22371* V850 Opcodes:: Opcodes 22372 22373 22374File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 22375 223769.49.1 Options 22377-------------- 22378 22379'as' supports the following additional command-line options for the V850 22380processor family: 22381 22382'-wsigned_overflow' 22383 Causes warnings to be produced when signed immediate values 22384 overflow the space available for then within their opcodes. By 22385 default this option is disabled as it is possible to receive 22386 spurious warnings due to using exact bit patterns as immediate 22387 constants. 22388 22389'-wunsigned_overflow' 22390 Causes warnings to be produced when unsigned immediate values 22391 overflow the space available for then within their opcodes. By 22392 default this option is disabled as it is possible to receive 22393 spurious warnings due to using exact bit patterns as immediate 22394 constants. 22395 22396'-mv850' 22397 Specifies that the assembled code should be marked as being 22398 targeted at the V850 processor. This allows the linker to detect 22399 attempts to link such code with code assembled for other 22400 processors. 22401 22402'-mv850e' 22403 Specifies that the assembled code should be marked as being 22404 targeted at the V850E processor. This allows the linker to detect 22405 attempts to link such code with code assembled for other 22406 processors. 22407 22408'-mv850e1' 22409 Specifies that the assembled code should be marked as being 22410 targeted at the V850E1 processor. This allows the linker to detect 22411 attempts to link such code with code assembled for other 22412 processors. 22413 22414'-mv850any' 22415 Specifies that the assembled code should be marked as being 22416 targeted at the V850 processor but support instructions that are 22417 specific to the extended variants of the process. This allows the 22418 production of binaries that contain target specific code, but which 22419 are also intended to be used in a generic fashion. For example 22420 libgcc.a contains generic routines used by the code produced by GCC 22421 for all versions of the v850 architecture, together with support 22422 routines only used by the V850E architecture. 22423 22424'-mv850e2' 22425 Specifies that the assembled code should be marked as being 22426 targeted at the V850E2 processor. This allows the linker to detect 22427 attempts to link such code with code assembled for other 22428 processors. 22429 22430'-mv850e2v3' 22431 Specifies that the assembled code should be marked as being 22432 targeted at the V850E2V3 processor. This allows the linker to 22433 detect attempts to link such code with code assembled for other 22434 processors. 22435 22436'-mv850e2v4' 22437 This is an alias for '-mv850e3v5'. 22438 22439'-mv850e3v5' 22440 Specifies that the assembled code should be marked as being 22441 targeted at the V850E3V5 processor. This allows the linker to 22442 detect attempts to link such code with code assembled for other 22443 processors. 22444 22445'-mrelax' 22446 Enables relaxation. This allows the .longcall and .longjump pseudo 22447 ops to be used in the assembler source code. These ops label 22448 sections of code which are either a long function call or a long 22449 branch. The assembler will then flag these sections of code and 22450 the linker will attempt to relax them. 22451 22452'-mgcc-abi' 22453 Marks the generated object file as supporting the old GCC ABI. 22454 22455'-mrh850-abi' 22456 Marks the generated object file as supporting the RH850 ABI. This 22457 is the default. 22458 22459'-m8byte-align' 22460 Marks the generated object file as supporting a maximum 64-bits of 22461 alignment for variables defined in the source code. 22462 22463'-m4byte-align' 22464 Marks the generated object file as supporting a maximum 32-bits of 22465 alignment for variables defined in the source code. This is the 22466 default. 22467 22468'-msoft-float' 22469 Marks the generated object file as not using any floating point 22470 instructions - and hence can be linked with other V850 binaries 22471 that do or do not use floating point. This is the default for 22472 binaries for architectures earlier than the 'e2v3'. 22473 22474'-mhard-float' 22475 Marks the generated object file as one that uses floating point 22476 instructions - and hence can only be linked with other V850 22477 binaries that use the same kind of floating point instructions, or 22478 with binaries that do not use floating point at all. This is the 22479 default for binaries the 'e2v3' and later architectures. 22480 22481 22482File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 22483 224849.49.2 Syntax 22485------------- 22486 22487* Menu: 22488 22489* V850-Chars:: Special Characters 22490* V850-Regs:: Register Names 22491 22492 22493File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 22494 224959.49.2.1 Special Characters 22496........................... 22497 22498'#' is the line comment character. If a '#' appears as the first 22499character of a line, the whole line is treated as a comment, but in this 22500case the line can also be a logical line number directive (*note 22501Comments::) or a preprocessor control command (*note Preprocessing::). 22502 22503 Two dashes ('--') can also be used to start a line comment. 22504 22505 The ';' character can be used to separate statements on the same 22506line. 22507 22508 22509File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 22510 225119.49.2.2 Register Names 22512....................... 22513 22514'as' supports the following names for registers: 22515'general register 0' 22516 r0, zero 22517'general register 1' 22518 r1 22519'general register 2' 22520 r2, hp 22521'general register 3' 22522 r3, sp 22523'general register 4' 22524 r4, gp 22525'general register 5' 22526 r5, tp 22527'general register 6' 22528 r6 22529'general register 7' 22530 r7 22531'general register 8' 22532 r8 22533'general register 9' 22534 r9 22535'general register 10' 22536 r10 22537'general register 11' 22538 r11 22539'general register 12' 22540 r12 22541'general register 13' 22542 r13 22543'general register 14' 22544 r14 22545'general register 15' 22546 r15 22547'general register 16' 22548 r16 22549'general register 17' 22550 r17 22551'general register 18' 22552 r18 22553'general register 19' 22554 r19 22555'general register 20' 22556 r20 22557'general register 21' 22558 r21 22559'general register 22' 22560 r22 22561'general register 23' 22562 r23 22563'general register 24' 22564 r24 22565'general register 25' 22566 r25 22567'general register 26' 22568 r26 22569'general register 27' 22570 r27 22571'general register 28' 22572 r28 22573'general register 29' 22574 r29 22575'general register 30' 22576 r30, ep 22577'general register 31' 22578 r31, lp 22579'system register 0' 22580 eipc 22581'system register 1' 22582 eipsw 22583'system register 2' 22584 fepc 22585'system register 3' 22586 fepsw 22587'system register 4' 22588 ecr 22589'system register 5' 22590 psw 22591'system register 16' 22592 ctpc 22593'system register 17' 22594 ctpsw 22595'system register 18' 22596 dbpc 22597'system register 19' 22598 dbpsw 22599'system register 20' 22600 ctbp 22601 22602 22603File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 22604 226059.49.3 Floating Point 22606--------------------- 22607 22608The V850 family uses IEEE floating-point numbers. 22609 22610 22611File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 22612 226139.49.4 V850 Machine Directives 22614------------------------------ 22615 22616'.offset <EXPRESSION>' 22617 Moves the offset into the current section to the specified amount. 22618 22619'.section "name", <type>' 22620 This is an extension to the standard .section directive. It sets 22621 the current section to be <type> and creates an alias for this 22622 section called "name". 22623 22624'.v850' 22625 Specifies that the assembled code should be marked as being 22626 targeted at the V850 processor. This allows the linker to detect 22627 attempts to link such code with code assembled for other 22628 processors. 22629 22630'.v850e' 22631 Specifies that the assembled code should be marked as being 22632 targeted at the V850E processor. This allows the linker to detect 22633 attempts to link such code with code assembled for other 22634 processors. 22635 22636'.v850e1' 22637 Specifies that the assembled code should be marked as being 22638 targeted at the V850E1 processor. This allows the linker to detect 22639 attempts to link such code with code assembled for other 22640 processors. 22641 22642'.v850e2' 22643 Specifies that the assembled code should be marked as being 22644 targeted at the V850E2 processor. This allows the linker to detect 22645 attempts to link such code with code assembled for other 22646 processors. 22647 22648'.v850e2v3' 22649 Specifies that the assembled code should be marked as being 22650 targeted at the V850E2V3 processor. This allows the linker to 22651 detect attempts to link such code with code assembled for other 22652 processors. 22653 22654'.v850e2v4' 22655 Specifies that the assembled code should be marked as being 22656 targeted at the V850E3V5 processor. This allows the linker to 22657 detect attempts to link such code with code assembled for other 22658 processors. 22659 22660'.v850e3v5' 22661 Specifies that the assembled code should be marked as being 22662 targeted at the V850E3V5 processor. This allows the linker to 22663 detect attempts to link such code with code assembled for other 22664 processors. 22665 22666 22667File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 22668 226699.49.5 Opcodes 22670-------------- 22671 22672'as' implements all the standard V850 opcodes. 22673 22674 'as' also implements the following pseudo ops: 22675 22676'hi0()' 22677 Computes the higher 16 bits of the given expression and stores it 22678 into the immediate operand field of the given instruction. For 22679 example: 22680 22681 'mulhi hi0(here - there), r5, r6' 22682 22683 computes the difference between the address of labels 'here' and 22684 'there', takes the upper 16 bits of this difference, shifts it down 22685 16 bits and then multiplies it by the lower 16 bits in register 5, 22686 putting the result into register 6. 22687 22688'lo()' 22689 Computes the lower 16 bits of the given expression and stores it 22690 into the immediate operand field of the given instruction. For 22691 example: 22692 22693 'addi lo(here - there), r5, r6' 22694 22695 computes the difference between the address of labels 'here' and 22696 'there', takes the lower 16 bits of this difference and adds it to 22697 register 5, putting the result into register 6. 22698 22699'hi()' 22700 Computes the higher 16 bits of the given expression and then adds 22701 the value of the most significant bit of the lower 16 bits of the 22702 expression and stores the result into the immediate operand field 22703 of the given instruction. For example the following code can be 22704 used to compute the address of the label 'here' and store it into 22705 register 6: 22706 22707 'movhi hi(here), r0, r6' 'movea lo(here), r6, r6' 22708 22709 The reason for this special behaviour is that movea performs a sign 22710 extension on its immediate operand. So for example if the address 22711 of 'here' was 0xFFFFFFFF then without the special behaviour of the 22712 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 22713 then the movea instruction would takes its immediate operand, 22714 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into 22715 r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With 22716 the hi() pseudo op adding in the top bit of the lo() pseudo op, the 22717 movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), 22718 so that the movea instruction stores 0xFFFFFFFF into r6 - the right 22719 value. 22720 22721'hilo()' 22722 Computes the 32 bit value of the given expression and stores it 22723 into the immediate operand field of the given instruction (which 22724 must be a mov instruction). For example: 22725 22726 'mov hilo(here), r6' 22727 22728 computes the absolute address of label 'here' and puts the result 22729 into register 6. 22730 22731'sdaoff()' 22732 Computes the offset of the named variable from the start of the 22733 Small Data Area (whose address is held in register 4, the GP 22734 register) and stores the result as a 16 bit signed value in the 22735 immediate operand field of the given instruction. For example: 22736 22737 'ld.w sdaoff(_a_variable)[gp],r6' 22738 22739 loads the contents of the location pointed to by the label 22740 '_a_variable' into register 6, provided that the label is located 22741 somewhere within +/- 32K of the address held in the GP register. 22742 [Note the linker assumes that the GP register contains a fixed 22743 address set to the address of the label called '__gp'. This can 22744 either be set up automatically by the linker, or specifically set 22745 by using the '--defsym __gp=<value>' command-line option]. 22746 22747'tdaoff()' 22748 Computes the offset of the named variable from the start of the 22749 Tiny Data Area (whose address is held in register 30, the EP 22750 register) and stores the result as a 4,5, 7 or 8 bit unsigned value 22751 in the immediate operand field of the given instruction. For 22752 example: 22753 22754 'sld.w tdaoff(_a_variable)[ep],r6' 22755 22756 loads the contents of the location pointed to by the label 22757 '_a_variable' into register 6, provided that the label is located 22758 somewhere within +256 bytes of the address held in the EP register. 22759 [Note the linker assumes that the EP register contains a fixed 22760 address set to the address of the label called '__ep'. This can 22761 either be set up automatically by the linker, or specifically set 22762 by using the '--defsym __ep=<value>' command-line option]. 22763 22764'zdaoff()' 22765 Computes the offset of the named variable from address 0 and stores 22766 the result as a 16 bit signed value in the immediate operand field 22767 of the given instruction. For example: 22768 22769 'movea zdaoff(_a_variable),zero,r6' 22770 22771 puts the address of the label '_a_variable' into register 6, 22772 assuming that the label is somewhere within the first 32K of 22773 memory. (Strictly speaking it also possible to access the last 32K 22774 of memory as well, as the offsets are signed). 22775 22776'ctoff()' 22777 Computes the offset of the named variable from the start of the 22778 Call Table Area (whose address is held in system register 20, the 22779 CTBP register) and stores the result a 6 or 16 bit unsigned value 22780 in the immediate field of then given instruction or piece of data. 22781 For example: 22782 22783 'callt ctoff(table_func1)' 22784 22785 will put the call the function whose address is held in the call 22786 table at the location labeled 'table_func1'. 22787 22788'.longcall name' 22789 Indicates that the following sequence of instructions is a long 22790 call to function 'name'. The linker will attempt to shorten this 22791 call sequence if 'name' is within a 22bit offset of the call. Only 22792 valid if the '-mrelax' command-line switch has been enabled. 22793 22794'.longjump name' 22795 Indicates that the following sequence of instructions is a long 22796 jump to label 'name'. The linker will attempt to shorten this code 22797 sequence if 'name' is within a 22bit offset of the jump. Only 22798 valid if the '-mrelax' command-line switch has been enabled. 22799 22800 For information on the V850 instruction set, see 'V850 Family 2280132-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 22802Ltd. 22803 22804 22805File: as.info, Node: Vax-Dependent, Next: Visium-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 22806 228079.50 VAX Dependent Features 22808=========================== 22809 22810* Menu: 22811 22812* VAX-Opts:: VAX Command-Line Options 22813* VAX-float:: VAX Floating Point 22814* VAX-directives:: Vax Machine Directives 22815* VAX-opcodes:: VAX Opcodes 22816* VAX-branch:: VAX Branch Improvement 22817* VAX-operands:: VAX Operands 22818* VAX-no:: Not Supported on VAX 22819* VAX-Syntax:: VAX Syntax 22820 22821 22822File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 22823 228249.50.1 VAX Command-Line Options 22825------------------------------- 22826 22827The Vax version of 'as' accepts any of the following options, gives a 22828warning message that the option was ignored and proceeds. These options 22829are for compatibility with scripts designed for other people's 22830assemblers. 22831 22832'-D (Debug)' 22833'-S (Symbol Table)' 22834'-T (Token Trace)' 22835 These are obsolete options used to debug old assemblers. 22836 22837'-d (Displacement size for JUMPs)' 22838 This option expects a number following the '-d'. Like options that 22839 expect filenames, the number may immediately follow the '-d' (old 22840 standard) or constitute the whole of the command-line argument that 22841 follows '-d' (GNU standard). 22842 22843'-V (Virtualize Interpass Temporary File)' 22844 Some other assemblers use a temporary file. This option commanded 22845 them to keep the information in active memory rather than in a disk 22846 file. 'as' always does this, so this option is redundant. 22847 22848'-J (JUMPify Longer Branches)' 22849 Many 32-bit computers permit a variety of branch instructions to do 22850 the same job. Some of these instructions are short (and fast) but 22851 have a limited range; others are long (and slow) but can branch 22852 anywhere in virtual memory. Often there are 3 flavors of branch: 22853 short, medium and long. Some other assemblers would emit short and 22854 medium branches, unless told by this option to emit short and long 22855 branches. 22856 22857'-t (Temporary File Directory)' 22858 Some other assemblers may use a temporary file, and this option 22859 takes a filename being the directory to site the temporary file. 22860 Since 'as' does not use a temporary disk file, this option makes no 22861 difference. '-t' needs exactly one filename. 22862 22863 The Vax version of the assembler accepts additional options when 22864compiled for VMS: 22865 22866'-h N' 22867 External symbol or section (used for global variables) names are 22868 not case sensitive on VAX/VMS and always mapped to upper case. 22869 This is contrary to the C language definition which explicitly 22870 distinguishes upper and lower case. To implement a standard 22871 conforming C compiler, names must be changed (mapped) to preserve 22872 the case information. The default mapping is to convert all lower 22873 case characters to uppercase and adding an underscore followed by a 22874 6 digit hex value, representing a 24 digit binary value. The one 22875 digits in the binary value represent which characters are uppercase 22876 in the original symbol name. 22877 22878 The '-h N' option determines how we map names. This takes several 22879 values. No '-h' switch at all allows case hacking as described 22880 above. A value of zero ('-h0') implies names should be upper case, 22881 and inhibits the case hack. A value of 2 ('-h2') implies names 22882 should be all lower case, with no case hack. A value of 3 ('-h3') 22883 implies that case should be preserved. The value 1 is unused. The 22884 '-H' option directs 'as' to display every mapped symbol during 22885 assembly. 22886 22887 Symbols whose names include a dollar sign '$' are exceptions to the 22888 general name mapping. These symbols are normally only used to 22889 reference VMS library names. Such symbols are always mapped to 22890 upper case. 22891 22892'-+' 22893 The '-+' option causes 'as' to truncate any symbol name larger than 22894 31 characters. The '-+' option also prevents some code following 22895 the '_main' symbol normally added to make the object file 22896 compatible with Vax-11 "C". 22897 22898'-1' 22899 This option is ignored for backward compatibility with 'as' version 22900 1.x. 22901 22902'-H' 22903 The '-H' option causes 'as' to print every symbol which was changed 22904 by case mapping. 22905 22906 22907File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 22908 229099.50.2 VAX Floating Point 22910------------------------- 22911 22912Conversion of flonums to floating point is correct, and compatible with 22913previous assemblers. Rounding is towards zero if the remainder is 22914exactly half the least significant bit. 22915 22916 'D', 'F', 'G' and 'H' floating point formats are understood. 22917 22918 Immediate floating literals (_e.g._ 'S`$6.9') are rendered 22919correctly. Again, rounding is towards zero in the boundary case. 22920 22921 The '.float' directive produces 'f' format numbers. The '.double' 22922directive produces 'd' format numbers. 22923 22924 22925File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 22926 229279.50.3 Vax Machine Directives 22928----------------------------- 22929 22930The Vax version of the assembler supports four directives for generating 22931Vax floating point constants. They are described in the table below. 22932 22933'.dfloat' 22934 This expects zero or more flonums, separated by commas, and 22935 assembles Vax 'd' format 64-bit floating point constants. 22936 22937'.ffloat' 22938 This expects zero or more flonums, separated by commas, and 22939 assembles Vax 'f' format 32-bit floating point constants. 22940 22941'.gfloat' 22942 This expects zero or more flonums, separated by commas, and 22943 assembles Vax 'g' format 64-bit floating point constants. 22944 22945'.hfloat' 22946 This expects zero or more flonums, separated by commas, and 22947 assembles Vax 'h' format 128-bit floating point constants. 22948 22949 22950File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 22951 229529.50.4 VAX Opcodes 22953------------------ 22954 22955All DEC mnemonics are supported. Beware that 'case...' instructions 22956have exactly 3 operands. The dispatch table that follows the 'case...' 22957instruction should be made with '.word' statements. This is compatible 22958with all unix assemblers we know of. 22959 22960 22961File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 22962 229639.50.5 VAX Branch Improvement 22964----------------------------- 22965 22966Certain pseudo opcodes are permitted. They are for branch instructions. 22967They expand to the shortest branch instruction that reaches the target. 22968Generally these mnemonics are made by substituting 'j' for 'b' at the 22969start of a DEC mnemonic. This feature is included both for 22970compatibility and to help compilers. If you do not need this feature, 22971avoid these opcodes. Here are the mnemonics, and the code they can 22972expand into. 22973 22974'jbsb' 22975 'Jsb' is already an instruction mnemonic, so we chose 'jbsb'. 22976 (byte displacement) 22977 'bsbb ...' 22978 (word displacement) 22979 'bsbw ...' 22980 (long displacement) 22981 'jsb ...' 22982'jbr' 22983'jr' 22984 Unconditional branch. 22985 (byte displacement) 22986 'brb ...' 22987 (word displacement) 22988 'brw ...' 22989 (long displacement) 22990 'jmp ...' 22991'jCOND' 22992 COND may be any one of the conditional branches 'neq', 'nequ', 22993 'eql', 'eqlu', 'gtr', 'geq', 'lss', 'gtru', 'lequ', 'vc', 'vs', 22994 'gequ', 'cc', 'lssu', 'cs'. COND may also be one of the bit tests 22995 'bs', 'bc', 'bss', 'bcs', 'bsc', 'bcc', 'bssi', 'bcci', 'lbs', 22996 'lbc'. NOTCOND is the opposite condition to COND. 22997 (byte displacement) 22998 'bCOND ...' 22999 (word displacement) 23000 'bNOTCOND foo ; brw ... ; foo:' 23001 (long displacement) 23002 'bNOTCOND foo ; jmp ... ; foo:' 23003'jacbX' 23004 X may be one of 'b d f g h l w'. 23005 (word displacement) 23006 'OPCODE ...' 23007 (long displacement) 23008 OPCODE ..., foo ; 23009 brb bar ; 23010 foo: jmp ... ; 23011 bar: 23012'jaobYYY' 23013 YYY may be one of 'lss leq'. 23014'jsobZZZ' 23015 ZZZ may be one of 'geq gtr'. 23016 (byte displacement) 23017 'OPCODE ...' 23018 (word displacement) 23019 OPCODE ..., foo ; 23020 brb bar ; 23021 foo: brw DESTINATION ; 23022 bar: 23023 (long displacement) 23024 OPCODE ..., foo ; 23025 brb bar ; 23026 foo: jmp DESTINATION ; 23027 bar: 23028'aobleq' 23029'aoblss' 23030'sobgeq' 23031'sobgtr' 23032 (byte displacement) 23033 'OPCODE ...' 23034 (word displacement) 23035 OPCODE ..., foo ; 23036 brb bar ; 23037 foo: brw DESTINATION ; 23038 bar: 23039 (long displacement) 23040 OPCODE ..., foo ; 23041 brb bar ; 23042 foo: jmp DESTINATION ; 23043 bar: 23044 23045 23046File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 23047 230489.50.6 VAX Operands 23049------------------- 23050 23051The immediate character is '$' for Unix compatibility, not '#' as DEC 23052writes it. 23053 23054 The indirect character is '*' for Unix compatibility, not '@' as DEC 23055writes it. 23056 23057 The displacement sizing character is '`' (an accent grave) for Unix 23058compatibility, not '^' as DEC writes it. The letter preceding '`' may 23059have either case. 'G' is not understood, but all other letters ('b i l 23060s w') are understood. 23061 23062 Register names understood are 'r0 r1 r2 ... r15 ap fp sp pc'. Upper 23063and lower case letters are equivalent. 23064 23065 For instance 23066 tstb *w`$4(r5) 23067 23068 Any expression is permitted in an operand. Operands are comma 23069separated. 23070 23071 23072File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent 23073 230749.50.7 Not Supported on VAX 23075--------------------------- 23076 23077Vax bit fields can not be assembled with 'as'. Someone can add the 23078required code if they really need it. 23079 23080 23081File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent 23082 230839.50.8 VAX Syntax 23084----------------- 23085 23086* Menu: 23087 23088* VAX-Chars:: Special Characters 23089 23090 23091File: as.info, Node: VAX-Chars, Up: VAX-Syntax 23092 230939.50.8.1 Special Characters 23094........................... 23095 23096The presence of a '#' appearing anywhere on a line indicates the start 23097of a comment that extends to the end of that line. 23098 23099 If a '#' appears as the first character of a line then the whole line 23100is treated as a comment, but in this case the line can also be a logical 23101line number directive (*note Comments::) or a preprocessor control 23102command (*note Preprocessing::). 23103 23104 The ';' character can be used to separate statements on the same 23105line. 23106 23107 23108File: as.info, Node: Visium-Dependent, Next: WebAssembly-Dependent, Prev: Vax-Dependent, Up: Machine Dependencies 23109 231109.51 Visium Dependent Features 23111============================== 23112 23113* Menu: 23114 23115* Visium Options:: Options 23116* Visium Syntax:: Syntax 23117* Visium Opcodes:: Opcodes 23118 23119 23120File: as.info, Node: Visium Options, Next: Visium Syntax, Up: Visium-Dependent 23121 231229.51.1 Options 23123-------------- 23124 23125The Visium assembler implements one machine-specific option: 23126 23127'-mtune=ARCH' 23128 This option specifies the target architecture. If an attempt is 23129 made to assemble an instruction that will not execute on the target 23130 architecture, the assembler will issue an error message. 23131 23132 The following names are recognized: 'mcm24' 'mcm' 'gr5' 'gr6' 23133 23134 23135File: as.info, Node: Visium Syntax, Next: Visium Opcodes, Prev: Visium Options, Up: Visium-Dependent 23136 231379.51.2 Syntax 23138------------- 23139 23140* Menu: 23141 23142* Visium Characters:: Special Characters 23143* Visium Registers:: Register Names 23144 23145 23146File: as.info, Node: Visium Characters, Next: Visium Registers, Up: Visium Syntax 23147 231489.51.2.1 Special Characters 23149........................... 23150 23151Line comments are introduced either by the '!' character or by the ';' 23152character appearing anywhere on a line. 23153 23154 A hash character ('#') as the first character on a line also marks 23155the start of a line comment, but in this case it could also be a logical 23156line number directive (*note Comments::) or a preprocessor control 23157command (*note Preprocessing::). 23158 23159 The Visium assembler does not currently support a line separator 23160character. 23161 23162 23163File: as.info, Node: Visium Registers, Prev: Visium Characters, Up: Visium Syntax 23164 231659.51.2.2 Register Names 23166....................... 23167 23168Registers can be specified either by using their canonical mnemonic 23169names or by using their alias if they have one, for example 'sp'. 23170 23171 23172File: as.info, Node: Visium Opcodes, Prev: Visium Syntax, Up: Visium-Dependent 23173 231749.51.3 Opcodes 23175-------------- 23176 23177All the standard opcodes of the architecture are implemented, along with 23178the following three pseudo-instructions: 'cmp', 'cmpc', 'move'. 23179 23180 In addition, the following two illegal opcodes are implemented and 23181used by the simulation: 23182 23183 stop 5-bit immediate, SourceA 23184 trace 5-bit immediate, SourceA 23185 23186 23187File: as.info, Node: WebAssembly-Dependent, Next: XGATE-Dependent, Prev: Visium-Dependent, Up: Machine Dependencies 23188 231899.52 WebAssembly Dependent Features 23190=================================== 23191 23192* Menu: 23193 23194* WebAssembly-Notes:: Notes 23195* WebAssembly-Syntax:: Syntax 23196* WebAssembly-Floating-Point:: Floating Point 23197* WebAssembly-Opcodes:: Opcodes 23198* WebAssembly-module-layout:: Module Layout 23199 23200 23201File: as.info, Node: WebAssembly-Notes, Next: WebAssembly-Syntax, Up: WebAssembly-Dependent 23202 232039.52.1 Notes 23204------------ 23205 23206While WebAssembly provides its own module format for executables, this 23207documentation describes how to use 'as' to produce intermediate ELF 23208object format files. 23209 23210 23211File: as.info, Node: WebAssembly-Syntax, Next: WebAssembly-Floating-Point, Prev: WebAssembly-Notes, Up: WebAssembly-Dependent 23212 232139.52.2 Syntax 23214------------- 23215 23216The assembler syntax directly encodes sequences of opcodes as defined in 23217the WebAssembly binary encoding specification at 23218https://github.com/webassembly/spec/BinaryEncoding.md. Structured 23219sexp-style expressions are not supported as input. 23220 23221* Menu: 23222 23223* WebAssembly-Chars:: Special Characters 23224* WebAssembly-Relocs:: Relocations 23225* WebAssembly-Signatures:: Signatures 23226 23227 23228File: as.info, Node: WebAssembly-Chars, Next: WebAssembly-Relocs, Up: WebAssembly-Syntax 23229 232309.52.2.1 Special Characters 23231........................... 23232 23233'#' and ';' are the line comment characters. Note that if '#' is the 23234first character on a line then it can also be a logical line number 23235directive (*note Comments::) or a preprocessor control command (*note 23236Preprocessing::). 23237 23238 23239File: as.info, Node: WebAssembly-Relocs, Next: WebAssembly-Signatures, Prev: WebAssembly-Chars, Up: WebAssembly-Syntax 23240 232419.52.2.2 Relocations 23242.................... 23243 23244Special relocations are available by using the '@PLT', '@GOT', or '@GOT' 23245suffixes after a constant expression, which correspond to the 23246R_ASMJS_LEB128_PLT, R_ASMJS_LEB128_GOT, and R_ASMJS_LEB128_GOT_CODE 23247relocations, respectively. 23248 23249 The '@PLT' suffix is followed by a symbol name in braces; the symbol 23250value is used to determine the function signature for which a PLT stub 23251is generated. Currently, the symbol _name_ is parsed from its last 'F' 23252character to determine the argument count of the function, which is also 23253necessary for generating a PLT stub. 23254 23255 23256File: as.info, Node: WebAssembly-Signatures, Prev: WebAssembly-Relocs, Up: WebAssembly-Syntax 23257 232589.52.2.3 Signatures 23259................... 23260 23261Function signatures are specified with the 'signature' pseudo-opcode, 23262followed by a simple function signature imitating a C++-mangled function 23263type: 'F' followed by an optional 'v', then a sequence of 'i', 'l', 'f', 23264and 'd' characters to mark i32, i64, f32, and f64 parameters, 23265respectively; followed by a final 'E' to mark the end of the function 23266signature. 23267 23268 23269File: as.info, Node: WebAssembly-Floating-Point, Next: WebAssembly-Opcodes, Prev: WebAssembly-Syntax, Up: WebAssembly-Dependent 23270 232719.52.3 Floating Point 23272--------------------- 23273 23274WebAssembly uses little-endian IEEE floating-point numbers. 23275 23276 23277File: as.info, Node: WebAssembly-Opcodes, Next: WebAssembly-module-layout, Prev: WebAssembly-Floating-Point, Up: WebAssembly-Dependent 23278 232799.52.4 Regular Opcodes 23280---------------------- 23281 23282Ordinary instructions are encoded with the WebAssembly mnemonics as 23283listed at: 23284<https://github.com/WebAssembly/design/blob/master/BinaryEncoding.md>. 23285 23286 Opcodes are written directly in the order in which they are encoded, 23287without going through an intermediate sexp-style expression as in the 23288'was' format. 23289 23290 For "typed" opcodes (block, if, etc.), the type of the block is 23291specified in square brackets following the opcode: 'if[i]', 'if[]'. 23292 23293 23294File: as.info, Node: WebAssembly-module-layout, Prev: WebAssembly-Opcodes, Up: WebAssembly-Dependent 23295 232969.52.5 WebAssembly Module Layout 23297-------------------------------- 23298 23299'as' will only produce ELF output, not a valid WebAssembly module. It 23300is possible to make 'as' produce output in a single ELF section which 23301becomes a valid WebAssembly module, but a linker script to do so may be 23302preferrable, as it doesn't require running the entire module through the 23303assembler at once. 23304 23305 23306File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: WebAssembly-Dependent, Up: Machine Dependencies 23307 233089.53 XGATE Dependent Features 23309============================= 23310 23311* Menu: 23312 23313* XGATE-Opts:: XGATE Options 23314* XGATE-Syntax:: Syntax 23315* XGATE-Directives:: Assembler Directives 23316* XGATE-Float:: Floating Point 23317* XGATE-opcodes:: Opcodes 23318 23319 23320File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent 23321 233229.53.1 XGATE Options 23323-------------------- 23324 23325The Freescale XGATE version of 'as' has a few machine dependent options. 23326 23327'-mshort' 23328 This option controls the ABI and indicates to use a 16-bit integer 23329 ABI. It has no effect on the assembled instructions. This is the 23330 default. 23331 23332'-mlong' 23333 This option controls the ABI and indicates to use a 32-bit integer 23334 ABI. 23335 23336'-mshort-double' 23337 This option controls the ABI and indicates to use a 32-bit float 23338 ABI. This is the default. 23339 23340'-mlong-double' 23341 This option controls the ABI and indicates to use a 64-bit float 23342 ABI. 23343 23344'--print-insn-syntax' 23345 You can use the '--print-insn-syntax' option to obtain the syntax 23346 description of the instruction when an error is detected. 23347 23348'--print-opcodes' 23349 The '--print-opcodes' option prints the list of all the 23350 instructions with their syntax. Once the list is printed 'as' 23351 exits. 23352 23353 23354File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent 23355 233569.53.2 Syntax 23357------------- 23358 23359In XGATE RISC syntax, the instruction name comes first and it may be 23360followed by up to three operands. Operands are separated by commas 23361(','). 'as' will complain if too many operands are specified for a 23362given instruction. The same will happen if you specified too few 23363operands. 23364 23365 nop 23366 ldl #23 23367 CMP R1, R2 23368 23369 The presence of a ';' character or a '!' character anywhere on a line 23370indicates the start of a comment that extends to the end of that line. 23371 23372 A '*' or a '#' character at the start of a line also introduces a 23373line comment, but these characters do not work elsewhere on the line. 23374If the first character of the line is a '#' then as well as starting a 23375comment, the line could also be logical line number directive (*note 23376Comments::) or a preprocessor control command (*note Preprocessing::). 23377 23378 The XGATE assembler does not currently support a line separator 23379character. 23380 23381 The following addressing modes are understood for XGATE: 23382"Inherent" 23383 '' 23384 23385"Immediate 3 Bit Wide" 23386 '#NUMBER' 23387 23388"Immediate 4 Bit Wide" 23389 '#NUMBER' 23390 23391"Immediate 8 Bit Wide" 23392 '#NUMBER' 23393 23394"Monadic Addressing" 23395 'REG' 23396 23397"Dyadic Addressing" 23398 'REG, REG' 23399 23400"Triadic Addressing" 23401 'REG, REG, REG' 23402 23403"Relative Addressing 9 Bit Wide" 23404 '*SYMBOL' 23405 23406"Relative Addressing 10 Bit Wide" 23407 '*SYMBOL' 23408 23409"Index Register plus Immediate Offset" 23410 'REG, (REG, #NUMBER)' 23411 23412"Index Register plus Register Offset" 23413 'REG, REG, REG' 23414 23415"Index Register plus Register Offset with Post-increment" 23416 'REG, REG, REG+' 23417 23418"Index Register plus Register Offset with Pre-decrement" 23419 'REG, REG, -REG' 23420 23421 The register can be either 'R0', 'R1', 'R2', 'R3', 'R4', 'R5', 'R6' 23422 or 'R7'. 23423 23424 Convene macro opcodes to deal with 16-bit values have been added. 23425 23426"Immediate 16 Bit Wide" 23427 '#NUMBER', or '*SYMBOL' 23428 23429 For example: 23430 23431 ldw R1, #1024 23432 ldw R3, timer 23433 ldw R1, (R1, #0) 23434 COM R1 23435 stw R2, (R1, #0) 23436 23437 23438File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent 23439 234409.53.3 Assembler Directives 23441--------------------------- 23442 23443The XGATE version of 'as' have the following specific assembler 23444directives: 23445 23446 23447File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent 23448 234499.53.4 Floating Point 23450--------------------- 23451 23452Packed decimal (P) format floating literals are not supported(yet). 23453 23454 The floating point formats generated by directives are these. 23455 23456'.float' 23457 'Single' precision floating point constants. 23458 23459'.double' 23460 'Double' precision floating point constants. 23461 23462'.extend' 23463'.ldouble' 23464 'Extended' precision ('long double') floating point constants. 23465 23466 23467File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent 23468 234699.53.5 Opcodes 23470-------------- 23471 23472 23473File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies 23474 234759.54 XStormy16 Dependent Features 23476================================= 23477 23478* Menu: 23479 23480* XStormy16 Syntax:: Syntax 23481* XStormy16 Directives:: Machine Directives 23482* XStormy16 Opcodes:: Pseudo-Opcodes 23483 23484 23485File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent 23486 234879.54.1 Syntax 23488------------- 23489 23490* Menu: 23491 23492* XStormy16-Chars:: Special Characters 23493 23494 23495File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax 23496 234979.54.1.1 Special Characters 23498........................... 23499 23500'#' is the line comment character. If a '#' appears as the first 23501character of a line, the whole line is treated as a comment, but in this 23502case the line can also be a logical line number directive (*note 23503Comments::) or a preprocessor control command (*note Preprocessing::). 23504 23505 A semicolon (';') can be used to start a comment that extends from 23506wherever the character appears on the line up to the end of the line. 23507 23508 The '|' character can be used to separate statements on the same 23509line. 23510 23511 23512File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent 23513 235149.54.2 XStormy16 Machine Directives 23515----------------------------------- 23516 23517'.16bit_pointers' 23518 Like the '--16bit-pointers' command-line option this directive 23519 indicates that the assembly code makes use of 16-bit pointers. 23520 23521'.32bit_pointers' 23522 Like the '--32bit-pointers' command-line option this directive 23523 indicates that the assembly code makes use of 32-bit pointers. 23524 23525'.no_pointers' 23526 Like the '--no-pointers' command-line option this directive 23527 indicates that the assembly code does not makes use pointers. 23528 23529 23530File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent 23531 235329.54.3 XStormy16 Pseudo-Opcodes 23533------------------------------- 23534 23535'as' implements all the standard XStormy16 opcodes. 23536 23537 'as' also implements the following pseudo ops: 23538 23539'@lo()' 23540 Computes the lower 16 bits of the given expression and stores it 23541 into the immediate operand field of the given instruction. For 23542 example: 23543 23544 'add r6, @lo(here - there)' 23545 23546 computes the difference between the address of labels 'here' and 23547 'there', takes the lower 16 bits of this difference and adds it to 23548 register 6. 23549 23550'@hi()' 23551 Computes the higher 16 bits of the given expression and stores it 23552 into the immediate operand field of the given instruction. For 23553 example: 23554 23555 'addc r7, @hi(here - there)' 23556 23557 computes the difference between the address of labels 'here' and 23558 'there', takes the upper 16 bits of this difference, shifts it down 23559 16 bits and then adds it, along with the carry bit, to the value in 23560 register 7. 23561 23562 23563File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies 23564 235659.55 Xtensa Dependent Features 23566============================== 23567 23568This chapter covers features of the GNU assembler that are specific to 23569the Xtensa architecture. For details about the Xtensa instruction set, 23570please consult the 'Xtensa Instruction Set Architecture (ISA) Reference 23571Manual'. 23572 23573* Menu: 23574 23575* Xtensa Options:: Command-line Options. 23576* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 23577* Xtensa Optimizations:: Assembler Optimizations. 23578* Xtensa Relaxation:: Other Automatic Transformations. 23579* Xtensa Directives:: Directives for Xtensa Processors. 23580 23581 23582File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 23583 235849.55.1 Command-line Options 23585--------------------------- 23586 23587'--text-section-literals | --no-text-section-literals' 23588 Control the treatment of literal pools. The default is 23589 '--no-text-section-literals', which places literals in separate 23590 sections in the output file. This allows the literal pool to be 23591 placed in a data RAM/ROM. With '--text-section-literals', the 23592 literals are interspersed in the text section in order to keep them 23593 as close as possible to their references. This may be necessary 23594 for large assembly files, where the literals would otherwise be out 23595 of range of the 'L32R' instructions in the text section. Literals 23596 are grouped into pools following '.literal_position' directives or 23597 preceding 'ENTRY' instructions. These options only affect literals 23598 referenced via PC-relative 'L32R' instructions; literals for 23599 absolute mode 'L32R' instructions are handled separately. *Note 23600 literal: Literal Directive. 23601 23602'--auto-litpools | --no-auto-litpools' 23603 Control the treatment of literal pools. The default is 23604 '--no-auto-litpools', which in the absence of 23605 '--text-section-literals' places literals in separate sections in 23606 the output file. This allows the literal pool to be placed in a 23607 data RAM/ROM. With '--auto-litpools', the literals are interspersed 23608 in the text section in order to keep them as close as possible to 23609 their references, explicit '.literal_position' directives are not 23610 required. This may be necessary for very large functions, where 23611 single literal pool at the beginning of the function may not be 23612 reachable by 'L32R' instructions at the end. These options only 23613 affect literals referenced via PC-relative 'L32R' instructions; 23614 literals for absolute mode 'L32R' instructions are handled 23615 separately. When used together with '--text-section-literals', 23616 '--auto-litpools' takes precedence. *Note literal: Literal 23617 Directive. 23618 23619'--absolute-literals | --no-absolute-literals' 23620 Indicate to the assembler whether 'L32R' instructions use absolute 23621 or PC-relative addressing. If the processor includes the absolute 23622 addressing option, the default is to use absolute 'L32R' 23623 relocations. Otherwise, only the PC-relative 'L32R' relocations 23624 can be used. 23625 23626'--target-align | --no-target-align' 23627 Enable or disable automatic alignment to reduce branch penalties at 23628 some expense in code size. *Note Automatic Instruction Alignment: 23629 Xtensa Automatic Alignment. This optimization is enabled by 23630 default. Note that the assembler will always align instructions 23631 like 'LOOP' that have fixed alignment requirements. 23632 23633'--longcalls | --no-longcalls' 23634 Enable or disable transformation of call instructions to allow 23635 calls across a greater range of addresses. *Note Function Call 23636 Relaxation: Xtensa Call Relaxation. This option should be used 23637 when call targets can potentially be out of range. It may degrade 23638 both code size and performance, but the linker can generally 23639 optimize away the unnecessary overhead when a call ends up within 23640 range. The default is '--no-longcalls'. 23641 23642'--transform | --no-transform' 23643 Enable or disable all assembler transformations of Xtensa 23644 instructions, including both relaxation and optimization. The 23645 default is '--transform'; '--no-transform' should only be used in 23646 the rare cases when the instructions must be exactly as specified 23647 in the assembly source. Using '--no-transform' causes out of range 23648 instruction operands to be errors. 23649 23650'--rename-section OLDNAME=NEWNAME' 23651 Rename the OLDNAME section to NEWNAME. This option can be used 23652 multiple times to rename multiple sections. 23653 23654'--trampolines | --no-trampolines' 23655 Enable or disable transformation of jump instructions to allow 23656 jumps across a greater range of addresses. *Note Jump Trampolines: 23657 Xtensa Jump Relaxation. This option should be used when jump 23658 targets can potentially be out of range. In the absence of such 23659 jumps this option does not affect code size or performance. The 23660 default is '--trampolines'. 23661 23662 23663File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 23664 236659.55.2 Assembler Syntax 23666----------------------- 23667 23668Block comments are delimited by '/*' and '*/'. End of line comments may 23669be introduced with either '#' or '//'. 23670 23671 If a '#' appears as the first character of a line then the whole line 23672is treated as a comment, but in this case the line could also be a 23673logical line number directive (*note Comments::) or a preprocessor 23674control command (*note Preprocessing::). 23675 23676 Instructions consist of a leading opcode or macro name followed by 23677whitespace and an optional comma-separated list of operands: 23678 23679 OPCODE [OPERAND, ...] 23680 23681 Instructions must be separated by a newline or semicolon (';'). 23682 23683 FLIX instructions, which bundle multiple opcodes together in a single 23684instruction, are specified by enclosing the bundled opcodes inside 23685braces: 23686 23687 { 23688 [FORMAT] 23689 OPCODE0 [OPERANDS] 23690 OPCODE1 [OPERANDS] 23691 OPCODE2 [OPERANDS] 23692 ... 23693 } 23694 23695 The opcodes in a FLIX instruction are listed in the same order as the 23696corresponding instruction slots in the TIE format declaration. 23697Directives and labels are not allowed inside the braces of a FLIX 23698instruction. A particular TIE format name can optionally be specified 23699immediately after the opening brace, but this is usually unnecessary. 23700The assembler will automatically search for a format that can encode the 23701specified opcodes, so the format name need only be specified in rare 23702cases where there is more than one applicable format and where it 23703matters which of those formats is used. A FLIX instruction can also be 23704specified on a single line by separating the opcodes with semicolons: 23705 23706 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 23707 23708 If an opcode can only be encoded in a FLIX instruction but is not 23709specified as part of a FLIX bundle, the assembler will choose the 23710smallest format where the opcode can be encoded and will fill unused 23711instruction slots with no-ops. 23712 23713* Menu: 23714 23715* Xtensa Opcodes:: Opcode Naming Conventions. 23716* Xtensa Registers:: Register Naming. 23717 23718 23719File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 23720 237219.55.2.1 Opcode Names 23722..................... 23723 23724See the 'Xtensa Instruction Set Architecture (ISA) Reference Manual' for 23725a complete list of opcodes and descriptions of their semantics. 23726 23727 If an opcode name is prefixed with an underscore character ('_'), 23728'as' will not transform that instruction in any way. The underscore 23729prefix disables both optimization (*note Xtensa Optimizations: Xtensa 23730Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 23731Relaxation.) for that particular instruction. Only use the underscore 23732prefix when it is essential to select the exact opcode produced by the 23733assembler. Using this feature unnecessarily makes the code less 23734efficient by disabling assembler optimization and less flexible by 23735disabling relaxation. 23736 23737 Note that this special handling of underscore prefixes only applies 23738to Xtensa opcodes, not to either built-in macros or user-defined macros. 23739When an underscore prefix is used with a macro (e.g., '_MOV'), it refers 23740to a different macro. The assembler generally provides built-in macros 23741both with and without the underscore prefix, where the underscore 23742versions behave as if the underscore carries through to the instructions 23743in the macros. For example, '_MOV' may expand to '_MOV.N'. 23744 23745 The underscore prefix only applies to individual instructions, not to 23746series of instructions. For example, if a series of instructions have 23747underscore prefixes, the assembler will not transform the individual 23748instructions, but it may insert other instructions between them (e.g., 23749to align a 'LOOP' instruction). To prevent the assembler from modifying 23750a series of instructions as a whole, use the 'no-transform' directive. 23751*Note transform: Transform Directive. 23752 23753 23754File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 23755 237569.55.2.2 Register Names 23757....................... 23758 23759The assembly syntax for a register file entry is the "short" name for a 23760TIE register file followed by the index into that register file. For 23761example, the general-purpose 'AR' register file has a short name of 'a', 23762so these registers are named 'a0'...'a15'. As a special feature, 'sp' 23763is also supported as a synonym for 'a1'. Additional registers may be 23764added by processor configuration options and by designer-defined TIE 23765extensions. An initial '$' character is optional in all register names. 23766 23767 23768File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 23769 237709.55.3 Xtensa Optimizations 23771--------------------------- 23772 23773The optimizations currently supported by 'as' are generation of density 23774instructions where appropriate and automatic branch target alignment. 23775 23776* Menu: 23777 23778* Density Instructions:: Using Density Instructions. 23779* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 23780 23781 23782File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 23783 237849.55.3.1 Using Density Instructions 23785................................... 23786 23787The Xtensa instruction set has a code density option that provides 2378816-bit versions of some of the most commonly used opcodes. Use of these 23789opcodes can significantly reduce code size. When possible, the 23790assembler automatically translates instructions from the core Xtensa 23791instruction set into equivalent instructions from the Xtensa code 23792density option. This translation can be disabled by using underscore 23793prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 23794'--no-transform' command-line option (*note Command Line Options: Xtensa 23795Options.), or by using the 'no-transform' directive (*note transform: 23796Transform Directive.). 23797 23798 It is a good idea _not_ to use the density instructions directly. 23799The assembler will automatically select dense instructions where 23800possible. If you later need to use an Xtensa processor without the code 23801density option, the same assembly code will then work without 23802modification. 23803 23804 23805File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 23806 238079.55.3.2 Automatic Instruction Alignment 23808........................................ 23809 23810The Xtensa assembler will automatically align certain instructions, both 23811to optimize performance and to satisfy architectural requirements. 23812 23813 As an optimization to improve performance, the assembler attempts to 23814align branch targets so they do not cross instruction fetch boundaries. 23815(Xtensa processors can be configured with either 32-bit or 64-bit 23816instruction fetch widths.) An instruction immediately following a call 23817is treated as a branch target in this context, because it will be the 23818target of a return from the call. This alignment has the potential to 23819reduce branch penalties at some expense in code size. This optimization 23820is enabled by default. You can disable it with the '--no-target-align' 23821command-line option (*note Command-line Options: Xtensa Options.). 23822 23823 The target alignment optimization is done without adding instructions 23824that could increase the execution time of the program. If there are 23825density instructions in the code preceding a target, the assembler can 23826change the target alignment by widening some of those instructions to 23827the equivalent 24-bit instructions. Extra bytes of padding can be 23828inserted immediately following unconditional jump and return 23829instructions. This approach is usually successful in aligning many, but 23830not all, branch targets. 23831 23832 The 'LOOP' family of instructions must be aligned such that the first 23833instruction in the loop body does not cross an instruction fetch 23834boundary (e.g., with a 32-bit fetch width, a 'LOOP' instruction must be 23835on either a 1 or 2 mod 4 byte boundary). The assembler knows about this 23836restriction and inserts the minimal number of 2 or 3 byte no-op 23837instructions to satisfy it. When no-op instructions are added, any 23838label immediately preceding the original loop will be moved in order to 23839refer to the loop instruction, not the newly generated no-op 23840instruction. To preserve binary compatibility across processors with 23841different fetch widths, the assembler conservatively assumes a 32-bit 23842fetch width when aligning 'LOOP' instructions (except if the first 23843instruction in the loop is a 64-bit instruction). 23844 23845 Previous versions of the assembler automatically aligned 'ENTRY' 23846instructions to 4-byte boundaries, but that alignment is now the 23847programmer's responsibility. 23848 23849 23850File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 23851 238529.55.4 Xtensa Relaxation 23853------------------------ 23854 23855When an instruction operand is outside the range allowed for that 23856particular instruction field, 'as' can transform the code to use a 23857functionally-equivalent instruction or sequence of instructions. This 23858process is known as "relaxation". This is typically done for branch 23859instructions because the distance of the branch targets is not known 23860until assembly-time. The Xtensa assembler offers branch relaxation and 23861also extends this concept to function calls, 'MOVI' instructions and 23862other instructions with immediate fields. 23863 23864* Menu: 23865 23866* Xtensa Branch Relaxation:: Relaxation of Branches. 23867* Xtensa Call Relaxation:: Relaxation of Function Calls. 23868* Xtensa Jump Relaxation:: Relaxation of Jumps. 23869* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 23870 23871 23872File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 23873 238749.55.4.1 Conditional Branch Relaxation 23875...................................... 23876 23877When the target of a branch is too far away from the branch itself, 23878i.e., when the offset from the branch to the target is too large to fit 23879in the immediate field of the branch instruction, it may be necessary to 23880replace the branch with a branch around a jump. For example, 23881 23882 beqz a2, L 23883 23884 may result in: 23885 23886 bnez.n a2, M 23887 j L 23888 M: 23889 23890 (The 'BNEZ.N' instruction would be used in this example only if the 23891density option is available. Otherwise, 'BNEZ' would be used.) 23892 23893 This relaxation works well because the unconditional jump instruction 23894has a much larger offset range than the various conditional branches. 23895However, an error will occur if a branch target is beyond the range of a 23896jump instruction. 'as' cannot relax unconditional jumps. Similarly, an 23897error will occur if the original input contains an unconditional jump to 23898a target that is out of range. 23899 23900 Branch relaxation is enabled by default. It can be disabled by using 23901underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 23902'--no-transform' command-line option (*note Command-line Options: Xtensa 23903Options.), or the 'no-transform' directive (*note transform: Transform 23904Directive.). 23905 23906 23907File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Jump Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 23908 239099.55.4.2 Function Call Relaxation 23910................................. 23911 23912Function calls may require relaxation because the Xtensa immediate call 23913instructions ('CALL0', 'CALL4', 'CALL8' and 'CALL12') provide a 23914PC-relative offset of only 512 Kbytes in either direction. For larger 23915programs, it may be necessary to use indirect calls ('CALLX0', 'CALLX4', 23916'CALLX8' and 'CALLX12') where the target address is specified in a 23917register. The Xtensa assembler can automatically relax immediate call 23918instructions into indirect call instructions. This relaxation is done 23919by loading the address of the called function into the callee's return 23920address register and then using a 'CALLX' instruction. So, for example: 23921 23922 call8 func 23923 23924 might be relaxed to: 23925 23926 .literal .L1, func 23927 l32r a8, .L1 23928 callx8 a8 23929 23930 Because the addresses of targets of function calls are not generally 23931known until link-time, the assembler must assume the worst and relax all 23932the calls to functions in other source files, not just those that really 23933will be out of range. The linker can recognize calls that were 23934unnecessarily relaxed, and it will remove the overhead introduced by the 23935assembler for those cases where direct calls are sufficient. 23936 23937 Call relaxation is disabled by default because it can have a negative 23938effect on both code size and performance, although the linker can 23939usually eliminate the unnecessary overhead. If a program is too large 23940and some of the calls are out of range, function call relaxation can be 23941enabled using the '--longcalls' command-line option or the 'longcalls' 23942directive (*note longcalls: Longcalls Directive.). 23943 23944 23945File: as.info, Node: Xtensa Jump Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 23946 239479.55.4.3 Jump Relaxation 23948........................ 23949 23950Jump instruction may require relaxation because the Xtensa jump 23951instruction ('J') provide a PC-relative offset of only 128 Kbytes in 23952either direction. One option is to use jump long ('J.L') instruction, 23953which depending on jump distance may be assembled as jump ('J') or 23954indirect jump ('JX'). However it needs a free register. When there's 23955no spare register it is possible to plant intermediate jump sites 23956(trampolines) between the jump instruction and its target. These sites 23957may be located in areas unreachable by normal code execution flow, in 23958that case they only contain intermediate jumps, or they may be inserted 23959in the middle of code block, in which case there's an additional jump 23960from the beginning of the trampoline to the instruction past its end. 23961So, for example: 23962 23963 j 1f 23964 ... 23965 retw 23966 ... 23967 mov a10, a2 23968 call8 func 23969 ... 23970 1: 23971 ... 23972 23973 might be relaxed to: 23974 23975 j .L0_TR_1 23976 ... 23977 retw 23978 .L0_TR_1: 23979 j 1f 23980 ... 23981 mov a10, a2 23982 call8 func 23983 ... 23984 1: 23985 ... 23986 23987 or to: 23988 23989 j .L0_TR_1 23990 ... 23991 retw 23992 ... 23993 mov a10, a2 23994 j .L0_TR_0 23995 .L0_TR_1: 23996 j 1f 23997 .L0_TR_0: 23998 call8 func 23999 ... 24000 1: 24001 ... 24002 24003 The Xtensa assembler uses trampolines with jump around only when it 24004cannot find suitable unreachable trampoline. There may be multiple 24005trampolines between the jump instruction and its target. 24006 24007 This relaxation does not apply to jumps to undefined symbols, 24008assuming they will reach their targets once resolved. 24009 24010 Jump relaxation is enabled by default because it does not affect code 24011size or performance while the code itself is small. This relaxation may 24012be disabled completely with '--no-trampolines' or '--no-transform' 24013command-line options (*note Command-line Options: Xtensa Options.). 24014 24015 24016File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Jump Relaxation, Up: Xtensa Relaxation 24017 240189.55.4.4 Other Immediate Field Relaxation 24019......................................... 24020 24021The assembler normally performs the following other relaxations. They 24022can be disabled by using underscore prefixes (*note Opcode Names: Xtensa 24023Opcodes.), the '--no-transform' command-line option (*note Command-line 24024Options: Xtensa Options.), or the 'no-transform' directive (*note 24025transform: Transform Directive.). 24026 24027 The 'MOVI' machine instruction can only materialize values in the 24028range from -2048 to 2047. Values outside this range are best 24029materialized with 'L32R' instructions. Thus: 24030 24031 movi a0, 100000 24032 24033 is assembled into the following machine code: 24034 24035 .literal .L1, 100000 24036 l32r a0, .L1 24037 24038 The 'L8UI' machine instruction can only be used with immediate 24039offsets in the range from 0 to 255. The 'L16SI' and 'L16UI' machine 24040instructions can only be used with offsets from 0 to 510. The 'L32I' 24041machine instruction can only be used with offsets from 0 to 1020. A 24042load offset outside these ranges can be materialized with an 'L32R' 24043instruction if the destination register of the load is different than 24044the source address register. For example: 24045 24046 l32i a1, a0, 2040 24047 24048 is translated to: 24049 24050 .literal .L1, 2040 24051 l32r a1, .L1 24052 add a1, a0, a1 24053 l32i a1, a1, 0 24054 24055If the load destination and source address register are the same, an 24056out-of-range offset causes an error. 24057 24058 The Xtensa 'ADDI' instruction only allows immediate operands in the 24059range from -128 to 127. There are a number of alternate instruction 24060sequences for the 'ADDI' operation. First, if the immediate is 0, the 24061'ADDI' will be turned into a 'MOV.N' instruction (or the equivalent 'OR' 24062instruction if the code density option is not available). If the 'ADDI' 24063immediate is outside of the range -128 to 127, but inside the range 24064-32896 to 32639, an 'ADDMI' instruction or 'ADDMI'/'ADDI' sequence will 24065be used. Finally, if the immediate is outside of this range and a free 24066register is available, an 'L32R'/'ADD' sequence will be used with a 24067literal allocated from the literal pool. 24068 24069 For example: 24070 24071 addi a5, a6, 0 24072 addi a5, a6, 512 24073 addi a5, a6, 513 24074 addi a5, a6, 50000 24075 24076 is assembled into the following: 24077 24078 .literal .L1, 50000 24079 mov.n a5, a6 24080 addmi a5, a6, 0x200 24081 addmi a5, a6, 0x200 24082 addi a5, a5, 1 24083 l32r a5, .L1 24084 add a5, a6, a5 24085 24086 24087File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 24088 240899.55.5 Directives 24090----------------- 24091 24092The Xtensa assembler supports a region-based directive syntax: 24093 24094 .begin DIRECTIVE [OPTIONS] 24095 ... 24096 .end DIRECTIVE 24097 24098 All the Xtensa-specific directives that apply to a region of code use 24099this syntax. 24100 24101 The directive applies to code between the '.begin' and the '.end'. 24102The state of the option after the '.end' reverts to what it was before 24103the '.begin'. A nested '.begin'/'.end' region can further change the 24104state of the directive without having to be aware of its outer state. 24105For example, consider: 24106 24107 .begin no-transform 24108 L: add a0, a1, a2 24109 .begin transform 24110 M: add a0, a1, a2 24111 .end transform 24112 N: add a0, a1, a2 24113 .end no-transform 24114 24115 The 'ADD' opcodes at 'L' and 'N' in the outer 'no-transform' region 24116both result in 'ADD' machine instructions, but the assembler selects an 24117'ADD.N' instruction for the 'ADD' at 'M' in the inner 'transform' 24118region. 24119 24120 The advantage of this style is that it works well inside macros which 24121can preserve the context of their callers. 24122 24123 The following directives are available: 24124* Menu: 24125 24126* Schedule Directive:: Enable instruction scheduling. 24127* Longcalls Directive:: Use Indirect Calls for Greater Range. 24128* Transform Directive:: Disable All Assembler Transformations. 24129* Literal Directive:: Intermix Literals with Instructions. 24130* Literal Position Directive:: Specify Inline Literal Pool Locations. 24131* Literal Prefix Directive:: Specify Literal Section Name Prefix. 24132* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 24133 24134 24135File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 24136 241379.55.5.1 schedule 24138................. 24139 24140The 'schedule' directive is recognized only for compatibility with 24141Tensilica's assembler. 24142 24143 .begin [no-]schedule 24144 .end [no-]schedule 24145 24146 This directive is ignored and has no effect on 'as'. 24147 24148 24149File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 24150 241519.55.5.2 longcalls 24152.................. 24153 24154The 'longcalls' directive enables or disables function call relaxation. 24155*Note Function Call Relaxation: Xtensa Call Relaxation. 24156 24157 .begin [no-]longcalls 24158 .end [no-]longcalls 24159 24160 Call relaxation is disabled by default unless the '--longcalls' 24161command-line option is specified. The 'longcalls' directive overrides 24162the default determined by the command-line options. 24163 24164 24165File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 24166 241679.55.5.3 transform 24168.................. 24169 24170This directive enables or disables all assembler transformation, 24171including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 24172optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 24173 24174 .begin [no-]transform 24175 .end [no-]transform 24176 24177 Transformations are enabled by default unless the '--no-transform' 24178option is used. The 'transform' directive overrides the default 24179determined by the command-line options. An underscore opcode prefix, 24180disabling transformation of that opcode, always takes precedence over 24181both directives and command-line flags. 24182 24183 24184File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 24185 241869.55.5.4 literal 24187................ 24188 24189The '.literal' directive is used to define literal pool data, i.e., 24190read-only 32-bit data accessed via 'L32R' instructions. 24191 24192 .literal LABEL, VALUE[, VALUE...] 24193 24194 This directive is similar to the standard '.word' directive, except 24195that the actual location of the literal data is determined by the 24196assembler and linker, not by the position of the '.literal' directive. 24197Using this directive gives the assembler freedom to locate the literal 24198data in the most appropriate place and possibly to combine identical 24199literals. For example, the code: 24200 24201 entry sp, 40 24202 .literal .L1, sym 24203 l32r a4, .L1 24204 24205 can be used to load a pointer to the symbol 'sym' into register 'a4'. 24206The value of 'sym' will not be placed between the 'ENTRY' and 'L32R' 24207instructions; instead, the assembler puts the data in a literal pool. 24208 24209 Literal pools are placed by default in separate literal sections; 24210however, when using the '--text-section-literals' option (*note 24211Command-line Options: Xtensa Options.), the literal pools for 24212PC-relative mode 'L32R' instructions are placed in the current 24213section.(1) These text section literal pools are created automatically 24214before 'ENTRY' instructions and manually after '.literal_position' 24215directives (*note literal_position: Literal Position Directive.). If 24216there are no preceding 'ENTRY' instructions, explicit 24217'.literal_position' directives must be used to place the text section 24218literal pools; otherwise, 'as' will report an error. 24219 24220 When literals are placed in separate sections, the literal section 24221names are derived from the names of the sections where the literals are 24222defined. The base literal section names are '.literal' for PC-relative 24223mode 'L32R' instructions and '.lit4' for absolute mode 'L32R' 24224instructions (*note absolute-literals: Absolute Literals Directive.). 24225These base names are used for literals defined in the default '.text' 24226section. For literals defined in other sections or within the scope of 24227a 'literal_prefix' directive (*note literal_prefix: Literal Prefix 24228Directive.), the following rules determine the literal section name: 24229 24230 1. If the current section is a member of a section group, the literal 24231 section name includes the group name as a suffix to the base 24232 '.literal' or '.lit4' name, with a period to separate the base name 24233 and group name. The literal section is also made a member of the 24234 group. 24235 24236 2. If the current section name (or 'literal_prefix' value) begins with 24237 "'.gnu.linkonce.KIND.'", the literal section name is formed by 24238 replacing "'.KIND'" with the base '.literal' or '.lit4' name. For 24239 example, for literals defined in a section named 24240 '.gnu.linkonce.t.func', the literal section will be 24241 '.gnu.linkonce.literal.func' or '.gnu.linkonce.lit4.func'. 24242 24243 3. If the current section name (or 'literal_prefix' value) ends with 24244 '.text', the literal section name is formed by replacing that 24245 suffix with the base '.literal' or '.lit4' name. For example, for 24246 literals defined in a section named '.iram0.text', the literal 24247 section will be '.iram0.literal' or '.iram0.lit4'. 24248 24249 4. If none of the preceding conditions apply, the literal section name 24250 is formed by adding the base '.literal' or '.lit4' name as a suffix 24251 to the current section name (or 'literal_prefix' value). 24252 24253 ---------- Footnotes ---------- 24254 24255 (1) Literals for the '.init' and '.fini' sections are always placed 24256in separate sections, even when '--text-section-literals' is enabled. 24257 24258 24259File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 24260 242619.55.5.5 literal_position 24262......................... 24263 24264When using '--text-section-literals' to place literals inline in the 24265section being assembled, the '.literal_position' directive can be used 24266to mark a potential location for a literal pool. 24267 24268 .literal_position 24269 24270 The '.literal_position' directive is ignored when the 24271'--text-section-literals' option is not used or when 'L32R' instructions 24272use the absolute addressing mode. 24273 24274 The assembler will automatically place text section literal pools 24275before 'ENTRY' instructions, so the '.literal_position' directive is 24276only needed to specify some other location for a literal pool. You may 24277need to add an explicit jump instruction to skip over an inline literal 24278pool. 24279 24280 For example, an interrupt vector does not begin with an 'ENTRY' 24281instruction so the assembler will be unable to automatically find a good 24282place to put a literal pool. Moreover, the code for the interrupt 24283vector must be at a specific starting address, so the literal pool 24284cannot come before the start of the code. The literal pool for the 24285vector must be explicitly positioned in the middle of the vector (before 24286any uses of the literals, due to the negative offsets used by 24287PC-relative 'L32R' instructions). The '.literal_position' directive can 24288be used to do this. In the following code, the literal for 'M' will 24289automatically be aligned correctly and is placed after the unconditional 24290jump. 24291 24292 .global M 24293 code_start: 24294 j continue 24295 .literal_position 24296 .align 4 24297 continue: 24298 movi a4, M 24299 24300 24301File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 24302 243039.55.5.6 literal_prefix 24304....................... 24305 24306The 'literal_prefix' directive allows you to override the default 24307literal section names, which are derived from the names of the sections 24308where the literals are defined. 24309 24310 .begin literal_prefix [NAME] 24311 .end literal_prefix 24312 24313 For literals defined within the delimited region, the literal section 24314names are derived from the NAME argument instead of the name of the 24315current section. The rules used to derive the literal section names do 24316not change. *Note literal: Literal Directive. If the NAME argument is 24317omitted, the literal sections revert to the defaults. This directive 24318has no effect when using the '--text-section-literals' option (*note 24319Command-line Options: Xtensa Options.). 24320 24321 24322File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 24323 243249.55.5.7 absolute-literals 24325.......................... 24326 24327The 'absolute-literals' and 'no-absolute-literals' directives control 24328the absolute vs. PC-relative mode for 'L32R' instructions. These are 24329relevant only for Xtensa configurations that include the absolute 24330addressing option for 'L32R' instructions. 24331 24332 .begin [no-]absolute-literals 24333 .end [no-]absolute-literals 24334 24335 These directives do not change the 'L32R' mode--they only cause the 24336assembler to emit the appropriate kind of relocation for 'L32R' 24337instructions and to place the literal values in the appropriate section. 24338To change the 'L32R' mode, the program must write the 'LITBASE' special 24339register. It is the programmer's responsibility to keep track of the 24340mode and indicate to the assembler which mode is used in each region of 24341code. 24342 24343 If the Xtensa configuration includes the absolute 'L32R' addressing 24344option, the default is to assume absolute 'L32R' addressing unless the 24345'--no-absolute-literals' command-line option is specified. Otherwise, 24346the default is to assume PC-relative 'L32R' addressing. The 24347'absolute-literals' directive can then be used to override the default 24348determined by the command-line options. 24349 24350 24351File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 24352 243539.56 Z80 Dependent Features 24354=========================== 24355 24356* Menu: 24357 24358* Z80 Options:: Options 24359* Z80 Syntax:: Syntax 24360* Z80 Floating Point:: Floating Point 24361* Z80 Directives:: Z80 Machine Directives 24362* Z80 Opcodes:: Opcodes 24363 24364 24365File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 24366 243679.56.1 Command-line Options 24368--------------------------- 24369 24370'-z80' 24371 Produce code for the Z80 processor. By default accepted 24372 undocumented operations with halves of index registers ('IXL', 24373 'IXH', 'IYL', 'IYH') and instuction 'IN F,(C)'. Other useful 24374 undocumented instructions produces warnings. Undocumented 24375 instructions may not work on some CPUs, use them on your own risk. 24376 24377'-r800' 24378 Produce code for the R800 processor. 24379 24380'-z180' 24381 Produce code for the Z180 processor. 24382 24383'-ez80' 24384 Produce code for the eZ80 processor in Z80 memory mode by default. 24385 24386'-ez80-adl' 24387 Produce code for the eZ80 processor in ADL memory mode by default. 24388 24389'-local-prefix=PREFIX' 24390 Mark all labels with specified prefix as local. But such label can 24391 be marked global explicitly in the code. This option do not change 24392 default local label prefix '.L', it is just adds new one. 24393 24394'-colonless' 24395 Accept colonless labels. All names at line begin are treated as 24396 labels. 24397 24398'-sdcc' 24399 Accept assembler code produced by SDCC. 24400 24401'-fp-s=FORMAT' 24402 Single precision floating point numbers format. Default: ieee754 24403 (32 bit). 24404 24405'-fp-d=FORMAT' 24406 Double precision floating point numbers format. Default: ieee754 24407 (64 bit). 24408 24409'-strict' 24410 Accept documented instructions only. 24411 24412'-full' 24413 Accept all known Z80 instructions. 24414 24415'-with-inst=INST[,...]' 24416'-Wnins INST[,...]' 24417 Enable specified undocumented instruction(s). 24418 24419'-without-inst=INST[,...]' 24420'-Fins INST[,...]' 24421 Disable specified undocumented instruction(s). 24422 24423'-ignore-undocumented-instructions' 24424'-Wnud' 24425 Silently assemble undocumented Z80-instructions that have been 24426 adopted as documented R800-instructions . 24427'-ignore-unportable-instructions' 24428'-Wnup' 24429 Silently assemble all undocumented Z80-instructions. 24430'-warn-undocumented-instructions' 24431'-Wud' 24432 Issue warnings for undocumented Z80-instructions that work on R800, 24433 do not assemble other undocumented instructions without warning. 24434'-warn-unportable-instructions' 24435'-Wup' 24436 Issue warnings for other undocumented Z80-instructions, do not 24437 treat any undocumented instructions as errors. 24438'-forbid-undocumented-instructions' 24439'-Fud' 24440 Treat all undocumented z80-instructions as errors. 24441'-forbid-unportable-instructions' 24442'-Fup' 24443 Treat undocumented z80-instructions that do not work on R800 as 24444 errors. 24445 24446 Floating point numbers formats. 24447'ieee754' 24448 Single or double precision IEEE754 compatible format. 24449 24450'half' 24451 Half precision IEEE754 compatible format (16 bits). 24452 24453'single' 24454 Single precision IEEE754 compatible format (32 bits). 24455 24456'double' 24457 Double precision IEEE754 compatible format (64 bits). 24458 24459'zeda32' 24460 32 bit floating point format from z80float library by Zeda. 24461 24462'math48' 24463 48 bit floating point format from Math48 package by Anders 24464 Hejlsberg. 24465 24466 Known undocumented instructions. 24467'idx-reg-halves' 24468 All operations with halves of index registers ('IXL', 'IXH', 'IYL', 24469 'IYH'). 24470'sli' 24471 'SLI' or 'SLL' instruction. Same as 'SLA r; INC r'. 24472'op-ii-ld' 24473 Istructions like '<op> (<ii>+<d>),<r>'. For example: 'RL (IX+5),C' 24474'in-f-c' 24475 Instruction 'IN F,(C)'. 24476'out-c-0' 24477 Instruction 'OUT (C),0' 24478 24479 24480File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 24481 244829.56.2 Syntax 24483------------- 24484 24485The assembler syntax closely follows the 'Z80 family CPU User Manual' by 24486Zilog. In expressions a single '=' may be used as "is equal to" 24487comparison operator. 24488 24489 Suffices can be used to indicate the radix of integer constants; 'H' 24490or 'h' for hexadecimal, 'D' or 'd' for decimal, 'Q', 'O', 'q' or 'o' for 24491octal, and 'B' for binary. 24492 24493 The suffix 'b' denotes a backreference to local label. 24494 24495* Menu: 24496 24497* Z80-Chars:: Special Characters 24498* Z80-Regs:: Register Names 24499* Z80-Case:: Case Sensitivity 24500* Z80-Labels:: Labels 24501 24502 24503File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 24504 245059.56.2.1 Special Characters 24506........................... 24507 24508The semicolon ';' is the line comment character; 24509 24510 If a '#' appears as the first character of a line then the whole line 24511is treated as a comment, but in this case the line could also be a 24512logical line number directive (*note Comments::) or a preprocessor 24513control command (*note Preprocessing::). 24514 24515 The Z80 assembler does not support a line separator character. 24516 24517 The dollar sign '$' can be used as a prefix for hexadecimal numbers 24518and as a symbol denoting the current location counter. 24519 24520 A backslash '\' is an ordinary character for the Z80 assembler. 24521 24522 The single quote ''' must be followed by a closing quote. If there 24523is one character in between, it is a character constant, otherwise it is 24524a string constant. 24525 24526 24527File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 24528 245299.56.2.2 Register Names 24530....................... 24531 24532The registers are referred to with the letters assigned to them by 24533Zilog. In addition 'as' recognizes 'ixl' and 'ixh' as the least and 24534most significant octet in 'ix', and similarly 'iyl' and 'iyh' as parts 24535of 'iy'. 24536 24537 24538File: as.info, Node: Z80-Case, Next: Z80-Labels, Prev: Z80-Regs, Up: Z80 Syntax 24539 245409.56.2.3 Case Sensitivity 24541......................... 24542 24543Upper and lower case are equivalent in register names, opcodes, 24544condition codes and assembler directives. The case of letters is 24545significant in labels and symbol names. The case is also important to 24546distinguish the suffix 'b' for a backward reference to a local label 24547from the suffix 'B' for a number in binary notation. 24548 24549 24550File: as.info, Node: Z80-Labels, Prev: Z80-Case, Up: Z80 Syntax 24551 245529.56.2.4 Labels 24553............... 24554 24555Labels started by '.L' acts as local labels. You may specify custom 24556local label prefix by '-local-prefix' command-line option. Dollar, 24557forward and backward local labels are supported. By default, all labels 24558are followed by colon. Legacy code with colonless labels can be built 24559with '-colonless' command-line option specified. In this case all 24560tokens at line begin are treated as labels. 24561 24562 24563File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 24564 245659.56.3 Floating Point 24566--------------------- 24567 24568Floating-point numbers of following types are supported: 24569 24570'ieee754' 24571 Supported half, single and double precision IEEE754 compatible 24572 numbers. 24573 24574'zeda32' 24575 32 bit floating point numbers from z80float library by Zeda. 24576 24577'math48' 24578 48 bit floating point numbers from Math48 package by Anders 24579 Hejlsberg. 24580 24581 24582File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 24583 245849.56.4 Z80 Assembler Directives 24585------------------------------- 24586 24587'as' for the Z80 supports some additional directives for compatibility 24588with other assemblers. 24589 24590 These are the additional directives in 'as' for the Z80: 24591 24592'assume ADL'='EXPRESSION' 24593 Set ADL status for eZ80. Non-zero value enable compilation in ADL 24594 mode else used Z80 mode. ADL and Z80 mode produces incompatible 24595 object code. Mixing both of them within one binary may lead 24596 problems with disassembler. 24597 24598'db EXPRESSION|STRING[,EXPRESSION|STRING...]' 24599'defb EXPRESSION|STRING[,EXPRESSION|STRING...]' 24600'defm STRING...]' 24601 For each STRING the characters are copied to the object file, for 24602 each other EXPRESSION the value is stored in one byte. A warning 24603 is issued in case of an overflow. Backslash symbol in the strings 24604 is generic symbol, it cannot be used as escape character (for this 24605 purpose use '.ascii' or '.asciiz' directives). 24606 24607'dw EXPRESSION[,EXPRESSION...]' 24608'defw EXPRESSION[,EXPRESSION...]' 24609 For each EXPRESSION the value is stored in two bytes, ignoring 24610 overflow. 24611 24612'd24 EXPRESSION[,EXPRESSION...]' 24613'def24 EXPRESSION[,EXPRESSION...]' 24614 For each EXPRESSION the value is stored in three bytes, ignoring 24615 overflow. 24616 24617'd32 EXPRESSION[,EXPRESSION...]' 24618'def32 EXPRESSION[,EXPRESSION...]' 24619 For each EXPRESSION the value is stored in four bytes, ignoring 24620 overflow. 24621 24622'ds COUNT[, VALUE]' 24623'defs COUNT[, VALUE]' 24624 Fill COUNT bytes in the object file with VALUE, if VALUE is omitted 24625 it defaults to zero. 24626 24627'SYMBOL equ EXPRESSION' 24628'SYMBOL defl EXPRESSION' 24629 These directives set the value of SYMBOL to EXPRESSION. If 'equ' 24630 is used, it is an error if SYMBOL is already defined. Symbols 24631 defined with 'equ' are not protected from redefinition. 24632 24633'psect NAME' 24634 A synonym for *Note Section::, no second argument should be given. 24635 24636 24637File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 24638 246399.56.5 Opcodes 24640-------------- 24641 24642In line with common practice, Z80 mnemonics are used for the Z80, the 24643Z180, eZ80 and the R800. 24644 24645 In many instructions it is possible to use one of the half index 24646registers ('ixl','ixh','iyl','iyh') in stead of an 8-bit general purpose 24647register. This yields instructions that are documented on the eZ80 and 24648the R800, undocumented on the Z80 and unsupported on the Z180. 24649Similarly 'in f,(c)' is documented on the R800, undocumented on the Z80 24650and unsupported on the Z180 and the eZ80. 24651 24652 The assembler also supports the following undocumented 24653Z80-instructions, that have not been adopted in any other instruction 24654set: 24655'out (c),0' 24656 Sends zero to the port pointed to by register 'C'. 24657 24658'sli M' 24659 Equivalent to 'M = (M<<1)+1', the operand M can be any operand that 24660 is valid for 'sla'. One can use 'sll' as a synonym for 'sli'. 24661 24662'OP (ix+D), R' 24663 This is equivalent to 24664 24665 ld R, (ix+D) 24666 OPC R 24667 ld (ix+D), R 24668 24669 The operation 'OPC' may be any of 'res B,', 'set B,', 'rl', 'rlc', 24670 'rr', 'rrc', 'sla', 'sli', 'sra' and 'srl', and the register 'R' 24671 may be any of 'a', 'b', 'c', 'd', 'e', 'h' and 'l'. 24672 24673'OPC (iy+D), R' 24674 As above, but with 'iy' instead of 'ix'. 24675 24676 The web site at <http://www.z80.info> is a good starting place to 24677find more information on programming the Z80. 24678 24679 You may enable or disable any of these instructions for any target 24680CPU even this instruction is not supported by any real CPU of this type. 24681Useful for custom CPU cores. 24682 24683 24684File: as.info, Node: Z8000-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 24685 246869.57 Z8000 Dependent Features 24687============================= 24688 24689The Z8000 as supports both members of the Z8000 family: the unsegmented 24690Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit 24691addresses. 24692 24693 When the assembler is in unsegmented mode (specified with the 24694'unsegm' directive), an address takes up one word (16 bit) sized 24695register. When the assembler is in segmented mode (specified with the 24696'segm' directive), a 24-bit address takes up a long (32 bit) register. 24697*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 24698of other Z8000 specific assembler directives. 24699 24700* Menu: 24701 24702* Z8000 Options:: Command-line options for the Z8000 24703* Z8000 Syntax:: Assembler syntax for the Z8000 24704* Z8000 Directives:: Special directives for the Z8000 24705* Z8000 Opcodes:: Opcodes 24706 24707 24708File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 24709 247109.57.1 Options 24711-------------- 24712 24713'-z8001' 24714 Generate segmented code by default. 24715 24716'-z8002' 24717 Generate unsegmented code by default. 24718 24719 24720File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 24721 247229.57.2 Syntax 24723------------- 24724 24725* Menu: 24726 24727* Z8000-Chars:: Special Characters 24728* Z8000-Regs:: Register Names 24729* Z8000-Addressing:: Addressing Modes 24730 24731 24732File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 24733 247349.57.2.1 Special Characters 24735........................... 24736 24737'!' is the line comment character. 24738 24739 If a '#' appears as the first character of a line then the whole line 24740is treated as a comment, but in this case the line could also be a 24741logical line number directive (*note Comments::) or a preprocessor 24742control command (*note Preprocessing::). 24743 24744 You can use ';' instead of a newline to separate statements. 24745 24746 24747File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 24748 247499.57.2.2 Register Names 24750....................... 24751 24752The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 24753to different sized groups of registers by register number, with the 24754prefix 'r' for 16 bit registers, 'rr' for 32 bit registers and 'rq' for 2475564 bit registers. You can also refer to the contents of the first eight 24756(of the sixteen 16 bit registers) by bytes. They are named 'rlN' and 24757'rhN'. 24758 24759_byte registers_ 24760 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 24761 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 24762 24763_word registers_ 24764 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 24765 24766_long word registers_ 24767 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 24768 24769_quad word registers_ 24770 rq0 rq4 rq8 rq12 24771 24772 24773File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 24774 247759.57.2.3 Addressing Modes 24776......................... 24777 24778as understands the following addressing modes for the Z8000: 24779 24780'rlN' 24781'rhN' 24782'rN' 24783'rrN' 24784'rqN' 24785 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 24786 24787'@rN' 24788'@rrN' 24789 Indirect register: @rrN in segmented mode, @rN in unsegmented mode. 24790 24791'ADDR' 24792 Direct: the 16 bit or 24 bit address (depending on whether the 24793 assembler is in segmented or unsegmented mode) of the operand is in 24794 the instruction. 24795 24796'address(rN)' 24797 Indexed: the 16 or 24 bit address is added to the 16 bit register 24798 to produce the final address in memory of the operand. 24799 24800'rN(#IMM)' 24801'rrN(#IMM)' 24802 Base Address: the 16 or 24 bit register is added to the 16 bit sign 24803 extended immediate displacement to produce the final address in 24804 memory of the operand. 24805 24806'rN(rM)' 24807'rrN(rM)' 24808 Base Index: the 16 or 24 bit register rN or rrN is added to the 24809 sign extended 16 bit index register rM to produce the final address 24810 in memory of the operand. 24811 24812'#XX' 24813 Immediate data XX. 24814 24815 24816File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 24817 248189.57.3 Assembler Directives for the Z8000 24819----------------------------------------- 24820 24821The Z8000 port of as includes additional assembler directives, for 24822compatibility with other Z8000 assemblers. These do not begin with '.' 24823(unlike the ordinary as directives). 24824 24825'segm' 24826'.z8001' 24827 Generate code for the segmented Z8001. 24828 24829'unsegm' 24830'.z8002' 24831 Generate code for the unsegmented Z8002. 24832 24833'name' 24834 Synonym for '.file' 24835 24836'global' 24837 Synonym for '.global' 24838 24839'wval' 24840 Synonym for '.word' 24841 24842'lval' 24843 Synonym for '.long' 24844 24845'bval' 24846 Synonym for '.byte' 24847 24848'sval' 24849 Assemble a string. 'sval' expects one string literal, delimited by 24850 single quotes. It assembles each byte of the string into 24851 consecutive addresses. You can use the escape sequence '%XX' 24852 (where XX represents a two-digit hexadecimal number) to represent 24853 the character whose ASCII value is XX. Use this feature to 24854 describe single quote and other characters that may not appear in 24855 string literals as themselves. For example, the C statement 24856 'char *a = "he said \"it's 50% off\"";' is represented in Z8000 24857 assembly language (shown with the assembler output in hex at the 24858 left) as 24859 24860 68652073 sval 'he said %22it%27s 50%25 off%22%00' 24861 61696420 24862 22697427 24863 73203530 24864 25206F66 24865 662200 24866 24867'rsect' 24868 synonym for '.section' 24869 24870'block' 24871 synonym for '.space' 24872 24873'even' 24874 special case of '.align'; aligns output to even byte boundary. 24875 24876 24877File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 24878 248799.57.4 Opcodes 24880-------------- 24881 24882For detailed information on the Z8000 machine instruction set, see 24883'Z8000 Technical Manual'. 24884 24885 The following table summarizes the opcodes and their arguments: 24886 24887 rs 16 bit source register 24888 rd 16 bit destination register 24889 rbs 8 bit source register 24890 rbd 8 bit destination register 24891 rrs 32 bit source register 24892 rrd 32 bit destination register 24893 rqs 64 bit source register 24894 rqd 64 bit destination register 24895 addr 16/24 bit address 24896 imm immediate data 24897 24898 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 24899 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 24900 add rd,@rs clrb rbd dab rbd 24901 add rd,addr com @rd dbjnz rbd,disp7 24902 add rd,addr(rs) com addr dec @rd,imm4m1 24903 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 24904 add rd,rs com rd dec addr,imm4m1 24905 addb rbd,@rs comb @rd dec rd,imm4m1 24906 addb rbd,addr comb addr decb @rd,imm4m1 24907 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 24908 addb rbd,imm8 comb rbd decb addr,imm4m1 24909 addb rbd,rbs comflg flags decb rbd,imm4m1 24910 addl rrd,@rs cp @rd,imm16 di i2 24911 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 24912 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 24913 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 24914 addl rrd,rrs cp rd,addr div rrd,imm16 24915 and rd,@rs cp rd,addr(rs) div rrd,rs 24916 and rd,addr cp rd,imm16 divl rqd,@rs 24917 and rd,addr(rs) cp rd,rs divl rqd,addr 24918 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 24919 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 24920 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 24921 andb rbd,addr cpb rbd,@rs djnz rd,disp7 24922 andb rbd,addr(rs) cpb rbd,addr ei i2 24923 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 24924 andb rbd,rbs cpb rbd,imm8 ex rd,addr 24925 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 24926 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 24927 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 24928 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 24929 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 24930 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 24931 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 24932 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 24933 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 24934 bitb rbd,rs cpl rrd,@rs ext8f imm8 24935 bpt cpl rrd,addr exts rrd 24936 call @rd cpl rrd,addr(rs) extsb rd 24937 call addr cpl rrd,imm32 extsl rqd 24938 call addr(rd) cpl rrd,rrs halt 24939 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 24940 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 24941 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 24942 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 24943 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 24944 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 24945 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 24946 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 24947 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 24948 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 24949 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 24950 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 24951 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 24952 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 24953 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 24954 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 24955 iret ldib @rd,@rs,rr neg addr(rd) 24956 jp cc,@rd ldir @rd,@rs,rr neg rd 24957 jp cc,addr ldirb @rd,@rs,rr negb @rd 24958 jp cc,addr(rd) ldk rd,imm4 negb addr 24959 jr cc,disp8 ldl @rd,rrs negb addr(rd) 24960 ld @rd,imm16 ldl addr(rd),rrs negb rbd 24961 ld @rd,rs ldl addr,rrs nop 24962 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 24963 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 24964 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 24965 ld addr,rs ldl rrd,addr or rd,imm16 24966 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 24967 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 24968 ld rd,@rs ldl rrd,rrs orb rbd,addr 24969 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 24970 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 24971 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 24972 ld rd,rs ldm addr(rd),rs,n out @rd,rs 24973 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 24974 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 24975 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 24976 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 24977 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 24978 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 24979 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 24980 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 24981 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 24982 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 24983 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 24984 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 24985 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 24986 ldb rbd,@rs mbit popl addr,@rs 24987 ldb rbd,addr mreq rd popl rrd,@rs 24988 ldb rbd,addr(rs) mres push @rd,@rs 24989 ldb rbd,imm8 mset push @rd,addr 24990 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 24991 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 24992 push @rd,rs set addr,imm4 subl rrd,imm32 24993 pushl @rd,@rs set rd,imm4 subl rrd,rrs 24994 pushl @rd,addr set rd,rs tcc cc,rd 24995 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 24996 pushl @rd,rrs setb addr(rd),imm4 test @rd 24997 res @rd,imm4 setb addr,imm4 test addr 24998 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 24999 res addr,imm4 setb rbd,rs test rd 25000 res rd,imm4 setflg imm4 testb @rd 25001 res rd,rs sinb rbd,imm16 testb addr 25002 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 25003 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 25004 resb addr,imm4 sindb @rd,@rs,rba testl @rd 25005 resb rbd,imm4 sinib @rd,@rs,ra testl addr 25006 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 25007 resflg imm4 sla rd,imm8 testl rrd 25008 ret cc slab rbd,imm8 trdb @rd,@rs,rba 25009 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 25010 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 25011 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 25012 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 25013 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 25014 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 25015 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 25016 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 25017 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 25018 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 25019 rsvd36 sra rd,imm8 tset rd 25020 rsvd38 srab rbd,imm8 tsetb @rd 25021 rsvd78 sral rrd,imm8 tsetb addr 25022 rsvd7e srl rd,imm8 tsetb addr(rd) 25023 rsvd9d srlb rbd,imm8 tsetb rbd 25024 rsvd9f srll rrd,imm8 xor rd,@rs 25025 rsvdb9 sub rd,@rs xor rd,addr 25026 rsvdbf sub rd,addr xor rd,addr(rs) 25027 sbc rd,rs sub rd,addr(rs) xor rd,imm16 25028 sbcb rbd,rbs sub rd,imm16 xor rd,rs 25029 sc imm8 sub rd,rs xorb rbd,@rs 25030 sda rd,rs subb rbd,@rs xorb rbd,addr 25031 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 25032 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 25033 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 25034 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 25035 sdll rrd,rs subl rrd,@rs 25036 set @rd,imm4 subl rrd,addr 25037 set addr(rd),imm4 subl rrd,addr(rs) 25038 25039 25040File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 25041 2504210 Reporting Bugs 25043***************** 25044 25045Your bug reports play an essential role in making 'as' reliable. 25046 25047 Reporting a bug may help you by bringing a solution to your problem, 25048or it may not. But in any case the principal function of a bug report 25049is to help the entire community by making the next version of 'as' work 25050better. Bug reports are your contribution to the maintenance of 'as'. 25051 25052 In order for a bug report to serve its purpose, you must include the 25053information that enables us to fix the bug. 25054 25055* Menu: 25056 25057* Bug Criteria:: Have you found a bug? 25058* Bug Reporting:: How to report bugs 25059 25060 25061File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 25062 2506310.1 Have You Found a Bug? 25064========================== 25065 25066If you are not sure whether you have found a bug, here are some 25067guidelines: 25068 25069 * If the assembler gets a fatal signal, for any input whatever, that 25070 is a 'as' bug. Reliable assemblers never crash. 25071 25072 * If 'as' produces an error message for valid input, that is a bug. 25073 25074 * If 'as' does not produce an error message for invalid input, that 25075 is a bug. However, you should note that your idea of "invalid 25076 input" might be our idea of "an extension" or "support for 25077 traditional practice". 25078 25079 * If you are an experienced user of assemblers, your suggestions for 25080 improvement of 'as' are welcome in any case. 25081 25082 25083File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 25084 2508510.2 How to Report Bugs 25086======================= 25087 25088A number of companies and individuals offer support for GNU products. 25089If you obtained 'as' from a support organization, we recommend you 25090contact that organization first. 25091 25092 You can find contact information for many support companies and 25093individuals in the file 'etc/SERVICE' in the GNU Emacs distribution. 25094 25095 In any event, we also recommend that you send bug reports for 'as' to 25096<http://www.sourceware.org/bugzilla/>. 25097 25098 The fundamental principle of reporting bugs usefully is this: *report 25099all the facts*. If you are not sure whether to state a fact or leave it 25100out, state it! 25101 25102 Often people omit facts because they think they know what causes the 25103problem and assume that some details do not matter. Thus, you might 25104assume that the name of a symbol you use in an example does not matter. 25105Well, probably it does not, but one cannot be sure. Perhaps the bug is 25106a stray memory reference which happens to fetch from the location where 25107that name is stored in memory; perhaps, if the name were different, the 25108contents of that location would fool the assembler into doing the right 25109thing despite the bug. Play it safe and give a specific, complete 25110example. That is the easiest thing for you to do, and the most helpful. 25111 25112 Keep in mind that the purpose of a bug report is to enable us to fix 25113the bug if it is new to us. Therefore, always write your bug reports on 25114the assumption that the bug has not been reported previously. 25115 25116 Sometimes people give a few sketchy facts and ask, "Does this ring a 25117bell?" This cannot help us fix a bug, so it is basically useless. We 25118respond by asking for enough details to enable us to investigate. You 25119might as well expedite matters by sending them to begin with. 25120 25121 To enable us to fix the bug, you should include all these things: 25122 25123 * The version of 'as'. 'as' announces it if you start it with the 25124 '--version' argument. 25125 25126 Without this, we will not know whether there is any point in 25127 looking for the bug in the current version of 'as'. 25128 25129 * Any patches you may have applied to the 'as' source. 25130 25131 * The type of machine you are using, and the operating system name 25132 and version number. 25133 25134 * What compiler (and its version) was used to compile 'as'--e.g. 25135 "'gcc-2.7'". 25136 25137 * The command arguments you gave the assembler to assemble your 25138 example and observe the bug. To guarantee you will not omit 25139 something important, list them all. A copy of the Makefile (or the 25140 output from make) is sufficient. 25141 25142 If we were to try to guess the arguments, we would probably guess 25143 wrong and then we might not encounter the bug. 25144 25145 * A complete input file that will reproduce the bug. If the bug is 25146 observed when the assembler is invoked via a compiler, send the 25147 assembler source, not the high level language source. Most 25148 compilers will produce the assembler source when run with the '-S' 25149 option. If you are using 'gcc', use the options '-v --save-temps'; 25150 this will save the assembler source in a file with an extension of 25151 '.s', and also show you exactly how 'as' is being run. 25152 25153 * A description of what behavior you observe that you believe is 25154 incorrect. For example, "It gets a fatal signal." 25155 25156 Of course, if the bug is that 'as' gets a fatal signal, then we 25157 will certainly notice it. But if the bug is incorrect output, we 25158 might not notice unless it is glaringly wrong. You might as well 25159 not give us a chance to make a mistake. 25160 25161 Even if the problem you experience is a fatal signal, you should 25162 still say so explicitly. Suppose something strange is going on, 25163 such as, your copy of 'as' is out of sync, or you have encountered 25164 a bug in the C library on your system. (This has happened!) Your 25165 copy might crash and ours would not. If you told us to expect a 25166 crash, then when ours fails to crash, we would know that the bug 25167 was not happening for us. If you had not told us to expect a 25168 crash, then we would not be able to draw any conclusion from our 25169 observations. 25170 25171 * If you wish to suggest changes to the 'as' source, send us context 25172 diffs, as generated by 'diff' with the '-u', '-c', or '-p' option. 25173 Always send diffs from the old file to the new file. If you even 25174 discuss something in the 'as' source, refer to it by context, not 25175 by line number. 25176 25177 The line numbers in our development sources will not match those in 25178 your sources. Your line numbers would convey no useful information 25179 to us. 25180 25181 Here are some things that are not necessary: 25182 25183 * A description of the envelope of the bug. 25184 25185 Often people who encounter a bug spend a lot of time investigating 25186 which changes to the input file will make the bug go away and which 25187 changes will not affect it. 25188 25189 This is often time consuming and not very useful, because the way 25190 we will find the bug is by running a single example under the 25191 debugger with breakpoints, not by pure deduction from a series of 25192 examples. We recommend that you save your time for something else. 25193 25194 Of course, if you can find a simpler example to report _instead_ of 25195 the original one, that is a convenience for us. Errors in the 25196 output will be easier to spot, running under the debugger will take 25197 less time, and so on. 25198 25199 However, simplification is not vital; if you do not want to do 25200 this, report the bug anyway and send us the entire test case you 25201 used. 25202 25203 * A patch for the bug. 25204 25205 A patch for the bug does help us if it is a good one. But do not 25206 omit the necessary information, such as the test case, on the 25207 assumption that a patch is all we need. We might see problems with 25208 your patch and decide to fix the problem another way, or we might 25209 not understand it at all. 25210 25211 Sometimes with a program as complicated as 'as' it is very hard to 25212 construct an example that will make the program follow a certain 25213 path through the code. If you do not send us the example, we will 25214 not be able to construct one, so we will not be able to verify that 25215 the bug is fixed. 25216 25217 And if we cannot understand what bug you are trying to fix, or why 25218 your patch should be an improvement, we will not install it. A 25219 test case will help us to understand. 25220 25221 * A guess about what the bug is or what it depends on. 25222 25223 Such guesses are usually wrong. Even we cannot guess right about 25224 such things without first using the debugger to find the facts. 25225 25226 25227File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 25228 2522911 Acknowledgements 25230******************* 25231 25232If you have contributed to GAS and your name isn't listed here, it is 25233not meant as a slight. We just don't know about it. Send mail to the 25234maintainer, and we'll correct the situation. Currently the maintainer 25235is Nick Clifton (email address 'nickc@redhat.com'). 25236 25237 Dean Elsner wrote the original GNU assembler for the VAX.(1) 25238 25239 Jay Fenlason maintained GAS for a while, adding support for 25240GDB-specific debug information and the 68k series machines, most of the 25241preprocessing pass, and extensive changes in 'messages.c', 25242'input-file.c', 'write.c'. 25243 25244 K. Richard Pixley maintained GAS for a while, adding various 25245enhancements and many bug fixes, including merging support for several 25246processors, breaking GAS up to handle multiple object file format back 25247ends (including heavy rewrite, testing, an integration of the coff and 25248b.out back ends), adding configuration including heavy testing and 25249verification of cross assemblers and file splits and renaming, converted 25250GAS to strictly ANSI C including full prototypes, added support for 25251m680[34]0 and cpu32, did considerable work on i960 including a COFF port 25252(including considerable amounts of reverse engineering), a SPARC opcode 25253file rewrite, DECstation, rs6000, and hp300hpux host ports, updated 25254"know" assertions and made them work, much other reorganization, 25255cleanup, and lint. 25256 25257 Ken Raeburn wrote the high-level BFD interface code to replace most 25258of the code in format-specific I/O modules. 25259 25260 The original VMS support was contributed by David L. Kashtan. Eric 25261Youngdale has done much work with it since. 25262 25263 The Intel 80386 machine description was written by Eliot Dresselhaus. 25264 25265 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 25266 25267 The Motorola 88k machine description was contributed by Devon Bowen 25268of Buffalo University and Torbjorn Granlund of the Swedish Institute of 25269Computer Science. 25270 25271 Keith Knowles at the Open Software Foundation wrote the original MIPS 25272back end ('tc-mips.c', 'tc-mips.h'), and contributed Rose format support 25273(which hasn't been merged in yet). Ralph Campbell worked with the MIPS 25274code to support a.out format. 25275 25276 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 25277tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 25278Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 25279end to use BFD for some low-level operations, for use with the H8/300 25280and AMD 29k targets. 25281 25282 John Gilmore built the AMD 29000 support, added '.include' support, 25283and simplified the configuration of which versions accept which 25284directives. He updated the 68k machine description so that Motorola's 25285opcodes always produced fixed-size instructions (e.g., 'jsr'), while 25286synthetic instructions remained shrinkable ('jbsr'). John fixed many 25287bugs, including true tested cross-compilation support, and one bug in 25288relaxation that took a week and required the proverbial one-bit fix. 25289 25290 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax 25291for the 68k, completed support for some COFF targets (68k, i386 SVR3, 25292and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the 25293initial RS/6000 and PowerPC assembler, and made a few other minor 25294patches. 25295 25296 Steve Chamberlain made GAS able to generate listings. 25297 25298 Hewlett-Packard contributed support for the HP9000/300. 25299 25300 Jeff Law wrote GAS and BFD support for the native HPPA object format 25301(SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF 25302object formats). This work was supported by both the Center for 25303Software Science at the University of Utah and Cygnus Support. 25304 25305 Support for ELF format files has been worked on by Mark Eichin of 25306Cygnus Support (original, incomplete implementation for SPARC), Pete 25307Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael 25308Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn 25309of Cygnus Support (sparc, and some initial 64-bit support). 25310 25311 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 25312architecture. 25313 25314 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 25315GAS and BFD support for openVMS/Alpha. 25316 25317 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 25318various tic* flavors. 25319 25320 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 25321Tensilica, Inc. added support for Xtensa processors. 25322 25323 Several engineers at Cygnus Support have also provided many small bug 25324fixes and configuration enhancements. 25325 25326 Jon Beniston added support for the Lattice Mico32 architecture. 25327 25328 Many others have contributed large or small bugfixes and 25329enhancements. If you have contributed significant work and are not 25330mentioned on this list, and want to be, let us know. Some of the 25331history has been lost; we are not intentionally leaving anyone out. 25332 25333 ---------- Footnotes ---------- 25334 25335 (1) Any more details? 25336 25337 25338File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 25339 25340Appendix A GNU Free Documentation License 25341***************************************** 25342 25343 Version 1.3, 3 November 2008 25344 25345 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 25346 <http://fsf.org/> 25347 25348 Everyone is permitted to copy and distribute verbatim copies 25349 of this license document, but changing it is not allowed. 25350 25351 0. PREAMBLE 25352 25353 The purpose of this License is to make a manual, textbook, or other 25354 functional and useful document "free" in the sense of freedom: to 25355 assure everyone the effective freedom to copy and redistribute it, 25356 with or without modifying it, either commercially or 25357 noncommercially. Secondarily, this License preserves for the 25358 author and publisher a way to get credit for their work, while not 25359 being considered responsible for modifications made by others. 25360 25361 This License is a kind of "copyleft", which means that derivative 25362 works of the document must themselves be free in the same sense. 25363 It complements the GNU General Public License, which is a copyleft 25364 license designed for free software. 25365 25366 We have designed this License in order to use it for manuals for 25367 free software, because free software needs free documentation: a 25368 free program should come with manuals providing the same freedoms 25369 that the software does. But this License is not limited to 25370 software manuals; it can be used for any textual work, regardless 25371 of subject matter or whether it is published as a printed book. We 25372 recommend this License principally for works whose purpose is 25373 instruction or reference. 25374 25375 1. APPLICABILITY AND DEFINITIONS 25376 25377 This License applies to any manual or other work, in any medium, 25378 that contains a notice placed by the copyright holder saying it can 25379 be distributed under the terms of this License. Such a notice 25380 grants a world-wide, royalty-free license, unlimited in duration, 25381 to use that work under the conditions stated herein. The 25382 "Document", below, refers to any such manual or work. Any member 25383 of the public is a licensee, and is addressed as "you". You accept 25384 the license if you copy, modify or distribute the work in a way 25385 requiring permission under copyright law. 25386 25387 A "Modified Version" of the Document means any work containing the 25388 Document or a portion of it, either copied verbatim, or with 25389 modifications and/or translated into another language. 25390 25391 A "Secondary Section" is a named appendix or a front-matter section 25392 of the Document that deals exclusively with the relationship of the 25393 publishers or authors of the Document to the Document's overall 25394 subject (or to related matters) and contains nothing that could 25395 fall directly within that overall subject. (Thus, if the Document 25396 is in part a textbook of mathematics, a Secondary Section may not 25397 explain any mathematics.) The relationship could be a matter of 25398 historical connection with the subject or with related matters, or 25399 of legal, commercial, philosophical, ethical or political position 25400 regarding them. 25401 25402 The "Invariant Sections" are certain Secondary Sections whose 25403 titles are designated, as being those of Invariant Sections, in the 25404 notice that says that the Document is released under this License. 25405 If a section does not fit the above definition of Secondary then it 25406 is not allowed to be designated as Invariant. The Document may 25407 contain zero Invariant Sections. If the Document does not identify 25408 any Invariant Sections then there are none. 25409 25410 The "Cover Texts" are certain short passages of text that are 25411 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 25412 that says that the Document is released under this License. A 25413 Front-Cover Text may be at most 5 words, and a Back-Cover Text may 25414 be at most 25 words. 25415 25416 A "Transparent" copy of the Document means a machine-readable copy, 25417 represented in a format whose specification is available to the 25418 general public, that is suitable for revising the document 25419 straightforwardly with generic text editors or (for images composed 25420 of pixels) generic paint programs or (for drawings) some widely 25421 available drawing editor, and that is suitable for input to text 25422 formatters or for automatic translation to a variety of formats 25423 suitable for input to text formatters. A copy made in an otherwise 25424 Transparent file format whose markup, or absence of markup, has 25425 been arranged to thwart or discourage subsequent modification by 25426 readers is not Transparent. An image format is not Transparent if 25427 used for any substantial amount of text. A copy that is not 25428 "Transparent" is called "Opaque". 25429 25430 Examples of suitable formats for Transparent copies include plain 25431 ASCII without markup, Texinfo input format, LaTeX input format, 25432 SGML or XML using a publicly available DTD, and standard-conforming 25433 simple HTML, PostScript or PDF designed for human modification. 25434 Examples of transparent image formats include PNG, XCF and JPG. 25435 Opaque formats include proprietary formats that can be read and 25436 edited only by proprietary word processors, SGML or XML for which 25437 the DTD and/or processing tools are not generally available, and 25438 the machine-generated HTML, PostScript or PDF produced by some word 25439 processors for output purposes only. 25440 25441 The "Title Page" means, for a printed book, the title page itself, 25442 plus such following pages as are needed to hold, legibly, the 25443 material this License requires to appear in the title page. For 25444 works in formats which do not have any title page as such, "Title 25445 Page" means the text near the most prominent appearance of the 25446 work's title, preceding the beginning of the body of the text. 25447 25448 The "publisher" means any person or entity that distributes copies 25449 of the Document to the public. 25450 25451 A section "Entitled XYZ" means a named subunit of the Document 25452 whose title either is precisely XYZ or contains XYZ in parentheses 25453 following text that translates XYZ in another language. (Here XYZ 25454 stands for a specific section name mentioned below, such as 25455 "Acknowledgements", "Dedications", "Endorsements", or "History".) 25456 To "Preserve the Title" of such a section when you modify the 25457 Document means that it remains a section "Entitled XYZ" according 25458 to this definition. 25459 25460 The Document may include Warranty Disclaimers next to the notice 25461 which states that this License applies to the Document. These 25462 Warranty Disclaimers are considered to be included by reference in 25463 this License, but only as regards disclaiming warranties: any other 25464 implication that these Warranty Disclaimers may have is void and 25465 has no effect on the meaning of this License. 25466 25467 2. VERBATIM COPYING 25468 25469 You may copy and distribute the Document in any medium, either 25470 commercially or noncommercially, provided that this License, the 25471 copyright notices, and the license notice saying this License 25472 applies to the Document are reproduced in all copies, and that you 25473 add no other conditions whatsoever to those of this License. You 25474 may not use technical measures to obstruct or control the reading 25475 or further copying of the copies you make or distribute. However, 25476 you may accept compensation in exchange for copies. If you 25477 distribute a large enough number of copies you must also follow the 25478 conditions in section 3. 25479 25480 You may also lend copies, under the same conditions stated above, 25481 and you may publicly display copies. 25482 25483 3. COPYING IN QUANTITY 25484 25485 If you publish printed copies (or copies in media that commonly 25486 have printed covers) of the Document, numbering more than 100, and 25487 the Document's license notice requires Cover Texts, you must 25488 enclose the copies in covers that carry, clearly and legibly, all 25489 these Cover Texts: Front-Cover Texts on the front cover, and 25490 Back-Cover Texts on the back cover. Both covers must also clearly 25491 and legibly identify you as the publisher of these copies. The 25492 front cover must present the full title with all words of the title 25493 equally prominent and visible. You may add other material on the 25494 covers in addition. Copying with changes limited to the covers, as 25495 long as they preserve the title of the Document and satisfy these 25496 conditions, can be treated as verbatim copying in other respects. 25497 25498 If the required texts for either cover are too voluminous to fit 25499 legibly, you should put the first ones listed (as many as fit 25500 reasonably) on the actual cover, and continue the rest onto 25501 adjacent pages. 25502 25503 If you publish or distribute Opaque copies of the Document 25504 numbering more than 100, you must either include a machine-readable 25505 Transparent copy along with each Opaque copy, or state in or with 25506 each Opaque copy a computer-network location from which the general 25507 network-using public has access to download using public-standard 25508 network protocols a complete Transparent copy of the Document, free 25509 of added material. If you use the latter option, you must take 25510 reasonably prudent steps, when you begin distribution of Opaque 25511 copies in quantity, to ensure that this Transparent copy will 25512 remain thus accessible at the stated location until at least one 25513 year after the last time you distribute an Opaque copy (directly or 25514 through your agents or retailers) of that edition to the public. 25515 25516 It is requested, but not required, that you contact the authors of 25517 the Document well before redistributing any large number of copies, 25518 to give them a chance to provide you with an updated version of the 25519 Document. 25520 25521 4. MODIFICATIONS 25522 25523 You may copy and distribute a Modified Version of the Document 25524 under the conditions of sections 2 and 3 above, provided that you 25525 release the Modified Version under precisely this License, with the 25526 Modified Version filling the role of the Document, thus licensing 25527 distribution and modification of the Modified Version to whoever 25528 possesses a copy of it. In addition, you must do these things in 25529 the Modified Version: 25530 25531 A. Use in the Title Page (and on the covers, if any) a title 25532 distinct from that of the Document, and from those of previous 25533 versions (which should, if there were any, be listed in the 25534 History section of the Document). You may use the same title 25535 as a previous version if the original publisher of that 25536 version gives permission. 25537 25538 B. List on the Title Page, as authors, one or more persons or 25539 entities responsible for authorship of the modifications in 25540 the Modified Version, together with at least five of the 25541 principal authors of the Document (all of its principal 25542 authors, if it has fewer than five), unless they release you 25543 from this requirement. 25544 25545 C. State on the Title page the name of the publisher of the 25546 Modified Version, as the publisher. 25547 25548 D. Preserve all the copyright notices of the Document. 25549 25550 E. Add an appropriate copyright notice for your modifications 25551 adjacent to the other copyright notices. 25552 25553 F. Include, immediately after the copyright notices, a license 25554 notice giving the public permission to use the Modified 25555 Version under the terms of this License, in the form shown in 25556 the Addendum below. 25557 25558 G. Preserve in that license notice the full lists of Invariant 25559 Sections and required Cover Texts given in the Document's 25560 license notice. 25561 25562 H. Include an unaltered copy of this License. 25563 25564 I. Preserve the section Entitled "History", Preserve its Title, 25565 and add to it an item stating at least the title, year, new 25566 authors, and publisher of the Modified Version as given on the 25567 Title Page. If there is no section Entitled "History" in the 25568 Document, create one stating the title, year, authors, and 25569 publisher of the Document as given on its Title Page, then add 25570 an item describing the Modified Version as stated in the 25571 previous sentence. 25572 25573 J. Preserve the network location, if any, given in the Document 25574 for public access to a Transparent copy of the Document, and 25575 likewise the network locations given in the Document for 25576 previous versions it was based on. These may be placed in the 25577 "History" section. You may omit a network location for a work 25578 that was published at least four years before the Document 25579 itself, or if the original publisher of the version it refers 25580 to gives permission. 25581 25582 K. For any section Entitled "Acknowledgements" or "Dedications", 25583 Preserve the Title of the section, and preserve in the section 25584 all the substance and tone of each of the contributor 25585 acknowledgements and/or dedications given therein. 25586 25587 L. Preserve all the Invariant Sections of the Document, unaltered 25588 in their text and in their titles. Section numbers or the 25589 equivalent are not considered part of the section titles. 25590 25591 M. Delete any section Entitled "Endorsements". Such a section 25592 may not be included in the Modified Version. 25593 25594 N. Do not retitle any existing section to be Entitled 25595 "Endorsements" or to conflict in title with any Invariant 25596 Section. 25597 25598 O. Preserve any Warranty Disclaimers. 25599 25600 If the Modified Version includes new front-matter sections or 25601 appendices that qualify as Secondary Sections and contain no 25602 material copied from the Document, you may at your option designate 25603 some or all of these sections as invariant. To do this, add their 25604 titles to the list of Invariant Sections in the Modified Version's 25605 license notice. These titles must be distinct from any other 25606 section titles. 25607 25608 You may add a section Entitled "Endorsements", provided it contains 25609 nothing but endorsements of your Modified Version by various 25610 parties--for example, statements of peer review or that the text 25611 has been approved by an organization as the authoritative 25612 definition of a standard. 25613 25614 You may add a passage of up to five words as a Front-Cover Text, 25615 and a passage of up to 25 words as a Back-Cover Text, to the end of 25616 the list of Cover Texts in the Modified Version. Only one passage 25617 of Front-Cover Text and one of Back-Cover Text may be added by (or 25618 through arrangements made by) any one entity. If the Document 25619 already includes a cover text for the same cover, previously added 25620 by you or by arrangement made by the same entity you are acting on 25621 behalf of, you may not add another; but you may replace the old 25622 one, on explicit permission from the previous publisher that added 25623 the old one. 25624 25625 The author(s) and publisher(s) of the Document do not by this 25626 License give permission to use their names for publicity for or to 25627 assert or imply endorsement of any Modified Version. 25628 25629 5. COMBINING DOCUMENTS 25630 25631 You may combine the Document with other documents released under 25632 this License, under the terms defined in section 4 above for 25633 modified versions, provided that you include in the combination all 25634 of the Invariant Sections of all of the original documents, 25635 unmodified, and list them all as Invariant Sections of your 25636 combined work in its license notice, and that you preserve all 25637 their Warranty Disclaimers. 25638 25639 The combined work need only contain one copy of this License, and 25640 multiple identical Invariant Sections may be replaced with a single 25641 copy. If there are multiple Invariant Sections with the same name 25642 but different contents, make the title of each such section unique 25643 by adding at the end of it, in parentheses, the name of the 25644 original author or publisher of that section if known, or else a 25645 unique number. Make the same adjustment to the section titles in 25646 the list of Invariant Sections in the license notice of the 25647 combined work. 25648 25649 In the combination, you must combine any sections Entitled 25650 "History" in the various original documents, forming one section 25651 Entitled "History"; likewise combine any sections Entitled 25652 "Acknowledgements", and any sections Entitled "Dedications". You 25653 must delete all sections Entitled "Endorsements." 25654 25655 6. COLLECTIONS OF DOCUMENTS 25656 25657 You may make a collection consisting of the Document and other 25658 documents released under this License, and replace the individual 25659 copies of this License in the various documents with a single copy 25660 that is included in the collection, provided that you follow the 25661 rules of this License for verbatim copying of each of the documents 25662 in all other respects. 25663 25664 You may extract a single document from such a collection, and 25665 distribute it individually under this License, provided you insert 25666 a copy of this License into the extracted document, and follow this 25667 License in all other respects regarding verbatim copying of that 25668 document. 25669 25670 7. AGGREGATION WITH INDEPENDENT WORKS 25671 25672 A compilation of the Document or its derivatives with other 25673 separate and independent documents or works, in or on a volume of a 25674 storage or distribution medium, is called an "aggregate" if the 25675 copyright resulting from the compilation is not used to limit the 25676 legal rights of the compilation's users beyond what the individual 25677 works permit. When the Document is included in an aggregate, this 25678 License does not apply to the other works in the aggregate which 25679 are not themselves derivative works of the Document. 25680 25681 If the Cover Text requirement of section 3 is applicable to these 25682 copies of the Document, then if the Document is less than one half 25683 of the entire aggregate, the Document's Cover Texts may be placed 25684 on covers that bracket the Document within the aggregate, or the 25685 electronic equivalent of covers if the Document is in electronic 25686 form. Otherwise they must appear on printed covers that bracket 25687 the whole aggregate. 25688 25689 8. TRANSLATION 25690 25691 Translation is considered a kind of modification, so you may 25692 distribute translations of the Document under the terms of section 25693 4. Replacing Invariant Sections with translations requires special 25694 permission from their copyright holders, but you may include 25695 translations of some or all Invariant Sections in addition to the 25696 original versions of these Invariant Sections. You may include a 25697 translation of this License, and all the license notices in the 25698 Document, and any Warranty Disclaimers, provided that you also 25699 include the original English version of this License and the 25700 original versions of those notices and disclaimers. In case of a 25701 disagreement between the translation and the original version of 25702 this License or a notice or disclaimer, the original version will 25703 prevail. 25704 25705 If a section in the Document is Entitled "Acknowledgements", 25706 "Dedications", or "History", the requirement (section 4) to 25707 Preserve its Title (section 1) will typically require changing the 25708 actual title. 25709 25710 9. TERMINATION 25711 25712 You may not copy, modify, sublicense, or distribute the Document 25713 except as expressly provided under this License. Any attempt 25714 otherwise to copy, modify, sublicense, or distribute it is void, 25715 and will automatically terminate your rights under this License. 25716 25717 However, if you cease all violation of this License, then your 25718 license from a particular copyright holder is reinstated (a) 25719 provisionally, unless and until the copyright holder explicitly and 25720 finally terminates your license, and (b) permanently, if the 25721 copyright holder fails to notify you of the violation by some 25722 reasonable means prior to 60 days after the cessation. 25723 25724 Moreover, your license from a particular copyright holder is 25725 reinstated permanently if the copyright holder notifies you of the 25726 violation by some reasonable means, this is the first time you have 25727 received notice of violation of this License (for any work) from 25728 that copyright holder, and you cure the violation prior to 30 days 25729 after your receipt of the notice. 25730 25731 Termination of your rights under this section does not terminate 25732 the licenses of parties who have received copies or rights from you 25733 under this License. If your rights have been terminated and not 25734 permanently reinstated, receipt of a copy of some or all of the 25735 same material does not give you any rights to use it. 25736 25737 10. FUTURE REVISIONS OF THIS LICENSE 25738 25739 The Free Software Foundation may publish new, revised versions of 25740 the GNU Free Documentation License from time to time. Such new 25741 versions will be similar in spirit to the present version, but may 25742 differ in detail to address new problems or concerns. See 25743 <http://www.gnu.org/copyleft/>. 25744 25745 Each version of the License is given a distinguishing version 25746 number. If the Document specifies that a particular numbered 25747 version of this License "or any later version" applies to it, you 25748 have the option of following the terms and conditions either of 25749 that specified version or of any later version that has been 25750 published (not as a draft) by the Free Software Foundation. If the 25751 Document does not specify a version number of this License, you may 25752 choose any version ever published (not as a draft) by the Free 25753 Software Foundation. If the Document specifies that a proxy can 25754 decide which future versions of this License can be used, that 25755 proxy's public statement of acceptance of a version permanently 25756 authorizes you to choose that version for the Document. 25757 25758 11. RELICENSING 25759 25760 "Massive Multiauthor Collaboration Site" (or "MMC Site") means any 25761 World Wide Web server that publishes copyrightable works and also 25762 provides prominent facilities for anybody to edit those works. A 25763 public wiki that anybody can edit is an example of such a server. 25764 A "Massive Multiauthor Collaboration" (or "MMC") contained in the 25765 site means any set of copyrightable works thus published on the MMC 25766 site. 25767 25768 "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0 25769 license published by Creative Commons Corporation, a not-for-profit 25770 corporation with a principal place of business in San Francisco, 25771 California, as well as future copyleft versions of that license 25772 published by that same organization. 25773 25774 "Incorporate" means to publish or republish a Document, in whole or 25775 in part, as part of another Document. 25776 25777 An MMC is "eligible for relicensing" if it is licensed under this 25778 License, and if all works that were first published under this 25779 License somewhere other than this MMC, and subsequently 25780 incorporated in whole or in part into the MMC, (1) had no cover 25781 texts or invariant sections, and (2) were thus incorporated prior 25782 to November 1, 2008. 25783 25784 The operator of an MMC Site may republish an MMC contained in the 25785 site under CC-BY-SA on the same site at any time before August 1, 25786 2009, provided the MMC is eligible for relicensing. 25787 25788ADDENDUM: How to use this License for your documents 25789==================================================== 25790 25791To use this License in a document you have written, include a copy of 25792the License in the document and put the following copyright and license 25793notices just after the title page: 25794 25795 Copyright (C) YEAR YOUR NAME. 25796 Permission is granted to copy, distribute and/or modify this document 25797 under the terms of the GNU Free Documentation License, Version 1.3 25798 or any later version published by the Free Software Foundation; 25799 with no Invariant Sections, no Front-Cover Texts, and no Back-Cover 25800 Texts. A copy of the license is included in the section entitled ``GNU 25801 Free Documentation License''. 25802 25803 If you have Invariant Sections, Front-Cover Texts and Back-Cover 25804Texts, replace the "with...Texts." line with this: 25805 25806 with the Invariant Sections being LIST THEIR TITLES, with 25807 the Front-Cover Texts being LIST, and with the Back-Cover Texts 25808 being LIST. 25809 25810 If you have Invariant Sections without Cover Texts, or some other 25811combination of the three, merge those two alternatives to suit the 25812situation. 25813 25814 If your document contains nontrivial examples of program code, we 25815recommend releasing these examples in parallel under your choice of free 25816software license, such as the GNU General Public License, to permit 25817their use in free software. 25818 25819 25820File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 25821 25822AS Index 25823******** 25824 25825�[index�] 25826* Menu: 25827 25828* \" (doublequote character): Strings. (line 43) 25829* \b (backspace character): Strings. (line 15) 25830* \DDD (octal character code): Strings. (line 30) 25831* \f (formfeed character): Strings. (line 18) 25832* \n (newline character): Strings. (line 21) 25833* \r (carriage return character): Strings. (line 24) 25834* \t (tab): Strings. (line 27) 25835* \XD... (hex character code): Strings. (line 36) 25836* \\ (\ character): Strings. (line 40) 25837* #: Comments. (line 33) 25838* #APP: Preprocessing. (line 26) 25839* #NO_APP: Preprocessing. (line 26) 25840* $ in symbol names: D10V-Chars. (line 46) 25841* $ in symbol names <1>: D30V-Chars. (line 70) 25842* $ in symbol names <2>: Meta-Chars. (line 10) 25843* $ in symbol names <3>: SH-Chars. (line 15) 25844* $a: ARM Mapping Symbols. 25845 (line 9) 25846* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 25847* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 25848* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 25849* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 25850* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 25851* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 25852* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 25853* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 25854* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 25855* $d: AArch64 Mapping Symbols. 25856 (line 12) 25857* $d <1>: ARM Mapping Symbols. 25858 (line 15) 25859* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 25860* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 25861* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 25862* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 25863* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 25864* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 25865* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 25866* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 25867* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 25868* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 25869* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 25870* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 25871* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 25872* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 25873* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 25874* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 25875* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 25876* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 25877* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 25878* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 25879* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 25880* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 25881* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 25882* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 25883* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 25884* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 25885* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 25886* $t: ARM Mapping Symbols. 25887 (line 12) 25888* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 25889* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 25890* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 25891* $x: AArch64 Mapping Symbols. 25892 (line 9) 25893* %gp: RX-Modifiers. (line 6) 25894* %gpreg: RX-Modifiers. (line 22) 25895* %pidreg: RX-Modifiers. (line 25) 25896* -+ option, VAX/VMS: VAX-Opts. (line 71) 25897* --: Command Line. (line 10) 25898* --32 option, i386: i386-Options. (line 8) 25899* --32 option, x86-64: i386-Options. (line 8) 25900* --64 option, i386: i386-Options. (line 8) 25901* --64 option, x86-64: i386-Options. (line 8) 25902* --absolute-literals: Xtensa Options. (line 39) 25903* --allow-reg-prefix: SH Options. (line 9) 25904* --alternate: alternate. (line 6) 25905* --auto-litpools: Xtensa Options. (line 22) 25906* --base-size-default-16: M68K-Opts. (line 66) 25907* --base-size-default-32: M68K-Opts. (line 66) 25908* --big: SH Options. (line 9) 25909* --bitwise-or option, M680x0: M68K-Opts. (line 59) 25910* --compress-debug-sections= option: Overview. (line 386) 25911* --disp-size-default-16: M68K-Opts. (line 75) 25912* --disp-size-default-32: M68K-Opts. (line 75) 25913* --divide option, i386: i386-Options. (line 25) 25914* --dsp: SH Options. (line 9) 25915* --emulation=crisaout command-line option, CRIS: CRIS-Opts. (line 9) 25916* --emulation=criself command-line option, CRIS: CRIS-Opts. (line 9) 25917* --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 25918* --fatal-warnings: W. (line 16) 25919* --fdpic: SH Options. (line 31) 25920* --fix-v4bx command-line option, ARM: ARM Options. (line 370) 25921* --fixed-special-register-names command-line option, MMIX: MMIX-Opts. 25922 (line 8) 25923* --force-long-branches: M68HC11-Opts. (line 81) 25924* --generate-example: M68HC11-Opts. (line 98) 25925* --globalize-symbols command-line option, MMIX: MMIX-Opts. (line 12) 25926* --gnu-syntax command-line option, MMIX: MMIX-Opts. (line 16) 25927* --linker-allocated-gregs command-line option, MMIX: MMIX-Opts. 25928 (line 67) 25929* --listing-cont-lines: listing. (line 34) 25930* --listing-lhs-width: listing. (line 16) 25931* --listing-lhs-width2: listing. (line 21) 25932* --listing-rhs-width: listing. (line 28) 25933* --little: SH Options. (line 9) 25934* --longcalls: Xtensa Options. (line 53) 25935* --march=ARCHITECTURE command-line option, CRIS: CRIS-Opts. (line 34) 25936* --MD: MD. (line 6) 25937* --mul-bug-abort command-line option, CRIS: CRIS-Opts. (line 63) 25938* --no-absolute-literals: Xtensa Options. (line 39) 25939* --no-auto-litpools: Xtensa Options. (line 22) 25940* --no-expand command-line option, MMIX: MMIX-Opts. (line 31) 25941* --no-longcalls: Xtensa Options. (line 53) 25942* --no-merge-gregs command-line option, MMIX: MMIX-Opts. (line 36) 25943* --no-mul-bug-abort command-line option, CRIS: CRIS-Opts. (line 63) 25944* --no-pad-sections: no-pad-sections. (line 6) 25945* --no-predefined-syms command-line option, MMIX: MMIX-Opts. (line 22) 25946* --no-pushj-stubs command-line option, MMIX: MMIX-Opts. (line 54) 25947* --no-stubs command-line option, MMIX: MMIX-Opts. (line 54) 25948* --no-target-align: Xtensa Options. (line 46) 25949* --no-text-section-literals: Xtensa Options. (line 7) 25950* --no-trampolines: Xtensa Options. (line 74) 25951* --no-transform: Xtensa Options. (line 62) 25952* --no-underscore command-line option, CRIS: CRIS-Opts. (line 15) 25953* --no-warn: W. (line 11) 25954* --pcrel: M68K-Opts. (line 87) 25955* --pic command-line option, CRIS: CRIS-Opts. (line 27) 25956* --print-insn-syntax: M68HC11-Opts. (line 87) 25957* --print-insn-syntax <1>: XGATE-Opts. (line 25) 25958* --print-opcodes: M68HC11-Opts. (line 91) 25959* --print-opcodes <1>: XGATE-Opts. (line 29) 25960* --register-prefix-optional option, M680x0: M68K-Opts. (line 46) 25961* --relax: SH Options. (line 9) 25962* --relax command-line option, MMIX: MMIX-Opts. (line 19) 25963* --rename-section: Xtensa Options. (line 70) 25964* --renesas: SH Options. (line 9) 25965* --sectname-subst: Section. (line 71) 25966* --short-branches: M68HC11-Opts. (line 67) 25967* --small: SH Options. (line 9) 25968* --statistics: statistics. (line 6) 25969* --strict-direct-mode: M68HC11-Opts. (line 57) 25970* --target-align: Xtensa Options. (line 46) 25971* --text-section-literals: Xtensa Options. (line 7) 25972* --traditional-format: traditional-format. (line 6) 25973* --trampolines: Xtensa Options. (line 74) 25974* --transform: Xtensa Options. (line 62) 25975* --underscore command-line option, CRIS: CRIS-Opts. (line 15) 25976* --warn: W. (line 19) 25977* --x32 option, i386: i386-Options. (line 8) 25978* --x32 option, x86-64: i386-Options. (line 8) 25979* --xgate-ramoffset: M68HC11-Opts. (line 36) 25980* -1 option, VAX/VMS: VAX-Opts. (line 77) 25981* -32addr command-line option, Alpha: Alpha Options. (line 57) 25982* -a: a. (line 6) 25983* -ac: a. (line 6) 25984* -ad: a. (line 6) 25985* -ag: a. (line 6) 25986* -ah: a. (line 6) 25987* -al: a. (line 6) 25988* -Aleon: Sparc-Opts. (line 25) 25989* -an: a. (line 6) 25990* -as: a. (line 6) 25991* -Asparc: Sparc-Opts. (line 25) 25992* -Asparcfmaf: Sparc-Opts. (line 25) 25993* -Asparcima: Sparc-Opts. (line 25) 25994* -Asparclet: Sparc-Opts. (line 25) 25995* -Asparclite: Sparc-Opts. (line 25) 25996* -Asparcvis: Sparc-Opts. (line 25) 25997* -Asparcvis2: Sparc-Opts. (line 25) 25998* -Asparcvis3: Sparc-Opts. (line 25) 25999* -Asparcvis3r: Sparc-Opts. (line 25) 26000* -Av6: Sparc-Opts. (line 25) 26001* -Av7: Sparc-Opts. (line 25) 26002* -Av8: Sparc-Opts. (line 25) 26003* -Av9: Sparc-Opts. (line 25) 26004* -Av9a: Sparc-Opts. (line 25) 26005* -Av9b: Sparc-Opts. (line 25) 26006* -Av9c: Sparc-Opts. (line 25) 26007* -Av9d: Sparc-Opts. (line 25) 26008* -Av9e: Sparc-Opts. (line 25) 26009* -Av9m: Sparc-Opts. (line 25) 26010* -Av9v: Sparc-Opts. (line 25) 26011* -big option, M32R: M32R-Opts. (line 35) 26012* -colonless command-line option, Z80: Z80 Options. (line 30) 26013* -D: D. (line 6) 26014* -D, ignored on VAX: VAX-Opts. (line 11) 26015* -d, VAX option: VAX-Opts. (line 16) 26016* -eabi= command-line option, ARM: ARM Options. (line 346) 26017* -EB command-line option, AArch64: AArch64 Options. (line 6) 26018* -EB command-line option, ARC: ARC Options. (line 84) 26019* -EB command-line option, ARM: ARM Options. (line 351) 26020* -EB command-line option, BPF: BPF Options. (line 6) 26021* -EB option (MIPS): MIPS Options. (line 13) 26022* -EB option, M32R: M32R-Opts. (line 39) 26023* -EB option, TILE-Gx: TILE-Gx Options. (line 11) 26024* -EL command-line option, AArch64: AArch64 Options. (line 10) 26025* -EL command-line option, ARC: ARC Options. (line 88) 26026* -EL command-line option, ARM: ARM Options. (line 362) 26027* -EL command-line option, BPF: BPF Options. (line 10) 26028* -EL option (MIPS): MIPS Options. (line 13) 26029* -EL option, M32R: M32R-Opts. (line 32) 26030* -EL option, TILE-Gx: TILE-Gx Options. (line 11) 26031* -ez80 command-line option, Z80: Z80 Options. (line 19) 26032* -ez80-adl command-line option, Z80: Z80 Options. (line 22) 26033* -f: f. (line 6) 26034* -F command-line option, Alpha: Alpha Options. (line 57) 26035* -fno-pic option, RISC-V: RISC-V-Options. (line 12) 26036* -fp-d command-line option, Z80: Z80 Options. (line 41) 26037* -fp-s command-line option, Z80: Z80 Options. (line 37) 26038* -fpic option, RISC-V: RISC-V-Options. (line 8) 26039* -full command-line option, Z80: Z80 Options. (line 48) 26040* -g command-line option, Alpha: Alpha Options. (line 47) 26041* -G command-line option, Alpha: Alpha Options. (line 53) 26042* -G option (MIPS): MIPS Options. (line 8) 26043* -h option, VAX/VMS: VAX-Opts. (line 45) 26044* -H option, VAX/VMS: VAX-Opts. (line 81) 26045* -I PATH: I. (line 6) 26046* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 26047* -Ip option, M32RX: M32R-Opts. (line 97) 26048* -J, ignored on VAX: VAX-Opts. (line 27) 26049* -K: K. (line 6) 26050* -k command-line option, ARM: ARM Options. (line 366) 26051* -KPIC option, M32R: M32R-Opts. (line 42) 26052* -KPIC option, MIPS: MIPS Options. (line 21) 26053* -L: L. (line 6) 26054* -l option, M680x0: M68K-Opts. (line 34) 26055* -little option, M32R: M32R-Opts. (line 27) 26056* -local-prefix command-line option, Z80: Z80 Options. (line 25) 26057* -M: M. (line 6) 26058* -m11/03: PDP-11-Options. (line 140) 26059* -m11/04: PDP-11-Options. (line 143) 26060* -m11/05: PDP-11-Options. (line 146) 26061* -m11/10: PDP-11-Options. (line 146) 26062* -m11/15: PDP-11-Options. (line 149) 26063* -m11/20: PDP-11-Options. (line 149) 26064* -m11/21: PDP-11-Options. (line 152) 26065* -m11/23: PDP-11-Options. (line 155) 26066* -m11/24: PDP-11-Options. (line 155) 26067* -m11/34: PDP-11-Options. (line 158) 26068* -m11/34a: PDP-11-Options. (line 161) 26069* -m11/35: PDP-11-Options. (line 164) 26070* -m11/40: PDP-11-Options. (line 164) 26071* -m11/44: PDP-11-Options. (line 167) 26072* -m11/45: PDP-11-Options. (line 170) 26073* -m11/50: PDP-11-Options. (line 170) 26074* -m11/53: PDP-11-Options. (line 173) 26075* -m11/55: PDP-11-Options. (line 170) 26076* -m11/60: PDP-11-Options. (line 176) 26077* -m11/70: PDP-11-Options. (line 170) 26078* -m11/73: PDP-11-Options. (line 173) 26079* -m11/83: PDP-11-Options. (line 173) 26080* -m11/84: PDP-11-Options. (line 173) 26081* -m11/93: PDP-11-Options. (line 173) 26082* -m11/94: PDP-11-Options. (line 173) 26083* -m16c option, M16C: M32C-Opts. (line 12) 26084* -m31 option, s390: s390 Options. (line 8) 26085* -m32 option, TILE-Gx: TILE-Gx Options. (line 8) 26086* -m32bit-doubles: RX-Opts. (line 9) 26087* -m32c option, M32C: M32C-Opts. (line 9) 26088* -m32r option, M32R: M32R-Opts. (line 21) 26089* -m32rx option, M32R2: M32R-Opts. (line 17) 26090* -m32rx option, M32RX: M32R-Opts. (line 9) 26091* -m4byte-align command-line option, V850: V850 Options. (line 90) 26092* -m64 option, s390: s390 Options. (line 8) 26093* -m64 option, TILE-Gx: TILE-Gx Options. (line 8) 26094* -m64bit-doubles: RX-Opts. (line 15) 26095* -m68000 and related options: M68K-Opts. (line 99) 26096* -m68hc11: M68HC11-Opts. (line 9) 26097* -m68hc12: M68HC11-Opts. (line 14) 26098* -m68hcs12: M68HC11-Opts. (line 21) 26099* -m8byte-align command-line option, V850: V850 Options. (line 86) 26100* -mabi= command-line option, AArch64: AArch64 Options. (line 14) 26101* -mabi=ABI option, RISC-V: RISC-V-Options. (line 19) 26102* -madd-bnd-prefix option, i386: i386-Options. (line 154) 26103* -madd-bnd-prefix option, x86-64: i386-Options. (line 154) 26104* -malign-branch-boundary= option, i386: i386-Options. (line 200) 26105* -malign-branch-boundary= option, x86-64: i386-Options. (line 200) 26106* -malign-branch-prefix-size= option, i386: i386-Options. (line 215) 26107* -malign-branch-prefix-size= option, x86-64: i386-Options. (line 215) 26108* -malign-branch= option, i386: i386-Options. (line 207) 26109* -malign-branch= option, x86-64: i386-Options. (line 207) 26110* -mall: PDP-11-Options. (line 26) 26111* -mall-enabled command-line option, LM32: LM32 Options. (line 30) 26112* -mall-extensions: PDP-11-Options. (line 26) 26113* -mall-opcodes command-line option, AVR: AVR Options. (line 111) 26114* -mamd64 option, x86-64: i386-Options. (line 245) 26115* -mapcs-26 command-line option, ARM: ARM Options. (line 318) 26116* -mapcs-32 command-line option, ARM: ARM Options. (line 318) 26117* -mapcs-float command-line option, ARM: ARM Options. (line 332) 26118* -mapcs-reentrant command-line option, ARM: ARM Options. (line 337) 26119* -march= command-line option, AArch64: AArch64 Options. (line 42) 26120* -march= command-line option, ARM: ARM Options. (line 84) 26121* -march= command-line option, M680x0: M68K-Opts. (line 8) 26122* -march= command-line option, TIC6X: TIC6X Options. (line 6) 26123* -march= option, i386: i386-Options. (line 32) 26124* -march= option, s390: s390 Options. (line 25) 26125* -march= option, x86-64: i386-Options. (line 32) 26126* -march=ISA option, RISC-V: RISC-V-Options. (line 15) 26127* -matpcs command-line option, ARM: ARM Options. (line 324) 26128* -mavxscalar= option, i386: i386-Options. (line 99) 26129* -mavxscalar= option, x86-64: i386-Options. (line 99) 26130* -mbarrel-shift-enabled command-line option, LM32: LM32 Options. 26131 (line 12) 26132* -mbig-endian: RX-Opts. (line 20) 26133* -mbig-obj option, x86-64: i386-Options. (line 168) 26134* -mbranches-within-32B-boundaries option, i386: i386-Options. 26135 (line 220) 26136* -mbranches-within-32B-boundaries option, x86-64: i386-Options. 26137 (line 220) 26138* -mbreak-enabled command-line option, LM32: LM32 Options. (line 27) 26139* -mccs command-line option, ARM: ARM Options. (line 379) 26140* -mcis: PDP-11-Options. (line 32) 26141* -mcode-density command-line option, ARC: ARC Options. (line 93) 26142* -mconstant-gp command-line option, IA-64: IA-64 Options. (line 6) 26143* -mCPU command-line option, Alpha: Alpha Options. (line 6) 26144* -mcpu option, cpu: TIC54X-Opts. (line 15) 26145* -mcpu=: RX-Opts. (line 75) 26146* -mcpu= command-line option, AArch64: AArch64 Options. (line 19) 26147* -mcpu= command-line option, ARM: ARM Options. (line 6) 26148* -mcpu= command-line option, Blackfin: Blackfin Options. (line 6) 26149* -mcpu= command-line option, M680x0: M68K-Opts. (line 14) 26150* -mcpu=CPU command-line option, ARC: ARC Options. (line 10) 26151* -mcsm: PDP-11-Options. (line 43) 26152* -mdcache-enabled command-line option, LM32: LM32 Options. (line 24) 26153* -mdebug command-line option, Alpha: Alpha Options. (line 25) 26154* -mdivide-enabled command-line option, LM32: LM32 Options. (line 9) 26155* -mdollar-hex option, dollar-hex: S12Z Options. (line 17) 26156* -mdpfp command-line option, ARC: ARC Options. (line 108) 26157* -mdsbt command-line option, TIC6X: TIC6X Options. (line 13) 26158* -me option, stderr redirect: TIC54X-Opts. (line 20) 26159* -meis: PDP-11-Options. (line 46) 26160* -mepiphany command-line option, Epiphany: Epiphany Options. 26161 (line 9) 26162* -mepiphany16 command-line option, Epiphany: Epiphany Options. 26163 (line 13) 26164* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 26165* -mesa option, s390: s390 Options. (line 17) 26166* -mevexlig= option, i386: i386-Options. (line 120) 26167* -mevexlig= option, x86-64: i386-Options. (line 120) 26168* -mevexrcig= option, i386: i386-Options. (line 235) 26169* -mevexrcig= option, x86-64: i386-Options. (line 235) 26170* -mevexwig= option, i386: i386-Options. (line 130) 26171* -mevexwig= option, x86-64: i386-Options. (line 130) 26172* -mf option, far-mode: TIC54X-Opts. (line 8) 26173* -mf11: PDP-11-Options. (line 122) 26174* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 26175* -mfdpic command-line option, Blackfin: Blackfin Options. (line 19) 26176* -mfence-as-lock-add= option, i386: i386-Options. (line 181) 26177* -mfence-as-lock-add= option, x86-64: i386-Options. (line 181) 26178* -mfis: PDP-11-Options. (line 51) 26179* -mfloat-abi= command-line option, ARM: ARM Options. (line 341) 26180* -mfp-11: PDP-11-Options. (line 56) 26181* -mfp16-format= command-line option: ARM Options. (line 279) 26182* -mfpp: PDP-11-Options. (line 56) 26183* -mfpu: PDP-11-Options. (line 56) 26184* -mfpu= command-line option, ARM: ARM Options. (line 255) 26185* -mfpuda command-line option, ARC: ARC Options. (line 111) 26186* -mgcc-abi: RX-Opts. (line 63) 26187* -mgcc-abi command-line option, V850: V850 Options. (line 79) 26188* -mgcc-isr command-line option, AVR: AVR Options. (line 132) 26189* -mhard-float command-line option, V850: V850 Options. (line 101) 26190* -micache-enabled command-line option, LM32: LM32 Options. (line 21) 26191* -mimplicit-it command-line option, ARM: ARM Options. (line 302) 26192* -mint-register: RX-Opts. (line 57) 26193* -mintel64 option, x86-64: i386-Options. (line 245) 26194* -mip2022 option, IP2K: IP2K-Opts. (line 14) 26195* -mip2022ext option, IP2022: IP2K-Opts. (line 9) 26196* -mj11: PDP-11-Options. (line 126) 26197* -mka11: PDP-11-Options. (line 92) 26198* -mkb11: PDP-11-Options. (line 95) 26199* -mkd11a: PDP-11-Options. (line 98) 26200* -mkd11b: PDP-11-Options. (line 101) 26201* -mkd11d: PDP-11-Options. (line 104) 26202* -mkd11e: PDP-11-Options. (line 107) 26203* -mkd11f: PDP-11-Options. (line 110) 26204* -mkd11h: PDP-11-Options. (line 110) 26205* -mkd11k: PDP-11-Options. (line 114) 26206* -mkd11q: PDP-11-Options. (line 110) 26207* -mkd11z: PDP-11-Options. (line 118) 26208* -mkev11: PDP-11-Options. (line 51) 26209* -mkev11 <1>: PDP-11-Options. (line 51) 26210* -mlimited-eis: PDP-11-Options. (line 64) 26211* -mlink-relax command-line option, AVR: AVR Options. (line 123) 26212* -mlittle-endian: RX-Opts. (line 26) 26213* -mlong: M68HC11-Opts. (line 45) 26214* -mlong <1>: XGATE-Opts. (line 13) 26215* -mlong-double: M68HC11-Opts. (line 53) 26216* -mlong-double <1>: XGATE-Opts. (line 21) 26217* -mm9s12x: M68HC11-Opts. (line 27) 26218* -mm9s12xg: M68HC11-Opts. (line 32) 26219* -mmcu= command-line option, AVR: AVR Options. (line 6) 26220* -mmfpt: PDP-11-Options. (line 70) 26221* -mmicrocode: PDP-11-Options. (line 83) 26222* -mmnemonic= option, i386: i386-Options. (line 137) 26223* -mmnemonic= option, x86-64: i386-Options. (line 137) 26224* -mmultiply-enabled command-line option, LM32: LM32 Options. 26225 (line 6) 26226* -mmutiproc: PDP-11-Options. (line 73) 26227* -mmxps: PDP-11-Options. (line 77) 26228* -mnaked-reg option, i386: i386-Options. (line 149) 26229* -mnaked-reg option, x86-64: i386-Options. (line 149) 26230* -mnan= command-line option, MIPS: MIPS Options. (line 439) 26231* -mno-allow-string-insns: RX-Opts. (line 82) 26232* -mno-cis: PDP-11-Options. (line 32) 26233* -mno-csm: PDP-11-Options. (line 43) 26234* -mno-dsbt command-line option, TIC6X: TIC6X Options. (line 13) 26235* -mno-eis: PDP-11-Options. (line 46) 26236* -mno-extensions: PDP-11-Options. (line 29) 26237* -mno-fdpic command-line option, Blackfin: Blackfin Options. 26238 (line 22) 26239* -mno-fis: PDP-11-Options. (line 51) 26240* -mno-fp-11: PDP-11-Options. (line 56) 26241* -mno-fpp: PDP-11-Options. (line 56) 26242* -mno-fpu: PDP-11-Options. (line 56) 26243* -mno-kev11: PDP-11-Options. (line 51) 26244* -mno-limited-eis: PDP-11-Options. (line 64) 26245* -mno-link-relax command-line option, AVR: AVR Options. (line 127) 26246* -mno-mfpt: PDP-11-Options. (line 70) 26247* -mno-microcode: PDP-11-Options. (line 83) 26248* -mno-mutiproc: PDP-11-Options. (line 73) 26249* -mno-mxps: PDP-11-Options. (line 77) 26250* -mno-pic: PDP-11-Options. (line 11) 26251* -mno-pic command-line option, TIC6X: TIC6X Options. (line 36) 26252* -mno-regnames option, s390: s390 Options. (line 50) 26253* -mno-relax option, RISC-V: RISC-V-Options. (line 31) 26254* -mno-skip-bug command-line option, AVR: AVR Options. (line 114) 26255* -mno-spl: PDP-11-Options. (line 80) 26256* -mno-sym32: MIPS Options. (line 348) 26257* -mno-verbose-error command-line option, AArch64: AArch64 Options. 26258 (line 63) 26259* -mno-wrap command-line option, AVR: AVR Options. (line 117) 26260* -mnopic command-line option, Blackfin: Blackfin Options. (line 22) 26261* -mnps400 command-line option, ARC: ARC Options. (line 102) 26262* -momit-lock-prefix= option, i386: i386-Options. (line 172) 26263* -momit-lock-prefix= option, x86-64: i386-Options. (line 172) 26264* -mpic: PDP-11-Options. (line 11) 26265* -mpic command-line option, TIC6X: TIC6X Options. (line 36) 26266* -mpid: RX-Opts. (line 50) 26267* -mpid= command-line option, TIC6X: TIC6X Options. (line 23) 26268* -mreg-prefix=PREFIX option, reg-prefix: S12Z Options. (line 9) 26269* -mregnames option, s390: s390 Options. (line 47) 26270* -mrelax command-line option, ARC: ARC Options. (line 97) 26271* -mrelax command-line option, V850: V850 Options. (line 72) 26272* -mrelax option, RISC-V: RISC-V-Options. (line 27) 26273* -mrelax-relocations= option, i386: i386-Options. (line 190) 26274* -mrelax-relocations= option, x86-64: i386-Options. (line 190) 26275* -mrh850-abi command-line option, V850: V850 Options. (line 82) 26276* -mrmw command-line option, AVR: AVR Options. (line 120) 26277* -mrx-abi: RX-Opts. (line 69) 26278* -mshared option, i386: i386-Options. (line 159) 26279* -mshared option, x86-64: i386-Options. (line 159) 26280* -mshort: M68HC11-Opts. (line 40) 26281* -mshort <1>: XGATE-Opts. (line 8) 26282* -mshort-double: M68HC11-Opts. (line 49) 26283* -mshort-double <1>: XGATE-Opts. (line 17) 26284* -msign-extend-enabled command-line option, LM32: LM32 Options. 26285 (line 15) 26286* -msmall-data-limit: RX-Opts. (line 42) 26287* -msoft-float command-line option, V850: V850 Options. (line 95) 26288* -mspfp command-line option, ARC: ARC Options. (line 105) 26289* -mspl: PDP-11-Options. (line 80) 26290* -msse-check= option, i386: i386-Options. (line 89) 26291* -msse-check= option, x86-64: i386-Options. (line 89) 26292* -msse2avx option, i386: i386-Options. (line 85) 26293* -msse2avx option, x86-64: i386-Options. (line 85) 26294* -msym32: MIPS Options. (line 348) 26295* -msyntax= option, i386: i386-Options. (line 143) 26296* -msyntax= option, x86-64: i386-Options. (line 143) 26297* -mt11: PDP-11-Options. (line 130) 26298* -mthumb command-line option, ARM: ARM Options. (line 292) 26299* -mthumb-interwork command-line option, ARM: ARM Options. (line 297) 26300* -mtune= option, i386: i386-Options. (line 77) 26301* -mtune= option, x86-64: i386-Options. (line 77) 26302* -mtune=ARCH command-line option, Visium: Visium Options. (line 8) 26303* -muse-conventional-section-names: RX-Opts. (line 33) 26304* -muse-renesas-section-names: RX-Opts. (line 37) 26305* -muser-enabled command-line option, LM32: LM32 Options. (line 18) 26306* -mv850 command-line option, V850: V850 Options. (line 23) 26307* -mv850any command-line option, V850: V850 Options. (line 41) 26308* -mv850e command-line option, V850: V850 Options. (line 29) 26309* -mv850e1 command-line option, V850: V850 Options. (line 35) 26310* -mv850e2 command-line option, V850: V850 Options. (line 51) 26311* -mv850e2v3 command-line option, V850: V850 Options. (line 57) 26312* -mv850e2v4 command-line option, V850: V850 Options. (line 63) 26313* -mv850e3v5 command-line option, V850: V850 Options. (line 66) 26314* -mverbose-error command-line option, AArch64: AArch64 Options. 26315 (line 59) 26316* -mvexwig= option, i386: i386-Options. (line 110) 26317* -mvexwig= option, x86-64: i386-Options. (line 110) 26318* -mvxworks-pic option, MIPS: MIPS Options. (line 26) 26319* -mwarn-areg-zero option, s390: s390 Options. (line 53) 26320* -mwarn-deprecated command-line option, ARM: ARM Options. (line 374) 26321* -mwarn-syms command-line option, ARM: ARM Options. (line 382) 26322* -mx86-used-note= option, i386: i386-Options. (line 228) 26323* -mx86-used-note= option, x86-64: i386-Options. (line 228) 26324* -mzarch option, s390: s390 Options. (line 17) 26325* -m[no-]68851 command-line option, M680x0: M68K-Opts. (line 21) 26326* -m[no-]68881 command-line option, M680x0: M68K-Opts. (line 21) 26327* -m[no-]div command-line option, M680x0: M68K-Opts. (line 21) 26328* -m[no-]emac command-line option, M680x0: M68K-Opts. (line 21) 26329* -m[no-]float command-line option, M680x0: M68K-Opts. (line 21) 26330* -m[no-]mac command-line option, M680x0: M68K-Opts. (line 21) 26331* -m[no-]usp command-line option, M680x0: M68K-Opts. (line 21) 26332* -N command-line option, CRIS: CRIS-Opts. (line 59) 26333* -nIp option, M32RX: M32R-Opts. (line 101) 26334* -no-bitinst, M32R2: M32R-Opts. (line 54) 26335* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 26336* -no-mdebug command-line option, Alpha: Alpha Options. (line 25) 26337* -no-parallel option, M32RX: M32R-Opts. (line 51) 26338* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 26339 (line 79) 26340* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 26341* -nocpp ignored (MIPS): MIPS Options. (line 351) 26342* -noreplace command-line option, Alpha: Alpha Options. (line 40) 26343* -o: o. (line 6) 26344* -O option, i386: i386-Options. (line 250) 26345* -O option, M32RX: M32R-Opts. (line 59) 26346* -O option, x86-64: i386-Options. (line 250) 26347* -O0 option, i386: i386-Options. (line 250) 26348* -O0 option, x86-64: i386-Options. (line 250) 26349* -O1 option, i386: i386-Options. (line 250) 26350* -O1 option, x86-64: i386-Options. (line 250) 26351* -O2 option, i386: i386-Options. (line 250) 26352* -O2 option, x86-64: i386-Options. (line 250) 26353* -Os option, i386: i386-Options. (line 250) 26354* -Os option, x86-64: i386-Options. (line 250) 26355* -parallel option, M32RX: M32R-Opts. (line 46) 26356* -R: R. (line 6) 26357* -r800 command-line option, Z80: Z80 Options. (line 13) 26358* -relax command-line option, Alpha: Alpha Options. (line 32) 26359* -replace command-line option, Alpha: Alpha Options. (line 40) 26360* -S, ignored on VAX: VAX-Opts. (line 11) 26361* -sdcc command-line option, Z80: Z80 Options. (line 34) 26362* -strict command-line option, Z80: Z80 Options. (line 45) 26363* -T, ignored on VAX: VAX-Opts. (line 11) 26364* -t, ignored on VAX: VAX-Opts. (line 36) 26365* -v: v. (line 6) 26366* -V, redundant on VAX: VAX-Opts. (line 22) 26367* -version: v. (line 6) 26368* -W: W. (line 11) 26369* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 26370 (line 65) 26371* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 26372* -Wnp option, M32RX: M32R-Opts. (line 83) 26373* -Wnuh option, M32RX: M32R-Opts. (line 117) 26374* -Wp option, M32RX: M32R-Opts. (line 75) 26375* -wsigned_overflow command-line option, V850: V850 Options. (line 9) 26376* -Wuh option, M32RX: M32R-Opts. (line 114) 26377* -wunsigned_overflow command-line option, V850: V850 Options. 26378 (line 16) 26379* -x command-line option, MMIX: MMIX-Opts. (line 44) 26380* -z180 command-line option, Z80: Z80 Options. (line 16) 26381* -z80 command-line option, Z80: Z80 Options. (line 6) 26382* -z8001 command-line option, Z8000: Z8000 Options. (line 6) 26383* -z8002 command-line option, Z8000: Z8000 Options. (line 9) 26384* . (symbol): Dot. (line 6) 26385* .align directive, ARM: ARM Directives. (line 6) 26386* .align directive, TILE-Gx: TILE-Gx Directives. (line 6) 26387* .align directive, TILEPro: TILEPro Directives. (line 6) 26388* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives. 26389 (line 10) 26390* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives. 26391 (line 10) 26392* .arch directive, AArch64: AArch64 Directives. (line 6) 26393* .arch directive, ARM: ARM Directives. (line 13) 26394* .arch directive, TIC6X: TIC6X Directives. (line 10) 26395* .arch_extension directive, AArch64: AArch64 Directives. (line 13) 26396* .arch_extension directive, ARM: ARM Directives. (line 21) 26397* .arc_attribute directive, ARC: ARC Directives. (line 240) 26398* .arm directive, ARM: ARM Directives. (line 30) 26399* .attribute directive, RISC-V: RISC-V-Directives. (line 96) 26400* .big directive, M32RX: M32R-Directives. (line 88) 26401* .bss directive, AArch64: AArch64 Directives. (line 21) 26402* .bss directive, ARM: ARM Directives. (line 33) 26403* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20) 26404* .cantunwind directive, ARM: ARM Directives. (line 36) 26405* .cantunwind directive, TIC6X: TIC6X Directives. (line 13) 26406* .cfi_b_key_frame directive, AArch64: AArch64 Directives. (line 99) 26407* .code directive, ARM: ARM Directives. (line 40) 26408* .cpu directive, AArch64: AArch64 Directives. (line 24) 26409* .cpu directive, ARM: ARM Directives. (line 44) 26410* .dn and .qn directives, ARM: ARM Directives. (line 52) 26411* .dword directive, AArch64: AArch64 Directives. (line 28) 26412* .eabi_attribute directive, ARM: ARM Directives. (line 76) 26413* .ehtype directive, TIC6X: TIC6X Directives. (line 31) 26414* .endp directive, TIC6X: TIC6X Directives. (line 34) 26415* .even directive, AArch64: AArch64 Directives. (line 31) 26416* .even directive, ARM: ARM Directives. (line 105) 26417* .extend directive, ARM: ARM Directives. (line 108) 26418* .float16 directive, AArch64: AArch64 Directives. (line 35) 26419* .float16 directive, ARM: ARM Directives. (line 114) 26420* .float16_format directive, ARM: ARM Directives. (line 122) 26421* .fnend directive, ARM: ARM Directives. (line 129) 26422* .fnstart directive, ARM: ARM Directives. (line 137) 26423* .force_thumb directive, ARM: ARM Directives. (line 140) 26424* .fpu directive, ARM: ARM Directives. (line 144) 26425* .global: MIPS insn. (line 12) 26426* .gnu_attribute 4, N directive, MIPS: MIPS FP ABI History. 26427 (line 6) 26428* .gnu_attribute Tag_GNU_MIPS_ABI_FP, N directive, MIPS: MIPS FP ABI History. 26429 (line 6) 26430* .handlerdata directive, ARM: ARM Directives. (line 148) 26431* .handlerdata directive, TIC6X: TIC6X Directives. (line 39) 26432* .insn: MIPS insn. (line 6) 26433* .insn directive, s390: s390 Directives. (line 11) 26434* .inst directive, AArch64: AArch64 Directives. (line 41) 26435* .inst directive, ARM: ARM Directives. (line 157) 26436* .ldouble directive, ARM: ARM Directives. (line 108) 26437* .little directive, M32RX: M32R-Directives. (line 82) 26438* .long directive, s390: s390 Directives. (line 16) 26439* .ltorg directive, AArch64: AArch64 Directives. (line 45) 26440* .ltorg directive, ARM: ARM Directives. (line 167) 26441* .ltorg directive, s390: s390 Directives. (line 79) 26442* .m32r directive, M32R: M32R-Directives. (line 66) 26443* .m32r2 directive, M32R2: M32R-Directives. (line 77) 26444* .m32rx directive, M32RX: M32R-Directives. (line 72) 26445* .machine directive, s390: s390 Directives. (line 84) 26446* .machinemode directive, s390: s390 Directives. (line 101) 26447* .module: MIPS assembly options. 26448 (line 6) 26449* .module fp=NN directive, MIPS: MIPS FP ABI Selection. 26450 (line 6) 26451* .movsp directive, ARM: ARM Directives. (line 181) 26452* .nan directive, MIPS: MIPS NaN Encodings. (line 6) 26453* .nocmp directive, TIC6X: TIC6X Directives. (line 47) 26454* .no_pointers directive, XStormy16: XStormy16 Directives. 26455 (line 14) 26456* .o: Object. (line 6) 26457* .object_arch directive, ARM: ARM Directives. (line 186) 26458* .packed directive, ARM: ARM Directives. (line 192) 26459* .pad directive, ARM: ARM Directives. (line 197) 26460* .param on HPPA: HPPA Directives. (line 19) 26461* .personality directive, ARM: ARM Directives. (line 202) 26462* .personality directive, TIC6X: TIC6X Directives. (line 55) 26463* .personalityindex directive, ARM: ARM Directives. (line 205) 26464* .personalityindex directive, TIC6X: TIC6X Directives. (line 51) 26465* .pool directive, AArch64: AArch64 Directives. (line 59) 26466* .pool directive, ARM: ARM Directives. (line 209) 26467* .quad directive, s390: s390 Directives. (line 16) 26468* .req directive, AArch64: AArch64 Directives. (line 62) 26469* .req directive, ARM: ARM Directives. (line 212) 26470* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives. 26471 (line 19) 26472* .require_canonical_reg_names directive, TILEPro: TILEPro Directives. 26473 (line 19) 26474* .save directive, ARM: ARM Directives. (line 217) 26475* .scomm directive, TIC6X: TIC6X Directives. (line 58) 26476* .secrel32 directive, ARM: ARM Directives. (line 255) 26477* .set arch=CPU: MIPS ISA. (line 18) 26478* .set at: MIPS Macros. (line 41) 26479* .set at=REG: MIPS Macros. (line 35) 26480* .set autoextend: MIPS autoextend. (line 6) 26481* .set crc: MIPS ASE Instruction Generation Overrides. 26482 (line 68) 26483* .set doublefloat: MIPS Floating-Point. 26484 (line 12) 26485* .set dsp: MIPS ASE Instruction Generation Overrides. 26486 (line 21) 26487* .set dspr2: MIPS ASE Instruction Generation Overrides. 26488 (line 26) 26489* .set dspr3: MIPS ASE Instruction Generation Overrides. 26490 (line 31) 26491* .set ginv: MIPS ASE Instruction Generation Overrides. 26492 (line 72) 26493* .set hardfloat: MIPS Floating-Point. 26494 (line 6) 26495* .set insn32: MIPS assembly options. 26496 (line 18) 26497* .set loongson-cam: MIPS ASE Instruction Generation Overrides. 26498 (line 81) 26499* .set loongson-ext: MIPS ASE Instruction Generation Overrides. 26500 (line 86) 26501* .set loongson-ext2: MIPS ASE Instruction Generation Overrides. 26502 (line 91) 26503* .set loongson-mmi: MIPS ASE Instruction Generation Overrides. 26504 (line 76) 26505* .set macro: MIPS Macros. (line 30) 26506* .set mcu: MIPS ASE Instruction Generation Overrides. 26507 (line 42) 26508* .set mdmx: MIPS ASE Instruction Generation Overrides. 26509 (line 16) 26510* .set mips16e2: MIPS ASE Instruction Generation Overrides. 26511 (line 61) 26512* .set mips3d: MIPS ASE Instruction Generation Overrides. 26513 (line 6) 26514* .set mipsN: MIPS ISA. (line 6) 26515* .set msa: MIPS ASE Instruction Generation Overrides. 26516 (line 47) 26517* .set mt: MIPS ASE Instruction Generation Overrides. 26518 (line 37) 26519* .set noat: MIPS Macros. (line 41) 26520* .set noautoextend: MIPS autoextend. (line 6) 26521* .set nocrc: MIPS ASE Instruction Generation Overrides. 26522 (line 68) 26523* .set nodsp: MIPS ASE Instruction Generation Overrides. 26524 (line 21) 26525* .set nodspr2: MIPS ASE Instruction Generation Overrides. 26526 (line 26) 26527* .set nodspr3: MIPS ASE Instruction Generation Overrides. 26528 (line 31) 26529* .set noginv: MIPS ASE Instruction Generation Overrides. 26530 (line 72) 26531* .set noinsn32: MIPS assembly options. 26532 (line 18) 26533* .set noloongson-cam: MIPS ASE Instruction Generation Overrides. 26534 (line 81) 26535* .set noloongson-ext: MIPS ASE Instruction Generation Overrides. 26536 (line 86) 26537* .set noloongson-ext2: MIPS ASE Instruction Generation Overrides. 26538 (line 91) 26539* .set noloongson-mmi: MIPS ASE Instruction Generation Overrides. 26540 (line 76) 26541* .set nomacro: MIPS Macros. (line 30) 26542* .set nomcu: MIPS ASE Instruction Generation Overrides. 26543 (line 42) 26544* .set nomdmx: MIPS ASE Instruction Generation Overrides. 26545 (line 16) 26546* .set nomips16e2: MIPS ASE Instruction Generation Overrides. 26547 (line 61) 26548* .set nomips3d: MIPS ASE Instruction Generation Overrides. 26549 (line 6) 26550* .set nomsa: MIPS ASE Instruction Generation Overrides. 26551 (line 47) 26552* .set nomt: MIPS ASE Instruction Generation Overrides. 26553 (line 37) 26554* .set nosmartmips: MIPS ASE Instruction Generation Overrides. 26555 (line 11) 26556* .set nosym32: MIPS Symbol Sizes. (line 6) 26557* .set novirt: MIPS ASE Instruction Generation Overrides. 26558 (line 52) 26559* .set noxpa: MIPS ASE Instruction Generation Overrides. 26560 (line 57) 26561* .set pop: MIPS Option Stack. (line 6) 26562* .set push: MIPS Option Stack. (line 6) 26563* .set singlefloat: MIPS Floating-Point. 26564 (line 12) 26565* .set smartmips: MIPS ASE Instruction Generation Overrides. 26566 (line 11) 26567* .set softfloat: MIPS Floating-Point. 26568 (line 6) 26569* .set sym32: MIPS Symbol Sizes. (line 6) 26570* .set virt: MIPS ASE Instruction Generation Overrides. 26571 (line 52) 26572* .set xpa: MIPS ASE Instruction Generation Overrides. 26573 (line 57) 26574* .setfp directive, ARM: ARM Directives. (line 241) 26575* .short directive, s390: s390 Directives. (line 16) 26576* .syntax directive, ARM: ARM Directives. (line 260) 26577* .thumb directive, ARM: ARM Directives. (line 264) 26578* .thumb_func directive, ARM: ARM Directives. (line 267) 26579* .thumb_set directive, ARM: ARM Directives. (line 278) 26580* .tlsdescadd directive, AArch64: AArch64 Directives. (line 70) 26581* .tlsdesccall directive, AArch64: AArch64 Directives. (line 73) 26582* .tlsdescldr directive, AArch64: AArch64 Directives. (line 76) 26583* .tlsdescseq directive, ARM: ARM Directives. (line 285) 26584* .unreq directive, AArch64: AArch64 Directives. (line 79) 26585* .unreq directive, ARM: ARM Directives. (line 290) 26586* .unwind_raw directive, ARM: ARM Directives. (line 301) 26587* .v850 directive, V850: V850 Directives. (line 14) 26588* .v850e directive, V850: V850 Directives. (line 20) 26589* .v850e1 directive, V850: V850 Directives. (line 26) 26590* .v850e2 directive, V850: V850 Directives. (line 32) 26591* .v850e2v3 directive, V850: V850 Directives. (line 38) 26592* .v850e2v4 directive, V850: V850 Directives. (line 44) 26593* .v850e3v5 directive, V850: V850 Directives. (line 50) 26594* .variant_pcs directive, AArch64: AArch64 Directives. (line 90) 26595* .vsave directive, ARM: ARM Directives. (line 308) 26596* .xword directive, AArch64: AArch64 Directives. (line 95) 26597* .z8001: Z8000 Directives. (line 11) 26598* .z8002: Z8000 Directives. (line 15) 26599* 16-bit code, i386: i386-16bit. (line 6) 26600* 16bit_pointers directive, XStormy16: XStormy16 Directives. 26601 (line 6) 26602* 16byte directive, Nios II: Nios II Directives. (line 28) 26603* 16byte directive, PRU: PRU Directives. (line 25) 26604* 2byte directive: 2byte. (line 6) 26605* 2byte directive, Nios II: Nios II Directives. (line 19) 26606* 2byte directive, PRU: PRU Directives. (line 16) 26607* 32bit_pointers directive, XStormy16: XStormy16 Directives. 26608 (line 10) 26609* 3DNow!, i386: i386-SIMD. (line 6) 26610* 3DNow!, x86-64: i386-SIMD. (line 6) 26611* 430 support: MSP430-Dependent. (line 6) 26612* 4byte directive: 4byte. (line 6) 26613* 4byte directive, Nios II: Nios II Directives. (line 22) 26614* 4byte directive, PRU: PRU Directives. (line 19) 26615* 8byte directive: 8byte. (line 6) 26616* 8byte directive, Nios II: Nios II Directives. (line 25) 26617* 8byte directive, PRU: PRU Directives. (line 22) 26618* : (label): Statements. (line 31) 26619* @gotoff(SYMBOL), ARC modifier: ARC Modifiers. (line 20) 26620* @gotpc(SYMBOL), ARC modifier: ARC Modifiers. (line 16) 26621* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) 26622* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) 26623* @pcl(SYMBOL), ARC modifier: ARC Modifiers. (line 12) 26624* @plt(SYMBOL), ARC modifier: ARC Modifiers. (line 23) 26625* @sda(SYMBOL), ARC modifier: ARC Modifiers. (line 28) 26626* @word modifier, D10V: D10V-Word. (line 6) 26627* _ opcode prefix: Xtensa Opcodes. (line 9) 26628* __DYNAMIC__, ARC pre-defined symbol: ARC Symbols. (line 14) 26629* __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol: ARC Symbols. 26630 (line 11) 26631* a.out: Object. (line 6) 26632* a.out symbol attributes: a.out Symbols. (line 6) 26633* AArch64 floating point (IEEE): AArch64 Floating Point. 26634 (line 6) 26635* AArch64 immediate character: AArch64-Chars. (line 13) 26636* AArch64 line comment character: AArch64-Chars. (line 6) 26637* AArch64 line separator: AArch64-Chars. (line 10) 26638* AArch64 machine directives: AArch64 Directives. (line 6) 26639* AArch64 opcodes: AArch64 Opcodes. (line 6) 26640* AArch64 options (none): AArch64 Options. (line 6) 26641* AArch64 register names: AArch64-Regs. (line 6) 26642* AArch64 relocations: AArch64-Relocations. 26643 (line 6) 26644* AArch64 support: AArch64-Dependent. (line 6) 26645* abort directive: Abort. (line 6) 26646* ABORT directive: ABORT (COFF). (line 6) 26647* absolute section: Ld Sections. (line 29) 26648* absolute-literals directive: Absolute Literals Directive. 26649 (line 6) 26650* ADDI instructions, relaxation: Xtensa Immediate Relaxation. 26651 (line 43) 26652* addition, permitted arguments: Infix Ops. (line 45) 26653* addresses: Expressions. (line 6) 26654* addresses, format of: Secs Background. (line 65) 26655* addressing modes, D10V: D10V-Addressing. (line 6) 26656* addressing modes, D30V: D30V-Addressing. (line 6) 26657* addressing modes, H8/300: H8/300-Addressing. (line 6) 26658* addressing modes, M680x0: M68K-Syntax. (line 21) 26659* addressing modes, M68HC11: M68HC11-Syntax. (line 29) 26660* addressing modes, S12Z: S12Z Addressing Modes. 26661 (line 6) 26662* addressing modes, SH: SH-Addressing. (line 6) 26663* addressing modes, XGATE: XGATE-Syntax. (line 28) 26664* addressing modes, Z8000: Z8000-Addressing. (line 6) 26665* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 26666* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 43) 26667* ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations. 26668 (line 14) 26669* advancing location counter: Org. (line 6) 26670* align directive: Align. (line 6) 26671* align directive <1>: RISC-V-Directives. (line 8) 26672* align directive, Nios II: Nios II Directives. (line 6) 26673* align directive, OpenRISC: OpenRISC-Directives. 26674 (line 9) 26675* align directive, PRU: PRU Directives. (line 6) 26676* align directive, SPARC: Sparc-Directives. (line 9) 26677* align directive, TIC54X: TIC54X-Directives. (line 6) 26678* aligned instruction bundle: Bundle directives. (line 9) 26679* alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 26680* alignment of branch targets: Xtensa Automatic Alignment. 26681 (line 6) 26682* alignment of LOOP instructions: Xtensa Automatic Alignment. 26683 (line 6) 26684* Alpha floating point (IEEE): Alpha Floating Point. 26685 (line 6) 26686* Alpha line comment character: Alpha-Chars. (line 6) 26687* Alpha line separator: Alpha-Chars. (line 11) 26688* Alpha notes: Alpha Notes. (line 6) 26689* Alpha options: Alpha Options. (line 6) 26690* Alpha registers: Alpha-Regs. (line 6) 26691* Alpha relocations: Alpha-Relocs. (line 6) 26692* Alpha support: Alpha-Dependent. (line 6) 26693* Alpha Syntax: Alpha Options. (line 60) 26694* Alpha-only directives: Alpha Directives. (line 9) 26695* Altera Nios II support: NiosII-Dependent. (line 6) 26696* altered difference tables: Word. (line 12) 26697* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 26698* ARC Branch Target Address: ARC-Regs. (line 60) 26699* ARC BTA saved on exception entry: ARC-Regs. (line 79) 26700* ARC Build configuration for: BTA Registers: ARC-Regs. (line 89) 26701* ARC Build configuration for: Core Registers: ARC-Regs. (line 97) 26702* ARC Build configuration for: Interrupts: ARC-Regs. (line 93) 26703* ARC Build Configuration Registers Version: ARC-Regs. (line 85) 26704* ARC C preprocessor macro separator: ARC-Chars. (line 31) 26705* ARC core general registers: ARC-Regs. (line 10) 26706* ARC DCCM RAM Configuration Register: ARC-Regs. (line 101) 26707* ARC Exception Cause Register: ARC-Regs. (line 63) 26708* ARC Exception Return Address: ARC-Regs. (line 76) 26709* ARC extension core registers: ARC-Regs. (line 38) 26710* ARC frame pointer: ARC-Regs. (line 17) 26711* ARC global pointer: ARC-Regs. (line 14) 26712* ARC interrupt link register: ARC-Regs. (line 27) 26713* ARC Interrupt Vector Base address: ARC-Regs. (line 66) 26714* ARC level 1 interrupt link register: ARC-Regs. (line 23) 26715* ARC level 2 interrupt link register: ARC-Regs. (line 31) 26716* ARC line comment character: ARC-Chars. (line 11) 26717* ARC line separator: ARC-Chars. (line 27) 26718* ARC link register: ARC-Regs. (line 35) 26719* ARC loop counter: ARC-Regs. (line 41) 26720* ARC machine directives: ARC Directives. (line 6) 26721* ARC opcodes: ARC Opcodes. (line 6) 26722* ARC options: ARC Options. (line 6) 26723* ARC Processor Identification register: ARC-Regs. (line 51) 26724* ARC Program Counter: ARC-Regs. (line 54) 26725* ARC register name prefix character: ARC-Chars. (line 7) 26726* ARC register names: ARC-Regs. (line 6) 26727* ARC Saved User Stack Pointer: ARC-Regs. (line 73) 26728* ARC stack pointer: ARC-Regs. (line 20) 26729* ARC Status register: ARC-Regs. (line 57) 26730* ARC STATUS32 saved on exception: ARC-Regs. (line 82) 26731* ARC Stored STATUS32 register on entry to level P0 interrupts: ARC-Regs. 26732 (line 69) 26733* ARC support: ARC-Dependent. (line 6) 26734* ARC symbol prefix character: ARC-Chars. (line 20) 26735* ARC word aligned program counter: ARC-Regs. (line 44) 26736* arch directive, i386: i386-Arch. (line 6) 26737* arch directive, M680x0: M68K-Directives. (line 22) 26738* arch directive, MSP 430: MSP430 Directives. (line 18) 26739* arch directive, x86-64: i386-Arch. (line 6) 26740* architecture options, IP2022: IP2K-Opts. (line 9) 26741* architecture options, IP2K: IP2K-Opts. (line 14) 26742* architecture options, M16C: M32C-Opts. (line 12) 26743* architecture options, M32C: M32C-Opts. (line 9) 26744* architecture options, M32R: M32R-Opts. (line 21) 26745* architecture options, M32R2: M32R-Opts. (line 17) 26746* architecture options, M32RX: M32R-Opts. (line 9) 26747* architecture options, M680x0: M68K-Opts. (line 99) 26748* Architecture variant option, CRIS: CRIS-Opts. (line 34) 26749* architectures, Meta: Meta Options. (line 6) 26750* architectures, PowerPC: PowerPC-Opts. (line 6) 26751* architectures, SCORE: SCORE-Opts. (line 6) 26752* architectures, SPARC: Sparc-Opts. (line 6) 26753* arguments for addition: Infix Ops. (line 45) 26754* arguments for subtraction: Infix Ops. (line 50) 26755* arguments in expressions: Arguments. (line 6) 26756* arithmetic functions: Operators. (line 6) 26757* arithmetic operands: Arguments. (line 6) 26758* ARM data relocations: ARM-Relocations. (line 6) 26759* ARM floating point (IEEE): ARM Floating Point. (line 6) 26760* ARM identifiers: ARM-Chars. (line 19) 26761* ARM immediate character: ARM-Chars. (line 17) 26762* ARM line comment character: ARM-Chars. (line 6) 26763* ARM line separator: ARM-Chars. (line 14) 26764* ARM machine directives: ARM Directives. (line 6) 26765* ARM opcodes: ARM Opcodes. (line 6) 26766* ARM options (none): ARM Options. (line 6) 26767* ARM register names: ARM-Regs. (line 6) 26768* ARM support: ARM-Dependent. (line 6) 26769* ascii directive: Ascii. (line 6) 26770* asciz directive: Asciz. (line 6) 26771* asg directive, TIC54X: TIC54X-Directives. (line 18) 26772* assembler bugs, reporting: Bug Reporting. (line 6) 26773* assembler crash: Bug Criteria. (line 9) 26774* assembler directive .3byte, RX: RX-Directives. (line 9) 26775* assembler directive .arch, CRIS: CRIS-Pseudos. (line 50) 26776* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 26777* assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 26778* assembler directive .fetchalign, RX: RX-Directives. (line 13) 26779* assembler directive .interrupt, M68HC11: M68HC11-Directives. 26780 (line 26) 26781* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 26782* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 26783* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 18) 26784* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 26785* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 137) 26786* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 101) 26787* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 137) 26788* assembler directive GREG, MMIX: MMIX-Pseudos. (line 53) 26789* assembler directive IS, MMIX: MMIX-Pseudos. (line 44) 26790* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 26791* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 29) 26792* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 113) 26793* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 125) 26794* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 113) 26795* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 113) 26796* assembler directives, CRIS: CRIS-Pseudos. (line 6) 26797* assembler directives, M68HC11: M68HC11-Directives. (line 6) 26798* assembler directives, M68HC12: M68HC11-Directives. (line 6) 26799* assembler directives, MMIX: MMIX-Pseudos. (line 6) 26800* assembler directives, RL78: RL78-Directives. (line 6) 26801* assembler directives, RX: RX-Directives. (line 6) 26802* assembler directives, XGATE: XGATE-Directives. (line 6) 26803* assembler internal logic error: As Sections. (line 13) 26804* assembler version: v. (line 6) 26805* assembler, and linker: Secs Background. (line 10) 26806* assembly listings, enabling: a. (line 6) 26807* assigning values to symbols: Setting Symbols. (line 6) 26808* assigning values to symbols <1>: Equ. (line 6) 26809* at register, MIPS: MIPS Macros. (line 35) 26810* attributes, symbol: Symbol Attributes. (line 6) 26811* att_syntax pseudo op, i386: i386-Variations. (line 6) 26812* att_syntax pseudo op, x86-64: i386-Variations. (line 6) 26813* auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 26814* auxiliary symbol information, COFF: Dim. (line 6) 26815* AVR line comment character: AVR-Chars. (line 6) 26816* AVR line separator: AVR-Chars. (line 14) 26817* AVR modifiers: AVR-Modifiers. (line 6) 26818* AVR opcode summary: AVR Opcodes. (line 6) 26819* AVR options (none): AVR Options. (line 6) 26820* AVR register names: AVR-Regs. (line 6) 26821* AVR support: AVR-Dependent. (line 6) 26822* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 26823* backslash (\\): Strings. (line 40) 26824* backspace (\b): Strings. (line 15) 26825* balign directive: Balign. (line 6) 26826* balignl directive: Balign. (line 29) 26827* balignw directive: Balign. (line 29) 26828* bes directive, TIC54X: TIC54X-Directives. (line 194) 26829* big endian output, MIPS: Overview. (line 855) 26830* big endian output, PJ: Overview. (line 759) 26831* big-endian output, MIPS: MIPS Options. (line 13) 26832* big-endian output, TIC6X: TIC6X Options. (line 46) 26833* bignums: Bignums. (line 6) 26834* binary constants, TIC54X: TIC54X-Constants. (line 8) 26835* binary files, including: Incbin. (line 6) 26836* binary integers: Integers. (line 6) 26837* bit names, IA-64: IA-64-Bits. (line 6) 26838* bitfields, not supported on VAX: VAX-no. (line 6) 26839* Blackfin directives: Blackfin Directives. 26840 (line 6) 26841* Blackfin options (none): Blackfin Options. (line 6) 26842* Blackfin support: Blackfin-Dependent. (line 6) 26843* Blackfin syntax: Blackfin Syntax. (line 6) 26844* block: Z8000 Directives. (line 55) 26845* BMI, i386: i386-BMI. (line 6) 26846* BMI, x86-64: i386-BMI. (line 6) 26847* BPF line comment character: BPF-Chars. (line 6) 26848* BPF opcodes: BPF Opcodes. (line 6) 26849* BPF options (none): BPF Options. (line 6) 26850* BPF register names: BPF-Regs. (line 6) 26851* BPF support: BPF-Dependent. (line 6) 26852* branch improvement, M680x0: M68K-Branch. (line 6) 26853* branch improvement, M68HC11: M68HC11-Branch. (line 6) 26854* branch improvement, VAX: VAX-branch. (line 6) 26855* branch instructions, relaxation: Xtensa Branch Relaxation. 26856 (line 6) 26857* Branch Target Address, ARC: ARC-Regs. (line 60) 26858* branch target alignment: Xtensa Automatic Alignment. 26859 (line 6) 26860* break directive, TIC54X: TIC54X-Directives. (line 141) 26861* BSD syntax: PDP-11-Syntax. (line 6) 26862* BSS directive: RISC-V-Directives. (line 24) 26863* bss directive, TIC54X: TIC54X-Directives. (line 27) 26864* bss section: Ld Sections. (line 20) 26865* bss section <1>: bss. (line 6) 26866* BTA saved on exception entry, ARC: ARC-Regs. (line 79) 26867* bug criteria: Bug Criteria. (line 6) 26868* bug reports: Bug Reporting. (line 6) 26869* bugs in assembler: Reporting Bugs. (line 6) 26870* Build configuration for: BTA Registers, ARC: ARC-Regs. (line 89) 26871* Build configuration for: Core Registers, ARC: ARC-Regs. (line 97) 26872* Build configuration for: Interrupts, ARC: ARC-Regs. (line 93) 26873* Build Configuration Registers Version, ARC: ARC-Regs. (line 85) 26874* Built-in symbols, CRIS: CRIS-Symbols. (line 6) 26875* builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 26876* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 26877* bundle: Bundle directives. (line 9) 26878* bundle-locked: Bundle directives. (line 39) 26879* bundle_align_mode directive: Bundle directives. (line 9) 26880* bundle_lock directive: Bundle directives. (line 31) 26881* bundle_unlock directive: Bundle directives. (line 31) 26882* bus lock prefixes, i386: i386-Prefixes. (line 36) 26883* bval: Z8000 Directives. (line 30) 26884* byte directive: Byte. (line 6) 26885* byte directive, TIC54X: TIC54X-Directives. (line 34) 26886* C preprocessor macro separator, ARC: ARC-Chars. (line 31) 26887* C-SKY options: C-SKY Options. (line 6) 26888* C-SKY support: C-SKY-Dependent. (line 6) 26889* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 26890* call directive, Nios II: Nios II Relocations. 26891 (line 38) 26892* call instructions, i386: i386-Mnemonics. (line 75) 26893* call instructions, relaxation: Xtensa Call Relaxation. 26894 (line 6) 26895* call instructions, x86-64: i386-Mnemonics. (line 75) 26896* call_hiadj directive, Nios II: Nios II Relocations. 26897 (line 38) 26898* call_lo directive, Nios II: Nios II Relocations. 26899 (line 38) 26900* carriage return (backslash-r): Strings. (line 24) 26901* case sensitivity, Z80: Z80-Case. (line 6) 26902* cfi_endproc directive: CFI directives. (line 40) 26903* cfi_fde_data directive: CFI directives. (line 66) 26904* cfi_personality directive: CFI directives. (line 47) 26905* cfi_personality_id directive: CFI directives. (line 59) 26906* cfi_sections directive: CFI directives. (line 9) 26907* cfi_startproc directive: CFI directives. (line 30) 26908* char directive, TIC54X: TIC54X-Directives. (line 34) 26909* character constant, Z80: Z80-Chars. (line 20) 26910* character constants: Characters. (line 6) 26911* character escape codes: Strings. (line 15) 26912* character escapes, Z80: Z80-Chars. (line 18) 26913* character, single: Chars. (line 6) 26914* characters used in symbols: Symbol Intro. (line 6) 26915* clink directive, TIC54X: TIC54X-Directives. (line 43) 26916* code16 directive, i386: i386-16bit. (line 6) 26917* code16gcc directive, i386: i386-16bit. (line 6) 26918* code32 directive, i386: i386-16bit. (line 6) 26919* code64 directive, i386: i386-16bit. (line 6) 26920* code64 directive, x86-64: i386-16bit. (line 6) 26921* COFF auxiliary symbol information: Dim. (line 6) 26922* COFF structure debugging: Tag. (line 6) 26923* COFF symbol attributes: COFF Symbols. (line 6) 26924* COFF symbol descriptor: Desc. (line 6) 26925* COFF symbol storage class: Scl. (line 6) 26926* COFF symbol type: Type. (line 11) 26927* COFF symbols, debugging: Def. (line 6) 26928* COFF value attribute: Val. (line 6) 26929* COMDAT: Linkonce. (line 6) 26930* comm directive: Comm. (line 6) 26931* command line conventions: Command Line. (line 6) 26932* command-line options ignored, VAX: VAX-Opts. (line 6) 26933* command-line options, V850: V850 Options. (line 9) 26934* comment character, XStormy16: XStormy16-Chars. (line 11) 26935* comments: Comments. (line 6) 26936* comments, M680x0: M68K-Chars. (line 6) 26937* comments, removed by preprocessor: Preprocessing. (line 11) 26938* common directive, SPARC: Sparc-Directives. (line 12) 26939* common sections: Linkonce. (line 6) 26940* common variable storage: bss. (line 6) 26941* comparison expressions: Infix Ops. (line 56) 26942* conditional assembly: If. (line 6) 26943* constant, single character: Chars. (line 6) 26944* constants: Constants. (line 6) 26945* constants, bignum: Bignums. (line 6) 26946* constants, character: Characters. (line 6) 26947* constants, converted by preprocessor: Preprocessing. (line 14) 26948* constants, floating point: Flonums. (line 6) 26949* constants, integer: Integers. (line 6) 26950* constants, number: Numbers. (line 6) 26951* constants, Sparc: Sparc-Constants. (line 6) 26952* constants, string: Strings. (line 6) 26953* constants, TIC54X: TIC54X-Constants. (line 6) 26954* conversion instructions, i386: i386-Mnemonics. (line 56) 26955* conversion instructions, x86-64: i386-Mnemonics. (line 56) 26956* coprocessor wait, i386: i386-Prefixes. (line 40) 26957* copy directive, TIC54X: TIC54X-Directives. (line 52) 26958* core general registers, ARC: ARC-Regs. (line 10) 26959* cpu directive, ARC: ARC Directives. (line 27) 26960* cpu directive, M680x0: M68K-Directives. (line 30) 26961* cpu directive, MSP 430: MSP430 Directives. (line 22) 26962* CR16 line comment character: CR16-Chars. (line 6) 26963* CR16 line separator: CR16-Chars. (line 12) 26964* CR16 Operand Qualifiers: CR16 Operand Qualifiers. 26965 (line 6) 26966* CR16 support: CR16-Dependent. (line 6) 26967* crash of assembler: Bug Criteria. (line 9) 26968* CRIS --emulation=crisaout command-line option: CRIS-Opts. (line 9) 26969* CRIS --emulation=criself command-line option: CRIS-Opts. (line 9) 26970* CRIS --march=ARCHITECTURE command-line option: CRIS-Opts. (line 34) 26971* CRIS --mul-bug-abort command-line option: CRIS-Opts. (line 63) 26972* CRIS --no-mul-bug-abort command-line option: CRIS-Opts. (line 63) 26973* CRIS --no-underscore command-line option: CRIS-Opts. (line 15) 26974* CRIS --pic command-line option: CRIS-Opts. (line 27) 26975* CRIS --underscore command-line option: CRIS-Opts. (line 15) 26976* CRIS -N command-line option: CRIS-Opts. (line 59) 26977* CRIS architecture variant option: CRIS-Opts. (line 34) 26978* CRIS assembler directive .arch: CRIS-Pseudos. (line 50) 26979* CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 26980* CRIS assembler directive .syntax: CRIS-Pseudos. (line 18) 26981* CRIS assembler directives: CRIS-Pseudos. (line 6) 26982* CRIS built-in symbols: CRIS-Symbols. (line 6) 26983* CRIS instruction expansion: CRIS-Expand. (line 6) 26984* CRIS line comment characters: CRIS-Chars. (line 6) 26985* CRIS options: CRIS-Opts. (line 6) 26986* CRIS position-independent code: CRIS-Opts. (line 27) 26987* CRIS pseudo-op .arch: CRIS-Pseudos. (line 50) 26988* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 26989* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 18) 26990* CRIS pseudo-ops: CRIS-Pseudos. (line 6) 26991* CRIS register names: CRIS-Regs. (line 6) 26992* CRIS support: CRIS-Dependent. (line 6) 26993* CRIS symbols in position-independent code: CRIS-Pic. (line 6) 26994* ctbp register, V850: V850-Regs. (line 90) 26995* ctoff pseudo-op, V850: V850 Opcodes. (line 110) 26996* ctpc register, V850: V850-Regs. (line 82) 26997* ctpsw register, V850: V850-Regs. (line 84) 26998* current address: Dot. (line 6) 26999* current address, advancing: Org. (line 6) 27000* c_mode directive, TIC54X: TIC54X-Directives. (line 49) 27001* D10V @word modifier: D10V-Word. (line 6) 27002* D10V addressing modes: D10V-Addressing. (line 6) 27003* D10V floating point: D10V-Float. (line 6) 27004* D10V line comment character: D10V-Chars. (line 6) 27005* D10V opcode summary: D10V-Opcodes. (line 6) 27006* D10V optimization: Overview. (line 638) 27007* D10V options: D10V-Opts. (line 6) 27008* D10V registers: D10V-Regs. (line 6) 27009* D10V size modifiers: D10V-Size. (line 6) 27010* D10V sub-instruction ordering: D10V-Chars. (line 14) 27011* D10V sub-instructions: D10V-Subs. (line 6) 27012* D10V support: D10V-Dependent. (line 6) 27013* D10V syntax: D10V-Syntax. (line 6) 27014* D30V addressing modes: D30V-Addressing. (line 6) 27015* D30V floating point: D30V-Float. (line 6) 27016* D30V Guarded Execution: D30V-Guarded. (line 6) 27017* D30V line comment character: D30V-Chars. (line 6) 27018* D30V nops: Overview. (line 646) 27019* D30V nops after 32-bit multiply: Overview. (line 649) 27020* D30V opcode summary: D30V-Opcodes. (line 6) 27021* D30V optimization: Overview. (line 643) 27022* D30V options: D30V-Opts. (line 6) 27023* D30V registers: D30V-Regs. (line 6) 27024* D30V size modifiers: D30V-Size. (line 6) 27025* D30V sub-instruction ordering: D30V-Chars. (line 14) 27026* D30V sub-instructions: D30V-Subs. (line 6) 27027* D30V support: D30V-Dependent. (line 6) 27028* D30V syntax: D30V-Syntax. (line 6) 27029* data alignment on SPARC: Sparc-Aligned-Data. (line 6) 27030* data and text sections, joining: R. (line 6) 27031* data directive: Data. (line 6) 27032* data directive, TIC54X: TIC54X-Directives. (line 59) 27033* Data directives: RISC-V-Directives. (line 12) 27034* data relocations, ARM: ARM-Relocations. (line 6) 27035* data section: Ld Sections. (line 9) 27036* data1 directive, M680x0: M68K-Directives. (line 9) 27037* data2 directive, M680x0: M68K-Directives. (line 12) 27038* dbpc register, V850: V850-Regs. (line 86) 27039* dbpsw register, V850: V850-Regs. (line 88) 27040* dc directive: Dc. (line 6) 27041* dcb directive: Dcb. (line 6) 27042* DCCM RAM Configuration Register, ARC: ARC-Regs. (line 101) 27043* debuggers, and symbol order: Symbols. (line 10) 27044* debugging COFF symbols: Def. (line 6) 27045* DEC syntax: PDP-11-Syntax. (line 6) 27046* decimal integers: Integers. (line 12) 27047* def directive: Def. (line 6) 27048* def directive, TIC54X: TIC54X-Directives. (line 101) 27049* density instructions: Density Instructions. 27050 (line 6) 27051* dependency tracking: MD. (line 6) 27052* deprecated directives: Deprecated. (line 6) 27053* desc directive: Desc. (line 6) 27054* descriptor, of a.out symbol: Symbol Desc. (line 6) 27055* dfloat directive, VAX: VAX-directives. (line 9) 27056* difference tables altered: Word. (line 12) 27057* difference tables, warning: K. (line 6) 27058* differences, mmixal: MMIX-mmixal. (line 6) 27059* dim directive: Dim. (line 6) 27060* directives and instructions: Statements. (line 20) 27061* directives for PowerPC: PowerPC-Pseudo. (line 6) 27062* directives for SCORE: SCORE-Pseudo. (line 6) 27063* directives, Blackfin: Blackfin Directives. 27064 (line 6) 27065* directives, M32R: M32R-Directives. (line 6) 27066* directives, M680x0: M68K-Directives. (line 6) 27067* directives, machine independent: Pseudo Ops. (line 6) 27068* directives, Xtensa: Xtensa Directives. (line 6) 27069* directives, Z8000: Z8000 Directives. (line 6) 27070* Disable floating-point instructions: MIPS Floating-Point. 27071 (line 6) 27072* Disable single-precision floating-point operations: MIPS Floating-Point. 27073 (line 12) 27074* displacement sizing character, VAX: VAX-operands. (line 12) 27075* dollar local symbols: Symbol Names. (line 113) 27076* dot (symbol): Dot. (line 6) 27077* double directive: Double. (line 6) 27078* double directive, i386: i386-Float. (line 14) 27079* double directive, M680x0: M68K-Float. (line 14) 27080* double directive, M68HC11: M68HC11-Float. (line 14) 27081* double directive, RX: RX-Float. (line 11) 27082* double directive, TIC54X: TIC54X-Directives. (line 62) 27083* double directive, VAX: VAX-float. (line 15) 27084* double directive, x86-64: i386-Float. (line 14) 27085* double directive, XGATE: XGATE-Float. (line 13) 27086* doublequote (\"): Strings. (line 43) 27087* drlist directive, TIC54X: TIC54X-Directives. (line 71) 27088* drnolist directive, TIC54X: TIC54X-Directives. (line 71) 27089* ds directive: Ds. (line 6) 27090* DTP-relative data directives: RISC-V-Directives. (line 18) 27091* dword directive, BPF: BPF Directives. (line 15) 27092* dword directive, Nios II: Nios II Directives. (line 16) 27093* dword directive, PRU: PRU Directives. (line 13) 27094* EB command-line option, C-SKY: C-SKY Options. (line 18) 27095* EB command-line option, Nios II: Nios II Options. (line 22) 27096* ecr register, V850: V850-Regs. (line 78) 27097* eight-byte integer: Quad. (line 9) 27098* eight-byte integer <1>: 8byte. (line 6) 27099* eipc register, V850: V850-Regs. (line 70) 27100* eipsw register, V850: V850-Regs. (line 72) 27101* eject directive: Eject. (line 6) 27102* EL command-line option, C-SKY: C-SKY Options. (line 14) 27103* EL command-line option, Nios II: Nios II Options. (line 25) 27104* ELF symbol type: Type. (line 22) 27105* else directive: Else. (line 6) 27106* elseif directive: Elseif. (line 6) 27107* empty expressions: Empty Exprs. (line 6) 27108* emsg directive, TIC54X: TIC54X-Directives. (line 75) 27109* emulation: Overview. (line 1109) 27110* encoding options, i386: i386-Mnemonics. (line 34) 27111* encoding options, x86-64: i386-Mnemonics. (line 34) 27112* end directive: End. (line 6) 27113* endef directive: Endef. (line 6) 27114* endfunc directive: Endfunc. (line 6) 27115* endianness, MIPS: Overview. (line 855) 27116* endianness, PJ: Overview. (line 759) 27117* endif directive: Endif. (line 6) 27118* endloop directive, TIC54X: TIC54X-Directives. (line 141) 27119* endm directive: Macro. (line 137) 27120* endm directive, TIC54X: TIC54X-Directives. (line 151) 27121* endproc directive, OpenRISC: OpenRISC-Directives. 27122 (line 24) 27123* endstruct directive, TIC54X: TIC54X-Directives. (line 214) 27124* endunion directive, TIC54X: TIC54X-Directives. (line 248) 27125* environment settings, TIC54X: TIC54X-Env. (line 6) 27126* EOF, newline must precede: Statements. (line 14) 27127* ep register, V850: V850-Regs. (line 66) 27128* Epiphany line comment character: Epiphany-Chars. (line 6) 27129* Epiphany line separator: Epiphany-Chars. (line 14) 27130* Epiphany options: Epiphany Options. (line 6) 27131* Epiphany support: Epiphany-Dependent. (line 6) 27132* equ directive: Equ. (line 6) 27133* equ directive, TIC54X: TIC54X-Directives. (line 189) 27134* equiv directive: Equiv. (line 6) 27135* eqv directive: Eqv. (line 6) 27136* err directive: Err. (line 6) 27137* error directive: Error. (line 6) 27138* error messages: Errors. (line 6) 27139* error on valid input: Bug Criteria. (line 12) 27140* errors, caused by warnings: W. (line 16) 27141* errors, continuing after: Z. (line 6) 27142* escape codes, character: Strings. (line 15) 27143* eval directive, TIC54X: TIC54X-Directives. (line 22) 27144* even: Z8000 Directives. (line 58) 27145* even directive, M680x0: M68K-Directives. (line 15) 27146* even directive, TIC54X: TIC54X-Directives. (line 6) 27147* Exception Cause Register, ARC: ARC-Regs. (line 63) 27148* Exception Return Address, ARC: ARC-Regs. (line 76) 27149* exitm directive: Macro. (line 140) 27150* expr (internal section): As Sections. (line 17) 27151* expression arguments: Arguments. (line 6) 27152* expressions: Expressions. (line 6) 27153* expressions, comparison: Infix Ops. (line 56) 27154* expressions, empty: Empty Exprs. (line 6) 27155* expressions, integer: Integer Exprs. (line 6) 27156* extAuxRegister directive, ARC: ARC Directives. (line 105) 27157* extCondCode directive, ARC: ARC Directives. (line 126) 27158* extCoreRegister directive, ARC: ARC Directives. (line 137) 27159* extend directive M680x0: M68K-Float. (line 17) 27160* extend directive M68HC11: M68HC11-Float. (line 17) 27161* extend directive XGATE: XGATE-Float. (line 16) 27162* extension core registers, ARC: ARC-Regs. (line 38) 27163* extern directive: Extern. (line 6) 27164* extInstruction directive, ARC: ARC Directives. (line 164) 27165* fail directive: Fail. (line 6) 27166* far_mode directive, TIC54X: TIC54X-Directives. (line 80) 27167* faster processing (-f): f. (line 6) 27168* fatal signal: Bug Criteria. (line 9) 27169* fclist directive, TIC54X: TIC54X-Directives. (line 85) 27170* fcnolist directive, TIC54X: TIC54X-Directives. (line 85) 27171* fepc register, V850: V850-Regs. (line 74) 27172* fepsw register, V850: V850-Regs. (line 76) 27173* ffloat directive, VAX: VAX-directives. (line 13) 27174* field directive, TIC54X: TIC54X-Directives. (line 89) 27175* file directive: File. (line 6) 27176* file directive, MSP 430: MSP430 Directives. (line 6) 27177* file name, logical: File. (line 13) 27178* file names and line numbers, in warnings/errors: Errors. (line 16) 27179* files, including: Include. (line 6) 27180* files, input: Input Files. (line 6) 27181* fill directive: Fill. (line 6) 27182* filling memory: Skip. (line 6) 27183* filling memory <1>: Space. (line 6) 27184* filling memory with no-op instructions: Nops. (line 6) 27185* filling memory with zero bytes: Zero. (line 6) 27186* FLIX syntax: Xtensa Syntax. (line 6) 27187* float directive: Float. (line 6) 27188* float directive, i386: i386-Float. (line 14) 27189* float directive, M680x0: M68K-Float. (line 11) 27190* float directive, M68HC11: M68HC11-Float. (line 11) 27191* float directive, RX: RX-Float. (line 8) 27192* float directive, TIC54X: TIC54X-Directives. (line 62) 27193* float directive, VAX: VAX-float. (line 15) 27194* float directive, x86-64: i386-Float. (line 14) 27195* float directive, XGATE: XGATE-Float. (line 10) 27196* floating point numbers: Flonums. (line 6) 27197* floating point numbers (double): Double. (line 6) 27198* floating point numbers (single): Float. (line 6) 27199* floating point numbers (single) <1>: Single. (line 6) 27200* floating point, AArch64 (IEEE): AArch64 Floating Point. 27201 (line 6) 27202* floating point, Alpha (IEEE): Alpha Floating Point. 27203 (line 6) 27204* floating point, ARM (IEEE): ARM Floating Point. (line 6) 27205* floating point, D10V: D10V-Float. (line 6) 27206* floating point, D30V: D30V-Float. (line 6) 27207* floating point, H8/300 (IEEE): H8/300 Floating Point. 27208 (line 6) 27209* floating point, HPPA (IEEE): HPPA Floating Point. 27210 (line 6) 27211* floating point, i386: i386-Float. (line 6) 27212* floating point, M680x0: M68K-Float. (line 6) 27213* floating point, M68HC11: M68HC11-Float. (line 6) 27214* floating point, MSP 430 (IEEE): MSP430 Floating Point. 27215 (line 6) 27216* floating point, OPENRISC (IEEE): OpenRISC-Float. (line 6) 27217* floating point, RX: RX-Float. (line 6) 27218* floating point, s390: s390 Floating Point. 27219 (line 6) 27220* floating point, SH (IEEE): SH Floating Point. (line 6) 27221* floating point, SPARC (IEEE): Sparc-Float. (line 6) 27222* floating point, V850 (IEEE): V850 Floating Point. 27223 (line 6) 27224* floating point, VAX: VAX-float. (line 6) 27225* floating point, WebAssembly (IEEE): WebAssembly-Floating-Point. 27226 (line 6) 27227* floating point, x86-64: i386-Float. (line 6) 27228* floating point, XGATE: XGATE-Float. (line 6) 27229* floating point, Z80: Z80 Floating Point. (line 6) 27230* flonums: Flonums. (line 6) 27231* force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 27232* format of error messages: Errors. (line 38) 27233* format of warning messages: Errors. (line 12) 27234* formfeed (\f): Strings. (line 18) 27235* four-byte integer: 4byte. (line 6) 27236* fpic command-line option, C-SKY: C-SKY Options. (line 22) 27237* frame pointer, ARC: ARC-Regs. (line 17) 27238* func directive: Func. (line 6) 27239* functions, in expressions: Operators. (line 6) 27240* gfloat directive, VAX: VAX-directives. (line 17) 27241* global: Z8000 Directives. (line 21) 27242* global directive: Global. (line 6) 27243* global directive, TIC54X: TIC54X-Directives. (line 101) 27244* global pointer, ARC: ARC-Regs. (line 14) 27245* got directive, Nios II: Nios II Relocations. 27246 (line 38) 27247* gotoff directive, Nios II: Nios II Relocations. 27248 (line 38) 27249* gotoff_hiadj directive, Nios II: Nios II Relocations. 27250 (line 38) 27251* gotoff_lo directive, Nios II: Nios II Relocations. 27252 (line 38) 27253* got_hiadj directive, Nios II: Nios II Relocations. 27254 (line 38) 27255* got_lo directive, Nios II: Nios II Relocations. 27256 (line 38) 27257* gp register, MIPS: MIPS Small Data. (line 6) 27258* gp register, V850: V850-Regs. (line 14) 27259* gprel directive, Nios II: Nios II Relocations. 27260 (line 26) 27261* grouping data: Sub-Sections. (line 6) 27262* H8/300 addressing modes: H8/300-Addressing. (line 6) 27263* H8/300 floating point (IEEE): H8/300 Floating Point. 27264 (line 6) 27265* H8/300 line comment character: H8/300-Chars. (line 6) 27266* H8/300 line separator: H8/300-Chars. (line 8) 27267* H8/300 machine directives (none): H8/300 Directives. (line 6) 27268* H8/300 opcode summary: H8/300 Opcodes. (line 6) 27269* H8/300 options: H8/300 Options. (line 6) 27270* H8/300 registers: H8/300-Regs. (line 6) 27271* H8/300 size suffixes: H8/300 Opcodes. (line 160) 27272* H8/300 support: H8/300-Dependent. (line 6) 27273* H8/300H, assembling for: H8/300 Directives. (line 8) 27274* half directive, BPF: BPF Directives. (line 9) 27275* half directive, Nios II: Nios II Directives. (line 10) 27276* half directive, SPARC: Sparc-Directives. (line 17) 27277* half directive, TIC54X: TIC54X-Directives. (line 109) 27278* hex character code (\XD...): Strings. (line 36) 27279* hexadecimal integers: Integers. (line 15) 27280* hexadecimal prefix, S12Z: S12Z Options. (line 17) 27281* hexadecimal prefix, Z80: Z80-Chars. (line 15) 27282* hfloat directive, VAX: VAX-directives. (line 21) 27283* hi directive, Nios II: Nios II Relocations. 27284 (line 20) 27285* hi pseudo-op, V850: V850 Opcodes. (line 33) 27286* hi0 pseudo-op, V850: V850 Opcodes. (line 10) 27287* hiadj directive, Nios II: Nios II Relocations. 27288 (line 6) 27289* hidden directive: Hidden. (line 6) 27290* high directive, M32R: M32R-Directives. (line 18) 27291* hilo pseudo-op, V850: V850 Opcodes. (line 55) 27292* HPPA directives not supported: HPPA Directives. (line 11) 27293* HPPA floating point (IEEE): HPPA Floating Point. 27294 (line 6) 27295* HPPA Syntax: HPPA Options. (line 7) 27296* HPPA-only directives: HPPA Directives. (line 24) 27297* hword directive: hword. (line 6) 27298* i386 16-bit code: i386-16bit. (line 6) 27299* i386 arch directive: i386-Arch. (line 6) 27300* i386 att_syntax pseudo op: i386-Variations. (line 6) 27301* i386 conversion instructions: i386-Mnemonics. (line 56) 27302* i386 floating point: i386-Float. (line 6) 27303* i386 immediate operands: i386-Variations. (line 15) 27304* i386 instruction naming: i386-Mnemonics. (line 9) 27305* i386 instruction prefixes: i386-Prefixes. (line 6) 27306* i386 intel_syntax pseudo op: i386-Variations. (line 6) 27307* i386 jump optimization: i386-Jumps. (line 6) 27308* i386 jump, call, return: i386-Variations. (line 45) 27309* i386 jump/call operands: i386-Variations. (line 15) 27310* i386 line comment character: i386-Chars. (line 6) 27311* i386 line separator: i386-Chars. (line 18) 27312* i386 memory references: i386-Memory. (line 6) 27313* i386 mnemonic compatibility: i386-Mnemonics. (line 81) 27314* i386 mul, imul instructions: i386-Notes. (line 6) 27315* i386 options: i386-Options. (line 6) 27316* i386 register operands: i386-Variations. (line 15) 27317* i386 registers: i386-Regs. (line 6) 27318* i386 sections: i386-Variations. (line 51) 27319* i386 size suffixes: i386-Variations. (line 28) 27320* i386 source, destination operands: i386-Variations. (line 21) 27321* i386 support: i386-Dependent. (line 6) 27322* i386 syntax compatibility: i386-Variations. (line 6) 27323* i80386 support: i386-Dependent. (line 6) 27324* IA-64 line comment character: IA-64-Chars. (line 6) 27325* IA-64 line separator: IA-64-Chars. (line 8) 27326* IA-64 options: IA-64 Options. (line 6) 27327* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 27328* IA-64 registers: IA-64-Regs. (line 6) 27329* IA-64 relocations: IA-64-Relocs. (line 6) 27330* IA-64 support: IA-64-Dependent. (line 6) 27331* IA-64 Syntax: IA-64 Options. (line 85) 27332* ident directive: Ident. (line 6) 27333* identifiers, ARM: ARM-Chars. (line 19) 27334* identifiers, MSP 430: MSP430-Chars. (line 17) 27335* if directive: If. (line 6) 27336* ifb directive: If. (line 21) 27337* ifc directive: If. (line 25) 27338* ifdef directive: If. (line 16) 27339* ifeq directive: If. (line 33) 27340* ifeqs directive: If. (line 36) 27341* ifge directive: If. (line 40) 27342* ifgt directive: If. (line 44) 27343* ifle directive: If. (line 48) 27344* iflt directive: If. (line 52) 27345* ifnb directive: If. (line 56) 27346* ifnc directive: If. (line 61) 27347* ifndef directive: If. (line 65) 27348* ifne directive: If. (line 72) 27349* ifnes directive: If. (line 76) 27350* ifnotdef directive: If. (line 65) 27351* immediate character, AArch64: AArch64-Chars. (line 13) 27352* immediate character, ARM: ARM-Chars. (line 17) 27353* immediate character, M680x0: M68K-Chars. (line 13) 27354* immediate character, VAX: VAX-operands. (line 6) 27355* immediate fields, relaxation: Xtensa Immediate Relaxation. 27356 (line 6) 27357* immediate operands, i386: i386-Variations. (line 15) 27358* immediate operands, x86-64: i386-Variations. (line 15) 27359* imul instruction, i386: i386-Notes. (line 6) 27360* imul instruction, x86-64: i386-Notes. (line 6) 27361* incbin directive: Incbin. (line 6) 27362* include directive: Include. (line 6) 27363* include directive search path: I. (line 6) 27364* indirect character, VAX: VAX-operands. (line 9) 27365* infix operators: Infix Ops. (line 6) 27366* inhibiting interrupts, i386: i386-Prefixes. (line 36) 27367* input: Input Files. (line 6) 27368* input file linenumbers: Input Files. (line 35) 27369* INSN directives: RISC-V-Directives. (line 88) 27370* instruction aliases, s390: s390 Aliases. (line 6) 27371* instruction bundle: Bundle directives. (line 9) 27372* instruction expansion, CRIS: CRIS-Expand. (line 6) 27373* instruction expansion, MMIX: MMIX-Expand. (line 6) 27374* instruction formats, risc-v: RISC-V-Formats. (line 6) 27375* instruction formats, s390: s390 Formats. (line 6) 27376* instruction marker, s390: s390 Instruction Marker. 27377 (line 6) 27378* instruction mnemonics, s390: s390 Mnemonics. (line 6) 27379* instruction naming, i386: i386-Mnemonics. (line 9) 27380* instruction naming, x86-64: i386-Mnemonics. (line 9) 27381* instruction operand modifier, s390: s390 Operand Modifier. 27382 (line 6) 27383* instruction operands, s390: s390 Operands. (line 6) 27384* instruction prefixes, i386: i386-Prefixes. (line 6) 27385* instruction set, M680x0: M68K-opcodes. (line 6) 27386* instruction set, M68HC11: M68HC11-opcodes. (line 6) 27387* instruction set, XGATE: XGATE-opcodes. (line 5) 27388* instruction summary, AVR: AVR Opcodes. (line 6) 27389* instruction summary, D10V: D10V-Opcodes. (line 6) 27390* instruction summary, D30V: D30V-Opcodes. (line 6) 27391* instruction summary, H8/300: H8/300 Opcodes. (line 6) 27392* instruction summary, LM32: LM32 Opcodes. (line 6) 27393* instruction summary, LM32 <1>: OpenRISC-Opcodes. (line 6) 27394* instruction summary, SH: SH Opcodes. (line 6) 27395* instruction summary, Z8000: Z8000 Opcodes. (line 6) 27396* instruction syntax, s390: s390 Syntax. (line 6) 27397* instructions and directives: Statements. (line 20) 27398* int directive: Int. (line 6) 27399* int directive, H8/300: H8/300 Directives. (line 6) 27400* int directive, i386: i386-Float. (line 21) 27401* int directive, TIC54X: TIC54X-Directives. (line 109) 27402* int directive, x86-64: i386-Float. (line 21) 27403* integer expressions: Integer Exprs. (line 6) 27404* integer, 16-byte: Octa. (line 6) 27405* integer, 2-byte: 2byte. (line 6) 27406* integer, 4-byte: 4byte. (line 6) 27407* integer, 8-byte: Quad. (line 9) 27408* integer, 8-byte <1>: 8byte. (line 6) 27409* integers: Integers. (line 6) 27410* integers, 16-bit: hword. (line 6) 27411* integers, 32-bit: Int. (line 6) 27412* integers, binary: Integers. (line 6) 27413* integers, decimal: Integers. (line 12) 27414* integers, hexadecimal: Integers. (line 15) 27415* integers, octal: Integers. (line 9) 27416* integers, one byte: Byte. (line 6) 27417* intel_syntax pseudo op, i386: i386-Variations. (line 6) 27418* intel_syntax pseudo op, x86-64: i386-Variations. (line 6) 27419* internal assembler sections: As Sections. (line 6) 27420* internal directive: Internal. (line 6) 27421* interrupt link register, ARC: ARC-Regs. (line 27) 27422* Interrupt Vector Base address, ARC: ARC-Regs. (line 66) 27423* invalid input: Bug Criteria. (line 14) 27424* invocation summary: Overview. (line 6) 27425* IP2K architecture options: IP2K-Opts. (line 9) 27426* IP2K architecture options <1>: IP2K-Opts. (line 14) 27427* IP2K line comment character: IP2K-Chars. (line 6) 27428* IP2K line separator: IP2K-Chars. (line 14) 27429* IP2K options: IP2K-Opts. (line 6) 27430* IP2K support: IP2K-Dependent. (line 6) 27431* irp directive: Irp. (line 6) 27432* irpc directive: Irpc. (line 6) 27433* joining text and data sections: R. (line 6) 27434* jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 27435* jump instructions, i386: i386-Mnemonics. (line 75) 27436* jump instructions, relaxation: Xtensa Jump Relaxation. 27437 (line 6) 27438* jump instructions, x86-64: i386-Mnemonics. (line 75) 27439* jump optimization, i386: i386-Jumps. (line 6) 27440* jump optimization, x86-64: i386-Jumps. (line 6) 27441* jump/call operands, i386: i386-Variations. (line 15) 27442* jump/call operands, x86-64: i386-Variations. (line 15) 27443* Known undocumented instructions: Z80 Options. (line 103) 27444* L16SI instructions, relaxation: Xtensa Immediate Relaxation. 27445 (line 23) 27446* L16UI instructions, relaxation: Xtensa Immediate Relaxation. 27447 (line 23) 27448* L32I instructions, relaxation: Xtensa Immediate Relaxation. 27449 (line 23) 27450* L8UI instructions, relaxation: Xtensa Immediate Relaxation. 27451 (line 23) 27452* label (:): Statements. (line 31) 27453* label directive, TIC54X: TIC54X-Directives. (line 121) 27454* labels: Labels. (line 6) 27455* labels, Z80: Z80-Labels. (line 6) 27456* largecomm directive, ELF: i386-Directives. (line 17) 27457* lcomm directive: Lcomm. (line 6) 27458* lcomm directive <1>: ARC Directives. (line 9) 27459* lcomm directive, COFF: i386-Directives. (line 6) 27460* lcommon directive, ARC: ARC Directives. (line 24) 27461* ld: Object. (line 15) 27462* ldouble directive M680x0: M68K-Float. (line 17) 27463* ldouble directive M68HC11: M68HC11-Float. (line 17) 27464* ldouble directive XGATE: XGATE-Float. (line 16) 27465* ldouble directive, TIC54X: TIC54X-Directives. (line 62) 27466* LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9) 27467* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 27468* LEB128 directives: RISC-V-Directives. (line 27) 27469* length directive, TIC54X: TIC54X-Directives. (line 125) 27470* length of symbols: Symbol Intro. (line 19) 27471* level 1 interrupt link register, ARC: ARC-Regs. (line 23) 27472* level 2 interrupt link register, ARC: ARC-Regs. (line 31) 27473* lflags directive (ignored): Lflags. (line 6) 27474* line: ARC-Chars. (line 30) 27475* line comment character: Comments. (line 19) 27476* line comment character, AArch64: AArch64-Chars. (line 6) 27477* line comment character, Alpha: Alpha-Chars. (line 6) 27478* line comment character, ARC: ARC-Chars. (line 11) 27479* line comment character, ARM: ARM-Chars. (line 6) 27480* line comment character, AVR: AVR-Chars. (line 6) 27481* line comment character, BPF: BPF-Chars. (line 6) 27482* line comment character, CR16: CR16-Chars. (line 6) 27483* line comment character, D10V: D10V-Chars. (line 6) 27484* line comment character, D30V: D30V-Chars. (line 6) 27485* line comment character, Epiphany: Epiphany-Chars. (line 6) 27486* line comment character, H8/300: H8/300-Chars. (line 6) 27487* line comment character, i386: i386-Chars. (line 6) 27488* line comment character, IA-64: IA-64-Chars. (line 6) 27489* line comment character, IP2K: IP2K-Chars. (line 6) 27490* line comment character, LM32: LM32-Chars. (line 6) 27491* line comment character, M32C: M32C-Chars. (line 6) 27492* line comment character, M680x0: M68K-Chars. (line 6) 27493* line comment character, M68HC11: M68HC11-Syntax. (line 17) 27494* line comment character, Meta: Meta-Chars. (line 6) 27495* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6) 27496* line comment character, MIPS: MIPS-Chars. (line 6) 27497* line comment character, MSP 430: MSP430-Chars. (line 6) 27498* line comment character, Nios II: Nios II Chars. (line 6) 27499* line comment character, NS32K: NS32K-Chars. (line 6) 27500* line comment character, OpenRISC: OpenRISC-Chars. (line 6) 27501* line comment character, PJ: PJ-Chars. (line 6) 27502* line comment character, PowerPC: PowerPC-Chars. (line 6) 27503* line comment character, PRU: PRU Chars. (line 6) 27504* line comment character, RL78: RL78-Chars. (line 6) 27505* line comment character, RX: RX-Chars. (line 6) 27506* line comment character, S12Z: S12Z Syntax Overview. 27507 (line 32) 27508* line comment character, s390: s390 Characters. (line 6) 27509* line comment character, SCORE: SCORE-Chars. (line 6) 27510* line comment character, SH: SH-Chars. (line 6) 27511* line comment character, Sparc: Sparc-Chars. (line 6) 27512* line comment character, TIC54X: TIC54X-Chars. (line 6) 27513* line comment character, TIC6X: TIC6X Syntax. (line 6) 27514* line comment character, V850: V850-Chars. (line 6) 27515* line comment character, VAX: VAX-Chars. (line 6) 27516* line comment character, Visium: Visium Characters. (line 6) 27517* line comment character, WebAssembly: WebAssembly-Chars. (line 6) 27518* line comment character, XGATE: XGATE-Syntax. (line 16) 27519* line comment character, XStormy16: XStormy16-Chars. (line 6) 27520* line comment character, Z80: Z80-Chars. (line 6) 27521* line comment character, Z8000: Z8000-Chars. (line 6) 27522* line comment characters, CRIS: CRIS-Chars. (line 6) 27523* line comment characters, MMIX: MMIX-Chars. (line 6) 27524* line directive: Line. (line 6) 27525* line directive, MSP 430: MSP430 Directives. (line 14) 27526* line numbers, in input files: Input Files. (line 35) 27527* line separator character: Statements. (line 6) 27528* line separator character, Nios II: Nios II Chars. (line 6) 27529* line separator, AArch64: AArch64-Chars. (line 10) 27530* line separator, Alpha: Alpha-Chars. (line 11) 27531* line separator, ARC: ARC-Chars. (line 27) 27532* line separator, ARM: ARM-Chars. (line 14) 27533* line separator, AVR: AVR-Chars. (line 14) 27534* line separator, CR16: CR16-Chars. (line 12) 27535* line separator, Epiphany: Epiphany-Chars. (line 14) 27536* line separator, H8/300: H8/300-Chars. (line 8) 27537* line separator, i386: i386-Chars. (line 18) 27538* line separator, IA-64: IA-64-Chars. (line 8) 27539* line separator, IP2K: IP2K-Chars. (line 14) 27540* line separator, LM32: LM32-Chars. (line 12) 27541* line separator, M32C: M32C-Chars. (line 14) 27542* line separator, M680x0: M68K-Chars. (line 20) 27543* line separator, M68HC11: M68HC11-Syntax. (line 26) 27544* line separator, Meta: Meta-Chars. (line 8) 27545* line separator, MicroBlaze: MicroBlaze-Chars. (line 14) 27546* line separator, MIPS: MIPS-Chars. (line 14) 27547* line separator, MSP 430: MSP430-Chars. (line 14) 27548* line separator, NS32K: NS32K-Chars. (line 18) 27549* line separator, OpenRISC: OpenRISC-Chars. (line 9) 27550* line separator, PJ: PJ-Chars. (line 14) 27551* line separator, PowerPC: PowerPC-Chars. (line 18) 27552* line separator, RL78: RL78-Chars. (line 14) 27553* line separator, RX: RX-Chars. (line 14) 27554* line separator, S12Z: S12Z Syntax Overview. 27555 (line 41) 27556* line separator, s390: s390 Characters. (line 13) 27557* line separator, SCORE: SCORE-Chars. (line 14) 27558* line separator, SH: SH-Chars. (line 8) 27559* line separator, Sparc: Sparc-Chars. (line 14) 27560* line separator, TIC54X: TIC54X-Chars. (line 17) 27561* line separator, TIC6X: TIC6X Syntax. (line 13) 27562* line separator, V850: V850-Chars. (line 13) 27563* line separator, VAX: VAX-Chars. (line 14) 27564* line separator, Visium: Visium Characters. (line 14) 27565* line separator, XGATE: XGATE-Syntax. (line 25) 27566* line separator, XStormy16: XStormy16-Chars. (line 14) 27567* line separator, Z80: Z80-Chars. (line 13) 27568* line separator, Z8000: Z8000-Chars. (line 13) 27569* lines starting with #: Comments. (line 33) 27570* link register, ARC: ARC-Regs. (line 35) 27571* linker: Object. (line 15) 27572* linker, and assembler: Secs Background. (line 10) 27573* linkonce directive: Linkonce. (line 6) 27574* list directive: List. (line 6) 27575* list directive, TIC54X: TIC54X-Directives. (line 129) 27576* listing control, turning off: Nolist. (line 6) 27577* listing control, turning on: List. (line 6) 27578* listing control: new page: Eject. (line 6) 27579* listing control: paper size: Psize. (line 6) 27580* listing control: subtitle: Sbttl. (line 6) 27581* listing control: title line: Title. (line 6) 27582* listings, enabling: a. (line 6) 27583* literal directive: Literal Directive. (line 6) 27584* literal pool entries, s390: s390 Literal Pool Entries. 27585 (line 6) 27586* literal_position directive: Literal Position Directive. 27587 (line 6) 27588* literal_prefix directive: Literal Prefix Directive. 27589 (line 6) 27590* little endian output, MIPS: Overview. (line 858) 27591* little endian output, PJ: Overview. (line 762) 27592* little-endian output, MIPS: MIPS Options. (line 13) 27593* little-endian output, TIC6X: TIC6X Options. (line 46) 27594* LM32 line comment character: LM32-Chars. (line 6) 27595* LM32 line separator: LM32-Chars. (line 12) 27596* LM32 modifiers: LM32-Modifiers. (line 6) 27597* LM32 opcode summary: LM32 Opcodes. (line 6) 27598* LM32 options (none): LM32 Options. (line 6) 27599* LM32 register names: LM32-Regs. (line 6) 27600* LM32 support: LM32-Dependent. (line 6) 27601* ln directive: Ln. (line 6) 27602* lo directive, Nios II: Nios II Relocations. 27603 (line 23) 27604* lo pseudo-op, V850: V850 Opcodes. (line 22) 27605* loc directive: Loc. (line 6) 27606* local common symbols: Lcomm. (line 6) 27607* local directive: Local. (line 6) 27608* local labels: Symbol Names. (line 43) 27609* local symbol names: Symbol Names. (line 30) 27610* local symbols, retaining in output: L. (line 6) 27611* location counter: Dot. (line 6) 27612* location counter, advancing: Org. (line 6) 27613* location counter, Z80: Z80-Chars. (line 15) 27614* loc_mark_labels directive: Loc_mark_labels. (line 6) 27615* logical file name: File. (line 13) 27616* logical line number: Line. (line 6) 27617* logical line numbers: Comments. (line 33) 27618* long directive: Long. (line 6) 27619* long directive, i386: i386-Float. (line 21) 27620* long directive, TIC54X: TIC54X-Directives. (line 133) 27621* long directive, x86-64: i386-Float. (line 21) 27622* longcall pseudo-op, V850: V850 Opcodes. (line 122) 27623* longcalls directive: Longcalls Directive. 27624 (line 6) 27625* longjump pseudo-op, V850: V850 Opcodes. (line 128) 27626* Loongson Content Address Memory (CAM) generation override: MIPS ASE Instruction Generation Overrides. 27627 (line 81) 27628* Loongson EXTensions (EXT) instructions generation override: MIPS ASE Instruction Generation Overrides. 27629 (line 86) 27630* Loongson EXTensions R2 (EXT2) instructions generation override: MIPS ASE Instruction Generation Overrides. 27631 (line 91) 27632* Loongson MultiMedia extensions Instructions (MMI) generation override: MIPS ASE Instruction Generation Overrides. 27633 (line 76) 27634* loop counter, ARC: ARC-Regs. (line 41) 27635* loop directive, TIC54X: TIC54X-Directives. (line 141) 27636* LOOP instructions, alignment: Xtensa Automatic Alignment. 27637 (line 6) 27638* low directive, M32R: M32R-Directives. (line 9) 27639* lp register, V850: V850-Regs. (line 68) 27640* lval: Z8000 Directives. (line 27) 27641* LWP, i386: i386-LWP. (line 6) 27642* LWP, x86-64: i386-LWP. (line 6) 27643* M16C architecture option: M32C-Opts. (line 12) 27644* M32C architecture option: M32C-Opts. (line 9) 27645* M32C line comment character: M32C-Chars. (line 6) 27646* M32C line separator: M32C-Chars. (line 14) 27647* M32C modifiers: M32C-Modifiers. (line 6) 27648* M32C options: M32C-Opts. (line 6) 27649* M32C support: M32C-Dependent. (line 6) 27650* M32R architecture options: M32R-Opts. (line 9) 27651* M32R architecture options <1>: M32R-Opts. (line 17) 27652* M32R architecture options <2>: M32R-Opts. (line 21) 27653* M32R directives: M32R-Directives. (line 6) 27654* M32R options: M32R-Opts. (line 6) 27655* M32R support: M32R-Dependent. (line 6) 27656* M32R warnings: M32R-Warnings. (line 6) 27657* M680x0 addressing modes: M68K-Syntax. (line 21) 27658* M680x0 architecture options: M68K-Opts. (line 99) 27659* M680x0 branch improvement: M68K-Branch. (line 6) 27660* M680x0 directives: M68K-Directives. (line 6) 27661* M680x0 floating point: M68K-Float. (line 6) 27662* M680x0 immediate character: M68K-Chars. (line 13) 27663* M680x0 line comment character: M68K-Chars. (line 6) 27664* M680x0 line separator: M68K-Chars. (line 20) 27665* M680x0 opcodes: M68K-opcodes. (line 6) 27666* M680x0 options: M68K-Opts. (line 6) 27667* M680x0 pseudo-opcodes: M68K-Branch. (line 6) 27668* M680x0 size modifiers: M68K-Syntax. (line 8) 27669* M680x0 support: M68K-Dependent. (line 6) 27670* M680x0 syntax: M68K-Syntax. (line 8) 27671* M68HC11 addressing modes: M68HC11-Syntax. (line 29) 27672* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 27673* M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 27674* M68HC11 assembler directive .interrupt: M68HC11-Directives. 27675 (line 26) 27676* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 27677* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 27678* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 27679* M68HC11 assembler directives: M68HC11-Directives. (line 6) 27680* M68HC11 branch improvement: M68HC11-Branch. (line 6) 27681* M68HC11 floating point: M68HC11-Float. (line 6) 27682* M68HC11 line comment character: M68HC11-Syntax. (line 17) 27683* M68HC11 line separator: M68HC11-Syntax. (line 26) 27684* M68HC11 modifiers: M68HC11-Modifiers. (line 6) 27685* M68HC11 opcodes: M68HC11-opcodes. (line 6) 27686* M68HC11 options: M68HC11-Opts. (line 6) 27687* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 27688* M68HC11 syntax: M68HC11-Syntax. (line 6) 27689* M68HC12 assembler directives: M68HC11-Directives. (line 6) 27690* mA6 command-line option, ARC: ARC Options. (line 14) 27691* mA7 command-line option, ARC: ARC Options. (line 39) 27692* machine dependencies: Machine Dependencies. 27693 (line 6) 27694* machine directives, AArch64: AArch64 Directives. (line 6) 27695* machine directives, ARC: ARC Directives. (line 6) 27696* machine directives, ARM: ARM Directives. (line 6) 27697* machine directives, BPF: BPF Directives. (line 6) 27698* machine directives, H8/300 (none): H8/300 Directives. (line 6) 27699* machine directives, MSP 430: MSP430 Directives. (line 6) 27700* machine directives, Nios II: Nios II Directives. (line 6) 27701* machine directives, OPENRISC: OpenRISC-Directives. 27702 (line 6) 27703* machine directives, PRU: PRU Directives. (line 6) 27704* machine directives, RISC-V: RISC-V-Directives. (line 6) 27705* machine directives, SH: SH Directives. (line 6) 27706* machine directives, SPARC: Sparc-Directives. (line 6) 27707* machine directives, TIC54X: TIC54X-Directives. (line 6) 27708* machine directives, TIC6X: TIC6X Directives. (line 6) 27709* machine directives, TILE-Gx: TILE-Gx Directives. (line 6) 27710* machine directives, TILEPro: TILEPro Directives. (line 6) 27711* machine directives, V850: V850 Directives. (line 6) 27712* machine directives, VAX: VAX-directives. (line 6) 27713* machine directives, x86: i386-Directives. (line 6) 27714* machine directives, XStormy16: XStormy16 Directives. 27715 (line 6) 27716* machine independent directives: Pseudo Ops. (line 6) 27717* machine instructions (not covered): Manual. (line 14) 27718* machine relocations, Nios II: Nios II Relocations. 27719 (line 6) 27720* machine relocations, PRU: PRU Relocations. (line 6) 27721* machine-independent syntax: Syntax. (line 6) 27722* macro directive: Macro. (line 28) 27723* macro directive, TIC54X: TIC54X-Directives. (line 151) 27724* macros: Macro. (line 6) 27725* macros, count executed: Macro. (line 142) 27726* Macros, MSP 430: MSP430-Macros. (line 6) 27727* macros, TIC54X: TIC54X-Macros. (line 6) 27728* make rules: MD. (line 6) 27729* manual, structure and purpose: Manual. (line 6) 27730* marc600 command-line option, ARC: ARC Options. (line 14) 27731* mARC601 command-line option, ARC: ARC Options. (line 27) 27732* mARC700 command-line option, ARC: ARC Options. (line 39) 27733* march command-line option, C-SKY: C-SKY Options. (line 6) 27734* march command-line option, Nios II: Nios II Options. (line 28) 27735* math builtins, TIC54X: TIC54X-Builtins. (line 6) 27736* Maximum number of continuation lines: listing. (line 34) 27737* mbig-endian command-line option, C-SKY: C-SKY Options. (line 18) 27738* mbranch-stub command-line option, C-SKY: C-SKY Options. (line 34) 27739* mcache command-line option, C-SKY: C-SKY Options. (line 100) 27740* mcp command-line option, C-SKY: C-SKY Options. (line 97) 27741* mcpu command-line option, C-SKY: C-SKY Options. (line 10) 27742* mdsp command-line option, C-SKY: C-SKY Options. (line 109) 27743* medsp command-line option, C-SKY: C-SKY Options. (line 112) 27744* melrw command-line option, C-SKY: C-SKY Options. (line 64) 27745* mEM command-line option, ARC: ARC Options. (line 42) 27746* memory references, i386: i386-Memory. (line 6) 27747* memory references, x86-64: i386-Memory. (line 6) 27748* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 27749* merging text and data sections: R. (line 6) 27750* messages from assembler: Errors. (line 6) 27751* Meta architectures: Meta Options. (line 6) 27752* Meta line comment character: Meta-Chars. (line 6) 27753* Meta line separator: Meta-Chars. (line 8) 27754* Meta options: Meta Options. (line 6) 27755* Meta registers: Meta-Regs. (line 6) 27756* Meta support: Meta-Dependent. (line 6) 27757* mforce2bsr command-line option, C-SKY: C-SKY Options. (line 43) 27758* mhard-float command-line option, C-SKY: C-SKY Options. (line 91) 27759* mHS command-line option, ARC: ARC Options. (line 64) 27760* MicroBlaze architectures: MicroBlaze-Dependent. 27761 (line 6) 27762* MicroBlaze directives: MicroBlaze Directives. 27763 (line 6) 27764* MicroBlaze line comment character: MicroBlaze-Chars. (line 6) 27765* MicroBlaze line separator: MicroBlaze-Chars. (line 14) 27766* MicroBlaze support: MicroBlaze-Dependent. 27767 (line 12) 27768* minus, permitted arguments: Infix Ops. (line 50) 27769* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options. 27770 (line 18) 27771* MIPS architecture options: MIPS Options. (line 29) 27772* MIPS big-endian output: MIPS Options. (line 13) 27773* MIPS CPU override: MIPS ISA. (line 18) 27774* MIPS cyclic redundancy check (CRC) instruction generation override: MIPS ASE Instruction Generation Overrides. 27775 (line 68) 27776* MIPS directives to override command-line options: MIPS assembly options. 27777 (line 6) 27778* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides. 27779 (line 21) 27780* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides. 27781 (line 26) 27782* MIPS DSP Release 3 instruction generation override: MIPS ASE Instruction Generation Overrides. 27783 (line 31) 27784* MIPS endianness: Overview. (line 855) 27785* MIPS eXtended Physical Address (XPA) instruction generation override: MIPS ASE Instruction Generation Overrides. 27786 (line 57) 27787* MIPS Global INValidate (GINV) instruction generation override: MIPS ASE Instruction Generation Overrides. 27788 (line 72) 27789* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings. 27790 (line 6) 27791* MIPS ISA: Overview. (line 861) 27792* MIPS ISA override: MIPS ISA. (line 6) 27793* MIPS line comment character: MIPS-Chars. (line 6) 27794* MIPS line separator: MIPS-Chars. (line 14) 27795* MIPS little-endian output: MIPS Options. (line 13) 27796* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides. 27797 (line 42) 27798* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides. 27799 (line 16) 27800* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides. 27801 (line 6) 27802* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides. 27803 (line 37) 27804* MIPS option stack: MIPS Option Stack. (line 6) 27805* MIPS processor: MIPS-Dependent. (line 6) 27806* MIPS SIMD Architecture instruction generation override: MIPS ASE Instruction Generation Overrides. 27807 (line 47) 27808* MIPS16e2 instruction generation override: MIPS ASE Instruction Generation Overrides. 27809 (line 61) 27810* mistack command-line option, C-SKY: C-SKY Options. (line 82) 27811* MIT: M68K-Syntax. (line 6) 27812* mjsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 27813* mlabr command-line option, C-SKY: C-SKY Options. (line 75) 27814* mlaf command-line option, C-SKY: C-SKY Options. (line 69) 27815* mlib directive, TIC54X: TIC54X-Directives. (line 157) 27816* mlink-relax command-line option, PRU: PRU Options. (line 6) 27817* mlist directive, TIC54X: TIC54X-Directives. (line 162) 27818* mliterals-after-br command-line option, C-SKY: C-SKY Options. 27819 (line 75) 27820* mliterals-after-func command-line option, C-SKY: C-SKY Options. 27821 (line 69) 27822* mlittle-endian command-line option, C-SKY: C-SKY Options. (line 14) 27823* mljump command-line option, C-SKY: C-SKY Options. (line 26) 27824* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 137) 27825* MMIX assembler directive BYTE: MMIX-Pseudos. (line 101) 27826* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 137) 27827* MMIX assembler directive GREG: MMIX-Pseudos. (line 53) 27828* MMIX assembler directive IS: MMIX-Pseudos. (line 44) 27829* MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 27830* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 29) 27831* MMIX assembler directive OCTA: MMIX-Pseudos. (line 113) 27832* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 125) 27833* MMIX assembler directive TETRA: MMIX-Pseudos. (line 113) 27834* MMIX assembler directive WYDE: MMIX-Pseudos. (line 113) 27835* MMIX assembler directives: MMIX-Pseudos. (line 6) 27836* MMIX line comment characters: MMIX-Chars. (line 6) 27837* MMIX options: MMIX-Opts. (line 6) 27838* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 137) 27839* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 101) 27840* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 137) 27841* MMIX pseudo-op GREG: MMIX-Pseudos. (line 53) 27842* MMIX pseudo-op IS: MMIX-Pseudos. (line 44) 27843* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 27844* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 29) 27845* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 113) 27846* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 125) 27847* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 113) 27848* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 113) 27849* MMIX pseudo-ops: MMIX-Pseudos. (line 6) 27850* MMIX register names: MMIX-Regs. (line 6) 27851* MMIX support: MMIX-Dependent. (line 6) 27852* mmixal differences: MMIX-mmixal. (line 6) 27853* mmp command-line option, C-SKY: C-SKY Options. (line 94) 27854* mmregs directive, TIC54X: TIC54X-Directives. (line 167) 27855* mmsg directive, TIC54X: TIC54X-Directives. (line 75) 27856* MMX, i386: i386-SIMD. (line 6) 27857* MMX, x86-64: i386-SIMD. (line 6) 27858* mnemonic compatibility, i386: i386-Mnemonics. (line 81) 27859* mnemonic suffixes, i386: i386-Variations. (line 28) 27860* mnemonic suffixes, x86-64: i386-Variations. (line 28) 27861* mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 27862* mnemonics, AVR: AVR Opcodes. (line 6) 27863* mnemonics, D10V: D10V-Opcodes. (line 6) 27864* mnemonics, D30V: D30V-Opcodes. (line 6) 27865* mnemonics, H8/300: H8/300 Opcodes. (line 6) 27866* mnemonics, LM32: LM32 Opcodes. (line 6) 27867* mnemonics, OpenRISC: OpenRISC-Opcodes. (line 6) 27868* mnemonics, SH: SH Opcodes. (line 6) 27869* mnemonics, Z8000: Z8000 Opcodes. (line 6) 27870* mno-branch-stub command-line option, C-SKY: C-SKY Options. (line 34) 27871* mno-elrw command-line option, C-SKY: C-SKY Options. (line 64) 27872* mno-force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 27873* mno-istack command-line option, C-SKY: C-SKY Options. (line 82) 27874* mno-jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 27875* mno-labr command-line option, C-SKY: C-SKY Options. (line 75) 27876* mno-laf command-line option, C-SKY: C-SKY Options. (line 69) 27877* mno-link-relax command-line option, PRU: PRU Options. (line 12) 27878* mno-literals-after-func command-line option, C-SKY: C-SKY Options. 27879 (line 69) 27880* mno-ljump command-line option, C-SKY: C-SKY Options. (line 26) 27881* mno-lrw command-line option, C-SKY: C-SKY Options. (line 59) 27882* mno-warn-regname-label command-line option, PRU: PRU Options. 27883 (line 16) 27884* mnolist directive, TIC54X: TIC54X-Directives. (line 162) 27885* mnoliterals-after-br command-line option, C-SKY: C-SKY Options. 27886 (line 75) 27887* mnolrw command-line option, C-SKY: C-SKY Options. (line 59) 27888* mnps400 command-line option, ARC: ARC Options. (line 79) 27889* modifiers, M32C: M32C-Modifiers. (line 6) 27890* module layout, WebAssembly: WebAssembly-module-layout. 27891 (line 6) 27892* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 27893* MOVI instructions, relaxation: Xtensa Immediate Relaxation. 27894 (line 12) 27895* MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations. 27896 (line 6) 27897* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21) 27898* MRI compatibility mode: M. (line 6) 27899* mri directive: MRI. (line 6) 27900* MRI mode, temporarily: MRI. (line 6) 27901* msecurity command-line option, C-SKY: C-SKY Options. (line 103) 27902* MSP 430 floating point (IEEE): MSP430 Floating Point. 27903 (line 6) 27904* MSP 430 identifiers: MSP430-Chars. (line 17) 27905* MSP 430 line comment character: MSP430-Chars. (line 6) 27906* MSP 430 line separator: MSP430-Chars. (line 14) 27907* MSP 430 machine directives: MSP430 Directives. (line 6) 27908* MSP 430 macros: MSP430-Macros. (line 6) 27909* MSP 430 opcodes: MSP430 Opcodes. (line 6) 27910* MSP 430 options (none): MSP430 Options. (line 6) 27911* MSP 430 profiling capability: MSP430 Profiling Capability. 27912 (line 6) 27913* MSP 430 register names: MSP430-Regs. (line 6) 27914* MSP 430 support: MSP430-Dependent. (line 6) 27915* MSP430 Assembler Extensions: MSP430-Ext. (line 6) 27916* mspabi_attribute directive, MSP430: MSP430 Directives. (line 38) 27917* mtrust command-line option, C-SKY: C-SKY Options. (line 106) 27918* mul instruction, i386: i386-Notes. (line 6) 27919* mul instruction, x86-64: i386-Notes. (line 6) 27920* mvdsp command-line option, C-SKY: C-SKY Options. (line 115) 27921* N32K support: NS32K-Dependent. (line 6) 27922* name: Z8000 Directives. (line 18) 27923* named section: Section. (line 6) 27924* named sections: Ld Sections. (line 8) 27925* names, symbol: Symbol Names. (line 6) 27926* naming object file: o. (line 6) 27927* NDS32 options: NDS32 Options. (line 6) 27928* NDS32 processor: NDS32-Dependent. (line 6) 27929* new page, in listings: Eject. (line 6) 27930* newblock directive, TIC54X: TIC54X-Directives. (line 173) 27931* newline (\n): Strings. (line 21) 27932* newline, required at file end: Statements. (line 14) 27933* Nios II line comment character: Nios II Chars. (line 6) 27934* Nios II line separator character: Nios II Chars. (line 6) 27935* Nios II machine directives: Nios II Directives. (line 6) 27936* Nios II machine relocations: Nios II Relocations. 27937 (line 6) 27938* Nios II opcodes: Nios II Opcodes. (line 6) 27939* Nios II options: Nios II Options. (line 6) 27940* Nios II support: NiosII-Dependent. (line 6) 27941* Nios support: NiosII-Dependent. (line 6) 27942* no-absolute-literals directive: Absolute Literals Directive. 27943 (line 6) 27944* no-force2bsr command-line option, C-SKY: C-SKY Options. (line 43) 27945* no-jsri2bsr command-line option, C-SKY: C-SKY Options. (line 52) 27946* no-longcalls directive: Longcalls Directive. 27947 (line 6) 27948* no-relax command-line option, Nios II: Nios II Options. (line 19) 27949* no-schedule directive: Schedule Directive. (line 6) 27950* no-transform directive: Transform Directive. 27951 (line 6) 27952* nodelay directive, OpenRISC: OpenRISC-Directives. 27953 (line 15) 27954* nolist directive: Nolist. (line 6) 27955* nolist directive, TIC54X: TIC54X-Directives. (line 129) 27956* NOP pseudo op, ARM: ARM Opcodes. (line 9) 27957* nops directive: Nops. (line 6) 27958* notes for Alpha: Alpha Notes. (line 6) 27959* notes for WebAssembly: WebAssembly-Notes. (line 6) 27960* NS32K line comment character: NS32K-Chars. (line 6) 27961* NS32K line separator: NS32K-Chars. (line 18) 27962* null-terminated strings: Asciz. (line 6) 27963* number constants: Numbers. (line 6) 27964* number of macros executed: Macro. (line 142) 27965* numbered subsections: Sub-Sections. (line 6) 27966* numbers, 16-bit: hword. (line 6) 27967* numeric values: Expressions. (line 6) 27968* nword directive, SPARC: Sparc-Directives. (line 20) 27969* Object Attribute, RISC-V: RISC-V-ATTRIBUTE. (line 6) 27970* object attributes: Object Attributes. (line 6) 27971* object file: Object. (line 6) 27972* object file format: Object Formats. (line 6) 27973* object file name: o. (line 6) 27974* object file, after errors: Z. (line 6) 27975* obsolescent directives: Deprecated. (line 6) 27976* octa directive: Octa. (line 6) 27977* octal character code (\DDD): Strings. (line 30) 27978* octal integers: Integers. (line 9) 27979* offset directive: Offset. (line 6) 27980* offset directive, V850: V850 Directives. (line 6) 27981* opcode mnemonics, VAX: VAX-opcodes. (line 6) 27982* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6) 27983* opcode names, TILEPro: TILEPro Opcodes. (line 6) 27984* opcode names, Xtensa: Xtensa Opcodes. (line 6) 27985* opcode summary, AVR: AVR Opcodes. (line 6) 27986* opcode summary, D10V: D10V-Opcodes. (line 6) 27987* opcode summary, D30V: D30V-Opcodes. (line 6) 27988* opcode summary, H8/300: H8/300 Opcodes. (line 6) 27989* opcode summary, LM32: LM32 Opcodes. (line 6) 27990* opcode summary, OpenRISC: OpenRISC-Opcodes. (line 6) 27991* opcode summary, SH: SH Opcodes. (line 6) 27992* opcode summary, Z8000: Z8000 Opcodes. (line 6) 27993* opcodes for AArch64: AArch64 Opcodes. (line 6) 27994* opcodes for ARC: ARC Opcodes. (line 6) 27995* opcodes for ARM: ARM Opcodes. (line 6) 27996* opcodes for BPF: BPF Opcodes. (line 6) 27997* opcodes for MSP 430: MSP430 Opcodes. (line 6) 27998* opcodes for Nios II: Nios II Opcodes. (line 6) 27999* opcodes for PRU: PRU Opcodes. (line 6) 28000* opcodes for V850: V850 Opcodes. (line 6) 28001* opcodes, M680x0: M68K-opcodes. (line 6) 28002* opcodes, M68HC11: M68HC11-opcodes. (line 6) 28003* opcodes, WebAssembly: WebAssembly-Opcodes. 28004 (line 6) 28005* OPENRISC floating point (IEEE): OpenRISC-Float. (line 6) 28006* OpenRISC line comment character: OpenRISC-Chars. (line 6) 28007* OpenRISC line separator: OpenRISC-Chars. (line 9) 28008* OPENRISC machine directives: OpenRISC-Directives. 28009 (line 6) 28010* OpenRISC opcode summary: OpenRISC-Opcodes. (line 6) 28011* OpenRISC registers: OpenRISC-Regs. (line 6) 28012* OpenRISC relocations: OpenRISC-Relocs. (line 6) 28013* OPENRISC support: OpenRISC-Dependent. (line 6) 28014* OPENRISC syntax: OpenRISC-Dependent. (line 13) 28015* operand delimiters, i386: i386-Variations. (line 15) 28016* operand delimiters, x86-64: i386-Variations. (line 15) 28017* operand notation, VAX: VAX-operands. (line 6) 28018* operands in expressions: Arguments. (line 6) 28019* operator precedence: Infix Ops. (line 11) 28020* operators, in expressions: Operators. (line 6) 28021* operators, permitted arguments: Infix Ops. (line 6) 28022* optimization, D10V: Overview. (line 638) 28023* optimization, D30V: Overview. (line 643) 28024* optimizations: Xtensa Optimizations. 28025 (line 6) 28026* Option directive: RISC-V-Directives. (line 34) 28027* option directive: RISC-V-Directives. (line 34) 28028* option directive, TIC54X: TIC54X-Directives. (line 177) 28029* option summary: Overview. (line 6) 28030* options for AArch64 (none): AArch64 Options. (line 6) 28031* options for Alpha: Alpha Options. (line 6) 28032* options for ARC: ARC Options. (line 6) 28033* options for ARM (none): ARM Options. (line 6) 28034* options for AVR (none): AVR Options. (line 6) 28035* options for Blackfin (none): Blackfin Options. (line 6) 28036* options for BPF (none): BPF Options. (line 6) 28037* options for C-SKY: C-SKY Options. (line 6) 28038* options for i386: i386-Options. (line 6) 28039* options for IA-64: IA-64 Options. (line 6) 28040* options for LM32 (none): LM32 Options. (line 6) 28041* options for Meta: Meta Options. (line 6) 28042* options for MSP430 (none): MSP430 Options. (line 6) 28043* options for NDS32: NDS32 Options. (line 6) 28044* options for Nios II: Nios II Options. (line 6) 28045* options for PDP-11: PDP-11-Options. (line 6) 28046* options for PowerPC: PowerPC-Opts. (line 6) 28047* options for PRU: PRU Options. (line 6) 28048* options for s390: s390 Options. (line 6) 28049* options for SCORE: SCORE-Opts. (line 6) 28050* options for SPARC: Sparc-Opts. (line 6) 28051* options for TIC6X: TIC6X Options. (line 6) 28052* options for V850 (none): V850 Options. (line 6) 28053* options for VAX/VMS: VAX-Opts. (line 42) 28054* options for Visium: Visium Options. (line 6) 28055* options for x86-64: i386-Options. (line 6) 28056* options for Z80: Z80 Options. (line 6) 28057* options, all versions of assembler: Invoking. (line 6) 28058* options, command line: Command Line. (line 13) 28059* options, CRIS: CRIS-Opts. (line 6) 28060* options, D10V: D10V-Opts. (line 6) 28061* options, D30V: D30V-Opts. (line 6) 28062* options, Epiphany: Epiphany Options. (line 6) 28063* options, H8/300: H8/300 Options. (line 6) 28064* options, IP2K: IP2K-Opts. (line 6) 28065* options, M32C: M32C-Opts. (line 6) 28066* options, M32R: M32R-Opts. (line 6) 28067* options, M680x0: M68K-Opts. (line 6) 28068* options, M68HC11: M68HC11-Opts. (line 6) 28069* options, MMIX: MMIX-Opts. (line 6) 28070* options, PJ: PJ Options. (line 6) 28071* options, RL78: RL78-Opts. (line 6) 28072* options, RX: RX-Opts. (line 6) 28073* options, S12Z: S12Z Options. (line 6) 28074* options, SH: SH Options. (line 6) 28075* options, TIC54X: TIC54X-Opts. (line 6) 28076* options, XGATE: XGATE-Opts. (line 6) 28077* options, Z8000: Z8000 Options. (line 6) 28078* org directive: Org. (line 6) 28079* other attribute, of a.out symbol: Symbol Other. (line 6) 28080* output file: Object. (line 6) 28081* output section padding: no-pad-sections. (line 6) 28082* p2align directive: P2align. (line 6) 28083* p2alignl directive: P2align. (line 30) 28084* p2alignw directive: P2align. (line 30) 28085* padding the location counter: Align. (line 6) 28086* padding the location counter given a power of two: P2align. 28087 (line 6) 28088* padding the location counter given number of bytes: Balign. 28089 (line 6) 28090* page, in listings: Eject. (line 6) 28091* paper size, for listings: Psize. (line 6) 28092* paths for .include: I. (line 6) 28093* patterns, writing in memory: Fill. (line 6) 28094* PDP-11 comments: PDP-11-Syntax. (line 16) 28095* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 28096* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 28097* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 28098* PDP-11 line separator: PDP-11-Syntax. (line 19) 28099* PDP-11 support: PDP-11-Dependent. (line 6) 28100* PDP-11 syntax: PDP-11-Syntax. (line 6) 28101* PIC code generation for ARM: ARM Options. (line 366) 28102* PIC code generation for M32R: M32R-Opts. (line 42) 28103* pic command-line option, C-SKY: C-SKY Options. (line 22) 28104* PIC selection, MIPS: MIPS Options. (line 21) 28105* PJ endianness: Overview. (line 759) 28106* PJ line comment character: PJ-Chars. (line 6) 28107* PJ line separator: PJ-Chars. (line 14) 28108* PJ options: PJ Options. (line 6) 28109* PJ support: PJ-Dependent. (line 6) 28110* plus, permitted arguments: Infix Ops. (line 45) 28111* pmem directive, PRU: PRU Relocations. (line 6) 28112* popsection directive: PopSection. (line 6) 28113* Position-independent code, CRIS: CRIS-Opts. (line 27) 28114* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 28115* PowerPC architectures: PowerPC-Opts. (line 6) 28116* PowerPC directives: PowerPC-Pseudo. (line 6) 28117* PowerPC line comment character: PowerPC-Chars. (line 6) 28118* PowerPC line separator: PowerPC-Chars. (line 18) 28119* PowerPC options: PowerPC-Opts. (line 6) 28120* PowerPC support: PPC-Dependent. (line 6) 28121* precedence of operators: Infix Ops. (line 11) 28122* precision, floating point: Flonums. (line 6) 28123* prefix operators: Prefix Ops. (line 6) 28124* prefixes, i386: i386-Prefixes. (line 6) 28125* preprocessing: Preprocessing. (line 6) 28126* preprocessing, turning on and off: Preprocessing. (line 26) 28127* previous directive: Previous. (line 6) 28128* primary attributes, COFF symbols: COFF Symbols. (line 13) 28129* print directive: Print. (line 6) 28130* proc directive, OpenRISC: OpenRISC-Directives. 28131 (line 20) 28132* proc directive, SPARC: Sparc-Directives. (line 25) 28133* Processor Identification register, ARC: ARC-Regs. (line 51) 28134* profiler directive, MSP 430: MSP430 Directives. (line 26) 28135* profiling capability for MSP 430: MSP430 Profiling Capability. 28136 (line 6) 28137* Program Counter, ARC: ARC-Regs. (line 54) 28138* protected directive: Protected. (line 6) 28139* PRU line comment character: PRU Chars. (line 6) 28140* PRU machine directives: PRU Directives. (line 6) 28141* PRU machine relocations: PRU Relocations. (line 6) 28142* PRU opcodes: PRU Opcodes. (line 6) 28143* PRU options: PRU Options. (line 6) 28144* PRU support: PRU-Dependent. (line 6) 28145* pseudo map fd, BPF: BPF-Pseudo-Maps. (line 6) 28146* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 50) 28147* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 28148* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 18) 28149* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 137) 28150* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 101) 28151* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 137) 28152* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 53) 28153* pseudo-op IS, MMIX: MMIX-Pseudos. (line 44) 28154* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 28155* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 29) 28156* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 113) 28157* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 125) 28158* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 113) 28159* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 113) 28160* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6) 28161* pseudo-opcodes, M680x0: M68K-Branch. (line 6) 28162* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 28163* pseudo-ops for branch, VAX: VAX-branch. (line 6) 28164* pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 28165* pseudo-ops, machine independent: Pseudo Ops. (line 6) 28166* pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 28167* psize directive: Psize. (line 6) 28168* PSR bits: IA-64-Bits. (line 6) 28169* pstring directive, TIC54X: TIC54X-Directives. (line 206) 28170* psw register, V850: V850-Regs. (line 80) 28171* purgem directive: Purgem. (line 6) 28172* purpose of GNU assembler: GNU Assembler. (line 12) 28173* pushsection directive: PushSection. (line 6) 28174* quad directive: Quad. (line 6) 28175* quad directive, i386: i386-Float. (line 21) 28176* quad directive, x86-64: i386-Float. (line 21) 28177* real-mode code, i386: i386-16bit. (line 6) 28178* ref directive, TIC54X: TIC54X-Directives. (line 101) 28179* refsym directive, MSP 430: MSP430 Directives. (line 30) 28180* register directive, SPARC: Sparc-Directives. (line 29) 28181* register name prefix character, ARC: ARC-Chars. (line 7) 28182* register names, AArch64: AArch64-Regs. (line 6) 28183* register names, Alpha: Alpha-Regs. (line 6) 28184* register names, ARC: ARC-Regs. (line 6) 28185* register names, ARM: ARM-Regs. (line 6) 28186* register names, AVR: AVR-Regs. (line 6) 28187* register names, BPF: BPF-Regs. (line 6) 28188* register names, CRIS: CRIS-Regs. (line 6) 28189* register names, H8/300: H8/300-Regs. (line 6) 28190* register names, IA-64: IA-64-Regs. (line 6) 28191* register names, LM32: LM32-Regs. (line 6) 28192* register names, MMIX: MMIX-Regs. (line 6) 28193* register names, MSP 430: MSP430-Regs. (line 6) 28194* register names, OpenRISC: OpenRISC-Regs. (line 6) 28195* register names, S12Z: S12Z Addressing Modes. 28196 (line 28) 28197* register names, Sparc: Sparc-Regs. (line 6) 28198* register names, TILE-Gx: TILE-Gx Registers. (line 6) 28199* register names, TILEPro: TILEPro Registers. (line 6) 28200* register names, V850: V850-Regs. (line 6) 28201* register names, VAX: VAX-operands. (line 17) 28202* register names, Visium: Visium Registers. (line 6) 28203* register names, Xtensa: Xtensa Registers. (line 6) 28204* register names, Z80: Z80-Regs. (line 6) 28205* register naming, s390: s390 Register. (line 6) 28206* register notation, S12Z: S12Z Register Notation. 28207 (line 6) 28208* register operands, i386: i386-Variations. (line 15) 28209* register operands, x86-64: i386-Variations. (line 15) 28210* registers, D10V: D10V-Regs. (line 6) 28211* registers, D30V: D30V-Regs. (line 6) 28212* registers, i386: i386-Regs. (line 6) 28213* registers, Meta: Meta-Regs. (line 6) 28214* registers, SH: SH-Regs. (line 6) 28215* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 28216* registers, x86-64: i386-Regs. (line 6) 28217* registers, Z8000: Z8000-Regs. (line 6) 28218* relax-all command-line option, Nios II: Nios II Options. (line 13) 28219* relax-section command-line option, Nios II: Nios II Options. 28220 (line 6) 28221* relaxation: Xtensa Relaxation. (line 6) 28222* relaxation of ADDI instructions: Xtensa Immediate Relaxation. 28223 (line 43) 28224* relaxation of branch instructions: Xtensa Branch Relaxation. 28225 (line 6) 28226* relaxation of call instructions: Xtensa Call Relaxation. 28227 (line 6) 28228* relaxation of immediate fields: Xtensa Immediate Relaxation. 28229 (line 6) 28230* relaxation of jump instructions: Xtensa Jump Relaxation. 28231 (line 6) 28232* relaxation of L16SI instructions: Xtensa Immediate Relaxation. 28233 (line 23) 28234* relaxation of L16UI instructions: Xtensa Immediate Relaxation. 28235 (line 23) 28236* relaxation of L32I instructions: Xtensa Immediate Relaxation. 28237 (line 23) 28238* relaxation of L8UI instructions: Xtensa Immediate Relaxation. 28239 (line 23) 28240* relaxation of MOVI instructions: Xtensa Immediate Relaxation. 28241 (line 12) 28242* reloc directive: Reloc. (line 6) 28243* relocation: Sections. (line 6) 28244* relocation example: Ld Sections. (line 40) 28245* relocations, AArch64: AArch64-Relocations. 28246 (line 6) 28247* relocations, Alpha: Alpha-Relocs. (line 6) 28248* relocations, OpenRISC: OpenRISC-Relocs. (line 6) 28249* relocations, Sparc: Sparc-Relocs. (line 6) 28250* relocations, WebAssembly: WebAssembly-Relocs. (line 6) 28251* repeat prefixes, i386: i386-Prefixes. (line 44) 28252* reporting bugs in assembler: Reporting Bugs. (line 6) 28253* rept directive: Rept. (line 6) 28254* reserve directive, SPARC: Sparc-Directives. (line 39) 28255* return instructions, i386: i386-Variations. (line 45) 28256* return instructions, x86-64: i386-Variations. (line 45) 28257* REX prefixes, i386: i386-Prefixes. (line 46) 28258* RISC-V instruction formats: RISC-V-Formats. (line 6) 28259* RISC-V machine directives: RISC-V-Directives. (line 6) 28260* RISC-V support: RISC-V-Dependent. (line 6) 28261* RL78 assembler directives: RL78-Directives. (line 6) 28262* RL78 line comment character: RL78-Chars. (line 6) 28263* RL78 line separator: RL78-Chars. (line 14) 28264* RL78 modifiers: RL78-Modifiers. (line 6) 28265* RL78 options: RL78-Opts. (line 6) 28266* RL78 support: RL78-Dependent. (line 6) 28267* rsect: Z8000 Directives. (line 52) 28268* RX assembler directive .3byte: RX-Directives. (line 9) 28269* RX assembler directive .fetchalign: RX-Directives. (line 13) 28270* RX assembler directives: RX-Directives. (line 6) 28271* RX floating point: RX-Float. (line 6) 28272* RX line comment character: RX-Chars. (line 6) 28273* RX line separator: RX-Chars. (line 14) 28274* RX modifiers: RX-Modifiers. (line 6) 28275* RX options: RX-Opts. (line 6) 28276* RX support: RX-Dependent. (line 6) 28277* S12Z addressing modes: S12Z Addressing Modes. 28278 (line 6) 28279* S12Z line separator: S12Z Syntax Overview. 28280 (line 41) 28281* S12Z options: S12Z Options. (line 6) 28282* S12Z support: S12Z-Dependent. (line 8) 28283* S12Z syntax: S12Z Syntax. (line 12) 28284* s390 floating point: s390 Floating Point. 28285 (line 6) 28286* s390 instruction aliases: s390 Aliases. (line 6) 28287* s390 instruction formats: s390 Formats. (line 6) 28288* s390 instruction marker: s390 Instruction Marker. 28289 (line 6) 28290* s390 instruction mnemonics: s390 Mnemonics. (line 6) 28291* s390 instruction operand modifier: s390 Operand Modifier. 28292 (line 6) 28293* s390 instruction operands: s390 Operands. (line 6) 28294* s390 instruction syntax: s390 Syntax. (line 6) 28295* s390 line comment character: s390 Characters. (line 6) 28296* s390 line separator: s390 Characters. (line 13) 28297* s390 literal pool entries: s390 Literal Pool Entries. 28298 (line 6) 28299* s390 options: s390 Options. (line 6) 28300* s390 register naming: s390 Register. (line 6) 28301* s390 support: S/390-Dependent. (line 6) 28302* Saved User Stack Pointer, ARC: ARC-Regs. (line 73) 28303* sblock directive, TIC54X: TIC54X-Directives. (line 180) 28304* sbttl directive: Sbttl. (line 6) 28305* schedule directive: Schedule Directive. (line 6) 28306* scl directive: Scl. (line 6) 28307* SCORE architectures: SCORE-Opts. (line 6) 28308* SCORE directives: SCORE-Pseudo. (line 6) 28309* SCORE line comment character: SCORE-Chars. (line 6) 28310* SCORE line separator: SCORE-Chars. (line 14) 28311* SCORE options: SCORE-Opts. (line 6) 28312* SCORE processor: SCORE-Dependent. (line 6) 28313* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 28314* search path for .include: I. (line 6) 28315* sect directive, TIC54X: TIC54X-Directives. (line 186) 28316* section directive (COFF version): Section. (line 16) 28317* section directive (ELF version): Section. (line 67) 28318* section directive, V850: V850 Directives. (line 9) 28319* section name substitution: Section. (line 71) 28320* section override prefixes, i386: i386-Prefixes. (line 23) 28321* Section Stack: PopSection. (line 6) 28322* Section Stack <1>: Previous. (line 6) 28323* Section Stack <2>: PushSection. (line 6) 28324* Section Stack <3>: Section. (line 62) 28325* Section Stack <4>: SubSection. (line 6) 28326* section-relative addressing: Secs Background. (line 65) 28327* sections: Sections. (line 6) 28328* sections in messages, internal: As Sections. (line 6) 28329* sections, i386: i386-Variations. (line 51) 28330* sections, named: Ld Sections. (line 8) 28331* sections, x86-64: i386-Variations. (line 51) 28332* seg directive, SPARC: Sparc-Directives. (line 44) 28333* segm: Z8000 Directives. (line 10) 28334* set at directive, Nios II: Nios II Directives. (line 35) 28335* set break directive, Nios II: Nios II Directives. (line 43) 28336* set directive: Set. (line 6) 28337* set directive, Nios II: Nios II Directives. (line 57) 28338* set directive, TIC54X: TIC54X-Directives. (line 189) 28339* set noat directive, Nios II: Nios II Directives. (line 31) 28340* set nobreak directive, Nios II: Nios II Directives. (line 39) 28341* set norelax directive, Nios II: Nios II Directives. (line 46) 28342* set no_warn_regname_label directive, PRU: PRU Directives. (line 28) 28343* set relaxall directive, Nios II: Nios II Directives. (line 53) 28344* set relaxsection directive, Nios II: Nios II Directives. (line 49) 28345* SH addressing modes: SH-Addressing. (line 6) 28346* SH floating point (IEEE): SH Floating Point. (line 6) 28347* SH line comment character: SH-Chars. (line 6) 28348* SH line separator: SH-Chars. (line 8) 28349* SH machine directives: SH Directives. (line 6) 28350* SH opcode summary: SH Opcodes. (line 6) 28351* SH options: SH Options. (line 6) 28352* SH registers: SH-Regs. (line 6) 28353* SH support: SH-Dependent. (line 6) 28354* shigh directive, M32R: M32R-Directives. (line 26) 28355* short directive: Short. (line 6) 28356* short directive, TIC54X: TIC54X-Directives. (line 109) 28357* signatures, WebAssembly: WebAssembly-Signatures. 28358 (line 6) 28359* SIMD, i386: i386-SIMD. (line 6) 28360* SIMD, x86-64: i386-SIMD. (line 6) 28361* single character constant: Chars. (line 6) 28362* single directive: Single. (line 6) 28363* single directive, i386: i386-Float. (line 14) 28364* single directive, x86-64: i386-Float. (line 14) 28365* single quote, Z80: Z80-Chars. (line 20) 28366* sixteen bit integers: hword. (line 6) 28367* sixteen byte integer: Octa. (line 6) 28368* size directive (COFF version): Size. (line 11) 28369* size directive (ELF version): Size. (line 19) 28370* size modifiers, D10V: D10V-Size. (line 6) 28371* size modifiers, D30V: D30V-Size. (line 6) 28372* size modifiers, M680x0: M68K-Syntax. (line 8) 28373* size prefixes, i386: i386-Prefixes. (line 27) 28374* size suffixes, H8/300: H8/300 Opcodes. (line 160) 28375* size, translations, Sparc: Sparc-Size-Translations. 28376 (line 6) 28377* sizes operands, i386: i386-Variations. (line 28) 28378* sizes operands, x86-64: i386-Variations. (line 28) 28379* skip directive: Skip. (line 6) 28380* skip directive, M680x0: M68K-Directives. (line 19) 28381* skip directive, SPARC: Sparc-Directives. (line 48) 28382* sleb128 directive: Sleb128. (line 6) 28383* small data, MIPS: MIPS Small Data. (line 6) 28384* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides. 28385 (line 11) 28386* SOM symbol attributes: SOM Symbols. (line 6) 28387* source program: Input Files. (line 6) 28388* source, destination operands; i386: i386-Variations. (line 21) 28389* source, destination operands; x86-64: i386-Variations. (line 21) 28390* sp register: Xtensa Registers. (line 6) 28391* sp register, V850: V850-Regs. (line 12) 28392* space directive: Space. (line 6) 28393* space directive, TIC54X: TIC54X-Directives. (line 194) 28394* space used, maximum for assembly: statistics. (line 6) 28395* SPARC architectures: Sparc-Opts. (line 6) 28396* Sparc constants: Sparc-Constants. (line 6) 28397* SPARC data alignment: Sparc-Aligned-Data. (line 6) 28398* SPARC floating point (IEEE): Sparc-Float. (line 6) 28399* Sparc line comment character: Sparc-Chars. (line 6) 28400* Sparc line separator: Sparc-Chars. (line 14) 28401* SPARC machine directives: Sparc-Directives. (line 6) 28402* SPARC options: Sparc-Opts. (line 6) 28403* Sparc registers: Sparc-Regs. (line 6) 28404* Sparc relocations: Sparc-Relocs. (line 6) 28405* Sparc size translations: Sparc-Size-Translations. 28406 (line 6) 28407* SPARC support: Sparc-Dependent. (line 6) 28408* SPARC syntax: Sparc-Aligned-Data. (line 21) 28409* special characters, M680x0: M68K-Chars. (line 6) 28410* special purpose registers, MSP 430: MSP430-Regs. (line 11) 28411* sslist directive, TIC54X: TIC54X-Directives. (line 201) 28412* ssnolist directive, TIC54X: TIC54X-Directives. (line 201) 28413* stabd directive: Stab. (line 38) 28414* stabn directive: Stab. (line 49) 28415* stabs directive: Stab. (line 52) 28416* stabX directives: Stab. (line 6) 28417* stack pointer, ARC: ARC-Regs. (line 20) 28418* standard assembler sections: Secs Background. (line 27) 28419* standard input, as input file: Command Line. (line 10) 28420* statement separator character: Statements. (line 6) 28421* statement separator, AArch64: AArch64-Chars. (line 10) 28422* statement separator, Alpha: Alpha-Chars. (line 11) 28423* statement separator, ARC: ARC-Chars. (line 27) 28424* statement separator, ARM: ARM-Chars. (line 14) 28425* statement separator, AVR: AVR-Chars. (line 14) 28426* statement separator, BPF: BPF-Chars. (line 10) 28427* statement separator, CR16: CR16-Chars. (line 12) 28428* statement separator, Epiphany: Epiphany-Chars. (line 14) 28429* statement separator, H8/300: H8/300-Chars. (line 8) 28430* statement separator, i386: i386-Chars. (line 18) 28431* statement separator, IA-64: IA-64-Chars. (line 8) 28432* statement separator, IP2K: IP2K-Chars. (line 14) 28433* statement separator, LM32: LM32-Chars. (line 12) 28434* statement separator, M32C: M32C-Chars. (line 14) 28435* statement separator, M68HC11: M68HC11-Syntax. (line 26) 28436* statement separator, Meta: Meta-Chars. (line 8) 28437* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14) 28438* statement separator, MIPS: MIPS-Chars. (line 14) 28439* statement separator, MSP 430: MSP430-Chars. (line 14) 28440* statement separator, NS32K: NS32K-Chars. (line 18) 28441* statement separator, OpenRISC: OpenRISC-Chars. (line 9) 28442* statement separator, PJ: PJ-Chars. (line 14) 28443* statement separator, PowerPC: PowerPC-Chars. (line 18) 28444* statement separator, RL78: RL78-Chars. (line 14) 28445* statement separator, RX: RX-Chars. (line 14) 28446* statement separator, S12Z: S12Z Syntax Overview. 28447 (line 41) 28448* statement separator, s390: s390 Characters. (line 13) 28449* statement separator, SCORE: SCORE-Chars. (line 14) 28450* statement separator, SH: SH-Chars. (line 8) 28451* statement separator, Sparc: Sparc-Chars. (line 14) 28452* statement separator, TIC54X: TIC54X-Chars. (line 17) 28453* statement separator, TIC6X: TIC6X Syntax. (line 13) 28454* statement separator, V850: V850-Chars. (line 13) 28455* statement separator, VAX: VAX-Chars. (line 14) 28456* statement separator, Visium: Visium Characters. (line 14) 28457* statement separator, XGATE: XGATE-Syntax. (line 25) 28458* statement separator, XStormy16: XStormy16-Chars. (line 14) 28459* statement separator, Z80: Z80-Chars. (line 13) 28460* statement separator, Z8000: Z8000-Chars. (line 13) 28461* statements, structure of: Statements. (line 6) 28462* statistics, about assembly: statistics. (line 6) 28463* Status register, ARC: ARC-Regs. (line 57) 28464* STATUS32 saved on exception, ARC: ARC-Regs. (line 82) 28465* stopping the assembly: Abort. (line 6) 28466* Stored STATUS32 register on entry to level P0 interrupts, ARC: ARC-Regs. 28467 (line 69) 28468* string constants: Strings. (line 6) 28469* string directive: String. (line 8) 28470* string directive on HPPA: HPPA Directives. (line 137) 28471* string directive, TIC54X: TIC54X-Directives. (line 206) 28472* string literals: Ascii. (line 6) 28473* string, copying to object file: String. (line 8) 28474* string16 directive: String. (line 8) 28475* string16, copying to object file: String. (line 8) 28476* string32 directive: String. (line 8) 28477* string32, copying to object file: String. (line 8) 28478* string64 directive: String. (line 8) 28479* string64, copying to object file: String. (line 8) 28480* string8 directive: String. (line 8) 28481* string8, copying to object file: String. (line 8) 28482* struct directive: Struct. (line 6) 28483* struct directive, TIC54X: TIC54X-Directives. (line 214) 28484* structure debugging, COFF: Tag. (line 6) 28485* sub-instruction ordering, D10V: D10V-Chars. (line 14) 28486* sub-instruction ordering, D30V: D30V-Chars. (line 14) 28487* sub-instructions, D10V: D10V-Subs. (line 6) 28488* sub-instructions, D30V: D30V-Subs. (line 6) 28489* subexpressions: Arguments. (line 24) 28490* subsection directive: SubSection. (line 6) 28491* subsym builtins, TIC54X: TIC54X-Macros. (line 16) 28492* subtitles for listings: Sbttl. (line 6) 28493* subtraction, permitted arguments: Infix Ops. (line 50) 28494* summary of options: Overview. (line 6) 28495* support: HPPA-Dependent. (line 6) 28496* supporting files, including: Include. (line 6) 28497* suppressing warnings: W. (line 11) 28498* sval: Z8000 Directives. (line 33) 28499* symbol attributes: Symbol Attributes. (line 6) 28500* symbol attributes, a.out: a.out Symbols. (line 6) 28501* symbol attributes, COFF: COFF Symbols. (line 6) 28502* symbol attributes, SOM: SOM Symbols. (line 6) 28503* symbol descriptor, COFF: Desc. (line 6) 28504* symbol modifiers: AVR-Modifiers. (line 12) 28505* symbol modifiers <1>: LM32-Modifiers. (line 12) 28506* symbol modifiers <2>: M32C-Modifiers. (line 11) 28507* symbol modifiers <3>: M68HC11-Modifiers. (line 12) 28508* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6) 28509* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6) 28510* symbol names: Symbol Names. (line 6) 28511* symbol names, $ in: D10V-Chars. (line 46) 28512* symbol names, $ in <1>: D30V-Chars. (line 70) 28513* symbol names, $ in <2>: Meta-Chars. (line 10) 28514* symbol names, $ in <3>: SH-Chars. (line 15) 28515* symbol names, local: Symbol Names. (line 30) 28516* symbol names, temporary: Symbol Names. (line 43) 28517* symbol prefix character, ARC: ARC-Chars. (line 20) 28518* symbol storage class (COFF): Scl. (line 6) 28519* symbol type: Symbol Type. (line 6) 28520* symbol type, COFF: Type. (line 11) 28521* symbol type, ELF: Type. (line 22) 28522* symbol value: Symbol Value. (line 6) 28523* symbol value, setting: Set. (line 6) 28524* symbol values, assigning: Setting Symbols. (line 6) 28525* symbol versioning: Symver. (line 6) 28526* symbol, common: Comm. (line 6) 28527* symbol, making visible to linker: Global. (line 6) 28528* symbolic debuggers, information for: Stab. (line 6) 28529* symbols: Symbols. (line 6) 28530* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 28531* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 28532* symbols, assigning values to: Equ. (line 6) 28533* Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 28534* Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 28535* symbols, local common: Lcomm. (line 6) 28536* symver directive: Symver. (line 6) 28537* syntax compatibility, i386: i386-Variations. (line 6) 28538* syntax compatibility, x86-64: i386-Variations. (line 6) 28539* syntax, AVR: AVR-Modifiers. (line 6) 28540* syntax, Blackfin: Blackfin Syntax. (line 6) 28541* syntax, D10V: D10V-Syntax. (line 6) 28542* syntax, D30V: D30V-Syntax. (line 6) 28543* syntax, LM32: LM32-Modifiers. (line 6) 28544* syntax, M680x0: M68K-Syntax. (line 8) 28545* syntax, M68HC11: M68HC11-Syntax. (line 6) 28546* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) 28547* syntax, machine-independent: Syntax. (line 6) 28548* syntax, OPENRISC: OpenRISC-Dependent. (line 12) 28549* syntax, RL78: RL78-Modifiers. (line 6) 28550* syntax, RX: RX-Modifiers. (line 6) 28551* syntax, S12Z: S12Z Syntax. (line 11) 28552* syntax, SPARC: Sparc-Aligned-Data. (line 20) 28553* syntax, TILE-Gx: TILE-Gx Syntax. (line 6) 28554* syntax, TILEPro: TILEPro Syntax. (line 6) 28555* syntax, XGATE: XGATE-Syntax. (line 6) 28556* syntax, Xtensa assembler: Xtensa Syntax. (line 6) 28557* tab (\t): Strings. (line 27) 28558* tab directive, TIC54X: TIC54X-Directives. (line 245) 28559* tag directive: Tag. (line 6) 28560* tag directive, TIC54X: TIC54X-Directives. (line 214) 28561* tag directive, TIC54X <1>: TIC54X-Directives. (line 248) 28562* TBM, i386: i386-TBM. (line 6) 28563* TBM, x86-64: i386-TBM. (line 6) 28564* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 28565* temporary symbol names: Symbol Names. (line 43) 28566* text and data sections, joining: R. (line 6) 28567* text directive: Text. (line 6) 28568* text section: Ld Sections. (line 9) 28569* tfloat directive, i386: i386-Float. (line 14) 28570* tfloat directive, x86-64: i386-Float. (line 14) 28571* Thumb support: ARM-Dependent. (line 6) 28572* TIC54X builtin math functions: TIC54X-Builtins. (line 6) 28573* TIC54X line comment character: TIC54X-Chars. (line 6) 28574* TIC54X line separator: TIC54X-Chars. (line 17) 28575* TIC54X machine directives: TIC54X-Directives. (line 6) 28576* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 28577* TIC54X options: TIC54X-Opts. (line 6) 28578* TIC54X subsym builtins: TIC54X-Macros. (line 16) 28579* TIC54X support: TIC54X-Dependent. (line 6) 28580* TIC54X-specific macros: TIC54X-Macros. (line 6) 28581* TIC6X big-endian output: TIC6X Options. (line 46) 28582* TIC6X line comment character: TIC6X Syntax. (line 6) 28583* TIC6X line separator: TIC6X Syntax. (line 13) 28584* TIC6X little-endian output: TIC6X Options. (line 46) 28585* TIC6X machine directives: TIC6X Directives. (line 6) 28586* TIC6X options: TIC6X Options. (line 6) 28587* TIC6X support: TIC6X-Dependent. (line 6) 28588* TILE-Gx machine directives: TILE-Gx Directives. (line 6) 28589* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6) 28590* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6) 28591* TILE-Gx register names: TILE-Gx Registers. (line 6) 28592* TILE-Gx support: TILE-Gx-Dependent. (line 6) 28593* TILE-Gx syntax: TILE-Gx Syntax. (line 6) 28594* TILEPro machine directives: TILEPro Directives. (line 6) 28595* TILEPro modifiers: TILEPro Modifiers. (line 6) 28596* TILEPro opcode names: TILEPro Opcodes. (line 6) 28597* TILEPro register names: TILEPro Registers. (line 6) 28598* TILEPro support: TILEPro-Dependent. (line 6) 28599* TILEPro syntax: TILEPro Syntax. (line 6) 28600* time, total for assembly: statistics. (line 6) 28601* title directive: Title. (line 6) 28602* tls_gd directive, Nios II: Nios II Relocations. 28603 (line 38) 28604* tls_ie directive, Nios II: Nios II Relocations. 28605 (line 38) 28606* tls_ldm directive, Nios II: Nios II Relocations. 28607 (line 38) 28608* tls_ldo directive, Nios II: Nios II Relocations. 28609 (line 38) 28610* tls_le directive, Nios II: Nios II Relocations. 28611 (line 38) 28612* TMS320C6X support: TIC6X-Dependent. (line 6) 28613* tp register, V850: V850-Regs. (line 16) 28614* transform directive: Transform Directive. 28615 (line 6) 28616* trusted compiler: f. (line 6) 28617* turning preprocessing on and off: Preprocessing. (line 26) 28618* two-byte integer: 2byte. (line 6) 28619* type directive (COFF version): Type. (line 11) 28620* type directive (ELF version): Type. (line 22) 28621* type of a symbol: Symbol Type. (line 6) 28622* ualong directive, SH: SH Directives. (line 6) 28623* uaquad directive, SH: SH Directives. (line 6) 28624* uaword directive, SH: SH Directives. (line 6) 28625* ubyte directive, TIC54X: TIC54X-Directives. (line 34) 28626* uchar directive, TIC54X: TIC54X-Directives. (line 34) 28627* uhalf directive, TIC54X: TIC54X-Directives. (line 109) 28628* uint directive, TIC54X: TIC54X-Directives. (line 109) 28629* uleb128 directive: Uleb128. (line 6) 28630* ulong directive, TIC54X: TIC54X-Directives. (line 133) 28631* undefined section: Ld Sections. (line 36) 28632* union directive, TIC54X: TIC54X-Directives. (line 248) 28633* unsegm: Z8000 Directives. (line 14) 28634* usect directive, TIC54X: TIC54X-Directives. (line 260) 28635* ushort directive, TIC54X: TIC54X-Directives. (line 109) 28636* uword directive, TIC54X: TIC54X-Directives. (line 109) 28637* V850 command-line options: V850 Options. (line 9) 28638* V850 floating point (IEEE): V850 Floating Point. 28639 (line 6) 28640* V850 line comment character: V850-Chars. (line 6) 28641* V850 line separator: V850-Chars. (line 13) 28642* V850 machine directives: V850 Directives. (line 6) 28643* V850 opcodes: V850 Opcodes. (line 6) 28644* V850 options (none): V850 Options. (line 6) 28645* V850 register names: V850-Regs. (line 6) 28646* V850 support: V850-Dependent. (line 6) 28647* val directive: Val. (line 6) 28648* value attribute, COFF: Val. (line 6) 28649* value directive: i386-Directives. (line 26) 28650* value of a symbol: Symbol Value. (line 6) 28651* var directive, TIC54X: TIC54X-Directives. (line 270) 28652* VAX bitfields not supported: VAX-no. (line 6) 28653* VAX branch improvement: VAX-branch. (line 6) 28654* VAX command-line options ignored: VAX-Opts. (line 6) 28655* VAX displacement sizing character: VAX-operands. (line 12) 28656* VAX floating point: VAX-float. (line 6) 28657* VAX immediate character: VAX-operands. (line 6) 28658* VAX indirect character: VAX-operands. (line 9) 28659* VAX line comment character: VAX-Chars. (line 6) 28660* VAX line separator: VAX-Chars. (line 14) 28661* VAX machine directives: VAX-directives. (line 6) 28662* VAX opcode mnemonics: VAX-opcodes. (line 6) 28663* VAX operand notation: VAX-operands. (line 6) 28664* VAX register names: VAX-operands. (line 17) 28665* VAX support: Vax-Dependent. (line 6) 28666* Vax-11 C compatibility: VAX-Opts. (line 42) 28667* VAX/VMS options: VAX-Opts. (line 42) 28668* version directive: Version. (line 6) 28669* version directive, TIC54X: TIC54X-Directives. (line 274) 28670* version of assembler: v. (line 6) 28671* versions of symbols: Symver. (line 6) 28672* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides. 28673 (line 52) 28674* visibility: Hidden. (line 6) 28675* visibility <1>: Internal. (line 6) 28676* visibility <2>: Protected. (line 6) 28677* Visium line comment character: Visium Characters. (line 6) 28678* Visium line separator: Visium Characters. (line 14) 28679* Visium options: Visium Options. (line 6) 28680* Visium registers: Visium Registers. (line 6) 28681* Visium support: Visium-Dependent. (line 6) 28682* VMS (VAX) options: VAX-Opts. (line 42) 28683* vtable_entry directive: VTableEntry. (line 6) 28684* vtable_inherit directive: VTableInherit. (line 6) 28685* warning directive: Warning. (line 6) 28686* warning for altered difference tables: K. (line 6) 28687* warning messages: Errors. (line 6) 28688* warnings, causing error: W. (line 16) 28689* warnings, M32R: M32R-Warnings. (line 6) 28690* warnings, suppressing: W. (line 11) 28691* warnings, switching on: W. (line 19) 28692* weak directive: Weak. (line 6) 28693* weakref directive: Weakref. (line 6) 28694* WebAssembly floating point (IEEE): WebAssembly-Floating-Point. 28695 (line 6) 28696* WebAssembly line comment character: WebAssembly-Chars. (line 6) 28697* WebAssembly module layout: WebAssembly-module-layout. 28698 (line 6) 28699* WebAssembly notes: WebAssembly-Notes. (line 6) 28700* WebAssembly opcodes: WebAssembly-Opcodes. 28701 (line 6) 28702* WebAssembly relocations: WebAssembly-Relocs. (line 6) 28703* WebAssembly signatures: WebAssembly-Signatures. 28704 (line 6) 28705* WebAssembly support: WebAssembly-Dependent. 28706 (line 6) 28707* WebAssembly Syntax: WebAssembly-Syntax. (line 6) 28708* whitespace: Whitespace. (line 6) 28709* whitespace, removed by preprocessor: Preprocessing. (line 7) 28710* wide floating point directives, VAX: VAX-directives. (line 9) 28711* width directive, TIC54X: TIC54X-Directives. (line 125) 28712* Width of continuation lines of disassembly output: listing. 28713 (line 21) 28714* Width of first line disassembly output: listing. (line 16) 28715* Width of source line output: listing. (line 28) 28716* wmsg directive, TIC54X: TIC54X-Directives. (line 75) 28717* word aligned program counter, ARC: ARC-Regs. (line 44) 28718* word directive: Word. (line 6) 28719* word directive, BPF: BPF Directives. (line 12) 28720* word directive, H8/300: H8/300 Directives. (line 6) 28721* word directive, i386: i386-Float. (line 21) 28722* word directive, Nios II: Nios II Directives. (line 13) 28723* word directive, OpenRISC: OpenRISC-Directives. 28724 (line 12) 28725* word directive, PRU: PRU Directives. (line 10) 28726* word directive, SPARC: Sparc-Directives. (line 51) 28727* word directive, TIC54X: TIC54X-Directives. (line 109) 28728* word directive, x86-64: i386-Float. (line 21) 28729* writing patterns in memory: Fill. (line 6) 28730* wval: Z8000 Directives. (line 24) 28731* x86 machine directives: i386-Directives. (line 6) 28732* x86-64 arch directive: i386-Arch. (line 6) 28733* x86-64 att_syntax pseudo op: i386-Variations. (line 6) 28734* x86-64 conversion instructions: i386-Mnemonics. (line 56) 28735* x86-64 floating point: i386-Float. (line 6) 28736* x86-64 immediate operands: i386-Variations. (line 15) 28737* x86-64 instruction naming: i386-Mnemonics. (line 9) 28738* x86-64 intel_syntax pseudo op: i386-Variations. (line 6) 28739* x86-64 jump optimization: i386-Jumps. (line 6) 28740* x86-64 jump, call, return: i386-Variations. (line 45) 28741* x86-64 jump/call operands: i386-Variations. (line 15) 28742* x86-64 memory references: i386-Memory. (line 6) 28743* x86-64 options: i386-Options. (line 6) 28744* x86-64 register operands: i386-Variations. (line 15) 28745* x86-64 registers: i386-Regs. (line 6) 28746* x86-64 sections: i386-Variations. (line 51) 28747* x86-64 size suffixes: i386-Variations. (line 28) 28748* x86-64 source, destination operands: i386-Variations. (line 21) 28749* x86-64 support: i386-Dependent. (line 6) 28750* x86-64 syntax compatibility: i386-Variations. (line 6) 28751* xfloat directive, TIC54X: TIC54X-Directives. (line 62) 28752* XGATE addressing modes: XGATE-Syntax. (line 28) 28753* XGATE assembler directives: XGATE-Directives. (line 6) 28754* XGATE floating point: XGATE-Float. (line 6) 28755* XGATE line comment character: XGATE-Syntax. (line 16) 28756* XGATE line separator: XGATE-Syntax. (line 25) 28757* XGATE opcodes: XGATE-opcodes. (line 6) 28758* XGATE options: XGATE-Opts. (line 6) 28759* XGATE support: XGATE-Dependent. (line 6) 28760* XGATE syntax: XGATE-Syntax. (line 6) 28761* xlong directive, TIC54X: TIC54X-Directives. (line 133) 28762* XStormy16 comment character: XStormy16-Chars. (line 11) 28763* XStormy16 line comment character: XStormy16-Chars. (line 6) 28764* XStormy16 line separator: XStormy16-Chars. (line 14) 28765* XStormy16 machine directives: XStormy16 Directives. 28766 (line 6) 28767* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6) 28768* XStormy16 support: XSTORMY16-Dependent. 28769 (line 6) 28770* Xtensa architecture: Xtensa-Dependent. (line 6) 28771* Xtensa assembler syntax: Xtensa Syntax. (line 6) 28772* Xtensa directives: Xtensa Directives. (line 6) 28773* Xtensa opcode names: Xtensa Opcodes. (line 6) 28774* Xtensa register names: Xtensa Registers. (line 6) 28775* xword directive, SPARC: Sparc-Directives. (line 55) 28776* Z80 $: Z80-Chars. (line 15) 28777* Z80 ': Z80-Chars. (line 20) 28778* Z80 floating point: Z80 Floating Point. (line 6) 28779* Z80 labels: Z80-Labels. (line 6) 28780* Z80 line comment character: Z80-Chars. (line 6) 28781* Z80 line separator: Z80-Chars. (line 13) 28782* Z80 options: Z80 Options. (line 6) 28783* Z80 registers: Z80-Regs. (line 6) 28784* Z80 support: Z80-Dependent. (line 6) 28785* Z80 Syntax: Z80 Options. (line 114) 28786* Z80, case sensitivity: Z80-Case. (line 6) 28787* Z80, \: Z80-Chars. (line 18) 28788* Z80-only directives: Z80 Directives. (line 9) 28789* Z800 addressing modes: Z8000-Addressing. (line 6) 28790* Z8000 directives: Z8000 Directives. (line 6) 28791* Z8000 line comment character: Z8000-Chars. (line 6) 28792* Z8000 line separator: Z8000-Chars. (line 13) 28793* Z8000 opcode summary: Z8000 Opcodes. (line 6) 28794* Z8000 options: Z8000 Options. (line 6) 28795* Z8000 registers: Z8000-Regs. (line 6) 28796* Z8000 support: Z8000-Dependent. (line 6) 28797* zdaoff pseudo-op, V850: V850 Opcodes. (line 98) 28798* zero directive: Zero. (line 6) 28799* zero register, V850: V850-Regs. (line 7) 28800* zero-terminated strings: Asciz. (line 6) 28801 28802 28803 28804Tag Table: 28805Node: Top733 28806Node: Overview1718 28807Node: Manual43341 28808Node: GNU Assembler44285 28809Node: Object Formats45456 28810Node: Command Line45908 28811Node: Input Files46994 28812Node: Object48975 28813Node: Errors49871 28814Node: Invoking51433 28815Node: a53439 28816Node: alternate55350 28817Node: D55522 28818Node: f55755 28819Node: I56264 28820Node: K56808 28821Node: L57112 28822Node: listing57851 28823Node: M59510 28824Node: MD63347 28825Node: no-pad-sections63787 28826Node: o64162 28827Node: R64589 28828Node: statistics65619 28829Node: traditional-format66026 28830Node: v66499 28831Node: W66774 28832Node: Z67681 28833Node: Syntax68203 28834Node: Preprocessing68795 28835Node: Whitespace70359 28836Node: Comments70755 28837Node: Symbol Intro72766 28838Node: Statements73751 28839Node: Constants75739 28840Node: Characters76370 28841Node: Strings76872 28842Node: Chars79045 28843Node: Numbers79897 28844Node: Integers80437 28845Node: Bignums81093 28846Node: Flonums81449 28847Node: Sections83066 28848Node: Secs Background83444 28849Node: Ld Sections88477 28850Node: As Sections90861 28851Node: Sub-Sections91771 28852Node: bss94919 28853Node: Symbols95869 28854Node: Labels96517 28855Node: Setting Symbols97248 28856Node: Symbol Names97802 28857Node: Dot103269 28858Node: Symbol Attributes103716 28859Node: Symbol Value104449 28860Node: Symbol Type105494 28861Node: a.out Symbols105882 28862Node: Symbol Desc106144 28863Node: Symbol Other106440 28864Node: COFF Symbols106609 28865Node: SOM Symbols107282 28866Node: Expressions107724 28867Node: Empty Exprs108473 28868Node: Integer Exprs108820 28869Node: Arguments109215 28870Node: Operators110321 28871Node: Prefix Ops110656 28872Node: Infix Ops110983 28873Node: Pseudo Ops113377 28874Node: Abort119435 28875Node: ABORT (COFF)119848 28876Node: Align120056 28877Node: Altmacro122452 28878Node: Ascii123783 28879Node: Asciz124092 28880Node: Balign124337 28881Node: Bundle directives126336 28882Node: Byte129317 28883Node: CFI directives129576 28884Node: Comm138888 28885Ref: Comm-Footnote-1140488 28886Node: Data140850 28887Node: Dc141166 28888Node: Dcb142143 28889Node: Ds142936 28890Node: Def143766 28891Node: Desc143996 28892Node: Dim144496 28893Node: Double144753 28894Node: Eject145091 28895Node: Else145266 28896Node: Elseif145566 28897Node: End145860 28898Node: Endef146075 28899Node: Endfunc146252 28900Node: Endif146427 28901Node: Equ146688 28902Node: Equiv147203 28903Node: Eqv147759 28904Node: Err148123 28905Node: Error148434 28906Node: Exitm148879 28907Node: Extern149048 28908Node: Fail149309 28909Node: File149754 28910Node: Fill151083 28911Node: Float152047 28912Node: Func152389 28913Node: Global152979 28914Node: Gnu_attribute153736 28915Node: Hidden153961 28916Node: hword154547 28917Node: Ident154875 28918Node: If155449 28919Node: Incbin158510 28920Node: Include159204 28921Node: Int159755 28922Node: Internal160136 28923Node: Irp160783 28924Node: Irpc161662 28925Node: Lcomm162578 28926Node: Lflags163325 28927Node: Line163519 28928Node: Linkonce164435 28929Node: List165664 28930Node: Ln166271 28931Node: Loc166421 28932Node: Loc_mark_labels168613 28933Node: Local169097 28934Node: Long169709 28935Node: Macro169887 28936Node: MRI175818 28937Node: Noaltmacro176156 28938Node: Nolist176325 28939Node: Nops176754 28940Node: Octa177555 28941Node: Offset177890 28942Node: Org178217 28943Node: P2align179502 28944Node: PopSection181556 28945Node: Previous182064 28946Node: Print183476 28947Node: Protected183705 28948Node: Psize184352 28949Node: Purgem185036 28950Node: PushSection185257 28951Node: Quad186001 28952Node: Reloc186455 28953Node: Rept187216 28954Node: Sbttl187778 28955Node: Scl188143 28956Node: Section188484 28957Ref: Section Name Substitutions190542 28958Node: Set196651 28959Node: Short197743 28960Node: Single198064 28961Node: Size198409 28962Node: Skip199075 28963Node: Sleb128199399 28964Node: Space199721 28965Node: Stab200362 28966Node: String202365 28967Node: Struct203357 28968Node: SubSection204080 28969Node: Symver204641 28970Node: Tag207035 28971Node: Text207415 28972Node: Title207735 28973Node: Type208114 28974Node: Uleb128210575 28975Node: Val210897 28976Node: Version211147 28977Node: VTableEntry211421 28978Node: VTableInherit211711 28979Node: Warning212161 28980Node: Weak212395 28981Node: Weakref213064 28982Node: Word214029 28983Node: Zero215869 28984Node: 2byte216276 28985Node: 4byte217280 28986Node: 8byte217544 28987Node: Deprecated217821 28988Node: Object Attributes218056 28989Node: GNU Object Attributes219776 28990Node: Defining New Object Attributes223761 28991Node: Machine Dependencies224553 28992Node: AArch64-Dependent228588 28993Node: AArch64 Options229070 28994Node: AArch64 Extensions231928 28995Node: AArch64 Syntax237455 28996Node: AArch64-Chars237755 28997Node: AArch64-Regs238241 28998Node: AArch64-Relocations238535 28999Node: AArch64 Floating Point239609 29000Node: AArch64 Directives239834 29001Node: AArch64 Opcodes243761 29002Node: AArch64 Mapping Symbols244438 29003Node: Alpha-Dependent244819 29004Node: Alpha Notes245259 29005Node: Alpha Options245540 29006Node: Alpha Syntax248015 29007Node: Alpha-Chars248484 29008Node: Alpha-Regs248896 29009Node: Alpha-Relocs249283 29010Node: Alpha Floating Point255529 29011Node: Alpha Directives255751 29012Node: Alpha Opcodes261278 29013Node: ARC-Dependent261573 29014Node: ARC Options262018 29015Node: ARC Syntax265144 29016Node: ARC-Chars265372 29017Node: ARC-Regs266494 29018Node: ARC Directives269262 29019Node: ARC Modifiers277917 29020Node: ARC Symbols278927 29021Node: ARC Opcodes279481 29022Node: ARM-Dependent279727 29023Node: ARM Options280192 29024Node: ARM Syntax299684 29025Node: ARM-Instruction-Set300052 29026Node: ARM-Chars301267 29027Node: ARM-Regs301978 29028Node: ARM-Relocations302187 29029Node: ARM-Neon-Alignment303873 29030Node: ARM Floating Point304338 29031Node: ARM Directives304537 29032Ref: arm_fnend309696 29033Ref: arm_fnstart310015 29034Ref: arm_pad312423 29035Ref: arm_save313025 29036Ref: arm_setfp313726 29037Node: ARM Opcodes317012 29038Node: ARM Mapping Symbols319614 29039Node: ARM Unwinding Tutorial320423 29040Node: AVR-Dependent326623 29041Node: AVR Options326962 29042Node: AVR Syntax333280 29043Node: AVR-Chars333567 29044Node: AVR-Regs334126 29045Node: AVR-Modifiers334707 29046Node: AVR Opcodes336771 29047Node: AVR Pseudo Instructions342049 29048Node: Blackfin-Dependent343708 29049Node: Blackfin Options344019 29050Node: Blackfin Syntax344993 29051Node: Blackfin Directives351199 29052Node: BPF-Dependent351940 29053Node: BPF Options352257 29054Node: BPF Syntax352640 29055Node: BPF-Chars352908 29056Node: BPF-Regs353301 29057Node: BPF-Pseudo-Maps353813 29058Node: BPF Directives354233 29059Node: BPF Opcodes354647 29060Node: CR16-Dependent361205 29061Node: CR16 Operand Qualifiers361500 29062Node: CR16 Syntax364209 29063Node: CR16-Chars364395 29064Node: CRIS-Dependent364932 29065Node: CRIS-Opts365279 29066Ref: march-option366964 29067Node: CRIS-Expand368783 29068Node: CRIS-Symbols369966 29069Node: CRIS-Syntax371137 29070Node: CRIS-Chars371473 29071Node: CRIS-Pic372024 29072Ref: crispic372219 29073Node: CRIS-Regs375768 29074Node: CRIS-Pseudos376185 29075Ref: crisnous376962 29076Node: C-SKY-Dependent378250 29077Node: C-SKY Options378512 29078Node: C-SKY Syntax381497 29079Node: D10V-Dependent381742 29080Node: D10V-Opts382096 29081Node: D10V-Syntax383067 29082Node: D10V-Size383598 29083Node: D10V-Subs384571 29084Node: D10V-Chars385608 29085Node: D10V-Regs387421 29086Node: D10V-Addressing388450 29087Node: D10V-Word389130 29088Node: D10V-Float389647 29089Node: D10V-Opcodes389960 29090Node: D30V-Dependent390355 29091Node: D30V-Opts390712 29092Node: D30V-Syntax391390 29093Node: D30V-Size391924 29094Node: D30V-Subs392897 29095Node: D30V-Chars393934 29096Node: D30V-Guarded396544 29097Node: D30V-Regs397221 29098Node: D30V-Addressing398340 29099Node: D30V-Float399002 29100Node: D30V-Opcodes399315 29101Node: Epiphany-Dependent399710 29102Node: Epiphany Options399998 29103Node: Epiphany Syntax400397 29104Node: Epiphany-Chars400598 29105Node: H8/300-Dependent401152 29106Node: H8/300 Options401568 29107Node: H8/300 Syntax402008 29108Node: H8/300-Chars402309 29109Node: H8/300-Regs402608 29110Node: H8/300-Addressing403527 29111Node: H8/300 Floating Point404551 29112Node: H8/300 Directives404878 29113Node: H8/300 Opcodes406006 29114Node: HPPA-Dependent414325 29115Node: HPPA Notes414757 29116Node: HPPA Options415516 29117Node: HPPA Syntax415711 29118Node: HPPA Floating Point416981 29119Node: HPPA Directives417187 29120Node: HPPA Opcodes425869 29121Node: i386-Dependent426128 29122Node: i386-Options427453 29123Node: i386-Directives440137 29124Node: i386-Syntax441479 29125Node: i386-Variations441784 29126Node: i386-Chars444708 29127Node: i386-Mnemonics445437 29128Node: i386-Regs449198 29129Node: i386-Prefixes452028 29130Node: i386-Memory454788 29131Node: i386-Jumps457727 29132Node: i386-Float458850 29133Node: i386-SIMD460680 29134Node: i386-LWP461789 29135Node: i386-BMI462623 29136Node: i386-TBM463001 29137Node: i386-16bit463531 29138Node: i386-Arch465602 29139Node: i386-Bugs469070 29140Node: i386-Notes469821 29141Node: IA-64-Dependent470680 29142Node: IA-64 Options470981 29143Node: IA-64 Syntax474132 29144Node: IA-64-Chars474538 29145Node: IA-64-Regs474768 29146Node: IA-64-Bits475694 29147Node: IA-64-Relocs476224 29148Node: IA-64 Opcodes476695 29149Node: IP2K-Dependent476967 29150Node: IP2K-Opts477239 29151Node: IP2K-Syntax477738 29152Node: IP2K-Chars477912 29153Node: LM32-Dependent478455 29154Node: LM32 Options478750 29155Node: LM32 Syntax479383 29156Node: LM32-Regs479679 29157Node: LM32-Modifiers480620 29158Node: LM32-Chars482000 29159Node: LM32 Opcodes482508 29160Node: M32C-Dependent482812 29161Node: M32C-Opts483318 29162Node: M32C-Syntax483737 29163Node: M32C-Modifiers483972 29164Node: M32C-Chars485764 29165Node: M32R-Dependent486330 29166Node: M32R-Opts486651 29167Node: M32R-Directives490813 29168Node: M32R-Warnings494787 29169Node: M68K-Dependent497792 29170Node: M68K-Opts498259 29171Node: M68K-Syntax505681 29172Node: M68K-Moto-Syntax507521 29173Node: M68K-Float510105 29174Node: M68K-Directives510625 29175Node: M68K-opcodes511952 29176Node: M68K-Branch512178 29177Node: M68K-Chars516373 29178Node: M68HC11-Dependent517236 29179Node: M68HC11-Opts517767 29180Node: M68HC11-Syntax522079 29181Node: M68HC11-Modifiers524873 29182Node: M68HC11-Directives526700 29183Node: M68HC11-Float528074 29184Node: M68HC11-opcodes528602 29185Node: M68HC11-Branch528784 29186Node: S12Z-Dependent531234 29187Node: S12Z Options531577 29188Node: S12Z Syntax532561 29189Node: S12Z Syntax Overview532880 29190Node: S12Z Addressing Modes534542 29191Node: S12Z Register Notation538346 29192Node: Meta-Dependent539522 29193Node: Meta Options539804 29194Node: Meta Syntax540466 29195Node: Meta-Chars540678 29196Node: Meta-Regs540978 29197Node: MicroBlaze-Dependent541254 29198Node: MicroBlaze Directives541941 29199Node: MicroBlaze Syntax543332 29200Node: MicroBlaze-Chars543564 29201Node: MIPS-Dependent544116 29202Node: MIPS Options545550 29203Node: MIPS Macros564642 29204Ref: MIPS Macros-Footnote-1567356 29205Node: MIPS Symbol Sizes567499 29206Node: MIPS Small Data569171 29207Node: MIPS ISA571335 29208Node: MIPS assembly options573119 29209Node: MIPS autoextend574252 29210Node: MIPS insn574986 29211Node: MIPS FP ABIs576267 29212Node: MIPS FP ABI History576719 29213Node: MIPS FP ABI Variants577479 29214Node: MIPS FP ABI Selection580032 29215Node: MIPS FP ABI Compatibility581095 29216Node: MIPS NaN Encodings581905 29217Node: MIPS Option Stack583868 29218Node: MIPS ASE Instruction Generation Overrides584653 29219Node: MIPS Floating-Point589414 29220Node: MIPS Syntax590320 29221Node: MIPS-Chars590582 29222Node: MMIX-Dependent591124 29223Node: MMIX-Opts591504 29224Node: MMIX-Expand595110 29225Node: MMIX-Syntax596422 29226Ref: mmixsite596778 29227Node: MMIX-Chars597620 29228Node: MMIX-Symbols598493 29229Node: MMIX-Regs600564 29230Node: MMIX-Pseudos601589 29231Ref: MMIX-loc601731 29232Ref: MMIX-local602812 29233Ref: MMIX-is603345 29234Ref: MMIX-greg603617 29235Ref: GREG-base604535 29236Ref: MMIX-byte605854 29237Ref: MMIX-constants606326 29238Ref: MMIX-prefix606968 29239Ref: MMIX-spec607343 29240Node: MMIX-mmixal607677 29241Node: MSP430-Dependent611172 29242Node: MSP430 Options611641 29243Node: MSP430 Syntax615209 29244Node: MSP430-Macros615525 29245Node: MSP430-Chars616255 29246Node: MSP430-Regs616970 29247Node: MSP430-Ext617531 29248Node: MSP430 Floating Point619350 29249Node: MSP430 Directives619574 29250Node: MSP430 Opcodes621415 29251Node: MSP430 Profiling Capability621810 29252Node: NDS32-Dependent624138 29253Node: NDS32 Options624747 29254Node: NDS32 Syntax626630 29255Node: NDS32-Chars626898 29256Node: NDS32-Regs627365 29257Node: NDS32-Ops628219 29258Node: NiosII-Dependent631816 29259Node: Nios II Options632235 29260Node: Nios II Syntax633467 29261Node: Nios II Chars633673 29262Node: Nios II Relocations633864 29263Node: Nios II Directives635435 29264Node: Nios II Opcodes636997 29265Node: NS32K-Dependent637272 29266Node: NS32K Syntax637501 29267Node: NS32K-Chars637650 29268Node: OpenRISC-Dependent638390 29269Node: OpenRISC-Syntax638733 29270Node: OpenRISC-Chars639054 29271Node: OpenRISC-Regs639377 29272Node: OpenRISC-Relocs640390 29273Node: OpenRISC-Float645170 29274Node: OpenRISC-Directives645376 29275Node: OpenRISC-Opcodes646174 29276Node: PDP-11-Dependent646466 29277Node: PDP-11-Options646859 29278Node: PDP-11-Pseudos651918 29279Node: PDP-11-Syntax652263 29280Node: PDP-11-Mnemonics653095 29281Node: PDP-11-Synthetic653397 29282Node: PJ-Dependent653615 29283Node: PJ Options653878 29284Node: PJ Syntax654173 29285Node: PJ-Chars654338 29286Node: PPC-Dependent654887 29287Node: PowerPC-Opts655219 29288Node: PowerPC-Pseudo658943 29289Node: PowerPC-Syntax659564 29290Node: PowerPC-Chars659754 29291Node: PRU-Dependent660505 29292Node: PRU Options660888 29293Node: PRU Syntax661627 29294Node: PRU Chars661814 29295Node: PRU Relocations661969 29296Node: PRU Directives662520 29297Node: PRU Opcodes663423 29298Node: RISC-V-Dependent663840 29299Node: RISC-V-Options664215 29300Node: RISC-V-Directives665222 29301Node: RISC-V-Formats668947 29302Node: RISC-V-ATTRIBUTE676665 29303Node: RL78-Dependent678627 29304Node: RL78-Opts679028 29305Node: RL78-Modifiers679862 29306Node: RL78-Directives680641 29307Node: RL78-Syntax681245 29308Node: RL78-Chars681441 29309Node: RX-Dependent681997 29310Node: RX-Opts682428 29311Node: RX-Modifiers686692 29312Node: RX-Directives687795 29313Node: RX-Float688534 29314Node: RX-Syntax689169 29315Node: RX-Chars689348 29316Node: S/390-Dependent689900 29317Node: s390 Options690745 29318Node: s390 Characters692905 29319Node: s390 Syntax693426 29320Node: s390 Register694328 29321Node: s390 Mnemonics695144 29322Node: s390 Operands698164 29323Node: s390 Formats700795 29324Node: s390 Aliases708642 29325Node: s390 Operand Modifier712607 29326Node: s390 Instruction Marker716410 29327Node: s390 Literal Pool Entries717424 29328Node: s390 Directives719357 29329Node: s390 Floating Point724810 29330Node: SCORE-Dependent725258 29331Node: SCORE-Opts725560 29332Node: SCORE-Pseudo726847 29333Node: SCORE-Syntax728929 29334Node: SCORE-Chars729111 29335Node: SH-Dependent729669 29336Node: SH Options730081 29337Node: SH Syntax731132 29338Node: SH-Chars731405 29339Node: SH-Regs731948 29340Node: SH-Addressing732562 29341Node: SH Floating Point733470 29342Node: SH Directives734567 29343Node: SH Opcodes734968 29344Node: Sparc-Dependent739289 29345Node: Sparc-Opts739698 29346Node: Sparc-Aligned-Data745411 29347Node: Sparc-Syntax746243 29348Node: Sparc-Chars746817 29349Node: Sparc-Regs747380 29350Node: Sparc-Constants753228 29351Node: Sparc-Relocs757988 29352Node: Sparc-Size-Translations763106 29353Node: Sparc-Float764756 29354Node: Sparc-Directives764951 29355Node: TIC54X-Dependent766913 29356Node: TIC54X-Opts767676 29357Node: TIC54X-Block768717 29358Node: TIC54X-Env769077 29359Node: TIC54X-Constants769425 29360Node: TIC54X-Subsyms769822 29361Node: TIC54X-Locals771726 29362Node: TIC54X-Builtins772466 29363Node: TIC54X-Ext774880 29364Node: TIC54X-Directives775451 29365Node: TIC54X-Macros786359 29366Node: TIC54X-MMRegs788446 29367Node: TIC54X-Syntax788683 29368Node: TIC54X-Chars788873 29369Node: TIC6X-Dependent789564 29370Node: TIC6X Options789867 29371Node: TIC6X Syntax791866 29372Node: TIC6X Directives792969 29373Node: TILE-Gx-Dependent795253 29374Node: TILE-Gx Options795563 29375Node: TILE-Gx Syntax795912 29376Node: TILE-Gx Opcodes798148 29377Node: TILE-Gx Registers798436 29378Node: TILE-Gx Modifiers799207 29379Node: TILE-Gx Directives804206 29380Node: TILEPro-Dependent805109 29381Node: TILEPro Options805418 29382Node: TILEPro Syntax805602 29383Node: TILEPro Opcodes807838 29384Node: TILEPro Registers808129 29385Node: TILEPro Modifiers808899 29386Node: TILEPro Directives813688 29387Node: V850-Dependent814591 29388Node: V850 Options814987 29389Node: V850 Syntax819265 29390Node: V850-Chars819505 29391Node: V850-Regs820049 29392Node: V850 Floating Point821559 29393Node: V850 Directives821765 29394Node: V850 Opcodes823831 29395Node: Vax-Dependent829710 29396Node: VAX-Opts830294 29397Node: VAX-float834015 29398Node: VAX-directives834648 29399Node: VAX-opcodes835508 29400Node: VAX-branch835897 29401Node: VAX-operands838401 29402Node: VAX-no839164 29403Node: VAX-Syntax839420 29404Node: VAX-Chars839586 29405Node: Visium-Dependent840140 29406Node: Visium Options840453 29407Node: Visium Syntax840919 29408Node: Visium Characters841164 29409Node: Visium Registers841745 29410Node: Visium Opcodes842017 29411Node: WebAssembly-Dependent842443 29412Node: WebAssembly-Notes842884 29413Node: WebAssembly-Syntax843170 29414Node: WebAssembly-Chars843736 29415Node: WebAssembly-Relocs844115 29416Node: WebAssembly-Signatures844841 29417Node: WebAssembly-Floating-Point845342 29418Node: WebAssembly-Opcodes845583 29419Node: WebAssembly-module-layout846216 29420Node: XGATE-Dependent846696 29421Node: XGATE-Opts847123 29422Node: XGATE-Syntax848112 29423Node: XGATE-Directives850191 29424Node: XGATE-Float850430 29425Node: XGATE-opcodes850927 29426Node: XSTORMY16-Dependent851039 29427Node: XStormy16 Syntax851385 29428Node: XStormy16-Chars851575 29429Node: XStormy16 Directives852188 29430Node: XStormy16 Opcodes852842 29431Node: Xtensa-Dependent853897 29432Node: Xtensa Options854628 29433Node: Xtensa Syntax858895 29434Node: Xtensa Opcodes861039 29435Node: Xtensa Registers862832 29436Node: Xtensa Optimizations863465 29437Node: Density Instructions863917 29438Node: Xtensa Automatic Alignment865019 29439Node: Xtensa Relaxation867466 29440Node: Xtensa Branch Relaxation868431 29441Node: Xtensa Call Relaxation869803 29442Node: Xtensa Jump Relaxation871584 29443Node: Xtensa Immediate Relaxation873684 29444Node: Xtensa Directives876259 29445Node: Schedule Directive877967 29446Node: Longcalls Directive878307 29447Node: Transform Directive878851 29448Node: Literal Directive879593 29449Ref: Literal Directive-Footnote-1883132 29450Node: Literal Position Directive883274 29451Node: Literal Prefix Directive884973 29452Node: Absolute Literals Directive885871 29453Node: Z80-Dependent887178 29454Node: Z80 Options887566 29455Node: Z80 Syntax890856 29456Node: Z80-Chars891564 29457Node: Z80-Regs892415 29458Node: Z80-Case892767 29459Node: Z80-Labels893231 29460Node: Z80 Floating Point893727 29461Node: Z80 Directives894196 29462Node: Z80 Opcodes896178 29463Node: Z8000-Dependent897786 29464Node: Z8000 Options898722 29465Node: Z8000 Syntax898939 29466Node: Z8000-Chars899229 29467Node: Z8000-Regs899711 29468Node: Z8000-Addressing900501 29469Node: Z8000 Directives901611 29470Node: Z8000 Opcodes903220 29471Node: Reporting Bugs913162 29472Node: Bug Criteria913888 29473Node: Bug Reporting914655 29474Node: Acknowledgements921299 29475Ref: Acknowledgements-Footnote-1926265 29476Node: GNU Free Documentation License926291 29477Node: AS Index951441 29478 29479End Tag Table 29480