1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright (C) 1989-2018 Free Software Foundation, Inc. 3 This file is part of GAS, the GNU Assembler. 4 5 GAS is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3, or (at your option) 8 any later version. 9 10 GAS is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public 16 License along with GAS; see the file COPYING. If not, write 17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 18 Boston, MA 02110-1301, USA. */ 19 20 #include "as.h" 21 #include "safe-ctype.h" 22 #include "subsegs.h" 23 24 #include "opcode/sparc.h" 25 #include "dw2gencfi.h" 26 27 #include "elf/sparc.h" 28 #include "dwarf2dbg.h" 29 30 /* Some ancient Sun C compilers would not take such hex constants as 31 unsigned, and would end up sign-extending them to form an offsetT, 32 so use these constants instead. */ 33 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 34 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 35 36 static int sparc_ip (char *, const struct sparc_opcode **); 37 static int parse_sparc_asi (char **, const sparc_asi **); 38 static int parse_keyword_arg (int (*) (const char *), char **, int *); 39 static int parse_const_expr_arg (char **, int *); 40 static int get_expression (char *); 41 42 /* Default architecture. */ 43 /* ??? The default value should be V8, but sparclite support was added 44 by making it the default. GCC now passes -Asparclite, so maybe sometime in 45 the future we can set this to V8. */ 46 #ifndef DEFAULT_ARCH 47 #define DEFAULT_ARCH "sparclite" 48 #endif 49 static const char *default_arch = DEFAULT_ARCH; 50 51 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 52 have been set. */ 53 static int default_init_p; 54 55 /* Current architecture. We don't bump up unless necessary. */ 56 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 57 58 /* The maximum architecture level we can bump up to. 59 In a 32 bit environment, don't allow bumping up to v9 by default. 60 The native assembler works this way. The user is required to pass 61 an explicit argument before we'll create v9 object files. However, if 62 we don't see any v9 insns, a v8plus object file is not created. */ 63 static enum sparc_opcode_arch_val max_architecture; 64 65 /* Either 32 or 64, selects file format. */ 66 static int sparc_arch_size; 67 /* Initial (default) value, recorded separately in case a user option 68 changes the value before md_show_usage is called. */ 69 static int default_arch_size; 70 71 /* The currently selected v9 memory model. Currently only used for 72 ELF. */ 73 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 74 75 #ifndef TE_SOLARIS 76 /* Bitmask of instruction types seen so far, used to populate the 77 GNU attributes section with hwcap information. */ 78 static bfd_uint64_t hwcap_seen; 79 #endif 80 81 static bfd_uint64_t hwcap_allowed; 82 83 static int architecture_requested; 84 static int warn_on_bump; 85 86 /* If warn_on_bump and the needed architecture is higher than this 87 architecture, issue a warning. */ 88 static enum sparc_opcode_arch_val warn_after_architecture; 89 90 /* Non-zero if the assembler should generate error if an undeclared 91 g[23] register has been used in -64. */ 92 static int no_undeclared_regs; 93 94 /* Non-zero if the assembler should generate a warning if an 95 unpredictable DCTI (delayed control transfer instruction) couple is 96 found. */ 97 static int dcti_couples_detect; 98 99 /* Non-zero if we should try to relax jumps and calls. */ 100 static int sparc_relax; 101 102 /* Non-zero if we are generating PIC code. */ 103 int sparc_pic_code; 104 105 /* Non-zero if we should give an error when misaligned data is seen. */ 106 static int enforce_aligned_data; 107 108 extern int target_big_endian; 109 110 static int target_little_endian_data; 111 112 /* Symbols for global registers on v9. */ 113 static symbolS *globals[8]; 114 115 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 116 int sparc_cie_data_alignment; 117 118 /* V9 and 86x have big and little endian data, but instructions are always big 119 endian. The sparclet has bi-endian support but both data and insns have 120 the same endianness. Global `target_big_endian' is used for data. 121 The following macro is used for instructions. */ 122 #ifndef INSN_BIG_ENDIAN 123 #define INSN_BIG_ENDIAN (target_big_endian \ 124 || default_arch_type == sparc86x \ 125 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 126 #endif 127 128 /* Handle of the OPCODE hash table. */ 129 static struct hash_control *op_hash; 130 131 static void s_data1 (void); 132 static void s_seg (int); 133 static void s_proc (int); 134 static void s_reserve (int); 135 static void s_common (int); 136 static void s_empty (int); 137 static void s_uacons (int); 138 static void s_ncons (int); 139 static void s_register (int); 140 141 const pseudo_typeS md_pseudo_table[] = 142 { 143 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 144 {"common", s_common, 0}, 145 {"empty", s_empty, 0}, 146 {"global", s_globl, 0}, 147 {"half", cons, 2}, 148 {"nword", s_ncons, 0}, 149 {"optim", s_ignore, 0}, 150 {"proc", s_proc, 0}, 151 {"reserve", s_reserve, 0}, 152 {"seg", s_seg, 0}, 153 {"skip", s_space, 0}, 154 {"word", cons, 4}, 155 {"xword", cons, 8}, 156 {"uahalf", s_uacons, 2}, 157 {"uaword", s_uacons, 4}, 158 {"uaxword", s_uacons, 8}, 159 /* These are specific to sparc/svr4. */ 160 {"2byte", s_uacons, 2}, 161 {"4byte", s_uacons, 4}, 162 {"8byte", s_uacons, 8}, 163 {"register", s_register, 0}, 164 {NULL, 0, 0}, 165 }; 166 167 /* This array holds the chars that always start a comment. If the 168 pre-processor is disabled, these aren't very useful. */ 169 const char comment_chars[] = "!"; /* JF removed '|' from 170 comment_chars. */ 171 172 /* This array holds the chars that only start a comment at the beginning of 173 a line. If the line seems to have the form '# 123 filename' 174 .line and .file directives will appear in the pre-processed output. */ 175 /* Note that input_file.c hand checks for '#' at the beginning of the 176 first line of the input file. This is because the compiler outputs 177 #NO_APP at the beginning of its output. */ 178 /* Also note that comments started like this one will always 179 work if '/' isn't otherwise defined. */ 180 const char line_comment_chars[] = "#"; 181 182 const char line_separator_chars[] = ";"; 183 184 /* Chars that can be used to separate mant from exp in floating point 185 nums. */ 186 const char EXP_CHARS[] = "eE"; 187 188 /* Chars that mean this number is a floating point constant. 189 As in 0f12.456 190 or 0d1.2345e12 */ 191 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 192 193 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 194 changed in read.c. Ideally it shouldn't have to know about it at all, 195 but nothing is ideal around here. */ 196 197 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 198 199 struct sparc_it 200 { 201 const char *error; 202 unsigned long opcode; 203 struct nlist *nlistp; 204 expressionS exp; 205 expressionS exp2; 206 int pcrel; 207 bfd_reloc_code_real_type reloc; 208 }; 209 210 struct sparc_it the_insn, set_insn; 211 212 static void output_insn (const struct sparc_opcode *, struct sparc_it *); 213 214 /* Table of arguments to -A. 215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 216 for this use. That table is for opcodes only. This table is for opcodes 217 and file formats. */ 218 219 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, 220 v8plusa, v9, v9a, v9b, v9_64}; 221 222 static struct sparc_arch { 223 const char *name; 224 const char *opcode_arch; 225 enum sparc_arch_types arch_type; 226 /* Default word size, as specified during configuration. 227 A value of zero means can't be used to specify default architecture. */ 228 int default_arch_size; 229 /* Allowable arg to -A? */ 230 int user_option_p; 231 /* Extra hardware capabilities allowed. These are added to the 232 hardware capabilities associated with the opcode 233 architecture. */ 234 int hwcap_allowed; 235 int hwcap2_allowed; 236 } sparc_arch_table[] = { 237 { "v6", "v6", v6, 0, 1, 0, 0 }, 238 { "v7", "v7", v7, 0, 1, 0, 0 }, 239 { "v8", "v8", v8, 32, 1, 0, 0 }, 240 { "v8a", "v8", v8, 32, 1, 0, 0 }, 241 { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, 242 { "sparcvis", "v9a", v9, 0, 1, 0, 0 }, 243 { "sparcvis2", "v9b", v9, 0, 1, 0, 0 }, 244 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_FMAF, 0 }, 245 { "sparcima", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_IMA, 0 }, 246 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, 247 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, 248 249 { "sparc4", "v9v", v9, 0, 1, 0, 0 }, 250 { "sparc5", "v9m", v9, 0, 1, 0, 0 }, 251 { "sparc6", "m8", v9, 0, 1, 0, 0 }, 252 253 { "leon", "leon", leon, 32, 1, 0, 0 }, 254 { "sparclet", "sparclet", sparclet, 32, 1, 0, 0 }, 255 { "sparclite", "sparclite", sparclite, 32, 1, 0, 0 }, 256 { "sparc86x", "sparclite", sparc86x, 32, 1, 0, 0 }, 257 258 { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 }, 259 { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS, 0 }, 260 { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS, 0 }, 261 { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS, 0 }, 262 { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS, 0 }, 263 { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS, 0 }, 264 { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS, 0 }, 265 { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS, 0 }, 266 { "v8plusm8", "m8", v9, 0, 1, HWCAP_V8PLUS, 0 }, 267 268 { "v9", "v9", v9, 0, 1, 0, 0 }, 269 { "v9a", "v9a", v9, 0, 1, 0, 0 }, 270 { "v9b", "v9b", v9, 0, 1, 0, 0 }, 271 { "v9c", "v9c", v9, 0, 1, 0, 0 }, 272 { "v9d", "v9d", v9, 0, 1, 0, 0 }, 273 { "v9e", "v9e", v9, 0, 1, 0, 0 }, 274 { "v9v", "v9v", v9, 0, 1, 0, 0 }, 275 { "v9m", "v9m", v9, 0, 1, 0, 0 }, 276 { "v9m8", "m8", v9, 0, 1, 0, 0 }, 277 278 /* This exists to allow configure.tgt to pass one 279 value to specify both the default machine and default word size. */ 280 { "v9-64", "v9", v9, 64, 0, 0, 0 }, 281 { NULL, NULL, v8, 0, 0, 0, 0 } 282 }; 283 284 /* Variant of default_arch */ 285 static enum sparc_arch_types default_arch_type; 286 287 static struct sparc_arch * 288 lookup_arch (const char *name) 289 { 290 struct sparc_arch *sa; 291 292 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 293 if (strcmp (sa->name, name) == 0) 294 break; 295 if (sa->name == NULL) 296 return NULL; 297 return sa; 298 } 299 300 /* Initialize the default opcode arch and word size from the default 301 architecture name. */ 302 303 static void 304 init_default_arch (void) 305 { 306 struct sparc_arch *sa = lookup_arch (default_arch); 307 308 if (sa == NULL 309 || sa->default_arch_size == 0) 310 as_fatal (_("Invalid default architecture, broken assembler.")); 311 312 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 313 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 314 as_fatal (_("Bad opcode table, broken assembler.")); 315 default_arch_size = sparc_arch_size = sa->default_arch_size; 316 default_init_p = 1; 317 default_arch_type = sa->arch_type; 318 } 319 320 /* Called by TARGET_MACH. */ 321 322 unsigned long 323 sparc_mach (void) 324 { 325 /* We don't get a chance to initialize anything before we're called, 326 so handle that now. */ 327 if (! default_init_p) 328 init_default_arch (); 329 330 return sparc_arch_size == 64 ? bfd_mach_sparc_v9 : bfd_mach_sparc; 331 } 332 333 /* Called by TARGET_FORMAT. */ 334 335 const char * 336 sparc_target_format (void) 337 { 338 /* We don't get a chance to initialize anything before we're called, 339 so handle that now. */ 340 if (! default_init_p) 341 init_default_arch (); 342 343 #ifdef TE_VXWORKS 344 return "elf32-sparc-vxworks"; 345 #endif 346 347 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; 348 } 349 350 /* md_parse_option 351 * Invocation line includes a switch not recognized by the base assembler. 352 * See if it's a processor-specific option. These are: 353 * 354 * -bump 355 * Warn on architecture bumps. See also -A. 356 * 357 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet 358 * Standard 32 bit architectures. 359 * -Av9, -Av9a, -Av9b 360 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 361 * This used to only mean 64 bits, but properly specifying it 362 * complicated gcc's ASM_SPECs, so now opcode selection is 363 * specified orthogonally to word size (except when specifying 364 * the default, but that is an internal implementation detail). 365 * -Av8plus, -Av8plusa, -Av8plusb 366 * Same as -Av9{,a,b}. 367 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 368 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 369 * assembler. 370 * -xarch=v9, -xarch=v9a, -xarch=v9b 371 * Same as -Av9{,a,b} -64, for compatibility with Sun's 372 * assembler. 373 * 374 * Select the architecture and possibly the file format. 375 * Instructions or features not supported by the selected 376 * architecture cause fatal errors. 377 * 378 * The default is to start at v6, and bump the architecture up 379 * whenever an instruction is seen at a higher level. In 32 bit 380 * environments, v9 is not bumped up to, the user must pass 381 * -Av8plus{,a,b}. 382 * 383 * If -bump is specified, a warning is printing when bumping to 384 * higher levels. 385 * 386 * If an architecture is specified, all instructions must match 387 * that architecture. Any higher level instructions are flagged 388 * as errors. Note that in the 32 bit environment specifying 389 * -Av8plus does not automatically create a v8plus object file, a 390 * v9 insn must be seen. 391 * 392 * If both an architecture and -bump are specified, the 393 * architecture starts at the specified level, but bumps are 394 * warnings. Note that we can't set `current_architecture' to 395 * the requested level in this case: in the 32 bit environment, 396 * we still must avoid creating v8plus object files unless v9 397 * insns are seen. 398 * 399 * Note: 400 * Bumping between incompatible architectures is always an 401 * error. For example, from sparclite to v9. 402 */ 403 404 const char *md_shortopts = "A:K:VQ:sq"; 405 struct option md_longopts[] = { 406 #define OPTION_BUMP (OPTION_MD_BASE) 407 {"bump", no_argument, NULL, OPTION_BUMP}, 408 #define OPTION_SPARC (OPTION_MD_BASE + 1) 409 {"sparc", no_argument, NULL, OPTION_SPARC}, 410 #define OPTION_XARCH (OPTION_MD_BASE + 2) 411 {"xarch", required_argument, NULL, OPTION_XARCH}, 412 #define OPTION_32 (OPTION_MD_BASE + 3) 413 {"32", no_argument, NULL, OPTION_32}, 414 #define OPTION_64 (OPTION_MD_BASE + 4) 415 {"64", no_argument, NULL, OPTION_64}, 416 #define OPTION_TSO (OPTION_MD_BASE + 5) 417 {"TSO", no_argument, NULL, OPTION_TSO}, 418 #define OPTION_PSO (OPTION_MD_BASE + 6) 419 {"PSO", no_argument, NULL, OPTION_PSO}, 420 #define OPTION_RMO (OPTION_MD_BASE + 7) 421 {"RMO", no_argument, NULL, OPTION_RMO}, 422 #ifdef SPARC_BIENDIAN 423 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 424 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 425 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 426 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 427 #endif 428 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 429 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 430 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 431 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 432 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 433 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 434 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 435 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 436 #define OPTION_RELAX (OPTION_MD_BASE + 14) 437 {"relax", no_argument, NULL, OPTION_RELAX}, 438 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 439 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 440 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16) 441 {"dcti-couples-detect", no_argument, NULL, OPTION_DCTI_COUPLES_DETECT}, 442 {NULL, no_argument, NULL, 0} 443 }; 444 445 size_t md_longopts_size = sizeof (md_longopts); 446 447 int 448 md_parse_option (int c, const char *arg) 449 { 450 /* We don't get a chance to initialize anything before we're called, 451 so handle that now. */ 452 if (! default_init_p) 453 init_default_arch (); 454 455 switch (c) 456 { 457 case OPTION_BUMP: 458 warn_on_bump = 1; 459 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 460 break; 461 462 case OPTION_XARCH: 463 if (!strncmp (arg, "v9", 2)) 464 md_parse_option (OPTION_64, NULL); 465 else 466 { 467 if (!strncmp (arg, "v8", 2) 468 || !strncmp (arg, "v7", 2) 469 || !strncmp (arg, "v6", 2) 470 || !strcmp (arg, "sparclet") 471 || !strcmp (arg, "sparclite") 472 || !strcmp (arg, "sparc86x")) 473 md_parse_option (OPTION_32, NULL); 474 } 475 /* Fall through. */ 476 477 case 'A': 478 { 479 struct sparc_arch *sa; 480 enum sparc_opcode_arch_val opcode_arch; 481 482 sa = lookup_arch (arg); 483 if (sa == NULL 484 || ! sa->user_option_p) 485 { 486 if (c == OPTION_XARCH) 487 as_bad (_("invalid architecture -xarch=%s"), arg); 488 else 489 as_bad (_("invalid architecture -A%s"), arg); 490 return 0; 491 } 492 493 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 494 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 495 as_fatal (_("Bad opcode table, broken assembler.")); 496 497 if (!architecture_requested 498 || opcode_arch > max_architecture) 499 max_architecture = opcode_arch; 500 501 /* The allowed hardware capabilities are the implied by the 502 opcodes arch plus any extra capabilities defined in the GAS 503 arch. */ 504 hwcap_allowed 505 = (hwcap_allowed 506 | (((bfd_uint64_t) sparc_opcode_archs[opcode_arch].hwcaps2) << 32) 507 | (((bfd_uint64_t) sa->hwcap2_allowed) << 32) 508 | sparc_opcode_archs[opcode_arch].hwcaps 509 | sa->hwcap_allowed); 510 architecture_requested = 1; 511 } 512 break; 513 514 case OPTION_SPARC: 515 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 516 break; 517 518 case OPTION_ENFORCE_ALIGNED_DATA: 519 enforce_aligned_data = 1; 520 break; 521 522 #ifdef SPARC_BIENDIAN 523 case OPTION_LITTLE_ENDIAN: 524 target_big_endian = 0; 525 if (default_arch_type != sparclet) 526 as_fatal ("This target does not support -EL"); 527 break; 528 case OPTION_LITTLE_ENDIAN_DATA: 529 target_little_endian_data = 1; 530 target_big_endian = 0; 531 if (default_arch_type != sparc86x 532 && default_arch_type != v9) 533 as_fatal ("This target does not support --little-endian-data"); 534 break; 535 case OPTION_BIG_ENDIAN: 536 target_big_endian = 1; 537 break; 538 #endif 539 540 case OPTION_32: 541 case OPTION_64: 542 { 543 const char **list, **l; 544 545 sparc_arch_size = c == OPTION_32 ? 32 : 64; 546 list = bfd_target_list (); 547 for (l = list; *l != NULL; l++) 548 { 549 if (sparc_arch_size == 32) 550 { 551 if (CONST_STRNEQ (*l, "elf32-sparc")) 552 break; 553 } 554 else 555 { 556 if (CONST_STRNEQ (*l, "elf64-sparc")) 557 break; 558 } 559 } 560 if (*l == NULL) 561 as_fatal (_("No compiled in support for %d bit object file format"), 562 sparc_arch_size); 563 free (list); 564 565 if (sparc_arch_size == 64 566 && max_architecture < SPARC_OPCODE_ARCH_V9) 567 max_architecture = SPARC_OPCODE_ARCH_V9; 568 } 569 break; 570 571 case OPTION_TSO: 572 sparc_memory_model = MM_TSO; 573 break; 574 575 case OPTION_PSO: 576 sparc_memory_model = MM_PSO; 577 break; 578 579 case OPTION_RMO: 580 sparc_memory_model = MM_RMO; 581 break; 582 583 case 'V': 584 print_version_id (); 585 break; 586 587 case 'Q': 588 /* Qy - do emit .comment 589 Qn - do not emit .comment. */ 590 break; 591 592 case 's': 593 /* Use .stab instead of .stab.excl. */ 594 break; 595 596 case 'q': 597 /* quick -- Native assembler does fewer checks. */ 598 break; 599 600 case 'K': 601 if (strcmp (arg, "PIC") != 0) 602 as_warn (_("Unrecognized option following -K")); 603 else 604 sparc_pic_code = 1; 605 break; 606 607 case OPTION_NO_UNDECLARED_REGS: 608 no_undeclared_regs = 1; 609 break; 610 611 case OPTION_UNDECLARED_REGS: 612 no_undeclared_regs = 0; 613 break; 614 615 case OPTION_RELAX: 616 sparc_relax = 1; 617 break; 618 619 case OPTION_NO_RELAX: 620 sparc_relax = 0; 621 break; 622 623 case OPTION_DCTI_COUPLES_DETECT: 624 dcti_couples_detect = 1; 625 break; 626 627 default: 628 return 0; 629 } 630 631 return 1; 632 } 633 634 void 635 md_show_usage (FILE *stream) 636 { 637 const struct sparc_arch *arch; 638 int column; 639 640 /* We don't get a chance to initialize anything before we're called, 641 so handle that now. */ 642 if (! default_init_p) 643 init_default_arch (); 644 645 fprintf (stream, _("SPARC options:\n")); 646 column = 0; 647 for (arch = &sparc_arch_table[0]; arch->name; arch++) 648 { 649 if (!arch->user_option_p) 650 continue; 651 if (arch != &sparc_arch_table[0]) 652 fprintf (stream, " | "); 653 if (column + strlen (arch->name) > 70) 654 { 655 column = 0; 656 fputc ('\n', stream); 657 } 658 column += 5 + 2 + strlen (arch->name); 659 fprintf (stream, "-A%s", arch->name); 660 } 661 for (arch = &sparc_arch_table[0]; arch->name; arch++) 662 { 663 if (!arch->user_option_p) 664 continue; 665 fprintf (stream, " | "); 666 if (column + strlen (arch->name) > 65) 667 { 668 column = 0; 669 fputc ('\n', stream); 670 } 671 column += 5 + 7 + strlen (arch->name); 672 fprintf (stream, "-xarch=%s", arch->name); 673 } 674 fprintf (stream, _("\n\ 675 specify variant of SPARC architecture\n\ 676 -bump warn when assembler switches architectures\n\ 677 -sparc ignored\n\ 678 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 679 -relax relax jumps and branches (default)\n\ 680 -no-relax avoid changing any jumps and branches\n")); 681 fprintf (stream, _("\ 682 -32 create 32 bit object file\n\ 683 -64 create 64 bit object file\n")); 684 fprintf (stream, _("\ 685 [default is %d]\n"), default_arch_size); 686 fprintf (stream, _("\ 687 -TSO use Total Store Ordering\n\ 688 -PSO use Partial Store Ordering\n\ 689 -RMO use Relaxed Memory Ordering\n")); 690 fprintf (stream, _("\ 691 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 692 fprintf (stream, _("\ 693 -KPIC generate PIC\n\ 694 -V print assembler version number\n\ 695 -undeclared-regs ignore application global register usage without\n\ 696 appropriate .register directive (default)\n\ 697 -no-undeclared-regs force error on application global register usage\n\ 698 without appropriate .register directive\n\ 699 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\ 700 -q ignored\n\ 701 -Qy, -Qn ignored\n\ 702 -s ignored\n")); 703 #ifdef SPARC_BIENDIAN 704 fprintf (stream, _("\ 705 -EL generate code for a little endian machine\n\ 706 -EB generate code for a big endian machine\n\ 707 --little-endian-data generate code for a machine having big endian\n\ 708 instructions and little endian data.\n")); 709 #endif 710 } 711 712 /* Native operand size opcode translation. */ 713 static struct 714 { 715 const char *name; 716 const char *name32; 717 const char *name64; 718 } native_op_table[] = 719 { 720 {"ldn", "ld", "ldx"}, 721 {"ldna", "lda", "ldxa"}, 722 {"stn", "st", "stx"}, 723 {"stna", "sta", "stxa"}, 724 {"slln", "sll", "sllx"}, 725 {"srln", "srl", "srlx"}, 726 {"sran", "sra", "srax"}, 727 {"casn", "cas", "casx"}, 728 {"casna", "casa", "casxa"}, 729 {"clrn", "clr", "clrx"}, 730 {NULL, NULL, NULL}, 731 }; 732 733 /* sparc64 privileged and hyperprivileged registers. */ 734 735 struct priv_reg_entry 736 { 737 const char *name; 738 int regnum; 739 }; 740 741 struct priv_reg_entry priv_reg_table[] = 742 { 743 {"tpc", 0}, 744 {"tnpc", 1}, 745 {"tstate", 2}, 746 {"tt", 3}, 747 {"tick", 4}, 748 {"tba", 5}, 749 {"pstate", 6}, 750 {"tl", 7}, 751 {"pil", 8}, 752 {"cwp", 9}, 753 {"cansave", 10}, 754 {"canrestore", 11}, 755 {"cleanwin", 12}, 756 {"otherwin", 13}, 757 {"wstate", 14}, 758 {"fq", 15}, 759 {"gl", 16}, 760 {"pmcdper", 23}, 761 {"ver", 31}, 762 {NULL, -1}, /* End marker. */ 763 }; 764 765 struct priv_reg_entry hpriv_reg_table[] = 766 { 767 {"hpstate", 0}, 768 {"htstate", 1}, 769 {"hintp", 3}, 770 {"htba", 5}, 771 {"hver", 6}, 772 {"hmcdper", 23}, 773 {"hmcddfr", 24}, 774 {"hva_mask_nz", 27}, 775 {"hstick_offset", 28}, 776 {"hstick_enable", 29}, 777 {"hstick_cmpr", 31}, 778 {NULL, -1}, /* End marker. */ 779 }; 780 781 /* v9a or later specific ancillary state registers. */ 782 783 struct priv_reg_entry v9a_asr_table[] = 784 { 785 {"tick_cmpr", 23}, 786 {"sys_tick_cmpr", 25}, 787 {"sys_tick", 24}, 788 {"stick_cmpr", 25}, 789 {"stick", 24}, 790 {"softint_clear", 21}, 791 {"softint_set", 20}, 792 {"softint", 22}, 793 {"set_softint", 20}, 794 {"pause", 27}, 795 {"pic", 17}, 796 {"pcr", 16}, 797 {"mwait", 28}, 798 {"gsr", 19}, 799 {"dcr", 18}, 800 {"cfr", 26}, 801 {"clear_softint", 21}, 802 {NULL, -1}, /* End marker. */ 803 }; 804 805 static int 806 cmp_reg_entry (const void *parg, const void *qarg) 807 { 808 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 809 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 810 811 if (p->name == q->name) 812 return 0; 813 else if (p->name == NULL) 814 return 1; 815 else if (q->name == NULL) 816 return -1; 817 else 818 return strcmp (q->name, p->name); 819 } 820 821 /* sparc %-pseudo-operations. */ 822 823 824 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */ 825 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative 826 contexts. */ 827 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */ 828 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the 829 last operand of an 830 instruction. (Generally they can appear 831 anywhere an immediate operand is 832 expected. */ 833 struct pop_entry 834 { 835 /* The name as it appears in assembler. */ 836 const char *name; 837 /* The reloc this pseudo-op translates to. */ 838 bfd_reloc_code_real_type reloc; 839 /* Flags. See F_POP_* above. */ 840 int flags; 841 }; 842 843 struct pop_entry pop_table[] = 844 { 845 { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 }, 846 { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 }, 847 { "hi", BFD_RELOC_HI22, F_POP_PCREL }, 848 { "lo", BFD_RELOC_LO10, F_POP_PCREL }, 849 { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL }, 850 { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL }, 851 { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL }, 852 { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL }, 853 { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL }, 854 { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 }, 855 { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 }, 856 { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 }, 857 { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 }, 858 { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 }, 859 { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 }, 860 { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 }, 861 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 }, 862 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 }, 863 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 }, 864 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 }, 865 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 }, 866 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 }, 867 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 }, 868 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 }, 869 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 }, 870 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 }, 871 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 }, 872 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 }, 873 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX }, 874 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, 875 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX }, 876 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, 877 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX }, 878 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX }, 879 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX }, 880 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX }, 881 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX } 882 }; 883 884 /* Table of %-names that can appear in a sparc assembly program. This 885 table is initialized in md_begin and contains entries for each 886 privileged/hyperprivileged/alternate register and %-pseudo-op. */ 887 888 enum perc_entry_type 889 { 890 perc_entry_none = 0, 891 perc_entry_reg, 892 perc_entry_post_pop, 893 perc_entry_imm_pop 894 }; 895 896 struct perc_entry 897 { 898 /* Entry type. */ 899 enum perc_entry_type type; 900 /* Name of the %-entity. */ 901 const char *name; 902 /* strlen (name). */ 903 int len; 904 /* Value. Either a pop or a reg depending on type.*/ 905 union 906 { 907 struct pop_entry *pop; 908 struct priv_reg_entry *reg; 909 }; 910 }; 911 912 #define NUM_PERC_ENTRIES \ 913 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \ 914 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \ 915 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \ 916 + ARRAY_SIZE (pop_table) \ 917 + 1) 918 919 struct perc_entry perc_table[NUM_PERC_ENTRIES]; 920 921 static int 922 cmp_perc_entry (const void *parg, const void *qarg) 923 { 924 const struct perc_entry *p = (const struct perc_entry *) parg; 925 const struct perc_entry *q = (const struct perc_entry *) qarg; 926 927 if (p->name == q->name) 928 return 0; 929 else if (p->name == NULL) 930 return 1; 931 else if (q->name == NULL) 932 return -1; 933 else 934 return strcmp (q->name, p->name); 935 } 936 937 /* This function is called once, at assembler startup time. It should 938 set up all the tables, etc. that the MD part of the assembler will 939 need. */ 940 941 void 942 md_begin (void) 943 { 944 const char *retval = NULL; 945 int lose = 0; 946 unsigned int i = 0; 947 948 /* We don't get a chance to initialize anything before md_parse_option 949 is called, and it may not be called, so handle default initialization 950 now if not already done. */ 951 if (! default_init_p) 952 init_default_arch (); 953 954 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 955 op_hash = hash_new (); 956 957 while (i < (unsigned int) sparc_num_opcodes) 958 { 959 const char *name = sparc_opcodes[i].name; 960 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); 961 if (retval != NULL) 962 { 963 as_bad (_("Internal error: can't hash `%s': %s\n"), 964 sparc_opcodes[i].name, retval); 965 lose = 1; 966 } 967 do 968 { 969 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 970 { 971 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 972 sparc_opcodes[i].name, sparc_opcodes[i].args); 973 lose = 1; 974 } 975 ++i; 976 } 977 while (i < (unsigned int) sparc_num_opcodes 978 && !strcmp (sparc_opcodes[i].name, name)); 979 } 980 981 for (i = 0; native_op_table[i].name; i++) 982 { 983 const struct sparc_opcode *insn; 984 const char *name = ((sparc_arch_size == 32) 985 ? native_op_table[i].name32 986 : native_op_table[i].name64); 987 insn = (struct sparc_opcode *) hash_find (op_hash, name); 988 if (insn == NULL) 989 { 990 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 991 name, native_op_table[i].name); 992 lose = 1; 993 } 994 else 995 { 996 retval = hash_insert (op_hash, native_op_table[i].name, 997 (void *) insn); 998 if (retval != NULL) 999 { 1000 as_bad (_("Internal error: can't hash `%s': %s\n"), 1001 sparc_opcodes[i].name, retval); 1002 lose = 1; 1003 } 1004 } 1005 } 1006 1007 if (lose) 1008 as_fatal (_("Broken assembler. No assembly attempted.")); 1009 1010 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 1011 sizeof (priv_reg_table[0]), cmp_reg_entry); 1012 qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]), 1013 sizeof (hpriv_reg_table[0]), cmp_reg_entry); 1014 qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]), 1015 sizeof (v9a_asr_table[0]), cmp_reg_entry); 1016 1017 /* If -bump, record the architecture level at which we start issuing 1018 warnings. The behaviour is different depending upon whether an 1019 architecture was explicitly specified. If it wasn't, we issue warnings 1020 for all upwards bumps. If it was, we don't start issuing warnings until 1021 we need to bump beyond the requested architecture or when we bump between 1022 conflicting architectures. */ 1023 1024 if (warn_on_bump 1025 && architecture_requested) 1026 { 1027 /* `max_architecture' records the requested architecture. 1028 Issue warnings if we go above it. */ 1029 warn_after_architecture = max_architecture; 1030 } 1031 1032 /* Find the highest architecture level that doesn't conflict with 1033 the requested one. */ 1034 1035 if (warn_on_bump 1036 || !architecture_requested) 1037 { 1038 enum sparc_opcode_arch_val current_max_architecture 1039 = max_architecture; 1040 1041 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 1042 max_architecture > warn_after_architecture; 1043 --max_architecture) 1044 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 1045 current_max_architecture)) 1046 break; 1047 } 1048 1049 /* Prepare the tables of %-pseudo-ops. */ 1050 { 1051 struct priv_reg_entry *reg_tables[] 1052 = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL}; 1053 struct priv_reg_entry **reg_table; 1054 int entry = 0; 1055 1056 /* Add registers. */ 1057 for (reg_table = reg_tables; reg_table[0]; reg_table++) 1058 { 1059 struct priv_reg_entry *reg; 1060 for (reg = *reg_table; reg->name; reg++) 1061 { 1062 struct perc_entry *p = &perc_table[entry++]; 1063 p->type = perc_entry_reg; 1064 p->name = reg->name; 1065 p->len = strlen (reg->name); 1066 p->reg = reg; 1067 } 1068 } 1069 1070 /* Add %-pseudo-ops. */ 1071 for (i = 0; i < ARRAY_SIZE (pop_table); i++) 1072 { 1073 struct perc_entry *p = &perc_table[entry++]; 1074 p->type = (pop_table[i].flags & F_POP_POSTFIX 1075 ? perc_entry_post_pop : perc_entry_imm_pop); 1076 p->name = pop_table[i].name; 1077 p->len = strlen (pop_table[i].name); 1078 p->pop = &pop_table[i]; 1079 } 1080 1081 /* Last entry is the sentinel. */ 1082 perc_table[entry].type = perc_entry_none; 1083 1084 qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]), 1085 sizeof (perc_table[0]), cmp_perc_entry); 1086 1087 } 1088 } 1089 1090 /* Called after all assembly has been done. */ 1091 1092 void 1093 sparc_md_end (void) 1094 { 1095 unsigned long mach; 1096 #ifndef TE_SOLARIS 1097 int hwcaps, hwcaps2; 1098 #endif 1099 1100 if (sparc_arch_size == 64) 1101 switch (current_architecture) 1102 { 1103 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 1104 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 1105 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break; 1106 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break; 1107 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break; 1108 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break; 1109 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break; 1110 case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v9m8; break; 1111 default: mach = bfd_mach_sparc_v9; break; 1112 } 1113 else 1114 switch (current_architecture) 1115 { 1116 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 1117 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 1118 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 1119 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 1120 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break; 1121 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break; 1122 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break; 1123 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break; 1124 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break; 1125 case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v8plusm8; break; 1126 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 1127 be but for now it is (since that's the way it's always been 1128 treated). */ 1129 default: mach = bfd_mach_sparc; break; 1130 } 1131 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 1132 1133 #ifndef TE_SOLARIS 1134 hwcaps = hwcap_seen & U0xffffffff; 1135 hwcaps2 = hwcap_seen >> 32; 1136 1137 if (hwcaps) 1138 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); 1139 if (hwcaps2) 1140 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); 1141 #endif 1142 } 1143 1144 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 1145 1146 static inline int 1147 in_signed_range (bfd_signed_vma val, bfd_signed_vma max) 1148 { 1149 if (max <= 0) 1150 abort (); 1151 /* Sign-extend the value from the architecture word size, so that 1152 0xffffffff is always considered -1 on sparc32. */ 1153 if (sparc_arch_size == 32) 1154 { 1155 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 1156 val = ((val & U0xffffffff) ^ sign) - sign; 1157 } 1158 if (val > max) 1159 return 0; 1160 if (val < ~max) 1161 return 0; 1162 return 1; 1163 } 1164 1165 /* Return non-zero if VAL is in the range 0 to MAX. */ 1166 1167 static inline int 1168 in_unsigned_range (bfd_vma val, bfd_vma max) 1169 { 1170 if (val > max) 1171 return 0; 1172 return 1; 1173 } 1174 1175 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 1176 (e.g. -15 to +31). */ 1177 1178 static inline int 1179 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) 1180 { 1181 if (max <= 0) 1182 abort (); 1183 if (val > max) 1184 return 0; 1185 if (val < ~(max >> 1)) 1186 return 0; 1187 return 1; 1188 } 1189 1190 static int 1191 sparc_ffs (unsigned int mask) 1192 { 1193 int i; 1194 1195 if (mask == 0) 1196 return -1; 1197 1198 for (i = 0; (mask & 1) == 0; ++i) 1199 mask >>= 1; 1200 return i; 1201 } 1202 1203 /* Implement big shift right. */ 1204 static bfd_vma 1205 BSR (bfd_vma val, int amount) 1206 { 1207 if (sizeof (bfd_vma) <= 4 && amount >= 32) 1208 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 1209 return val >> amount; 1210 } 1211 1212 /* For communication between sparc_ip and get_expression. */ 1213 static char *expr_end; 1214 1215 /* Values for `special_case'. 1216 Instructions that require weird handling because they're longer than 1217 4 bytes. */ 1218 #define SPECIAL_CASE_NONE 0 1219 #define SPECIAL_CASE_SET 1 1220 #define SPECIAL_CASE_SETSW 2 1221 #define SPECIAL_CASE_SETX 3 1222 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1223 #define SPECIAL_CASE_FDIV 4 1224 1225 /* Bit masks of various insns. */ 1226 #define NOP_INSN 0x01000000 1227 #define OR_INSN 0x80100000 1228 #define XOR_INSN 0x80180000 1229 #define FMOVS_INSN 0x81A00020 1230 #define SETHI_INSN 0x01000000 1231 #define SLLX_INSN 0x81281000 1232 #define SRA_INSN 0x81380000 1233 1234 /* The last instruction to be assembled. */ 1235 static const struct sparc_opcode *last_insn; 1236 /* The assembled opcode of `last_insn'. */ 1237 static unsigned long last_opcode; 1238 1239 /* Handle the set and setuw synthetic instructions. */ 1240 1241 static void 1242 synthetize_setuw (const struct sparc_opcode *insn) 1243 { 1244 int need_hi22_p = 0; 1245 int rd = (the_insn.opcode & RD (~0)) >> 25; 1246 1247 if (the_insn.exp.X_op == O_constant) 1248 { 1249 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1250 { 1251 if (sizeof (offsetT) > 4 1252 && (the_insn.exp.X_add_number < 0 1253 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1254 as_warn (_("set: number not in 0..4294967295 range")); 1255 } 1256 else 1257 { 1258 if (sizeof (offsetT) > 4 1259 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1260 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1261 as_warn (_("set: number not in -2147483648..4294967295 range")); 1262 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1263 } 1264 } 1265 1266 /* See if operand is absolute and small; skip sethi if so. */ 1267 if (the_insn.exp.X_op != O_constant 1268 || the_insn.exp.X_add_number >= (1 << 12) 1269 || the_insn.exp.X_add_number < -(1 << 12)) 1270 { 1271 the_insn.opcode = (SETHI_INSN | RD (rd) 1272 | ((the_insn.exp.X_add_number >> 10) 1273 & (the_insn.exp.X_op == O_constant 1274 ? 0x3fffff : 0))); 1275 the_insn.reloc = (the_insn.exp.X_op != O_constant 1276 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1277 output_insn (insn, &the_insn); 1278 need_hi22_p = 1; 1279 } 1280 1281 /* See if operand has no low-order bits; skip OR if so. */ 1282 if (the_insn.exp.X_op != O_constant 1283 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1284 || ! need_hi22_p) 1285 { 1286 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1287 | RD (rd) | IMMED 1288 | (the_insn.exp.X_add_number 1289 & (the_insn.exp.X_op != O_constant 1290 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1291 the_insn.reloc = (the_insn.exp.X_op != O_constant 1292 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1293 output_insn (insn, &the_insn); 1294 } 1295 } 1296 1297 /* Handle the setsw synthetic instruction. */ 1298 1299 static void 1300 synthetize_setsw (const struct sparc_opcode *insn) 1301 { 1302 int low32, rd, opc; 1303 1304 rd = (the_insn.opcode & RD (~0)) >> 25; 1305 1306 if (the_insn.exp.X_op != O_constant) 1307 { 1308 synthetize_setuw (insn); 1309 1310 /* Need to sign extend it. */ 1311 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1312 the_insn.reloc = BFD_RELOC_NONE; 1313 output_insn (insn, &the_insn); 1314 return; 1315 } 1316 1317 if (sizeof (offsetT) > 4 1318 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1319 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1320 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1321 1322 low32 = the_insn.exp.X_add_number; 1323 1324 if (low32 >= 0) 1325 { 1326 synthetize_setuw (insn); 1327 return; 1328 } 1329 1330 opc = OR_INSN; 1331 1332 the_insn.reloc = BFD_RELOC_NONE; 1333 /* See if operand is absolute and small; skip sethi if so. */ 1334 if (low32 < -(1 << 12)) 1335 { 1336 the_insn.opcode = (SETHI_INSN | RD (rd) 1337 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1338 output_insn (insn, &the_insn); 1339 low32 = 0x1c00 | (low32 & 0x3ff); 1340 opc = RS1 (rd) | XOR_INSN; 1341 } 1342 1343 the_insn.opcode = (opc | RD (rd) | IMMED 1344 | (low32 & 0x1fff)); 1345 output_insn (insn, &the_insn); 1346 } 1347 1348 /* Handle the setx synthetic instruction. */ 1349 1350 static void 1351 synthetize_setx (const struct sparc_opcode *insn) 1352 { 1353 int upper32, lower32; 1354 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1355 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1356 int upper_dstreg; 1357 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1358 int need_xor10_p = 0; 1359 1360 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1361 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1362 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1363 #undef SIGNEXT32 1364 1365 upper_dstreg = tmpreg; 1366 /* The tmp reg should not be the dst reg. */ 1367 if (tmpreg == dstreg) 1368 as_warn (_("setx: temporary register same as destination register")); 1369 1370 /* ??? Obviously there are other optimizations we can do 1371 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1372 doing some of these. Later. If you do change things, try to 1373 change all of this to be table driven as well. */ 1374 /* What to output depends on the number if it's constant. 1375 Compute that first, then output what we've decided upon. */ 1376 if (the_insn.exp.X_op != O_constant) 1377 { 1378 if (sparc_arch_size == 32) 1379 { 1380 /* When arch size is 32, we want setx to be equivalent 1381 to setuw for anything but constants. */ 1382 the_insn.exp.X_add_number &= 0xffffffff; 1383 synthetize_setuw (insn); 1384 return; 1385 } 1386 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1387 lower32 = 0; 1388 upper32 = 0; 1389 } 1390 else 1391 { 1392 /* Reset X_add_number, we've extracted it as upper32/lower32. 1393 Otherwise fixup_segment will complain about not being able to 1394 write an 8 byte number in a 4 byte field. */ 1395 the_insn.exp.X_add_number = 0; 1396 1397 /* Only need hh22 if `or' insn can't handle constant. */ 1398 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1399 need_hh22_p = 1; 1400 1401 /* Does bottom part (after sethi) have bits? */ 1402 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1403 /* No hh22, but does upper32 still have bits we can't set 1404 from lower32? */ 1405 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1406 need_hm10_p = 1; 1407 1408 /* If the lower half is all zero, we build the upper half directly 1409 into the dst reg. */ 1410 if (lower32 != 0 1411 /* Need lower half if number is zero or 0xffffffff00000000. */ 1412 || (! need_hh22_p && ! need_hm10_p)) 1413 { 1414 /* No need for sethi if `or' insn can handle constant. */ 1415 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1416 /* Note that we can't use a negative constant in the `or' 1417 insn unless the upper 32 bits are all ones. */ 1418 || (lower32 < 0 && upper32 != -1) 1419 || (lower32 >= 0 && upper32 == -1)) 1420 need_hi22_p = 1; 1421 1422 if (need_hi22_p && upper32 == -1) 1423 need_xor10_p = 1; 1424 1425 /* Does bottom part (after sethi) have bits? */ 1426 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1427 /* No sethi. */ 1428 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1429 /* Need `or' if we didn't set anything else. */ 1430 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1431 need_lo10_p = 1; 1432 } 1433 else 1434 /* Output directly to dst reg if lower 32 bits are all zero. */ 1435 upper_dstreg = dstreg; 1436 } 1437 1438 if (!upper_dstreg && dstreg) 1439 as_warn (_("setx: illegal temporary register g0")); 1440 1441 if (need_hh22_p) 1442 { 1443 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1444 | ((upper32 >> 10) & 0x3fffff)); 1445 the_insn.reloc = (the_insn.exp.X_op != O_constant 1446 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1447 output_insn (insn, &the_insn); 1448 } 1449 1450 if (need_hi22_p) 1451 { 1452 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1453 | (((need_xor10_p ? ~lower32 : lower32) 1454 >> 10) & 0x3fffff)); 1455 the_insn.reloc = (the_insn.exp.X_op != O_constant 1456 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1457 output_insn (insn, &the_insn); 1458 } 1459 1460 if (need_hm10_p) 1461 { 1462 the_insn.opcode = (OR_INSN 1463 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1464 | RD (upper_dstreg) 1465 | IMMED 1466 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1467 the_insn.reloc = (the_insn.exp.X_op != O_constant 1468 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1469 output_insn (insn, &the_insn); 1470 } 1471 1472 if (need_lo10_p) 1473 { 1474 /* FIXME: One nice optimization to do here is to OR the low part 1475 with the highpart if hi22 isn't needed and the low part is 1476 positive. */ 1477 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1478 | RD (dstreg) 1479 | IMMED 1480 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1481 the_insn.reloc = (the_insn.exp.X_op != O_constant 1482 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1483 output_insn (insn, &the_insn); 1484 } 1485 1486 /* If we needed to build the upper part, shift it into place. */ 1487 if (need_hh22_p || need_hm10_p) 1488 { 1489 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1490 | IMMED | 32); 1491 the_insn.reloc = BFD_RELOC_NONE; 1492 output_insn (insn, &the_insn); 1493 } 1494 1495 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1496 if (need_xor10_p) 1497 { 1498 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1499 | 0x1c00 | (lower32 & 0x3ff)); 1500 the_insn.reloc = BFD_RELOC_NONE; 1501 output_insn (insn, &the_insn); 1502 } 1503 1504 /* If we needed to build both upper and lower parts, OR them together. */ 1505 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1506 { 1507 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1508 | RD (dstreg)); 1509 the_insn.reloc = BFD_RELOC_NONE; 1510 output_insn (insn, &the_insn); 1511 } 1512 } 1513 1514 /* Main entry point to assemble one instruction. */ 1515 1516 void 1517 md_assemble (char *str) 1518 { 1519 const struct sparc_opcode *insn; 1520 int special_case; 1521 1522 know (str); 1523 special_case = sparc_ip (str, &insn); 1524 if (insn == NULL) 1525 return; 1526 1527 /* Certain instructions may not appear on delay slots. Check for 1528 these situations. */ 1529 if (last_insn != NULL 1530 && (last_insn->flags & F_DELAYED) != 0) 1531 { 1532 /* Before SPARC V9 the effect of having a delayed branch 1533 instruction in the delay slot of a conditional delayed branch 1534 was undefined. 1535 1536 In SPARC V9 DCTI couples are well defined. 1537 1538 However, starting with the UltraSPARC Architecture 2005, DCTI 1539 couples (of all kind) are deprecated and should not be used, 1540 as they may be slow or behave differently to what the 1541 programmer expects. */ 1542 if (dcti_couples_detect 1543 && (insn->flags & F_DELAYED) != 0 1544 && ((max_architecture < SPARC_OPCODE_ARCH_V9 1545 && (last_insn->flags & F_CONDBR) != 0) 1546 || max_architecture >= SPARC_OPCODE_ARCH_V9C)) 1547 as_warn (_("unpredictable DCTI couple")); 1548 1549 1550 /* We warn about attempts to put a floating point branch in a 1551 delay slot, unless the delay slot has been annulled. */ 1552 if ((insn->flags & F_FBR) != 0 1553 /* ??? This test isn't completely accurate. We assume anything with 1554 F_{UNBR,CONDBR,FBR} set is annullable. */ 1555 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1556 || (last_opcode & ANNUL) == 0)) 1557 as_warn (_("FP branch in delay slot")); 1558 } 1559 1560 /* SPARC before v8 requires a nop instruction between a floating 1561 point instruction and a floating point branch. SPARCv8 requires 1562 a nop only immediately after FPop2 (fcmp*) instructions. 1563 We insert one automatically, with a warning. 1564 */ 1565 if (last_insn != NULL 1566 && (insn->flags & F_FBR) != 0 1567 && (last_insn->flags & F_FLOAT) != 0 1568 && (max_architecture < SPARC_OPCODE_ARCH_V8 || 1569 (max_architecture < SPARC_OPCODE_ARCH_V9 && 1570 strncmp(last_insn->name, "fcmp", 4) == 0))) 1571 { 1572 struct sparc_it nop_insn; 1573 1574 nop_insn.opcode = NOP_INSN; 1575 nop_insn.reloc = BFD_RELOC_NONE; 1576 output_insn (insn, &nop_insn); 1577 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1578 } 1579 1580 switch (special_case) 1581 { 1582 case SPECIAL_CASE_NONE: 1583 /* Normal insn. */ 1584 output_insn (insn, &the_insn); 1585 break; 1586 1587 case SPECIAL_CASE_SETSW: 1588 synthetize_setsw (insn); 1589 break; 1590 1591 case SPECIAL_CASE_SET: 1592 synthetize_setuw (insn); 1593 break; 1594 1595 case SPECIAL_CASE_SETX: 1596 synthetize_setx (insn); 1597 break; 1598 1599 case SPECIAL_CASE_FDIV: 1600 { 1601 int rd = (the_insn.opcode >> 25) & 0x1f; 1602 1603 output_insn (insn, &the_insn); 1604 1605 /* According to information leaked from Sun, the "fdiv" instructions 1606 on early SPARC machines would produce incorrect results sometimes. 1607 The workaround is to add an fmovs of the destination register to 1608 itself just after the instruction. This was true on machines 1609 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1610 gas_assert (the_insn.reloc == BFD_RELOC_NONE); 1611 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1612 output_insn (insn, &the_insn); 1613 return; 1614 } 1615 1616 default: 1617 as_fatal (_("failed special case insn sanity check")); 1618 } 1619 } 1620 1621 static const char * 1622 get_hwcap_name (bfd_uint64_t mask) 1623 { 1624 if (mask & HWCAP_MUL32) 1625 return "mul32"; 1626 if (mask & HWCAP_DIV32) 1627 return "div32"; 1628 if (mask & HWCAP_FSMULD) 1629 return "fsmuld"; 1630 if (mask & HWCAP_V8PLUS) 1631 return "v8plus"; 1632 if (mask & HWCAP_POPC) 1633 return "popc"; 1634 if (mask & HWCAP_VIS) 1635 return "vis"; 1636 if (mask & HWCAP_VIS2) 1637 return "vis2"; 1638 if (mask & HWCAP_ASI_BLK_INIT) 1639 return "ASIBlkInit"; 1640 if (mask & HWCAP_FMAF) 1641 return "fmaf"; 1642 if (mask & HWCAP_VIS3) 1643 return "vis3"; 1644 if (mask & HWCAP_HPC) 1645 return "hpc"; 1646 if (mask & HWCAP_RANDOM) 1647 return "random"; 1648 if (mask & HWCAP_TRANS) 1649 return "trans"; 1650 if (mask & HWCAP_FJFMAU) 1651 return "fjfmau"; 1652 if (mask & HWCAP_IMA) 1653 return "ima"; 1654 if (mask & HWCAP_ASI_CACHE_SPARING) 1655 return "cspare"; 1656 if (mask & HWCAP_AES) 1657 return "aes"; 1658 if (mask & HWCAP_DES) 1659 return "des"; 1660 if (mask & HWCAP_KASUMI) 1661 return "kasumi"; 1662 if (mask & HWCAP_CAMELLIA) 1663 return "camellia"; 1664 if (mask & HWCAP_MD5) 1665 return "md5"; 1666 if (mask & HWCAP_SHA1) 1667 return "sha1"; 1668 if (mask & HWCAP_SHA256) 1669 return "sha256"; 1670 if (mask & HWCAP_SHA512) 1671 return "sha512"; 1672 if (mask & HWCAP_MPMUL) 1673 return "mpmul"; 1674 if (mask & HWCAP_MONT) 1675 return "mont"; 1676 if (mask & HWCAP_PAUSE) 1677 return "pause"; 1678 if (mask & HWCAP_CBCOND) 1679 return "cbcond"; 1680 if (mask & HWCAP_CRC32C) 1681 return "crc32c"; 1682 1683 mask = mask >> 32; 1684 if (mask & HWCAP2_FJATHPLUS) 1685 return "fjathplus"; 1686 if (mask & HWCAP2_VIS3B) 1687 return "vis3b"; 1688 if (mask & HWCAP2_ADP) 1689 return "adp"; 1690 if (mask & HWCAP2_SPARC5) 1691 return "sparc5"; 1692 if (mask & HWCAP2_MWAIT) 1693 return "mwait"; 1694 if (mask & HWCAP2_XMPMUL) 1695 return "xmpmul"; 1696 if (mask & HWCAP2_XMONT) 1697 return "xmont"; 1698 if (mask & HWCAP2_NSEC) 1699 return "nsec"; 1700 if (mask & HWCAP2_SPARC6) 1701 return "sparc6"; 1702 if (mask & HWCAP2_ONADDSUB) 1703 return "onaddsub"; 1704 if (mask & HWCAP2_ONMUL) 1705 return "onmul"; 1706 if (mask & HWCAP2_ONDIV) 1707 return "ondiv"; 1708 if (mask & HWCAP2_DICTUNP) 1709 return "dictunp"; 1710 if (mask & HWCAP2_FPCMPSHL) 1711 return "fpcmpshl"; 1712 if (mask & HWCAP2_RLE) 1713 return "rle"; 1714 if (mask & HWCAP2_SHA3) 1715 return "sha3"; 1716 1717 return "UNKNOWN"; 1718 } 1719 1720 /* Subroutine of md_assemble to do the actual parsing. */ 1721 1722 static int 1723 sparc_ip (char *str, const struct sparc_opcode **pinsn) 1724 { 1725 const char *error_message = ""; 1726 char *s; 1727 const char *args; 1728 char c; 1729 const struct sparc_opcode *insn; 1730 char *argsStart; 1731 unsigned long opcode; 1732 unsigned int mask = 0; 1733 int match = 0; 1734 int comma = 0; 1735 int v9_arg_p; 1736 int special_case = SPECIAL_CASE_NONE; 1737 const sparc_asi *sasi = NULL; 1738 1739 s = str; 1740 if (ISLOWER (*s)) 1741 { 1742 do 1743 ++s; 1744 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); 1745 } 1746 1747 switch (*s) 1748 { 1749 case '\0': 1750 break; 1751 1752 case ',': 1753 comma = 1; 1754 /* Fall through. */ 1755 1756 case ' ': 1757 *s++ = '\0'; 1758 break; 1759 1760 default: 1761 as_bad (_("Unknown opcode: `%s'"), str); 1762 *pinsn = NULL; 1763 return special_case; 1764 } 1765 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1766 *pinsn = insn; 1767 if (insn == NULL) 1768 { 1769 as_bad (_("Unknown opcode: `%s'"), str); 1770 return special_case; 1771 } 1772 if (comma) 1773 { 1774 *--s = ','; 1775 } 1776 1777 argsStart = s; 1778 for (;;) 1779 { 1780 opcode = insn->match; 1781 memset (&the_insn, '\0', sizeof (the_insn)); 1782 the_insn.reloc = BFD_RELOC_NONE; 1783 v9_arg_p = 0; 1784 1785 /* Build the opcode, checking as we go to make sure that the 1786 operands match. */ 1787 for (args = insn->args;; ++args) 1788 { 1789 switch (*args) 1790 { 1791 case 'K': 1792 { 1793 int kmask = 0; 1794 1795 /* Parse a series of masks. */ 1796 if (*s == '#') 1797 { 1798 while (*s == '#') 1799 { 1800 int jmask; 1801 1802 if (! parse_keyword_arg (sparc_encode_membar, &s, 1803 &jmask)) 1804 { 1805 error_message = _(": invalid membar mask name"); 1806 goto error; 1807 } 1808 kmask |= jmask; 1809 while (*s == ' ') 1810 ++s; 1811 if (*s == '|' || *s == '+') 1812 ++s; 1813 while (*s == ' ') 1814 ++s; 1815 } 1816 } 1817 else 1818 { 1819 if (! parse_const_expr_arg (&s, &kmask)) 1820 { 1821 error_message = _(": invalid membar mask expression"); 1822 goto error; 1823 } 1824 if (kmask < 0 || kmask > 127) 1825 { 1826 error_message = _(": invalid membar mask number"); 1827 goto error; 1828 } 1829 } 1830 1831 opcode |= MEMBAR (kmask); 1832 continue; 1833 } 1834 1835 case '3': 1836 { 1837 int smask = 0; 1838 1839 if (! parse_const_expr_arg (&s, &smask)) 1840 { 1841 error_message = _(": invalid siam mode expression"); 1842 goto error; 1843 } 1844 if (smask < 0 || smask > 7) 1845 { 1846 error_message = _(": invalid siam mode number"); 1847 goto error; 1848 } 1849 opcode |= smask; 1850 continue; 1851 } 1852 1853 case '*': 1854 { 1855 int fcn = 0; 1856 1857 /* Parse a prefetch function. */ 1858 if (*s == '#') 1859 { 1860 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1861 { 1862 error_message = _(": invalid prefetch function name"); 1863 goto error; 1864 } 1865 } 1866 else 1867 { 1868 if (! parse_const_expr_arg (&s, &fcn)) 1869 { 1870 error_message = _(": invalid prefetch function expression"); 1871 goto error; 1872 } 1873 if (fcn < 0 || fcn > 31) 1874 { 1875 error_message = _(": invalid prefetch function number"); 1876 goto error; 1877 } 1878 } 1879 opcode |= RD (fcn); 1880 continue; 1881 } 1882 1883 case '!': 1884 case '?': 1885 /* Parse a sparc64 privileged register. */ 1886 if (*s == '%') 1887 { 1888 struct priv_reg_entry *p; 1889 unsigned int len = 9999999; /* Init to make gcc happy. */ 1890 1891 s += 1; 1892 for (p = priv_reg_table; p->name; p++) 1893 if (p->name[0] == s[0]) 1894 { 1895 len = strlen (p->name); 1896 if (strncmp (p->name, s, len) == 0) 1897 break; 1898 } 1899 1900 if (!p->name) 1901 { 1902 error_message = _(": unrecognizable privileged register"); 1903 goto error; 1904 } 1905 1906 if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1907 { 1908 error_message = _(": unrecognizable privileged register"); 1909 goto error; 1910 } 1911 1912 s += len; 1913 continue; 1914 } 1915 else 1916 { 1917 error_message = _(": unrecognizable privileged register"); 1918 goto error; 1919 } 1920 1921 case '$': 1922 case '%': 1923 /* Parse a sparc64 hyperprivileged register. */ 1924 if (*s == '%') 1925 { 1926 struct priv_reg_entry *p; 1927 unsigned int len = 9999999; /* Init to make gcc happy. */ 1928 1929 s += 1; 1930 for (p = hpriv_reg_table; p->name; p++) 1931 if (p->name[0] == s[0]) 1932 { 1933 len = strlen (p->name); 1934 if (strncmp (p->name, s, len) == 0) 1935 break; 1936 } 1937 1938 if (!p->name) 1939 { 1940 error_message = _(": unrecognizable hyperprivileged register"); 1941 goto error; 1942 } 1943 1944 if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1945 { 1946 error_message = _(": unrecognizable hyperprivileged register"); 1947 goto error; 1948 } 1949 1950 s += len; 1951 continue; 1952 } 1953 else 1954 { 1955 error_message = _(": unrecognizable hyperprivileged register"); 1956 goto error; 1957 } 1958 1959 case '_': 1960 case '/': 1961 /* Parse a v9a or later ancillary state register. */ 1962 if (*s == '%') 1963 { 1964 struct priv_reg_entry *p; 1965 unsigned int len = 9999999; /* Init to make gcc happy. */ 1966 1967 s += 1; 1968 for (p = v9a_asr_table; p->name; p++) 1969 if (p->name[0] == s[0]) 1970 { 1971 len = strlen (p->name); 1972 if (strncmp (p->name, s, len) == 0) 1973 break; 1974 } 1975 1976 if (!p->name) 1977 { 1978 error_message = _(": unrecognizable ancillary state register"); 1979 goto error; 1980 } 1981 1982 if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1983 { 1984 error_message = _(": unrecognizable ancillary state register"); 1985 goto error; 1986 } 1987 1988 s += len; 1989 continue; 1990 } 1991 else 1992 { 1993 error_message = _(": unrecognizable ancillary state register"); 1994 goto error; 1995 } 1996 1997 case 'M': 1998 case 'm': 1999 if (strncmp (s, "%asr", 4) == 0) 2000 { 2001 s += 4; 2002 2003 if (ISDIGIT (*s)) 2004 { 2005 long num = 0; 2006 2007 while (ISDIGIT (*s)) 2008 { 2009 num = num * 10 + *s - '0'; 2010 ++s; 2011 } 2012 2013 /* We used to check here for the asr number to 2014 be between 16 and 31 in V9 and later, as 2015 mandated by the section C.1.1 "Register 2016 Names" in the SPARC spec. However, we 2017 decided to remove this restriction as a) it 2018 introduces problems when new V9 asr registers 2019 are introduced, b) the Solaris assembler 2020 doesn't implement this restriction and c) the 2021 restriction will go away in future revisions 2022 of the Oracle SPARC Architecture. */ 2023 2024 if (num < 0 || 31 < num) 2025 { 2026 error_message = _(": asr number must be between 0 and 31"); 2027 goto error; 2028 } 2029 2030 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 2031 continue; 2032 } 2033 else 2034 { 2035 error_message = _(": expecting %asrN"); 2036 goto error; 2037 } 2038 } /* if %asr */ 2039 break; 2040 2041 case 'I': 2042 the_insn.reloc = BFD_RELOC_SPARC_11; 2043 goto immediate; 2044 2045 case 'j': 2046 the_insn.reloc = BFD_RELOC_SPARC_10; 2047 goto immediate; 2048 2049 case ')': 2050 if (*s == ' ') 2051 s++; 2052 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) 2053 || ISDIGIT (*s)) 2054 { 2055 long num = 0; 2056 2057 if (s[0] == '0' && s[1] == 'x') 2058 { 2059 s += 2; 2060 while (ISXDIGIT (*s)) 2061 { 2062 num <<= 4; 2063 num |= hex_value (*s); 2064 ++s; 2065 } 2066 } 2067 else 2068 { 2069 while (ISDIGIT (*s)) 2070 { 2071 num = num * 10 + *s - '0'; 2072 ++s; 2073 } 2074 } 2075 if (num < 0 || num > 31) 2076 { 2077 error_message = _(": crypto immediate must be between 0 and 31"); 2078 goto error; 2079 } 2080 2081 opcode |= RS3 (num); 2082 continue; 2083 } 2084 else 2085 { 2086 error_message = _(": expecting crypto immediate"); 2087 goto error; 2088 } 2089 2090 case 'X': 2091 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 2092 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2093 the_insn.reloc = BFD_RELOC_SPARC_5; 2094 else 2095 the_insn.reloc = BFD_RELOC_SPARC13; 2096 /* These fields are unsigned, but for upward compatibility, 2097 allow negative values as well. */ 2098 goto immediate; 2099 2100 case 'Y': 2101 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 2102 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2103 the_insn.reloc = BFD_RELOC_SPARC_6; 2104 else 2105 the_insn.reloc = BFD_RELOC_SPARC13; 2106 /* These fields are unsigned, but for upward compatibility, 2107 allow negative values as well. */ 2108 goto immediate; 2109 2110 case 'k': 2111 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 2112 the_insn.pcrel = 1; 2113 goto immediate; 2114 2115 case '=': 2116 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; 2117 the_insn.pcrel = 1; 2118 goto immediate; 2119 2120 case 'G': 2121 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 2122 the_insn.pcrel = 1; 2123 goto immediate; 2124 2125 case 'N': 2126 if (*s == 'p' && s[1] == 'n') 2127 { 2128 s += 2; 2129 continue; 2130 } 2131 break; 2132 2133 case 'T': 2134 if (*s == 'p' && s[1] == 't') 2135 { 2136 s += 2; 2137 continue; 2138 } 2139 break; 2140 2141 case 'z': 2142 if (*s == ' ') 2143 { 2144 ++s; 2145 } 2146 if ((strncmp (s, "%icc", 4) == 0) 2147 || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) 2148 { 2149 s += 4; 2150 continue; 2151 } 2152 break; 2153 2154 case 'Z': 2155 if (*s == ' ') 2156 { 2157 ++s; 2158 } 2159 if ((strncmp (s, "%xcc", 4) == 0) 2160 || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) 2161 { 2162 s += 4; 2163 continue; 2164 } 2165 break; 2166 2167 case '6': 2168 if (*s == ' ') 2169 { 2170 ++s; 2171 } 2172 if (strncmp (s, "%fcc0", 5) == 0) 2173 { 2174 s += 5; 2175 continue; 2176 } 2177 break; 2178 2179 case '7': 2180 if (*s == ' ') 2181 { 2182 ++s; 2183 } 2184 if (strncmp (s, "%fcc1", 5) == 0) 2185 { 2186 s += 5; 2187 continue; 2188 } 2189 break; 2190 2191 case '8': 2192 if (*s == ' ') 2193 { 2194 ++s; 2195 } 2196 if (strncmp (s, "%fcc2", 5) == 0) 2197 { 2198 s += 5; 2199 continue; 2200 } 2201 break; 2202 2203 case '9': 2204 if (*s == ' ') 2205 { 2206 ++s; 2207 } 2208 if (strncmp (s, "%fcc3", 5) == 0) 2209 { 2210 s += 5; 2211 continue; 2212 } 2213 break; 2214 2215 case 'P': 2216 if (strncmp (s, "%pc", 3) == 0) 2217 { 2218 s += 3; 2219 continue; 2220 } 2221 break; 2222 2223 case 'W': 2224 if (strncmp (s, "%tick", 5) == 0) 2225 { 2226 s += 5; 2227 continue; 2228 } 2229 break; 2230 2231 case '\0': /* End of args. */ 2232 if (s[0] == ',' && s[1] == '%') 2233 { 2234 char *s1; 2235 int npar = 0; 2236 const struct perc_entry *p; 2237 2238 for (p = perc_table; p->type != perc_entry_none; p++) 2239 if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg) 2240 && strncmp (s + 2, p->name, p->len) == 0) 2241 break; 2242 if (p->type == perc_entry_none || p->type == perc_entry_reg) 2243 break; 2244 2245 if (s[p->len + 2] != '(') 2246 { 2247 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2248 return special_case; 2249 } 2250 2251 if (! (p->pop->flags & F_POP_TLS_CALL) 2252 && the_insn.reloc != BFD_RELOC_NONE) 2253 { 2254 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 2255 p->name); 2256 return special_case; 2257 } 2258 2259 if ((p->pop->flags & F_POP_TLS_CALL) 2260 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 2261 || the_insn.exp.X_add_number != 0 2262 || the_insn.exp.X_add_symbol 2263 != symbol_find_or_make ("__tls_get_addr"))) 2264 { 2265 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 2266 p->name); 2267 return special_case; 2268 } 2269 2270 the_insn.reloc = p->pop->reloc; 2271 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2272 s += p->len + 3; 2273 2274 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2275 if (*s1 == '(') 2276 npar++; 2277 else if (*s1 == ')') 2278 { 2279 if (!npar) 2280 break; 2281 npar--; 2282 } 2283 2284 if (*s1 != ')') 2285 { 2286 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2287 return special_case; 2288 } 2289 2290 *s1 = '\0'; 2291 (void) get_expression (s); 2292 *s1 = ')'; 2293 s = s1 + 1; 2294 } 2295 if (*s == '\0') 2296 match = 1; 2297 break; 2298 2299 case '+': 2300 if (*s == '+') 2301 { 2302 ++s; 2303 continue; 2304 } 2305 if (*s == '-') 2306 { 2307 continue; 2308 } 2309 break; 2310 2311 case '[': /* These must match exactly. */ 2312 case ']': 2313 case ',': 2314 case ' ': 2315 if (*s++ == *args) 2316 continue; 2317 break; 2318 2319 case '#': /* Must be at least one digit. */ 2320 if (ISDIGIT (*s++)) 2321 { 2322 while (ISDIGIT (*s)) 2323 { 2324 ++s; 2325 } 2326 continue; 2327 } 2328 break; 2329 2330 case 'C': /* Coprocessor state register. */ 2331 if (strncmp (s, "%csr", 4) == 0) 2332 { 2333 s += 4; 2334 continue; 2335 } 2336 break; 2337 2338 case 'b': /* Next operand is a coprocessor register. */ 2339 case 'c': 2340 case 'D': 2341 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 2342 { 2343 mask = *s++; 2344 if (ISDIGIT (*s)) 2345 { 2346 mask = 10 * (mask - '0') + (*s++ - '0'); 2347 if (mask >= 32) 2348 { 2349 break; 2350 } 2351 } 2352 else 2353 { 2354 mask -= '0'; 2355 } 2356 switch (*args) 2357 { 2358 2359 case 'b': 2360 opcode |= mask << 14; 2361 continue; 2362 2363 case 'c': 2364 opcode |= mask; 2365 continue; 2366 2367 case 'D': 2368 opcode |= mask << 25; 2369 continue; 2370 } 2371 } 2372 break; 2373 2374 case 'r': /* next operand must be a register */ 2375 case 'O': 2376 case '1': 2377 case '2': 2378 case 'd': 2379 if (*s++ == '%') 2380 { 2381 switch (c = *s++) 2382 { 2383 2384 case 'f': /* frame pointer */ 2385 if (*s++ == 'p') 2386 { 2387 mask = 0x1e; 2388 break; 2389 } 2390 goto error; 2391 2392 case 'g': /* global register */ 2393 c = *s++; 2394 if (isoctal (c)) 2395 { 2396 mask = c - '0'; 2397 break; 2398 } 2399 goto error; 2400 2401 case 'i': /* in register */ 2402 c = *s++; 2403 if (isoctal (c)) 2404 { 2405 mask = c - '0' + 24; 2406 break; 2407 } 2408 goto error; 2409 2410 case 'l': /* local register */ 2411 c = *s++; 2412 if (isoctal (c)) 2413 { 2414 mask = (c - '0' + 16); 2415 break; 2416 } 2417 goto error; 2418 2419 case 'o': /* out register */ 2420 c = *s++; 2421 if (isoctal (c)) 2422 { 2423 mask = (c - '0' + 8); 2424 break; 2425 } 2426 goto error; 2427 2428 case 's': /* stack pointer */ 2429 if (*s++ == 'p') 2430 { 2431 mask = 0xe; 2432 break; 2433 } 2434 goto error; 2435 2436 case 'r': /* any register */ 2437 if (!ISDIGIT ((c = *s++))) 2438 { 2439 goto error; 2440 } 2441 /* FALLTHROUGH */ 2442 case '0': 2443 case '1': 2444 case '2': 2445 case '3': 2446 case '4': 2447 case '5': 2448 case '6': 2449 case '7': 2450 case '8': 2451 case '9': 2452 if (ISDIGIT (*s)) 2453 { 2454 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2455 { 2456 goto error; 2457 } 2458 } 2459 else 2460 { 2461 c -= '0'; 2462 } 2463 mask = c; 2464 break; 2465 2466 default: 2467 goto error; 2468 } 2469 2470 if ((mask & ~1) == 2 && sparc_arch_size == 64 2471 && no_undeclared_regs && ! globals[mask]) 2472 as_bad (_("detected global register use not covered by .register pseudo-op")); 2473 2474 /* Got the register, now figure out where 2475 it goes in the opcode. */ 2476 switch (*args) 2477 { 2478 case '1': 2479 opcode |= mask << 14; 2480 continue; 2481 2482 case '2': 2483 opcode |= mask; 2484 continue; 2485 2486 case 'd': 2487 opcode |= mask << 25; 2488 continue; 2489 2490 case 'r': 2491 opcode |= (mask << 25) | (mask << 14); 2492 continue; 2493 2494 case 'O': 2495 opcode |= (mask << 25) | (mask << 0); 2496 continue; 2497 } 2498 } 2499 break; 2500 2501 case 'e': /* next operand is a floating point register */ 2502 case 'v': 2503 case 'V': 2504 case ';': 2505 2506 case 'f': 2507 case 'B': 2508 case 'R': 2509 case ':': 2510 case '\'': 2511 2512 case '4': 2513 case '5': 2514 2515 case 'g': 2516 case 'H': 2517 case 'J': 2518 case '}': 2519 case '^': 2520 { 2521 char format; 2522 2523 if (*s++ == '%' 2524 && ((format = *s) == 'f' 2525 || format == 'd' 2526 || format == 'q') 2527 && ISDIGIT (*++s)) 2528 { 2529 for (mask = 0; ISDIGIT (*s); ++s) 2530 { 2531 mask = 10 * mask + (*s - '0'); 2532 } /* read the number */ 2533 2534 if ((*args == 'v' 2535 || *args == 'B' 2536 || *args == '5' 2537 || *args == 'H' 2538 || *args == '\'' 2539 || format == 'd') 2540 && (mask & 1)) 2541 { 2542 /* register must be even numbered */ 2543 break; 2544 } 2545 2546 if ((*args == 'V' 2547 || *args == 'R' 2548 || *args == 'J' 2549 || format == 'q') 2550 && (mask & 3)) 2551 { 2552 /* register must be multiple of 4 */ 2553 break; 2554 } 2555 2556 if ((*args == ':' 2557 || *args == ';' 2558 || *args == '^') 2559 && (mask & 7)) 2560 { 2561 /* register must be multiple of 8 */ 2562 break; 2563 } 2564 2565 if (*args == '\'' && mask < 48) 2566 { 2567 /* register must be higher or equal than %f48 */ 2568 break; 2569 } 2570 2571 if (mask >= 64) 2572 { 2573 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2574 error_message = _(": There are only 64 f registers; [0-63]"); 2575 else 2576 error_message = _(": There are only 32 f registers; [0-31]"); 2577 goto error; 2578 } /* on error */ 2579 else if (mask >= 32) 2580 { 2581 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2582 { 2583 if (*args == 'e' || *args == 'f' || *args == 'g') 2584 { 2585 error_message 2586 = _(": There are only 32 single precision f registers; [0-31]"); 2587 goto error; 2588 } 2589 v9_arg_p = 1; 2590 mask -= 31; /* wrap high bit */ 2591 } 2592 else 2593 { 2594 error_message = _(": There are only 32 f registers; [0-31]"); 2595 goto error; 2596 } 2597 } 2598 } 2599 else 2600 { 2601 break; 2602 } /* if not an 'f' register. */ 2603 2604 if (*args == '}' && mask != RS2 (opcode)) 2605 { 2606 error_message 2607 = _(": Instruction requires frs2 and frsd must be the same register"); 2608 goto error; 2609 } 2610 2611 switch (*args) 2612 { 2613 case 'v': 2614 case 'V': 2615 case 'e': 2616 case ';': 2617 opcode |= RS1 (mask); 2618 continue; 2619 2620 case 'f': 2621 case 'B': 2622 case 'R': 2623 case ':': 2624 opcode |= RS2 (mask); 2625 continue; 2626 2627 case '\'': 2628 opcode |= RS2 (mask & 0xe); 2629 continue; 2630 2631 case '4': 2632 case '5': 2633 opcode |= RS3 (mask); 2634 continue; 2635 2636 case 'g': 2637 case 'H': 2638 case 'J': 2639 case '}': 2640 case '^': 2641 opcode |= RD (mask); 2642 continue; 2643 } /* Pack it in. */ 2644 2645 know (0); 2646 break; 2647 } /* float arg */ 2648 2649 case 'F': 2650 if (strncmp (s, "%fsr", 4) == 0) 2651 { 2652 s += 4; 2653 continue; 2654 } 2655 break; 2656 2657 case '(': 2658 if (strncmp (s, "%efsr", 5) == 0) 2659 { 2660 s += 5; 2661 continue; 2662 } 2663 break; 2664 2665 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2666 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2667 goto immediate; 2668 2669 case 'l': /* 22 bit PC relative immediate */ 2670 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2671 the_insn.pcrel = 1; 2672 goto immediate; 2673 2674 case 'L': /* 30 bit immediate */ 2675 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2676 the_insn.pcrel = 1; 2677 goto immediate; 2678 2679 case 'h': 2680 case 'n': /* 22 bit immediate */ 2681 the_insn.reloc = BFD_RELOC_SPARC22; 2682 goto immediate; 2683 2684 case 'i': /* 13 bit immediate */ 2685 the_insn.reloc = BFD_RELOC_SPARC13; 2686 2687 /* fallthrough */ 2688 2689 immediate: 2690 if (*s == ' ') 2691 s++; 2692 2693 { 2694 char *s1; 2695 const char *op_arg = NULL; 2696 static expressionS op_exp; 2697 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2698 2699 /* Check for %hi, etc. */ 2700 if (*s == '%') 2701 { 2702 const struct perc_entry *p; 2703 2704 for (p = perc_table; p->type != perc_entry_none; p++) 2705 if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg) 2706 && strncmp (s + 1, p->name, p->len) == 0) 2707 break; 2708 if (p->type == perc_entry_none || p->type == perc_entry_reg) 2709 break; 2710 2711 if (s[p->len + 1] != '(') 2712 { 2713 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2714 return special_case; 2715 } 2716 2717 op_arg = p->name; 2718 the_insn.reloc = p->pop->reloc; 2719 s += p->len + 2; 2720 v9_arg_p = p->pop->flags & F_POP_V9; 2721 } 2722 2723 /* Note that if the get_expression() fails, we will still 2724 have created U entries in the symbol table for the 2725 'symbols' in the input string. Try not to create U 2726 symbols for registers, etc. */ 2727 2728 /* This stuff checks to see if the expression ends in 2729 +%reg. If it does, it removes the register from 2730 the expression, and re-sets 's' to point to the 2731 right place. */ 2732 2733 if (op_arg) 2734 { 2735 int npar = 0; 2736 2737 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2738 if (*s1 == '(') 2739 npar++; 2740 else if (*s1 == ')') 2741 { 2742 if (!npar) 2743 break; 2744 npar--; 2745 } 2746 2747 if (*s1 != ')') 2748 { 2749 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2750 return special_case; 2751 } 2752 2753 *s1 = '\0'; 2754 (void) get_expression (s); 2755 *s1 = ')'; 2756 if (expr_end != s1) 2757 { 2758 as_bad (_("Expression inside %%%s could not be parsed"), op_arg); 2759 return special_case; 2760 } 2761 s = s1 + 1; 2762 if (*s == ',' || *s == ']' || !*s) 2763 continue; 2764 if (*s != '+' && *s != '-') 2765 { 2766 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2767 return special_case; 2768 } 2769 *s1 = '0'; 2770 s = s1; 2771 op_exp = the_insn.exp; 2772 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2773 } 2774 2775 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2776 ; 2777 2778 if (s1 != s && ISDIGIT (s1[-1])) 2779 { 2780 if (s1[-2] == '%' && s1[-3] == '+') 2781 s1 -= 3; 2782 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2783 s1 -= 4; 2784 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') 2785 s1 -= 5; 2786 else 2787 s1 = NULL; 2788 if (s1) 2789 { 2790 *s1 = '\0'; 2791 if (op_arg && s1 == s + 1) 2792 the_insn.exp.X_op = O_absent; 2793 else 2794 (void) get_expression (s); 2795 *s1 = '+'; 2796 if (op_arg) 2797 *s = ')'; 2798 s = s1; 2799 } 2800 } 2801 else 2802 s1 = NULL; 2803 2804 if (!s1) 2805 { 2806 (void) get_expression (s); 2807 if (op_arg) 2808 *s = ')'; 2809 s = expr_end; 2810 } 2811 2812 if (op_arg) 2813 { 2814 the_insn.exp2 = the_insn.exp; 2815 the_insn.exp = op_exp; 2816 if (the_insn.exp2.X_op == O_absent) 2817 the_insn.exp2.X_op = O_illegal; 2818 else if (the_insn.exp.X_op == O_absent) 2819 { 2820 the_insn.exp = the_insn.exp2; 2821 the_insn.exp2.X_op = O_illegal; 2822 } 2823 else if (the_insn.exp.X_op == O_constant) 2824 { 2825 valueT val = the_insn.exp.X_add_number; 2826 switch (the_insn.reloc) 2827 { 2828 default: 2829 break; 2830 2831 case BFD_RELOC_SPARC_HH22: 2832 val = BSR (val, 32); 2833 /* Fall through. */ 2834 2835 case BFD_RELOC_SPARC_LM22: 2836 case BFD_RELOC_HI22: 2837 val = (val >> 10) & 0x3fffff; 2838 break; 2839 2840 case BFD_RELOC_SPARC_HM10: 2841 val = BSR (val, 32); 2842 /* Fall through. */ 2843 2844 case BFD_RELOC_LO10: 2845 val &= 0x3ff; 2846 break; 2847 2848 case BFD_RELOC_SPARC_H34: 2849 val >>= 12; 2850 val &= 0x3fffff; 2851 break; 2852 2853 case BFD_RELOC_SPARC_H44: 2854 val >>= 22; 2855 val &= 0x3fffff; 2856 break; 2857 2858 case BFD_RELOC_SPARC_M44: 2859 val >>= 12; 2860 val &= 0x3ff; 2861 break; 2862 2863 case BFD_RELOC_SPARC_L44: 2864 val &= 0xfff; 2865 break; 2866 2867 case BFD_RELOC_SPARC_HIX22: 2868 val = ~val; 2869 val = (val >> 10) & 0x3fffff; 2870 break; 2871 2872 case BFD_RELOC_SPARC_LOX10: 2873 val = (val & 0x3ff) | 0x1c00; 2874 break; 2875 } 2876 the_insn.exp = the_insn.exp2; 2877 the_insn.exp.X_add_number += val; 2878 the_insn.exp2.X_op = O_illegal; 2879 the_insn.reloc = old_reloc; 2880 } 2881 else if (the_insn.exp2.X_op != O_constant) 2882 { 2883 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2884 return special_case; 2885 } 2886 else 2887 { 2888 if (old_reloc != BFD_RELOC_SPARC13 2889 || the_insn.reloc != BFD_RELOC_LO10 2890 || sparc_arch_size != 64 2891 || sparc_pic_code) 2892 { 2893 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2894 return special_case; 2895 } 2896 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2897 } 2898 } 2899 } 2900 /* Check for constants that don't require emitting a reloc. */ 2901 if (the_insn.exp.X_op == O_constant 2902 && the_insn.exp.X_add_symbol == 0 2903 && the_insn.exp.X_op_symbol == 0) 2904 { 2905 /* For pc-relative call instructions, we reject 2906 constants to get better code. */ 2907 if (the_insn.pcrel 2908 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2909 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2910 { 2911 error_message = _(": PC-relative operand can't be a constant"); 2912 goto error; 2913 } 2914 2915 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2916 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2917 { 2918 error_message = _(": TLS operand can't be a constant"); 2919 goto error; 2920 } 2921 2922 /* Constants that won't fit are checked in md_apply_fix 2923 and bfd_install_relocation. 2924 ??? It would be preferable to install the constants 2925 into the insn here and save having to create a fixS 2926 for each one. There already exists code to handle 2927 all the various cases (e.g. in md_apply_fix and 2928 bfd_install_relocation) so duplicating all that code 2929 here isn't right. */ 2930 2931 /* This is a special case to handle cbcond instructions 2932 properly, which can need two relocations. The first 2933 one is for the 5-bit immediate field and the latter 2934 is going to be for the WDISP10 branch part. We 2935 handle the R_SPARC_5 immediate directly here so that 2936 we don't need to add support for multiple relocations 2937 in one instruction just yet. */ 2938 if (the_insn.reloc == BFD_RELOC_SPARC_5 2939 && ((insn->match & OP(0x3)) == 0)) 2940 { 2941 valueT val = the_insn.exp.X_add_number; 2942 2943 the_insn.reloc = BFD_RELOC_NONE; 2944 if (! in_bitfield_range (val, 0x1f)) 2945 { 2946 error_message = _(": Immediate value in cbcond is out of range."); 2947 goto error; 2948 } 2949 opcode |= val & 0x1f; 2950 } 2951 } 2952 2953 continue; 2954 2955 case 'a': 2956 if (*s++ == 'a') 2957 { 2958 opcode |= ANNUL; 2959 continue; 2960 } 2961 break; 2962 2963 case 'A': 2964 { 2965 int asi = 0; 2966 2967 /* Parse an asi. */ 2968 if (*s == '#') 2969 { 2970 if (! parse_sparc_asi (&s, &sasi)) 2971 { 2972 error_message = _(": invalid ASI name"); 2973 goto error; 2974 } 2975 asi = sasi->value; 2976 } 2977 else 2978 { 2979 if (! parse_const_expr_arg (&s, &asi)) 2980 { 2981 error_message = _(": invalid ASI expression"); 2982 goto error; 2983 } 2984 if (asi < 0 || asi > 255) 2985 { 2986 error_message = _(": invalid ASI number"); 2987 goto error; 2988 } 2989 } 2990 opcode |= ASI (asi); 2991 continue; 2992 } /* Alternate space. */ 2993 2994 case 'p': 2995 if (strncmp (s, "%psr", 4) == 0) 2996 { 2997 s += 4; 2998 continue; 2999 } 3000 break; 3001 3002 case 'q': /* Floating point queue. */ 3003 if (strncmp (s, "%fq", 3) == 0) 3004 { 3005 s += 3; 3006 continue; 3007 } 3008 break; 3009 3010 case 'Q': /* Coprocessor queue. */ 3011 if (strncmp (s, "%cq", 3) == 0) 3012 { 3013 s += 3; 3014 continue; 3015 } 3016 break; 3017 3018 case 'S': 3019 if (strcmp (str, "set") == 0 3020 || strcmp (str, "setuw") == 0) 3021 { 3022 special_case = SPECIAL_CASE_SET; 3023 continue; 3024 } 3025 else if (strcmp (str, "setsw") == 0) 3026 { 3027 special_case = SPECIAL_CASE_SETSW; 3028 continue; 3029 } 3030 else if (strcmp (str, "setx") == 0) 3031 { 3032 special_case = SPECIAL_CASE_SETX; 3033 continue; 3034 } 3035 else if (strncmp (str, "fdiv", 4) == 0) 3036 { 3037 special_case = SPECIAL_CASE_FDIV; 3038 continue; 3039 } 3040 break; 3041 3042 case 'o': 3043 if (strncmp (s, "%asi", 4) != 0) 3044 break; 3045 s += 4; 3046 continue; 3047 3048 case 's': 3049 if (strncmp (s, "%fprs", 5) != 0) 3050 break; 3051 s += 5; 3052 continue; 3053 3054 case '{': 3055 if (strncmp (s, "%mcdper",7) != 0) 3056 break; 3057 s += 7; 3058 continue; 3059 3060 case '&': 3061 if (strncmp (s, "%entropy", 8) != 0) 3062 break; 3063 s += 8; 3064 continue; 3065 3066 case 'E': 3067 if (strncmp (s, "%ccr", 4) != 0) 3068 break; 3069 s += 4; 3070 continue; 3071 3072 case 't': 3073 if (strncmp (s, "%tbr", 4) != 0) 3074 break; 3075 s += 4; 3076 continue; 3077 3078 case 'w': 3079 if (strncmp (s, "%wim", 4) != 0) 3080 break; 3081 s += 4; 3082 continue; 3083 3084 case '|': 3085 { 3086 int imm2 = 0; 3087 3088 /* Parse a 2-bit immediate. */ 3089 if (! parse_const_expr_arg (&s, &imm2)) 3090 { 3091 error_message = _(": non-immdiate imm2 operand"); 3092 goto error; 3093 } 3094 if ((imm2 & ~0x3) != 0) 3095 { 3096 error_message = _(": imm2 immediate operand out of range (0-3)"); 3097 goto error; 3098 } 3099 3100 opcode |= ((imm2 & 0x2) << 3) | (imm2 & 0x1); 3101 continue; 3102 } 3103 3104 case 'x': 3105 { 3106 char *push = input_line_pointer; 3107 expressionS e; 3108 3109 input_line_pointer = s; 3110 expression (&e); 3111 if (e.X_op == O_constant) 3112 { 3113 int n = e.X_add_number; 3114 if (n != e.X_add_number || (n & ~0x1ff) != 0) 3115 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 3116 else 3117 opcode |= e.X_add_number << 5; 3118 } 3119 else 3120 as_bad (_("non-immediate OPF operand, ignored")); 3121 s = input_line_pointer; 3122 input_line_pointer = push; 3123 continue; 3124 } 3125 3126 case 'y': 3127 if (strncmp (s, "%y", 2) != 0) 3128 break; 3129 s += 2; 3130 continue; 3131 3132 case 'u': 3133 case 'U': 3134 { 3135 /* Parse a sparclet cpreg. */ 3136 int cpreg; 3137 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 3138 { 3139 error_message = _(": invalid cpreg name"); 3140 goto error; 3141 } 3142 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 3143 continue; 3144 } 3145 3146 default: 3147 as_fatal (_("failed sanity check.")); 3148 } /* switch on arg code. */ 3149 3150 /* Break out of for() loop. */ 3151 break; 3152 } /* For each arg that we expect. */ 3153 3154 error: 3155 if (match == 0) 3156 { 3157 /* Args don't match. */ 3158 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 3159 && (insn->name == insn[1].name 3160 || !strcmp (insn->name, insn[1].name))) 3161 { 3162 ++insn; 3163 s = argsStart; 3164 continue; 3165 } 3166 else 3167 { 3168 as_bad (_("Illegal operands%s"), error_message); 3169 return special_case; 3170 } 3171 } 3172 else 3173 { 3174 /* We have a match. Now see if the architecture is OK. */ 3175 /* String to use in case of architecture warning. */ 3176 const char *msg_str = str; 3177 int needed_arch_mask = insn->architecture; 3178 3179 /* Include the ASI architecture needed as well */ 3180 if (sasi && needed_arch_mask > sasi->architecture) 3181 { 3182 needed_arch_mask = sasi->architecture; 3183 msg_str = sasi->name; 3184 } 3185 3186 bfd_uint64_t hwcaps 3187 = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; 3188 3189 #ifndef TE_SOLARIS 3190 if (hwcaps) 3191 hwcap_seen |= hwcaps; 3192 #endif 3193 if (v9_arg_p) 3194 { 3195 needed_arch_mask &= 3196 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 3197 if (! needed_arch_mask) 3198 needed_arch_mask = 3199 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 3200 } 3201 3202 if (needed_arch_mask 3203 & SPARC_OPCODE_SUPPORTED (current_architecture)) 3204 /* OK. */ 3205 ; 3206 /* Can we bump up the architecture? */ 3207 else if (needed_arch_mask 3208 & SPARC_OPCODE_SUPPORTED (max_architecture)) 3209 { 3210 enum sparc_opcode_arch_val needed_architecture = 3211 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 3212 & needed_arch_mask); 3213 3214 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 3215 if (warn_on_bump 3216 && needed_architecture > warn_after_architecture) 3217 { 3218 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 3219 sparc_opcode_archs[current_architecture].name, 3220 sparc_opcode_archs[needed_architecture].name, 3221 msg_str); 3222 warn_after_architecture = needed_architecture; 3223 } 3224 current_architecture = needed_architecture; 3225 hwcap_allowed 3226 = (hwcap_allowed 3227 | hwcaps 3228 | (((bfd_uint64_t) sparc_opcode_archs[current_architecture].hwcaps2) << 32) 3229 | sparc_opcode_archs[current_architecture].hwcaps); 3230 } 3231 /* Conflict. */ 3232 /* ??? This seems to be a bit fragile. What if the next entry in 3233 the opcode table is the one we want and it is supported? 3234 It is possible to arrange the table today so that this can't 3235 happen but what about tomorrow? */ 3236 else 3237 { 3238 int arch, printed_one_p = 0; 3239 char *p; 3240 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 3241 3242 /* Create a list of the architectures that support the insn. */ 3243 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 3244 p = required_archs; 3245 arch = sparc_ffs (needed_arch_mask); 3246 while ((1 << arch) <= needed_arch_mask) 3247 { 3248 if ((1 << arch) & needed_arch_mask) 3249 { 3250 if (printed_one_p) 3251 *p++ = '|'; 3252 strcpy (p, sparc_opcode_archs[arch].name); 3253 p += strlen (p); 3254 printed_one_p = 1; 3255 } 3256 ++arch; 3257 } 3258 3259 as_bad (_("Architecture mismatch on \"%s %s\"."), str, argsStart); 3260 as_tsktsk (_("(Requires %s; requested architecture is %s.)"), 3261 required_archs, 3262 sparc_opcode_archs[max_architecture].name); 3263 return special_case; 3264 } 3265 3266 /* Make sure the hwcaps used by the instruction are 3267 currently enabled. */ 3268 if (hwcaps & ~hwcap_allowed) 3269 { 3270 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); 3271 3272 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), 3273 hwcap_name, str); 3274 return special_case; 3275 } 3276 } /* If no match. */ 3277 3278 break; 3279 } /* Forever looking for a match. */ 3280 3281 the_insn.opcode = opcode; 3282 return special_case; 3283 } 3284 3285 static char * 3286 skip_over_keyword (char *q) 3287 { 3288 for (q = q + (*q == '#' || *q == '%'); 3289 ISALNUM (*q) || *q == '_'; 3290 ++q) 3291 continue; 3292 return q; 3293 } 3294 3295 static int 3296 parse_sparc_asi (char **input_pointer_p, const sparc_asi **value_p) 3297 { 3298 const sparc_asi *value; 3299 char c, *p, *q; 3300 3301 p = *input_pointer_p; 3302 q = skip_over_keyword(p); 3303 c = *q; 3304 *q = 0; 3305 value = sparc_encode_asi (p); 3306 *q = c; 3307 if (value == NULL) 3308 return 0; 3309 *value_p = value; 3310 *input_pointer_p = q; 3311 return 1; 3312 } 3313 3314 /* Parse an argument that can be expressed as a keyword. 3315 (eg: #StoreStore or %ccfr). 3316 The result is a boolean indicating success. 3317 If successful, INPUT_POINTER is updated. */ 3318 3319 static int 3320 parse_keyword_arg (int (*lookup_fn) (const char *), 3321 char **input_pointerP, 3322 int *valueP) 3323 { 3324 int value; 3325 char c, *p, *q; 3326 3327 p = *input_pointerP; 3328 q = skip_over_keyword(p); 3329 c = *q; 3330 *q = 0; 3331 value = (*lookup_fn) (p); 3332 *q = c; 3333 if (value == -1) 3334 return 0; 3335 *valueP = value; 3336 *input_pointerP = q; 3337 return 1; 3338 } 3339 3340 /* Parse an argument that is a constant expression. 3341 The result is a boolean indicating success. */ 3342 3343 static int 3344 parse_const_expr_arg (char **input_pointerP, int *valueP) 3345 { 3346 char *save = input_line_pointer; 3347 expressionS exp; 3348 3349 input_line_pointer = *input_pointerP; 3350 /* The next expression may be something other than a constant 3351 (say if we're not processing the right variant of the insn). 3352 Don't call expression unless we're sure it will succeed as it will 3353 signal an error (which we want to defer until later). */ 3354 /* FIXME: It might be better to define md_operand and have it recognize 3355 things like %asi, etc. but continuing that route through to the end 3356 is a lot of work. */ 3357 if (*input_line_pointer == '%') 3358 { 3359 input_line_pointer = save; 3360 return 0; 3361 } 3362 expression (&exp); 3363 *input_pointerP = input_line_pointer; 3364 input_line_pointer = save; 3365 if (exp.X_op != O_constant) 3366 return 0; 3367 *valueP = exp.X_add_number; 3368 return 1; 3369 } 3370 3371 /* Subroutine of sparc_ip to parse an expression. */ 3372 3373 static int 3374 get_expression (char *str) 3375 { 3376 char *save_in; 3377 segT seg; 3378 3379 save_in = input_line_pointer; 3380 input_line_pointer = str; 3381 seg = expression (&the_insn.exp); 3382 if (seg != absolute_section 3383 && seg != text_section 3384 && seg != data_section 3385 && seg != bss_section 3386 && seg != undefined_section) 3387 { 3388 the_insn.error = _("bad segment"); 3389 expr_end = input_line_pointer; 3390 input_line_pointer = save_in; 3391 return 1; 3392 } 3393 expr_end = input_line_pointer; 3394 input_line_pointer = save_in; 3395 return 0; 3396 } 3397 3398 /* Subroutine of md_assemble to output one insn. */ 3399 3400 static void 3401 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) 3402 { 3403 char *toP = frag_more (4); 3404 3405 /* Put out the opcode. */ 3406 if (INSN_BIG_ENDIAN) 3407 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); 3408 else 3409 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); 3410 3411 /* Put out the symbol-dependent stuff. */ 3412 if (theinsn->reloc != BFD_RELOC_NONE) 3413 { 3414 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 3415 (toP - frag_now->fr_literal), /* Where. */ 3416 4, /* Size. */ 3417 &theinsn->exp, 3418 theinsn->pcrel, 3419 theinsn->reloc); 3420 /* Turn off overflow checking in fixup_segment. We'll do our 3421 own overflow checking in md_apply_fix. This is necessary because 3422 the insn size is 4 and fixup_segment will signal an overflow for 3423 large 8 byte quantities. */ 3424 fixP->fx_no_overflow = 1; 3425 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) 3426 fixP->tc_fix_data = theinsn->exp2.X_add_number; 3427 } 3428 3429 last_insn = insn; 3430 last_opcode = theinsn->opcode; 3431 3432 dwarf2_emit_insn (4); 3433 } 3434 3435 const char * 3436 md_atof (int type, char *litP, int *sizeP) 3437 { 3438 return ieee_md_atof (type, litP, sizeP, target_big_endian); 3439 } 3440 3441 /* Write a value out to the object file, using the appropriate 3442 endianness. */ 3443 3444 void 3445 md_number_to_chars (char *buf, valueT val, int n) 3446 { 3447 if (target_big_endian) 3448 number_to_chars_bigendian (buf, val, n); 3449 else if (target_little_endian_data 3450 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3451 /* Output debug words, which are not in allocated sections, as big 3452 endian. */ 3453 number_to_chars_bigendian (buf, val, n); 3454 else if (target_little_endian_data || ! target_big_endian) 3455 number_to_chars_littleendian (buf, val, n); 3456 } 3457 3458 /* Apply a fixS to the frags, now that we know the value it ought to 3459 hold. */ 3460 3461 void 3462 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) 3463 { 3464 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3465 offsetT val = * (offsetT *) valP; 3466 long insn; 3467 3468 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3469 3470 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3471 3472 /* SPARC ELF relocations don't use an addend in the data field. */ 3473 if (fixP->fx_addsy != NULL) 3474 { 3475 switch (fixP->fx_r_type) 3476 { 3477 case BFD_RELOC_SPARC_TLS_GD_HI22: 3478 case BFD_RELOC_SPARC_TLS_GD_LO10: 3479 case BFD_RELOC_SPARC_TLS_GD_ADD: 3480 case BFD_RELOC_SPARC_TLS_GD_CALL: 3481 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3482 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3483 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3484 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3485 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3486 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3487 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3488 case BFD_RELOC_SPARC_TLS_IE_HI22: 3489 case BFD_RELOC_SPARC_TLS_IE_LO10: 3490 case BFD_RELOC_SPARC_TLS_IE_LD: 3491 case BFD_RELOC_SPARC_TLS_IE_LDX: 3492 case BFD_RELOC_SPARC_TLS_IE_ADD: 3493 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3494 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3495 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3496 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3497 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3498 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3499 case BFD_RELOC_SPARC_TLS_TPOFF32: 3500 case BFD_RELOC_SPARC_TLS_TPOFF64: 3501 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3502 3503 default: 3504 break; 3505 } 3506 3507 return; 3508 } 3509 3510 /* This is a hack. There should be a better way to 3511 handle this. Probably in terms of howto fields, once 3512 we can look at these fixups in terms of howtos. */ 3513 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3514 val += fixP->fx_where + fixP->fx_frag->fr_address; 3515 3516 /* If this is a data relocation, just output VAL. */ 3517 3518 if (fixP->fx_r_type == BFD_RELOC_8) 3519 { 3520 md_number_to_chars (buf, val, 1); 3521 } 3522 else if (fixP->fx_r_type == BFD_RELOC_16 3523 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3524 { 3525 md_number_to_chars (buf, val, 2); 3526 } 3527 else if (fixP->fx_r_type == BFD_RELOC_32 3528 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3529 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3530 { 3531 md_number_to_chars (buf, val, 4); 3532 } 3533 else if (fixP->fx_r_type == BFD_RELOC_64 3534 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3535 { 3536 md_number_to_chars (buf, val, 8); 3537 } 3538 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3539 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3540 { 3541 fixP->fx_done = 0; 3542 return; 3543 } 3544 else 3545 { 3546 /* It's a relocation against an instruction. */ 3547 3548 if (INSN_BIG_ENDIAN) 3549 insn = bfd_getb32 ((unsigned char *) buf); 3550 else 3551 insn = bfd_getl32 ((unsigned char *) buf); 3552 3553 switch (fixP->fx_r_type) 3554 { 3555 case BFD_RELOC_32_PCREL_S2: 3556 val = val >> 2; 3557 /* FIXME: This increment-by-one deserves a comment of why it's 3558 being done! */ 3559 if (! sparc_pic_code 3560 || fixP->fx_addsy == NULL 3561 || symbol_section_p (fixP->fx_addsy)) 3562 ++val; 3563 3564 insn |= val & 0x3fffffff; 3565 3566 /* See if we have a delay slot. In that case we attempt to 3567 optimize several cases transforming CALL instructions 3568 into branches. But we can only do that if the relocation 3569 can be completely resolved here, i.e. if no undefined 3570 symbol is associated with it. */ 3571 if (sparc_relax && fixP->fx_addsy == NULL 3572 && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3573 { 3574 #define G0 0 3575 #define O7 15 3576 #define XCC (2 << 20) 3577 #define COND(x) (((x)&0xf)<<25) 3578 #define CONDA COND(0x8) 3579 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3580 #define INSN_BA (F2(0,2) | CONDA) 3581 #define INSN_OR F3(2, 0x2, 0) 3582 #define INSN_NOP F2(0,4) 3583 3584 long delay; 3585 3586 /* If the instruction is a call with either: 3587 restore 3588 arithmetic instruction with rd == %o7 3589 where rs1 != %o7 and rs2 if it is register != %o7 3590 then we can optimize if the call destination is near 3591 by changing the call into a branch always. */ 3592 if (INSN_BIG_ENDIAN) 3593 delay = bfd_getb32 ((unsigned char *) buf + 4); 3594 else 3595 delay = bfd_getl32 ((unsigned char *) buf + 4); 3596 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3597 break; 3598 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3599 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3600 || ((delay & RD (~0)) != RD (O7)))) 3601 break; 3602 if ((delay & RS1 (~0)) == RS1 (O7) 3603 || ((delay & F3I (~0)) == 0 3604 && (delay & RS2 (~0)) == RS2 (O7))) 3605 break; 3606 /* Ensure the branch will fit into simm22. */ 3607 if ((val & 0x3fe00000) 3608 && (val & 0x3fe00000) != 0x3fe00000) 3609 break; 3610 /* Check if the arch is v9 and branch will fit 3611 into simm19. */ 3612 if (((val & 0x3c0000) == 0 3613 || (val & 0x3c0000) == 0x3c0000) 3614 && (sparc_arch_size == 64 3615 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3616 /* ba,pt %xcc */ 3617 insn = INSN_BPA | (val & 0x7ffff); 3618 else 3619 /* ba */ 3620 insn = INSN_BA | (val & 0x3fffff); 3621 if (fixP->fx_where >= 4 3622 && ((delay & (0xffffffff ^ RS1 (~0))) 3623 == (INSN_OR | RD (O7) | RS2 (G0)))) 3624 { 3625 long setter; 3626 int reg; 3627 3628 if (INSN_BIG_ENDIAN) 3629 setter = bfd_getb32 ((unsigned char *) buf - 4); 3630 else 3631 setter = bfd_getl32 ((unsigned char *) buf - 4); 3632 if ((setter & (0xffffffff ^ RD (~0))) 3633 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3634 break; 3635 /* The sequence was 3636 or %o7, %g0, %rN 3637 call foo 3638 or %rN, %g0, %o7 3639 3640 If call foo was replaced with ba, replace 3641 or %rN, %g0, %o7 with nop. */ 3642 reg = (delay & RS1 (~0)) >> 14; 3643 if (reg != ((setter & RD (~0)) >> 25) 3644 || reg == G0 || reg == O7) 3645 break; 3646 3647 if (INSN_BIG_ENDIAN) 3648 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3649 else 3650 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3651 } 3652 } 3653 break; 3654 3655 case BFD_RELOC_SPARC_11: 3656 if (! in_signed_range (val, 0x7ff)) 3657 as_bad_where (fixP->fx_file, fixP->fx_line, 3658 _("relocation overflow")); 3659 insn |= val & 0x7ff; 3660 break; 3661 3662 case BFD_RELOC_SPARC_10: 3663 if (! in_signed_range (val, 0x3ff)) 3664 as_bad_where (fixP->fx_file, fixP->fx_line, 3665 _("relocation overflow")); 3666 insn |= val & 0x3ff; 3667 break; 3668 3669 case BFD_RELOC_SPARC_7: 3670 if (! in_bitfield_range (val, 0x7f)) 3671 as_bad_where (fixP->fx_file, fixP->fx_line, 3672 _("relocation overflow")); 3673 insn |= val & 0x7f; 3674 break; 3675 3676 case BFD_RELOC_SPARC_6: 3677 if (! in_bitfield_range (val, 0x3f)) 3678 as_bad_where (fixP->fx_file, fixP->fx_line, 3679 _("relocation overflow")); 3680 insn |= val & 0x3f; 3681 break; 3682 3683 case BFD_RELOC_SPARC_5: 3684 if (! in_bitfield_range (val, 0x1f)) 3685 as_bad_where (fixP->fx_file, fixP->fx_line, 3686 _("relocation overflow")); 3687 insn |= val & 0x1f; 3688 break; 3689 3690 case BFD_RELOC_SPARC_WDISP10: 3691 if ((val & 3) 3692 || val >= 0x007fc 3693 || val <= -(offsetT) 0x808) 3694 as_bad_where (fixP->fx_file, fixP->fx_line, 3695 _("relocation overflow")); 3696 /* FIXME: The +1 deserves a comment. */ 3697 val = (val >> 2) + 1; 3698 insn |= ((val & 0x300) << 11) 3699 | ((val & 0xff) << 5); 3700 break; 3701 3702 case BFD_RELOC_SPARC_WDISP16: 3703 if ((val & 3) 3704 || val >= 0x1fffc 3705 || val <= -(offsetT) 0x20008) 3706 as_bad_where (fixP->fx_file, fixP->fx_line, 3707 _("relocation overflow")); 3708 /* FIXME: The +1 deserves a comment. */ 3709 val = (val >> 2) + 1; 3710 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3711 break; 3712 3713 case BFD_RELOC_SPARC_WDISP19: 3714 if ((val & 3) 3715 || val >= 0xffffc 3716 || val <= -(offsetT) 0x100008) 3717 as_bad_where (fixP->fx_file, fixP->fx_line, 3718 _("relocation overflow")); 3719 /* FIXME: The +1 deserves a comment. */ 3720 val = (val >> 2) + 1; 3721 insn |= val & 0x7ffff; 3722 break; 3723 3724 case BFD_RELOC_SPARC_HH22: 3725 val = BSR (val, 32); 3726 /* Fall through. */ 3727 3728 case BFD_RELOC_SPARC_LM22: 3729 case BFD_RELOC_HI22: 3730 if (!fixP->fx_addsy) 3731 insn |= (val >> 10) & 0x3fffff; 3732 else 3733 /* FIXME: Need comment explaining why we do this. */ 3734 insn &= ~0xffff; 3735 break; 3736 3737 case BFD_RELOC_SPARC22: 3738 if (val & ~0x003fffff) 3739 as_bad_where (fixP->fx_file, fixP->fx_line, 3740 _("relocation overflow")); 3741 insn |= (val & 0x3fffff); 3742 break; 3743 3744 case BFD_RELOC_SPARC_HM10: 3745 val = BSR (val, 32); 3746 /* Fall through. */ 3747 3748 case BFD_RELOC_LO10: 3749 if (!fixP->fx_addsy) 3750 insn |= val & 0x3ff; 3751 else 3752 /* FIXME: Need comment explaining why we do this. */ 3753 insn &= ~0xff; 3754 break; 3755 3756 case BFD_RELOC_SPARC_OLO10: 3757 val &= 0x3ff; 3758 val += fixP->tc_fix_data; 3759 /* Fall through. */ 3760 3761 case BFD_RELOC_SPARC13: 3762 if (! in_signed_range (val, 0x1fff)) 3763 as_bad_where (fixP->fx_file, fixP->fx_line, 3764 _("relocation overflow")); 3765 insn |= val & 0x1fff; 3766 break; 3767 3768 case BFD_RELOC_SPARC_WDISP22: 3769 val = (val >> 2) + 1; 3770 /* Fall through. */ 3771 case BFD_RELOC_SPARC_BASE22: 3772 insn |= val & 0x3fffff; 3773 break; 3774 3775 case BFD_RELOC_SPARC_H34: 3776 if (!fixP->fx_addsy) 3777 { 3778 bfd_vma tval = val; 3779 tval >>= 12; 3780 insn |= tval & 0x3fffff; 3781 } 3782 break; 3783 3784 case BFD_RELOC_SPARC_H44: 3785 if (!fixP->fx_addsy) 3786 { 3787 bfd_vma tval = val; 3788 tval >>= 22; 3789 insn |= tval & 0x3fffff; 3790 } 3791 break; 3792 3793 case BFD_RELOC_SPARC_M44: 3794 if (!fixP->fx_addsy) 3795 insn |= (val >> 12) & 0x3ff; 3796 break; 3797 3798 case BFD_RELOC_SPARC_L44: 3799 if (!fixP->fx_addsy) 3800 insn |= val & 0xfff; 3801 break; 3802 3803 case BFD_RELOC_SPARC_HIX22: 3804 if (!fixP->fx_addsy) 3805 { 3806 val ^= ~(offsetT) 0; 3807 insn |= (val >> 10) & 0x3fffff; 3808 } 3809 break; 3810 3811 case BFD_RELOC_SPARC_LOX10: 3812 if (!fixP->fx_addsy) 3813 insn |= 0x1c00 | (val & 0x3ff); 3814 break; 3815 3816 case BFD_RELOC_NONE: 3817 default: 3818 as_bad_where (fixP->fx_file, fixP->fx_line, 3819 _("bad or unhandled relocation type: 0x%02x"), 3820 fixP->fx_r_type); 3821 break; 3822 } 3823 3824 if (INSN_BIG_ENDIAN) 3825 bfd_putb32 (insn, (unsigned char *) buf); 3826 else 3827 bfd_putl32 (insn, (unsigned char *) buf); 3828 } 3829 3830 /* Are we finished with this relocation now? */ 3831 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3832 fixP->fx_done = 1; 3833 } 3834 3835 /* Translate internal representation of relocation info to BFD target 3836 format. */ 3837 3838 arelent ** 3839 tc_gen_reloc (asection *section, fixS *fixp) 3840 { 3841 static arelent *relocs[3]; 3842 arelent *reloc; 3843 bfd_reloc_code_real_type code; 3844 3845 relocs[0] = reloc = XNEW (arelent); 3846 relocs[1] = NULL; 3847 3848 reloc->sym_ptr_ptr = XNEW (asymbol *); 3849 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3850 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3851 3852 switch (fixp->fx_r_type) 3853 { 3854 case BFD_RELOC_8: 3855 case BFD_RELOC_16: 3856 case BFD_RELOC_32: 3857 case BFD_RELOC_64: 3858 if (fixp->fx_pcrel) 3859 { 3860 switch (fixp->fx_size) 3861 { 3862 default: 3863 as_bad_where (fixp->fx_file, fixp->fx_line, 3864 _("can not do %d byte pc-relative relocation"), 3865 fixp->fx_size); 3866 code = fixp->fx_r_type; 3867 fixp->fx_pcrel = 0; 3868 break; 3869 case 1: code = BFD_RELOC_8_PCREL; break; 3870 case 2: code = BFD_RELOC_16_PCREL; break; 3871 case 4: code = BFD_RELOC_32_PCREL; break; 3872 #ifdef BFD64 3873 case 8: code = BFD_RELOC_64_PCREL; break; 3874 #endif 3875 } 3876 if (fixp->fx_pcrel) 3877 fixp->fx_addnumber = fixp->fx_offset; 3878 break; 3879 } 3880 /* Fall through. */ 3881 case BFD_RELOC_HI22: 3882 case BFD_RELOC_LO10: 3883 case BFD_RELOC_32_PCREL_S2: 3884 case BFD_RELOC_SPARC13: 3885 case BFD_RELOC_SPARC22: 3886 case BFD_RELOC_SPARC_PC22: 3887 case BFD_RELOC_SPARC_PC10: 3888 case BFD_RELOC_SPARC_BASE13: 3889 case BFD_RELOC_SPARC_WDISP10: 3890 case BFD_RELOC_SPARC_WDISP16: 3891 case BFD_RELOC_SPARC_WDISP19: 3892 case BFD_RELOC_SPARC_WDISP22: 3893 case BFD_RELOC_SPARC_5: 3894 case BFD_RELOC_SPARC_6: 3895 case BFD_RELOC_SPARC_7: 3896 case BFD_RELOC_SPARC_10: 3897 case BFD_RELOC_SPARC_11: 3898 case BFD_RELOC_SPARC_HH22: 3899 case BFD_RELOC_SPARC_HM10: 3900 case BFD_RELOC_SPARC_LM22: 3901 case BFD_RELOC_SPARC_PC_HH22: 3902 case BFD_RELOC_SPARC_PC_HM10: 3903 case BFD_RELOC_SPARC_PC_LM22: 3904 case BFD_RELOC_SPARC_H34: 3905 case BFD_RELOC_SPARC_H44: 3906 case BFD_RELOC_SPARC_M44: 3907 case BFD_RELOC_SPARC_L44: 3908 case BFD_RELOC_SPARC_HIX22: 3909 case BFD_RELOC_SPARC_LOX10: 3910 case BFD_RELOC_SPARC_REV32: 3911 case BFD_RELOC_SPARC_OLO10: 3912 case BFD_RELOC_SPARC_UA16: 3913 case BFD_RELOC_SPARC_UA32: 3914 case BFD_RELOC_SPARC_UA64: 3915 case BFD_RELOC_8_PCREL: 3916 case BFD_RELOC_16_PCREL: 3917 case BFD_RELOC_32_PCREL: 3918 case BFD_RELOC_64_PCREL: 3919 case BFD_RELOC_SPARC_PLT32: 3920 case BFD_RELOC_SPARC_PLT64: 3921 case BFD_RELOC_VTABLE_ENTRY: 3922 case BFD_RELOC_VTABLE_INHERIT: 3923 case BFD_RELOC_SPARC_TLS_GD_HI22: 3924 case BFD_RELOC_SPARC_TLS_GD_LO10: 3925 case BFD_RELOC_SPARC_TLS_GD_ADD: 3926 case BFD_RELOC_SPARC_TLS_GD_CALL: 3927 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3928 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3929 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3930 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3931 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3932 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3933 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3934 case BFD_RELOC_SPARC_TLS_IE_HI22: 3935 case BFD_RELOC_SPARC_TLS_IE_LO10: 3936 case BFD_RELOC_SPARC_TLS_IE_LD: 3937 case BFD_RELOC_SPARC_TLS_IE_LDX: 3938 case BFD_RELOC_SPARC_TLS_IE_ADD: 3939 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3940 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3941 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3942 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3943 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: 3944 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: 3945 case BFD_RELOC_SPARC_GOTDATA_OP: 3946 code = fixp->fx_r_type; 3947 break; 3948 default: 3949 abort (); 3950 return NULL; 3951 } 3952 3953 /* If we are generating PIC code, we need to generate a different 3954 set of relocs. */ 3955 3956 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3957 #ifdef TE_VXWORKS 3958 #define GOTT_BASE "__GOTT_BASE__" 3959 #define GOTT_INDEX "__GOTT_INDEX__" 3960 #endif 3961 3962 /* This code must be parallel to tc_fix_adjustable. */ 3963 3964 if (sparc_pic_code) 3965 { 3966 switch (code) 3967 { 3968 case BFD_RELOC_32_PCREL_S2: 3969 if (generic_force_reloc (fixp)) 3970 code = BFD_RELOC_SPARC_WPLT30; 3971 break; 3972 case BFD_RELOC_HI22: 3973 code = BFD_RELOC_SPARC_GOT22; 3974 if (fixp->fx_addsy != NULL) 3975 { 3976 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3977 code = BFD_RELOC_SPARC_PC22; 3978 #ifdef TE_VXWORKS 3979 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3980 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3981 code = BFD_RELOC_HI22; /* Unchanged. */ 3982 #endif 3983 } 3984 break; 3985 case BFD_RELOC_LO10: 3986 code = BFD_RELOC_SPARC_GOT10; 3987 if (fixp->fx_addsy != NULL) 3988 { 3989 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3990 code = BFD_RELOC_SPARC_PC10; 3991 #ifdef TE_VXWORKS 3992 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3993 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3994 code = BFD_RELOC_LO10; /* Unchanged. */ 3995 #endif 3996 } 3997 break; 3998 case BFD_RELOC_SPARC13: 3999 code = BFD_RELOC_SPARC_GOT13; 4000 break; 4001 default: 4002 break; 4003 } 4004 } 4005 4006 /* Nothing is aligned in DWARF debugging sections. */ 4007 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) 4008 switch (code) 4009 { 4010 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; 4011 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; 4012 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; 4013 default: break; 4014 } 4015 4016 if (code == BFD_RELOC_SPARC_OLO10) 4017 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 4018 else 4019 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 4020 if (reloc->howto == 0) 4021 { 4022 as_bad_where (fixp->fx_file, fixp->fx_line, 4023 _("internal error: can't export reloc type %d (`%s')"), 4024 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 4025 xfree (reloc); 4026 relocs[0] = NULL; 4027 return relocs; 4028 } 4029 4030 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 4031 if (code != BFD_RELOC_32_PCREL_S2 4032 && code != BFD_RELOC_SPARC_WDISP22 4033 && code != BFD_RELOC_SPARC_WDISP16 4034 && code != BFD_RELOC_SPARC_WDISP19 4035 && code != BFD_RELOC_SPARC_WDISP10 4036 && code != BFD_RELOC_SPARC_WPLT30 4037 && code != BFD_RELOC_SPARC_TLS_GD_CALL 4038 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 4039 reloc->addend = fixp->fx_addnumber; 4040 else if (symbol_section_p (fixp->fx_addsy)) 4041 reloc->addend = (section->vma 4042 + fixp->fx_addnumber 4043 + md_pcrel_from (fixp)); 4044 else 4045 reloc->addend = fixp->fx_offset; 4046 4047 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 4048 on the same location. */ 4049 if (code == BFD_RELOC_SPARC_OLO10) 4050 { 4051 relocs[1] = reloc = XNEW (arelent); 4052 relocs[2] = NULL; 4053 4054 reloc->sym_ptr_ptr = XNEW (asymbol *); 4055 *reloc->sym_ptr_ptr 4056 = symbol_get_bfdsym (section_symbol (absolute_section)); 4057 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 4058 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 4059 reloc->addend = fixp->tc_fix_data; 4060 } 4061 4062 return relocs; 4063 } 4064 4065 /* We have no need to default values of symbols. */ 4066 4067 symbolS * 4068 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 4069 { 4070 return 0; 4071 } 4072 4073 /* Round up a section size to the appropriate boundary. */ 4074 4075 valueT 4076 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 4077 { 4078 return size; 4079 } 4080 4081 /* Exactly what point is a PC-relative offset relative TO? 4082 On the sparc, they're relative to the address of the offset, plus 4083 its size. This gets us to the following instruction. 4084 (??? Is this right? FIXME-SOON) */ 4085 long 4086 md_pcrel_from (fixS *fixP) 4087 { 4088 long ret; 4089 4090 ret = fixP->fx_where + fixP->fx_frag->fr_address; 4091 if (! sparc_pic_code 4092 || fixP->fx_addsy == NULL 4093 || symbol_section_p (fixP->fx_addsy)) 4094 ret += fixP->fx_size; 4095 return ret; 4096 } 4097 4098 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 4099 of two. */ 4100 4101 static int 4102 mylog2 (int value) 4103 { 4104 int shift; 4105 4106 if (value <= 0) 4107 return -1; 4108 4109 for (shift = 0; (value & 1) == 0; value >>= 1) 4110 ++shift; 4111 4112 return (value == 1) ? shift : -1; 4113 } 4114 4115 /* Sort of like s_lcomm. */ 4116 4117 static void 4118 s_reserve (int ignore ATTRIBUTE_UNUSED) 4119 { 4120 char *name; 4121 char *p; 4122 char c; 4123 int align; 4124 int size; 4125 int temp; 4126 symbolS *symbolP; 4127 4128 c = get_symbol_name (&name); 4129 p = input_line_pointer; 4130 *p = c; 4131 SKIP_WHITESPACE_AFTER_NAME (); 4132 4133 if (*input_line_pointer != ',') 4134 { 4135 as_bad (_("Expected comma after name")); 4136 ignore_rest_of_line (); 4137 return; 4138 } 4139 4140 ++input_line_pointer; 4141 4142 if ((size = get_absolute_expression ()) < 0) 4143 { 4144 as_bad (_("BSS length (%d.) <0! Ignored."), size); 4145 ignore_rest_of_line (); 4146 return; 4147 } /* Bad length. */ 4148 4149 *p = 0; 4150 symbolP = symbol_find_or_make (name); 4151 *p = c; 4152 4153 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 4154 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 4155 { 4156 as_bad (_("bad .reserve segment -- expected BSS segment")); 4157 return; 4158 } 4159 4160 if (input_line_pointer[2] == '.') 4161 input_line_pointer += 7; 4162 else 4163 input_line_pointer += 6; 4164 SKIP_WHITESPACE (); 4165 4166 if (*input_line_pointer == ',') 4167 { 4168 ++input_line_pointer; 4169 4170 SKIP_WHITESPACE (); 4171 if (*input_line_pointer == '\n') 4172 { 4173 as_bad (_("missing alignment")); 4174 ignore_rest_of_line (); 4175 return; 4176 } 4177 4178 align = (int) get_absolute_expression (); 4179 4180 if (align < 0) 4181 { 4182 as_bad (_("negative alignment")); 4183 ignore_rest_of_line (); 4184 return; 4185 } 4186 4187 if (align != 0) 4188 { 4189 temp = mylog2 (align); 4190 if (temp < 0) 4191 { 4192 as_bad (_("alignment not a power of 2")); 4193 ignore_rest_of_line (); 4194 return; 4195 } 4196 4197 align = temp; 4198 } 4199 4200 record_alignment (bss_section, align); 4201 } 4202 else 4203 align = 0; 4204 4205 if (!S_IS_DEFINED (symbolP)) 4206 { 4207 if (! need_pass_2) 4208 { 4209 char *pfrag; 4210 segT current_seg = now_seg; 4211 subsegT current_subseg = now_subseg; 4212 4213 /* Switch to bss. */ 4214 subseg_set (bss_section, 1); 4215 4216 if (align) 4217 /* Do alignment. */ 4218 frag_align (align, 0, 0); 4219 4220 /* Detach from old frag. */ 4221 if (S_GET_SEGMENT (symbolP) == bss_section) 4222 symbol_get_frag (symbolP)->fr_symbol = NULL; 4223 4224 symbol_set_frag (symbolP, frag_now); 4225 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4226 (offsetT) size, (char *) 0); 4227 *pfrag = 0; 4228 4229 S_SET_SEGMENT (symbolP, bss_section); 4230 4231 subseg_set (current_seg, current_subseg); 4232 4233 S_SET_SIZE (symbolP, size); 4234 } 4235 } 4236 else 4237 { 4238 as_warn (_("Ignoring attempt to re-define symbol %s"), 4239 S_GET_NAME (symbolP)); 4240 } 4241 4242 demand_empty_rest_of_line (); 4243 } 4244 4245 static void 4246 s_common (int ignore ATTRIBUTE_UNUSED) 4247 { 4248 char *name; 4249 char c; 4250 char *p; 4251 offsetT temp, size; 4252 symbolS *symbolP; 4253 4254 c = get_symbol_name (&name); 4255 /* Just after name is now '\0'. */ 4256 p = input_line_pointer; 4257 *p = c; 4258 SKIP_WHITESPACE_AFTER_NAME (); 4259 if (*input_line_pointer != ',') 4260 { 4261 as_bad (_("Expected comma after symbol-name")); 4262 ignore_rest_of_line (); 4263 return; 4264 } 4265 4266 /* Skip ','. */ 4267 input_line_pointer++; 4268 4269 if ((temp = get_absolute_expression ()) < 0) 4270 { 4271 as_bad (_(".COMMon length (%lu) out of range ignored"), 4272 (unsigned long) temp); 4273 ignore_rest_of_line (); 4274 return; 4275 } 4276 size = temp; 4277 *p = 0; 4278 symbolP = symbol_find_or_make (name); 4279 *p = c; 4280 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 4281 { 4282 as_bad (_("Ignoring attempt to re-define symbol")); 4283 ignore_rest_of_line (); 4284 return; 4285 } 4286 if (S_GET_VALUE (symbolP) != 0) 4287 { 4288 if (S_GET_VALUE (symbolP) != (valueT) size) 4289 { 4290 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 4291 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 4292 } 4293 } 4294 know (symbol_get_frag (symbolP) == &zero_address_frag); 4295 if (*input_line_pointer != ',') 4296 { 4297 as_bad (_("Expected comma after common length")); 4298 ignore_rest_of_line (); 4299 return; 4300 } 4301 input_line_pointer++; 4302 SKIP_WHITESPACE (); 4303 if (*input_line_pointer != '"') 4304 { 4305 temp = get_absolute_expression (); 4306 4307 if (temp < 0) 4308 { 4309 as_bad (_("negative alignment")); 4310 ignore_rest_of_line (); 4311 return; 4312 } 4313 4314 if (symbol_get_obj (symbolP)->local) 4315 { 4316 segT old_sec; 4317 int old_subsec; 4318 int align; 4319 4320 old_sec = now_seg; 4321 old_subsec = now_subseg; 4322 4323 if (temp == 0) 4324 align = 0; 4325 else 4326 align = mylog2 (temp); 4327 4328 if (align < 0) 4329 { 4330 as_bad (_("alignment not a power of 2")); 4331 ignore_rest_of_line (); 4332 return; 4333 } 4334 4335 record_alignment (bss_section, align); 4336 subseg_set (bss_section, 0); 4337 if (align) 4338 frag_align (align, 0, 0); 4339 if (S_GET_SEGMENT (symbolP) == bss_section) 4340 symbol_get_frag (symbolP)->fr_symbol = 0; 4341 symbol_set_frag (symbolP, frag_now); 4342 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4343 (offsetT) size, (char *) 0); 4344 *p = 0; 4345 S_SET_SEGMENT (symbolP, bss_section); 4346 S_CLEAR_EXTERNAL (symbolP); 4347 S_SET_SIZE (symbolP, size); 4348 subseg_set (old_sec, old_subsec); 4349 } 4350 else 4351 { 4352 allocate_common: 4353 S_SET_VALUE (symbolP, (valueT) size); 4354 S_SET_ALIGN (symbolP, temp); 4355 S_SET_SIZE (symbolP, size); 4356 S_SET_EXTERNAL (symbolP); 4357 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 4358 } 4359 } 4360 else 4361 { 4362 input_line_pointer++; 4363 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4364 if (*input_line_pointer == '.') 4365 input_line_pointer++; 4366 /* @@ Some say data, some say bss. */ 4367 if (strncmp (input_line_pointer, "bss\"", 4) 4368 && strncmp (input_line_pointer, "data\"", 5)) 4369 { 4370 while (*--input_line_pointer != '"') 4371 ; 4372 input_line_pointer--; 4373 goto bad_common_segment; 4374 } 4375 while (*input_line_pointer++ != '"') 4376 ; 4377 goto allocate_common; 4378 } 4379 4380 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4381 4382 demand_empty_rest_of_line (); 4383 return; 4384 4385 { 4386 bad_common_segment: 4387 p = input_line_pointer; 4388 while (*p && *p != '\n') 4389 p++; 4390 c = *p; 4391 *p = '\0'; 4392 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4393 *p = c; 4394 input_line_pointer = p; 4395 ignore_rest_of_line (); 4396 return; 4397 } 4398 } 4399 4400 /* Handle the .empty pseudo-op. This suppresses the warnings about 4401 invalid delay slot usage. */ 4402 4403 static void 4404 s_empty (int ignore ATTRIBUTE_UNUSED) 4405 { 4406 /* The easy way to implement is to just forget about the last 4407 instruction. */ 4408 last_insn = NULL; 4409 } 4410 4411 static void 4412 s_seg (int ignore ATTRIBUTE_UNUSED) 4413 { 4414 4415 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4416 { 4417 input_line_pointer += 6; 4418 s_text (0); 4419 return; 4420 } 4421 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4422 { 4423 input_line_pointer += 6; 4424 s_data (0); 4425 return; 4426 } 4427 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4428 { 4429 input_line_pointer += 7; 4430 s_data1 (); 4431 return; 4432 } 4433 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4434 { 4435 input_line_pointer += 5; 4436 /* We only support 2 segments -- text and data -- for now, so 4437 things in the "bss segment" will have to go into data for now. 4438 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4439 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4440 return; 4441 } 4442 as_bad (_("Unknown segment type")); 4443 demand_empty_rest_of_line (); 4444 } 4445 4446 static void 4447 s_data1 (void) 4448 { 4449 subseg_set (data_section, 1); 4450 demand_empty_rest_of_line (); 4451 } 4452 4453 static void 4454 s_proc (int ignore ATTRIBUTE_UNUSED) 4455 { 4456 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4457 { 4458 ++input_line_pointer; 4459 } 4460 ++input_line_pointer; 4461 } 4462 4463 /* This static variable is set by s_uacons to tell sparc_cons_align 4464 that the expression does not need to be aligned. */ 4465 4466 static int sparc_no_align_cons = 0; 4467 4468 /* This handles the unaligned space allocation pseudo-ops, such as 4469 .uaword. .uaword is just like .word, but the value does not need 4470 to be aligned. */ 4471 4472 static void 4473 s_uacons (int bytes) 4474 { 4475 /* Tell sparc_cons_align not to align this value. */ 4476 sparc_no_align_cons = 1; 4477 cons (bytes); 4478 sparc_no_align_cons = 0; 4479 } 4480 4481 /* This handles the native word allocation pseudo-op .nword. 4482 For sparc_arch_size 32 it is equivalent to .word, for 4483 sparc_arch_size 64 it is equivalent to .xword. */ 4484 4485 static void 4486 s_ncons (int bytes ATTRIBUTE_UNUSED) 4487 { 4488 cons (sparc_arch_size == 32 ? 4 : 8); 4489 } 4490 4491 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4492 global register. 4493 The syntax is: 4494 4495 .register %g[2367],{#scratch|symbolname|#ignore} 4496 */ 4497 4498 static void 4499 s_register (int ignore ATTRIBUTE_UNUSED) 4500 { 4501 char c; 4502 int reg; 4503 int flags; 4504 char *regname; 4505 4506 if (input_line_pointer[0] != '%' 4507 || input_line_pointer[1] != 'g' 4508 || ((input_line_pointer[2] & ~1) != '2' 4509 && (input_line_pointer[2] & ~1) != '6') 4510 || input_line_pointer[3] != ',') 4511 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4512 reg = input_line_pointer[2] - '0'; 4513 input_line_pointer += 4; 4514 4515 if (*input_line_pointer == '#') 4516 { 4517 ++input_line_pointer; 4518 c = get_symbol_name (®name); 4519 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4520 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4521 if (regname[0] == 'i') 4522 regname = NULL; 4523 else 4524 regname = (char *) ""; 4525 } 4526 else 4527 { 4528 c = get_symbol_name (®name); 4529 } 4530 4531 if (sparc_arch_size == 64) 4532 { 4533 if (globals[reg]) 4534 { 4535 if ((regname && globals[reg] != (symbolS *) 1 4536 && strcmp (S_GET_NAME (globals[reg]), regname)) 4537 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4538 as_bad (_("redefinition of global register")); 4539 } 4540 else 4541 { 4542 if (regname == NULL) 4543 globals[reg] = (symbolS *) 1; 4544 else 4545 { 4546 if (*regname) 4547 { 4548 if (symbol_find (regname)) 4549 as_bad (_("Register symbol %s already defined."), 4550 regname); 4551 } 4552 globals[reg] = symbol_make (regname); 4553 flags = symbol_get_bfdsym (globals[reg])->flags; 4554 if (! *regname) 4555 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4556 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4557 flags |= BSF_GLOBAL; 4558 symbol_get_bfdsym (globals[reg])->flags = flags; 4559 S_SET_VALUE (globals[reg], (valueT) reg); 4560 S_SET_ALIGN (globals[reg], reg); 4561 S_SET_SIZE (globals[reg], 0); 4562 /* Although we actually want undefined_section here, 4563 we have to use absolute_section, because otherwise 4564 generic as code will make it a COM section. 4565 We fix this up in sparc_adjust_symtab. */ 4566 S_SET_SEGMENT (globals[reg], absolute_section); 4567 S_SET_OTHER (globals[reg], 0); 4568 elf_symbol (symbol_get_bfdsym (globals[reg])) 4569 ->internal_elf_sym.st_info = 4570 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4571 elf_symbol (symbol_get_bfdsym (globals[reg])) 4572 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4573 } 4574 } 4575 } 4576 4577 (void) restore_line_pointer (c); 4578 4579 demand_empty_rest_of_line (); 4580 } 4581 4582 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4583 symbols which need it. */ 4584 4585 void 4586 sparc_adjust_symtab (void) 4587 { 4588 symbolS *sym; 4589 4590 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4591 { 4592 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4593 ->internal_elf_sym.st_info) != STT_REGISTER) 4594 continue; 4595 4596 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4597 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4598 continue; 4599 4600 S_SET_SEGMENT (sym, undefined_section); 4601 } 4602 } 4603 4604 /* If the --enforce-aligned-data option is used, we require .word, 4605 et. al., to be aligned correctly. We do it by setting up an 4606 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4607 no unexpected alignment was introduced. 4608 4609 The SunOS and Solaris native assemblers enforce aligned data by 4610 default. We don't want to do that, because gcc can deliberately 4611 generate misaligned data if the packed attribute is used. Instead, 4612 we permit misaligned data by default, and permit the user to set an 4613 option to check for it. */ 4614 4615 void 4616 sparc_cons_align (int nbytes) 4617 { 4618 int nalign; 4619 4620 /* Only do this if we are enforcing aligned data. */ 4621 if (! enforce_aligned_data) 4622 return; 4623 4624 /* Don't align if this is an unaligned pseudo-op. */ 4625 if (sparc_no_align_cons) 4626 return; 4627 4628 nalign = mylog2 (nbytes); 4629 if (nalign == 0) 4630 return; 4631 4632 gas_assert (nalign > 0); 4633 4634 if (now_seg == absolute_section) 4635 { 4636 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4637 as_bad (_("misaligned data")); 4638 return; 4639 } 4640 4641 frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4642 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4643 4644 record_alignment (now_seg, nalign); 4645 } 4646 4647 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4648 4649 void 4650 sparc_handle_align (fragS *fragp) 4651 { 4652 int count, fix; 4653 char *p; 4654 4655 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4656 4657 switch (fragp->fr_type) 4658 { 4659 case rs_align_test: 4660 if (count != 0) 4661 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4662 break; 4663 4664 case rs_align_code: 4665 p = fragp->fr_literal + fragp->fr_fix; 4666 fix = 0; 4667 4668 if (count & 3) 4669 { 4670 fix = count & 3; 4671 memset (p, 0, fix); 4672 p += fix; 4673 count -= fix; 4674 } 4675 4676 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4677 { 4678 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4679 if (INSN_BIG_ENDIAN) 4680 number_to_chars_bigendian (p, wval, 4); 4681 else 4682 number_to_chars_littleendian (p, wval, 4); 4683 p += 4; 4684 count -= 4; 4685 fix += 4; 4686 } 4687 4688 if (INSN_BIG_ENDIAN) 4689 number_to_chars_bigendian (p, 0x01000000, 4); 4690 else 4691 number_to_chars_littleendian (p, 0x01000000, 4); 4692 4693 fragp->fr_fix += fix; 4694 fragp->fr_var = 4; 4695 break; 4696 4697 default: 4698 break; 4699 } 4700 } 4701 4702 /* Some special processing for a Sparc ELF file. */ 4703 4704 void 4705 sparc_elf_final_processing (void) 4706 { 4707 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4708 sort of BFD interface for this. */ 4709 if (sparc_arch_size == 64) 4710 { 4711 switch (sparc_memory_model) 4712 { 4713 case MM_RMO: 4714 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4715 break; 4716 case MM_PSO: 4717 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4718 break; 4719 default: 4720 break; 4721 } 4722 } 4723 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4724 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4725 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4726 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4727 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4728 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4729 } 4730 4731 const char * 4732 sparc_cons (expressionS *exp, int size) 4733 { 4734 char *save; 4735 const char *sparc_cons_special_reloc = NULL; 4736 4737 SKIP_WHITESPACE (); 4738 save = input_line_pointer; 4739 if (input_line_pointer[0] == '%' 4740 && input_line_pointer[1] == 'r' 4741 && input_line_pointer[2] == '_') 4742 { 4743 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4744 { 4745 input_line_pointer += 7; 4746 sparc_cons_special_reloc = "disp"; 4747 } 4748 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4749 { 4750 if (size != 4 && size != 8) 4751 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4752 else 4753 { 4754 input_line_pointer += 6; 4755 sparc_cons_special_reloc = "plt"; 4756 } 4757 } 4758 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4759 { 4760 if (size != 4 && size != 8) 4761 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4762 else 4763 { 4764 input_line_pointer += 13; 4765 sparc_cons_special_reloc = "tls_dtpoff"; 4766 } 4767 } 4768 if (sparc_cons_special_reloc) 4769 { 4770 int bad = 0; 4771 4772 switch (size) 4773 { 4774 case 1: 4775 if (*input_line_pointer != '8') 4776 bad = 1; 4777 input_line_pointer--; 4778 break; 4779 case 2: 4780 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4781 bad = 1; 4782 break; 4783 case 4: 4784 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4785 bad = 1; 4786 break; 4787 case 8: 4788 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4789 bad = 1; 4790 break; 4791 default: 4792 bad = 1; 4793 break; 4794 } 4795 4796 if (bad) 4797 { 4798 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4799 sparc_cons_special_reloc, size * 8, size); 4800 } 4801 else 4802 { 4803 input_line_pointer += 2; 4804 if (*input_line_pointer != '(') 4805 { 4806 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4807 sparc_cons_special_reloc, size * 8); 4808 bad = 1; 4809 } 4810 } 4811 4812 if (bad) 4813 { 4814 input_line_pointer = save; 4815 sparc_cons_special_reloc = NULL; 4816 } 4817 else 4818 { 4819 int c; 4820 char *end = ++input_line_pointer; 4821 int npar = 0; 4822 4823 while (! is_end_of_line[(c = *end)]) 4824 { 4825 if (c == '(') 4826 npar++; 4827 else if (c == ')') 4828 { 4829 if (!npar) 4830 break; 4831 npar--; 4832 } 4833 end++; 4834 } 4835 4836 if (c != ')') 4837 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4838 sparc_cons_special_reloc, size * 8); 4839 else 4840 { 4841 *end = '\0'; 4842 expression (exp); 4843 *end = c; 4844 if (input_line_pointer != end) 4845 { 4846 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4847 sparc_cons_special_reloc, size * 8); 4848 } 4849 else 4850 { 4851 input_line_pointer++; 4852 SKIP_WHITESPACE (); 4853 c = *input_line_pointer; 4854 if (! is_end_of_line[c] && c != ',') 4855 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4856 sparc_cons_special_reloc, size * 8); 4857 } 4858 } 4859 } 4860 } 4861 } 4862 if (sparc_cons_special_reloc == NULL) 4863 expression (exp); 4864 return sparc_cons_special_reloc; 4865 } 4866 4867 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4868 reloc for a cons. We could use the definition there, except that 4869 we want to handle little endian relocs specially. */ 4870 4871 void 4872 cons_fix_new_sparc (fragS *frag, 4873 int where, 4874 unsigned int nbytes, 4875 expressionS *exp, 4876 const char *sparc_cons_special_reloc) 4877 { 4878 bfd_reloc_code_real_type r; 4879 4880 r = (nbytes == 1 ? BFD_RELOC_8 : 4881 (nbytes == 2 ? BFD_RELOC_16 : 4882 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4883 4884 if (target_little_endian_data 4885 && nbytes == 4 4886 && now_seg->flags & SEC_ALLOC) 4887 r = BFD_RELOC_SPARC_REV32; 4888 4889 #ifdef TE_SOLARIS 4890 /* The Solaris linker does not allow R_SPARC_UA64 4891 relocations for 32-bit executables. */ 4892 if (!target_little_endian_data 4893 && sparc_arch_size != 64 4894 && r == BFD_RELOC_64) 4895 r = BFD_RELOC_32; 4896 #endif 4897 4898 if (sparc_cons_special_reloc) 4899 { 4900 if (*sparc_cons_special_reloc == 'd') 4901 switch (nbytes) 4902 { 4903 case 1: r = BFD_RELOC_8_PCREL; break; 4904 case 2: r = BFD_RELOC_16_PCREL; break; 4905 case 4: r = BFD_RELOC_32_PCREL; break; 4906 case 8: r = BFD_RELOC_64_PCREL; break; 4907 default: abort (); 4908 } 4909 else if (*sparc_cons_special_reloc == 'p') 4910 switch (nbytes) 4911 { 4912 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4913 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4914 } 4915 else 4916 switch (nbytes) 4917 { 4918 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4919 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4920 } 4921 } 4922 else if (sparc_no_align_cons 4923 || /* PR 20803 - relocs in the .eh_frame section 4924 need to support unaligned access. */ 4925 strcmp (now_seg->name, ".eh_frame") == 0) 4926 { 4927 switch (nbytes) 4928 { 4929 case 2: r = BFD_RELOC_SPARC_UA16; break; 4930 case 4: r = BFD_RELOC_SPARC_UA32; break; 4931 #ifdef TE_SOLARIS 4932 /* The Solaris linker does not allow R_SPARC_UA64 4933 relocations for 32-bit executables. */ 4934 case 8: r = sparc_arch_size == 64 ? 4935 BFD_RELOC_SPARC_UA64 : BFD_RELOC_SPARC_UA32; break; 4936 #else 4937 case 8: r = BFD_RELOC_SPARC_UA64; break; 4938 #endif 4939 default: abort (); 4940 } 4941 } 4942 4943 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4944 } 4945 4946 void 4947 sparc_cfi_frame_initial_instructions (void) 4948 { 4949 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4950 } 4951 4952 int 4953 sparc_regname_to_dw2regnum (char *regname) 4954 { 4955 char *q; 4956 int i; 4957 4958 if (!regname[0]) 4959 return -1; 4960 4961 switch (regname[0]) 4962 { 4963 case 'g': i = 0; break; 4964 case 'o': i = 1; break; 4965 case 'l': i = 2; break; 4966 case 'i': i = 3; break; 4967 default: i = -1; break; 4968 } 4969 if (i != -1) 4970 { 4971 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4972 return -1; 4973 return i * 8 + regname[1] - '0'; 4974 } 4975 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4976 return 14; 4977 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4978 return 30; 4979 if (regname[0] == 'f' || regname[0] == 'r') 4980 { 4981 unsigned int regnum; 4982 4983 regnum = strtoul (regname + 1, &q, 10); 4984 if (q == NULL || *q) 4985 return -1; 4986 if (regnum >= ((regname[0] == 'f' 4987 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4988 ? 64 : 32)) 4989 return -1; 4990 if (regname[0] == 'f') 4991 { 4992 regnum += 32; 4993 if (regnum >= 64 && (regnum & 1)) 4994 return -1; 4995 } 4996 return regnum; 4997 } 4998 return -1; 4999 } 5000 5001 void 5002 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 5003 { 5004 sparc_no_align_cons = 1; 5005 emit_expr_with_reloc (exp, nbytes, "disp"); 5006 sparc_no_align_cons = 0; 5007 } 5008