1 /* tc-m68k.c -- Assemble for the m68k family 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23 #include "as.h" 24 #include "safe-ctype.h" 25 #include "obstack.h" 26 #include "subsegs.h" 27 #include "dwarf2dbg.h" 28 #include "dw2gencfi.h" 29 30 #include "opcode/m68k.h" 31 #include "m68k-parse.h" 32 33 #if defined (OBJ_ELF) 34 #include "elf/m68k.h" 35 #endif 36 37 #ifdef M68KCOFF 38 #include "obj-coff.h" 39 #endif 40 41 #ifdef OBJ_ELF 42 static void m68k_elf_cons (int); 43 #endif 44 45 /* This string holds the chars that always start a comment. If the 46 pre-processor is disabled, these aren't very useful. The macro 47 tc_comment_chars points to this. We use this, rather than the 48 usual comment_chars, so that the --bitwise-or option will work. */ 49 #if defined (TE_SVR4) || defined (TE_DELTA) 50 const char *m68k_comment_chars = "|#"; 51 #else 52 const char *m68k_comment_chars = "|"; 53 #endif 54 55 /* This array holds the chars that only start a comment at the beginning of 56 a line. If the line seems to have the form '# 123 filename' 57 .line and .file directives will appear in the pre-processed output */ 58 /* Note that input_file.c hand checks for '#' at the beginning of the 59 first line of the input file. This is because the compiler outputs 60 #NO_APP at the beginning of its output. */ 61 /* Also note that comments like this one will always work. */ 62 const char line_comment_chars[] = "#*"; 63 64 const char line_separator_chars[] = ";"; 65 66 /* Chars that can be used to separate mant from exp in floating point nums. */ 67 const char EXP_CHARS[] = "eE"; 68 69 /* Chars that mean this number is a floating point constant, as 70 in "0f12.456" or "0d1.2345e12". */ 71 72 const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; 73 74 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 75 changed in read.c . Ideally it shouldn't have to know about it at all, 76 but nothing is ideal around here. */ 77 78 /* Are we trying to generate PIC code? If so, absolute references 79 ought to be made into linkage table references or pc-relative 80 references. Not implemented. For ELF there are other means 81 to denote pic relocations. */ 82 int flag_want_pic; 83 84 static int flag_short_refs; /* -l option. */ 85 static int flag_long_jumps; /* -S option. */ 86 static int flag_keep_pcrel; /* --pcrel option. */ 87 88 #ifdef REGISTER_PREFIX_OPTIONAL 89 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 90 #else 91 int flag_reg_prefix_optional; 92 #endif 93 94 /* Whether --register-prefix-optional was used on the command line. */ 95 static int reg_prefix_optional_seen; 96 97 /* The floating point coprocessor to use by default. */ 98 static enum m68k_register m68k_float_copnum = COP1; 99 100 /* If this is non-zero, then references to number(%pc) will be taken 101 to refer to number, rather than to %pc + number. */ 102 static int m68k_abspcadd; 103 104 /* If this is non-zero, then the quick forms of the move, add, and sub 105 instructions are used when possible. */ 106 static int m68k_quick = 1; 107 108 /* If this is non-zero, then if the size is not specified for a base 109 or outer displacement, the assembler assumes that the size should 110 be 32 bits. */ 111 static int m68k_rel32 = 1; 112 113 /* This is non-zero if m68k_rel32 was set from the command line. */ 114 static int m68k_rel32_from_cmdline; 115 116 /* The default width to use for an index register when using a base 117 displacement. */ 118 static enum m68k_size m68k_index_width_default = SIZE_LONG; 119 120 /* We want to warn if any text labels are misaligned. In order to get 121 the right line number, we need to record the line number for each 122 label. */ 123 struct label_line 124 { 125 struct label_line *next; 126 symbolS *label; 127 char *file; 128 unsigned int line; 129 int text; 130 }; 131 132 /* The list of labels. */ 133 134 static struct label_line *labels; 135 136 /* The current label. */ 137 138 static struct label_line *current_label; 139 140 /* Pointer to list holding the opcodes sorted by name. */ 141 static struct m68k_opcode const ** m68k_sorted_opcodes; 142 143 /* Its an arbitrary name: This means I don't approve of it. 144 See flames below. */ 145 static struct obstack robyn; 146 147 struct m68k_incant 148 { 149 const char *m_operands; 150 unsigned long m_opcode; 151 short m_opnum; 152 short m_codenum; 153 int m_arch; 154 struct m68k_incant *m_next; 155 }; 156 157 #define getone(x) ((((x)->m_opcode)>>16)&0xffff) 158 #define gettwo(x) (((x)->m_opcode)&0xffff) 159 160 static const enum m68k_register m68000_ctrl[] = { 0 }; 161 static const enum m68k_register m68010_ctrl[] = { 162 SFC, DFC, USP, VBR, 163 0 164 }; 165 static const enum m68k_register m68020_ctrl[] = { 166 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP, 167 0 168 }; 169 static const enum m68k_register m68040_ctrl[] = { 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, 171 USP, VBR, MSP, ISP, MMUSR, URP, SRP, 172 0 173 }; 174 static const enum m68k_register m68060_ctrl[] = { 175 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, 176 USP, VBR, URP, SRP, PCR, 177 0 178 }; 179 static const enum m68k_register mcf_ctrl[] = { 180 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, 181 RAMBAR0, RAMBAR1, RAMBAR, MBAR, 182 0 183 }; 184 static const enum m68k_register mcf51_ctrl[] = { 185 VBR, CPUCR, 186 0 187 }; 188 static const enum m68k_register mcf5206_ctrl[] = { 189 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR, 190 0 191 }; 192 static const enum m68k_register mcf5208_ctrl[] = { 193 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1, 194 0 195 }; 196 static const enum m68k_register mcf5210a_ctrl[] = { 197 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR, 198 0 199 }; 200 static const enum m68k_register mcf5213_ctrl[] = { 201 VBR, RAMBAR, RAMBAR1, FLASHBAR, 202 0 203 }; 204 static const enum m68k_register mcf5216_ctrl[] = { 205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 206 0 207 }; 208 static const enum m68k_register mcf5221x_ctrl[] = { 209 VBR, FLASHBAR, RAMBAR, RAMBAR1, 210 0 211 }; 212 static const enum m68k_register mcf52223_ctrl[] = { 213 VBR, FLASHBAR, RAMBAR, RAMBAR1, 214 0 215 }; 216 static const enum m68k_register mcf52235_ctrl[] = { 217 VBR, FLASHBAR, RAMBAR, RAMBAR1, 218 0 219 }; 220 static const enum m68k_register mcf5225_ctrl[] = { 221 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1, 222 0 223 }; 224 static const enum m68k_register mcf52259_ctrl[] = { 225 VBR, FLASHBAR, RAMBAR, RAMBAR1, 226 0 227 }; 228 static const enum m68k_register mcf52277_ctrl[] = { 229 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 230 0 231 }; 232 static const enum m68k_register mcf5235_ctrl[] = { 233 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 234 0 235 }; 236 static const enum m68k_register mcf5249_ctrl[] = { 237 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 238 0 239 }; 240 static const enum m68k_register mcf5250_ctrl[] = { 241 VBR, 242 0 243 }; 244 static const enum m68k_register mcf5253_ctrl[] = { 245 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2, 246 0 247 }; 248 static const enum m68k_register mcf5271_ctrl[] = { 249 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 250 0 251 }; 252 static const enum m68k_register mcf5272_ctrl[] = { 253 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR, 254 0 255 }; 256 static const enum m68k_register mcf5275_ctrl[] = { 257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 258 0 259 }; 260 static const enum m68k_register mcf5282_ctrl[] = { 261 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1, 262 0 263 }; 264 static const enum m68k_register mcf53017_ctrl[] = { 265 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 266 0 267 }; 268 static const enum m68k_register mcf5307_ctrl[] = { 269 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR, 270 0 271 }; 272 static const enum m68k_register mcf5329_ctrl[] = { 273 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 274 0 275 }; 276 static const enum m68k_register mcf5373_ctrl[] = { 277 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1, 278 0 279 }; 280 static const enum m68k_register mcfv4e_ctrl[] = { 281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 282 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1, 283 MBAR, SECMBAR, 284 MPCR /* Multiprocessor Control register */, 285 EDRAMBAR /* Embedded DRAM Base Address Register */, 286 /* Permutation control registers. */ 287 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, 288 PCR3U0, PCR3L0, PCR3U1, PCR3L1, 289 /* Legacy names */ 290 TC /* ASID */, BUSCR /* MMUBAR */, 291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 292 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */, 293 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */, 294 0 295 }; 296 static const enum m68k_register mcf5407_ctrl[] = { 297 CACR, ASID, ACR0, ACR1, ACR2, ACR3, 298 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 299 /* Legacy names */ 300 TC /* ASID */, 301 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 302 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 303 0 304 }; 305 static const enum m68k_register mcf54418_ctrl[] = { 306 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR, 307 VBR, PC, RAMBAR1, 308 /* Legacy names */ 309 TC /* ASID */, BUSCR /* MMUBAR */, 310 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 311 RAMBAR /* RAMBAR1 */, 312 0 313 }; 314 static const enum m68k_register mcf54455_ctrl[] = { 315 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 316 VBR, PC, RAMBAR1, 317 /* Legacy names */ 318 TC /* ASID */, BUSCR /* MMUBAR */, 319 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 320 RAMBAR /* RAMBAR1 */, 321 0 322 }; 323 static const enum m68k_register mcf5475_ctrl[] = { 324 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 325 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 326 /* Legacy names */ 327 TC /* ASID */, BUSCR /* MMUBAR */, 328 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 329 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 330 0 331 }; 332 static const enum m68k_register mcf5485_ctrl[] = { 333 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR, 334 VBR, PC, RAMBAR0, RAMBAR1, MBAR, 335 /* Legacy names */ 336 TC /* ASID */, BUSCR /* MMUBAR */, 337 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */, 338 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */, 339 0 340 }; 341 static const enum m68k_register fido_ctrl[] = { 342 SFC, DFC, USP, VBR, CAC, MBO, 343 0 344 }; 345 #define cpu32_ctrl m68010_ctrl 346 347 static const enum m68k_register *control_regs; 348 349 /* Internal form of a 68020 instruction. */ 350 struct m68k_it 351 { 352 const char *error; 353 const char *args; /* List of opcode info. */ 354 int numargs; 355 356 int numo; /* Number of shorts in opcode. */ 357 short opcode[11]; 358 359 struct m68k_op operands[6]; 360 361 int nexp; /* Number of exprs in use. */ 362 struct m68k_exp exprs[4]; 363 364 int nfrag; /* Number of frags we have to produce. */ 365 struct 366 { 367 int fragoff; /* Where in the current opcode the frag ends. */ 368 symbolS *fadd; 369 offsetT foff; 370 int fragty; 371 } 372 fragb[4]; 373 374 int nrel; /* Num of reloc strucs in use. */ 375 struct 376 { 377 int n; 378 expressionS exp; 379 char wid; 380 char pcrel; 381 /* In a pc relative address the difference between the address 382 of the offset and the address that the offset is relative 383 to. This depends on the addressing mode. Basically this 384 is the value to put in the offset field to address the 385 first byte of the offset, without regarding the special 386 significance of some values (in the branch instruction, for 387 example). */ 388 int pcrel_fix; 389 #ifdef OBJ_ELF 390 /* Whether this expression needs special pic relocation, and if 391 so, which. */ 392 enum pic_relocation pic_reloc; 393 #endif 394 } 395 reloc[5]; /* Five is enough??? */ 396 }; 397 398 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a)) 399 #define float_of_arch(x) ((x) & mfloat) 400 #define mmu_of_arch(x) ((x) & mmmu) 401 #define arch_coldfire_p(x) ((x) & mcfisa_a) 402 #define arch_coldfire_fpu(x) ((x) & cfloat) 403 404 /* Macros for determining if cpu supports a specific addressing mode. */ 405 #define HAVE_LONG_DISP(x) \ 406 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 407 #define HAVE_LONG_CALL(x) \ 408 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 409 #define HAVE_LONG_COND(x) \ 410 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c)) 411 #define HAVE_LONG_BRANCH(x) \ 412 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b)) 413 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x)) 414 415 static struct m68k_it the_ins; /* The instruction being assembled. */ 416 417 #define op(ex) ((ex)->exp.X_op) 418 #define adds(ex) ((ex)->exp.X_add_symbol) 419 #define subs(ex) ((ex)->exp.X_op_symbol) 420 #define offs(ex) ((ex)->exp.X_add_number) 421 422 /* Macros for adding things to the m68k_it struct. */ 423 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w)) 424 425 /* Like addword, but goes BEFORE general operands. */ 426 427 static void 428 insop (int w, const struct m68k_incant *opcode) 429 { 430 int z; 431 for (z = the_ins.numo; z > opcode->m_codenum; --z) 432 the_ins.opcode[z] = the_ins.opcode[z - 1]; 433 for (z = 0; z < the_ins.nrel; z++) 434 the_ins.reloc[z].n += 2; 435 for (z = 0; z < the_ins.nfrag; z++) 436 the_ins.fragb[z].fragoff++; 437 the_ins.opcode[opcode->m_codenum] = w; 438 the_ins.numo++; 439 } 440 441 /* The numo+1 kludge is so we can hit the low order byte of the prev word. 442 Blecch. */ 443 static void 444 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix) 445 { 446 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3' 447 ? the_ins.numo * 2 - 1 448 : (width == 'b' 449 ? the_ins.numo * 2 + 1 450 : the_ins.numo * 2)); 451 the_ins.reloc[the_ins.nrel].exp = exp->exp; 452 the_ins.reloc[the_ins.nrel].wid = width; 453 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix; 454 #ifdef OBJ_ELF 455 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc; 456 #endif 457 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel; 458 } 459 460 /* Cause an extra frag to be generated here, inserting up to 10 bytes 461 (that value is chosen in the frag_var call in md_assemble). TYPE 462 is the subtype of the frag to be generated; its primary type is 463 rs_machine_dependent. 464 465 The TYPE parameter is also used by md_convert_frag_1 and 466 md_estimate_size_before_relax. The appropriate type of fixup will 467 be emitted by md_convert_frag_1. 468 469 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 470 static void 471 add_frag (symbolS *add, offsetT off, int type) 472 { 473 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo; 474 the_ins.fragb[the_ins.nfrag].fadd = add; 475 the_ins.fragb[the_ins.nfrag].foff = off; 476 the_ins.fragb[the_ins.nfrag++].fragty = type; 477 } 478 479 #define isvar(ex) \ 480 (op (ex) != O_constant && op (ex) != O_big) 481 482 static char *crack_operand (char *str, struct m68k_op *opP); 483 static int get_num (struct m68k_exp *exp, int ok); 484 static int reverse_16_bits (int in); 485 static int reverse_8_bits (int in); 486 static void install_gen_operand (int mode, int val); 487 static void install_operand (int mode, int val); 488 static void s_bss (int); 489 static void s_data1 (int); 490 static void s_data2 (int); 491 static void s_even (int); 492 static void s_proc (int); 493 static void s_chip (int); 494 static void s_fopt (int); 495 static void s_opt (int); 496 static void s_reg (int); 497 static void s_restore (int); 498 static void s_save (int); 499 static void s_mri_if (int); 500 static void s_mri_else (int); 501 static void s_mri_endi (int); 502 static void s_mri_break (int); 503 static void s_mri_next (int); 504 static void s_mri_for (int); 505 static void s_mri_endf (int); 506 static void s_mri_repeat (int); 507 static void s_mri_until (int); 508 static void s_mri_while (int); 509 static void s_mri_endw (int); 510 static void s_m68k_cpu (int); 511 static void s_m68k_arch (int); 512 513 struct m68k_cpu 514 { 515 unsigned long arch; /* Architecture features. */ 516 const enum m68k_register *control_regs; /* Control regs on chip */ 517 const char *name; /* Name */ 518 int alias; /* Alias for a cannonical name. If 1, then 519 succeeds canonical name, if -1 then 520 succeeds canonical name, if <-1 ||>1 this is a 521 deprecated name, and the next/previous name 522 should be used. */ 523 }; 524 525 /* We hold flags for features explicitly enabled and explicitly 526 disabled. */ 527 static int current_architecture; 528 static int not_current_architecture; 529 static const struct m68k_cpu *selected_arch; 530 static const struct m68k_cpu *selected_cpu; 531 static int initialized; 532 533 /* Architecture models. */ 534 static const struct m68k_cpu m68k_archs[] = 535 { 536 {m68000, m68000_ctrl, "68000", 0}, 537 {m68010, m68010_ctrl, "68010", 0}, 538 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 539 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 540 {m68040, m68040_ctrl, "68040", 0}, 541 {m68060, m68060_ctrl, "68060", 0}, 542 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 543 {fido_a, fido_ctrl, "fidoa", 0}, 544 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0}, 545 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0}, 546 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0}, 547 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0}, 548 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0}, 549 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0}, 550 {0,0,NULL, 0} 551 }; 552 553 /* For -mno-mac we want to turn off all types of mac. */ 554 static const unsigned no_mac = mcfmac | mcfemac; 555 556 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0 557 for either. */ 558 static const struct m68k_cpu m68k_extensions[] = 559 { 560 {m68851, NULL, "68851", -1}, 561 {m68881, NULL, "68881", -1}, 562 {m68881, NULL, "68882", -1}, 563 564 {cfloat|m68881, NULL, "float", 0}, 565 566 {mcfhwdiv, NULL, "div", 1}, 567 {mcfusp, NULL, "usp", 1}, 568 {mcfmac, (void *)&no_mac, "mac", 1}, 569 {mcfemac, NULL, "emac", 1}, 570 571 {0,NULL,NULL, 0} 572 }; 573 574 /* Processor list */ 575 static const struct m68k_cpu m68k_cpus[] = 576 { 577 {m68000, m68000_ctrl, "68000", 0}, 578 {m68000, m68000_ctrl, "68ec000", 1}, 579 {m68000, m68000_ctrl, "68hc000", 1}, 580 {m68000, m68000_ctrl, "68hc001", 1}, 581 {m68000, m68000_ctrl, "68008", 1}, 582 {m68000, m68000_ctrl, "68302", 1}, 583 {m68000, m68000_ctrl, "68306", 1}, 584 {m68000, m68000_ctrl, "68307", 1}, 585 {m68000, m68000_ctrl, "68322", 1}, 586 {m68000, m68000_ctrl, "68356", 1}, 587 {m68010, m68010_ctrl, "68010", 0}, 588 {m68020|m68881|m68851, m68020_ctrl, "68020", 0}, 589 {m68020|m68881|m68851, m68020_ctrl, "68k", 1}, 590 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1}, 591 {m68030|m68881|m68851, m68020_ctrl, "68030", 0}, 592 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1}, 593 {m68040, m68040_ctrl, "68040", 0}, 594 {m68040, m68040_ctrl, "68ec040", 1}, 595 {m68060, m68060_ctrl, "68060", 0}, 596 {m68060, m68060_ctrl, "68ec060", 1}, 597 598 {cpu32|m68881, cpu32_ctrl, "cpu32", 0}, 599 {cpu32|m68881, cpu32_ctrl, "68330", 1}, 600 {cpu32|m68881, cpu32_ctrl, "68331", 1}, 601 {cpu32|m68881, cpu32_ctrl, "68332", 1}, 602 {cpu32|m68881, cpu32_ctrl, "68333", 1}, 603 {cpu32|m68881, cpu32_ctrl, "68334", 1}, 604 {cpu32|m68881, cpu32_ctrl, "68336", 1}, 605 {cpu32|m68881, cpu32_ctrl, "68340", 1}, 606 {cpu32|m68881, cpu32_ctrl, "68341", 1}, 607 {cpu32|m68881, cpu32_ctrl, "68349", 1}, 608 {cpu32|m68881, cpu32_ctrl, "68360", 1}, 609 610 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0}, 611 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1}, 612 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1}, 613 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1}, 614 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1}, 615 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1}, 616 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1}, 617 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1}, 618 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1}, 619 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1}, 620 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1}, 621 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1}, 622 623 {mcfisa_a, mcf_ctrl, "5200", 0}, 624 {mcfisa_a, mcf_ctrl, "5202", 1}, 625 {mcfisa_a, mcf_ctrl, "5204", 1}, 626 {mcfisa_a, mcf5206_ctrl, "5206", 1}, 627 628 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0}, 629 630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1}, 631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0}, 632 633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0}, 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1}, 635 636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1}, 637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1}, 638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0}, 639 640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1}, 641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0}, 642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2}, 643 644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0}, 645 646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1}, 647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0}, 648 649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1}, 650 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1}, 651 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1}, 652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0}, 653 654 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1}, 655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0}, 656 657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1}, 658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0}, 659 660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1}, 661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1}, 662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1}, 663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1}, 664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0}, 665 666 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0}, 667 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0}, 668 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0}, 669 670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1}, 671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1}, 672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1}, 673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1}, 674 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1}, 675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0}, 676 677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1}, 678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0}, 679 680 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0}, 681 682 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1}, 683 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0}, 684 685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1}, 686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1}, 687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1}, 688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0}, 689 690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1}, 691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1}, 692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1}, 693 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1}, 694 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1}, 695 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1}, 696 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0}, 697 698 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0}, 699 700 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1}, 701 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1}, 702 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1}, 703 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0}, 704 705 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1}, 706 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1}, 707 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0}, 708 709 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0}, 710 711 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1}, 712 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1}, 713 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1}, 714 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1}, 715 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0}, 716 717 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1}, 718 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1}, 719 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1}, 720 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1}, 721 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1}, 722 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0}, 723 724 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1}, 725 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1}, 726 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1}, 727 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1}, 728 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1}, 729 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1}, 730 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0}, 731 732 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1}, 733 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1}, 734 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1}, 735 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1}, 736 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1}, 737 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1}, 738 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0}, 739 740 {fido_a, fido_ctrl, "fidoa", 0}, 741 {fido_a, fido_ctrl, "fido", 1}, 742 743 {0,NULL,NULL, 0} 744 }; 745 746 static const struct m68k_cpu *m68k_lookup_cpu 747 (const char *, const struct m68k_cpu *, int, int *); 748 static int m68k_set_arch (const char *, int, int); 749 static int m68k_set_cpu (const char *, int, int); 750 static int m68k_set_extension (const char *, int, int); 751 static void m68k_init_arch (void); 752 753 /* This is the assembler relaxation table for m68k. m68k is a rich CISC 754 architecture and we have a lot of relaxation modes. */ 755 756 /* Macros used in the relaxation code. */ 757 #define TAB(x,y) (((x) << 2) + (y)) 758 #define TABTYPE(x) ((x) >> 2) 759 760 /* Relaxation states. */ 761 #define BYTE 0 762 #define SHORT 1 763 #define LONG 2 764 #define SZ_UNDEF 3 765 766 /* Here are all the relaxation modes we support. First we can relax ordinary 767 branches. On 68020 and higher and on CPU32 all branch instructions take 768 three forms, so on these CPUs all branches always remain as such. When we 769 have to expand to the LONG form on a 68000, though, we substitute an 770 absolute jump instead. This is a direct replacement for unconditional 771 branches and a branch over a jump for conditional branches. However, if the 772 user requires PIC and disables this with --pcrel, we can only relax between 773 BYTE and SHORT forms, punting if that isn't enough. This gives us four 774 different relaxation modes for branches: */ 775 776 #define BRANCHBWL 0 /* Branch byte, word, or long. */ 777 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ 778 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ 779 #define BRANCHBW 3 /* Branch byte or word. */ 780 781 /* We also relax coprocessor branches and DBcc's. All CPUs that support 782 coprocessor branches support them in word and long forms, so we have only 783 one relaxation mode for them. DBcc's are word only on all CPUs. We can 784 relax them to the LONG form with a branch-around sequence. This sequence 785 can use a long branch (if available) or an absolute jump (if acceptable). 786 This gives us two relaxation modes. If long branches are not available and 787 absolute jumps are not acceptable, we don't relax DBcc's. */ 788 789 #define FBRANCH 4 /* Coprocessor branch. */ 790 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */ 791 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ 792 793 /* That's all for instruction relaxation. However, we also relax PC-relative 794 operands. Specifically, we have three operand relaxation modes. On the 795 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and 796 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the 797 two. Also PC+displacement+index operands in their simple form (with a non- 798 suppressed index without memory indirection) are supported on all CPUs, but 799 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher 800 and on CPU32 we relax it to SHORT and LONG forms as well using the extended 801 form of the PC+displacement+index operand. Finally, some absolute operands 802 can be relaxed down to 16-bit PC-relative. */ 803 804 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ 805 #define PCINDEX 8 /* PC + displacement + index. */ 806 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ 807 808 /* This relaxation is required for branches where there is no long 809 branch and we are in pcrel mode. We generate a bne/beq pair. */ 810 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs 811 */ 812 813 /* Note that calls to frag_var need to specify the maximum expansion 814 needed; this is currently 12 bytes for bne/beq pair. */ 815 #define FRAG_VAR_SIZE 12 816 817 /* The fields are: 818 How far Forward this mode will reach: 819 How far Backward this mode will reach: 820 How many bytes this mode will add to the size of the frag 821 Which mode to go to if the offset won't fit in this one 822 823 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */ 824 relax_typeS md_relax_table[] = 825 { 826 { 127, -128, 0, TAB (BRANCHBWL, SHORT) }, 827 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) }, 828 { 0, 0, 4, 0 }, 829 { 1, 1, 0, 0 }, 830 831 { 127, -128, 0, TAB (BRABSJUNC, SHORT) }, 832 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) }, 833 { 0, 0, 4, 0 }, 834 { 1, 1, 0, 0 }, 835 836 { 127, -128, 0, TAB (BRABSJCOND, SHORT) }, 837 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) }, 838 { 0, 0, 6, 0 }, 839 { 1, 1, 0, 0 }, 840 841 { 127, -128, 0, TAB (BRANCHBW, SHORT) }, 842 { 0, 0, 2, 0 }, 843 { 1, 1, 0, 0 }, 844 { 1, 1, 0, 0 }, 845 846 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ 847 { 32767, -32768, 2, TAB (FBRANCH, LONG) }, 848 { 0, 0, 4, 0 }, 849 { 1, 1, 0, 0 }, 850 851 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 852 { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, 853 { 0, 0, 10, 0 }, 854 { 1, 1, 0, 0 }, 855 856 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ 857 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, 858 { 0, 0, 10, 0 }, 859 { 1, 1, 0, 0 }, 860 861 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ 862 { 32767, -32768, 2, TAB (PCREL1632, LONG) }, 863 { 0, 0, 6, 0 }, 864 { 1, 1, 0, 0 }, 865 866 { 125, -130, 0, TAB (PCINDEX, SHORT) }, 867 { 32765, -32770, 2, TAB (PCINDEX, LONG) }, 868 { 0, 0, 4, 0 }, 869 { 1, 1, 0, 0 }, 870 871 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ 872 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, 873 { 0, 0, 4, 0 }, 874 { 1, 1, 0, 0 }, 875 876 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) }, 877 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) }, 878 { 0, 0, 10, 0 }, 879 { 1, 1, 0, 0 }, 880 }; 881 882 /* These are the machine dependent pseudo-ops. These are included so 883 the assembler can work on the output from the SUN C compiler, which 884 generates these. */ 885 886 /* This table describes all the machine specific pseudo-ops the assembler 887 has to support. The fields are: 888 pseudo-op name without dot 889 function to call to execute this pseudo-op 890 Integer arg to pass to the function. */ 891 const pseudo_typeS md_pseudo_table[] = 892 { 893 {"data1", s_data1, 0}, 894 {"data2", s_data2, 0}, 895 {"bss", s_bss, 0}, 896 {"even", s_even, 0}, 897 {"skip", s_space, 0}, 898 {"proc", s_proc, 0}, 899 #if defined (TE_SUN3) || defined (OBJ_ELF) 900 {"align", s_align_bytes, 0}, 901 #endif 902 #ifdef OBJ_ELF 903 {"swbeg", s_ignore, 0}, 904 {"long", m68k_elf_cons, 4}, 905 #endif 906 {"extend", float_cons, 'x'}, 907 {"ldouble", float_cons, 'x'}, 908 909 {"arch", s_m68k_arch, 0}, 910 {"cpu", s_m68k_cpu, 0}, 911 912 /* The following pseudo-ops are supported for MRI compatibility. */ 913 {"chip", s_chip, 0}, 914 {"comline", s_space, 1}, 915 {"fopt", s_fopt, 0}, 916 {"mask2", s_ignore, 0}, 917 {"opt", s_opt, 0}, 918 {"reg", s_reg, 0}, 919 {"restore", s_restore, 0}, 920 {"save", s_save, 0}, 921 922 {"if", s_mri_if, 0}, 923 {"if.b", s_mri_if, 'b'}, 924 {"if.w", s_mri_if, 'w'}, 925 {"if.l", s_mri_if, 'l'}, 926 {"else", s_mri_else, 0}, 927 {"else.s", s_mri_else, 's'}, 928 {"else.l", s_mri_else, 'l'}, 929 {"endi", s_mri_endi, 0}, 930 {"break", s_mri_break, 0}, 931 {"break.s", s_mri_break, 's'}, 932 {"break.l", s_mri_break, 'l'}, 933 {"next", s_mri_next, 0}, 934 {"next.s", s_mri_next, 's'}, 935 {"next.l", s_mri_next, 'l'}, 936 {"for", s_mri_for, 0}, 937 {"for.b", s_mri_for, 'b'}, 938 {"for.w", s_mri_for, 'w'}, 939 {"for.l", s_mri_for, 'l'}, 940 {"endf", s_mri_endf, 0}, 941 {"repeat", s_mri_repeat, 0}, 942 {"until", s_mri_until, 0}, 943 {"until.b", s_mri_until, 'b'}, 944 {"until.w", s_mri_until, 'w'}, 945 {"until.l", s_mri_until, 'l'}, 946 {"while", s_mri_while, 0}, 947 {"while.b", s_mri_while, 'b'}, 948 {"while.w", s_mri_while, 'w'}, 949 {"while.l", s_mri_while, 'l'}, 950 {"endw", s_mri_endw, 0}, 951 952 {0, 0, 0} 953 }; 954 955 /* The mote pseudo ops are put into the opcode table, since they 956 don't start with a . they look like opcodes to gas. */ 957 958 const pseudo_typeS mote_pseudo_table[] = 959 { 960 961 {"dcl", cons, 4}, 962 {"dc", cons, 2}, 963 {"dcw", cons, 2}, 964 {"dcb", cons, 1}, 965 966 {"dsl", s_space, 4}, 967 {"ds", s_space, 2}, 968 {"dsw", s_space, 2}, 969 {"dsb", s_space, 1}, 970 971 {"xdef", s_globl, 0}, 972 #ifdef OBJ_ELF 973 {"align", s_align_bytes, 0}, 974 #else 975 {"align", s_align_ptwo, 0}, 976 #endif 977 #ifdef M68KCOFF 978 {"sect", obj_coff_section, 0}, 979 {"section", obj_coff_section, 0}, 980 #endif 981 {0, 0, 0} 982 }; 983 984 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host 985 gives identical results to a 32-bit host. */ 986 #define TRUNC(X) ((valueT) (X) & 0xffffffff) 987 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000) 988 989 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100) 990 #define isubyte(x) ((valueT) TRUNC (x) < 0x100) 991 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000) 992 #define isuword(x) ((valueT) TRUNC (x) < 0x10000) 993 994 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff) 995 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff) 996 #define islong(x) (1) 997 998 static char notend_table[256]; 999 static char alt_notend_table[256]; 1000 #define notend(s) \ 1001 (! (notend_table[(unsigned char) *s] \ 1002 || (*s == ':' \ 1003 && alt_notend_table[(unsigned char) s[1]]))) 1004 1005 #ifdef OBJ_ELF 1006 1007 /* Return zero if the reference to SYMBOL from within the same segment may 1008 be relaxed. */ 1009 1010 /* On an ELF system, we can't relax an externally visible symbol, 1011 because it may be overridden by a shared library. However, if 1012 TARGET_OS is "elf", then we presume that we are assembling for an 1013 embedded system, in which case we don't have to worry about shared 1014 libraries, and we can relax any external sym. */ 1015 1016 #define relaxable_symbol(symbol) \ 1017 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ 1018 || S_IS_WEAK (symbol))) 1019 1020 /* Compute the relocation code for a fixup of SIZE bytes, using pc 1021 relative relocation if PCREL is non-zero. PIC says whether a special 1022 pic relocation was requested. */ 1023 1024 static bfd_reloc_code_real_type 1025 get_reloc_code (int size, int pcrel, enum pic_relocation pic) 1026 { 1027 switch (pic) 1028 { 1029 case pic_got_pcrel: 1030 switch (size) 1031 { 1032 case 1: 1033 return BFD_RELOC_8_GOT_PCREL; 1034 case 2: 1035 return BFD_RELOC_16_GOT_PCREL; 1036 case 4: 1037 return BFD_RELOC_32_GOT_PCREL; 1038 } 1039 break; 1040 1041 case pic_got_off: 1042 switch (size) 1043 { 1044 case 1: 1045 return BFD_RELOC_8_GOTOFF; 1046 case 2: 1047 return BFD_RELOC_16_GOTOFF; 1048 case 4: 1049 return BFD_RELOC_32_GOTOFF; 1050 } 1051 break; 1052 1053 case pic_plt_pcrel: 1054 switch (size) 1055 { 1056 case 1: 1057 return BFD_RELOC_8_PLT_PCREL; 1058 case 2: 1059 return BFD_RELOC_16_PLT_PCREL; 1060 case 4: 1061 return BFD_RELOC_32_PLT_PCREL; 1062 } 1063 break; 1064 1065 case pic_plt_off: 1066 switch (size) 1067 { 1068 case 1: 1069 return BFD_RELOC_8_PLTOFF; 1070 case 2: 1071 return BFD_RELOC_16_PLTOFF; 1072 case 4: 1073 return BFD_RELOC_32_PLTOFF; 1074 } 1075 break; 1076 1077 case pic_tls_gd: 1078 switch (size) 1079 { 1080 case 1: 1081 return BFD_RELOC_68K_TLS_GD8; 1082 case 2: 1083 return BFD_RELOC_68K_TLS_GD16; 1084 case 4: 1085 return BFD_RELOC_68K_TLS_GD32; 1086 } 1087 break; 1088 1089 case pic_tls_ldm: 1090 switch (size) 1091 { 1092 case 1: 1093 return BFD_RELOC_68K_TLS_LDM8; 1094 case 2: 1095 return BFD_RELOC_68K_TLS_LDM16; 1096 case 4: 1097 return BFD_RELOC_68K_TLS_LDM32; 1098 } 1099 break; 1100 1101 case pic_tls_ldo: 1102 switch (size) 1103 { 1104 case 1: 1105 return BFD_RELOC_68K_TLS_LDO8; 1106 case 2: 1107 return BFD_RELOC_68K_TLS_LDO16; 1108 case 4: 1109 return BFD_RELOC_68K_TLS_LDO32; 1110 } 1111 break; 1112 1113 case pic_tls_ie: 1114 switch (size) 1115 { 1116 case 1: 1117 return BFD_RELOC_68K_TLS_IE8; 1118 case 2: 1119 return BFD_RELOC_68K_TLS_IE16; 1120 case 4: 1121 return BFD_RELOC_68K_TLS_IE32; 1122 } 1123 break; 1124 1125 case pic_tls_le: 1126 switch (size) 1127 { 1128 case 1: 1129 return BFD_RELOC_68K_TLS_LE8; 1130 case 2: 1131 return BFD_RELOC_68K_TLS_LE16; 1132 case 4: 1133 return BFD_RELOC_68K_TLS_LE32; 1134 } 1135 break; 1136 1137 case pic_none: 1138 if (pcrel) 1139 { 1140 switch (size) 1141 { 1142 case 1: 1143 return BFD_RELOC_8_PCREL; 1144 case 2: 1145 return BFD_RELOC_16_PCREL; 1146 case 4: 1147 return BFD_RELOC_32_PCREL; 1148 } 1149 } 1150 else 1151 { 1152 switch (size) 1153 { 1154 case 1: 1155 return BFD_RELOC_8; 1156 case 2: 1157 return BFD_RELOC_16; 1158 case 4: 1159 return BFD_RELOC_32; 1160 } 1161 } 1162 } 1163 1164 if (pcrel) 1165 { 1166 if (pic == pic_none) 1167 as_bad (_("Can not do %d byte pc-relative relocation"), size); 1168 else 1169 as_bad (_("Can not do %d byte pc-relative pic relocation"), size); 1170 } 1171 else 1172 { 1173 if (pic == pic_none) 1174 as_bad (_("Can not do %d byte relocation"), size); 1175 else 1176 as_bad (_("Can not do %d byte pic relocation"), size); 1177 } 1178 1179 return BFD_RELOC_NONE; 1180 } 1181 1182 /* Here we decide which fixups can be adjusted to make them relative 1183 to the beginning of the section instead of the symbol. Basically 1184 we need to make sure that the dynamic relocations are done 1185 correctly, so in some cases we force the original symbol to be 1186 used. */ 1187 int 1188 tc_m68k_fix_adjustable (fixS *fixP) 1189 { 1190 /* Adjust_reloc_syms doesn't know about the GOT. */ 1191 switch (fixP->fx_r_type) 1192 { 1193 case BFD_RELOC_8_GOT_PCREL: 1194 case BFD_RELOC_16_GOT_PCREL: 1195 case BFD_RELOC_32_GOT_PCREL: 1196 case BFD_RELOC_8_GOTOFF: 1197 case BFD_RELOC_16_GOTOFF: 1198 case BFD_RELOC_32_GOTOFF: 1199 case BFD_RELOC_8_PLT_PCREL: 1200 case BFD_RELOC_16_PLT_PCREL: 1201 case BFD_RELOC_32_PLT_PCREL: 1202 case BFD_RELOC_8_PLTOFF: 1203 case BFD_RELOC_16_PLTOFF: 1204 case BFD_RELOC_32_PLTOFF: 1205 case BFD_RELOC_68K_TLS_GD32: 1206 case BFD_RELOC_68K_TLS_GD16: 1207 case BFD_RELOC_68K_TLS_GD8: 1208 case BFD_RELOC_68K_TLS_LDM32: 1209 case BFD_RELOC_68K_TLS_LDM16: 1210 case BFD_RELOC_68K_TLS_LDM8: 1211 case BFD_RELOC_68K_TLS_LDO32: 1212 case BFD_RELOC_68K_TLS_LDO16: 1213 case BFD_RELOC_68K_TLS_LDO8: 1214 case BFD_RELOC_68K_TLS_IE32: 1215 case BFD_RELOC_68K_TLS_IE16: 1216 case BFD_RELOC_68K_TLS_IE8: 1217 case BFD_RELOC_68K_TLS_LE32: 1218 case BFD_RELOC_68K_TLS_LE16: 1219 case BFD_RELOC_68K_TLS_LE8: 1220 return 0; 1221 1222 case BFD_RELOC_VTABLE_INHERIT: 1223 case BFD_RELOC_VTABLE_ENTRY: 1224 return 0; 1225 1226 default: 1227 return 1; 1228 } 1229 } 1230 1231 #else /* !OBJ_ELF */ 1232 1233 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC 1234 1235 /* PR gas/3041 Weak symbols are not relaxable 1236 because they must be treated as extern. */ 1237 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol))) 1238 1239 #endif /* OBJ_ELF */ 1240 1241 arelent * 1242 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 1243 { 1244 arelent *reloc; 1245 bfd_reloc_code_real_type code; 1246 1247 /* If the tcbit is set, then this was a fixup of a negative value 1248 that was never resolved. We do not have a reloc to handle this, 1249 so just return. We assume that other code will have detected this 1250 situation and produced a helpful error message, so we just tell the 1251 user that the reloc cannot be produced. */ 1252 if (fixp->fx_tcbit) 1253 { 1254 if (fixp->fx_addsy) 1255 as_bad_where (fixp->fx_file, fixp->fx_line, 1256 _("Unable to produce reloc against symbol '%s'"), 1257 S_GET_NAME (fixp->fx_addsy)); 1258 return NULL; 1259 } 1260 1261 if (fixp->fx_r_type != BFD_RELOC_NONE) 1262 { 1263 code = fixp->fx_r_type; 1264 1265 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible 1266 that fixup_segment converted a non-PC relative reloc into a 1267 PC relative reloc. In such a case, we need to convert the 1268 reloc code. */ 1269 if (fixp->fx_pcrel) 1270 { 1271 switch (code) 1272 { 1273 case BFD_RELOC_8: 1274 code = BFD_RELOC_8_PCREL; 1275 break; 1276 case BFD_RELOC_16: 1277 code = BFD_RELOC_16_PCREL; 1278 break; 1279 case BFD_RELOC_32: 1280 code = BFD_RELOC_32_PCREL; 1281 break; 1282 case BFD_RELOC_8_PCREL: 1283 case BFD_RELOC_16_PCREL: 1284 case BFD_RELOC_32_PCREL: 1285 case BFD_RELOC_8_GOT_PCREL: 1286 case BFD_RELOC_16_GOT_PCREL: 1287 case BFD_RELOC_32_GOT_PCREL: 1288 case BFD_RELOC_8_GOTOFF: 1289 case BFD_RELOC_16_GOTOFF: 1290 case BFD_RELOC_32_GOTOFF: 1291 case BFD_RELOC_8_PLT_PCREL: 1292 case BFD_RELOC_16_PLT_PCREL: 1293 case BFD_RELOC_32_PLT_PCREL: 1294 case BFD_RELOC_8_PLTOFF: 1295 case BFD_RELOC_16_PLTOFF: 1296 case BFD_RELOC_32_PLTOFF: 1297 case BFD_RELOC_68K_TLS_GD32: 1298 case BFD_RELOC_68K_TLS_GD16: 1299 case BFD_RELOC_68K_TLS_GD8: 1300 case BFD_RELOC_68K_TLS_LDM32: 1301 case BFD_RELOC_68K_TLS_LDM16: 1302 case BFD_RELOC_68K_TLS_LDM8: 1303 case BFD_RELOC_68K_TLS_LDO32: 1304 case BFD_RELOC_68K_TLS_LDO16: 1305 case BFD_RELOC_68K_TLS_LDO8: 1306 case BFD_RELOC_68K_TLS_IE32: 1307 case BFD_RELOC_68K_TLS_IE16: 1308 case BFD_RELOC_68K_TLS_IE8: 1309 case BFD_RELOC_68K_TLS_LE32: 1310 case BFD_RELOC_68K_TLS_LE16: 1311 case BFD_RELOC_68K_TLS_LE8: 1312 break; 1313 default: 1314 as_bad_where (fixp->fx_file, fixp->fx_line, 1315 _("Cannot make %s relocation PC relative"), 1316 bfd_get_reloc_code_name (code)); 1317 } 1318 } 1319 } 1320 else 1321 { 1322 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) 1323 switch (F (fixp->fx_size, fixp->fx_pcrel)) 1324 { 1325 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break 1326 MAP (1, 0, BFD_RELOC_8); 1327 MAP (2, 0, BFD_RELOC_16); 1328 MAP (4, 0, BFD_RELOC_32); 1329 MAP (1, 1, BFD_RELOC_8_PCREL); 1330 MAP (2, 1, BFD_RELOC_16_PCREL); 1331 MAP (4, 1, BFD_RELOC_32_PCREL); 1332 default: 1333 abort (); 1334 } 1335 } 1336 #undef F 1337 #undef MAP 1338 1339 reloc = (arelent *) xmalloc (sizeof (arelent)); 1340 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 1341 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 1342 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 1343 #ifndef OBJ_ELF 1344 if (OUTPUT_FLAVOR == bfd_target_aout_flavour 1345 && fixp->fx_addsy 1346 && S_IS_WEAK (fixp->fx_addsy) 1347 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy))) 1348 { 1349 /* PR gas/3041 References to weak symbols must be treated as extern 1350 in order to be overridable by the linker, even if they are defined 1351 in the same object file. So the original addend must be written 1352 "as is" into the output section without further processing. 1353 The addend value must be hacked here in order to force 1354 bfd_install_relocation() to write the original value into the 1355 output section. 1356 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol 1357 value has already been added to the addend in fixup_segment(). We 1358 have to remove it. 1359 2) bfd_install_relocation() will incorrectly treat this symbol as 1360 resolved, so it will write the symbol value plus its addend and 1361 section VMA. As a workaround we can tweak the addend value here in 1362 order to get the original value in the section after the call to 1363 bfd_install_relocation(). */ 1364 reloc->addend = fixp->fx_addnumber 1365 /* Fix because of MD_APPLY_SYM_VALUE() */ 1366 - S_GET_VALUE (fixp->fx_addsy) 1367 /* Fix for bfd_install_relocation() */ 1368 - (S_GET_VALUE (fixp->fx_addsy) 1369 + S_GET_SEGMENT (fixp->fx_addsy)->vma); 1370 } 1371 else if (fixp->fx_pcrel) 1372 reloc->addend = fixp->fx_addnumber; 1373 else 1374 reloc->addend = 0; 1375 #else 1376 if (!fixp->fx_pcrel) 1377 reloc->addend = fixp->fx_addnumber; 1378 else 1379 reloc->addend = (section->vma 1380 /* Explicit sign extension in case char is 1381 unsigned. */ 1382 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80 1383 + fixp->fx_addnumber 1384 + md_pcrel_from (fixp)); 1385 #endif 1386 1387 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 1388 gas_assert (reloc->howto != 0); 1389 1390 return reloc; 1391 } 1392 1393 /* Handle of the OPCODE hash table. NULL means any use before 1394 m68k_ip_begin() will crash. */ 1395 static struct hash_control *op_hash; 1396 1397 /* Assemble an m68k instruction. */ 1398 1399 static void 1400 m68k_ip (char *instring) 1401 { 1402 register char *p; 1403 register struct m68k_op *opP; 1404 register const struct m68k_incant *opcode; 1405 register const char *s; 1406 register int tmpreg = 0, baseo = 0, outro = 0, nextword; 1407 char *pdot, *pdotmove; 1408 enum m68k_size siz1, siz2; 1409 char c; 1410 int losing; 1411 int opsfound; 1412 struct m68k_op operands_backup[6]; 1413 LITTLENUM_TYPE words[6]; 1414 LITTLENUM_TYPE *wordp; 1415 unsigned long ok_arch = 0; 1416 1417 if (*instring == ' ') 1418 instring++; /* Skip leading whitespace. */ 1419 1420 /* Scan up to end of operation-code, which MUST end in end-of-string 1421 or exactly 1 space. */ 1422 pdot = 0; 1423 for (p = instring; *p != '\0'; p++) 1424 { 1425 if (*p == ' ') 1426 break; 1427 if (*p == '.') 1428 pdot = p; 1429 } 1430 1431 if (p == instring) 1432 { 1433 the_ins.error = _("No operator"); 1434 return; 1435 } 1436 1437 /* p now points to the end of the opcode name, probably whitespace. 1438 Make sure the name is null terminated by clobbering the 1439 whitespace, look it up in the hash table, then fix it back. 1440 Remove a dot, first, since the opcode tables have none. */ 1441 if (pdot != NULL) 1442 { 1443 for (pdotmove = pdot; pdotmove < p; pdotmove++) 1444 *pdotmove = pdotmove[1]; 1445 p--; 1446 } 1447 1448 c = *p; 1449 *p = '\0'; 1450 opcode = (const struct m68k_incant *) hash_find (op_hash, instring); 1451 *p = c; 1452 1453 if (pdot != NULL) 1454 { 1455 for (pdotmove = p; pdotmove > pdot; pdotmove--) 1456 *pdotmove = pdotmove[-1]; 1457 *pdot = '.'; 1458 ++p; 1459 } 1460 1461 if (opcode == NULL) 1462 { 1463 the_ins.error = _("Unknown operator"); 1464 return; 1465 } 1466 1467 /* Found a legitimate opcode, start matching operands. */ 1468 while (*p == ' ') 1469 ++p; 1470 1471 if (opcode->m_operands == 0) 1472 { 1473 char *old = input_line_pointer; 1474 *old = '\n'; 1475 input_line_pointer = p; 1476 /* Ahh - it's a motorola style psuedo op. */ 1477 mote_pseudo_table[opcode->m_opnum].poc_handler 1478 (mote_pseudo_table[opcode->m_opnum].poc_val); 1479 input_line_pointer = old; 1480 *old = 0; 1481 1482 return; 1483 } 1484 1485 if (flag_mri && opcode->m_opnum == 0) 1486 { 1487 /* In MRI mode, random garbage is allowed after an instruction 1488 which accepts no operands. */ 1489 the_ins.args = opcode->m_operands; 1490 the_ins.numargs = opcode->m_opnum; 1491 the_ins.numo = opcode->m_codenum; 1492 the_ins.opcode[0] = getone (opcode); 1493 the_ins.opcode[1] = gettwo (opcode); 1494 return; 1495 } 1496 1497 for (opP = &the_ins.operands[0]; *p; opP++) 1498 { 1499 p = crack_operand (p, opP); 1500 1501 if (opP->error) 1502 { 1503 the_ins.error = opP->error; 1504 return; 1505 } 1506 } 1507 1508 opsfound = opP - &the_ins.operands[0]; 1509 1510 /* This ugly hack is to support the floating pt opcodes in their 1511 standard form. Essentially, we fake a first enty of type COP#1 */ 1512 if (opcode->m_operands[0] == 'I') 1513 { 1514 int n; 1515 1516 for (n = opsfound; n > 0; --n) 1517 the_ins.operands[n] = the_ins.operands[n - 1]; 1518 1519 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0])); 1520 the_ins.operands[0].mode = CONTROL; 1521 the_ins.operands[0].reg = m68k_float_copnum; 1522 opsfound++; 1523 } 1524 1525 /* We've got the operands. Find an opcode that'll accept them. */ 1526 for (losing = 0;;) 1527 { 1528 /* If we didn't get the right number of ops, or we have no 1529 common model with this pattern then reject this pattern. */ 1530 1531 ok_arch |= opcode->m_arch; 1532 if (opsfound != opcode->m_opnum 1533 || ((opcode->m_arch & current_architecture) == 0)) 1534 ++losing; 1535 else 1536 { 1537 int i; 1538 1539 /* Make a copy of the operands of this insn so that 1540 we can modify them safely, should we want to. */ 1541 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup)); 1542 for (i = 0; i < opsfound; i++) 1543 operands_backup[i] = the_ins.operands[i]; 1544 1545 for (s = opcode->m_operands, opP = &operands_backup[0]; 1546 *s && !losing; 1547 s += 2, opP++) 1548 { 1549 /* Warning: this switch is huge! */ 1550 /* I've tried to organize the cases into this order: 1551 non-alpha first, then alpha by letter. Lower-case 1552 goes directly before uppercase counterpart. */ 1553 /* Code with multiple case ...: gets sorted by the lowest 1554 case ... it belongs to. I hope this makes sense. */ 1555 switch (*s) 1556 { 1557 case '!': 1558 switch (opP->mode) 1559 { 1560 case IMMED: 1561 case DREG: 1562 case AREG: 1563 case FPREG: 1564 case CONTROL: 1565 case AINC: 1566 case ADEC: 1567 case REGLST: 1568 losing++; 1569 break; 1570 default: 1571 break; 1572 } 1573 break; 1574 1575 case '<': 1576 switch (opP->mode) 1577 { 1578 case DREG: 1579 case AREG: 1580 case FPREG: 1581 case CONTROL: 1582 case IMMED: 1583 case ADEC: 1584 case REGLST: 1585 losing++; 1586 break; 1587 default: 1588 break; 1589 } 1590 break; 1591 1592 case '>': 1593 switch (opP->mode) 1594 { 1595 case DREG: 1596 case AREG: 1597 case FPREG: 1598 case CONTROL: 1599 case IMMED: 1600 case AINC: 1601 case REGLST: 1602 losing++; 1603 break; 1604 case ABSL: 1605 break; 1606 default: 1607 if (opP->reg == PC 1608 || opP->reg == ZPC) 1609 losing++; 1610 break; 1611 } 1612 break; 1613 1614 case 'm': 1615 switch (opP->mode) 1616 { 1617 case DREG: 1618 case AREG: 1619 case AINDR: 1620 case AINC: 1621 case ADEC: 1622 break; 1623 default: 1624 losing++; 1625 } 1626 break; 1627 1628 case 'n': 1629 switch (opP->mode) 1630 { 1631 case DISP: 1632 break; 1633 default: 1634 losing++; 1635 } 1636 break; 1637 1638 case 'o': 1639 switch (opP->mode) 1640 { 1641 case BASE: 1642 case ABSL: 1643 case IMMED: 1644 break; 1645 default: 1646 losing++; 1647 } 1648 break; 1649 1650 case 'p': 1651 switch (opP->mode) 1652 { 1653 case DREG: 1654 case AREG: 1655 case AINDR: 1656 case AINC: 1657 case ADEC: 1658 break; 1659 case DISP: 1660 if (opP->reg == PC || opP->reg == ZPC) 1661 losing++; 1662 break; 1663 default: 1664 losing++; 1665 } 1666 break; 1667 1668 case 'q': 1669 switch (opP->mode) 1670 { 1671 case DREG: 1672 case AINDR: 1673 case AINC: 1674 case ADEC: 1675 break; 1676 case DISP: 1677 if (opP->reg == PC || opP->reg == ZPC) 1678 losing++; 1679 break; 1680 default: 1681 losing++; 1682 break; 1683 } 1684 break; 1685 1686 case 'v': 1687 switch (opP->mode) 1688 { 1689 case DREG: 1690 case AINDR: 1691 case AINC: 1692 case ADEC: 1693 case ABSL: 1694 break; 1695 case DISP: 1696 if (opP->reg == PC || opP->reg == ZPC) 1697 losing++; 1698 break; 1699 default: 1700 losing++; 1701 break; 1702 } 1703 break; 1704 1705 case '#': 1706 if (opP->mode != IMMED) 1707 losing++; 1708 else if (s[1] == 'b' 1709 && ! isvar (&opP->disp) 1710 && (opP->disp.exp.X_op != O_constant 1711 || ! isbyte (opP->disp.exp.X_add_number))) 1712 losing++; 1713 else if (s[1] == 'B' 1714 && ! isvar (&opP->disp) 1715 && (opP->disp.exp.X_op != O_constant 1716 || ! issbyte (opP->disp.exp.X_add_number))) 1717 losing++; 1718 else if (s[1] == 'w' 1719 && ! isvar (&opP->disp) 1720 && (opP->disp.exp.X_op != O_constant 1721 || ! isword (opP->disp.exp.X_add_number))) 1722 losing++; 1723 else if (s[1] == 'W' 1724 && ! isvar (&opP->disp) 1725 && (opP->disp.exp.X_op != O_constant 1726 || ! issword (opP->disp.exp.X_add_number))) 1727 losing++; 1728 break; 1729 1730 case '^': 1731 case 'T': 1732 if (opP->mode != IMMED) 1733 losing++; 1734 break; 1735 1736 case '$': 1737 if (opP->mode == AREG 1738 || opP->mode == CONTROL 1739 || opP->mode == FPREG 1740 || opP->mode == IMMED 1741 || opP->mode == REGLST 1742 || (opP->mode != ABSL 1743 && (opP->reg == PC 1744 || opP->reg == ZPC))) 1745 losing++; 1746 break; 1747 1748 case '%': 1749 if (opP->mode == CONTROL 1750 || opP->mode == FPREG 1751 || opP->mode == REGLST 1752 || opP->mode == IMMED 1753 || (opP->mode != ABSL 1754 && (opP->reg == PC 1755 || opP->reg == ZPC))) 1756 losing++; 1757 break; 1758 1759 case '&': 1760 switch (opP->mode) 1761 { 1762 case DREG: 1763 case AREG: 1764 case FPREG: 1765 case CONTROL: 1766 case IMMED: 1767 case AINC: 1768 case ADEC: 1769 case REGLST: 1770 losing++; 1771 break; 1772 case ABSL: 1773 break; 1774 default: 1775 if (opP->reg == PC 1776 || opP->reg == ZPC) 1777 losing++; 1778 break; 1779 } 1780 break; 1781 1782 case '*': 1783 if (opP->mode == CONTROL 1784 || opP->mode == FPREG 1785 || opP->mode == REGLST) 1786 losing++; 1787 break; 1788 1789 case '+': 1790 if (opP->mode != AINC) 1791 losing++; 1792 break; 1793 1794 case '-': 1795 if (opP->mode != ADEC) 1796 losing++; 1797 break; 1798 1799 case '/': 1800 switch (opP->mode) 1801 { 1802 case AREG: 1803 case CONTROL: 1804 case FPREG: 1805 case AINC: 1806 case ADEC: 1807 case IMMED: 1808 case REGLST: 1809 losing++; 1810 break; 1811 default: 1812 break; 1813 } 1814 break; 1815 1816 case ';': 1817 switch (opP->mode) 1818 { 1819 case AREG: 1820 case CONTROL: 1821 case FPREG: 1822 case REGLST: 1823 losing++; 1824 break; 1825 default: 1826 break; 1827 } 1828 break; 1829 1830 case '?': 1831 switch (opP->mode) 1832 { 1833 case AREG: 1834 case CONTROL: 1835 case FPREG: 1836 case AINC: 1837 case ADEC: 1838 case IMMED: 1839 case REGLST: 1840 losing++; 1841 break; 1842 case ABSL: 1843 break; 1844 default: 1845 if (opP->reg == PC || opP->reg == ZPC) 1846 losing++; 1847 break; 1848 } 1849 break; 1850 1851 case '@': 1852 switch (opP->mode) 1853 { 1854 case AREG: 1855 case CONTROL: 1856 case FPREG: 1857 case IMMED: 1858 case REGLST: 1859 losing++; 1860 break; 1861 default: 1862 break; 1863 } 1864 break; 1865 1866 case '~': /* For now! (JF FOO is this right?) */ 1867 switch (opP->mode) 1868 { 1869 case DREG: 1870 case AREG: 1871 case CONTROL: 1872 case FPREG: 1873 case IMMED: 1874 case REGLST: 1875 losing++; 1876 break; 1877 case ABSL: 1878 break; 1879 default: 1880 if (opP->reg == PC 1881 || opP->reg == ZPC) 1882 losing++; 1883 break; 1884 } 1885 break; 1886 1887 case '3': 1888 if (opP->mode != CONTROL 1889 || (opP->reg != TT0 && opP->reg != TT1)) 1890 losing++; 1891 break; 1892 1893 case 'A': 1894 if (opP->mode != AREG) 1895 losing++; 1896 break; 1897 1898 case 'a': 1899 if (opP->mode != AINDR) 1900 ++losing; 1901 break; 1902 1903 case '4': 1904 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC 1905 && (opP->mode != DISP 1906 || opP->reg < ADDR0 1907 || opP->reg > ADDR7)) 1908 ++losing; 1909 break; 1910 1911 case 'B': /* FOO */ 1912 if (opP->mode != ABSL 1913 || (flag_long_jumps 1914 && strncmp (instring, "jbsr", 4) == 0)) 1915 losing++; 1916 break; 1917 1918 case 'b': 1919 switch (opP->mode) 1920 { 1921 case IMMED: 1922 case ABSL: 1923 case AREG: 1924 case FPREG: 1925 case CONTROL: 1926 case POST: 1927 case PRE: 1928 case REGLST: 1929 losing++; 1930 break; 1931 default: 1932 break; 1933 } 1934 break; 1935 1936 case 'C': 1937 if (opP->mode != CONTROL || opP->reg != CCR) 1938 losing++; 1939 break; 1940 1941 case 'd': 1942 if (opP->mode != DISP 1943 || opP->reg < ADDR0 1944 || opP->reg > ADDR7) 1945 losing++; 1946 break; 1947 1948 case 'D': 1949 if (opP->mode != DREG) 1950 losing++; 1951 break; 1952 1953 case 'E': 1954 if (opP->reg != ACC) 1955 losing++; 1956 break; 1957 1958 case 'e': 1959 if (opP->reg != ACC && opP->reg != ACC1 1960 && opP->reg != ACC2 && opP->reg != ACC3) 1961 losing++; 1962 break; 1963 1964 case 'F': 1965 if (opP->mode != FPREG) 1966 losing++; 1967 break; 1968 1969 case 'G': 1970 if (opP->reg != MACSR) 1971 losing++; 1972 break; 1973 1974 case 'g': 1975 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) 1976 losing++; 1977 break; 1978 1979 case 'H': 1980 if (opP->reg != MASK) 1981 losing++; 1982 break; 1983 1984 case 'I': 1985 if (opP->mode != CONTROL 1986 || opP->reg < COP0 1987 || opP->reg > COP7) 1988 losing++; 1989 break; 1990 1991 case 'i': 1992 if (opP->mode != LSH && opP->mode != RSH) 1993 losing++; 1994 break; 1995 1996 case 'J': 1997 if (opP->mode != CONTROL 1998 || opP->reg < USP 1999 || opP->reg > last_movec_reg 2000 || !control_regs) 2001 losing++; 2002 else 2003 { 2004 const enum m68k_register *rp; 2005 2006 for (rp = control_regs; *rp; rp++) 2007 { 2008 if (*rp == opP->reg) 2009 break; 2010 /* In most CPUs RAMBAR refers to control reg 2011 c05 (RAMBAR1), but a few CPUs have it 2012 refer to c04 (RAMBAR0). */ 2013 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR) 2014 { 2015 opP->reg = RAMBAR_ALT; 2016 break; 2017 } 2018 } 2019 if (*rp == 0) 2020 losing++; 2021 } 2022 break; 2023 2024 case 'k': 2025 if (opP->mode != IMMED) 2026 losing++; 2027 break; 2028 2029 case 'l': 2030 case 'L': 2031 if (opP->mode == DREG 2032 || opP->mode == AREG 2033 || opP->mode == FPREG) 2034 { 2035 if (s[1] == '8') 2036 losing++; 2037 else 2038 { 2039 switch (opP->mode) 2040 { 2041 case DREG: 2042 opP->mask = 1 << (opP->reg - DATA0); 2043 break; 2044 case AREG: 2045 opP->mask = 1 << (opP->reg - ADDR0 + 8); 2046 break; 2047 case FPREG: 2048 opP->mask = 1 << (opP->reg - FP0 + 16); 2049 break; 2050 default: 2051 abort (); 2052 } 2053 opP->mode = REGLST; 2054 } 2055 } 2056 else if (opP->mode == CONTROL) 2057 { 2058 if (s[1] != '8') 2059 losing++; 2060 else 2061 { 2062 switch (opP->reg) 2063 { 2064 case FPI: 2065 opP->mask = 1 << 24; 2066 break; 2067 case FPS: 2068 opP->mask = 1 << 25; 2069 break; 2070 case FPC: 2071 opP->mask = 1 << 26; 2072 break; 2073 default: 2074 losing++; 2075 break; 2076 } 2077 opP->mode = REGLST; 2078 } 2079 } 2080 else if (opP->mode != REGLST) 2081 losing++; 2082 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0) 2083 losing++; 2084 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0) 2085 losing++; 2086 break; 2087 2088 case 'M': 2089 if (opP->mode != IMMED) 2090 losing++; 2091 else if (opP->disp.exp.X_op != O_constant 2092 || ! issbyte (opP->disp.exp.X_add_number)) 2093 losing++; 2094 else if (! m68k_quick 2095 && instring[3] != 'q' 2096 && instring[4] != 'q') 2097 losing++; 2098 break; 2099 2100 case 'O': 2101 if (opP->mode != DREG 2102 && opP->mode != IMMED 2103 && opP->mode != ABSL) 2104 losing++; 2105 break; 2106 2107 case 'Q': 2108 if (opP->mode != IMMED) 2109 losing++; 2110 else if (opP->disp.exp.X_op != O_constant 2111 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2112 losing++; 2113 else if (! m68k_quick 2114 && (strncmp (instring, "add", 3) == 0 2115 || strncmp (instring, "sub", 3) == 0) 2116 && instring[3] != 'q') 2117 losing++; 2118 break; 2119 2120 case 'R': 2121 if (opP->mode != DREG && opP->mode != AREG) 2122 losing++; 2123 break; 2124 2125 case 'r': 2126 if (opP->mode != AINDR 2127 && (opP->mode != BASE 2128 || (opP->reg != 0 2129 && opP->reg != ZADDR0) 2130 || opP->disp.exp.X_op != O_absent 2131 || ((opP->index.reg < DATA0 2132 || opP->index.reg > DATA7) 2133 && (opP->index.reg < ADDR0 2134 || opP->index.reg > ADDR7)) 2135 || opP->index.size != SIZE_UNSPEC 2136 || opP->index.scale != 1)) 2137 losing++; 2138 break; 2139 2140 case 's': 2141 if (opP->mode != CONTROL 2142 || ! (opP->reg == FPI 2143 || opP->reg == FPS 2144 || opP->reg == FPC)) 2145 losing++; 2146 break; 2147 2148 case 'S': 2149 if (opP->mode != CONTROL || opP->reg != SR) 2150 losing++; 2151 break; 2152 2153 case 't': 2154 if (opP->mode != IMMED) 2155 losing++; 2156 else if (opP->disp.exp.X_op != O_constant 2157 || TRUNC (opP->disp.exp.X_add_number) > 7) 2158 losing++; 2159 break; 2160 2161 case 'U': 2162 if (opP->mode != CONTROL || opP->reg != USP) 2163 losing++; 2164 break; 2165 2166 case 'x': 2167 if (opP->mode != IMMED) 2168 losing++; 2169 else if (opP->disp.exp.X_op != O_constant 2170 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff 2171 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6)) 2172 losing++; 2173 break; 2174 2175 case 'j': 2176 if (opP->mode != IMMED) 2177 losing++; 2178 else if (opP->disp.exp.X_op != O_constant 2179 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7) 2180 losing++; 2181 break; 2182 2183 case 'K': 2184 if (opP->mode != IMMED) 2185 losing++; 2186 else if (opP->disp.exp.X_op != O_constant 2187 || TRUNC (opP->disp.exp.X_add_number) > 511) 2188 losing++; 2189 break; 2190 2191 /* JF these are out of order. We could put them 2192 in order if we were willing to put up with 2193 bunches of #ifdef m68851s in the code. 2194 2195 Don't forget that you need these operands 2196 to use 68030 MMU instructions. */ 2197 #ifndef NO_68851 2198 /* Memory addressing mode used by pflushr. */ 2199 case '|': 2200 if (opP->mode == CONTROL 2201 || opP->mode == FPREG 2202 || opP->mode == DREG 2203 || opP->mode == AREG 2204 || opP->mode == REGLST) 2205 losing++; 2206 /* We should accept immediate operands, but they 2207 supposedly have to be quad word, and we don't 2208 handle that. I would like to see what a Motorola 2209 assembler does before doing something here. */ 2210 if (opP->mode == IMMED) 2211 losing++; 2212 break; 2213 2214 case 'f': 2215 if (opP->mode != CONTROL 2216 || (opP->reg != SFC && opP->reg != DFC)) 2217 losing++; 2218 break; 2219 2220 case '0': 2221 if (opP->mode != CONTROL || opP->reg != TC) 2222 losing++; 2223 break; 2224 2225 case '1': 2226 if (opP->mode != CONTROL || opP->reg != AC) 2227 losing++; 2228 break; 2229 2230 case '2': 2231 if (opP->mode != CONTROL 2232 || (opP->reg != CAL 2233 && opP->reg != VAL 2234 && opP->reg != SCC)) 2235 losing++; 2236 break; 2237 2238 case 'V': 2239 if (opP->mode != CONTROL 2240 || opP->reg != VAL) 2241 losing++; 2242 break; 2243 2244 case 'W': 2245 if (opP->mode != CONTROL 2246 || (opP->reg != DRP 2247 && opP->reg != SRP 2248 && opP->reg != CRP)) 2249 losing++; 2250 break; 2251 2252 case 'w': 2253 switch (opP->mode) 2254 { 2255 case IMMED: 2256 case ABSL: 2257 case AREG: 2258 case DREG: 2259 case FPREG: 2260 case CONTROL: 2261 case POST: 2262 case PRE: 2263 case REGLST: 2264 losing++; 2265 break; 2266 default: 2267 break; 2268 } 2269 break; 2270 2271 case 'X': 2272 if (opP->mode != CONTROL 2273 || (!(opP->reg >= BAD && opP->reg <= BAD + 7) 2274 && !(opP->reg >= BAC && opP->reg <= BAC + 7))) 2275 losing++; 2276 break; 2277 2278 case 'Y': 2279 if (opP->mode != CONTROL || opP->reg != PSR) 2280 losing++; 2281 break; 2282 2283 case 'Z': 2284 if (opP->mode != CONTROL || opP->reg != PCSR) 2285 losing++; 2286 break; 2287 #endif 2288 case 'c': 2289 if (opP->mode != CONTROL 2290 || (opP->reg != NC 2291 && opP->reg != IC 2292 && opP->reg != DC 2293 && opP->reg != BC)) 2294 losing++; 2295 break; 2296 2297 case '_': 2298 if (opP->mode != ABSL) 2299 ++losing; 2300 break; 2301 2302 case 'u': 2303 if (opP->reg < DATA0L || opP->reg > ADDR7U) 2304 losing++; 2305 /* FIXME: kludge instead of fixing parser: 2306 upper/lower registers are *not* CONTROL 2307 registers, but ordinary ones. */ 2308 if ((opP->reg >= DATA0L && opP->reg <= DATA7L) 2309 || (opP->reg >= DATA0U && opP->reg <= DATA7U)) 2310 opP->mode = DREG; 2311 else 2312 opP->mode = AREG; 2313 break; 2314 2315 case 'y': 2316 if (!(opP->mode == AINDR 2317 || (opP->mode == DISP 2318 && !(opP->reg == PC || opP->reg == ZPC)))) 2319 losing++; 2320 break; 2321 2322 case 'z': 2323 if (!(opP->mode == AINDR || opP->mode == DISP)) 2324 losing++; 2325 break; 2326 2327 default: 2328 abort (); 2329 } 2330 2331 if (losing) 2332 break; 2333 } 2334 2335 /* Since we have found the correct instruction, copy 2336 in the modifications that we may have made. */ 2337 if (!losing) 2338 for (i = 0; i < opsfound; i++) 2339 the_ins.operands[i] = operands_backup[i]; 2340 } 2341 2342 if (!losing) 2343 break; 2344 2345 opcode = opcode->m_next; 2346 2347 if (!opcode) 2348 { 2349 if (ok_arch 2350 && !(ok_arch & current_architecture)) 2351 { 2352 const struct m68k_cpu *cpu; 2353 int any = 0; 2354 size_t space = 400; 2355 char *buf = xmalloc (space + 1); 2356 size_t len; 2357 int paren = 1; 2358 2359 the_ins.error = buf; 2360 /* Make sure there's a NUL at the end of the buffer -- strncpy 2361 won't write one when it runs out of buffer. */ 2362 buf[space] = 0; 2363 #define APPEND(STRING) \ 2364 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len) 2365 2366 APPEND (_("invalid instruction for this architecture; needs ")); 2367 switch (ok_arch) 2368 { 2369 case mcfisa_a: 2370 APPEND ("ColdFire ISA_A"); 2371 break; 2372 case mcfhwdiv: 2373 APPEND ("ColdFire "); 2374 APPEND (_("hardware divide")); 2375 break; 2376 case mcfisa_aa: 2377 APPEND ("ColdFire ISA_A+"); 2378 break; 2379 case mcfisa_b: 2380 APPEND ("ColdFire ISA_B"); 2381 break; 2382 case mcfisa_c: 2383 APPEND ("ColdFire ISA_C"); 2384 break; 2385 case cfloat: 2386 APPEND ("ColdFire fpu"); 2387 break; 2388 case mfloat: 2389 APPEND ("M68K fpu"); 2390 break; 2391 case mmmu: 2392 APPEND ("M68K mmu"); 2393 break; 2394 case m68020up: 2395 APPEND ("68020 "); 2396 APPEND (_("or higher")); 2397 break; 2398 case m68000up: 2399 APPEND ("68000 "); 2400 APPEND (_("or higher")); 2401 break; 2402 case m68010up: 2403 APPEND ("68010 "); 2404 APPEND (_("or higher")); 2405 break; 2406 default: 2407 paren = 0; 2408 } 2409 if (paren) 2410 APPEND (" ("); 2411 2412 for (cpu = m68k_cpus; cpu->name; cpu++) 2413 if (!cpu->alias && (cpu->arch & ok_arch)) 2414 { 2415 const struct m68k_cpu *alias; 2416 int seen_master = 0; 2417 2418 if (any) 2419 APPEND (", "); 2420 any = 0; 2421 APPEND (cpu->name); 2422 for (alias = cpu; alias != m68k_cpus; alias--) 2423 if (alias[-1].alias >= 0) 2424 break; 2425 for (; !seen_master || alias->alias > 0; alias++) 2426 { 2427 if (!alias->alias) 2428 seen_master = 1; 2429 else 2430 { 2431 if (any) 2432 APPEND (", "); 2433 else 2434 APPEND (" ["); 2435 APPEND (alias->name); 2436 any = 1; 2437 } 2438 } 2439 if (any) 2440 APPEND ("]"); 2441 any = 1; 2442 } 2443 if (paren) 2444 APPEND (")"); 2445 #undef APPEND 2446 if (!space) 2447 { 2448 /* We ran out of space, so replace the end of the list 2449 with ellipsis. */ 2450 buf -= 4; 2451 while (*buf != ' ') 2452 buf--; 2453 strcpy (buf, " ..."); 2454 } 2455 } 2456 else 2457 the_ins.error = _("operands mismatch"); 2458 return; 2459 } 2460 2461 losing = 0; 2462 } 2463 2464 /* Now assemble it. */ 2465 the_ins.args = opcode->m_operands; 2466 the_ins.numargs = opcode->m_opnum; 2467 the_ins.numo = opcode->m_codenum; 2468 the_ins.opcode[0] = getone (opcode); 2469 the_ins.opcode[1] = gettwo (opcode); 2470 2471 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++) 2472 { 2473 int have_disp = 0; 2474 int use_pl = 0; 2475 2476 /* This switch is a doozy. 2477 Watch the first step; its a big one! */ 2478 switch (s[0]) 2479 { 2480 2481 case '*': 2482 case '~': 2483 case '%': 2484 case ';': 2485 case '@': 2486 case '!': 2487 case '&': 2488 case '$': 2489 case '?': 2490 case '/': 2491 case '<': 2492 case '>': 2493 case 'b': 2494 case 'm': 2495 case 'n': 2496 case 'o': 2497 case 'p': 2498 case 'q': 2499 case 'v': 2500 case 'w': 2501 case 'y': 2502 case 'z': 2503 case '4': 2504 #ifndef NO_68851 2505 case '|': 2506 #endif 2507 switch (opP->mode) 2508 { 2509 case IMMED: 2510 tmpreg = 0x3c; /* 7.4 */ 2511 if (strchr ("bwl", s[1])) 2512 nextword = get_num (&opP->disp, 90); 2513 else 2514 nextword = get_num (&opP->disp, 0); 2515 if (isvar (&opP->disp)) 2516 add_fix (s[1], &opP->disp, 0, 0); 2517 switch (s[1]) 2518 { 2519 case 'b': 2520 if (!isbyte (nextword)) 2521 opP->error = _("operand out of range"); 2522 addword (nextword); 2523 baseo = 0; 2524 break; 2525 case 'w': 2526 if (!isword (nextword)) 2527 opP->error = _("operand out of range"); 2528 addword (nextword); 2529 baseo = 0; 2530 break; 2531 case 'W': 2532 if (!issword (nextword)) 2533 opP->error = _("operand out of range"); 2534 addword (nextword); 2535 baseo = 0; 2536 break; 2537 case 'l': 2538 addword (nextword >> 16); 2539 addword (nextword); 2540 baseo = 0; 2541 break; 2542 2543 case 'f': 2544 baseo = 2; 2545 outro = 8; 2546 break; 2547 case 'F': 2548 baseo = 4; 2549 outro = 11; 2550 break; 2551 case 'x': 2552 baseo = 6; 2553 outro = 15; 2554 break; 2555 case 'p': 2556 baseo = 6; 2557 outro = -1; 2558 break; 2559 default: 2560 abort (); 2561 } 2562 if (!baseo) 2563 break; 2564 2565 /* We gotta put out some float. */ 2566 if (op (&opP->disp) != O_big) 2567 { 2568 valueT val; 2569 int gencnt; 2570 2571 /* Can other cases happen here? */ 2572 if (op (&opP->disp) != O_constant) 2573 abort (); 2574 2575 val = (valueT) offs (&opP->disp); 2576 gencnt = 0; 2577 do 2578 { 2579 generic_bignum[gencnt] = (LITTLENUM_TYPE) val; 2580 val >>= LITTLENUM_NUMBER_OF_BITS; 2581 ++gencnt; 2582 } 2583 while (val != 0); 2584 offs (&opP->disp) = gencnt; 2585 } 2586 if (offs (&opP->disp) > 0) 2587 { 2588 if (offs (&opP->disp) > baseo) 2589 { 2590 as_warn (_("Bignum too big for %c format; truncated"), 2591 s[1]); 2592 offs (&opP->disp) = baseo; 2593 } 2594 baseo -= offs (&opP->disp); 2595 while (baseo--) 2596 addword (0); 2597 for (wordp = generic_bignum + offs (&opP->disp) - 1; 2598 offs (&opP->disp)--; 2599 --wordp) 2600 addword (*wordp); 2601 break; 2602 } 2603 gen_to_words (words, baseo, (long) outro); 2604 for (wordp = words; baseo--; wordp++) 2605 addword (*wordp); 2606 break; 2607 case DREG: 2608 tmpreg = opP->reg - DATA; /* 0.dreg */ 2609 break; 2610 case AREG: 2611 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */ 2612 break; 2613 case AINDR: 2614 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2615 break; 2616 case ADEC: 2617 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */ 2618 break; 2619 case AINC: 2620 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */ 2621 break; 2622 case DISP: 2623 2624 nextword = get_num (&opP->disp, 90); 2625 2626 /* Convert mode 5 addressing with a zero offset into 2627 mode 2 addressing to reduce the instruction size by a 2628 word. */ 2629 if (! isvar (&opP->disp) 2630 && (nextword == 0) 2631 && (opP->disp.size == SIZE_UNSPEC) 2632 && (opP->reg >= ADDR0) 2633 && (opP->reg <= ADDR7)) 2634 { 2635 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */ 2636 break; 2637 } 2638 2639 if (opP->reg == PC 2640 && ! isvar (&opP->disp) 2641 && m68k_abspcadd) 2642 { 2643 opP->disp.exp.X_op = O_symbol; 2644 opP->disp.exp.X_add_symbol = 2645 section_symbol (absolute_section); 2646 } 2647 2648 /* Force into index mode. Hope this works. */ 2649 2650 /* We do the first bit for 32-bit displacements, and the 2651 second bit for 16 bit ones. It is possible that we 2652 should make the default be WORD instead of LONG, but 2653 I think that'd break GCC, so we put up with a little 2654 inefficiency for the sake of working output. */ 2655 2656 if (!issword (nextword) 2657 || (isvar (&opP->disp) 2658 && ((opP->disp.size == SIZE_UNSPEC 2659 && flag_short_refs == 0 2660 && cpu_of_arch (current_architecture) >= m68020 2661 && ! arch_coldfire_p (current_architecture)) 2662 || opP->disp.size == SIZE_LONG))) 2663 { 2664 if (cpu_of_arch (current_architecture) < m68020 2665 || arch_coldfire_p (current_architecture)) 2666 opP->error = 2667 _("displacement too large for this architecture; needs 68020 or higher"); 2668 if (opP->reg == PC) 2669 tmpreg = 0x3B; /* 7.3 */ 2670 else 2671 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2672 if (isvar (&opP->disp)) 2673 { 2674 if (opP->reg == PC) 2675 { 2676 if (opP->disp.size == SIZE_LONG 2677 #ifdef OBJ_ELF 2678 /* If the displacement needs pic 2679 relocation it cannot be relaxed. */ 2680 || opP->disp.pic_reloc != pic_none 2681 #endif 2682 ) 2683 { 2684 addword (0x0170); 2685 add_fix ('l', &opP->disp, 1, 2); 2686 } 2687 else 2688 { 2689 add_frag (adds (&opP->disp), 2690 SEXT (offs (&opP->disp)), 2691 TAB (PCREL1632, SZ_UNDEF)); 2692 break; 2693 } 2694 } 2695 else 2696 { 2697 addword (0x0170); 2698 add_fix ('l', &opP->disp, 0, 0); 2699 } 2700 } 2701 else 2702 addword (0x0170); 2703 addword (nextword >> 16); 2704 } 2705 else 2706 { 2707 if (opP->reg == PC) 2708 tmpreg = 0x3A; /* 7.2 */ 2709 else 2710 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */ 2711 2712 if (isvar (&opP->disp)) 2713 { 2714 if (opP->reg == PC) 2715 { 2716 add_fix ('w', &opP->disp, 1, 0); 2717 } 2718 else 2719 add_fix ('w', &opP->disp, 0, 0); 2720 } 2721 } 2722 addword (nextword); 2723 break; 2724 2725 case POST: 2726 case PRE: 2727 case BASE: 2728 nextword = 0; 2729 baseo = get_num (&opP->disp, 90); 2730 if (opP->mode == POST || opP->mode == PRE) 2731 outro = get_num (&opP->odisp, 90); 2732 /* Figure out the `addressing mode'. 2733 Also turn on the BASE_DISABLE bit, if needed. */ 2734 if (opP->reg == PC || opP->reg == ZPC) 2735 { 2736 tmpreg = 0x3b; /* 7.3 */ 2737 if (opP->reg == ZPC) 2738 nextword |= 0x80; 2739 } 2740 else if (opP->reg == 0) 2741 { 2742 nextword |= 0x80; 2743 tmpreg = 0x30; /* 6.garbage */ 2744 } 2745 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7) 2746 { 2747 nextword |= 0x80; 2748 tmpreg = 0x30 + opP->reg - ZADDR0; 2749 } 2750 else 2751 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */ 2752 2753 siz1 = opP->disp.size; 2754 if (opP->mode == POST || opP->mode == PRE) 2755 siz2 = opP->odisp.size; 2756 else 2757 siz2 = SIZE_UNSPEC; 2758 2759 /* Index register stuff. */ 2760 if (opP->index.reg != 0 2761 && opP->index.reg >= DATA 2762 && opP->index.reg <= ADDR7) 2763 { 2764 nextword |= (opP->index.reg - DATA) << 12; 2765 2766 if (opP->index.size == SIZE_LONG 2767 || (opP->index.size == SIZE_UNSPEC 2768 && m68k_index_width_default == SIZE_LONG)) 2769 nextword |= 0x800; 2770 2771 if ((opP->index.scale != 1 2772 && cpu_of_arch (current_architecture) < m68020) 2773 || (opP->index.scale == 8 2774 && (arch_coldfire_p (current_architecture) 2775 && !arch_coldfire_fpu (current_architecture)))) 2776 { 2777 opP->error = 2778 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); 2779 } 2780 2781 if (arch_coldfire_p (current_architecture) 2782 && opP->index.size == SIZE_WORD) 2783 opP->error = _("invalid index size for coldfire"); 2784 2785 switch (opP->index.scale) 2786 { 2787 case 1: 2788 break; 2789 case 2: 2790 nextword |= 0x200; 2791 break; 2792 case 4: 2793 nextword |= 0x400; 2794 break; 2795 case 8: 2796 nextword |= 0x600; 2797 break; 2798 default: 2799 abort (); 2800 } 2801 /* IF its simple, 2802 GET US OUT OF HERE! */ 2803 2804 /* Must be INDEX, with an index register. Address 2805 register cannot be ZERO-PC, and either :b was 2806 forced, or we know it will fit. For a 68000 or 2807 68010, force this mode anyways, because the 2808 larger modes aren't supported. */ 2809 if (opP->mode == BASE 2810 && ((opP->reg >= ADDR0 2811 && opP->reg <= ADDR7) 2812 || opP->reg == PC)) 2813 { 2814 if (siz1 == SIZE_BYTE 2815 || cpu_of_arch (current_architecture) < m68020 2816 || arch_coldfire_p (current_architecture) 2817 || (siz1 == SIZE_UNSPEC 2818 && ! isvar (&opP->disp) 2819 && issbyte (baseo))) 2820 { 2821 nextword += baseo & 0xff; 2822 addword (nextword); 2823 if (isvar (&opP->disp)) 2824 { 2825 /* Do a byte relocation. If it doesn't 2826 fit (possible on m68000) let the 2827 fixup processing complain later. */ 2828 if (opP->reg == PC) 2829 add_fix ('B', &opP->disp, 1, 1); 2830 else 2831 add_fix ('B', &opP->disp, 0, 0); 2832 } 2833 else if (siz1 != SIZE_BYTE) 2834 { 2835 if (siz1 != SIZE_UNSPEC) 2836 as_warn (_("Forcing byte displacement")); 2837 if (! issbyte (baseo)) 2838 opP->error = _("byte displacement out of range"); 2839 } 2840 2841 break; 2842 } 2843 else if (siz1 == SIZE_UNSPEC 2844 && opP->reg == PC 2845 && isvar (&opP->disp) 2846 && subs (&opP->disp) == NULL 2847 #ifdef OBJ_ELF 2848 /* If the displacement needs pic 2849 relocation it cannot be relaxed. */ 2850 && opP->disp.pic_reloc == pic_none 2851 #endif 2852 ) 2853 { 2854 /* The code in md_convert_frag_1 needs to be 2855 able to adjust nextword. Call frag_grow 2856 to ensure that we have enough space in 2857 the frag obstack to make all the bytes 2858 contiguous. */ 2859 frag_grow (14); 2860 nextword += baseo & 0xff; 2861 addword (nextword); 2862 add_frag (adds (&opP->disp), 2863 SEXT (offs (&opP->disp)), 2864 TAB (PCINDEX, SZ_UNDEF)); 2865 2866 break; 2867 } 2868 } 2869 } 2870 else 2871 { 2872 nextword |= 0x40; /* No index reg. */ 2873 if (opP->index.reg >= ZDATA0 2874 && opP->index.reg <= ZDATA7) 2875 nextword |= (opP->index.reg - ZDATA0) << 12; 2876 else if (opP->index.reg >= ZADDR0 2877 || opP->index.reg <= ZADDR7) 2878 nextword |= (opP->index.reg - ZADDR0 + 8) << 12; 2879 } 2880 2881 /* It isn't simple. */ 2882 2883 if (cpu_of_arch (current_architecture) < m68020 2884 || arch_coldfire_p (current_architecture)) 2885 opP->error = 2886 _("invalid operand mode for this architecture; needs 68020 or higher"); 2887 2888 nextword |= 0x100; 2889 /* If the guy specified a width, we assume that it is 2890 wide enough. Maybe it isn't. If so, we lose. */ 2891 switch (siz1) 2892 { 2893 case SIZE_UNSPEC: 2894 if (isvar (&opP->disp) 2895 ? m68k_rel32 2896 : ! issword (baseo)) 2897 { 2898 siz1 = SIZE_LONG; 2899 nextword |= 0x30; 2900 } 2901 else if (! isvar (&opP->disp) && baseo == 0) 2902 nextword |= 0x10; 2903 else 2904 { 2905 nextword |= 0x20; 2906 siz1 = SIZE_WORD; 2907 } 2908 break; 2909 case SIZE_BYTE: 2910 as_warn (_(":b not permitted; defaulting to :w")); 2911 /* Fall through. */ 2912 case SIZE_WORD: 2913 nextword |= 0x20; 2914 break; 2915 case SIZE_LONG: 2916 nextword |= 0x30; 2917 break; 2918 } 2919 2920 /* Figure out inner displacement stuff. */ 2921 if (opP->mode == POST || opP->mode == PRE) 2922 { 2923 if (cpu_of_arch (current_architecture) & cpu32) 2924 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher"); 2925 switch (siz2) 2926 { 2927 case SIZE_UNSPEC: 2928 if (isvar (&opP->odisp) 2929 ? m68k_rel32 2930 : ! issword (outro)) 2931 { 2932 siz2 = SIZE_LONG; 2933 nextword |= 0x3; 2934 } 2935 else if (! isvar (&opP->odisp) && outro == 0) 2936 nextword |= 0x1; 2937 else 2938 { 2939 nextword |= 0x2; 2940 siz2 = SIZE_WORD; 2941 } 2942 break; 2943 case 1: 2944 as_warn (_(":b not permitted; defaulting to :w")); 2945 /* Fall through. */ 2946 case 2: 2947 nextword |= 0x2; 2948 break; 2949 case 3: 2950 nextword |= 0x3; 2951 break; 2952 } 2953 if (opP->mode == POST 2954 && (nextword & 0x40) == 0) 2955 nextword |= 0x04; 2956 } 2957 addword (nextword); 2958 2959 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp)) 2960 { 2961 if (opP->reg == PC || opP->reg == ZPC) 2962 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2); 2963 else 2964 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0); 2965 } 2966 if (siz1 == SIZE_LONG) 2967 addword (baseo >> 16); 2968 if (siz1 != SIZE_UNSPEC) 2969 addword (baseo); 2970 2971 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp)) 2972 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0); 2973 if (siz2 == SIZE_LONG) 2974 addword (outro >> 16); 2975 if (siz2 != SIZE_UNSPEC) 2976 addword (outro); 2977 2978 break; 2979 2980 case ABSL: 2981 nextword = get_num (&opP->disp, 90); 2982 switch (opP->disp.size) 2983 { 2984 default: 2985 abort (); 2986 case SIZE_UNSPEC: 2987 if (!isvar (&opP->disp) && issword (offs (&opP->disp))) 2988 { 2989 tmpreg = 0x38; /* 7.0 */ 2990 addword (nextword); 2991 break; 2992 } 2993 if (isvar (&opP->disp) 2994 && !subs (&opP->disp) 2995 && adds (&opP->disp) 2996 #ifdef OBJ_ELF 2997 /* If the displacement needs pic relocation it 2998 cannot be relaxed. */ 2999 && opP->disp.pic_reloc == pic_none 3000 #endif 3001 && !flag_long_jumps 3002 && !strchr ("~%&$?", s[0])) 3003 { 3004 tmpreg = 0x3A; /* 7.2 */ 3005 add_frag (adds (&opP->disp), 3006 SEXT (offs (&opP->disp)), 3007 TAB (ABSTOPCREL, SZ_UNDEF)); 3008 break; 3009 } 3010 /* Fall through into long. */ 3011 case SIZE_LONG: 3012 if (isvar (&opP->disp)) 3013 add_fix ('l', &opP->disp, 0, 0); 3014 3015 tmpreg = 0x39;/* 7.1 mode */ 3016 addword (nextword >> 16); 3017 addword (nextword); 3018 break; 3019 3020 case SIZE_BYTE: 3021 as_bad (_("unsupported byte value; use a different suffix")); 3022 /* Fall through. */ 3023 3024 case SIZE_WORD: 3025 if (isvar (&opP->disp)) 3026 add_fix ('w', &opP->disp, 0, 0); 3027 3028 tmpreg = 0x38;/* 7.0 mode */ 3029 addword (nextword); 3030 break; 3031 } 3032 break; 3033 case CONTROL: 3034 case FPREG: 3035 default: 3036 as_bad (_("unknown/incorrect operand")); 3037 /* abort (); */ 3038 } 3039 3040 /* If s[0] is '4', then this is for the mac instructions 3041 that can have a trailing_ampersand set. If so, set 0x100 3042 bit on tmpreg so install_gen_operand can check for it and 3043 set the appropriate bit (word2, bit 5). */ 3044 if (s[0] == '4') 3045 { 3046 if (opP->trailing_ampersand) 3047 tmpreg |= 0x100; 3048 } 3049 install_gen_operand (s[1], tmpreg); 3050 break; 3051 3052 case '#': 3053 case '^': 3054 switch (s[1]) 3055 { /* JF: I hate floating point! */ 3056 case 'j': 3057 tmpreg = 70; 3058 break; 3059 case '8': 3060 tmpreg = 20; 3061 break; 3062 case 'C': 3063 tmpreg = 50; 3064 break; 3065 case '3': 3066 default: 3067 tmpreg = 90; 3068 break; 3069 } 3070 tmpreg = get_num (&opP->disp, tmpreg); 3071 if (isvar (&opP->disp)) 3072 add_fix (s[1], &opP->disp, 0, 0); 3073 switch (s[1]) 3074 { 3075 case 'b': /* Danger: These do no check for 3076 certain types of overflow. 3077 user beware! */ 3078 if (!isbyte (tmpreg)) 3079 opP->error = _("out of range"); 3080 insop (tmpreg, opcode); 3081 if (isvar (&opP->disp)) 3082 the_ins.reloc[the_ins.nrel - 1].n = 3083 (opcode->m_codenum) * 2 + 1; 3084 break; 3085 case 'B': 3086 if (!issbyte (tmpreg)) 3087 opP->error = _("out of range"); 3088 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff; 3089 if (isvar (&opP->disp)) 3090 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1; 3091 break; 3092 case 'w': 3093 if (!isword (tmpreg)) 3094 opP->error = _("out of range"); 3095 insop (tmpreg, opcode); 3096 if (isvar (&opP->disp)) 3097 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3098 break; 3099 case 'W': 3100 if (!issword (tmpreg)) 3101 opP->error = _("out of range"); 3102 insop (tmpreg, opcode); 3103 if (isvar (&opP->disp)) 3104 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3105 break; 3106 case 'l': 3107 /* Because of the way insop works, we put these two out 3108 backwards. */ 3109 insop (tmpreg, opcode); 3110 insop (tmpreg >> 16, opcode); 3111 if (isvar (&opP->disp)) 3112 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2; 3113 break; 3114 case '3': 3115 tmpreg &= 0xFF; 3116 case '8': 3117 case 'C': 3118 case 'j': 3119 install_operand (s[1], tmpreg); 3120 break; 3121 default: 3122 abort (); 3123 } 3124 break; 3125 3126 case '+': 3127 case '-': 3128 case 'A': 3129 case 'a': 3130 install_operand (s[1], opP->reg - ADDR); 3131 break; 3132 3133 case 'B': 3134 tmpreg = get_num (&opP->disp, 90); 3135 3136 switch (s[1]) 3137 { 3138 case 'B': 3139 add_fix ('B', &opP->disp, 1, -1); 3140 break; 3141 case 'W': 3142 add_fix ('w', &opP->disp, 1, 0); 3143 addword (0); 3144 break; 3145 case 'L': 3146 long_branch: 3147 the_ins.opcode[0] |= 0xff; 3148 add_fix ('l', &opP->disp, 1, 0); 3149 addword (0); 3150 addword (0); 3151 break; 3152 case 'g': /* Conditional branch */ 3153 have_disp = HAVE_LONG_CALL (current_architecture); 3154 goto var_branch; 3155 3156 case 'b': /* Unconditional branch */ 3157 have_disp = HAVE_LONG_BRANCH (current_architecture); 3158 use_pl = LONG_BRANCH_VIA_COND (current_architecture); 3159 goto var_branch; 3160 3161 case 's': /* Unconditional subroutine */ 3162 have_disp = HAVE_LONG_CALL (current_architecture); 3163 3164 var_branch: 3165 if (subs (&opP->disp) /* We can't relax it. */ 3166 #ifdef OBJ_ELF 3167 /* If the displacement needs pic relocation it cannot be 3168 relaxed. */ 3169 || opP->disp.pic_reloc != pic_none 3170 #endif 3171 || 0) 3172 { 3173 if (!have_disp) 3174 as_warn (_("Can't use long branches on this architecture")); 3175 goto long_branch; 3176 } 3177 3178 /* This could either be a symbol, or an absolute 3179 address. If it's an absolute address, turn it into 3180 an absolute jump right here and keep it out of the 3181 relaxer. */ 3182 if (adds (&opP->disp) == 0) 3183 { 3184 if (the_ins.opcode[0] == 0x6000) /* jbra */ 3185 the_ins.opcode[0] = 0x4EF9; 3186 else if (the_ins.opcode[0] == 0x6100) /* jbsr */ 3187 the_ins.opcode[0] = 0x4EB9; 3188 else /* jCC */ 3189 { 3190 the_ins.opcode[0] ^= 0x0100; 3191 the_ins.opcode[0] |= 0x0006; 3192 addword (0x4EF9); 3193 } 3194 add_fix ('l', &opP->disp, 0, 0); 3195 addword (0); 3196 addword (0); 3197 break; 3198 } 3199 3200 /* Now we know it's going into the relaxer. Now figure 3201 out which mode. We try in this order of preference: 3202 long branch, absolute jump, byte/word branches only. */ 3203 if (have_disp) 3204 add_frag (adds (&opP->disp), 3205 SEXT (offs (&opP->disp)), 3206 TAB (BRANCHBWL, SZ_UNDEF)); 3207 else if (! flag_keep_pcrel) 3208 { 3209 if ((the_ins.opcode[0] == 0x6000) 3210 || (the_ins.opcode[0] == 0x6100)) 3211 add_frag (adds (&opP->disp), 3212 SEXT (offs (&opP->disp)), 3213 TAB (BRABSJUNC, SZ_UNDEF)); 3214 else 3215 add_frag (adds (&opP->disp), 3216 SEXT (offs (&opP->disp)), 3217 TAB (BRABSJCOND, SZ_UNDEF)); 3218 } 3219 else 3220 add_frag (adds (&opP->disp), 3221 SEXT (offs (&opP->disp)), 3222 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF) 3223 : TAB (BRANCHBW, SZ_UNDEF))); 3224 break; 3225 case 'w': 3226 if (isvar (&opP->disp)) 3227 { 3228 /* Check for DBcc instructions. We can relax them, 3229 but only if we have long branches and/or absolute 3230 jumps. */ 3231 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8) 3232 && (HAVE_LONG_BRANCH (current_architecture) 3233 || ! flag_keep_pcrel)) 3234 { 3235 if (HAVE_LONG_BRANCH (current_architecture)) 3236 add_frag (adds (&opP->disp), 3237 SEXT (offs (&opP->disp)), 3238 TAB (DBCCLBR, SZ_UNDEF)); 3239 else 3240 add_frag (adds (&opP->disp), 3241 SEXT (offs (&opP->disp)), 3242 TAB (DBCCABSJ, SZ_UNDEF)); 3243 break; 3244 } 3245 add_fix ('w', &opP->disp, 1, 0); 3246 } 3247 addword (0); 3248 break; 3249 case 'C': /* Fixed size LONG coproc branches. */ 3250 add_fix ('l', &opP->disp, 1, 0); 3251 addword (0); 3252 addword (0); 3253 break; 3254 case 'c': /* Var size Coprocesssor branches. */ 3255 if (subs (&opP->disp) || (adds (&opP->disp) == 0)) 3256 { 3257 the_ins.opcode[the_ins.numo - 1] |= 0x40; 3258 add_fix ('l', &opP->disp, 1, 0); 3259 addword (0); 3260 addword (0); 3261 } 3262 else 3263 add_frag (adds (&opP->disp), 3264 SEXT (offs (&opP->disp)), 3265 TAB (FBRANCH, SZ_UNDEF)); 3266 break; 3267 default: 3268 abort (); 3269 } 3270 break; 3271 3272 case 'C': /* Ignore it. */ 3273 break; 3274 3275 case 'd': /* JF this is a kludge. */ 3276 install_operand ('s', opP->reg - ADDR); 3277 tmpreg = get_num (&opP->disp, 90); 3278 if (!issword (tmpreg)) 3279 { 3280 as_warn (_("Expression out of range, using 0")); 3281 tmpreg = 0; 3282 } 3283 addword (tmpreg); 3284 break; 3285 3286 case 'D': 3287 install_operand (s[1], opP->reg - DATA); 3288 break; 3289 3290 case 'e': /* EMAC ACCx, reg/reg. */ 3291 install_operand (s[1], opP->reg - ACC); 3292 break; 3293 3294 case 'E': /* Ignore it. */ 3295 break; 3296 3297 case 'F': 3298 install_operand (s[1], opP->reg - FP0); 3299 break; 3300 3301 case 'g': /* EMAC ACCEXTx. */ 3302 install_operand (s[1], opP->reg - ACCEXT01); 3303 break; 3304 3305 case 'G': /* Ignore it. */ 3306 case 'H': 3307 break; 3308 3309 case 'I': 3310 tmpreg = opP->reg - COP0; 3311 install_operand (s[1], tmpreg); 3312 break; 3313 3314 case 'i': /* MAC/EMAC scale factor. */ 3315 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); 3316 break; 3317 3318 case 'J': /* JF foo. */ 3319 switch (opP->reg) 3320 { 3321 case SFC: 3322 tmpreg = 0x000; 3323 break; 3324 case DFC: 3325 tmpreg = 0x001; 3326 break; 3327 case CACR: 3328 tmpreg = 0x002; 3329 break; 3330 case TC: 3331 case ASID: 3332 tmpreg = 0x003; 3333 break; 3334 case ACR0: 3335 case ITT0: 3336 tmpreg = 0x004; 3337 break; 3338 case ACR1: 3339 case ITT1: 3340 tmpreg = 0x005; 3341 break; 3342 case ACR2: 3343 case DTT0: 3344 tmpreg = 0x006; 3345 break; 3346 case ACR3: 3347 case DTT1: 3348 tmpreg = 0x007; 3349 break; 3350 case BUSCR: 3351 case MMUBAR: 3352 tmpreg = 0x008; 3353 break; 3354 case RGPIOBAR: 3355 tmpreg = 0x009; 3356 break; 3357 case ACR4: 3358 case ACR5: 3359 case ACR6: 3360 case ACR7: 3361 tmpreg = 0x00c + (opP->reg - ACR4); 3362 break; 3363 3364 case USP: 3365 tmpreg = 0x800; 3366 break; 3367 case VBR: 3368 tmpreg = 0x801; 3369 break; 3370 case CAAR: 3371 case CPUCR: 3372 tmpreg = 0x802; 3373 break; 3374 case MSP: 3375 tmpreg = 0x803; 3376 break; 3377 case ISP: 3378 tmpreg = 0x804; 3379 break; 3380 case MMUSR: 3381 tmpreg = 0x805; 3382 break; 3383 case URP: 3384 tmpreg = 0x806; 3385 break; 3386 case SRP: 3387 tmpreg = 0x807; 3388 break; 3389 case PCR: 3390 tmpreg = 0x808; 3391 break; 3392 case ROMBAR: 3393 case ROMBAR0: 3394 tmpreg = 0xC00; 3395 break; 3396 case ROMBAR1: 3397 tmpreg = 0xC01; 3398 break; 3399 case FLASHBAR: 3400 case RAMBAR0: 3401 case RAMBAR_ALT: 3402 tmpreg = 0xC04; 3403 break; 3404 case RAMBAR: 3405 case RAMBAR1: 3406 tmpreg = 0xC05; 3407 break; 3408 case MPCR: 3409 tmpreg = 0xC0C; 3410 break; 3411 case EDRAMBAR: 3412 tmpreg = 0xC0D; 3413 break; 3414 case MBAR0: 3415 case MBAR2: 3416 case SECMBAR: 3417 tmpreg = 0xC0E; 3418 break; 3419 case MBAR1: 3420 case MBAR: 3421 tmpreg = 0xC0F; 3422 break; 3423 case PCR1U0: 3424 tmpreg = 0xD02; 3425 break; 3426 case PCR1L0: 3427 tmpreg = 0xD03; 3428 break; 3429 case PCR2U0: 3430 tmpreg = 0xD04; 3431 break; 3432 case PCR2L0: 3433 tmpreg = 0xD05; 3434 break; 3435 case PCR3U0: 3436 tmpreg = 0xD06; 3437 break; 3438 case PCR3L0: 3439 tmpreg = 0xD07; 3440 break; 3441 case PCR1L1: 3442 tmpreg = 0xD0A; 3443 break; 3444 case PCR1U1: 3445 tmpreg = 0xD0B; 3446 break; 3447 case PCR2L1: 3448 tmpreg = 0xD0C; 3449 break; 3450 case PCR2U1: 3451 tmpreg = 0xD0D; 3452 break; 3453 case PCR3L1: 3454 tmpreg = 0xD0E; 3455 break; 3456 case PCR3U1: 3457 tmpreg = 0xD0F; 3458 break; 3459 case CAC: 3460 tmpreg = 0xFFE; 3461 break; 3462 case MBO: 3463 tmpreg = 0xFFF; 3464 break; 3465 default: 3466 abort (); 3467 } 3468 install_operand (s[1], tmpreg); 3469 break; 3470 3471 case 'k': 3472 tmpreg = get_num (&opP->disp, 55); 3473 install_operand (s[1], tmpreg & 0x7f); 3474 break; 3475 3476 case 'l': 3477 tmpreg = opP->mask; 3478 if (s[1] == 'w') 3479 { 3480 if (tmpreg & 0x7FF0000) 3481 as_bad (_("Floating point register in register list")); 3482 insop (reverse_16_bits (tmpreg), opcode); 3483 } 3484 else 3485 { 3486 if (tmpreg & 0x700FFFF) 3487 as_bad (_("Wrong register in floating-point reglist")); 3488 install_operand (s[1], reverse_8_bits (tmpreg >> 16)); 3489 } 3490 break; 3491 3492 case 'L': 3493 tmpreg = opP->mask; 3494 if (s[1] == 'w') 3495 { 3496 if (tmpreg & 0x7FF0000) 3497 as_bad (_("Floating point register in register list")); 3498 insop (tmpreg, opcode); 3499 } 3500 else if (s[1] == '8') 3501 { 3502 if (tmpreg & 0x0FFFFFF) 3503 as_bad (_("incorrect register in reglist")); 3504 install_operand (s[1], tmpreg >> 24); 3505 } 3506 else 3507 { 3508 if (tmpreg & 0x700FFFF) 3509 as_bad (_("wrong register in floating-point reglist")); 3510 else 3511 install_operand (s[1], tmpreg >> 16); 3512 } 3513 break; 3514 3515 case 'M': 3516 install_operand (s[1], get_num (&opP->disp, 60)); 3517 break; 3518 3519 case 'O': 3520 tmpreg = ((opP->mode == DREG) 3521 ? 0x20 + (int) (opP->reg - DATA) 3522 : (get_num (&opP->disp, 40) & 0x1F)); 3523 install_operand (s[1], tmpreg); 3524 break; 3525 3526 case 'Q': 3527 tmpreg = get_num (&opP->disp, 10); 3528 if (tmpreg == 8) 3529 tmpreg = 0; 3530 install_operand (s[1], tmpreg); 3531 break; 3532 3533 case 'R': 3534 /* This depends on the fact that ADDR registers are eight 3535 more than their corresponding DATA regs, so the result 3536 will have the ADDR_REG bit set. */ 3537 install_operand (s[1], opP->reg - DATA); 3538 break; 3539 3540 case 'r': 3541 if (opP->mode == AINDR) 3542 install_operand (s[1], opP->reg - DATA); 3543 else 3544 install_operand (s[1], opP->index.reg - DATA); 3545 break; 3546 3547 case 's': 3548 if (opP->reg == FPI) 3549 tmpreg = 0x1; 3550 else if (opP->reg == FPS) 3551 tmpreg = 0x2; 3552 else if (opP->reg == FPC) 3553 tmpreg = 0x4; 3554 else 3555 abort (); 3556 install_operand (s[1], tmpreg); 3557 break; 3558 3559 case 'S': /* Ignore it. */ 3560 break; 3561 3562 case 'T': 3563 install_operand (s[1], get_num (&opP->disp, 30)); 3564 break; 3565 3566 case 'U': /* Ignore it. */ 3567 break; 3568 3569 case 'c': 3570 switch (opP->reg) 3571 { 3572 case NC: 3573 tmpreg = 0; 3574 break; 3575 case DC: 3576 tmpreg = 1; 3577 break; 3578 case IC: 3579 tmpreg = 2; 3580 break; 3581 case BC: 3582 tmpreg = 3; 3583 break; 3584 default: 3585 as_fatal (_("failed sanity check")); 3586 } /* switch on cache token. */ 3587 install_operand (s[1], tmpreg); 3588 break; 3589 #ifndef NO_68851 3590 /* JF: These are out of order, I fear. */ 3591 case 'f': 3592 switch (opP->reg) 3593 { 3594 case SFC: 3595 tmpreg = 0; 3596 break; 3597 case DFC: 3598 tmpreg = 1; 3599 break; 3600 default: 3601 abort (); 3602 } 3603 install_operand (s[1], tmpreg); 3604 break; 3605 3606 case '0': 3607 case '1': 3608 case '2': 3609 switch (opP->reg) 3610 { 3611 case TC: 3612 tmpreg = 0; 3613 break; 3614 case CAL: 3615 tmpreg = 4; 3616 break; 3617 case VAL: 3618 tmpreg = 5; 3619 break; 3620 case SCC: 3621 tmpreg = 6; 3622 break; 3623 case AC: 3624 tmpreg = 7; 3625 break; 3626 default: 3627 abort (); 3628 } 3629 install_operand (s[1], tmpreg); 3630 break; 3631 3632 case 'V': 3633 if (opP->reg == VAL) 3634 break; 3635 abort (); 3636 3637 case 'W': 3638 switch (opP->reg) 3639 { 3640 case DRP: 3641 tmpreg = 1; 3642 break; 3643 case SRP: 3644 tmpreg = 2; 3645 break; 3646 case CRP: 3647 tmpreg = 3; 3648 break; 3649 default: 3650 abort (); 3651 } 3652 install_operand (s[1], tmpreg); 3653 break; 3654 3655 case 'X': 3656 switch (opP->reg) 3657 { 3658 case BAD: 3659 case BAD + 1: 3660 case BAD + 2: 3661 case BAD + 3: 3662 case BAD + 4: 3663 case BAD + 5: 3664 case BAD + 6: 3665 case BAD + 7: 3666 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); 3667 break; 3668 3669 case BAC: 3670 case BAC + 1: 3671 case BAC + 2: 3672 case BAC + 3: 3673 case BAC + 4: 3674 case BAC + 5: 3675 case BAC + 6: 3676 case BAC + 7: 3677 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); 3678 break; 3679 3680 default: 3681 abort (); 3682 } 3683 install_operand (s[1], tmpreg); 3684 break; 3685 case 'Y': 3686 know (opP->reg == PSR); 3687 break; 3688 case 'Z': 3689 know (opP->reg == PCSR); 3690 break; 3691 #endif /* m68851 */ 3692 case '3': 3693 switch (opP->reg) 3694 { 3695 case TT0: 3696 tmpreg = 2; 3697 break; 3698 case TT1: 3699 tmpreg = 3; 3700 break; 3701 default: 3702 abort (); 3703 } 3704 install_operand (s[1], tmpreg); 3705 break; 3706 case 't': 3707 tmpreg = get_num (&opP->disp, 20); 3708 install_operand (s[1], tmpreg); 3709 break; 3710 case '_': /* used only for move16 absolute 32-bit address. */ 3711 if (isvar (&opP->disp)) 3712 add_fix ('l', &opP->disp, 0, 0); 3713 tmpreg = get_num (&opP->disp, 90); 3714 addword (tmpreg >> 16); 3715 addword (tmpreg & 0xFFFF); 3716 break; 3717 case 'u': 3718 install_operand (s[1], opP->reg - DATA0L); 3719 opP->reg -= (DATA0L); 3720 opP->reg &= 0x0F; /* remove upper/lower bit. */ 3721 break; 3722 case 'x': 3723 tmpreg = get_num (&opP->disp, 80); 3724 if (tmpreg == -1) 3725 tmpreg = 0; 3726 install_operand (s[1], tmpreg); 3727 break; 3728 case 'j': 3729 tmpreg = get_num (&opP->disp, 10); 3730 install_operand (s[1], tmpreg - 1); 3731 break; 3732 case 'K': 3733 tmpreg = get_num (&opP->disp, 65); 3734 install_operand (s[1], tmpreg); 3735 break; 3736 default: 3737 abort (); 3738 } 3739 } 3740 3741 /* By the time whe get here (FINALLY) the_ins contains the complete 3742 instruction, ready to be emitted. . . */ 3743 } 3744 3745 static int 3746 reverse_16_bits (int in) 3747 { 3748 int out = 0; 3749 int n; 3750 3751 static int mask[16] = 3752 { 3753 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3754 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000 3755 }; 3756 for (n = 0; n < 16; n++) 3757 { 3758 if (in & mask[n]) 3759 out |= mask[15 - n]; 3760 } 3761 return out; 3762 } /* reverse_16_bits() */ 3763 3764 static int 3765 reverse_8_bits (int in) 3766 { 3767 int out = 0; 3768 int n; 3769 3770 static int mask[8] = 3771 { 3772 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080, 3773 }; 3774 3775 for (n = 0; n < 8; n++) 3776 { 3777 if (in & mask[n]) 3778 out |= mask[7 - n]; 3779 } 3780 return out; 3781 } /* reverse_8_bits() */ 3782 3783 /* Cause an extra frag to be generated here, inserting up to 3784 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be 3785 generated; its primary type is rs_machine_dependent. 3786 3787 The TYPE parameter is also used by md_convert_frag_1 and 3788 md_estimate_size_before_relax. The appropriate type of fixup will 3789 be emitted by md_convert_frag_1. 3790 3791 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */ 3792 static void 3793 install_operand (int mode, int val) 3794 { 3795 switch (mode) 3796 { 3797 case 's': 3798 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ 3799 break; 3800 case 'd': 3801 the_ins.opcode[0] |= val << 9; 3802 break; 3803 case 'E': 3804 the_ins.opcode[1] |= val << 9; 3805 break; 3806 case '1': 3807 the_ins.opcode[1] |= val << 12; 3808 break; 3809 case '2': 3810 the_ins.opcode[1] |= val << 6; 3811 break; 3812 case '3': 3813 the_ins.opcode[1] |= val; 3814 break; 3815 case '4': 3816 the_ins.opcode[2] |= val << 12; 3817 break; 3818 case '5': 3819 the_ins.opcode[2] |= val << 6; 3820 break; 3821 case '6': 3822 /* DANGER! This is a hack to force cas2l and cas2w cmds to be 3823 three words long! */ 3824 the_ins.numo++; 3825 the_ins.opcode[2] |= val; 3826 break; 3827 case '7': 3828 the_ins.opcode[1] |= val << 7; 3829 break; 3830 case '8': 3831 the_ins.opcode[1] |= val << 10; 3832 break; 3833 #ifndef NO_68851 3834 case '9': 3835 the_ins.opcode[1] |= val << 5; 3836 break; 3837 #endif 3838 3839 case 't': 3840 the_ins.opcode[1] |= (val << 10) | (val << 7); 3841 break; 3842 case 'D': 3843 the_ins.opcode[1] |= (val << 12) | val; 3844 break; 3845 case 'g': 3846 the_ins.opcode[0] |= val = 0xff; 3847 break; 3848 case 'i': 3849 the_ins.opcode[0] |= val << 9; 3850 break; 3851 case 'C': 3852 the_ins.opcode[1] |= val; 3853 break; 3854 case 'j': 3855 the_ins.opcode[1] |= val; 3856 the_ins.numo++; /* What a hack. */ 3857 break; 3858 case 'k': 3859 the_ins.opcode[1] |= val << 4; 3860 break; 3861 case 'b': 3862 case 'w': 3863 case 'W': 3864 case 'l': 3865 break; 3866 case 'e': 3867 the_ins.opcode[0] |= (val << 6); 3868 break; 3869 case 'L': 3870 the_ins.opcode[1] = (val >> 16); 3871 the_ins.opcode[2] = val & 0xffff; 3872 break; 3873 case 'm': 3874 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3875 the_ins.opcode[0] |= ((val & 0x7) << 9); 3876 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3877 break; 3878 case 'n': /* MAC/EMAC Rx on !load. */ 3879 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); 3880 the_ins.opcode[0] |= ((val & 0x7) << 9); 3881 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3882 break; 3883 case 'o': /* MAC/EMAC Rx on load. */ 3884 the_ins.opcode[1] |= val << 12; 3885 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); 3886 break; 3887 case 'M': /* MAC/EMAC Ry on !load. */ 3888 the_ins.opcode[0] |= (val & 0xF); 3889 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3890 break; 3891 case 'N': /* MAC/EMAC Ry on load. */ 3892 the_ins.opcode[1] |= (val & 0xF); 3893 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); 3894 break; 3895 case 'h': 3896 the_ins.opcode[1] |= ((val != 1) << 10); 3897 break; 3898 case 'F': 3899 the_ins.opcode[0] |= ((val & 0x3) << 9); 3900 break; 3901 case 'f': 3902 the_ins.opcode[0] |= ((val & 0x3) << 0); 3903 break; 3904 case 'G': /* EMAC accumulator in a EMAC load instruction. */ 3905 the_ins.opcode[0] |= ((~val & 0x1) << 7); 3906 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3907 break; 3908 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */ 3909 the_ins.opcode[0] |= ((val & 0x1) << 7); 3910 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); 3911 break; 3912 case 'I': 3913 the_ins.opcode[1] |= ((val & 0x3) << 9); 3914 break; 3915 case ']': 3916 the_ins.opcode[0] |= (val & 0x1) <<10; 3917 break; 3918 case 'c': 3919 default: 3920 as_fatal (_("failed sanity check.")); 3921 } 3922 } 3923 3924 static void 3925 install_gen_operand (int mode, int val) 3926 { 3927 switch (mode) 3928 { 3929 case '/': /* Special for mask loads for mac/msac insns with 3930 possible mask; trailing_ampersend set in bit 8. */ 3931 the_ins.opcode[0] |= (val & 0x3f); 3932 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); 3933 break; 3934 case 's': 3935 the_ins.opcode[0] |= val; 3936 break; 3937 case 'd': 3938 /* This is a kludge!!! */ 3939 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3; 3940 break; 3941 case 'b': 3942 case 'w': 3943 case 'l': 3944 case 'f': 3945 case 'F': 3946 case 'x': 3947 case 'p': 3948 the_ins.opcode[0] |= val; 3949 break; 3950 /* more stuff goes here. */ 3951 default: 3952 as_fatal (_("failed sanity check.")); 3953 } 3954 } 3955 3956 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and 3957 then deal with the bitfield hack. */ 3958 3959 static char * 3960 crack_operand (char *str, struct m68k_op *opP) 3961 { 3962 register int parens; 3963 register int c; 3964 register char *beg_str; 3965 int inquote = 0; 3966 3967 if (!str) 3968 { 3969 return str; 3970 } 3971 beg_str = str; 3972 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++) 3973 { 3974 if (! inquote) 3975 { 3976 if (*str == '(') 3977 parens++; 3978 else if (*str == ')') 3979 { 3980 if (!parens) 3981 { /* ERROR. */ 3982 opP->error = _("Extra )"); 3983 return str; 3984 } 3985 --parens; 3986 } 3987 } 3988 if (flag_mri && *str == '\'') 3989 inquote = ! inquote; 3990 } 3991 if (!*str && parens) 3992 { /* ERROR. */ 3993 opP->error = _("Missing )"); 3994 return str; 3995 } 3996 c = *str; 3997 *str = '\0'; 3998 if (m68k_ip_op (beg_str, opP) != 0) 3999 { 4000 *str = c; 4001 return str; 4002 } 4003 *str = c; 4004 if (c == '}') 4005 c = *++str; /* JF bitfield hack. */ 4006 if (c) 4007 { 4008 c = *++str; 4009 if (!c) 4010 as_bad (_("Missing operand")); 4011 } 4012 4013 /* Detect MRI REG symbols and convert them to REGLSTs. */ 4014 if (opP->mode == CONTROL && (int)opP->reg < 0) 4015 { 4016 opP->mode = REGLST; 4017 opP->mask = ~(int)opP->reg; 4018 opP->reg = 0; 4019 } 4020 4021 return str; 4022 } 4023 4024 /* This is the guts of the machine-dependent assembler. STR points to a 4025 machine dependent instruction. This function is supposed to emit 4026 the frags/bytes it assembles to. 4027 */ 4028 4029 static void 4030 insert_reg (const char *regname, int regnum) 4031 { 4032 char buf[100]; 4033 int i; 4034 4035 #ifdef REGISTER_PREFIX 4036 if (!flag_reg_prefix_optional) 4037 { 4038 buf[0] = REGISTER_PREFIX; 4039 strcpy (buf + 1, regname); 4040 regname = buf; 4041 } 4042 #endif 4043 4044 symbol_table_insert (symbol_new (regname, reg_section, regnum, 4045 &zero_address_frag)); 4046 4047 for (i = 0; regname[i]; i++) 4048 buf[i] = TOUPPER (regname[i]); 4049 buf[i] = '\0'; 4050 4051 symbol_table_insert (symbol_new (buf, reg_section, regnum, 4052 &zero_address_frag)); 4053 } 4054 4055 struct init_entry 4056 { 4057 const char *name; 4058 int number; 4059 }; 4060 4061 static const struct init_entry init_table[] = 4062 { 4063 { "d0", DATA0 }, 4064 { "d1", DATA1 }, 4065 { "d2", DATA2 }, 4066 { "d3", DATA3 }, 4067 { "d4", DATA4 }, 4068 { "d5", DATA5 }, 4069 { "d6", DATA6 }, 4070 { "d7", DATA7 }, 4071 { "a0", ADDR0 }, 4072 { "a1", ADDR1 }, 4073 { "a2", ADDR2 }, 4074 { "a3", ADDR3 }, 4075 { "a4", ADDR4 }, 4076 { "a5", ADDR5 }, 4077 { "a6", ADDR6 }, 4078 { "fp", ADDR6 }, 4079 { "a7", ADDR7 }, 4080 { "sp", ADDR7 }, 4081 { "ssp", ADDR7 }, 4082 { "fp0", FP0 }, 4083 { "fp1", FP1 }, 4084 { "fp2", FP2 }, 4085 { "fp3", FP3 }, 4086 { "fp4", FP4 }, 4087 { "fp5", FP5 }, 4088 { "fp6", FP6 }, 4089 { "fp7", FP7 }, 4090 { "fpi", FPI }, 4091 { "fpiar", FPI }, 4092 { "fpc", FPI }, 4093 { "fps", FPS }, 4094 { "fpsr", FPS }, 4095 { "fpc", FPC }, 4096 { "fpcr", FPC }, 4097 { "control", FPC }, 4098 { "status", FPS }, 4099 { "iaddr", FPI }, 4100 4101 { "cop0", COP0 }, 4102 { "cop1", COP1 }, 4103 { "cop2", COP2 }, 4104 { "cop3", COP3 }, 4105 { "cop4", COP4 }, 4106 { "cop5", COP5 }, 4107 { "cop6", COP6 }, 4108 { "cop7", COP7 }, 4109 { "pc", PC }, 4110 { "zpc", ZPC }, 4111 { "sr", SR }, 4112 4113 { "ccr", CCR }, 4114 { "cc", CCR }, 4115 4116 { "acc", ACC }, 4117 { "acc0", ACC }, 4118 { "acc1", ACC1 }, 4119 { "acc2", ACC2 }, 4120 { "acc3", ACC3 }, 4121 { "accext01", ACCEXT01 }, 4122 { "accext23", ACCEXT23 }, 4123 { "macsr", MACSR }, 4124 { "mask", MASK }, 4125 4126 /* Control registers. */ 4127 { "sfc", SFC }, /* Source Function Code. */ 4128 { "sfcr", SFC }, 4129 { "dfc", DFC }, /* Destination Function Code. */ 4130 { "dfcr", DFC }, 4131 { "cacr", CACR }, /* Cache Control Register. */ 4132 { "caar", CAAR }, /* Cache Address Register. */ 4133 { "cpucr", CPUCR }, /* CPU Control Register. */ 4134 4135 { "usp", USP }, /* User Stack Pointer. */ 4136 { "vbr", VBR }, /* Vector Base Register. */ 4137 { "msp", MSP }, /* Master Stack Pointer. */ 4138 { "isp", ISP }, /* Interrupt Stack Pointer. */ 4139 4140 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ 4141 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ 4142 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ 4143 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ 4144 4145 /* 68ec040 versions of same */ 4146 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ 4147 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ 4148 { "dacr0", DTT0 }, /* Data Access Control Register 0. */ 4149 { "dacr1", DTT1 }, /* Data Access Control Register 0. */ 4150 4151 /* Coldfire versions of same. The ColdFire programmer's reference 4152 manual indicated that the order is 2,3,0,1, but Ken Rose 4153 <rose@netcom.com> says that 0,1,2,3 is the correct order. */ 4154 { "acr0", ACR0 }, /* Access Control Unit 0. */ 4155 { "acr1", ACR1 }, /* Access Control Unit 1. */ 4156 { "acr2", ACR2 }, /* Access Control Unit 2. */ 4157 { "acr3", ACR3 }, /* Access Control Unit 3. */ 4158 { "acr4", ACR4 }, /* Access Control Unit 4. */ 4159 { "acr5", ACR5 }, /* Access Control Unit 5. */ 4160 { "acr6", ACR6 }, /* Access Control Unit 6. */ 4161 { "acr7", ACR7 }, /* Access Control Unit 7. */ 4162 4163 { "tc", TC }, /* MMU Translation Control Register. */ 4164 { "tcr", TC }, 4165 { "asid", ASID }, 4166 4167 { "mmusr", MMUSR }, /* MMU Status Register. */ 4168 { "srp", SRP }, /* User Root Pointer. */ 4169 { "urp", URP }, /* Supervisor Root Pointer. */ 4170 4171 { "buscr", BUSCR }, 4172 { "mmubar", MMUBAR }, 4173 { "pcr", PCR }, 4174 4175 { "rombar", ROMBAR }, /* ROM Base Address Register. */ 4176 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ 4177 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ 4178 { "mbar", MBAR }, /* Module Base Address Register. */ 4179 4180 { "mbar0", MBAR0 }, /* mcfv4e registers. */ 4181 { "mbar1", MBAR1 }, /* mcfv4e registers. */ 4182 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */ 4183 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ 4184 { "mpcr", MPCR }, /* mcfv4e registers. */ 4185 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ 4186 { "secmbar", SECMBAR }, /* mcfv4e registers. */ 4187 { "asid", TC }, /* mcfv4e registers. */ 4188 { "mmubar", BUSCR }, /* mcfv4e registers. */ 4189 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ 4190 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ 4191 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ 4192 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ 4193 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ 4194 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ 4195 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ 4196 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ 4197 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ 4198 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ 4199 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ 4200 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ 4201 4202 { "flashbar", FLASHBAR }, /* mcf528x registers. */ 4203 { "rambar", RAMBAR }, /* mcf528x registers. */ 4204 4205 { "mbar2", MBAR2 }, /* mcf5249 registers. */ 4206 4207 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */ 4208 4209 { "cac", CAC }, /* fido registers. */ 4210 { "mbb", MBO }, /* fido registers (obsolete). */ 4211 { "mbo", MBO }, /* fido registers. */ 4212 /* End of control registers. */ 4213 4214 { "ac", AC }, 4215 { "bc", BC }, 4216 { "cal", CAL }, 4217 { "crp", CRP }, 4218 { "drp", DRP }, 4219 { "pcsr", PCSR }, 4220 { "psr", PSR }, 4221 { "scc", SCC }, 4222 { "val", VAL }, 4223 { "bad0", BAD0 }, 4224 { "bad1", BAD1 }, 4225 { "bad2", BAD2 }, 4226 { "bad3", BAD3 }, 4227 { "bad4", BAD4 }, 4228 { "bad5", BAD5 }, 4229 { "bad6", BAD6 }, 4230 { "bad7", BAD7 }, 4231 { "bac0", BAC0 }, 4232 { "bac1", BAC1 }, 4233 { "bac2", BAC2 }, 4234 { "bac3", BAC3 }, 4235 { "bac4", BAC4 }, 4236 { "bac5", BAC5 }, 4237 { "bac6", BAC6 }, 4238 { "bac7", BAC7 }, 4239 4240 { "ic", IC }, 4241 { "dc", DC }, 4242 { "nc", NC }, 4243 4244 { "tt0", TT0 }, 4245 { "tt1", TT1 }, 4246 /* 68ec030 versions of same. */ 4247 { "ac0", TT0 }, 4248 { "ac1", TT1 }, 4249 /* 68ec030 access control unit, identical to 030 MMU status reg. */ 4250 { "acusr", PSR }, 4251 4252 /* Suppressed data and address registers. */ 4253 { "zd0", ZDATA0 }, 4254 { "zd1", ZDATA1 }, 4255 { "zd2", ZDATA2 }, 4256 { "zd3", ZDATA3 }, 4257 { "zd4", ZDATA4 }, 4258 { "zd5", ZDATA5 }, 4259 { "zd6", ZDATA6 }, 4260 { "zd7", ZDATA7 }, 4261 { "za0", ZADDR0 }, 4262 { "za1", ZADDR1 }, 4263 { "za2", ZADDR2 }, 4264 { "za3", ZADDR3 }, 4265 { "za4", ZADDR4 }, 4266 { "za5", ZADDR5 }, 4267 { "za6", ZADDR6 }, 4268 { "za7", ZADDR7 }, 4269 4270 /* Upper and lower data and address registers, used by macw and msacw. */ 4271 { "d0l", DATA0L }, 4272 { "d1l", DATA1L }, 4273 { "d2l", DATA2L }, 4274 { "d3l", DATA3L }, 4275 { "d4l", DATA4L }, 4276 { "d5l", DATA5L }, 4277 { "d6l", DATA6L }, 4278 { "d7l", DATA7L }, 4279 4280 { "a0l", ADDR0L }, 4281 { "a1l", ADDR1L }, 4282 { "a2l", ADDR2L }, 4283 { "a3l", ADDR3L }, 4284 { "a4l", ADDR4L }, 4285 { "a5l", ADDR5L }, 4286 { "a6l", ADDR6L }, 4287 { "a7l", ADDR7L }, 4288 4289 { "d0u", DATA0U }, 4290 { "d1u", DATA1U }, 4291 { "d2u", DATA2U }, 4292 { "d3u", DATA3U }, 4293 { "d4u", DATA4U }, 4294 { "d5u", DATA5U }, 4295 { "d6u", DATA6U }, 4296 { "d7u", DATA7U }, 4297 4298 { "a0u", ADDR0U }, 4299 { "a1u", ADDR1U }, 4300 { "a2u", ADDR2U }, 4301 { "a3u", ADDR3U }, 4302 { "a4u", ADDR4U }, 4303 { "a5u", ADDR5U }, 4304 { "a6u", ADDR6U }, 4305 { "a7u", ADDR7U }, 4306 4307 { 0, 0 } 4308 }; 4309 4310 static void 4311 init_regtable (void) 4312 { 4313 int i; 4314 for (i = 0; init_table[i].name; i++) 4315 insert_reg (init_table[i].name, init_table[i].number); 4316 } 4317 4318 void 4319 md_assemble (char *str) 4320 { 4321 const char *er; 4322 short *fromP; 4323 char *toP = NULL; 4324 int m, n = 0; 4325 char *to_beg_P; 4326 int shorts_this_frag; 4327 fixS *fixP; 4328 4329 if (!selected_cpu && !selected_arch) 4330 { 4331 /* We've not selected an architecture yet. Set the default 4332 now. We do this lazily so that an initial .cpu or .arch directive 4333 can specify. */ 4334 if (!m68k_set_cpu (TARGET_CPU, 1, 1)) 4335 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU); 4336 } 4337 if (!initialized) 4338 m68k_init_arch (); 4339 4340 /* In MRI mode, the instruction and operands are separated by a 4341 space. Anything following the operands is a comment. The label 4342 has already been removed. */ 4343 if (flag_mri) 4344 { 4345 char *s; 4346 int fields = 0; 4347 int infield = 0; 4348 int inquote = 0; 4349 4350 for (s = str; *s != '\0'; s++) 4351 { 4352 if ((*s == ' ' || *s == '\t') && ! inquote) 4353 { 4354 if (infield) 4355 { 4356 ++fields; 4357 if (fields >= 2) 4358 { 4359 *s = '\0'; 4360 break; 4361 } 4362 infield = 0; 4363 } 4364 } 4365 else 4366 { 4367 if (! infield) 4368 infield = 1; 4369 if (*s == '\'') 4370 inquote = ! inquote; 4371 } 4372 } 4373 } 4374 4375 memset (&the_ins, '\0', sizeof (the_ins)); 4376 m68k_ip (str); 4377 er = the_ins.error; 4378 if (!er) 4379 { 4380 for (n = 0; n < the_ins.numargs; n++) 4381 if (the_ins.operands[n].error) 4382 { 4383 er = the_ins.operands[n].error; 4384 break; 4385 } 4386 } 4387 if (er) 4388 { 4389 as_bad (_("%s -- statement `%s' ignored"), er, str); 4390 return; 4391 } 4392 4393 /* If there is a current label, record that it marks an instruction. */ 4394 if (current_label != NULL) 4395 { 4396 current_label->text = 1; 4397 current_label = NULL; 4398 } 4399 4400 #ifdef OBJ_ELF 4401 /* Tie dwarf2 debug info to the address at the start of the insn. */ 4402 dwarf2_emit_insn (0); 4403 #endif 4404 4405 if (the_ins.nfrag == 0) 4406 { 4407 /* No frag hacking involved; just put it out. */ 4408 toP = frag_more (2 * the_ins.numo); 4409 fromP = &the_ins.opcode[0]; 4410 for (m = the_ins.numo; m; --m) 4411 { 4412 md_number_to_chars (toP, (long) (*fromP), 2); 4413 toP += 2; 4414 fromP++; 4415 } 4416 /* Put out symbol-dependent info. */ 4417 for (m = 0; m < the_ins.nrel; m++) 4418 { 4419 switch (the_ins.reloc[m].wid) 4420 { 4421 case 'B': 4422 n = 1; 4423 break; 4424 case 'b': 4425 n = 1; 4426 break; 4427 case '3': 4428 n = 1; 4429 break; 4430 case 'w': 4431 case 'W': 4432 n = 2; 4433 break; 4434 case 'l': 4435 n = 4; 4436 break; 4437 default: 4438 as_fatal (_("Don't know how to figure width of %c in md_assemble()"), 4439 the_ins.reloc[m].wid); 4440 } 4441 4442 fixP = fix_new_exp (frag_now, 4443 ((toP - frag_now->fr_literal) 4444 - the_ins.numo * 2 + the_ins.reloc[m].n), 4445 n, 4446 &the_ins.reloc[m].exp, 4447 the_ins.reloc[m].pcrel, 4448 get_reloc_code (n, the_ins.reloc[m].pcrel, 4449 the_ins.reloc[m].pic_reloc)); 4450 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4451 if (the_ins.reloc[m].wid == 'B') 4452 fixP->fx_signed = 1; 4453 } 4454 return; 4455 } 4456 4457 /* There's some frag hacking. */ 4458 { 4459 /* Calculate the max frag size. */ 4460 int wid; 4461 4462 wid = 2 * the_ins.fragb[0].fragoff; 4463 for (n = 1; n < the_ins.nfrag; n++) 4464 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4465 /* frag_var part. */ 4466 wid += FRAG_VAR_SIZE; 4467 /* Make sure the whole insn fits in one chunk, in particular that 4468 the var part is attached, as we access one byte before the 4469 variable frag for byte branches. */ 4470 frag_grow (wid); 4471 } 4472 4473 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++) 4474 { 4475 int wid; 4476 4477 if (n == 0) 4478 wid = 2 * the_ins.fragb[n].fragoff; 4479 else 4480 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4481 toP = frag_more (wid); 4482 to_beg_P = toP; 4483 shorts_this_frag = 0; 4484 for (m = wid / 2; m; --m) 4485 { 4486 md_number_to_chars (toP, (long) (*fromP), 2); 4487 toP += 2; 4488 fromP++; 4489 shorts_this_frag++; 4490 } 4491 for (m = 0; m < the_ins.nrel; m++) 4492 { 4493 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag) 4494 { 4495 the_ins.reloc[m].n -= 2 * shorts_this_frag; 4496 break; 4497 } 4498 wid = the_ins.reloc[m].wid; 4499 if (wid == 0) 4500 continue; 4501 the_ins.reloc[m].wid = 0; 4502 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4503 4504 fixP = fix_new_exp (frag_now, 4505 ((toP - frag_now->fr_literal) 4506 - the_ins.numo * 2 + the_ins.reloc[m].n), 4507 wid, 4508 &the_ins.reloc[m].exp, 4509 the_ins.reloc[m].pcrel, 4510 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4511 the_ins.reloc[m].pic_reloc)); 4512 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4513 } 4514 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0, 4515 (relax_substateT) (the_ins.fragb[n].fragty), 4516 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P); 4517 } 4518 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff); 4519 shorts_this_frag = 0; 4520 if (n) 4521 { 4522 toP = frag_more (n * 2); 4523 while (n--) 4524 { 4525 md_number_to_chars (toP, (long) (*fromP), 2); 4526 toP += 2; 4527 fromP++; 4528 shorts_this_frag++; 4529 } 4530 } 4531 for (m = 0; m < the_ins.nrel; m++) 4532 { 4533 int wid; 4534 4535 wid = the_ins.reloc[m].wid; 4536 if (wid == 0) 4537 continue; 4538 the_ins.reloc[m].wid = 0; 4539 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000; 4540 4541 fixP = fix_new_exp (frag_now, 4542 ((the_ins.reloc[m].n + toP - frag_now->fr_literal) 4543 - shorts_this_frag * 2), 4544 wid, 4545 &the_ins.reloc[m].exp, 4546 the_ins.reloc[m].pcrel, 4547 get_reloc_code (wid, the_ins.reloc[m].pcrel, 4548 the_ins.reloc[m].pic_reloc)); 4549 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix; 4550 } 4551 } 4552 4553 /* Comparison function used by qsort to rank the opcode entries by name. */ 4554 4555 static int 4556 m68k_compare_opcode (const void * v1, const void * v2) 4557 { 4558 struct m68k_opcode * op1, * op2; 4559 int ret; 4560 4561 if (v1 == v2) 4562 return 0; 4563 4564 op1 = *(struct m68k_opcode **) v1; 4565 op2 = *(struct m68k_opcode **) v2; 4566 4567 /* Compare the two names. If different, return the comparison. 4568 If the same, return the order they are in the opcode table. */ 4569 ret = strcmp (op1->name, op2->name); 4570 if (ret) 4571 return ret; 4572 if (op1 < op2) 4573 return -1; 4574 return 1; 4575 } 4576 4577 void 4578 md_begin (void) 4579 { 4580 const struct m68k_opcode *ins; 4581 struct m68k_incant *hack, *slak; 4582 const char *retval = 0; /* Empty string, or error msg text. */ 4583 int i; 4584 4585 /* Set up hash tables with 68000 instructions. 4586 similar to what the vax assembler does. */ 4587 /* RMS claims the thing to do is take the m68k-opcode.h table, and make 4588 a copy of it at runtime, adding in the information we want but isn't 4589 there. I think it'd be better to have an awk script hack the table 4590 at compile time. Or even just xstr the table and use it as-is. But 4591 my lord ghod hath spoken, so we do it this way. Excuse the ugly var 4592 names. */ 4593 4594 if (flag_mri) 4595 { 4596 flag_reg_prefix_optional = 1; 4597 m68k_abspcadd = 1; 4598 if (! m68k_rel32_from_cmdline) 4599 m68k_rel32 = 0; 4600 } 4601 4602 /* First sort the opcode table into alphabetical order to seperate 4603 the order that the assembler wants to see the opcodes from the 4604 order that the disassembler wants to see them. */ 4605 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes)); 4606 if (!m68k_sorted_opcodes) 4607 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"), 4608 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes))); 4609 4610 for (i = m68k_numopcodes; i--;) 4611 m68k_sorted_opcodes[i] = m68k_opcodes + i; 4612 4613 qsort (m68k_sorted_opcodes, m68k_numopcodes, 4614 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode); 4615 4616 op_hash = hash_new (); 4617 4618 obstack_begin (&robyn, 4000); 4619 for (i = 0; i < m68k_numopcodes; i++) 4620 { 4621 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant)); 4622 do 4623 { 4624 ins = m68k_sorted_opcodes[i]; 4625 4626 /* We must enter all insns into the table, because .arch and 4627 .cpu directives can change things. */ 4628 slak->m_operands = ins->args; 4629 slak->m_arch = ins->arch; 4630 slak->m_opcode = ins->opcode; 4631 4632 /* In most cases we can determine the number of opcode words 4633 by checking the second word of the mask. Unfortunately 4634 some instructions have 2 opcode words, but no fixed bits 4635 in the second word. A leading dot in the operands 4636 string also indicates 2 opcodes. */ 4637 if (*slak->m_operands == '.') 4638 { 4639 slak->m_operands++; 4640 slak->m_codenum = 2; 4641 } 4642 else if (ins->match & 0xffffL) 4643 slak->m_codenum = 2; 4644 else 4645 slak->m_codenum = 1; 4646 slak->m_opnum = strlen (slak->m_operands) / 2; 4647 4648 if (i + 1 != m68k_numopcodes 4649 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name)) 4650 { 4651 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant)); 4652 i++; 4653 } 4654 else 4655 slak->m_next = 0; 4656 slak = slak->m_next; 4657 } 4658 while (slak); 4659 4660 retval = hash_insert (op_hash, ins->name, (char *) hack); 4661 if (retval) 4662 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval); 4663 } 4664 4665 for (i = 0; i < m68k_numaliases; i++) 4666 { 4667 const char *name = m68k_opcode_aliases[i].primary; 4668 const char *alias = m68k_opcode_aliases[i].alias; 4669 void *val = hash_find (op_hash, name); 4670 4671 if (!val) 4672 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4673 retval = hash_insert (op_hash, alias, val); 4674 if (retval) 4675 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); 4676 } 4677 4678 /* In MRI mode, all unsized branches are variable sized. Normally, 4679 they are word sized. */ 4680 if (flag_mri) 4681 { 4682 static struct m68k_opcode_alias mri_aliases[] = 4683 { 4684 { "bhi", "jhi", }, 4685 { "bls", "jls", }, 4686 { "bcc", "jcc", }, 4687 { "bcs", "jcs", }, 4688 { "bne", "jne", }, 4689 { "beq", "jeq", }, 4690 { "bvc", "jvc", }, 4691 { "bvs", "jvs", }, 4692 { "bpl", "jpl", }, 4693 { "bmi", "jmi", }, 4694 { "bge", "jge", }, 4695 { "blt", "jlt", }, 4696 { "bgt", "jgt", }, 4697 { "ble", "jle", }, 4698 { "bra", "jra", }, 4699 { "bsr", "jbsr", }, 4700 }; 4701 4702 for (i = 0; 4703 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]); 4704 i++) 4705 { 4706 const char *name = mri_aliases[i].primary; 4707 const char *alias = mri_aliases[i].alias; 4708 void *val = hash_find (op_hash, name); 4709 4710 if (!val) 4711 as_fatal (_("Internal Error: Can't find %s in hash table"), name); 4712 retval = hash_jam (op_hash, alias, val); 4713 if (retval) 4714 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval); 4715 } 4716 } 4717 4718 for (i = 0; i < (int) sizeof (notend_table); i++) 4719 { 4720 notend_table[i] = 0; 4721 alt_notend_table[i] = 0; 4722 } 4723 4724 notend_table[','] = 1; 4725 notend_table['{'] = 1; 4726 notend_table['}'] = 1; 4727 alt_notend_table['a'] = 1; 4728 alt_notend_table['A'] = 1; 4729 alt_notend_table['d'] = 1; 4730 alt_notend_table['D'] = 1; 4731 alt_notend_table['#'] = 1; 4732 alt_notend_table['&'] = 1; 4733 alt_notend_table['f'] = 1; 4734 alt_notend_table['F'] = 1; 4735 #ifdef REGISTER_PREFIX 4736 alt_notend_table[REGISTER_PREFIX] = 1; 4737 #endif 4738 4739 /* We need to put '(' in alt_notend_table to handle 4740 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */ 4741 alt_notend_table['('] = 1; 4742 4743 /* We need to put '@' in alt_notend_table to handle 4744 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */ 4745 alt_notend_table['@'] = 1; 4746 4747 /* We need to put digits in alt_notend_table to handle 4748 bfextu %d0{24:1},%d0 */ 4749 alt_notend_table['0'] = 1; 4750 alt_notend_table['1'] = 1; 4751 alt_notend_table['2'] = 1; 4752 alt_notend_table['3'] = 1; 4753 alt_notend_table['4'] = 1; 4754 alt_notend_table['5'] = 1; 4755 alt_notend_table['6'] = 1; 4756 alt_notend_table['7'] = 1; 4757 alt_notend_table['8'] = 1; 4758 alt_notend_table['9'] = 1; 4759 4760 #ifndef MIT_SYNTAX_ONLY 4761 /* Insert pseudo ops, these have to go into the opcode table since 4762 gas expects pseudo ops to start with a dot. */ 4763 { 4764 int n = 0; 4765 4766 while (mote_pseudo_table[n].poc_name) 4767 { 4768 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant)); 4769 hash_insert (op_hash, 4770 mote_pseudo_table[n].poc_name, (char *) hack); 4771 hack->m_operands = 0; 4772 hack->m_opnum = n; 4773 n++; 4774 } 4775 } 4776 #endif 4777 4778 init_regtable (); 4779 4780 #ifdef OBJ_ELF 4781 record_alignment (text_section, 2); 4782 record_alignment (data_section, 2); 4783 record_alignment (bss_section, 2); 4784 #endif 4785 } 4786 4787 4788 /* This is called when a label is defined. */ 4789 4790 void 4791 m68k_frob_label (symbolS *sym) 4792 { 4793 struct label_line *n; 4794 4795 n = (struct label_line *) xmalloc (sizeof *n); 4796 n->next = labels; 4797 n->label = sym; 4798 as_where (&n->file, &n->line); 4799 n->text = 0; 4800 labels = n; 4801 current_label = n; 4802 4803 #ifdef OBJ_ELF 4804 dwarf2_emit_label (sym); 4805 #endif 4806 } 4807 4808 /* This is called when a value that is not an instruction is emitted. */ 4809 4810 void 4811 m68k_flush_pending_output (void) 4812 { 4813 current_label = NULL; 4814 } 4815 4816 /* This is called at the end of the assembly, when the final value of 4817 the label is known. We warn if this is a text symbol aligned at an 4818 odd location. */ 4819 4820 void 4821 m68k_frob_symbol (symbolS *sym) 4822 { 4823 if (S_GET_SEGMENT (sym) == reg_section 4824 && (int) S_GET_VALUE (sym) < 0) 4825 { 4826 S_SET_SEGMENT (sym, absolute_section); 4827 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym)); 4828 } 4829 else if ((S_GET_VALUE (sym) & 1) != 0) 4830 { 4831 struct label_line *l; 4832 4833 for (l = labels; l != NULL; l = l->next) 4834 { 4835 if (l->label == sym) 4836 { 4837 if (l->text) 4838 as_warn_where (l->file, l->line, 4839 _("text label `%s' aligned to odd boundary"), 4840 S_GET_NAME (sym)); 4841 break; 4842 } 4843 } 4844 } 4845 } 4846 4847 /* This is called if we go in or out of MRI mode because of the .mri 4848 pseudo-op. */ 4849 4850 void 4851 m68k_mri_mode_change (int on) 4852 { 4853 if (on) 4854 { 4855 if (! flag_reg_prefix_optional) 4856 { 4857 flag_reg_prefix_optional = 1; 4858 #ifdef REGISTER_PREFIX 4859 init_regtable (); 4860 #endif 4861 } 4862 m68k_abspcadd = 1; 4863 if (! m68k_rel32_from_cmdline) 4864 m68k_rel32 = 0; 4865 } 4866 else 4867 { 4868 if (! reg_prefix_optional_seen) 4869 { 4870 #ifdef REGISTER_PREFIX_OPTIONAL 4871 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL; 4872 #else 4873 flag_reg_prefix_optional = 0; 4874 #endif 4875 #ifdef REGISTER_PREFIX 4876 init_regtable (); 4877 #endif 4878 } 4879 m68k_abspcadd = 0; 4880 if (! m68k_rel32_from_cmdline) 4881 m68k_rel32 = 1; 4882 } 4883 } 4884 4885 char * 4886 md_atof (int type, char *litP, int *sizeP) 4887 { 4888 return ieee_md_atof (type, litP, sizeP, TRUE); 4889 } 4890 4891 void 4892 md_number_to_chars (char *buf, valueT val, int n) 4893 { 4894 number_to_chars_bigendian (buf, val, n); 4895 } 4896 4897 void 4898 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 4899 { 4900 offsetT val = *valP; 4901 addressT upper_limit; 4902 offsetT lower_limit; 4903 4904 /* This is unnecessary but it convinces the native rs6000 compiler 4905 to generate the code we want. */ 4906 char *buf = fixP->fx_frag->fr_literal; 4907 buf += fixP->fx_where; 4908 /* End ibm compiler workaround. */ 4909 4910 val = SEXT (val); 4911 4912 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) 4913 fixP->fx_done = 1; 4914 4915 #ifdef OBJ_ELF 4916 if (fixP->fx_addsy) 4917 { 4918 memset (buf, 0, fixP->fx_size); 4919 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4920 4921 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4922 && !S_IS_DEFINED (fixP->fx_addsy) 4923 && !S_IS_WEAK (fixP->fx_addsy)) 4924 S_SET_WEAK (fixP->fx_addsy); 4925 4926 switch (fixP->fx_r_type) 4927 { 4928 case BFD_RELOC_68K_TLS_GD32: 4929 case BFD_RELOC_68K_TLS_GD16: 4930 case BFD_RELOC_68K_TLS_GD8: 4931 case BFD_RELOC_68K_TLS_LDM32: 4932 case BFD_RELOC_68K_TLS_LDM16: 4933 case BFD_RELOC_68K_TLS_LDM8: 4934 case BFD_RELOC_68K_TLS_LDO32: 4935 case BFD_RELOC_68K_TLS_LDO16: 4936 case BFD_RELOC_68K_TLS_LDO8: 4937 case BFD_RELOC_68K_TLS_IE32: 4938 case BFD_RELOC_68K_TLS_IE16: 4939 case BFD_RELOC_68K_TLS_IE8: 4940 case BFD_RELOC_68K_TLS_LE32: 4941 case BFD_RELOC_68K_TLS_LE16: 4942 case BFD_RELOC_68K_TLS_LE8: 4943 S_SET_THREAD_LOCAL (fixP->fx_addsy); 4944 break; 4945 4946 default: 4947 break; 4948 } 4949 4950 return; 4951 } 4952 #elif defined(OBJ_AOUT) 4953 /* PR gas/3041 Do not fix frags referencing a weak symbol. */ 4954 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)) 4955 { 4956 memset (buf, 0, fixP->fx_size); 4957 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 4958 return; 4959 } 4960 #endif 4961 4962 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 4963 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 4964 return; 4965 4966 switch (fixP->fx_size) 4967 { 4968 /* The cast to offsetT below are necessary to make code 4969 correct for machines where ints are smaller than offsetT. */ 4970 case 1: 4971 *buf++ = val; 4972 upper_limit = 0x7f; 4973 lower_limit = - (offsetT) 0x80; 4974 break; 4975 case 2: 4976 *buf++ = (val >> 8); 4977 *buf++ = val; 4978 upper_limit = 0x7fff; 4979 lower_limit = - (offsetT) 0x8000; 4980 break; 4981 case 4: 4982 *buf++ = (val >> 24); 4983 *buf++ = (val >> 16); 4984 *buf++ = (val >> 8); 4985 *buf++ = val; 4986 upper_limit = 0x7fffffff; 4987 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ 4988 break; 4989 default: 4990 BAD_CASE (fixP->fx_size); 4991 } 4992 4993 /* Fix up a negative reloc. */ 4994 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL) 4995 { 4996 fixP->fx_addsy = fixP->fx_subsy; 4997 fixP->fx_subsy = NULL; 4998 fixP->fx_tcbit = 1; 4999 } 5000 5001 /* For non-pc-relative values, it's conceivable we might get something 5002 like "0xff" for a byte field. So extend the upper part of the range 5003 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff", 5004 so that we can do any range checking at all. */ 5005 if (! fixP->fx_pcrel && ! fixP->fx_signed) 5006 upper_limit = upper_limit * 2 + 1; 5007 5008 if ((addressT) val > upper_limit 5009 && (val > 0 || val < lower_limit)) 5010 as_bad_where (fixP->fx_file, fixP->fx_line, 5011 _("value %ld out of range"), (long)val); 5012 5013 /* A one byte PC-relative reloc means a short branch. We can't use 5014 a short branch with a value of 0 or -1, because those indicate 5015 different opcodes (branches with longer offsets). fixup_segment 5016 in write.c may have clobbered fx_pcrel, so we need to examine the 5017 reloc type. */ 5018 if ((fixP->fx_pcrel 5019 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 5020 && fixP->fx_size == 1 5021 && (fixP->fx_addsy == NULL 5022 || S_IS_DEFINED (fixP->fx_addsy)) 5023 && (val == 0 || val == -1)) 5024 as_bad_where (fixP->fx_file, fixP->fx_line, 5025 _("invalid byte branch offset")); 5026 } 5027 5028 /* *fragP has been relaxed to its final size, and now needs to have 5029 the bytes inside it modified to conform to the new size There is UGLY 5030 MAGIC here. .. 5031 */ 5032 static void 5033 md_convert_frag_1 (fragS *fragP) 5034 { 5035 long disp; 5036 fixS *fixP = NULL; 5037 5038 /* Address in object code of the displacement. */ 5039 register int object_address = fragP->fr_fix + fragP->fr_address; 5040 5041 /* Address in gas core of the place to store the displacement. */ 5042 /* This convinces the native rs6000 compiler to generate the code we 5043 want. */ 5044 register char *buffer_address = fragP->fr_literal; 5045 buffer_address += fragP->fr_fix; 5046 /* End ibm compiler workaround. */ 5047 5048 /* The displacement of the address, from current location. */ 5049 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; 5050 disp = (disp + fragP->fr_offset) - object_address; 5051 5052 switch (fragP->fr_subtype) 5053 { 5054 case TAB (BRANCHBWL, BYTE): 5055 case TAB (BRABSJUNC, BYTE): 5056 case TAB (BRABSJCOND, BYTE): 5057 case TAB (BRANCHBW, BYTE): 5058 case TAB (BRANCHBWPL, BYTE): 5059 know (issbyte (disp)); 5060 if (disp == 0) 5061 as_bad_where (fragP->fr_file, fragP->fr_line, 5062 _("short branch with zero offset: use :w")); 5063 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5064 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5065 fixP->fx_pcrel_adjust = -1; 5066 break; 5067 case TAB (BRANCHBWL, SHORT): 5068 case TAB (BRABSJUNC, SHORT): 5069 case TAB (BRABSJCOND, SHORT): 5070 case TAB (BRANCHBW, SHORT): 5071 case TAB (BRANCHBWPL, SHORT): 5072 fragP->fr_opcode[1] = 0x00; 5073 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5074 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5075 fragP->fr_fix += 2; 5076 break; 5077 case TAB (BRANCHBWL, LONG): 5078 fragP->fr_opcode[1] = (char) 0xFF; 5079 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5080 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5081 fragP->fr_fix += 4; 5082 break; 5083 case TAB (BRANCHBWPL, LONG): 5084 /* Here we are converting an unconditional branch into a pair of 5085 conditional branches, in order to get the range. */ 5086 fragP->fr_opcode[0] = 0x66; /* bne */ 5087 fragP->fr_opcode[1] = 0xFF; 5088 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5089 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5090 fixP->fx_file = fragP->fr_file; 5091 fixP->fx_line = fragP->fr_line; 5092 fragP->fr_fix += 4; /* Skip first offset */ 5093 buffer_address += 4; 5094 *buffer_address++ = 0x67; /* beq */ 5095 *buffer_address++ = 0xff; 5096 fragP->fr_fix += 2; /* Skip second branch opcode */ 5097 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5098 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5099 fragP->fr_fix += 4; 5100 break; 5101 case TAB (BRABSJUNC, LONG): 5102 if (fragP->fr_opcode[0] == 0x61) /* jbsr */ 5103 { 5104 if (flag_keep_pcrel) 5105 as_bad_where (fragP->fr_file, fragP->fr_line, 5106 _("Conversion of PC relative BSR to absolute JSR")); 5107 fragP->fr_opcode[0] = 0x4E; 5108 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ 5109 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5110 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5111 fragP->fr_fix += 4; 5112 } 5113 else if (fragP->fr_opcode[0] == 0x60) /* jbra */ 5114 { 5115 if (flag_keep_pcrel) 5116 as_bad_where (fragP->fr_file, fragP->fr_line, 5117 _("Conversion of PC relative branch to absolute jump")); 5118 fragP->fr_opcode[0] = 0x4E; 5119 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ 5120 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5121 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5122 fragP->fr_fix += 4; 5123 } 5124 else 5125 { 5126 /* This cannot happen, because jbsr and jbra are the only two 5127 unconditional branches. */ 5128 abort (); 5129 } 5130 break; 5131 case TAB (BRABSJCOND, LONG): 5132 if (flag_keep_pcrel) 5133 as_bad_where (fragP->fr_file, fragP->fr_line, 5134 _("Conversion of PC relative conditional branch to absolute jump")); 5135 5136 /* Only Bcc 68000 instructions can come here 5137 Change bcc into b!cc/jmp absl long. */ 5138 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ 5139 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ 5140 5141 /* JF: these used to be fr_opcode[2,3], but they may be in a 5142 different frag, in which case referring to them is a no-no. 5143 Only fr_opcode[0,1] are guaranteed to work. */ 5144 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ 5145 *buffer_address++ = (char) 0xf9; 5146 fragP->fr_fix += 2; /* Account for jmp instruction. */ 5147 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5148 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5149 fragP->fr_fix += 4; 5150 break; 5151 case TAB (FBRANCH, SHORT): 5152 know ((fragP->fr_opcode[1] & 0x40) == 0); 5153 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5154 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5155 fragP->fr_fix += 2; 5156 break; 5157 case TAB (FBRANCH, LONG): 5158 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ 5159 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5160 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5161 fragP->fr_fix += 4; 5162 break; 5163 case TAB (DBCCLBR, SHORT): 5164 case TAB (DBCCABSJ, SHORT): 5165 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5166 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5167 fragP->fr_fix += 2; 5168 break; 5169 case TAB (DBCCLBR, LONG): 5170 /* Only DBcc instructions can come here. 5171 Change dbcc into dbcc/bral. 5172 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5173 if (flag_keep_pcrel) 5174 as_bad_where (fragP->fr_file, fragP->fr_line, 5175 _("Conversion of DBcc to absolute jump")); 5176 5177 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5178 *buffer_address++ = 0x04; 5179 *buffer_address++ = 0x60; /* Put in bra pc+6. */ 5180 *buffer_address++ = 0x06; 5181 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ 5182 *buffer_address++ = (char) 0xff; 5183 5184 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5185 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5186 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5187 fragP->fr_fix += 4; 5188 break; 5189 case TAB (DBCCABSJ, LONG): 5190 /* Only DBcc instructions can come here. 5191 Change dbcc into dbcc/jmp. 5192 JF: these used to be fr_opcode[2-7], but that's wrong. */ 5193 if (flag_keep_pcrel) 5194 as_bad_where (fragP->fr_file, fragP->fr_line, 5195 _("Conversion of PC relative conditional branch to absolute jump")); 5196 5197 *buffer_address++ = 0x00; /* Branch offset = 4. */ 5198 *buffer_address++ = 0x04; 5199 *buffer_address++ = 0x60; /* Put in bra pc + 6. */ 5200 *buffer_address++ = 0x06; 5201 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ 5202 *buffer_address++ = (char) 0xf9; 5203 5204 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ 5205 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5206 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5207 fragP->fr_fix += 4; 5208 break; 5209 case TAB (PCREL1632, SHORT): 5210 fragP->fr_opcode[1] &= ~0x3F; 5211 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */ 5212 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5213 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5214 fragP->fr_fix += 2; 5215 break; 5216 case TAB (PCREL1632, LONG): 5217 /* Already set to mode 7.3; this indicates: PC indirect with 5218 suppressed index, 32-bit displacement. */ 5219 *buffer_address++ = 0x01; 5220 *buffer_address++ = 0x70; 5221 fragP->fr_fix += 2; 5222 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5223 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5224 fixP->fx_pcrel_adjust = 2; 5225 fragP->fr_fix += 4; 5226 break; 5227 case TAB (PCINDEX, BYTE): 5228 gas_assert (fragP->fr_fix >= 2); 5229 buffer_address[-2] &= ~1; 5230 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol, 5231 fragP->fr_offset, 1, RELAX_RELOC_PC8); 5232 fixP->fx_pcrel_adjust = 1; 5233 break; 5234 case TAB (PCINDEX, SHORT): 5235 gas_assert (fragP->fr_fix >= 2); 5236 buffer_address[-2] |= 0x1; 5237 buffer_address[-1] = 0x20; 5238 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol, 5239 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5240 fixP->fx_pcrel_adjust = 2; 5241 fragP->fr_fix += 2; 5242 break; 5243 case TAB (PCINDEX, LONG): 5244 gas_assert (fragP->fr_fix >= 2); 5245 buffer_address[-2] |= 0x1; 5246 buffer_address[-1] = 0x30; 5247 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol, 5248 fragP->fr_offset, 1, RELAX_RELOC_PC32); 5249 fixP->fx_pcrel_adjust = 2; 5250 fragP->fr_fix += 4; 5251 break; 5252 case TAB (ABSTOPCREL, SHORT): 5253 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 5254 fragP->fr_offset, 1, RELAX_RELOC_PC16); 5255 fragP->fr_fix += 2; 5256 break; 5257 case TAB (ABSTOPCREL, LONG): 5258 if (flag_keep_pcrel) 5259 as_bad_where (fragP->fr_file, fragP->fr_line, 5260 _("Conversion of PC relative displacement to absolute")); 5261 /* The thing to do here is force it to ABSOLUTE LONG, since 5262 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ 5263 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) 5264 abort (); 5265 fragP->fr_opcode[1] &= ~0x3F; 5266 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 5267 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, 5268 fragP->fr_offset, 0, RELAX_RELOC_ABS32); 5269 fragP->fr_fix += 4; 5270 break; 5271 } 5272 if (fixP) 5273 { 5274 fixP->fx_file = fragP->fr_file; 5275 fixP->fx_line = fragP->fr_line; 5276 } 5277 } 5278 5279 void 5280 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, 5281 segT sec ATTRIBUTE_UNUSED, 5282 fragS *fragP) 5283 { 5284 md_convert_frag_1 (fragP); 5285 } 5286 5287 /* Force truly undefined symbols to their maximum size, and generally set up 5288 the frag list to be relaxed 5289 */ 5290 int 5291 md_estimate_size_before_relax (fragS *fragP, segT segment) 5292 { 5293 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */ 5294 switch (fragP->fr_subtype) 5295 { 5296 case TAB (BRANCHBWL, SZ_UNDEF): 5297 case TAB (BRANCHBWPL, SZ_UNDEF): 5298 case TAB (BRABSJUNC, SZ_UNDEF): 5299 case TAB (BRABSJCOND, SZ_UNDEF): 5300 { 5301 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5302 && relaxable_symbol (fragP->fr_symbol)) 5303 { 5304 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5305 } 5306 else if (flag_short_refs) 5307 { 5308 /* Symbol is undefined and we want short ref. */ 5309 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5310 } 5311 else 5312 { 5313 /* Symbol is still undefined. Make it LONG. */ 5314 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5315 } 5316 break; 5317 } 5318 5319 case TAB (BRANCHBW, SZ_UNDEF): 5320 { 5321 if (S_GET_SEGMENT (fragP->fr_symbol) == segment 5322 && relaxable_symbol (fragP->fr_symbol)) 5323 { 5324 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE); 5325 } 5326 else 5327 { 5328 /* Symbol is undefined and we don't have long branches. */ 5329 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5330 } 5331 break; 5332 } 5333 5334 case TAB (FBRANCH, SZ_UNDEF): 5335 case TAB (DBCCLBR, SZ_UNDEF): 5336 case TAB (DBCCABSJ, SZ_UNDEF): 5337 case TAB (PCREL1632, SZ_UNDEF): 5338 { 5339 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5340 && relaxable_symbol (fragP->fr_symbol)) 5341 || flag_short_refs) 5342 { 5343 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5344 } 5345 else 5346 { 5347 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG); 5348 } 5349 break; 5350 } 5351 5352 case TAB (PCINDEX, SZ_UNDEF): 5353 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5354 && relaxable_symbol (fragP->fr_symbol))) 5355 { 5356 fragP->fr_subtype = TAB (PCINDEX, BYTE); 5357 } 5358 else 5359 { 5360 fragP->fr_subtype = TAB (PCINDEX, LONG); 5361 } 5362 break; 5363 5364 case TAB (ABSTOPCREL, SZ_UNDEF): 5365 { 5366 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment 5367 && relaxable_symbol (fragP->fr_symbol))) 5368 { 5369 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT); 5370 } 5371 else 5372 { 5373 fragP->fr_subtype = TAB (ABSTOPCREL, LONG); 5374 } 5375 break; 5376 } 5377 5378 default: 5379 break; 5380 } 5381 5382 /* Now that SZ_UNDEF are taken care of, check others. */ 5383 switch (fragP->fr_subtype) 5384 { 5385 case TAB (BRANCHBWL, BYTE): 5386 case TAB (BRABSJUNC, BYTE): 5387 case TAB (BRABSJCOND, BYTE): 5388 case TAB (BRANCHBW, BYTE): 5389 /* We can't do a short jump to the next instruction, so in that 5390 case we force word mode. If the symbol is at the start of a 5391 frag, and it is the next frag with any data in it (usually 5392 this is just the next frag, but assembler listings may 5393 introduce empty frags), we must use word mode. */ 5394 if (fragP->fr_symbol) 5395 { 5396 fragS *sym_frag; 5397 5398 sym_frag = symbol_get_frag (fragP->fr_symbol); 5399 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address) 5400 { 5401 fragS *l; 5402 5403 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next) 5404 if (l->fr_fix != 0) 5405 break; 5406 if (l == sym_frag) 5407 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT); 5408 } 5409 } 5410 break; 5411 default: 5412 break; 5413 } 5414 return md_relax_table[fragP->fr_subtype].rlx_length; 5415 } 5416 5417 #if defined(OBJ_AOUT) | defined(OBJ_BOUT) 5418 /* the bit-field entries in the relocation_info struct plays hell 5419 with the byte-order problems of cross-assembly. So as a hack, 5420 I added this mach. dependent ri twiddler. Ugly, but it gets 5421 you there. -KWK */ 5422 /* on m68k: first 4 bytes are normal unsigned long, next three bytes 5423 are symbolnum, most sig. byte first. Last byte is broken up with 5424 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower 5425 nibble as nuthin. (on Sun 3 at least) */ 5426 /* Translate the internal relocation information into target-specific 5427 format. */ 5428 #ifdef comment 5429 void 5430 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri) 5431 { 5432 /* This is easy. */ 5433 md_number_to_chars (the_bytes, ri->r_address, 4); 5434 /* Now the fun stuff. */ 5435 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; 5436 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; 5437 the_bytes[6] = ri->r_symbolnum & 0x0ff; 5438 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) 5439 | ((ri->r_length << 5) & 0x60) 5440 | ((ri->r_extern << 4) & 0x10)); 5441 } 5442 5443 #endif 5444 5445 #endif /* OBJ_AOUT or OBJ_BOUT */ 5446 5447 #ifndef WORKING_DOT_WORD 5448 int md_short_jump_size = 4; 5449 int md_long_jump_size = 6; 5450 5451 void 5452 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr, 5453 fragS *frag ATTRIBUTE_UNUSED, 5454 symbolS *to_symbol ATTRIBUTE_UNUSED) 5455 { 5456 valueT offset; 5457 5458 offset = to_addr - (from_addr + 2); 5459 5460 md_number_to_chars (ptr, (valueT) 0x6000, 2); 5461 md_number_to_chars (ptr + 2, (valueT) offset, 2); 5462 } 5463 5464 void 5465 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr, 5466 fragS *frag, symbolS *to_symbol) 5467 { 5468 valueT offset; 5469 5470 if (!HAVE_LONG_BRANCH (current_architecture)) 5471 { 5472 if (flag_keep_pcrel) 5473 as_fatal (_("Tried to convert PC relative branch to absolute jump")); 5474 offset = to_addr - S_GET_VALUE (to_symbol); 5475 md_number_to_chars (ptr, (valueT) 0x4EF9, 2); 5476 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5477 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0, 5478 0, NO_RELOC); 5479 } 5480 else 5481 { 5482 offset = to_addr - (from_addr + 2); 5483 md_number_to_chars (ptr, (valueT) 0x60ff, 2); 5484 md_number_to_chars (ptr + 2, (valueT) offset, 4); 5485 } 5486 } 5487 5488 #endif 5489 5490 /* Different values of OK tell what its OK to return. Things that 5491 aren't OK are an error (what a shock, no?) 5492 5493 0: Everything is OK 5494 10: Absolute 1:8 only 5495 20: Absolute 0:7 only 5496 30: absolute 0:15 only 5497 40: Absolute 0:31 only 5498 50: absolute 0:127 only 5499 55: absolute -64:63 only 5500 60: absolute -128:127 only 5501 65: absolute 0:511 only 5502 70: absolute 0:4095 only 5503 80: absolute -1, 1:7 only 5504 90: No bignums. */ 5505 5506 static int 5507 get_num (struct m68k_exp *exp, int ok) 5508 { 5509 if (exp->exp.X_op == O_absent) 5510 { 5511 /* Do the same thing the VAX asm does. */ 5512 op (exp) = O_constant; 5513 adds (exp) = 0; 5514 subs (exp) = 0; 5515 offs (exp) = 0; 5516 if (ok == 10) 5517 { 5518 as_warn (_("expression out of range: defaulting to 1")); 5519 offs (exp) = 1; 5520 } 5521 } 5522 else if (exp->exp.X_op == O_constant) 5523 { 5524 switch (ok) 5525 { 5526 case 10: 5527 if ((valueT) TRUNC (offs (exp)) - 1 > 7) 5528 { 5529 as_warn (_("expression out of range: defaulting to 1")); 5530 offs (exp) = 1; 5531 } 5532 break; 5533 case 20: 5534 if ((valueT) TRUNC (offs (exp)) > 7) 5535 goto outrange; 5536 break; 5537 case 30: 5538 if ((valueT) TRUNC (offs (exp)) > 15) 5539 goto outrange; 5540 break; 5541 case 40: 5542 if ((valueT) TRUNC (offs (exp)) > 32) 5543 goto outrange; 5544 break; 5545 case 50: 5546 if ((valueT) TRUNC (offs (exp)) > 127) 5547 goto outrange; 5548 break; 5549 case 55: 5550 if ((valueT) SEXT (offs (exp)) + 64 > 127) 5551 goto outrange; 5552 break; 5553 case 60: 5554 if ((valueT) SEXT (offs (exp)) + 128 > 255) 5555 goto outrange; 5556 break; 5557 case 65: 5558 if ((valueT) TRUNC (offs (exp)) > 511) 5559 goto outrange; 5560 break; 5561 case 70: 5562 if ((valueT) TRUNC (offs (exp)) > 4095) 5563 { 5564 outrange: 5565 as_warn (_("expression out of range: defaulting to 0")); 5566 offs (exp) = 0; 5567 } 5568 break; 5569 case 80: 5570 if ((valueT) TRUNC (offs (exp)) != 0xffffffff 5571 && (valueT) TRUNC (offs (exp)) - 1 > 6) 5572 { 5573 as_warn (_("expression out of range: defaulting to 1")); 5574 offs (exp) = 1; 5575 } 5576 break; 5577 default: 5578 break; 5579 } 5580 } 5581 else if (exp->exp.X_op == O_big) 5582 { 5583 if (offs (exp) <= 0 /* flonum. */ 5584 && (ok == 90 /* no bignums */ 5585 || (ok > 10 /* Small-int ranges including 0 ok. */ 5586 /* If we have a flonum zero, a zero integer should 5587 do as well (e.g., in moveq). */ 5588 && generic_floating_point_number.exponent == 0 5589 && generic_floating_point_number.low[0] == 0))) 5590 { 5591 /* HACK! Turn it into a long. */ 5592 LITTLENUM_TYPE words[6]; 5593 5594 gen_to_words (words, 2, 8L); /* These numbers are magic! */ 5595 op (exp) = O_constant; 5596 adds (exp) = 0; 5597 subs (exp) = 0; 5598 offs (exp) = words[1] | (words[0] << 16); 5599 } 5600 else if (ok != 0) 5601 { 5602 op (exp) = O_constant; 5603 adds (exp) = 0; 5604 subs (exp) = 0; 5605 offs (exp) = (ok == 10) ? 1 : 0; 5606 as_warn (_("Can't deal with expression; defaulting to %ld"), 5607 (long) offs (exp)); 5608 } 5609 } 5610 else 5611 { 5612 if (ok >= 10 && ok <= 80) 5613 { 5614 op (exp) = O_constant; 5615 adds (exp) = 0; 5616 subs (exp) = 0; 5617 offs (exp) = (ok == 10) ? 1 : 0; 5618 as_warn (_("Can't deal with expression; defaulting to %ld"), 5619 (long) offs (exp)); 5620 } 5621 } 5622 5623 if (exp->size != SIZE_UNSPEC) 5624 { 5625 switch (exp->size) 5626 { 5627 case SIZE_UNSPEC: 5628 case SIZE_LONG: 5629 break; 5630 case SIZE_BYTE: 5631 if (!isbyte (offs (exp))) 5632 as_warn (_("expression doesn't fit in BYTE")); 5633 break; 5634 case SIZE_WORD: 5635 if (!isword (offs (exp))) 5636 as_warn (_("expression doesn't fit in WORD")); 5637 break; 5638 } 5639 } 5640 5641 return offs (exp); 5642 } 5643 5644 /* These are the back-ends for the various machine dependent pseudo-ops. */ 5645 5646 static void 5647 s_data1 (int ignore ATTRIBUTE_UNUSED) 5648 { 5649 subseg_set (data_section, 1); 5650 demand_empty_rest_of_line (); 5651 } 5652 5653 static void 5654 s_data2 (int ignore ATTRIBUTE_UNUSED) 5655 { 5656 subseg_set (data_section, 2); 5657 demand_empty_rest_of_line (); 5658 } 5659 5660 static void 5661 s_bss (int ignore ATTRIBUTE_UNUSED) 5662 { 5663 /* We don't support putting frags in the BSS segment, we fake it 5664 by marking in_bss, then looking at s_skip for clues. */ 5665 5666 subseg_set (bss_section, 0); 5667 demand_empty_rest_of_line (); 5668 } 5669 5670 static void 5671 s_even (int ignore ATTRIBUTE_UNUSED) 5672 { 5673 register int temp; 5674 register long temp_fill; 5675 5676 temp = 1; /* JF should be 2? */ 5677 temp_fill = get_absolute_expression (); 5678 if (!need_pass_2) /* Never make frag if expect extra pass. */ 5679 frag_align (temp, (int) temp_fill, 0); 5680 demand_empty_rest_of_line (); 5681 record_alignment (now_seg, temp); 5682 } 5683 5684 static void 5685 s_proc (int ignore ATTRIBUTE_UNUSED) 5686 { 5687 demand_empty_rest_of_line (); 5688 } 5689 5690 /* Pseudo-ops handled for MRI compatibility. */ 5691 5692 /* This function returns non-zero if the argument is a conditional 5693 pseudo-op. This is called when checking whether a pending 5694 alignment is needed. */ 5695 5696 int 5697 m68k_conditional_pseudoop (pseudo_typeS *pop) 5698 { 5699 return (pop->poc_handler == s_mri_if 5700 || pop->poc_handler == s_mri_else); 5701 } 5702 5703 /* Handle an MRI style chip specification. */ 5704 5705 static void 5706 mri_chip (void) 5707 { 5708 char *s; 5709 char c; 5710 int i; 5711 5712 s = input_line_pointer; 5713 /* We can't use get_symbol_end since the processor names are not proper 5714 symbols. */ 5715 while (is_part_of_name (c = *input_line_pointer++)) 5716 ; 5717 *--input_line_pointer = 0; 5718 for (i = 0; m68k_cpus[i].name; i++) 5719 if (strcasecmp (s, m68k_cpus[i].name) == 0) 5720 break; 5721 if (!m68k_cpus[i].name) 5722 { 5723 as_bad (_("%s: unrecognized processor name"), s); 5724 *input_line_pointer = c; 5725 ignore_rest_of_line (); 5726 return; 5727 } 5728 *input_line_pointer = c; 5729 5730 if (*input_line_pointer == '/') 5731 current_architecture = 0; 5732 else 5733 current_architecture &= m68881 | m68851; 5734 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851); 5735 control_regs = m68k_cpus[i].control_regs; 5736 5737 while (*input_line_pointer == '/') 5738 { 5739 ++input_line_pointer; 5740 s = input_line_pointer; 5741 /* We can't use get_symbol_end since the processor names are not 5742 proper symbols. */ 5743 while (is_part_of_name (c = *input_line_pointer++)) 5744 ; 5745 *--input_line_pointer = 0; 5746 if (strcmp (s, "68881") == 0) 5747 current_architecture |= m68881; 5748 else if (strcmp (s, "68851") == 0) 5749 current_architecture |= m68851; 5750 *input_line_pointer = c; 5751 } 5752 } 5753 5754 /* The MRI CHIP pseudo-op. */ 5755 5756 static void 5757 s_chip (int ignore ATTRIBUTE_UNUSED) 5758 { 5759 char *stop = NULL; 5760 char stopc; 5761 5762 if (flag_mri) 5763 stop = mri_comment_field (&stopc); 5764 mri_chip (); 5765 if (flag_mri) 5766 mri_comment_end (stop, stopc); 5767 demand_empty_rest_of_line (); 5768 } 5769 5770 /* The MRI FOPT pseudo-op. */ 5771 5772 static void 5773 s_fopt (int ignore ATTRIBUTE_UNUSED) 5774 { 5775 SKIP_WHITESPACE (); 5776 5777 if (strncasecmp (input_line_pointer, "ID=", 3) == 0) 5778 { 5779 int temp; 5780 5781 input_line_pointer += 3; 5782 temp = get_absolute_expression (); 5783 if (temp < 0 || temp > 7) 5784 as_bad (_("bad coprocessor id")); 5785 else 5786 m68k_float_copnum = COP0 + temp; 5787 } 5788 else 5789 { 5790 as_bad (_("unrecognized fopt option")); 5791 ignore_rest_of_line (); 5792 return; 5793 } 5794 5795 demand_empty_rest_of_line (); 5796 } 5797 5798 /* The structure used to handle the MRI OPT pseudo-op. */ 5799 5800 struct opt_action 5801 { 5802 /* The name of the option. */ 5803 const char *name; 5804 5805 /* If this is not NULL, just call this function. The first argument 5806 is the ARG field of this structure, the second argument is 5807 whether the option was negated. */ 5808 void (*pfn) (int arg, int on); 5809 5810 /* If this is not NULL, and the PFN field is NULL, set the variable 5811 this points to. Set it to the ARG field if the option was not 5812 negated, and the NOTARG field otherwise. */ 5813 int *pvar; 5814 5815 /* The value to pass to PFN or to assign to *PVAR. */ 5816 int arg; 5817 5818 /* The value to assign to *PVAR if the option is negated. If PFN is 5819 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then 5820 the option may not be negated. */ 5821 int notarg; 5822 }; 5823 5824 /* The table used to handle the MRI OPT pseudo-op. */ 5825 5826 static void skip_to_comma (int, int); 5827 static void opt_nest (int, int); 5828 static void opt_chip (int, int); 5829 static void opt_list (int, int); 5830 static void opt_list_symbols (int, int); 5831 5832 static const struct opt_action opt_table[] = 5833 { 5834 { "abspcadd", 0, &m68k_abspcadd, 1, 0 }, 5835 5836 /* We do relaxing, so there is little use for these options. */ 5837 { "b", 0, 0, 0, 0 }, 5838 { "brs", 0, 0, 0, 0 }, 5839 { "brb", 0, 0, 0, 0 }, 5840 { "brl", 0, 0, 0, 0 }, 5841 { "brw", 0, 0, 0, 0 }, 5842 5843 { "c", 0, 0, 0, 0 }, 5844 { "cex", 0, 0, 0, 0 }, 5845 { "case", 0, &symbols_case_sensitive, 1, 0 }, 5846 { "cl", 0, 0, 0, 0 }, 5847 { "cre", 0, 0, 0, 0 }, 5848 { "d", 0, &flag_keep_locals, 1, 0 }, 5849 { "e", 0, 0, 0, 0 }, 5850 { "f", 0, &flag_short_refs, 1, 0 }, 5851 { "frs", 0, &flag_short_refs, 1, 0 }, 5852 { "frl", 0, &flag_short_refs, 0, 1 }, 5853 { "g", 0, 0, 0, 0 }, 5854 { "i", 0, 0, 0, 0 }, 5855 { "m", 0, 0, 0, 0 }, 5856 { "mex", 0, 0, 0, 0 }, 5857 { "mc", 0, 0, 0, 0 }, 5858 { "md", 0, 0, 0, 0 }, 5859 { "nest", opt_nest, 0, 0, 0 }, 5860 { "next", skip_to_comma, 0, 0, 0 }, 5861 { "o", 0, 0, 0, 0 }, 5862 { "old", 0, 0, 0, 0 }, 5863 { "op", skip_to_comma, 0, 0, 0 }, 5864 { "pco", 0, 0, 0, 0 }, 5865 { "p", opt_chip, 0, 0, 0 }, 5866 { "pcr", 0, 0, 0, 0 }, 5867 { "pcs", 0, 0, 0, 0 }, 5868 { "r", 0, 0, 0, 0 }, 5869 { "quick", 0, &m68k_quick, 1, 0 }, 5870 { "rel32", 0, &m68k_rel32, 1, 0 }, 5871 { "s", opt_list, 0, 0, 0 }, 5872 { "t", opt_list_symbols, 0, 0, 0 }, 5873 { "w", 0, &flag_no_warnings, 0, 1 }, 5874 { "x", 0, 0, 0, 0 } 5875 }; 5876 5877 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0])) 5878 5879 /* The MRI OPT pseudo-op. */ 5880 5881 static void 5882 s_opt (int ignore ATTRIBUTE_UNUSED) 5883 { 5884 do 5885 { 5886 int t; 5887 char *s; 5888 char c; 5889 int i; 5890 const struct opt_action *o; 5891 5892 SKIP_WHITESPACE (); 5893 5894 t = 1; 5895 if (*input_line_pointer == '-') 5896 { 5897 ++input_line_pointer; 5898 t = 0; 5899 } 5900 else if (strncasecmp (input_line_pointer, "NO", 2) == 0) 5901 { 5902 input_line_pointer += 2; 5903 t = 0; 5904 } 5905 5906 s = input_line_pointer; 5907 c = get_symbol_end (); 5908 5909 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++) 5910 { 5911 if (strcasecmp (s, o->name) == 0) 5912 { 5913 if (o->pfn) 5914 { 5915 /* Restore input_line_pointer now in case the option 5916 takes arguments. */ 5917 *input_line_pointer = c; 5918 (*o->pfn) (o->arg, t); 5919 } 5920 else if (o->pvar != NULL) 5921 { 5922 if (! t && o->arg == o->notarg) 5923 as_bad (_("option `%s' may not be negated"), s); 5924 *input_line_pointer = c; 5925 *o->pvar = t ? o->arg : o->notarg; 5926 } 5927 else 5928 *input_line_pointer = c; 5929 break; 5930 } 5931 } 5932 if (i >= OPTCOUNT) 5933 { 5934 as_bad (_("option `%s' not recognized"), s); 5935 *input_line_pointer = c; 5936 } 5937 } 5938 while (*input_line_pointer++ == ','); 5939 5940 /* Move back to terminating character. */ 5941 --input_line_pointer; 5942 demand_empty_rest_of_line (); 5943 } 5944 5945 /* Skip ahead to a comma. This is used for OPT options which we do 5946 not support and which take arguments. */ 5947 5948 static void 5949 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5950 { 5951 while (*input_line_pointer != ',' 5952 && ! is_end_of_line[(unsigned char) *input_line_pointer]) 5953 ++input_line_pointer; 5954 } 5955 5956 /* Handle the OPT NEST=depth option. */ 5957 5958 static void 5959 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5960 { 5961 if (*input_line_pointer != '=') 5962 { 5963 as_bad (_("bad format of OPT NEST=depth")); 5964 return; 5965 } 5966 5967 ++input_line_pointer; 5968 max_macro_nest = get_absolute_expression (); 5969 } 5970 5971 /* Handle the OPT P=chip option. */ 5972 5973 static void 5974 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED) 5975 { 5976 if (*input_line_pointer != '=') 5977 { 5978 /* This is just OPT P, which we do not support. */ 5979 return; 5980 } 5981 5982 ++input_line_pointer; 5983 mri_chip (); 5984 } 5985 5986 /* Handle the OPT S option. */ 5987 5988 static void 5989 opt_list (int arg ATTRIBUTE_UNUSED, int on) 5990 { 5991 listing_list (on); 5992 } 5993 5994 /* Handle the OPT T option. */ 5995 5996 static void 5997 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on) 5998 { 5999 if (on) 6000 listing |= LISTING_SYMBOLS; 6001 else 6002 listing &= ~LISTING_SYMBOLS; 6003 } 6004 6005 /* Handle the MRI REG pseudo-op. */ 6006 6007 static void 6008 s_reg (int ignore ATTRIBUTE_UNUSED) 6009 { 6010 char *s; 6011 int c; 6012 struct m68k_op rop; 6013 int mask; 6014 char *stop = NULL; 6015 char stopc; 6016 6017 if (line_label == NULL) 6018 { 6019 as_bad (_("missing label")); 6020 ignore_rest_of_line (); 6021 return; 6022 } 6023 6024 if (flag_mri) 6025 stop = mri_comment_field (&stopc); 6026 6027 SKIP_WHITESPACE (); 6028 6029 s = input_line_pointer; 6030 while (ISALNUM (*input_line_pointer) 6031 #ifdef REGISTER_PREFIX 6032 || *input_line_pointer == REGISTER_PREFIX 6033 #endif 6034 || *input_line_pointer == '/' 6035 || *input_line_pointer == '-') 6036 ++input_line_pointer; 6037 c = *input_line_pointer; 6038 *input_line_pointer = '\0'; 6039 6040 if (m68k_ip_op (s, &rop) != 0) 6041 { 6042 if (rop.error == NULL) 6043 as_bad (_("bad register list")); 6044 else 6045 as_bad (_("bad register list: %s"), rop.error); 6046 *input_line_pointer = c; 6047 ignore_rest_of_line (); 6048 return; 6049 } 6050 6051 *input_line_pointer = c; 6052 6053 if (rop.mode == REGLST) 6054 mask = rop.mask; 6055 else if (rop.mode == DREG) 6056 mask = 1 << (rop.reg - DATA0); 6057 else if (rop.mode == AREG) 6058 mask = 1 << (rop.reg - ADDR0 + 8); 6059 else if (rop.mode == FPREG) 6060 mask = 1 << (rop.reg - FP0 + 16); 6061 else if (rop.mode == CONTROL 6062 && rop.reg == FPI) 6063 mask = 1 << 24; 6064 else if (rop.mode == CONTROL 6065 && rop.reg == FPS) 6066 mask = 1 << 25; 6067 else if (rop.mode == CONTROL 6068 && rop.reg == FPC) 6069 mask = 1 << 26; 6070 else 6071 { 6072 as_bad (_("bad register list")); 6073 ignore_rest_of_line (); 6074 return; 6075 } 6076 6077 S_SET_SEGMENT (line_label, reg_section); 6078 S_SET_VALUE (line_label, ~mask); 6079 symbol_set_frag (line_label, &zero_address_frag); 6080 6081 if (flag_mri) 6082 mri_comment_end (stop, stopc); 6083 6084 demand_empty_rest_of_line (); 6085 } 6086 6087 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */ 6088 6089 struct save_opts 6090 { 6091 struct save_opts *next; 6092 int abspcadd; 6093 int symbols_case_sensitive; 6094 int keep_locals; 6095 int short_refs; 6096 int architecture; 6097 const enum m68k_register *control_regs; 6098 int quick; 6099 int rel32; 6100 int listing; 6101 int no_warnings; 6102 /* FIXME: We don't save OPT S. */ 6103 }; 6104 6105 /* This variable holds the stack of saved options. */ 6106 6107 static struct save_opts *save_stack; 6108 6109 /* The MRI SAVE pseudo-op. */ 6110 6111 static void 6112 s_save (int ignore ATTRIBUTE_UNUSED) 6113 { 6114 struct save_opts *s; 6115 6116 s = (struct save_opts *) xmalloc (sizeof (struct save_opts)); 6117 s->abspcadd = m68k_abspcadd; 6118 s->symbols_case_sensitive = symbols_case_sensitive; 6119 s->keep_locals = flag_keep_locals; 6120 s->short_refs = flag_short_refs; 6121 s->architecture = current_architecture; 6122 s->control_regs = control_regs; 6123 s->quick = m68k_quick; 6124 s->rel32 = m68k_rel32; 6125 s->listing = listing; 6126 s->no_warnings = flag_no_warnings; 6127 6128 s->next = save_stack; 6129 save_stack = s; 6130 6131 demand_empty_rest_of_line (); 6132 } 6133 6134 /* The MRI RESTORE pseudo-op. */ 6135 6136 static void 6137 s_restore (int ignore ATTRIBUTE_UNUSED) 6138 { 6139 struct save_opts *s; 6140 6141 if (save_stack == NULL) 6142 { 6143 as_bad (_("restore without save")); 6144 ignore_rest_of_line (); 6145 return; 6146 } 6147 6148 s = save_stack; 6149 save_stack = s->next; 6150 6151 m68k_abspcadd = s->abspcadd; 6152 symbols_case_sensitive = s->symbols_case_sensitive; 6153 flag_keep_locals = s->keep_locals; 6154 flag_short_refs = s->short_refs; 6155 current_architecture = s->architecture; 6156 control_regs = s->control_regs; 6157 m68k_quick = s->quick; 6158 m68k_rel32 = s->rel32; 6159 listing = s->listing; 6160 flag_no_warnings = s->no_warnings; 6161 6162 free (s); 6163 6164 demand_empty_rest_of_line (); 6165 } 6166 6167 /* Types of MRI structured control directives. */ 6168 6169 enum mri_control_type 6170 { 6171 mri_for, 6172 mri_if, 6173 mri_repeat, 6174 mri_while 6175 }; 6176 6177 /* This structure is used to stack the MRI structured control 6178 directives. */ 6179 6180 struct mri_control_info 6181 { 6182 /* The directive within which this one is enclosed. */ 6183 struct mri_control_info *outer; 6184 6185 /* The type of directive. */ 6186 enum mri_control_type type; 6187 6188 /* Whether an ELSE has been in an IF. */ 6189 int else_seen; 6190 6191 /* The add or sub statement at the end of a FOR. */ 6192 char *incr; 6193 6194 /* The label of the top of a FOR or REPEAT loop. */ 6195 char *top; 6196 6197 /* The label to jump to for the next iteration, or the else 6198 expression of a conditional. */ 6199 char *next; 6200 6201 /* The label to jump to to break out of the loop, or the label past 6202 the end of a conditional. */ 6203 char *bottom; 6204 }; 6205 6206 /* The stack of MRI structured control directives. */ 6207 6208 static struct mri_control_info *mri_control_stack; 6209 6210 /* The current MRI structured control directive index number, used to 6211 generate label names. */ 6212 6213 static int mri_control_index; 6214 6215 /* Assemble an instruction for an MRI structured control directive. */ 6216 6217 static void 6218 mri_assemble (char *str) 6219 { 6220 char *s; 6221 6222 /* md_assemble expects the opcode to be in lower case. */ 6223 for (s = str; *s != ' ' && *s != '\0'; s++) 6224 *s = TOLOWER (*s); 6225 6226 md_assemble (str); 6227 } 6228 6229 /* Generate a new MRI label structured control directive label name. */ 6230 6231 static char * 6232 mri_control_label (void) 6233 { 6234 char *n; 6235 6236 n = (char *) xmalloc (20); 6237 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index); 6238 ++mri_control_index; 6239 return n; 6240 } 6241 6242 /* Create a new MRI structured control directive. */ 6243 6244 static struct mri_control_info * 6245 push_mri_control (enum mri_control_type type) 6246 { 6247 struct mri_control_info *n; 6248 6249 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info)); 6250 6251 n->type = type; 6252 n->else_seen = 0; 6253 if (type == mri_if || type == mri_while) 6254 n->top = NULL; 6255 else 6256 n->top = mri_control_label (); 6257 n->next = mri_control_label (); 6258 n->bottom = mri_control_label (); 6259 6260 n->outer = mri_control_stack; 6261 mri_control_stack = n; 6262 6263 return n; 6264 } 6265 6266 /* Pop off the stack of MRI structured control directives. */ 6267 6268 static void 6269 pop_mri_control (void) 6270 { 6271 struct mri_control_info *n; 6272 6273 n = mri_control_stack; 6274 mri_control_stack = n->outer; 6275 if (n->top != NULL) 6276 free (n->top); 6277 free (n->next); 6278 free (n->bottom); 6279 free (n); 6280 } 6281 6282 /* Recognize a condition code in an MRI structured control expression. */ 6283 6284 static int 6285 parse_mri_condition (int *pcc) 6286 { 6287 char c1, c2; 6288 6289 know (*input_line_pointer == '<'); 6290 6291 ++input_line_pointer; 6292 c1 = *input_line_pointer++; 6293 c2 = *input_line_pointer++; 6294 6295 if (*input_line_pointer != '>') 6296 { 6297 as_bad (_("syntax error in structured control directive")); 6298 return 0; 6299 } 6300 6301 ++input_line_pointer; 6302 SKIP_WHITESPACE (); 6303 6304 c1 = TOLOWER (c1); 6305 c2 = TOLOWER (c2); 6306 6307 *pcc = (c1 << 8) | c2; 6308 6309 return 1; 6310 } 6311 6312 /* Parse a single operand in an MRI structured control expression. */ 6313 6314 static int 6315 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop, 6316 char **rightstart, char **rightstop) 6317 { 6318 char *s; 6319 6320 SKIP_WHITESPACE (); 6321 6322 *pcc = -1; 6323 *leftstart = NULL; 6324 *leftstop = NULL; 6325 *rightstart = NULL; 6326 *rightstop = NULL; 6327 6328 if (*input_line_pointer == '<') 6329 { 6330 /* It's just a condition code. */ 6331 return parse_mri_condition (pcc); 6332 } 6333 6334 /* Look ahead for the condition code. */ 6335 for (s = input_line_pointer; *s != '\0'; ++s) 6336 { 6337 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>') 6338 break; 6339 } 6340 if (*s == '\0') 6341 { 6342 as_bad (_("missing condition code in structured control directive")); 6343 return 0; 6344 } 6345 6346 *leftstart = input_line_pointer; 6347 *leftstop = s; 6348 if (*leftstop > *leftstart 6349 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t')) 6350 --*leftstop; 6351 6352 input_line_pointer = s; 6353 if (! parse_mri_condition (pcc)) 6354 return 0; 6355 6356 /* Look ahead for AND or OR or end of line. */ 6357 for (s = input_line_pointer; *s != '\0'; ++s) 6358 { 6359 /* We must make sure we don't misinterpret AND/OR at the end of labels! 6360 if d0 <eq> #FOOAND and d1 <ne> #BAROR then 6361 ^^^ ^^ */ 6362 if ((s == input_line_pointer 6363 || *(s-1) == ' ' 6364 || *(s-1) == '\t') 6365 && ((strncasecmp (s, "AND", 3) == 0 6366 && (s[3] == '.' || ! is_part_of_name (s[3]))) 6367 || (strncasecmp (s, "OR", 2) == 0 6368 && (s[2] == '.' || ! is_part_of_name (s[2]))))) 6369 break; 6370 } 6371 6372 *rightstart = input_line_pointer; 6373 *rightstop = s; 6374 if (*rightstop > *rightstart 6375 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t')) 6376 --*rightstop; 6377 6378 input_line_pointer = s; 6379 6380 return 1; 6381 } 6382 6383 #define MCC(b1, b2) (((b1) << 8) | (b2)) 6384 6385 /* Swap the sense of a condition. This changes the condition so that 6386 it generates the same result when the operands are swapped. */ 6387 6388 static int 6389 swap_mri_condition (int cc) 6390 { 6391 switch (cc) 6392 { 6393 case MCC ('h', 'i'): return MCC ('c', 's'); 6394 case MCC ('l', 's'): return MCC ('c', 'c'); 6395 /* <HS> is an alias for <CC>. */ 6396 case MCC ('h', 's'): 6397 case MCC ('c', 'c'): return MCC ('l', 's'); 6398 /* <LO> is an alias for <CS>. */ 6399 case MCC ('l', 'o'): 6400 case MCC ('c', 's'): return MCC ('h', 'i'); 6401 case MCC ('p', 'l'): return MCC ('m', 'i'); 6402 case MCC ('m', 'i'): return MCC ('p', 'l'); 6403 case MCC ('g', 'e'): return MCC ('l', 'e'); 6404 case MCC ('l', 't'): return MCC ('g', 't'); 6405 case MCC ('g', 't'): return MCC ('l', 't'); 6406 case MCC ('l', 'e'): return MCC ('g', 'e'); 6407 /* Issue a warning for conditions we can not swap. */ 6408 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */ 6409 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */ 6410 case MCC ('v', 'c'): 6411 case MCC ('v', 's'): 6412 default : 6413 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"), 6414 (char) (cc >> 8), (char) (cc)); 6415 break; 6416 } 6417 return cc; 6418 } 6419 6420 /* Reverse the sense of a condition. */ 6421 6422 static int 6423 reverse_mri_condition (int cc) 6424 { 6425 switch (cc) 6426 { 6427 case MCC ('h', 'i'): return MCC ('l', 's'); 6428 case MCC ('l', 's'): return MCC ('h', 'i'); 6429 /* <HS> is an alias for <CC> */ 6430 case MCC ('h', 's'): return MCC ('l', 'o'); 6431 case MCC ('c', 'c'): return MCC ('c', 's'); 6432 /* <LO> is an alias for <CS> */ 6433 case MCC ('l', 'o'): return MCC ('h', 's'); 6434 case MCC ('c', 's'): return MCC ('c', 'c'); 6435 case MCC ('n', 'e'): return MCC ('e', 'q'); 6436 case MCC ('e', 'q'): return MCC ('n', 'e'); 6437 case MCC ('v', 'c'): return MCC ('v', 's'); 6438 case MCC ('v', 's'): return MCC ('v', 'c'); 6439 case MCC ('p', 'l'): return MCC ('m', 'i'); 6440 case MCC ('m', 'i'): return MCC ('p', 'l'); 6441 case MCC ('g', 'e'): return MCC ('l', 't'); 6442 case MCC ('l', 't'): return MCC ('g', 'e'); 6443 case MCC ('g', 't'): return MCC ('l', 'e'); 6444 case MCC ('l', 'e'): return MCC ('g', 't'); 6445 } 6446 return cc; 6447 } 6448 6449 /* Build an MRI structured control expression. This generates test 6450 and branch instructions. It goes to TRUELAB if the condition is 6451 true, and to FALSELAB if the condition is false. Exactly one of 6452 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL 6453 is the size qualifier for the expression. EXTENT is the size to 6454 use for the branch. */ 6455 6456 static void 6457 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop, 6458 char *rightstart, char *rightstop, 6459 const char *truelab, const char *falselab, 6460 int extent) 6461 { 6462 char *buf; 6463 char *s; 6464 6465 if (leftstart != NULL) 6466 { 6467 struct m68k_op leftop, rightop; 6468 char c; 6469 6470 /* Swap the compare operands, if necessary, to produce a legal 6471 m68k compare instruction. Comparing a register operand with 6472 a non-register operand requires the register to be on the 6473 right (cmp, cmpa). Comparing an immediate value with 6474 anything requires the immediate value to be on the left 6475 (cmpi). */ 6476 6477 c = *leftstop; 6478 *leftstop = '\0'; 6479 (void) m68k_ip_op (leftstart, &leftop); 6480 *leftstop = c; 6481 6482 c = *rightstop; 6483 *rightstop = '\0'; 6484 (void) m68k_ip_op (rightstart, &rightop); 6485 *rightstop = c; 6486 6487 if (rightop.mode == IMMED 6488 || ((leftop.mode == DREG || leftop.mode == AREG) 6489 && (rightop.mode != DREG && rightop.mode != AREG))) 6490 { 6491 char *temp; 6492 6493 /* Correct conditional handling: 6494 if #1 <lt> d0 then ;means if (1 < d0) 6495 ... 6496 endi 6497 6498 should assemble to: 6499 6500 cmp #1,d0 if we do *not* swap the operands 6501 bgt true we need the swapped condition! 6502 ble false 6503 true: 6504 ... 6505 false: 6506 */ 6507 temp = leftstart; 6508 leftstart = rightstart; 6509 rightstart = temp; 6510 temp = leftstop; 6511 leftstop = rightstop; 6512 rightstop = temp; 6513 } 6514 else 6515 { 6516 cc = swap_mri_condition (cc); 6517 } 6518 } 6519 6520 if (truelab == NULL) 6521 { 6522 cc = reverse_mri_condition (cc); 6523 truelab = falselab; 6524 } 6525 6526 if (leftstart != NULL) 6527 { 6528 buf = (char *) xmalloc (20 6529 + (leftstop - leftstart) 6530 + (rightstop - rightstart)); 6531 s = buf; 6532 *s++ = 'c'; 6533 *s++ = 'm'; 6534 *s++ = 'p'; 6535 if (qual != '\0') 6536 *s++ = TOLOWER (qual); 6537 *s++ = ' '; 6538 memcpy (s, leftstart, leftstop - leftstart); 6539 s += leftstop - leftstart; 6540 *s++ = ','; 6541 memcpy (s, rightstart, rightstop - rightstart); 6542 s += rightstop - rightstart; 6543 *s = '\0'; 6544 mri_assemble (buf); 6545 free (buf); 6546 } 6547 6548 buf = (char *) xmalloc (20 + strlen (truelab)); 6549 s = buf; 6550 *s++ = 'b'; 6551 *s++ = cc >> 8; 6552 *s++ = cc & 0xff; 6553 if (extent != '\0') 6554 *s++ = TOLOWER (extent); 6555 *s++ = ' '; 6556 strcpy (s, truelab); 6557 mri_assemble (buf); 6558 free (buf); 6559 } 6560 6561 /* Parse an MRI structured control expression. This generates test 6562 and branch instructions. STOP is where the expression ends. It 6563 goes to TRUELAB if the condition is true, and to FALSELAB if the 6564 condition is false. Exactly one of TRUELAB and FALSELAB will be 6565 NULL, meaning to fall through. QUAL is the size qualifier for the 6566 expression. EXTENT is the size to use for the branch. */ 6567 6568 static void 6569 parse_mri_control_expression (char *stop, int qual, const char *truelab, 6570 const char *falselab, int extent) 6571 { 6572 int c; 6573 int cc; 6574 char *leftstart; 6575 char *leftstop; 6576 char *rightstart; 6577 char *rightstop; 6578 6579 c = *stop; 6580 *stop = '\0'; 6581 6582 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6583 &rightstart, &rightstop)) 6584 { 6585 *stop = c; 6586 return; 6587 } 6588 6589 if (strncasecmp (input_line_pointer, "AND", 3) == 0) 6590 { 6591 const char *flab; 6592 6593 if (falselab != NULL) 6594 flab = falselab; 6595 else 6596 flab = mri_control_label (); 6597 6598 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6599 rightstop, (const char *) NULL, flab, extent); 6600 6601 input_line_pointer += 3; 6602 if (*input_line_pointer != '.' 6603 || input_line_pointer[1] == '\0') 6604 qual = '\0'; 6605 else 6606 { 6607 qual = input_line_pointer[1]; 6608 input_line_pointer += 2; 6609 } 6610 6611 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6612 &rightstart, &rightstop)) 6613 { 6614 *stop = c; 6615 return; 6616 } 6617 6618 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6619 rightstop, truelab, falselab, extent); 6620 6621 if (falselab == NULL) 6622 colon (flab); 6623 } 6624 else if (strncasecmp (input_line_pointer, "OR", 2) == 0) 6625 { 6626 const char *tlab; 6627 6628 if (truelab != NULL) 6629 tlab = truelab; 6630 else 6631 tlab = mri_control_label (); 6632 6633 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6634 rightstop, tlab, (const char *) NULL, extent); 6635 6636 input_line_pointer += 2; 6637 if (*input_line_pointer != '.' 6638 || input_line_pointer[1] == '\0') 6639 qual = '\0'; 6640 else 6641 { 6642 qual = input_line_pointer[1]; 6643 input_line_pointer += 2; 6644 } 6645 6646 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop, 6647 &rightstart, &rightstop)) 6648 { 6649 *stop = c; 6650 return; 6651 } 6652 6653 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6654 rightstop, truelab, falselab, extent); 6655 6656 if (truelab == NULL) 6657 colon (tlab); 6658 } 6659 else 6660 { 6661 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart, 6662 rightstop, truelab, falselab, extent); 6663 } 6664 6665 *stop = c; 6666 if (input_line_pointer != stop) 6667 as_bad (_("syntax error in structured control directive")); 6668 } 6669 6670 /* Handle the MRI IF pseudo-op. This may be a structured control 6671 directive, or it may be a regular assembler conditional, depending 6672 on its operands. */ 6673 6674 static void 6675 s_mri_if (int qual) 6676 { 6677 char *s; 6678 int c; 6679 struct mri_control_info *n; 6680 6681 /* A structured control directive must end with THEN with an 6682 optional qualifier. */ 6683 s = input_line_pointer; 6684 /* We only accept '*' as introduction of comments if preceded by white space 6685 or at first column of a line (I think this can't actually happen here?) 6686 This is important when assembling: 6687 if d0 <ne> 12(a0,d0*2) then 6688 if d0 <ne> #CONST*20 then. */ 6689 while (! (is_end_of_line[(unsigned char) *s] 6690 || (flag_mri 6691 && *s == '*' 6692 && (s == input_line_pointer 6693 || *(s-1) == ' ' 6694 || *(s-1) == '\t')))) 6695 ++s; 6696 --s; 6697 while (s > input_line_pointer && (*s == ' ' || *s == '\t')) 6698 --s; 6699 6700 if (s - input_line_pointer > 1 6701 && s[-1] == '.') 6702 s -= 2; 6703 6704 if (s - input_line_pointer < 3 6705 || strncasecmp (s - 3, "THEN", 4) != 0) 6706 { 6707 if (qual != '\0') 6708 { 6709 as_bad (_("missing then")); 6710 ignore_rest_of_line (); 6711 return; 6712 } 6713 6714 /* It's a conditional. */ 6715 s_if (O_ne); 6716 return; 6717 } 6718 6719 /* Since this might be a conditional if, this pseudo-op will be 6720 called even if we are supported to be ignoring input. Double 6721 check now. Clobber *input_line_pointer so that ignore_input 6722 thinks that this is not a special pseudo-op. */ 6723 c = *input_line_pointer; 6724 *input_line_pointer = 0; 6725 if (ignore_input ()) 6726 { 6727 *input_line_pointer = c; 6728 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6729 ++input_line_pointer; 6730 demand_empty_rest_of_line (); 6731 return; 6732 } 6733 *input_line_pointer = c; 6734 6735 n = push_mri_control (mri_if); 6736 6737 parse_mri_control_expression (s - 3, qual, (const char *) NULL, 6738 n->next, s[1] == '.' ? s[2] : '\0'); 6739 6740 if (s[1] == '.') 6741 input_line_pointer = s + 3; 6742 else 6743 input_line_pointer = s + 1; 6744 6745 if (flag_mri) 6746 { 6747 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6748 ++input_line_pointer; 6749 } 6750 6751 demand_empty_rest_of_line (); 6752 } 6753 6754 /* Handle the MRI else pseudo-op. If we are currently doing an MRI 6755 structured IF, associate the ELSE with the IF. Otherwise, assume 6756 it is a conditional else. */ 6757 6758 static void 6759 s_mri_else (int qual) 6760 { 6761 int c; 6762 char *buf; 6763 char q[2]; 6764 6765 if (qual == '\0' 6766 && (mri_control_stack == NULL 6767 || mri_control_stack->type != mri_if 6768 || mri_control_stack->else_seen)) 6769 { 6770 s_else (0); 6771 return; 6772 } 6773 6774 c = *input_line_pointer; 6775 *input_line_pointer = 0; 6776 if (ignore_input ()) 6777 { 6778 *input_line_pointer = c; 6779 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6780 ++input_line_pointer; 6781 demand_empty_rest_of_line (); 6782 return; 6783 } 6784 *input_line_pointer = c; 6785 6786 if (mri_control_stack == NULL 6787 || mri_control_stack->type != mri_if 6788 || mri_control_stack->else_seen) 6789 { 6790 as_bad (_("else without matching if")); 6791 ignore_rest_of_line (); 6792 return; 6793 } 6794 6795 mri_control_stack->else_seen = 1; 6796 6797 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom)); 6798 q[0] = TOLOWER (qual); 6799 q[1] = '\0'; 6800 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom); 6801 mri_assemble (buf); 6802 free (buf); 6803 6804 colon (mri_control_stack->next); 6805 6806 if (flag_mri) 6807 { 6808 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6809 ++input_line_pointer; 6810 } 6811 6812 demand_empty_rest_of_line (); 6813 } 6814 6815 /* Handle the MRI ENDI pseudo-op. */ 6816 6817 static void 6818 s_mri_endi (int ignore ATTRIBUTE_UNUSED) 6819 { 6820 if (mri_control_stack == NULL 6821 || mri_control_stack->type != mri_if) 6822 { 6823 as_bad (_("endi without matching if")); 6824 ignore_rest_of_line (); 6825 return; 6826 } 6827 6828 /* ignore_input will not return true for ENDI, so we don't need to 6829 worry about checking it again here. */ 6830 6831 if (! mri_control_stack->else_seen) 6832 colon (mri_control_stack->next); 6833 colon (mri_control_stack->bottom); 6834 6835 pop_mri_control (); 6836 6837 if (flag_mri) 6838 { 6839 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6840 ++input_line_pointer; 6841 } 6842 6843 demand_empty_rest_of_line (); 6844 } 6845 6846 /* Handle the MRI BREAK pseudo-op. */ 6847 6848 static void 6849 s_mri_break (int extent) 6850 { 6851 struct mri_control_info *n; 6852 char *buf; 6853 char ex[2]; 6854 6855 n = mri_control_stack; 6856 while (n != NULL 6857 && n->type != mri_for 6858 && n->type != mri_repeat 6859 && n->type != mri_while) 6860 n = n->outer; 6861 if (n == NULL) 6862 { 6863 as_bad (_("break outside of structured loop")); 6864 ignore_rest_of_line (); 6865 return; 6866 } 6867 6868 buf = (char *) xmalloc (20 + strlen (n->bottom)); 6869 ex[0] = TOLOWER (extent); 6870 ex[1] = '\0'; 6871 sprintf (buf, "bra%s %s", ex, n->bottom); 6872 mri_assemble (buf); 6873 free (buf); 6874 6875 if (flag_mri) 6876 { 6877 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6878 ++input_line_pointer; 6879 } 6880 6881 demand_empty_rest_of_line (); 6882 } 6883 6884 /* Handle the MRI NEXT pseudo-op. */ 6885 6886 static void 6887 s_mri_next (int extent) 6888 { 6889 struct mri_control_info *n; 6890 char *buf; 6891 char ex[2]; 6892 6893 n = mri_control_stack; 6894 while (n != NULL 6895 && n->type != mri_for 6896 && n->type != mri_repeat 6897 && n->type != mri_while) 6898 n = n->outer; 6899 if (n == NULL) 6900 { 6901 as_bad (_("next outside of structured loop")); 6902 ignore_rest_of_line (); 6903 return; 6904 } 6905 6906 buf = (char *) xmalloc (20 + strlen (n->next)); 6907 ex[0] = TOLOWER (extent); 6908 ex[1] = '\0'; 6909 sprintf (buf, "bra%s %s", ex, n->next); 6910 mri_assemble (buf); 6911 free (buf); 6912 6913 if (flag_mri) 6914 { 6915 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6916 ++input_line_pointer; 6917 } 6918 6919 demand_empty_rest_of_line (); 6920 } 6921 6922 /* Handle the MRI FOR pseudo-op. */ 6923 6924 static void 6925 s_mri_for (int qual) 6926 { 6927 const char *varstart, *varstop; 6928 const char *initstart, *initstop; 6929 const char *endstart, *endstop; 6930 const char *bystart, *bystop; 6931 int up; 6932 int by; 6933 int extent; 6934 struct mri_control_info *n; 6935 char *buf; 6936 char *s; 6937 char ex[2]; 6938 6939 /* The syntax is 6940 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e 6941 */ 6942 6943 SKIP_WHITESPACE (); 6944 varstart = input_line_pointer; 6945 6946 /* Look for the '='. */ 6947 while (! is_end_of_line[(unsigned char) *input_line_pointer] 6948 && *input_line_pointer != '=') 6949 ++input_line_pointer; 6950 if (*input_line_pointer != '=') 6951 { 6952 as_bad (_("missing =")); 6953 ignore_rest_of_line (); 6954 return; 6955 } 6956 6957 varstop = input_line_pointer; 6958 if (varstop > varstart 6959 && (varstop[-1] == ' ' || varstop[-1] == '\t')) 6960 --varstop; 6961 6962 ++input_line_pointer; 6963 6964 initstart = input_line_pointer; 6965 6966 /* Look for TO or DOWNTO. */ 6967 up = 1; 6968 initstop = NULL; 6969 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 6970 { 6971 if (strncasecmp (input_line_pointer, "TO", 2) == 0 6972 && ! is_part_of_name (input_line_pointer[2])) 6973 { 6974 initstop = input_line_pointer; 6975 input_line_pointer += 2; 6976 break; 6977 } 6978 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0 6979 && ! is_part_of_name (input_line_pointer[6])) 6980 { 6981 initstop = input_line_pointer; 6982 up = 0; 6983 input_line_pointer += 6; 6984 break; 6985 } 6986 ++input_line_pointer; 6987 } 6988 if (initstop == NULL) 6989 { 6990 as_bad (_("missing to or downto")); 6991 ignore_rest_of_line (); 6992 return; 6993 } 6994 if (initstop > initstart 6995 && (initstop[-1] == ' ' || initstop[-1] == '\t')) 6996 --initstop; 6997 6998 SKIP_WHITESPACE (); 6999 endstart = input_line_pointer; 7000 7001 /* Look for BY or DO. */ 7002 by = 0; 7003 endstop = NULL; 7004 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7005 { 7006 if (strncasecmp (input_line_pointer, "BY", 2) == 0 7007 && ! is_part_of_name (input_line_pointer[2])) 7008 { 7009 endstop = input_line_pointer; 7010 by = 1; 7011 input_line_pointer += 2; 7012 break; 7013 } 7014 if (strncasecmp (input_line_pointer, "DO", 2) == 0 7015 && (input_line_pointer[2] == '.' 7016 || ! is_part_of_name (input_line_pointer[2]))) 7017 { 7018 endstop = input_line_pointer; 7019 input_line_pointer += 2; 7020 break; 7021 } 7022 ++input_line_pointer; 7023 } 7024 if (endstop == NULL) 7025 { 7026 as_bad (_("missing do")); 7027 ignore_rest_of_line (); 7028 return; 7029 } 7030 if (endstop > endstart 7031 && (endstop[-1] == ' ' || endstop[-1] == '\t')) 7032 --endstop; 7033 7034 if (! by) 7035 { 7036 bystart = "#1"; 7037 bystop = bystart + 2; 7038 } 7039 else 7040 { 7041 SKIP_WHITESPACE (); 7042 bystart = input_line_pointer; 7043 7044 /* Look for DO. */ 7045 bystop = NULL; 7046 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7047 { 7048 if (strncasecmp (input_line_pointer, "DO", 2) == 0 7049 && (input_line_pointer[2] == '.' 7050 || ! is_part_of_name (input_line_pointer[2]))) 7051 { 7052 bystop = input_line_pointer; 7053 input_line_pointer += 2; 7054 break; 7055 } 7056 ++input_line_pointer; 7057 } 7058 if (bystop == NULL) 7059 { 7060 as_bad (_("missing do")); 7061 ignore_rest_of_line (); 7062 return; 7063 } 7064 if (bystop > bystart 7065 && (bystop[-1] == ' ' || bystop[-1] == '\t')) 7066 --bystop; 7067 } 7068 7069 if (*input_line_pointer != '.') 7070 extent = '\0'; 7071 else 7072 { 7073 extent = input_line_pointer[1]; 7074 input_line_pointer += 2; 7075 } 7076 7077 /* We have fully parsed the FOR operands. Now build the loop. */ 7078 n = push_mri_control (mri_for); 7079 7080 buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); 7081 7082 /* Move init,var. */ 7083 s = buf; 7084 *s++ = 'm'; 7085 *s++ = 'o'; 7086 *s++ = 'v'; 7087 *s++ = 'e'; 7088 if (qual != '\0') 7089 *s++ = TOLOWER (qual); 7090 *s++ = ' '; 7091 memcpy (s, initstart, initstop - initstart); 7092 s += initstop - initstart; 7093 *s++ = ','; 7094 memcpy (s, varstart, varstop - varstart); 7095 s += varstop - varstart; 7096 *s = '\0'; 7097 mri_assemble (buf); 7098 7099 colon (n->top); 7100 7101 /* cmp end,var. */ 7102 s = buf; 7103 *s++ = 'c'; 7104 *s++ = 'm'; 7105 *s++ = 'p'; 7106 if (qual != '\0') 7107 *s++ = TOLOWER (qual); 7108 *s++ = ' '; 7109 memcpy (s, endstart, endstop - endstart); 7110 s += endstop - endstart; 7111 *s++ = ','; 7112 memcpy (s, varstart, varstop - varstart); 7113 s += varstop - varstart; 7114 *s = '\0'; 7115 mri_assemble (buf); 7116 7117 /* bcc bottom. */ 7118 ex[0] = TOLOWER (extent); 7119 ex[1] = '\0'; 7120 if (up) 7121 sprintf (buf, "blt%s %s", ex, n->bottom); 7122 else 7123 sprintf (buf, "bgt%s %s", ex, n->bottom); 7124 mri_assemble (buf); 7125 7126 /* Put together the add or sub instruction used by ENDF. */ 7127 s = buf; 7128 if (up) 7129 strcpy (s, "add"); 7130 else 7131 strcpy (s, "sub"); 7132 s += 3; 7133 if (qual != '\0') 7134 *s++ = TOLOWER (qual); 7135 *s++ = ' '; 7136 memcpy (s, bystart, bystop - bystart); 7137 s += bystop - bystart; 7138 *s++ = ','; 7139 memcpy (s, varstart, varstop - varstart); 7140 s += varstop - varstart; 7141 *s = '\0'; 7142 n->incr = buf; 7143 7144 if (flag_mri) 7145 { 7146 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7147 ++input_line_pointer; 7148 } 7149 7150 demand_empty_rest_of_line (); 7151 } 7152 7153 /* Handle the MRI ENDF pseudo-op. */ 7154 7155 static void 7156 s_mri_endf (int ignore ATTRIBUTE_UNUSED) 7157 { 7158 if (mri_control_stack == NULL 7159 || mri_control_stack->type != mri_for) 7160 { 7161 as_bad (_("endf without for")); 7162 ignore_rest_of_line (); 7163 return; 7164 } 7165 7166 colon (mri_control_stack->next); 7167 7168 mri_assemble (mri_control_stack->incr); 7169 7170 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top); 7171 mri_assemble (mri_control_stack->incr); 7172 7173 free (mri_control_stack->incr); 7174 7175 colon (mri_control_stack->bottom); 7176 7177 pop_mri_control (); 7178 7179 if (flag_mri) 7180 { 7181 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7182 ++input_line_pointer; 7183 } 7184 7185 demand_empty_rest_of_line (); 7186 } 7187 7188 /* Handle the MRI REPEAT pseudo-op. */ 7189 7190 static void 7191 s_mri_repeat (int ignore ATTRIBUTE_UNUSED) 7192 { 7193 struct mri_control_info *n; 7194 7195 n = push_mri_control (mri_repeat); 7196 colon (n->top); 7197 if (flag_mri) 7198 { 7199 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7200 ++input_line_pointer; 7201 } 7202 demand_empty_rest_of_line (); 7203 } 7204 7205 /* Handle the MRI UNTIL pseudo-op. */ 7206 7207 static void 7208 s_mri_until (int qual) 7209 { 7210 char *s; 7211 7212 if (mri_control_stack == NULL 7213 || mri_control_stack->type != mri_repeat) 7214 { 7215 as_bad (_("until without repeat")); 7216 ignore_rest_of_line (); 7217 return; 7218 } 7219 7220 colon (mri_control_stack->next); 7221 7222 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++) 7223 ; 7224 7225 parse_mri_control_expression (s, qual, (const char *) NULL, 7226 mri_control_stack->top, '\0'); 7227 7228 colon (mri_control_stack->bottom); 7229 7230 input_line_pointer = s; 7231 7232 pop_mri_control (); 7233 7234 if (flag_mri) 7235 { 7236 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7237 ++input_line_pointer; 7238 } 7239 7240 demand_empty_rest_of_line (); 7241 } 7242 7243 /* Handle the MRI WHILE pseudo-op. */ 7244 7245 static void 7246 s_mri_while (int qual) 7247 { 7248 char *s; 7249 7250 struct mri_control_info *n; 7251 7252 s = input_line_pointer; 7253 /* We only accept '*' as introduction of comments if preceded by white space 7254 or at first column of a line (I think this can't actually happen here?) 7255 This is important when assembling: 7256 while d0 <ne> 12(a0,d0*2) do 7257 while d0 <ne> #CONST*20 do. */ 7258 while (! (is_end_of_line[(unsigned char) *s] 7259 || (flag_mri 7260 && *s == '*' 7261 && (s == input_line_pointer 7262 || *(s-1) == ' ' 7263 || *(s-1) == '\t')))) 7264 s++; 7265 --s; 7266 while (*s == ' ' || *s == '\t') 7267 --s; 7268 if (s - input_line_pointer > 1 7269 && s[-1] == '.') 7270 s -= 2; 7271 if (s - input_line_pointer < 2 7272 || strncasecmp (s - 1, "DO", 2) != 0) 7273 { 7274 as_bad (_("missing do")); 7275 ignore_rest_of_line (); 7276 return; 7277 } 7278 7279 n = push_mri_control (mri_while); 7280 7281 colon (n->next); 7282 7283 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom, 7284 s[1] == '.' ? s[2] : '\0'); 7285 7286 input_line_pointer = s + 1; 7287 if (*input_line_pointer == '.') 7288 input_line_pointer += 2; 7289 7290 if (flag_mri) 7291 { 7292 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7293 ++input_line_pointer; 7294 } 7295 7296 demand_empty_rest_of_line (); 7297 } 7298 7299 /* Handle the MRI ENDW pseudo-op. */ 7300 7301 static void 7302 s_mri_endw (int ignore ATTRIBUTE_UNUSED) 7303 { 7304 char *buf; 7305 7306 if (mri_control_stack == NULL 7307 || mri_control_stack->type != mri_while) 7308 { 7309 as_bad (_("endw without while")); 7310 ignore_rest_of_line (); 7311 return; 7312 } 7313 7314 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next)); 7315 sprintf (buf, "bra %s", mri_control_stack->next); 7316 mri_assemble (buf); 7317 free (buf); 7318 7319 colon (mri_control_stack->bottom); 7320 7321 pop_mri_control (); 7322 7323 if (flag_mri) 7324 { 7325 while (! is_end_of_line[(unsigned char) *input_line_pointer]) 7326 ++input_line_pointer; 7327 } 7328 7329 demand_empty_rest_of_line (); 7330 } 7331 7332 /* Parse a .cpu directive. */ 7333 7334 static void 7335 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED) 7336 { 7337 char saved_char; 7338 char *name; 7339 7340 if (initialized) 7341 { 7342 as_bad (_("already assembled instructions")); 7343 ignore_rest_of_line (); 7344 return; 7345 } 7346 7347 name = input_line_pointer; 7348 while (*input_line_pointer && !ISSPACE(*input_line_pointer)) 7349 input_line_pointer++; 7350 saved_char = *input_line_pointer; 7351 *input_line_pointer = 0; 7352 7353 m68k_set_cpu (name, 1, 0); 7354 7355 *input_line_pointer = saved_char; 7356 demand_empty_rest_of_line (); 7357 return; 7358 } 7359 7360 /* Parse a .arch directive. */ 7361 7362 static void 7363 s_m68k_arch (int ignored ATTRIBUTE_UNUSED) 7364 { 7365 char saved_char; 7366 char *name; 7367 7368 if (initialized) 7369 { 7370 as_bad (_("already assembled instructions")); 7371 ignore_rest_of_line (); 7372 return; 7373 } 7374 7375 name = input_line_pointer; 7376 while (*input_line_pointer && *input_line_pointer != ',' 7377 && !ISSPACE (*input_line_pointer)) 7378 input_line_pointer++; 7379 saved_char = *input_line_pointer; 7380 *input_line_pointer = 0; 7381 7382 if (m68k_set_arch (name, 1, 0)) 7383 { 7384 /* Scan extensions. */ 7385 do 7386 { 7387 *input_line_pointer++ = saved_char; 7388 if (!*input_line_pointer || ISSPACE (*input_line_pointer)) 7389 break; 7390 name = input_line_pointer; 7391 while (*input_line_pointer && *input_line_pointer != ',' 7392 && !ISSPACE (*input_line_pointer)) 7393 input_line_pointer++; 7394 saved_char = *input_line_pointer; 7395 *input_line_pointer = 0; 7396 } 7397 while (m68k_set_extension (name, 1, 0)); 7398 } 7399 7400 *input_line_pointer = saved_char; 7401 demand_empty_rest_of_line (); 7402 return; 7403 } 7404 7405 /* Lookup a cpu name in TABLE and return the slot found. Return NULL 7406 if none is found, the caller is responsible for emitting an error 7407 message. If ALLOW_M is non-zero, we allow an initial 'm' on the 7408 cpu name, if it begins with a '6' (possibly skipping an intervening 7409 'c'. We also allow a 'c' in the same place. if NEGATED is 7410 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if 7411 the option is indeed negated. */ 7412 7413 static const struct m68k_cpu * 7414 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table, 7415 int allow_m, int *negated) 7416 { 7417 /* allow negated value? */ 7418 if (negated) 7419 { 7420 *negated = 0; 7421 7422 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') 7423 { 7424 arg += 3; 7425 *negated = 1; 7426 } 7427 } 7428 7429 /* Remove 'm' or 'mc' prefix from 68k or coldfire variants. */ 7430 if (allow_m) 7431 { 7432 if (arg[0] == 'm') 7433 { 7434 if (arg[1] == '6' || arg[1] == '5') 7435 arg += 1; 7436 else if (arg[1] == 'c' && arg[2] == '6') 7437 arg += 2; 7438 } 7439 } 7440 else if (arg[0] == 'c' && arg[1] == '6') 7441 arg += 1; 7442 7443 for (; table->name; table++) 7444 if (!strcmp (arg, table->name)) 7445 { 7446 if (table->alias < -1 || table->alias > 1) 7447 as_bad (_("`%s' is deprecated, use `%s'"), 7448 table->name, table[table->alias < 0 ? 1 : -1].name); 7449 return table; 7450 } 7451 return 0; 7452 } 7453 7454 /* Set the cpu, issuing errors if it is unrecognized. */ 7455 7456 static int 7457 m68k_set_cpu (char const *name, int allow_m, int silent) 7458 { 7459 const struct m68k_cpu *cpu; 7460 7461 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL); 7462 7463 if (!cpu) 7464 { 7465 if (!silent) 7466 as_bad (_("cpu `%s' unrecognized"), name); 7467 return 0; 7468 } 7469 selected_cpu = cpu; 7470 return 1; 7471 } 7472 7473 /* Set the architecture, issuing errors if it is unrecognized. */ 7474 7475 static int 7476 m68k_set_arch (char const *name, int allow_m, int silent) 7477 { 7478 const struct m68k_cpu *arch; 7479 7480 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL); 7481 7482 if (!arch) 7483 { 7484 if (!silent) 7485 as_bad (_("architecture `%s' unrecognized"), name); 7486 return 0; 7487 } 7488 selected_arch = arch; 7489 return 1; 7490 } 7491 7492 /* Set the architecture extension, issuing errors if it is 7493 unrecognized, or invalid */ 7494 7495 static int 7496 m68k_set_extension (char const *name, int allow_m, int silent) 7497 { 7498 int negated; 7499 const struct m68k_cpu *ext; 7500 7501 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated); 7502 7503 if (!ext) 7504 { 7505 if (!silent) 7506 as_bad (_("extension `%s' unrecognized"), name); 7507 return 0; 7508 } 7509 7510 if (negated) 7511 not_current_architecture |= (ext->control_regs 7512 ? *(unsigned *)ext->control_regs: ext->arch); 7513 else 7514 current_architecture |= ext->arch; 7515 return 1; 7516 } 7517 7518 /* md_parse_option 7519 Invocation line includes a switch not recognized by the base assembler. 7520 */ 7521 7522 #ifdef OBJ_ELF 7523 const char *md_shortopts = "lSA:m:kQ:V"; 7524 #else 7525 const char *md_shortopts = "lSA:m:k"; 7526 #endif 7527 7528 struct option md_longopts[] = { 7529 #define OPTION_PIC (OPTION_MD_BASE) 7530 {"pic", no_argument, NULL, OPTION_PIC}, 7531 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1) 7532 {"register-prefix-optional", no_argument, NULL, 7533 OPTION_REGISTER_PREFIX_OPTIONAL}, 7534 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) 7535 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, 7536 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) 7537 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, 7538 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) 7539 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, 7540 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5) 7541 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16}, 7542 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6) 7543 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, 7544 #define OPTION_PCREL (OPTION_MD_BASE + 7) 7545 {"pcrel", no_argument, NULL, OPTION_PCREL}, 7546 {NULL, no_argument, NULL, 0} 7547 }; 7548 size_t md_longopts_size = sizeof (md_longopts); 7549 7550 int 7551 md_parse_option (int c, char *arg) 7552 { 7553 switch (c) 7554 { 7555 case 'l': /* -l means keep external to 2 bit offset 7556 rather than 16 bit one. */ 7557 flag_short_refs = 1; 7558 break; 7559 7560 case 'S': /* -S means that jbsr's always turn into 7561 jsr's. */ 7562 flag_long_jumps = 1; 7563 break; 7564 7565 case OPTION_PCREL: /* --pcrel means never turn PC-relative 7566 branches into absolute jumps. */ 7567 flag_keep_pcrel = 1; 7568 break; 7569 7570 case OPTION_PIC: 7571 case 'k': 7572 flag_want_pic = 1; 7573 break; /* -pic, Position Independent Code. */ 7574 7575 case OPTION_REGISTER_PREFIX_OPTIONAL: 7576 flag_reg_prefix_optional = 1; 7577 reg_prefix_optional_seen = 1; 7578 break; 7579 7580 /* -V: SVR4 argument to print version ID. */ 7581 case 'V': 7582 print_version_id (); 7583 break; 7584 7585 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 7586 should be emitted or not. FIXME: Not implemented. */ 7587 case 'Q': 7588 break; 7589 7590 case OPTION_BITWISE_OR: 7591 { 7592 char *n, *t; 7593 const char *s; 7594 7595 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1); 7596 t = n; 7597 for (s = m68k_comment_chars; *s != '\0'; s++) 7598 if (*s != '|') 7599 *t++ = *s; 7600 *t = '\0'; 7601 m68k_comment_chars = n; 7602 } 7603 break; 7604 7605 case OPTION_BASE_SIZE_DEFAULT_16: 7606 m68k_index_width_default = SIZE_WORD; 7607 break; 7608 7609 case OPTION_BASE_SIZE_DEFAULT_32: 7610 m68k_index_width_default = SIZE_LONG; 7611 break; 7612 7613 case OPTION_DISP_SIZE_DEFAULT_16: 7614 m68k_rel32 = 0; 7615 m68k_rel32_from_cmdline = 1; 7616 break; 7617 7618 case OPTION_DISP_SIZE_DEFAULT_32: 7619 m68k_rel32 = 1; 7620 m68k_rel32_from_cmdline = 1; 7621 break; 7622 7623 case 'A': 7624 #if WARN_DEPRECATED 7625 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'", 7626 arg, arg)); 7627 #endif 7628 /* Intentional fall-through. */ 7629 case 'm': 7630 if (!strncmp (arg, "arch=", 5)) 7631 m68k_set_arch (arg + 5, 1, 0); 7632 else if (!strncmp (arg, "cpu=", 4)) 7633 m68k_set_cpu (arg + 4, 1, 0); 7634 else if (m68k_set_extension (arg, 0, 1)) 7635 ; 7636 else if (m68k_set_arch (arg, 0, 1)) 7637 ; 7638 else if (m68k_set_cpu (arg, 0, 1)) 7639 ; 7640 else 7641 return 0; 7642 break; 7643 7644 default: 7645 return 0; 7646 } 7647 7648 return 1; 7649 } 7650 7651 /* Setup tables from the selected arch and/or cpu */ 7652 7653 static void 7654 m68k_init_arch (void) 7655 { 7656 if (not_current_architecture & current_architecture) 7657 { 7658 as_bad (_("architecture features both enabled and disabled")); 7659 not_current_architecture &= ~current_architecture; 7660 } 7661 if (selected_arch) 7662 { 7663 current_architecture |= selected_arch->arch; 7664 control_regs = selected_arch->control_regs; 7665 } 7666 else 7667 current_architecture |= selected_cpu->arch; 7668 7669 current_architecture &= ~not_current_architecture; 7670 7671 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881)) 7672 { 7673 /* Determine which float is really meant. */ 7674 if (current_architecture & (m68k_mask & ~m68881)) 7675 current_architecture ^= cfloat; 7676 else 7677 current_architecture ^= m68881; 7678 } 7679 7680 if (selected_cpu) 7681 { 7682 control_regs = selected_cpu->control_regs; 7683 if (current_architecture & ~selected_cpu->arch) 7684 { 7685 as_bad (_("selected processor does not have all features of selected architecture")); 7686 current_architecture 7687 = selected_cpu->arch & ~not_current_architecture; 7688 } 7689 } 7690 7691 if ((current_architecture & m68k_mask) 7692 && (current_architecture & ~m68k_mask)) 7693 { 7694 as_bad (_ ("m68k and cf features both selected")); 7695 if (current_architecture & m68k_mask) 7696 current_architecture &= m68k_mask; 7697 else 7698 current_architecture &= ~m68k_mask; 7699 } 7700 7701 /* Permit m68881 specification with all cpus; those that can't work 7702 with a coprocessor could be doing emulation. */ 7703 if (current_architecture & m68851) 7704 { 7705 if (current_architecture & m68040) 7706 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly")); 7707 } 7708 /* What other incompatibilities could we check for? */ 7709 7710 if (cpu_of_arch (current_architecture) < m68020 7711 || arch_coldfire_p (current_architecture)) 7712 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; 7713 7714 initialized = 1; 7715 } 7716 7717 void 7718 md_show_usage (FILE *stream) 7719 { 7720 const char *default_cpu = TARGET_CPU; 7721 int i; 7722 7723 /* Get the canonical name for the default target CPU. */ 7724 if (*default_cpu == 'm') 7725 default_cpu++; 7726 for (i = 0; m68k_cpus[i].name; i++) 7727 { 7728 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0) 7729 { 7730 while (m68k_cpus[i].alias > 0) 7731 i--; 7732 while (m68k_cpus[i].alias < 0) 7733 i++; 7734 default_cpu = m68k_cpus[i].name; 7735 } 7736 } 7737 7738 fprintf (stream, _("\ 7739 -march=<arch> set architecture\n\ 7740 -mcpu=<cpu> set cpu [default %s]\n\ 7741 "), default_cpu); 7742 for (i = 0; m68k_extensions[i].name; i++) 7743 fprintf (stream, _("\ 7744 -m[no-]%-16s enable/disable%s architecture extension\n\ 7745 "), m68k_extensions[i].name, 7746 m68k_extensions[i].alias > 0 ? " ColdFire" 7747 : m68k_extensions[i].alias < 0 ? " m68k" : ""); 7748 7749 fprintf (stream, _("\ 7750 -l use 1 word for refs to undefined symbols [default 2]\n\ 7751 -pic, -k generate position independent code\n\ 7752 -S turn jbsr into jsr\n\ 7753 --pcrel never turn PC-relative branches into absolute jumps\n\ 7754 --register-prefix-optional\n\ 7755 recognize register names without prefix character\n\ 7756 --bitwise-or do not treat `|' as a comment character\n\ 7757 --base-size-default-16 base reg without size is 16 bits\n\ 7758 --base-size-default-32 base reg without size is 32 bits (default)\n\ 7759 --disp-size-default-16 displacement with unknown size is 16 bits\n\ 7760 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\ 7761 ")); 7762 7763 fprintf (stream, _("Architecture variants are: ")); 7764 for (i = 0; m68k_archs[i].name; i++) 7765 { 7766 if (i) 7767 fprintf (stream, " | "); 7768 fprintf (stream, "%s", m68k_archs[i].name); 7769 } 7770 fprintf (stream, "\n"); 7771 7772 fprintf (stream, _("Processor variants are: ")); 7773 for (i = 0; m68k_cpus[i].name; i++) 7774 { 7775 if (i) 7776 fprintf (stream, " | "); 7777 fprintf (stream, "%s", m68k_cpus[i].name); 7778 } 7779 fprintf (stream, _("\n")); 7780 } 7781 7782 #ifdef TEST2 7783 7784 /* TEST2: Test md_assemble() */ 7785 /* Warning, this routine probably doesn't work anymore. */ 7786 int 7787 main (void) 7788 { 7789 struct m68k_it the_ins; 7790 char buf[120]; 7791 char *cp; 7792 int n; 7793 7794 m68k_ip_begin (); 7795 for (;;) 7796 { 7797 if (!gets (buf) || !*buf) 7798 break; 7799 if (buf[0] == '|' || buf[1] == '.') 7800 continue; 7801 for (cp = buf; *cp; cp++) 7802 if (*cp == '\t') 7803 *cp = ' '; 7804 if (is_label (buf)) 7805 continue; 7806 memset (&the_ins, '\0', sizeof (the_ins)); 7807 m68k_ip (&the_ins, buf); 7808 if (the_ins.error) 7809 { 7810 printf (_("Error %s in %s\n"), the_ins.error, buf); 7811 } 7812 else 7813 { 7814 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args); 7815 for (n = 0; n < the_ins.numo; n++) 7816 printf (" 0x%x", the_ins.opcode[n] & 0xffff); 7817 printf (" "); 7818 print_the_insn (&the_ins.opcode[0], stdout); 7819 (void) putchar ('\n'); 7820 } 7821 for (n = 0; n < strlen (the_ins.args) / 2; n++) 7822 { 7823 if (the_ins.operands[n].error) 7824 { 7825 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf); 7826 continue; 7827 } 7828 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, 7829 the_ins.operands[n].reg); 7830 if (the_ins.operands[n].b_const) 7831 printf ("Constant: '%.*s', ", 7832 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, 7833 the_ins.operands[n].b_const); 7834 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, 7835 the_ins.operands[n].isiz, the_ins.operands[n].imul); 7836 if (the_ins.operands[n].b_iadd) 7837 printf ("Iadd: '%.*s',", 7838 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, 7839 the_ins.operands[n].b_iadd); 7840 putchar ('\n'); 7841 } 7842 } 7843 m68k_ip_end (); 7844 return 0; 7845 } 7846 7847 int 7848 is_label (char *str) 7849 { 7850 while (*str == ' ') 7851 str++; 7852 while (*str && *str != ' ') 7853 str++; 7854 if (str[-1] == ':' || str[1] == '=') 7855 return 1; 7856 return 0; 7857 } 7858 7859 #endif 7860 7861 /* Possible states for relaxation: 7862 7863 0 0 branch offset byte (bra, etc) 7864 0 1 word 7865 0 2 long 7866 7867 1 0 indexed offsets byte a0@(32,d4:w:1) etc 7868 1 1 word 7869 1 2 long 7870 7871 2 0 two-offset index word-word a0@(32,d4)@(45) etc 7872 2 1 word-long 7873 2 2 long-word 7874 2 3 long-long 7875 7876 */ 7877 7878 /* We have no need to default values of symbols. */ 7879 7880 symbolS * 7881 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 7882 { 7883 return 0; 7884 } 7885 7886 /* Round up a section size to the appropriate boundary. */ 7887 valueT 7888 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 7889 { 7890 #ifdef OBJ_AOUT 7891 /* For a.out, force the section size to be aligned. If we don't do 7892 this, BFD will align it for us, but it will not write out the 7893 final bytes of the section. This may be a bug in BFD, but it is 7894 easier to fix it here since that is how the other a.out targets 7895 work. */ 7896 int align; 7897 7898 align = bfd_get_section_alignment (stdoutput, segment); 7899 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 7900 #endif 7901 7902 return size; 7903 } 7904 7905 /* Exactly what point is a PC-relative offset relative TO? 7906 On the 68k, it is relative to the address of the first extension 7907 word. The difference between the addresses of the offset and the 7908 first extension word is stored in fx_pcrel_adjust. */ 7909 long 7910 md_pcrel_from (fixS *fixP) 7911 { 7912 int adjust; 7913 7914 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly 7915 sign extend the value here. */ 7916 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80; 7917 if (adjust == 64) 7918 adjust = -1; 7919 return fixP->fx_where + fixP->fx_frag->fr_address - adjust; 7920 } 7921 7922 #ifdef OBJ_ELF 7923 void 7924 m68k_elf_final_processing (void) 7925 { 7926 unsigned flags = 0; 7927 7928 if (arch_coldfire_fpu (current_architecture)) 7929 flags |= EF_M68K_CFV4E; 7930 /* Set file-specific flags if this is a cpu32 processor. */ 7931 if (cpu_of_arch (current_architecture) & cpu32) 7932 flags |= EF_M68K_CPU32; 7933 else if (cpu_of_arch (current_architecture) & fido_a) 7934 flags |= EF_M68K_FIDO; 7935 else if ((cpu_of_arch (current_architecture) & m68000up) 7936 && !(cpu_of_arch (current_architecture) & m68020up)) 7937 flags |= EF_M68K_M68000; 7938 7939 if (current_architecture & mcfisa_a) 7940 { 7941 static const unsigned isa_features[][2] = 7942 { 7943 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a}, 7944 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv}, 7945 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp}, 7946 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv}, 7947 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp}, 7948 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp}, 7949 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp}, 7950 {0,0}, 7951 }; 7952 static const unsigned mac_features[][2] = 7953 { 7954 {EF_M68K_CF_MAC, mcfmac}, 7955 {EF_M68K_CF_EMAC, mcfemac}, 7956 {0,0}, 7957 }; 7958 unsigned ix; 7959 unsigned pattern; 7960 7961 pattern = (current_architecture 7962 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp)); 7963 for (ix = 0; isa_features[ix][1]; ix++) 7964 { 7965 if (pattern == isa_features[ix][1]) 7966 { 7967 flags |= isa_features[ix][0]; 7968 break; 7969 } 7970 } 7971 if (!isa_features[ix][1]) 7972 { 7973 cf_bad: 7974 as_warn (_("Not a defined coldfire architecture")); 7975 } 7976 else 7977 { 7978 if (current_architecture & cfloat) 7979 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E; 7980 7981 pattern = current_architecture & (mcfmac|mcfemac); 7982 if (pattern) 7983 { 7984 for (ix = 0; mac_features[ix][1]; ix++) 7985 { 7986 if (pattern == mac_features[ix][1]) 7987 { 7988 flags |= mac_features[ix][0]; 7989 break; 7990 } 7991 } 7992 if (!mac_features[ix][1]) 7993 goto cf_bad; 7994 } 7995 } 7996 } 7997 elf_elfheader (stdoutput)->e_flags |= flags; 7998 } 7999 8000 /* Parse @TLSLDO and return the desired relocation. */ 8001 static bfd_reloc_code_real_type 8002 m68k_elf_suffix (char **str_p, expressionS *exp_p) 8003 { 8004 char ident[20]; 8005 char *str = *str_p; 8006 char *str2; 8007 int ch; 8008 int len; 8009 8010 if (*str++ != '@') 8011 return BFD_RELOC_UNUSED; 8012 8013 for (ch = *str, str2 = ident; 8014 (str2 < ident + sizeof (ident) - 1 8015 && (ISALNUM (ch) || ch == '@')); 8016 ch = *++str) 8017 { 8018 *str2++ = ch; 8019 } 8020 8021 *str2 = '\0'; 8022 len = str2 - ident; 8023 8024 if (strncmp (ident, "TLSLDO", 6) == 0 8025 && len == 6) 8026 { 8027 /* Now check for identifier@suffix+constant. */ 8028 if (*str == '-' || *str == '+') 8029 { 8030 char *orig_line = input_line_pointer; 8031 expressionS new_exp; 8032 8033 input_line_pointer = str; 8034 expression (&new_exp); 8035 if (new_exp.X_op == O_constant) 8036 { 8037 exp_p->X_add_number += new_exp.X_add_number; 8038 str = input_line_pointer; 8039 } 8040 8041 if (&input_line_pointer != str_p) 8042 input_line_pointer = orig_line; 8043 } 8044 *str_p = str; 8045 8046 return BFD_RELOC_68K_TLS_LDO32; 8047 } 8048 8049 return BFD_RELOC_UNUSED; 8050 } 8051 8052 /* Handles .long <tls_symbol>+0x8000 debug info. 8053 Clobbers input_line_pointer, checks end-of-line. 8054 Adapted from tc-ppc.c:ppc_elf_cons. */ 8055 static void 8056 m68k_elf_cons (int nbytes /* 4=.long */) 8057 { 8058 if (is_it_end_of_statement ()) 8059 { 8060 demand_empty_rest_of_line (); 8061 return; 8062 } 8063 8064 do 8065 { 8066 expressionS exp; 8067 bfd_reloc_code_real_type reloc; 8068 8069 expression (&exp); 8070 if (exp.X_op == O_symbol 8071 && *input_line_pointer == '@' 8072 && (reloc = m68k_elf_suffix (&input_line_pointer, 8073 &exp)) != BFD_RELOC_UNUSED) 8074 { 8075 reloc_howto_type *reloc_howto; 8076 int size; 8077 8078 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); 8079 size = bfd_get_reloc_size (reloc_howto); 8080 8081 if (size > nbytes) 8082 { 8083 as_bad (_("%s relocations do not fit in %d bytes\n"), 8084 reloc_howto->name, nbytes); 8085 } 8086 else 8087 { 8088 char *p; 8089 int offset; 8090 8091 p = frag_more (nbytes); 8092 offset = 0; 8093 if (target_big_endian) 8094 offset = nbytes - size; 8095 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, 8096 &exp, 0, reloc); 8097 } 8098 } 8099 else 8100 emit_expr (&exp, (unsigned int) nbytes); 8101 } 8102 while (*input_line_pointer++ == ','); 8103 8104 /* Put terminator back into stream. */ 8105 input_line_pointer--; 8106 demand_empty_rest_of_line (); 8107 } 8108 #endif 8109 8110 int 8111 tc_m68k_regname_to_dw2regnum (char *regname) 8112 { 8113 unsigned int regnum; 8114 static const char *const regnames[] = 8115 { 8116 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 8117 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", 8118 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", 8119 "pc" 8120 }; 8121 8122 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) 8123 if (strcmp (regname, regnames[regnum]) == 0) 8124 return regnum; 8125 8126 return -1; 8127 } 8128 8129 void 8130 tc_m68k_frame_initial_instructions (void) 8131 { 8132 static int sp_regno = -1; 8133 8134 if (sp_regno < 0) 8135 sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); 8136 8137 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); 8138 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); 8139 } 8140