1 /* tc-cr16.c -- Assembler code for the CR16 CPU core. 2 Copyright (C) 2007-2018 Free Software Foundation, Inc. 3 4 Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com> 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23 #include "as.h" 24 #include "safe-ctype.h" 25 #include "dwarf2dbg.h" 26 #include "opcode/cr16.h" 27 #include "elf/cr16.h" 28 29 30 /* Word is considered here as a 16-bit unsigned short int. */ 31 #define WORD_SHIFT 16 32 33 /* Register is 2-byte size. */ 34 #define REG_SIZE 2 35 36 /* Maximum size of a single instruction (in words). */ 37 #define INSN_MAX_SIZE 3 38 39 /* Maximum bits which may be set in a `mask16' operand. */ 40 #define MAX_REGS_IN_MASK16 8 41 42 /* Assign a number NUM, shifted by SHIFT bytes, into a location 43 pointed by index BYTE of array 'output_opcode'. */ 44 #define CR16_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT) 45 46 /* Operand errors. */ 47 typedef enum 48 { 49 OP_LEGAL = 0, /* Legal operand. */ 50 OP_OUT_OF_RANGE, /* Operand not within permitted range. */ 51 OP_NOT_EVEN /* Operand is Odd number, should be even. */ 52 } 53 op_err; 54 55 /* Opcode mnemonics hash table. */ 56 static struct hash_control *cr16_inst_hash; 57 /* CR16 registers hash table. */ 58 static struct hash_control *reg_hash; 59 /* CR16 register pair hash table. */ 60 static struct hash_control *regp_hash; 61 /* CR16 processor registers hash table. */ 62 static struct hash_control *preg_hash; 63 /* CR16 processor registers 32 bit hash table. */ 64 static struct hash_control *pregp_hash; 65 /* Current instruction we're assembling. */ 66 const inst *instruction; 67 68 69 static int code_label = 0; 70 71 /* Global variables. */ 72 73 /* Array to hold an instruction encoding. */ 74 long output_opcode[2]; 75 76 /* Nonzero means a relocatable symbol. */ 77 int relocatable; 78 79 /* A copy of the original instruction (used in error messages). */ 80 char ins_parse[MAX_INST_LEN]; 81 82 /* The current processed argument number. */ 83 int cur_arg_num; 84 85 /* Generic assembler global variables which must be defined by all targets. */ 86 87 /* Characters which always start a comment. */ 88 const char comment_chars[] = "#"; 89 90 /* Characters which start a comment at the beginning of a line. */ 91 const char line_comment_chars[] = "#"; 92 93 /* This array holds machine specific line separator characters. */ 94 const char line_separator_chars[] = ";"; 95 96 /* Chars that can be used to separate mant from exp in floating point nums. */ 97 const char EXP_CHARS[] = "eE"; 98 99 /* Chars that mean this number is a floating point constant as in 0f12.456 */ 100 const char FLT_CHARS[] = "f'"; 101 102 #ifdef OBJ_ELF 103 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ 104 symbolS * GOT_symbol; 105 #endif 106 107 /* Target-specific multicharacter options, not const-declared at usage. */ 108 const char *md_shortopts = ""; 109 struct option md_longopts[] = 110 { 111 {NULL, no_argument, NULL, 0} 112 }; 113 size_t md_longopts_size = sizeof (md_longopts); 114 115 static void 116 l_cons (int nbytes) 117 { 118 int c; 119 expressionS exp; 120 121 #ifdef md_flush_pending_output 122 md_flush_pending_output (); 123 #endif 124 125 if (is_it_end_of_statement ()) 126 { 127 demand_empty_rest_of_line (); 128 return; 129 } 130 131 #ifdef TC_ADDRESS_BYTES 132 if (nbytes == 0) 133 nbytes = TC_ADDRESS_BYTES (); 134 #endif 135 136 #ifdef md_cons_align 137 md_cons_align (nbytes); 138 #endif 139 140 c = 0; 141 do 142 { 143 unsigned int bits_available = BITS_PER_CHAR * nbytes; 144 char *hold = input_line_pointer; 145 146 expression (&exp); 147 148 if (*input_line_pointer == ':') 149 { 150 /* Bitfields. */ 151 long value = 0; 152 153 for (;;) 154 { 155 unsigned long width; 156 157 if (*input_line_pointer != ':') 158 { 159 input_line_pointer = hold; 160 break; 161 } 162 if (exp.X_op == O_absent) 163 { 164 as_warn (_("using a bit field width of zero")); 165 exp.X_add_number = 0; 166 exp.X_op = O_constant; 167 } 168 169 if (exp.X_op != O_constant) 170 { 171 *input_line_pointer = '\0'; 172 as_bad (_("field width \"%s\" too complex for a bitfield"), hold); 173 *input_line_pointer = ':'; 174 demand_empty_rest_of_line (); 175 return; 176 } 177 178 if ((width = exp.X_add_number) > 179 (unsigned int)(BITS_PER_CHAR * nbytes)) 180 { 181 as_warn (ngettext ("field width %lu too big to fit in %d" 182 " byte: truncated to %d bits", 183 "field width %lu too big to fit in %d" 184 " bytes: truncated to %d bits", 185 nbytes), 186 width, nbytes, (BITS_PER_CHAR * nbytes)); 187 width = BITS_PER_CHAR * nbytes; 188 } /* Too big. */ 189 190 191 if (width > bits_available) 192 { 193 /* FIXME-SOMEDAY: backing up and reparsing is wasteful. */ 194 input_line_pointer = hold; 195 exp.X_add_number = value; 196 break; 197 } 198 199 /* Skip ':'. */ 200 hold = ++input_line_pointer; 201 202 expression (&exp); 203 if (exp.X_op != O_constant) 204 { 205 char cache = *input_line_pointer; 206 207 *input_line_pointer = '\0'; 208 as_bad (_("field value \"%s\" too complex for a bitfield"), hold); 209 *input_line_pointer = cache; 210 demand_empty_rest_of_line (); 211 return; 212 } 213 214 value |= ((~(-(1 << width)) & exp.X_add_number) 215 << ((BITS_PER_CHAR * nbytes) - bits_available)); 216 217 if ((bits_available -= width) == 0 218 || is_it_end_of_statement () 219 || *input_line_pointer != ',') 220 break; 221 222 hold = ++input_line_pointer; 223 expression (&exp); 224 } 225 226 exp.X_add_number = value; 227 exp.X_op = O_constant; 228 exp.X_unsigned = 1; 229 } 230 231 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c')) 232 code_label = 1; 233 emit_expr (&exp, (unsigned int) nbytes); 234 ++c; 235 if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c')) 236 { 237 input_line_pointer +=3; 238 break; 239 } 240 } 241 while ((*input_line_pointer++ == ',')); 242 243 /* Put terminator back into stream. */ 244 input_line_pointer--; 245 246 demand_empty_rest_of_line (); 247 } 248 249 /* This table describes all the machine specific pseudo-ops 250 the assembler has to support. The fields are: 251 *** Pseudo-op name without dot. 252 *** Function to call to execute this pseudo-op. 253 *** Integer arg to pass to the function. */ 254 255 const pseudo_typeS md_pseudo_table[] = 256 { 257 /* In CR16 machine, align is in bytes (not a ptwo boundary). */ 258 {"align", s_align_bytes, 0}, 259 {"long", l_cons, 4 }, 260 {"4byte", l_cons, 4 }, 261 {0, 0, 0} 262 }; 263 264 /* CR16 relaxation table. */ 265 const relax_typeS md_relax_table[] = 266 { 267 /* bCC */ 268 {0x7f, -0x80, 2, 1}, /* 8 */ 269 {0xfffe, -0x10000, 4, 2}, /* 16 */ 270 {0xfffffe, -0x1000000, 6, 0}, /* 24 */ 271 }; 272 273 /* Return the bit size for a given operand. */ 274 275 static int 276 get_opbits (operand_type op) 277 { 278 if (op < MAX_OPRD) 279 return cr16_optab[op].bit_size; 280 281 return 0; 282 } 283 284 /* Return the argument type of a given operand. */ 285 286 static argtype 287 get_optype (operand_type op) 288 { 289 if (op < MAX_OPRD) 290 return cr16_optab[op].arg_type; 291 else 292 return nullargs; 293 } 294 295 /* Return the flags of a given operand. */ 296 297 static int 298 get_opflags (operand_type op) 299 { 300 if (op < MAX_OPRD) 301 return cr16_optab[op].flags; 302 303 return 0; 304 } 305 306 /* Get the cc code. */ 307 308 static int 309 get_cc (char *cc_name) 310 { 311 unsigned int i; 312 313 for (i = 0; i < cr16_num_cc; i++) 314 if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0) 315 return i; 316 317 return -1; 318 } 319 320 /* Get the core processor register 'reg_name'. */ 321 322 static reg 323 get_register (char *reg_name) 324 { 325 const reg_entry *rreg; 326 327 rreg = (const reg_entry *) hash_find (reg_hash, reg_name); 328 329 if (rreg != NULL) 330 return rreg->value.reg_val; 331 332 return nullregister; 333 } 334 /* Get the core processor register-pair 'reg_name'. */ 335 336 static reg 337 get_register_pair (char *reg_name) 338 { 339 const reg_entry *rreg; 340 char tmp_rp[16]="\0"; 341 342 /* Add '(' and ')' to the reg pair, if it's not present. */ 343 if (reg_name[0] != '(') 344 { 345 tmp_rp[0] = '('; 346 strcat (tmp_rp, reg_name); 347 strcat (tmp_rp,")"); 348 rreg = (const reg_entry *) hash_find (regp_hash, tmp_rp); 349 } 350 else 351 rreg = (const reg_entry *) hash_find (regp_hash, reg_name); 352 353 if (rreg != NULL) 354 return rreg->value.reg_val; 355 356 return nullregister; 357 } 358 359 /* Get the index register 'reg_name'. */ 360 361 static reg 362 get_index_register (char *reg_name) 363 { 364 const reg_entry *rreg; 365 366 rreg = (const reg_entry *) hash_find (reg_hash, reg_name); 367 368 if ((rreg != NULL) 369 && ((rreg->value.reg_val == 12) || (rreg->value.reg_val == 13))) 370 return rreg->value.reg_val; 371 372 return nullregister; 373 } 374 /* Get the core processor index register-pair 'reg_name'. */ 375 376 static reg 377 get_index_register_pair (char *reg_name) 378 { 379 const reg_entry *rreg; 380 381 rreg = (const reg_entry *) hash_find (regp_hash, reg_name); 382 383 if (rreg != NULL) 384 { 385 if ((rreg->value.reg_val != 1) || (rreg->value.reg_val != 7) 386 || (rreg->value.reg_val != 9) || (rreg->value.reg_val > 10)) 387 return rreg->value.reg_val; 388 389 as_bad (_("Unknown register pair - index relative mode: `%d'"), rreg->value.reg_val); 390 } 391 392 return nullregister; 393 } 394 395 /* Get the processor register 'preg_name'. */ 396 397 static preg 398 get_pregister (char *preg_name) 399 { 400 const reg_entry *prreg; 401 402 prreg = (const reg_entry *) hash_find (preg_hash, preg_name); 403 404 if (prreg != NULL) 405 return prreg->value.preg_val; 406 407 return nullpregister; 408 } 409 410 /* Get the processor register 'preg_name 32 bit'. */ 411 412 static preg 413 get_pregisterp (char *preg_name) 414 { 415 const reg_entry *prreg; 416 417 prreg = (const reg_entry *) hash_find (pregp_hash, preg_name); 418 419 if (prreg != NULL) 420 return prreg->value.preg_val; 421 422 return nullpregister; 423 } 424 425 426 /* Round up a section size to the appropriate boundary. */ 427 428 valueT 429 md_section_align (segT seg, valueT val) 430 { 431 /* Round .text section to a multiple of 2. */ 432 if (seg == text_section) 433 return (val + 1) & ~1; 434 return val; 435 } 436 437 /* Parse an operand that is machine-specific (remove '*'). */ 438 439 void 440 md_operand (expressionS * exp) 441 { 442 char c = *input_line_pointer; 443 444 switch (c) 445 { 446 case '*': 447 input_line_pointer++; 448 expression (exp); 449 break; 450 default: 451 break; 452 } 453 } 454 455 /* Reset global variables before parsing a new instruction. */ 456 457 static void 458 reset_vars (char *op) 459 { 460 cur_arg_num = relocatable = 0; 461 memset (& output_opcode, '\0', sizeof (output_opcode)); 462 463 /* Save a copy of the original OP (used in error messages). */ 464 strncpy (ins_parse, op, sizeof ins_parse - 1); 465 ins_parse [sizeof ins_parse - 1] = 0; 466 } 467 468 /* This macro decides whether a particular reloc is an entry in a 469 switch table. It is used when relaxing, because the linker needs 470 to know about all such entries so that it can adjust them if 471 necessary. */ 472 473 #define SWITCH_TABLE(fix) \ 474 ( (fix)->fx_addsy != NULL \ 475 && (fix)->fx_subsy != NULL \ 476 && S_GET_SEGMENT ((fix)->fx_addsy) == \ 477 S_GET_SEGMENT ((fix)->fx_subsy) \ 478 && S_GET_SEGMENT (fix->fx_addsy) != undefined_section \ 479 && ( (fix)->fx_r_type == BFD_RELOC_CR16_NUM8 \ 480 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16 \ 481 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32 \ 482 || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a)) 483 484 /* See whether we need to force a relocation into the output file. 485 This is used to force out switch and PC relative relocations when 486 relaxing. */ 487 488 int 489 cr16_force_relocation (fixS *fix) 490 { 491 if (generic_force_reloc (fix) || SWITCH_TABLE (fix)) 492 return 1; 493 494 return 0; 495 } 496 497 /* Record a fixup for a cons expression. */ 498 499 void 500 cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp, 501 bfd_reloc_code_real_type rtype) 502 { 503 switch (len) 504 { 505 default: rtype = BFD_RELOC_NONE; break; 506 case 1: rtype = BFD_RELOC_CR16_NUM8 ; break; 507 case 2: rtype = BFD_RELOC_CR16_NUM16; break; 508 case 4: 509 if (code_label) 510 { 511 rtype = BFD_RELOC_CR16_NUM32a; 512 code_label = 0; 513 } 514 else 515 rtype = BFD_RELOC_CR16_NUM32; 516 break; 517 } 518 519 fix_new_exp (frag, offset, len, exp, 0, rtype); 520 } 521 522 /* Generate a relocation entry for a fixup. */ 523 524 arelent * 525 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP) 526 { 527 arelent * reloc; 528 529 /* If symbols are local and resolved, then no relocation needed. */ 530 if ( ((fixP->fx_addsy) 531 && (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section)) 532 || ((fixP->fx_subsy) 533 && (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section))) 534 return NULL; 535 536 reloc = XNEW (arelent); 537 reloc->sym_ptr_ptr = XNEW (asymbol *); 538 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 539 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; 540 reloc->addend = fixP->fx_offset; 541 542 if (fixP->fx_subsy != NULL) 543 { 544 if (SWITCH_TABLE (fixP)) 545 { 546 /* Keep the current difference in the addend. */ 547 reloc->addend = (S_GET_VALUE (fixP->fx_addsy) 548 - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset); 549 550 switch (fixP->fx_r_type) 551 { 552 case BFD_RELOC_CR16_NUM8: 553 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH8; 554 break; 555 case BFD_RELOC_CR16_NUM16: 556 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH16; 557 break; 558 case BFD_RELOC_CR16_NUM32: 559 fixP->fx_r_type = BFD_RELOC_CR16_SWITCH32; 560 break; 561 case BFD_RELOC_CR16_NUM32a: 562 fixP->fx_r_type = BFD_RELOC_CR16_NUM32a; 563 break; 564 default: 565 abort (); 566 break; 567 } 568 } 569 else 570 { 571 /* We only resolve difference expressions in the same section. */ 572 as_bad_where (fixP->fx_file, fixP->fx_line, 573 _("can't resolve `%s' {%s section} - `%s' {%s section}"), 574 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0", 575 segment_name (fixP->fx_addsy 576 ? S_GET_SEGMENT (fixP->fx_addsy) 577 : absolute_section), 578 S_GET_NAME (fixP->fx_subsy), 579 segment_name (S_GET_SEGMENT (fixP->fx_addsy))); 580 } 581 } 582 #ifdef OBJ_ELF 583 if ((fixP->fx_r_type == BFD_RELOC_CR16_GOT_REGREL20) 584 && GOT_symbol 585 && fixP->fx_addsy == GOT_symbol) 586 { 587 reloc->addend = fixP->fx_offset = reloc->address; 588 } 589 else if ((fixP->fx_r_type == BFD_RELOC_CR16_GOTC_REGREL20) 590 && GOT_symbol 591 && fixP->fx_addsy == GOT_symbol) 592 { 593 reloc->addend = fixP->fx_offset = reloc->address; 594 } 595 #endif 596 597 gas_assert ((int) fixP->fx_r_type > 0); 598 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); 599 600 if (reloc->howto == NULL) 601 { 602 as_bad_where (fixP->fx_file, fixP->fx_line, 603 _("internal error: reloc %d (`%s') not supported by object file format"), 604 fixP->fx_r_type, 605 bfd_get_reloc_code_name (fixP->fx_r_type)); 606 return NULL; 607 } 608 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative); 609 610 return reloc; 611 } 612 613 /* Prepare machine-dependent frags for relaxation. */ 614 615 int 616 md_estimate_size_before_relax (fragS *fragp, asection *seg) 617 { 618 /* If symbol is undefined or located in a different section, 619 select the largest supported relocation. */ 620 relax_substateT subtype; 621 relax_substateT rlx_state[] = {0, 2}; 622 623 for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2) 624 { 625 if (fragp->fr_subtype == rlx_state[subtype] 626 && (!S_IS_DEFINED (fragp->fr_symbol) 627 || seg != S_GET_SEGMENT (fragp->fr_symbol))) 628 { 629 fragp->fr_subtype = rlx_state[subtype + 1]; 630 break; 631 } 632 } 633 634 if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table)) 635 abort (); 636 637 return md_relax_table[fragp->fr_subtype].rlx_length; 638 } 639 640 void 641 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP) 642 { 643 /* 'opcode' points to the start of the instruction, whether 644 we need to change the instruction's fixed encoding. */ 645 char *opcode = fragP->fr_literal + fragP->fr_fix; 646 bfd_reloc_code_real_type reloc; 647 648 subseg_change (sec, 0); 649 650 switch (fragP->fr_subtype) 651 { 652 case 0: 653 reloc = BFD_RELOC_CR16_DISP8; 654 break; 655 case 1: 656 /* If the subtype is not changed due to :m operand qualifier, 657 then no need to update the opcode value. */ 658 if ((int)opcode[1] != 0x18) 659 { 660 opcode[0] = (opcode[0] & 0xf0); 661 opcode[1] = 0x18; 662 } 663 reloc = BFD_RELOC_CR16_DISP16; 664 break; 665 case 2: 666 /* If the subtype is not changed due to :l operand qualifier, 667 then no need to update the opcode value. */ 668 if ((int)opcode[1] != 0) 669 { 670 opcode[2] = opcode[0]; 671 opcode[0] = opcode[1]; 672 opcode[1] = 0x0; 673 } 674 reloc = BFD_RELOC_CR16_DISP24; 675 break; 676 default: 677 abort(); 678 } 679 680 fix_new (fragP, fragP->fr_fix, 681 bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)), 682 fragP->fr_symbol, fragP->fr_offset, 1, reloc); 683 fragP->fr_var = 0; 684 fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length; 685 } 686 687 symbolS * 688 md_undefined_symbol (char *name) 689 { 690 if (*name == '_' && *(name + 1) == 'G' 691 && strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0) 692 { 693 if (!GOT_symbol) 694 { 695 if (symbol_find (name)) 696 as_bad (_("GOT already in symbol table")); 697 GOT_symbol = symbol_new (name, undefined_section, 698 (valueT) 0, &zero_address_frag); 699 } 700 return GOT_symbol; 701 } 702 return 0; 703 } 704 705 /* Process machine-dependent command line options. Called once for 706 each option on the command line that the machine-independent part of 707 GAS does not understand. */ 708 709 int 710 md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED) 711 { 712 return 0; 713 } 714 715 /* Machine-dependent usage-output. */ 716 717 void 718 md_show_usage (FILE *stream ATTRIBUTE_UNUSED) 719 { 720 return; 721 } 722 723 const char * 724 md_atof (int type, char *litP, int *sizeP) 725 { 726 return ieee_md_atof (type, litP, sizeP, target_big_endian); 727 } 728 729 /* Apply a fixS (fixup of an instruction or data that we didn't have 730 enough info to complete immediately) to the data in a frag. 731 Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable 732 relaxation of debug sections, this function is called only when 733 fixuping relocations of debug sections. */ 734 735 void 736 md_apply_fix (fixS *fixP, valueT *valP, segT seg) 737 { 738 valueT val = * valP; 739 740 if (fixP->fx_addsy == NULL 741 && fixP->fx_pcrel == 0) 742 fixP->fx_done = 1; 743 else if (fixP->fx_pcrel == 1 744 && fixP->fx_addsy != NULL 745 && S_GET_SEGMENT (fixP->fx_addsy) == seg) 746 fixP->fx_done = 1; 747 else 748 fixP->fx_done = 0; 749 750 if (fixP->fx_addsy != NULL && !fixP->fx_pcrel) 751 { 752 val = fixP->fx_offset; 753 fixP->fx_done = 1; 754 } 755 756 if (fixP->fx_done) 757 { 758 char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; 759 760 fixP->fx_offset = 0; 761 762 switch (fixP->fx_r_type) 763 { 764 case BFD_RELOC_CR16_NUM8: 765 bfd_put_8 (stdoutput, (unsigned char) val, buf); 766 break; 767 case BFD_RELOC_CR16_NUM16: 768 bfd_put_16 (stdoutput, val, buf); 769 break; 770 case BFD_RELOC_CR16_NUM32: 771 bfd_put_32 (stdoutput, val, buf); 772 break; 773 case BFD_RELOC_CR16_NUM32a: 774 bfd_put_32 (stdoutput, val, buf); 775 break; 776 default: 777 /* We shouldn't ever get here because linkrelax is nonzero. */ 778 abort (); 779 break; 780 } 781 fixP->fx_done = 0; 782 } 783 else 784 fixP->fx_offset = * valP; 785 } 786 787 /* The location from which a PC relative jump should be calculated, 788 given a PC relative reloc. */ 789 790 long 791 md_pcrel_from (fixS *fixp) 792 { 793 return fixp->fx_frag->fr_address + fixp->fx_where; 794 } 795 796 static void 797 initialise_reg_hash_table (struct hash_control ** hash_table, 798 const reg_entry * register_table, 799 const unsigned int num_entries) 800 { 801 const reg_entry * rreg; 802 const char *hashret; 803 804 if ((* hash_table = hash_new ()) == NULL) 805 as_fatal (_("Virtual memory exhausted")); 806 807 for (rreg = register_table; 808 rreg < (register_table + num_entries); 809 rreg++) 810 { 811 hashret = hash_insert (* hash_table, rreg->name, (char *) rreg); 812 if (hashret) 813 as_fatal (_("Internal Error: Can't hash %s: %s"), 814 rreg->name, hashret); 815 } 816 } 817 818 /* This function is called once, at assembler startup time. This should 819 set up all the tables, etc that the MD part of the assembler needs. */ 820 821 void 822 md_begin (void) 823 { 824 int i = 0; 825 826 /* Set up a hash table for the instructions. */ 827 if ((cr16_inst_hash = hash_new ()) == NULL) 828 as_fatal (_("Virtual memory exhausted")); 829 830 while (cr16_instruction[i].mnemonic != NULL) 831 { 832 const char *hashret; 833 const char *mnemonic = cr16_instruction[i].mnemonic; 834 835 hashret = hash_insert (cr16_inst_hash, mnemonic, 836 (char *)(cr16_instruction + i)); 837 838 if (hashret != NULL && *hashret != '\0') 839 as_fatal (_("Can't hash `%s': %s\n"), cr16_instruction[i].mnemonic, 840 *hashret == 0 ? _("(unknown reason)") : hashret); 841 842 /* Insert unique names into hash table. The CR16 instruction set 843 has many identical opcode names that have different opcodes based 844 on the operands. This hash table then provides a quick index to 845 the first opcode with a particular name in the opcode table. */ 846 do 847 { 848 ++i; 849 } 850 while (cr16_instruction[i].mnemonic != NULL 851 && streq (cr16_instruction[i].mnemonic, mnemonic)); 852 } 853 854 /* Initialize reg_hash hash table. */ 855 initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS); 856 /* Initialize regp_hash hash table. */ 857 initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS); 858 /* Initialize preg_hash hash table. */ 859 initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS); 860 /* Initialize pregp_hash hash table. */ 861 initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS); 862 863 /* Set linkrelax here to avoid fixups in most sections. */ 864 linkrelax = 1; 865 } 866 867 /* Process constants (immediate/absolute) 868 and labels (jump targets/Memory locations). */ 869 870 static void 871 process_label_constant (char *str, ins * cr16_ins) 872 { 873 char *saved_input_line_pointer; 874 int symbol_with_at = 0; 875 int symbol_with_s = 0; 876 int symbol_with_m = 0; 877 int symbol_with_l = 0; 878 int symbol_with_at_got = 0; 879 int symbol_with_at_gotc = 0; 880 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */ 881 882 saved_input_line_pointer = input_line_pointer; 883 input_line_pointer = str; 884 885 expression (&cr16_ins->exp); 886 887 switch (cr16_ins->exp.X_op) 888 { 889 case O_big: 890 case O_absent: 891 /* Missing or bad expr becomes absolute 0. */ 892 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 893 str); 894 cr16_ins->exp.X_op = O_constant; 895 cr16_ins->exp.X_add_number = 0; 896 cr16_ins->exp.X_add_symbol = NULL; 897 cr16_ins->exp.X_op_symbol = NULL; 898 /* Fall through. */ 899 900 case O_constant: 901 cur_arg->X_op = O_constant; 902 cur_arg->constant = cr16_ins->exp.X_add_number; 903 break; 904 905 case O_symbol: 906 case O_subtract: 907 case O_add: 908 cur_arg->X_op = O_symbol; 909 cur_arg->constant = cr16_ins->exp.X_add_number; 910 cr16_ins->exp.X_add_number = 0; 911 cr16_ins->rtype = BFD_RELOC_NONE; 912 relocatable = 1; 913 914 if (strneq (input_line_pointer, "@c", 2)) 915 symbol_with_at = 1; 916 917 if (strneq (input_line_pointer, "@l", 2) 918 || strneq (input_line_pointer, ":l", 2)) 919 symbol_with_l = 1; 920 921 if (strneq (input_line_pointer, "@m", 2) 922 || strneq (input_line_pointer, ":m", 2)) 923 symbol_with_m = 1; 924 925 if (strneq (input_line_pointer, "@s", 2) 926 || strneq (input_line_pointer, ":s", 2)) 927 symbol_with_s = 1; 928 929 if (strneq (input_line_pointer, "@cGOT", 5) 930 || strneq (input_line_pointer, "@cgot", 5)) 931 { 932 if (GOT_symbol == NULL) 933 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 934 935 symbol_with_at_gotc = 1; 936 } 937 else if (strneq (input_line_pointer, "@GOT", 4) 938 || strneq (input_line_pointer, "@got", 4)) 939 { 940 if ((strneq (input_line_pointer, "+", 1)) 941 || (strneq (input_line_pointer, "-", 1))) 942 as_warn (_("GOT bad expression with %s."), input_line_pointer); 943 944 if (GOT_symbol == NULL) 945 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 946 947 symbol_with_at_got = 1; 948 } 949 950 switch (cur_arg->type) 951 { 952 case arg_cr: 953 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 954 { 955 if (symbol_with_at_got) 956 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 957 else if (symbol_with_at_gotc) 958 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 959 else if (cur_arg->size == 20) 960 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 961 else 962 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a; 963 } 964 break; 965 966 case arg_crp: 967 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 968 { 969 if (symbol_with_at_got) 970 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 971 else if (symbol_with_at_gotc) 972 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 973 } else { 974 switch (instruction->size) 975 { 976 case 1: 977 switch (cur_arg->size) 978 { 979 case 0: 980 cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; 981 break; 982 case 4: 983 if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb")) 984 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4; 985 else 986 cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a; 987 break; 988 default: break; 989 } 990 break; 991 case 2: 992 cr16_ins->rtype = BFD_RELOC_CR16_REGREL16; 993 break; 994 case 3: 995 if (cur_arg->size == 20) 996 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 997 else 998 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a; 999 break; 1000 default: 1001 break; 1002 } 1003 } 1004 break; 1005 1006 case arg_idxr: 1007 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 1008 { 1009 if (symbol_with_at_got) 1010 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1011 else if (symbol_with_at_gotc) 1012 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1013 else 1014 cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; 1015 } 1016 break; 1017 1018 case arg_idxrp: 1019 if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)) 1020 { 1021 if (symbol_with_at_got) 1022 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1023 else if (symbol_with_at_gotc) 1024 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1025 else { 1026 switch (instruction->size) 1027 { 1028 case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break; 1029 case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break; 1030 case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break; 1031 default: break; 1032 } 1033 } 1034 } 1035 break; 1036 1037 case arg_c: 1038 if (IS_INSN_MNEMONIC ("bal")) 1039 cr16_ins->rtype = BFD_RELOC_CR16_DISP24; 1040 else if (IS_INSN_TYPE (BRANCH_INS)) 1041 { 1042 if (symbol_with_l) 1043 cr16_ins->rtype = BFD_RELOC_CR16_DISP24; 1044 else if (symbol_with_m) 1045 cr16_ins->rtype = BFD_RELOC_CR16_DISP16; 1046 else 1047 cr16_ins->rtype = BFD_RELOC_CR16_DISP8; 1048 } 1049 else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS) 1050 || IS_INSN_TYPE (CSTBIT_INS)) 1051 { 1052 if (symbol_with_s) 1053 as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str); 1054 if (symbol_with_at_got) 1055 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1056 else if (symbol_with_at_gotc) 1057 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1058 else if (symbol_with_m) 1059 cr16_ins->rtype = BFD_RELOC_CR16_ABS20; 1060 else /* Default to (symbol_with_l) */ 1061 cr16_ins->rtype = BFD_RELOC_CR16_ABS24; 1062 } 1063 else if (IS_INSN_TYPE (BRANCH_NEQ_INS)) 1064 cr16_ins->rtype = BFD_RELOC_CR16_DISP4; 1065 break; 1066 1067 case arg_ic: 1068 if (IS_INSN_TYPE (ARITH_INS)) 1069 { 1070 if (symbol_with_at_got) 1071 cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20; 1072 else if (symbol_with_at_gotc) 1073 cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20; 1074 else if (symbol_with_s) 1075 cr16_ins->rtype = BFD_RELOC_CR16_IMM4; 1076 else if (symbol_with_m) 1077 cr16_ins->rtype = BFD_RELOC_CR16_IMM20; 1078 else if (symbol_with_at) 1079 cr16_ins->rtype = BFD_RELOC_CR16_IMM32a; 1080 else /* Default to (symbol_with_l) */ 1081 cr16_ins->rtype = BFD_RELOC_CR16_IMM32; 1082 } 1083 else if (IS_INSN_TYPE (ARITH_BYTE_INS)) 1084 { 1085 cr16_ins->rtype = BFD_RELOC_CR16_IMM16; 1086 } 1087 break; 1088 default: 1089 break; 1090 } 1091 break; 1092 1093 default: 1094 cur_arg->X_op = cr16_ins->exp.X_op; 1095 break; 1096 } 1097 1098 input_line_pointer = saved_input_line_pointer; 1099 return; 1100 } 1101 1102 /* Retrieve the opcode image of a given register. 1103 If the register is illegal for the current instruction, 1104 issue an error. */ 1105 1106 static int 1107 getreg_image (reg r) 1108 { 1109 const reg_entry *rreg; 1110 char *reg_name; 1111 int is_procreg = 0; /* Nonzero means argument should be processor reg. */ 1112 1113 /* Check whether the register is in registers table. */ 1114 if (r < MAX_REG) 1115 rreg = cr16_regtab + r; 1116 else /* Register not found. */ 1117 { 1118 as_bad (_("Unknown register: `%d'"), r); 1119 return 0; 1120 } 1121 1122 reg_name = rreg->name; 1123 1124 /* Issue a error message when register is illegal. */ 1125 #define IMAGE_ERR \ 1126 as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \ 1127 reg_name, ins_parse); 1128 1129 switch (rreg->type) 1130 { 1131 case CR16_R_REGTYPE: 1132 if (! is_procreg) 1133 return rreg->image; 1134 else 1135 IMAGE_ERR; 1136 break; 1137 1138 case CR16_P_REGTYPE: 1139 return rreg->image; 1140 break; 1141 1142 default: 1143 IMAGE_ERR; 1144 break; 1145 } 1146 1147 return 0; 1148 } 1149 1150 /* Parsing different types of operands 1151 -> constants Immediate/Absolute/Relative numbers 1152 -> Labels Relocatable symbols 1153 -> (reg pair base) Register pair base 1154 -> (rbase) Register base 1155 -> disp(rbase) Register relative 1156 -> [rinx]disp(reg pair) Register index with reg pair mode 1157 -> disp(rbase,ridx,scl) Register index mode. */ 1158 1159 static void 1160 set_operand (char *operand, ins * cr16_ins) 1161 { 1162 char *operandS; /* Pointer to start of sub-operand. */ 1163 char *operandE; /* Pointer to end of sub-operand. */ 1164 1165 argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */ 1166 1167 /* Initialize pointers. */ 1168 operandS = operandE = operand; 1169 1170 switch (cur_arg->type) 1171 { 1172 case arg_ic: /* Case $0x18. */ 1173 operandS++; 1174 /* Fall through. */ 1175 case arg_c: /* Case 0x18. */ 1176 /* Set constant. */ 1177 process_label_constant (operandS, cr16_ins); 1178 1179 if (cur_arg->type != arg_ic) 1180 cur_arg->type = arg_c; 1181 break; 1182 1183 case arg_icr: /* Case $0x18(r1). */ 1184 operandS++; 1185 case arg_cr: /* Case 0x18(r1). */ 1186 /* Set displacement constant. */ 1187 while (*operandE != '(') 1188 operandE++; 1189 *operandE = '\0'; 1190 process_label_constant (operandS, cr16_ins); 1191 operandS = operandE; 1192 /* Fall through. */ 1193 case arg_rbase: /* Case (r1) or (r1,r0). */ 1194 operandS++; 1195 /* Set register base. */ 1196 while (*operandE != ')') 1197 operandE++; 1198 *operandE = '\0'; 1199 if ((cur_arg->r = get_register (operandS)) == nullregister) 1200 as_bad (_("Illegal register `%s' in Instruction `%s'"), 1201 operandS, ins_parse); 1202 1203 /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */ 1204 if ((cur_arg->type != arg_rbase) 1205 && ((getreg_image (cur_arg->r) == 12) 1206 || (getreg_image (cur_arg->r) == 13) 1207 || (getreg_image (cur_arg->r) == 14) 1208 || (getreg_image (cur_arg->r) == 15))) 1209 { 1210 cur_arg->type = arg_crp; 1211 cur_arg->rp = cur_arg->r; 1212 } 1213 break; 1214 1215 case arg_crp: /* Case 0x18(r1,r0). */ 1216 /* Set displacement constant. */ 1217 while (*operandE != '(') 1218 operandE++; 1219 *operandE = '\0'; 1220 process_label_constant (operandS, cr16_ins); 1221 operandS = operandE; 1222 operandS++; 1223 /* Set register pair base. */ 1224 while (*operandE != ')') 1225 operandE++; 1226 *operandE = '\0'; 1227 if ((cur_arg->rp = get_register_pair (operandS)) == nullregister) 1228 as_bad (_("Illegal register pair `%s' in Instruction `%s'"), 1229 operandS, ins_parse); 1230 break; 1231 1232 case arg_idxr: 1233 /* Set register pair base. */ 1234 if ((strchr (operandS,'(') != NULL)) 1235 { 1236 while ((*operandE != '(') && (! ISSPACE (*operandE))) 1237 operandE++; 1238 if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister) 1239 as_bad (_("Illegal register pair `%s' in Instruction `%s'"), 1240 operandS, ins_parse); 1241 *operandE++ = '\0'; 1242 cur_arg->type = arg_idxrp; 1243 } 1244 else 1245 cur_arg->rp = -1; 1246 1247 operandE = operandS; 1248 /* Set displacement constant. */ 1249 while (*operandE != ']') 1250 operandE++; 1251 process_label_constant (++operandE, cr16_ins); 1252 *operandE++ = '\0'; 1253 operandE = operandS; 1254 1255 /* Set index register . */ 1256 operandS = strchr (operandE,'['); 1257 if (operandS != NULL) 1258 { /* Eliminate '[', detach from rest of operand. */ 1259 *operandS++ = '\0'; 1260 1261 operandE = strchr (operandS, ']'); 1262 1263 if (operandE == NULL) 1264 as_bad (_("unmatched '['")); 1265 else 1266 { /* Eliminate ']' and make sure it was the last thing 1267 in the string. */ 1268 *operandE = '\0'; 1269 if (*(operandE + 1) != '\0') 1270 as_bad (_("garbage after index spec ignored")); 1271 } 1272 } 1273 1274 if ((cur_arg->i_r = get_index_register (operandS)) == nullregister) 1275 as_bad (_("Illegal register `%s' in Instruction `%s'"), 1276 operandS, ins_parse); 1277 *operandE = '\0'; 1278 *operandS = '\0'; 1279 break; 1280 1281 default: 1282 break; 1283 } 1284 } 1285 1286 /* Parse a single operand. 1287 operand - Current operand to parse. 1288 cr16_ins - Current assembled instruction. */ 1289 1290 static void 1291 parse_operand (char *operand, ins * cr16_ins) 1292 { 1293 int ret_val; 1294 argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */ 1295 1296 /* Initialize the type to NULL before parsing. */ 1297 cur_arg->type = nullargs; 1298 1299 /* Check whether this is a condition code . */ 1300 if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1)) 1301 { 1302 cur_arg->type = arg_cc; 1303 cur_arg->cc = ret_val; 1304 cur_arg->X_op = O_register; 1305 return; 1306 } 1307 1308 /* Check whether this is a general processor register. */ 1309 if ((ret_val = get_register (operand)) != nullregister) 1310 { 1311 cur_arg->type = arg_r; 1312 cur_arg->r = ret_val; 1313 cur_arg->X_op = 0; 1314 return; 1315 } 1316 1317 /* Check whether this is a general processor register pair. */ 1318 if ((operand[0] == '(') 1319 && ((ret_val = get_register_pair (operand)) != nullregister)) 1320 { 1321 cur_arg->type = arg_rp; 1322 cur_arg->rp = ret_val; 1323 cur_arg->X_op = O_register; 1324 return; 1325 } 1326 1327 /* Check whether the operand is a processor register. 1328 For "lprd" and "sprd" instruction, only 32 bit 1329 processor registers used. */ 1330 if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd"))) 1331 && ((ret_val = get_pregister (operand)) != nullpregister)) 1332 { 1333 cur_arg->type = arg_pr; 1334 cur_arg->pr = ret_val; 1335 cur_arg->X_op = O_register; 1336 return; 1337 } 1338 1339 /* Check whether this is a processor register - 32 bit. */ 1340 if ((ret_val = get_pregisterp (operand)) != nullpregister) 1341 { 1342 cur_arg->type = arg_prp; 1343 cur_arg->prp = ret_val; 1344 cur_arg->X_op = O_register; 1345 return; 1346 } 1347 1348 /* Deal with special characters. */ 1349 switch (operand[0]) 1350 { 1351 case '$': 1352 if (strchr (operand, '(') != NULL) 1353 cur_arg->type = arg_icr; 1354 else 1355 cur_arg->type = arg_ic; 1356 goto set_params; 1357 break; 1358 1359 case '(': 1360 cur_arg->type = arg_rbase; 1361 goto set_params; 1362 break; 1363 1364 case '[': 1365 cur_arg->type = arg_idxr; 1366 goto set_params; 1367 break; 1368 1369 default: 1370 break; 1371 } 1372 1373 if (strchr (operand, '(') != NULL) 1374 { 1375 if (strchr (operand, ',') != NULL 1376 && (strchr (operand, ',') > strchr (operand, '('))) 1377 cur_arg->type = arg_crp; 1378 else 1379 cur_arg->type = arg_cr; 1380 } 1381 else 1382 cur_arg->type = arg_c; 1383 1384 /* Parse an operand according to its type. */ 1385 set_params: 1386 cur_arg->constant = 0; 1387 set_operand (operand, cr16_ins); 1388 } 1389 1390 /* Parse the various operands. Each operand is then analyzed to fillup 1391 the fields in the cr16_ins data structure. */ 1392 1393 static void 1394 parse_operands (ins * cr16_ins, char *operands) 1395 { 1396 char *operandS; /* Operands string. */ 1397 char *operandH, *operandT; /* Single operand head/tail pointers. */ 1398 int allocated = 0; /* Indicates a new operands string was allocated.*/ 1399 char *operand[MAX_OPERANDS];/* Separating the operands. */ 1400 int op_num = 0; /* Current operand number we are parsing. */ 1401 int bracket_flag = 0; /* Indicates a bracket '(' was found. */ 1402 int sq_bracket_flag = 0; /* Indicates a square bracket '[' was found. */ 1403 1404 /* Preprocess the list of registers, if necessary. */ 1405 operandS = operandH = operandT = operands; 1406 1407 while (*operandT != '\0') 1408 { 1409 if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1) 1410 { 1411 *operandT++ = '\0'; 1412 operand[op_num++] = strdup (operandH); 1413 operandH = operandT; 1414 continue; 1415 } 1416 1417 if (*operandT == ' ') 1418 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse); 1419 1420 if (*operandT == '(') 1421 bracket_flag = 1; 1422 else if (*operandT == '[') 1423 sq_bracket_flag = 1; 1424 1425 if (*operandT == ')') 1426 { 1427 if (bracket_flag) 1428 bracket_flag = 0; 1429 else 1430 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1431 } 1432 else if (*operandT == ']') 1433 { 1434 if (sq_bracket_flag) 1435 sq_bracket_flag = 0; 1436 else 1437 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1438 } 1439 1440 if (bracket_flag == 1 && *operandT == ')') 1441 bracket_flag = 0; 1442 else if (sq_bracket_flag == 1 && *operandT == ']') 1443 sq_bracket_flag = 0; 1444 1445 operandT++; 1446 } 1447 1448 /* Adding the last operand. */ 1449 operand[op_num++] = strdup (operandH); 1450 cr16_ins->nargs = op_num; 1451 1452 /* Verifying correct syntax of operands (all brackets should be closed). */ 1453 if (bracket_flag || sq_bracket_flag) 1454 as_fatal (_("Missing matching brackets : `%s'"), ins_parse); 1455 1456 /* Now we parse each operand separately. */ 1457 for (op_num = 0; op_num < cr16_ins->nargs; op_num++) 1458 { 1459 cur_arg_num = op_num; 1460 parse_operand (operand[op_num], cr16_ins); 1461 free (operand[op_num]); 1462 } 1463 1464 if (allocated) 1465 free (operandS); 1466 } 1467 1468 /* Get the trap index in dispatch table, given its name. 1469 This routine is used by assembling the 'excp' instruction. */ 1470 1471 static int 1472 gettrap (char *s) 1473 { 1474 const trap_entry *trap; 1475 1476 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++) 1477 if (strcasecmp (trap->name, s) == 0) 1478 return trap->entry; 1479 1480 /* To make compatible with CR16 4.1 tools, the below 3-lines of 1481 * code added. Refer: Development Tracker item #123 */ 1482 for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++) 1483 if (trap->entry == (unsigned int) atoi (s)) 1484 return trap->entry; 1485 1486 as_bad (_("Unknown exception: `%s'"), s); 1487 return 0; 1488 } 1489 1490 /* Top level module where instruction parsing starts. 1491 cr16_ins - data structure holds some information. 1492 operands - holds the operands part of the whole instruction. */ 1493 1494 static void 1495 parse_insn (ins *insn, char *operands) 1496 { 1497 int i; 1498 1499 /* Handle instructions with no operands. */ 1500 for (i = 0; cr16_no_op_insn[i] != NULL; i++) 1501 { 1502 if (streq (cr16_no_op_insn[i], instruction->mnemonic)) 1503 { 1504 insn->nargs = 0; 1505 return; 1506 } 1507 } 1508 1509 /* Handle 'excp' instructions. */ 1510 if (IS_INSN_MNEMONIC ("excp")) 1511 { 1512 insn->nargs = 1; 1513 insn->arg[0].type = arg_ic; 1514 insn->arg[0].constant = gettrap (operands); 1515 insn->arg[0].X_op = O_constant; 1516 return; 1517 } 1518 1519 if (operands != NULL) 1520 parse_operands (insn, operands); 1521 } 1522 1523 /* bCC instruction requires special handling. */ 1524 static char * 1525 get_b_cc (char * op) 1526 { 1527 unsigned int i; 1528 char op1[5]; 1529 1530 for (i = 1; i < strlen (op); i++) 1531 op1[i-1] = op[i]; 1532 1533 op1[i-1] = '\0'; 1534 1535 for (i = 0; i < cr16_num_cc ; i++) 1536 if (streq (op1, cr16_b_cond_tab[i])) 1537 return (char *) cr16_b_cond_tab[i]; 1538 1539 return NULL; 1540 } 1541 1542 /* bCC instruction requires special handling. */ 1543 static int 1544 is_bcc_insn (char * op) 1545 { 1546 if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b") 1547 || streq (op, "beq0w") || streq (op, "bnq0w"))) 1548 if ((op[0] == 'b') && (get_b_cc (op) != NULL)) 1549 return 1; 1550 return 0; 1551 } 1552 1553 /* Cinv instruction requires special handling. */ 1554 1555 static void 1556 check_cinv_options (char * operand) 1557 { 1558 char *p = operand; 1559 1560 while (*++p != ']') 1561 { 1562 switch (*p) 1563 { 1564 case ',': 1565 case ' ': 1566 case 'i': 1567 case 'u': 1568 case 'd': 1569 break; 1570 default: 1571 as_bad (_("Illegal `cinv' parameter: `%c'"), *p); 1572 } 1573 } 1574 } 1575 1576 /* Retrieve the opcode image of a given register pair. 1577 If the register is illegal for the current instruction, 1578 issue an error. */ 1579 1580 static int 1581 getregp_image (reg r) 1582 { 1583 const reg_entry *rreg; 1584 char *reg_name; 1585 1586 /* Check whether the register is in registers table. */ 1587 if (r < MAX_REG) 1588 rreg = cr16_regptab + r; 1589 /* Register not found. */ 1590 else 1591 { 1592 as_bad (_("Unknown register pair: `%d'"), r); 1593 return 0; 1594 } 1595 1596 reg_name = rreg->name; 1597 1598 /* Issue a error message when register pair is illegal. */ 1599 #define RPAIR_IMAGE_ERR \ 1600 as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \ 1601 reg_name, ins_parse); \ 1602 break; 1603 1604 switch (rreg->type) 1605 { 1606 case CR16_RP_REGTYPE: 1607 return rreg->image; 1608 default: 1609 RPAIR_IMAGE_ERR; 1610 } 1611 1612 return 0; 1613 } 1614 1615 /* Retrieve the opcode image of a given index register pair. 1616 If the register is illegal for the current instruction, 1617 issue an error. */ 1618 1619 static int 1620 getidxregp_image (reg r) 1621 { 1622 const reg_entry *rreg; 1623 char *reg_name; 1624 1625 /* Check whether the register is in registers table. */ 1626 if (r < MAX_REG) 1627 rreg = cr16_regptab + r; 1628 /* Register not found. */ 1629 else 1630 { 1631 as_bad (_("Unknown register pair: `%d'"), r); 1632 return 0; 1633 } 1634 1635 reg_name = rreg->name; 1636 1637 /* Issue a error message when register pair is illegal. */ 1638 #define IDX_RPAIR_IMAGE_ERR \ 1639 as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \ 1640 reg_name, ins_parse); \ 1641 1642 if (rreg->type == CR16_RP_REGTYPE) 1643 { 1644 switch (rreg->image) 1645 { 1646 case 0: return 0; break; 1647 case 2: return 1; break; 1648 case 4: return 2; break; 1649 case 6: return 3; break; 1650 case 8: return 4; break; 1651 case 10: return 5; break; 1652 case 3: return 6; break; 1653 case 5: return 7; break; 1654 default: 1655 break; 1656 } 1657 } 1658 1659 IDX_RPAIR_IMAGE_ERR; 1660 return 0; 1661 } 1662 1663 /* Retrieve the opcode image of a given processor register. 1664 If the register is illegal for the current instruction, 1665 issue an error. */ 1666 static int 1667 getprocreg_image (int r) 1668 { 1669 const reg_entry *rreg; 1670 char *reg_name; 1671 1672 /* Check whether the register is in registers table. */ 1673 if (r >= MAX_REG && r < MAX_PREG) 1674 rreg = &cr16_pregtab[r - MAX_REG]; 1675 /* Register not found. */ 1676 else 1677 { 1678 as_bad (_("Unknown processor register : `%d'"), r); 1679 return 0; 1680 } 1681 1682 reg_name = rreg->name; 1683 1684 /* Issue a error message when register pair is illegal. */ 1685 #define PROCREG_IMAGE_ERR \ 1686 as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \ 1687 reg_name, ins_parse); \ 1688 break; 1689 1690 switch (rreg->type) 1691 { 1692 case CR16_P_REGTYPE: 1693 return rreg->image; 1694 default: 1695 PROCREG_IMAGE_ERR; 1696 } 1697 1698 return 0; 1699 } 1700 1701 /* Retrieve the opcode image of a given processor register. 1702 If the register is illegal for the current instruction, 1703 issue an error. */ 1704 static int 1705 getprocregp_image (int r) 1706 { 1707 const reg_entry *rreg; 1708 char *reg_name; 1709 int pregptab_disp = 0; 1710 1711 /* Check whether the register is in registers table. */ 1712 if (r >= MAX_REG && r < MAX_PREG) 1713 { 1714 r = r - MAX_REG; 1715 switch (r) 1716 { 1717 case 4: pregptab_disp = 1; break; 1718 case 6: pregptab_disp = 2; break; 1719 case 8: 1720 case 9: 1721 case 10: 1722 pregptab_disp = 3; break; 1723 case 12: 1724 pregptab_disp = 4; break; 1725 case 14: 1726 pregptab_disp = 5; break; 1727 default: break; 1728 } 1729 rreg = &cr16_pregptab[r - pregptab_disp]; 1730 } 1731 /* Register not found. */ 1732 else 1733 { 1734 as_bad (_("Unknown processor register (32 bit) : `%d'"), r); 1735 return 0; 1736 } 1737 1738 reg_name = rreg->name; 1739 1740 /* Issue a error message when register pair is illegal. */ 1741 #define PROCREGP_IMAGE_ERR \ 1742 as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"),\ 1743 reg_name, ins_parse); \ 1744 break; 1745 1746 switch (rreg->type) 1747 { 1748 case CR16_P_REGTYPE: 1749 return rreg->image; 1750 default: 1751 PROCREGP_IMAGE_ERR; 1752 } 1753 1754 return 0; 1755 } 1756 1757 /* Routine used to represent integer X using NBITS bits. */ 1758 1759 static long 1760 getconstant (long x, int nbits) 1761 { 1762 /* The following expression avoids overflow if 1763 'nbits' is the number of bits in 'bfd_vma'. */ 1764 return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1)); 1765 } 1766 1767 /* Print a constant value to 'output_opcode': 1768 ARG holds the operand's type and value. 1769 SHIFT represents the location of the operand to be print into. 1770 NBITS determines the size (in bits) of the constant. */ 1771 1772 static void 1773 print_constant (int nbits, int shift, argument *arg) 1774 { 1775 unsigned long mask = 0; 1776 1777 long constant = getconstant (arg->constant, nbits); 1778 1779 switch (nbits) 1780 { 1781 case 32: 1782 case 28: 1783 /* mask the upper part of the constant, that is, the bits 1784 going to the lowest byte of output_opcode[0]. 1785 The upper part of output_opcode[1] is always filled, 1786 therefore it is always masked with 0xFFFF. */ 1787 mask = (1 << (nbits - 16)) - 1; 1788 /* Divide the constant between two consecutive words : 1789 0 1 2 3 1790 +---------+---------+---------+---------+ 1791 | | X X X X | x X x X | | 1792 +---------+---------+---------+---------+ 1793 output_opcode[0] output_opcode[1] */ 1794 1795 CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0); 1796 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1797 break; 1798 1799 case 21: 1800 if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS))) 1801 nbits = 20; 1802 /* Fall through. */ 1803 case 24: 1804 case 22: 1805 case 20: 1806 /* mask the upper part of the constant, that is, the bits 1807 going to the lowest byte of output_opcode[0]. 1808 The upper part of output_opcode[1] is always filled, 1809 therefore it is always masked with 0xFFFF. */ 1810 mask = (1 << (nbits - 16)) - 1; 1811 /* Divide the constant between two consecutive words : 1812 0 1 2 3 1813 +---------+---------+---------+---------+ 1814 | | X X X X | - X - X | | 1815 +---------+---------+---------+---------+ 1816 output_opcode[0] output_opcode[1] */ 1817 1818 if ((instruction->size > 2) && (shift == WORD_SHIFT)) 1819 { 1820 if (arg->type == arg_idxrp) 1821 { 1822 CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0); 1823 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1824 } 1825 else 1826 { 1827 CR16_PRINT (0, (((((constant >> WORD_SHIFT) & mask) << 8) & 0x0f00) | ((((constant >> WORD_SHIFT) & mask) >> 4) & 0xf)),0); 1828 CR16_PRINT (1, (constant & 0xFFFF), WORD_SHIFT); 1829 } 1830 } 1831 else 1832 CR16_PRINT (0, constant, shift); 1833 break; 1834 1835 case 14: 1836 if (arg->type == arg_idxrp) 1837 { 1838 if (instruction->size == 2) 1839 { 1840 CR16_PRINT (0, ((constant) & 0xf), shift); /* 0-3 bits. */ 1841 CR16_PRINT (0, ((constant >> 4) & 0x3), (shift + 20)); /* 4-5 bits. */ 1842 CR16_PRINT (0, ((constant >> 6) & 0x3), (shift + 14)); /* 6-7 bits. */ 1843 CR16_PRINT (0, ((constant >> 8) & 0x3f), (shift + 8)); /* 8-13 bits. */ 1844 } 1845 else 1846 CR16_PRINT (0, constant, shift); 1847 } 1848 break; 1849 1850 case 16: 1851 case 12: 1852 /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is 1853 always filling the upper part of output_opcode[1]. If we mistakenly 1854 write it to output_opcode[0], the constant prefix (that is, 'match') 1855 will be overridden. 1856 0 1 2 3 1857 +---------+---------+---------+---------+ 1858 | 'match' | | X X X X | | 1859 +---------+---------+---------+---------+ 1860 output_opcode[0] output_opcode[1] */ 1861 1862 if ((instruction->size > 2) && (shift == WORD_SHIFT)) 1863 CR16_PRINT (1, constant, WORD_SHIFT); 1864 else 1865 CR16_PRINT (0, constant, shift); 1866 break; 1867 1868 case 8: 1869 CR16_PRINT (0, ((constant / 2) & 0xf), shift); 1870 CR16_PRINT (0, ((constant / 2) >> 4), (shift + 8)); 1871 break; 1872 1873 default: 1874 CR16_PRINT (0, constant, shift); 1875 break; 1876 } 1877 } 1878 1879 /* Print an operand to 'output_opcode', which later on will be 1880 printed to the object file: 1881 ARG holds the operand's type, size and value. 1882 SHIFT represents the printing location of operand. 1883 NBITS determines the size (in bits) of a constant operand. */ 1884 1885 static void 1886 print_operand (int nbits, int shift, argument *arg) 1887 { 1888 switch (arg->type) 1889 { 1890 case arg_cc: 1891 CR16_PRINT (0, arg->cc, shift); 1892 break; 1893 1894 case arg_r: 1895 CR16_PRINT (0, getreg_image (arg->r), shift); 1896 break; 1897 1898 case arg_rp: 1899 CR16_PRINT (0, getregp_image (arg->rp), shift); 1900 break; 1901 1902 case arg_pr: 1903 CR16_PRINT (0, getprocreg_image (arg->pr), shift); 1904 break; 1905 1906 case arg_prp: 1907 CR16_PRINT (0, getprocregp_image (arg->prp), shift); 1908 break; 1909 1910 case arg_idxrp: 1911 /* 16 12 8 6 0 1912 +-----------------------------+ 1913 | r_index | disp | rp_base | 1914 +-----------------------------+ */ 1915 1916 if (instruction->size == 3) 1917 { 1918 CR16_PRINT (0, getidxregp_image (arg->rp), 0); 1919 if (getreg_image (arg->i_r) == 12) 1920 CR16_PRINT (0, 0, 3); 1921 else 1922 CR16_PRINT (0, 1, 3); 1923 } 1924 else 1925 { 1926 CR16_PRINT (0, getidxregp_image (arg->rp), 16); 1927 if (getreg_image (arg->i_r) == 12) 1928 CR16_PRINT (0, 0, 19); 1929 else 1930 CR16_PRINT (0, 1, 19); 1931 } 1932 print_constant (nbits, shift, arg); 1933 break; 1934 1935 case arg_idxr: 1936 if (getreg_image (arg->i_r) == 12) 1937 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb") 1938 || IS_INSN_MNEMONIC ("tbitb")) 1939 CR16_PRINT (0, 0, 23); 1940 else CR16_PRINT (0, 0, 24); 1941 else 1942 if (IS_INSN_MNEMONIC ("cbitb") || IS_INSN_MNEMONIC ("sbitb") 1943 || IS_INSN_MNEMONIC ("tbitb")) 1944 CR16_PRINT (0, 1, 23); 1945 else CR16_PRINT (0, 1, 24); 1946 1947 print_constant (nbits, shift, arg); 1948 break; 1949 1950 case arg_ic: 1951 case arg_c: 1952 print_constant (nbits, shift, arg); 1953 break; 1954 1955 case arg_rbase: 1956 CR16_PRINT (0, getreg_image (arg->r), shift); 1957 break; 1958 1959 case arg_cr: 1960 print_constant (nbits, shift , arg); 1961 /* Add the register argument to the output_opcode. */ 1962 CR16_PRINT (0, getreg_image (arg->r), (shift+16)); 1963 break; 1964 1965 case arg_crp: 1966 print_constant (nbits, shift , arg); 1967 if (instruction->size > 1) 1968 CR16_PRINT (0, getregp_image (arg->rp), (shift + 16)); 1969 else if (IS_INSN_TYPE (LD_STOR_INS) || (IS_INSN_TYPE (CSTBIT_INS))) 1970 { 1971 if (instruction->size == 2) 1972 CR16_PRINT (0, getregp_image (arg->rp), (shift - 8)); 1973 else if (instruction->size == 1) 1974 CR16_PRINT (0, getregp_image (arg->rp), 16); 1975 } 1976 else 1977 CR16_PRINT (0, getregp_image (arg->rp), shift); 1978 break; 1979 1980 default: 1981 break; 1982 } 1983 } 1984 1985 /* Retrieve the number of operands for the current assembled instruction. */ 1986 1987 static int 1988 get_number_of_operands (void) 1989 { 1990 int i; 1991 1992 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) 1993 ; 1994 return i; 1995 } 1996 1997 /* Verify that the number NUM can be represented in BITS bits (that is, 1998 within its permitted range), based on the instruction's FLAGS. 1999 If UPDATE is nonzero, update the value of NUM if necessary. 2000 Return OP_LEGAL upon success, actual error type upon failure. */ 2001 2002 static op_err 2003 check_range (long *num, int bits, int unsigned flags, int update) 2004 { 2005 long min, max; 2006 op_err retval = OP_LEGAL; 2007 long value = *num; 2008 2009 if (bits == 0 && value > 0) return OP_OUT_OF_RANGE; 2010 2011 /* For hosts with longs bigger than 32-bits make sure that the top 2012 bits of a 32-bit negative value read in by the parser are set, 2013 so that the correct comparisons are made. */ 2014 if (value & 0x80000000) 2015 value |= (-1UL << 31); 2016 2017 2018 /* Verify operand value is even. */ 2019 if (flags & OP_EVEN) 2020 { 2021 if (value % 2) 2022 return OP_NOT_EVEN; 2023 } 2024 2025 if (flags & OP_DEC) 2026 { 2027 value -= 1; 2028 if (update) 2029 *num = value; 2030 } 2031 2032 if (flags & OP_SHIFT) 2033 { 2034 value >>= 1; 2035 if (update) 2036 *num = value; 2037 } 2038 else if (flags & OP_SHIFT_DEC) 2039 { 2040 value = (value >> 1) - 1; 2041 if (update) 2042 *num = value; 2043 } 2044 2045 if (flags & OP_ABS20) 2046 { 2047 if (value > 0xEFFFF) 2048 return OP_OUT_OF_RANGE; 2049 } 2050 2051 if (flags & OP_ESC) 2052 { 2053 if (value == 0xB || value == 0x9) 2054 return OP_OUT_OF_RANGE; 2055 else if (value == -1) 2056 { 2057 if (update) 2058 *num = 9; 2059 return retval; 2060 } 2061 } 2062 2063 if (flags & OP_ESC1) 2064 { 2065 if (value > 13) 2066 return OP_OUT_OF_RANGE; 2067 } 2068 2069 if (flags & OP_SIGNED) 2070 { 2071 max = (1 << (bits - 1)) - 1; 2072 min = - (1 << (bits - 1)); 2073 if ((value > max) || (value < min)) 2074 retval = OP_OUT_OF_RANGE; 2075 } 2076 else if (flags & OP_UNSIGNED) 2077 { 2078 max = ((((1 << (bits - 1)) - 1) << 1) | 1); 2079 min = 0; 2080 if (((unsigned long) value > (unsigned long) max) 2081 || ((unsigned long) value < (unsigned long) min)) 2082 retval = OP_OUT_OF_RANGE; 2083 } 2084 else if (flags & OP_NEG) 2085 { 2086 max = - 1; 2087 min = - ((1 << (bits - 1)) - 1); 2088 if ((value > max) || (value < min)) 2089 retval = OP_OUT_OF_RANGE; 2090 } 2091 return retval; 2092 } 2093 2094 /* Bunch of error checking. 2095 The checks are made after a matching instruction was found. */ 2096 2097 static void 2098 warn_if_needed (ins *insn) 2099 { 2100 /* If the post-increment address mode is used and the load/store 2101 source register is the same as rbase, the result of the 2102 instruction is undefined. */ 2103 if (IS_INSN_TYPE (LD_STOR_INS_INC)) 2104 { 2105 /* Enough to verify that one of the arguments is a simple reg. */ 2106 if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r)) 2107 if (insn->arg[0].r == insn->arg[1].r) 2108 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), insn->arg[0].r); 2109 } 2110 2111 if (IS_INSN_MNEMONIC ("pop") 2112 || IS_INSN_MNEMONIC ("push") 2113 || IS_INSN_MNEMONIC ("popret")) 2114 { 2115 unsigned int count = insn->arg[0].constant, reg_val; 2116 2117 /* Check if count operand caused to save/retrieve the RA twice 2118 to generate warning message. */ 2119 if (insn->nargs > 2) 2120 { 2121 reg_val = getreg_image (insn->arg[1].r); 2122 2123 if ( ((reg_val == 9) && (count > 7)) 2124 || ((reg_val == 10) && (count > 6)) 2125 || ((reg_val == 11) && (count > 5)) 2126 || ((reg_val == 12) && (count > 4)) 2127 || ((reg_val == 13) && (count > 2)) 2128 || ((reg_val == 14) && (count > 0))) 2129 as_warn (_("RA register is saved twice.")); 2130 2131 /* Check if the third operand is "RA" or "ra" */ 2132 if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA))) 2133 as_bad (_("`%s' Illegal use of registers."), ins_parse); 2134 } 2135 2136 if (insn->nargs > 1) 2137 { 2138 reg_val = getreg_image (insn->arg[1].r); 2139 2140 /* If register is a register pair ie r12/r13/r14 in operand1, then 2141 the count constant should be validated. */ 2142 if (((reg_val == 11) && (count > 7)) 2143 || ((reg_val == 12) && (count > 6)) 2144 || ((reg_val == 13) && (count > 4)) 2145 || ((reg_val == 14) && (count > 2)) 2146 || ((reg_val == 15) && (count > 0))) 2147 as_bad (_("`%s' Illegal count-register combination."), ins_parse); 2148 } 2149 else 2150 { 2151 /* Check if the operand is "RA" or "ra" */ 2152 if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA))) 2153 as_bad (_("`%s' Illegal use of register."), ins_parse); 2154 } 2155 } 2156 2157 /* Some instruction assume the stack pointer as rptr operand. 2158 Issue an error when the register to be loaded is also SP. */ 2159 if (instruction->flags & NO_SP) 2160 { 2161 if (getreg_image (insn->arg[1].r) == getreg_image (sp)) 2162 as_bad (_("`%s' has undefined result"), ins_parse); 2163 } 2164 2165 /* If the rptr register is specified as one of the registers to be loaded, 2166 the final contents of rptr are undefined. Thus, we issue an error. */ 2167 if (instruction->flags & NO_RPTR) 2168 { 2169 if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant) 2170 as_bad (_("Same src/dest register is used (`r%d'),result is undefined"), 2171 getreg_image (insn->arg[0].r)); 2172 } 2173 } 2174 2175 /* In some cases, we need to adjust the instruction pointer although a 2176 match was already found. Here, we gather all these cases. 2177 Returns 1 if instruction pointer was adjusted, otherwise 0. */ 2178 2179 static int 2180 adjust_if_needed (ins *insn ATTRIBUTE_UNUSED) 2181 { 2182 int ret_value = 0; 2183 2184 if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS))) 2185 { 2186 if ((instruction->operands[0].op_type == abs24) 2187 && ((insn->arg[0].constant) > 0xF00000)) 2188 { 2189 insn->arg[0].constant &= 0xFFFFF; 2190 instruction--; 2191 ret_value = 1; 2192 } 2193 } 2194 2195 return ret_value; 2196 } 2197 2198 /* Assemble a single instruction: 2199 INSN is already parsed (that is, all operand values and types are set). 2200 For instruction to be assembled, we need to find an appropriate template in 2201 the instruction table, meeting the following conditions: 2202 1: Has the same number of operands. 2203 2: Has the same operand types. 2204 3: Each operand size is sufficient to represent the instruction's values. 2205 Returns 1 upon success, 0 upon failure. */ 2206 2207 static int 2208 assemble_insn (const char *mnemonic, ins *insn) 2209 { 2210 /* Type of each operand in the current template. */ 2211 argtype cur_type[MAX_OPERANDS]; 2212 /* Size (in bits) of each operand in the current template. */ 2213 unsigned int cur_size[MAX_OPERANDS]; 2214 /* Flags of each operand in the current template. */ 2215 unsigned int cur_flags[MAX_OPERANDS]; 2216 /* Instruction type to match. */ 2217 unsigned int ins_type; 2218 /* Boolean flag to mark whether a match was found. */ 2219 int match = 0; 2220 int i; 2221 /* Nonzero if an instruction with same number of operands was found. */ 2222 int found_same_number_of_operands = 0; 2223 /* Nonzero if an instruction with same argument types was found. */ 2224 int found_same_argument_types = 0; 2225 /* Nonzero if a constant was found within the required range. */ 2226 int found_const_within_range = 0; 2227 /* Argument number of an operand with invalid type. */ 2228 int invalid_optype = -1; 2229 /* Argument number of an operand with invalid constant value. */ 2230 int invalid_const = -1; 2231 /* Operand error (used for issuing various constant error messages). */ 2232 op_err op_error, const_err = OP_LEGAL; 2233 2234 /* Retrieve data (based on FUNC) for each operand of a given instruction. */ 2235 #define GET_CURRENT_DATA(FUNC, ARRAY) \ 2236 for (i = 0; i < insn->nargs; i++) \ 2237 ARRAY[i] = FUNC (instruction->operands[i].op_type) 2238 2239 #define GET_CURRENT_TYPE GET_CURRENT_DATA (get_optype, cur_type) 2240 #define GET_CURRENT_SIZE GET_CURRENT_DATA (get_opbits, cur_size) 2241 #define GET_CURRENT_FLAGS GET_CURRENT_DATA (get_opflags, cur_flags) 2242 2243 /* Instruction has no operands -> only copy the constant opcode. */ 2244 if (insn->nargs == 0) 2245 { 2246 output_opcode[0] = BIN (instruction->match, instruction->match_bits); 2247 return 1; 2248 } 2249 2250 /* In some case, same mnemonic can appear with different instruction types. 2251 For example, 'storb' is supported with 3 different types : 2252 LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS. 2253 We assume that when reaching this point, the instruction type was 2254 pre-determined. We need to make sure that the type stays the same 2255 during a search for matching instruction. */ 2256 ins_type = CR16_INS_TYPE (instruction->flags); 2257 2258 while (/* Check that match is still not found. */ 2259 match != 1 2260 /* Check we didn't get to end of table. */ 2261 && instruction->mnemonic != NULL 2262 /* Check that the actual mnemonic is still available. */ 2263 && IS_INSN_MNEMONIC (mnemonic) 2264 /* Check that the instruction type wasn't changed. */ 2265 && IS_INSN_TYPE (ins_type)) 2266 { 2267 /* Check whether number of arguments is legal. */ 2268 if (get_number_of_operands () != insn->nargs) 2269 goto next_insn; 2270 found_same_number_of_operands = 1; 2271 2272 /* Initialize arrays with data of each operand in current template. */ 2273 GET_CURRENT_TYPE; 2274 GET_CURRENT_SIZE; 2275 GET_CURRENT_FLAGS; 2276 2277 /* Check for type compatibility. */ 2278 for (i = 0; i < insn->nargs; i++) 2279 { 2280 if (cur_type[i] != insn->arg[i].type) 2281 { 2282 if (invalid_optype == -1) 2283 invalid_optype = i + 1; 2284 goto next_insn; 2285 } 2286 } 2287 found_same_argument_types = 1; 2288 2289 for (i = 0; i < insn->nargs; i++) 2290 { 2291 /* If 'bal' instruction size is '2' and reg operand is not 'ra' 2292 then goto next instruction. */ 2293 if (IS_INSN_MNEMONIC ("bal") && (i == 0) 2294 && (instruction->size == 2) && (insn->arg[i].rp != 14)) 2295 goto next_insn; 2296 2297 /* If 'storb' instruction with 'sp' reg and 16-bit disp of 2298 * reg-pair, leads to undefined trap, so this should use 2299 * 20-bit disp of reg-pair. */ 2300 if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2) 2301 && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp)) 2302 goto next_insn; 2303 2304 /* Only check range - don't update the constant's value, since the 2305 current instruction may not be the last we try to match. 2306 The constant's value will be updated later, right before printing 2307 it to the object file. */ 2308 if ((insn->arg[i].X_op == O_constant) 2309 && (op_error = check_range (&insn->arg[i].constant, cur_size[i], 2310 cur_flags[i], 0))) 2311 { 2312 if (invalid_const == -1) 2313 { 2314 invalid_const = i + 1; 2315 const_err = op_error; 2316 } 2317 goto next_insn; 2318 } 2319 /* For symbols, we make sure the relocation size (which was already 2320 determined) is sufficient. */ 2321 else if ((insn->arg[i].X_op == O_symbol) 2322 && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize 2323 > cur_size[i])) 2324 goto next_insn; 2325 } 2326 found_const_within_range = 1; 2327 2328 /* If we got till here -> Full match is found. */ 2329 match = 1; 2330 break; 2331 2332 /* Try again with next instruction. */ 2333 next_insn: 2334 instruction++; 2335 } 2336 2337 if (!match) 2338 { 2339 /* We haven't found a match - instruction can't be assembled. */ 2340 if (!found_same_number_of_operands) 2341 as_bad (_("Incorrect number of operands")); 2342 else if (!found_same_argument_types) 2343 as_bad (_("Illegal type of operand (arg %d)"), invalid_optype); 2344 else if (!found_const_within_range) 2345 { 2346 switch (const_err) 2347 { 2348 case OP_OUT_OF_RANGE: 2349 as_bad (_("Operand out of range (arg %d)"), invalid_const); 2350 break; 2351 case OP_NOT_EVEN: 2352 as_bad (_("Operand has odd displacement (arg %d)"), invalid_const); 2353 break; 2354 default: 2355 as_bad (_("Illegal operand (arg %d)"), invalid_const); 2356 break; 2357 } 2358 } 2359 2360 return 0; 2361 } 2362 else 2363 /* Full match - print the encoding to output file. */ 2364 { 2365 /* Make further checking (such that couldn't be made earlier). 2366 Warn the user if necessary. */ 2367 warn_if_needed (insn); 2368 2369 /* Check whether we need to adjust the instruction pointer. */ 2370 if (adjust_if_needed (insn)) 2371 /* If instruction pointer was adjusted, we need to update 2372 the size of the current template operands. */ 2373 GET_CURRENT_SIZE; 2374 2375 for (i = 0; i < insn->nargs; i++) 2376 { 2377 int j = instruction->flags & REVERSE_MATCH ? 2378 i == 0 ? 1 : 2379 i == 1 ? 0 : i : 2380 i; 2381 2382 /* This time, update constant value before printing it. */ 2383 if ((insn->arg[j].X_op == O_constant) 2384 && (check_range (&insn->arg[j].constant, cur_size[j], 2385 cur_flags[j], 1) != OP_LEGAL)) 2386 as_fatal (_("Illegal operand (arg %d)"), j+1); 2387 } 2388 2389 /* First, copy the instruction's opcode. */ 2390 output_opcode[0] = BIN (instruction->match, instruction->match_bits); 2391 2392 for (i = 0; i < insn->nargs; i++) 2393 { 2394 /* For BAL (ra),disp17 instruction only. And also set the 2395 DISP24a relocation type. */ 2396 if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0) 2397 { 2398 insn->rtype = BFD_RELOC_CR16_DISP24a; 2399 continue; 2400 } 2401 cur_arg_num = i; 2402 print_operand (cur_size[i], instruction->operands[i].shift, 2403 &insn->arg[i]); 2404 } 2405 } 2406 2407 return 1; 2408 } 2409 2410 /* Print the instruction. 2411 Handle also cases where the instruction is relaxable/relocatable. */ 2412 2413 static void 2414 print_insn (ins *insn) 2415 { 2416 unsigned int i, j, insn_size; 2417 char *this_frag; 2418 unsigned short words[4]; 2419 int addr_mod; 2420 2421 /* Arrange the insn encodings in a WORD size array. */ 2422 for (i = 0, j = 0; i < 2; i++) 2423 { 2424 words[j++] = (output_opcode[i] >> 16) & 0xFFFF; 2425 words[j++] = output_opcode[i] & 0xFFFF; 2426 } 2427 2428 /* Handle relocation. */ 2429 if ((instruction->flags & RELAXABLE) && relocatable) 2430 { 2431 int relax_subtype; 2432 /* Write the maximal instruction size supported. */ 2433 insn_size = INSN_MAX_SIZE; 2434 2435 if (IS_INSN_TYPE (BRANCH_INS)) 2436 { 2437 switch (insn->rtype) 2438 { 2439 case BFD_RELOC_CR16_DISP24: 2440 relax_subtype = 2; 2441 break; 2442 case BFD_RELOC_CR16_DISP16: 2443 relax_subtype = 1; 2444 break; 2445 default: 2446 relax_subtype = 0; 2447 break; 2448 } 2449 } 2450 else 2451 abort (); 2452 2453 this_frag = frag_var (rs_machine_dependent, insn_size *2, 2454 4, relax_subtype, 2455 insn->exp.X_add_symbol, 2456 0, 2457 0); 2458 } 2459 else 2460 { 2461 insn_size = instruction->size; 2462 this_frag = frag_more (insn_size * 2); 2463 2464 if ((relocatable) && (insn->rtype != BFD_RELOC_NONE)) 2465 { 2466 reloc_howto_type *reloc_howto; 2467 int size; 2468 2469 reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype); 2470 2471 if (!reloc_howto) 2472 abort (); 2473 2474 size = bfd_get_reloc_size (reloc_howto); 2475 2476 if (size < 1 || size > 4) 2477 abort (); 2478 2479 fix_new_exp (frag_now, this_frag - frag_now->fr_literal, 2480 size, &insn->exp, reloc_howto->pc_relative, 2481 insn->rtype); 2482 } 2483 } 2484 2485 /* Verify a 2-byte code alignment. */ 2486 addr_mod = frag_now_fix () & 1; 2487 if (frag_now->has_code && frag_now->insn_addr != addr_mod) 2488 as_bad (_("instruction address is not a multiple of 2")); 2489 frag_now->insn_addr = addr_mod; 2490 frag_now->has_code = 1; 2491 2492 /* Write the instruction encoding to frag. */ 2493 for (i = 0; i < insn_size; i++) 2494 { 2495 md_number_to_chars (this_frag, (valueT) words[i], 2); 2496 this_frag += 2; 2497 } 2498 } 2499 2500 /* Actually assemble an instruction. */ 2501 2502 static void 2503 cr16_assemble (const char *op, char *param) 2504 { 2505 ins cr16_ins; 2506 2507 /* Find the instruction. */ 2508 instruction = (const inst *) hash_find (cr16_inst_hash, op); 2509 if (instruction == NULL) 2510 { 2511 as_bad (_("Unknown opcode: `%s'"), op); 2512 return; 2513 } 2514 2515 /* Tie dwarf2 debug info to the address at the start of the insn. */ 2516 dwarf2_emit_insn (0); 2517 2518 /* Parse the instruction's operands. */ 2519 parse_insn (&cr16_ins, param); 2520 2521 /* Assemble the instruction - return upon failure. */ 2522 if (assemble_insn (op, &cr16_ins) == 0) 2523 return; 2524 2525 /* Print the instruction. */ 2526 print_insn (&cr16_ins); 2527 } 2528 2529 /* This is the guts of the machine-dependent assembler. OP points to a 2530 machine dependent instruction. This function is supposed to emit 2531 the frags/bytes it assembles to. */ 2532 2533 void 2534 md_assemble (char *op) 2535 { 2536 ins cr16_ins; 2537 char *param, param1[32]; 2538 2539 /* Reset global variables for a new instruction. */ 2540 reset_vars (op); 2541 2542 /* Strip the mnemonic. */ 2543 for (param = op; *param != 0 && !ISSPACE (*param); param++) 2544 ; 2545 *param++ = '\0'; 2546 2547 /* bCC instructions and adjust the mnemonic by adding extra white spaces. */ 2548 if (is_bcc_insn (op)) 2549 { 2550 strcpy (param1, get_b_cc (op)); 2551 strcat (param1,","); 2552 strcat (param1, param); 2553 param = (char *) ¶m1; 2554 cr16_assemble ("b", param); 2555 return; 2556 } 2557 2558 /* Checking the cinv options and adjust the mnemonic by removing the 2559 extra white spaces. */ 2560 if (streq ("cinv", op)) 2561 { 2562 /* Validate the cinv options. */ 2563 check_cinv_options (param); 2564 strcat (op, param); 2565 } 2566 2567 /* MAPPING - SHIFT INSN, if imm4/imm16 positive values 2568 lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg 2569 as CR16 core doesn't support lsh[b/w] right shift operations. */ 2570 if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op)) 2571 && (param [0] == '$')) 2572 { 2573 strcpy (param1, param); 2574 /* Find the instruction. */ 2575 instruction = (const inst *) hash_find (cr16_inst_hash, op); 2576 parse_operands (&cr16_ins, param1); 2577 if (((&cr16_ins)->arg[0].type == arg_ic) 2578 && ((&cr16_ins)->arg[0].constant >= 0)) 2579 { 2580 if (streq ("lshb", op)) 2581 cr16_assemble ("ashub", param); 2582 else if (streq ("lshd", op)) 2583 cr16_assemble ("ashud", param); 2584 else 2585 cr16_assemble ("ashuw", param); 2586 return; 2587 } 2588 } 2589 2590 cr16_assemble (op, param); 2591 } 2592