1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * $FreeBSD$ 23 */ 24/* 25 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29#define _ASM 30#define _LOCORE 31#define LOCORE 32 33#include <sys/cpuvar_defs.h> 34#include <sys/dtrace.h> 35 36#include <machine/asm.h> 37#include <arm/armreg.h> 38 39/* 40void dtrace_membar_producer(void) 41*/ 42ENTRY(dtrace_membar_producer) 43 RET 44END(dtrace_membar_producer) 45 46/* 47void dtrace_membar_consumer(void) 48*/ 49ENTRY(dtrace_membar_consumer) 50 RET 51END(dtrace_membar_consumer) 52 53/* 54dtrace_icookie_t dtrace_interrupt_disable(void) 55*/ 56ENTRY(dtrace_interrupt_disable) 57 mrs r0, cpsr 58 mov r1, r0 59 orr r1, r1, #(I32_bit|F32_bit) 60 msr cpsr_c, r1 61 RET 62END(dtrace_interrupt_disable) 63 64/* 65void dtrace_interrupt_enable(dtrace_icookie_t cookie) 66*/ 67ENTRY(dtrace_interrupt_enable) 68 and r0, r0, #(I32_bit|F32_bit) 69 mrs r1, cpsr 70 bic r1, r1, #(I32_bit|F32_bit) 71 orr r1, r1, r0 72 msr cpsr_c, r1 73 RET 74END(dtrace_interrupt_enable) 75 76/* 77uint32_t dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new) 78XXX: just disable interrupts for now, add proper implementation for 79ARMv6/ARMv7 later 80*/ 81ENTRY_NP(dtrace_casptr) 82ENTRY(dtrace_cas32) 83 stmfd sp!, {r4, r5} 84 85 mrs r3, cpsr 86 mov r4, r3 87 orr r4, r4, #(I32_bit|F32_bit) 88 msr cpsr_c, r4 89 90 ldr r5, [r0] 91 cmp r5, r1 92 movne r0, r5 93 bne 2f 94 95 str r2, [r0] 96 mov r0, r5 97 982: 99 msr cpsr_c, r3 100 ldmfd sp!, {r4, r5} 101 RET 102END(dtrace_cas32) 103END(dtrace_casptr) 104 105/* 106uint8_t 107dtrace_fuword8_nocheck(void *addr) 108*/ 109ENTRY(dtrace_fuword8_nocheck) 110 ldrb r3, [r0] 111 mov r0, r3 112 RET 113END(dtrace_fuword8_nocheck) 114 115/* 116uint16_t 117dtrace_fuword16_nocheck(void *addr) 118*/ 119ENTRY(dtrace_fuword16_nocheck) 120 ldrh r3, [r0] 121 mov r0, r3 122 RET 123END(dtrace_fuword16_nocheck) 124 125/* 126uint32_t 127dtrace_fuword32_nocheck(void *addr) 128*/ 129ENTRY(dtrace_fuword32_nocheck) 130 ldr r3, [r0] 131 mov r0, r3 132 RET 133END(dtrace_fuword32_nocheck) 134 135/* 136uint64_t 137dtrace_fuword64_nocheck(void *addr) 138XXX: add byteorder check 139*/ 140ENTRY(dtrace_fuword64_nocheck) 141 ldm r0, {r2, r3} 142 143 mov r0, r2 144 mov r1, r3 145#if 0 146/* little endian */ 147 mov r0, r2 148 mov r1, r3 149/* big endian */ 150 mov r0, r3 151 mov r1, r2 152#endif 153 RET 154END(dtrace_fuword64_nocheck) 155 156/* 157void 158dtrace_copy(uintptr_t uaddr, uintptr_t kaddr, size_t size) 159*/ 160ENTRY(dtrace_copy) 161 stmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 162 teq r2, #0x00000000 163 mov r5, #0x00000000 164 beq 2f 165 1661: ldrb r4, [r0], #0x0001 167 add r5, r5, #0x00000001 168 strb r4, [r1], #0x0001 169 teqne r5, r2 170 bne 1b 171 1722: ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 173 RET 174END(dtrace_copy) 175 176 177/* 178void 179dtrace_copystr(uintptr_t uaddr, uintptr_t kaddr, size_t size, 180 volatile uint16_t *flags) 181XXX: Check for flags? 182*/ 183ENTRY(dtrace_copystr) 184 stmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 185 teq r2, #0x00000000 186 mov r5, #0x00000000 187 beq 2f 188 1891: ldrb r4, [r0], #0x0001 190 add r5, r5, #0x00000001 191 teq r4, #0x00000000 192 strb r4, [r1], #0x0001 193 teqne r5, r2 194 bne 1b 195 1962: ldmfd sp!, {r4-r5} /* stack is 8 byte aligned */ 197 RET 198END(dtrace_copystr) 199 200 201/* 202void dtrace_invop_init(void) 203*/ 204ENTRY(dtrace_invop_init) 205 ldr r1, .Ldtrace_invop 206 ldr r2, .Ldtrace_invop_jump_addr 207 str r1, [r2] 208 RET 209 .align 0 210.Ldtrace_invop: 211 .word dtrace_invop 212.Ldtrace_invop_jump_addr: 213 .word dtrace_invop_jump_addr 214END(dtrace_invop_init) 215 216/* 217void dtrace_invop_uninit(void) 218*/ 219ENTRY(dtrace_invop_uninit) 220 mov r0, #0 221 ldr r1, .Ldtrace_invop_jump_addr 222 str r0, [r1] 223 RET 224END(dtrace_invop_uninit) 225 226/* 227void 228vpanic(const char *format, va_list alist) 229*/ 230ENTRY(vpanic) /* Initial stack layout: */ 231vpanic_common: 232 RET 233END(vpanic) 234 235/* 236void 237dtrace_vpanic(const char *format, va_list alist) 238*/ 239ENTRY(dtrace_vpanic) /* Initial stack layout: */ 240 RET 241END(dtrace_vpanic) 242 243/* 244uintptr_t 245dtrace_caller(int aframes) 246*/ 247ENTRY(dtrace_caller) 248 mov r0, #-1 249 RET 250END(dtrace_caller) 251