1*53d1339bSjoerg# $NetBSD: Makefile,v 1.2 2021/05/30 01:56:50 joerg Exp $ 276c7fc5fSjoerg 376c7fc5fSjoergLIB= LLVMARMCodeGen 476c7fc5fSjoerg 576c7fc5fSjoerg.include <bsd.init.mk> 676c7fc5fSjoerg 776c7fc5fSjoergCPPFLAGS+= -I${LLVM_SRCDIR}/lib/Target/ARM 876c7fc5fSjoerg 976c7fc5fSjoerg.PATH: ${LLVM_SRCDIR}/lib/Target/ARM 1076c7fc5fSjoerg 1176c7fc5fSjoergSRCS+= A15SDOptimizer.cpp \ 1276c7fc5fSjoerg ARMAsmPrinter.cpp \ 1376c7fc5fSjoerg ARMBaseInstrInfo.cpp \ 1476c7fc5fSjoerg ARMBaseRegisterInfo.cpp \ 15*53d1339bSjoerg ARMBasicBlockInfo.cpp \ 16*53d1339bSjoerg ARMBlockPlacement.cpp \ 1776c7fc5fSjoerg ARMCallingConv.cpp \ 1876c7fc5fSjoerg ARMCallLowering.cpp \ 1976c7fc5fSjoerg ARMConstantIslandPass.cpp \ 2076c7fc5fSjoerg ARMConstantPoolValue.cpp \ 2176c7fc5fSjoerg ARMExpandPseudoInsts.cpp \ 2276c7fc5fSjoerg ARMFastISel.cpp \ 2376c7fc5fSjoerg ARMFrameLowering.cpp \ 2476c7fc5fSjoerg ARMHazardRecognizer.cpp \ 2576c7fc5fSjoerg ARMInstrInfo.cpp \ 2676c7fc5fSjoerg ARMInstructionSelector.cpp \ 2776c7fc5fSjoerg ARMISelDAGToDAG.cpp \ 2876c7fc5fSjoerg ARMISelLowering.cpp \ 2976c7fc5fSjoerg ARMLegalizerInfo.cpp \ 3076c7fc5fSjoerg ARMLoadStoreOptimizer.cpp \ 3176c7fc5fSjoerg ARMLowOverheadLoops.cpp \ 3276c7fc5fSjoerg ARMMachineFunctionInfo.cpp \ 3376c7fc5fSjoerg ARMMacroFusion.cpp \ 3476c7fc5fSjoerg ARMMCInstLower.cpp \ 3576c7fc5fSjoerg ARMOptimizeBarriersPass.cpp \ 3676c7fc5fSjoerg ARMParallelDSP.cpp \ 3776c7fc5fSjoerg ARMRegisterBankInfo.cpp \ 3876c7fc5fSjoerg ARMRegisterInfo.cpp \ 3976c7fc5fSjoerg ARMSelectionDAGInfo.cpp \ 40*53d1339bSjoerg ARMSLSHardening.cpp \ 4176c7fc5fSjoerg ARMSubtarget.cpp \ 4276c7fc5fSjoerg ARMTargetMachine.cpp \ 4376c7fc5fSjoerg ARMTargetObjectFile.cpp \ 4476c7fc5fSjoerg ARMTargetTransformInfo.cpp \ 4576c7fc5fSjoerg MLxExpansionPass.cpp \ 46*53d1339bSjoerg MVEGatherScatterLowering.cpp \ 47*53d1339bSjoerg MVELaneInterleavingPass.cpp \ 4876c7fc5fSjoerg MVETailPredication.cpp \ 49*53d1339bSjoerg MVETPAndVPTOptimisationsPass.cpp \ 5076c7fc5fSjoerg MVEVPTBlockPass.cpp \ 5176c7fc5fSjoerg Thumb1FrameLowering.cpp \ 5276c7fc5fSjoerg Thumb1InstrInfo.cpp \ 5376c7fc5fSjoerg Thumb2InstrInfo.cpp \ 5476c7fc5fSjoerg Thumb2ITBlockPass.cpp \ 5576c7fc5fSjoerg Thumb2SizeReduction.cpp \ 5676c7fc5fSjoerg ThumbRegisterInfo.cpp 5776c7fc5fSjoerg 5876c7fc5fSjoergTABLEGEN_SRC= ARM.td 5976c7fc5fSjoergTABLEGEN_INCLUDES= -I${LLVM_SRCDIR}/lib/Target/ARM 6076c7fc5fSjoergTABLEGEN_OUTPUT= \ 6176c7fc5fSjoerg ARMGenAsmMatcher.inc|-gen-asm-matcher \ 6276c7fc5fSjoerg ARMGenAsmWriter.inc|-gen-asm-writer \ 6376c7fc5fSjoerg ARMGenCallingConv.inc|-gen-callingconv \ 6476c7fc5fSjoerg ARMGenCodeEmitter.inc|-gen-emitter \ 6576c7fc5fSjoerg ARMGenDAGISel.inc|-gen-dag-isel \ 6676c7fc5fSjoerg ARMGenDisassemblerTables.inc|-gen-disassembler \ 6776c7fc5fSjoerg ARMGenFastISel.inc|-gen-fast-isel \ 6876c7fc5fSjoerg ARMGenGlobalISel.inc|-gen-global-isel \ 6976c7fc5fSjoerg ARMGenInstrInfo.inc|-gen-instr-info \ 7076c7fc5fSjoerg ARMGenMCCodeEmitter.inc|-gen-emitter \ 7176c7fc5fSjoerg ARMGenMCPseudoLowering.inc|-gen-pseudo-lowering \ 7276c7fc5fSjoerg ARMGenRegisterBank.inc|-gen-register-bank \ 7376c7fc5fSjoerg ARMGenRegisterInfo.inc|-gen-register-info \ 7476c7fc5fSjoerg ARMGenSubtargetInfo.inc|-gen-subtarget \ 7576c7fc5fSjoerg ARMGenSystemRegister.inc|-gen-searchable-tables 7676c7fc5fSjoerg 7776c7fc5fSjoerg 7876c7fc5fSjoerg.include "${.PARSEDIR}/../../tablegen.mk" 7976c7fc5fSjoerg 8076c7fc5fSjoerg.if defined(HOSTLIB) 8176c7fc5fSjoerg.include <bsd.hostlib.mk> 8276c7fc5fSjoerg.else 8376c7fc5fSjoerg.include <bsd.lib.mk> 8476c7fc5fSjoerg.endif 85