1# $NetBSD: Makefile,v 1.1 2019/11/11 22:45:03 joerg Exp $ 2 3LIB= LLVMAMDGPUCodeGen 4 5.include <bsd.init.mk> 6 7CPPFLAGS+= -I${LLVM_SRCDIR}/lib/Target/AMDGPU 8 9.PATH: ${LLVM_SRCDIR}/lib/Target/AMDGPU 10 11SRCS+= AMDGPUAliasAnalysis.cpp \ 12 AMDGPUAlwaysInlinePass.cpp \ 13 AMDGPUAnnotateKernelFeatures.cpp \ 14 AMDGPUAnnotateUniformValues.cpp \ 15 AMDGPUArgumentUsageInfo.cpp \ 16 AMDGPUAsmPrinter.cpp \ 17 AMDGPUAtomicOptimizer.cpp \ 18 AMDGPUCallLowering.cpp \ 19 AMDGPUCodeGenPrepare.cpp \ 20 AMDGPUFixFunctionBitcasts.cpp \ 21 AMDGPUFrameLowering.cpp \ 22 AMDGPUHSAMetadataStreamer.cpp \ 23 AMDGPUInline.cpp \ 24 AMDGPUInstrInfo.cpp \ 25 AMDGPUInstructionSelector.cpp \ 26 AMDGPUISelDAGToDAG.cpp \ 27 AMDGPUISelLowering.cpp \ 28 AMDGPULegalizerInfo.cpp \ 29 AMDGPULibCalls.cpp \ 30 AMDGPULibFunc.cpp \ 31 AMDGPULowerIntrinsics.cpp \ 32 AMDGPULowerKernelArguments.cpp \ 33 AMDGPULowerKernelAttributes.cpp \ 34 AMDGPUMachineCFGStructurizer.cpp \ 35 AMDGPUMachineFunction.cpp \ 36 AMDGPUMachineModuleInfo.cpp \ 37 AMDGPUMacroFusion.cpp \ 38 AMDGPUMCInstLower.cpp \ 39 AMDGPUOpenCLEnqueuedBlockLowering.cpp \ 40 AMDGPUPerfHintAnalysis.cpp \ 41 AMDGPUPrintfRuntimeBinding.cpp \ 42 AMDGPUPromoteAlloca.cpp \ 43 AMDGPUPropagateAttributes.cpp \ 44 AMDGPURegisterBankInfo.cpp \ 45 AMDGPURegisterInfo.cpp \ 46 AMDGPURewriteOutArguments.cpp \ 47 AMDGPUSubtarget.cpp \ 48 AMDGPUTargetMachine.cpp \ 49 AMDGPUTargetObjectFile.cpp \ 50 AMDGPUTargetTransformInfo.cpp \ 51 AMDGPUUnifyDivergentExitNodes.cpp \ 52 AMDGPUUnifyMetadata.cpp \ 53 AMDILCFGStructurizer.cpp \ 54 GCNDPPCombine.cpp \ 55 GCNHazardRecognizer.cpp \ 56 GCNILPSched.cpp \ 57 GCNIterativeScheduler.cpp \ 58 GCNMinRegStrategy.cpp \ 59 GCNNSAReassign.cpp \ 60 GCNRegBankReassign.cpp \ 61 GCNRegPressure.cpp \ 62 GCNSchedStrategy.cpp \ 63 R600AsmPrinter.cpp \ 64 R600ClauseMergePass.cpp \ 65 R600ControlFlowFinalizer.cpp \ 66 R600EmitClauseMarkers.cpp \ 67 R600ExpandSpecialInstrs.cpp \ 68 R600FrameLowering.cpp \ 69 R600InstrInfo.cpp \ 70 R600ISelLowering.cpp \ 71 R600MachineFunctionInfo.cpp \ 72 R600MachineScheduler.cpp \ 73 R600OpenCLImageTypeLoweringPass.cpp \ 74 R600OptimizeVectorRegisters.cpp \ 75 R600Packetizer.cpp \ 76 R600RegisterInfo.cpp \ 77 SIAddIMGInit.cpp \ 78 SIAnnotateControlFlow.cpp \ 79 SIFixSGPRCopies.cpp \ 80 SIFixupVectorISel.cpp \ 81 SIFixVGPRCopies.cpp \ 82 SIFoldOperands.cpp \ 83 SIFormMemoryClauses.cpp \ 84 SIFrameLowering.cpp \ 85 SIInsertSkips.cpp \ 86 SIInsertWaitcnts.cpp \ 87 SIInstrInfo.cpp \ 88 SIISelLowering.cpp \ 89 SILoadStoreOptimizer.cpp \ 90 SILowerControlFlow.cpp \ 91 SILowerI1Copies.cpp \ 92 SILowerSGPRSpills.cpp \ 93 SIMachineFunctionInfo.cpp \ 94 SIMachineScheduler.cpp \ 95 SIMemoryLegalizer.cpp \ 96 SIModeRegister.cpp \ 97 SIOptimizeExecMasking.cpp \ 98 SIOptimizeExecMaskingPreRA.cpp \ 99 SIPeepholeSDWA.cpp \ 100 SIPreAllocateWWMRegs.cpp \ 101 SIRegisterInfo.cpp \ 102 SIShrinkInstructions.cpp \ 103 SIWholeQuadMode.cpp 104 105TABLEGEN_SRC= AMDGPU.td AMDGPUGISel.td R600.td 106TABLEGEN_INCLUDES= -I${LLVM_SRCDIR}/lib/Target/AMDGPU 107TABLEGEN_OUTPUT.AMDGPU.td= \ 108 AMDGPUGenAsmMatcher.inc|-gen-asm-matcher \ 109 AMDGPUGenAsmWriter.inc|-gen-asm-writer \ 110 AMDGPUGenCallingConv.inc|-gen-callingconv \ 111 AMDGPUGenDAGISel.inc|-gen-dag-isel \ 112 AMDGPUGenDisassemblerTables.inc|-gen-disassembler \ 113 AMDGPUGenInstrInfo.inc|-gen-instr-info \ 114 AMDGPUGenIntrinsicEnums.inc|-gen-tgt-intrinsic-enums \ 115 AMDGPUGenIntrinsicImpl.inc|-gen-tgt-intrinsic-impl \ 116 AMDGPUGenMCCodeEmitter.inc|-gen-emitter \ 117 AMDGPUGenMCPseudoLowering.inc|-gen-pseudo-lowering \ 118 AMDGPUGenRegisterBank.inc|-gen-register-bank \ 119 AMDGPUGenRegisterInfo.inc|-gen-register-info \ 120 AMDGPUGenSearchableTables.inc|-gen-searchable-tables \ 121 AMDGPUGenSubtargetInfo.inc|-gen-subtarget 122 123TABLEGEN_OUTPUT.AMDGPUGISel.td= \ 124 AMDGPUGenGlobalISel.inc|-gen-global-isel 125 126TABLEGEN_OUTPUT.R600.td= \ 127 R600GenAsmWriter.inc|-gen-asm-writer \ 128 R600GenCallingConv.inc|-gen-callingconv \ 129 R600GenDAGISel.inc|-gen-dag-isel \ 130 R600GenDFAPacketizer.inc|-gen-dfa-packetizer \ 131 R600GenInstrInfo.inc|-gen-instr-info \ 132 R600GenMCCodeEmitter.inc|-gen-emitter \ 133 R600GenRegisterInfo.inc|-gen-register-info \ 134 R600GenSubtargetInfo.inc|-gen-subtarget 135 136.include "${.PARSEDIR}/../../tablegen.mk" 137 138.if defined(HOSTLIB) 139.include <bsd.hostlib.mk> 140.else 141.include <bsd.lib.mk> 142.endif 143