1 //===-- RISCVMCTargetDesc.cpp - RISCV Target Descriptions -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// This file provides RISCV-specific target descriptions. 10 /// 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVMCTargetDesc.h" 14 #include "RISCVBaseInfo.h" 15 #include "RISCVELFStreamer.h" 16 #include "RISCVInstPrinter.h" 17 #include "RISCVMCAsmInfo.h" 18 #include "RISCVTargetStreamer.h" 19 #include "TargetInfo/RISCVTargetInfo.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/MC/MCAsmInfo.h" 22 #include "llvm/MC/MCInstrAnalysis.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCStreamer.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/TargetRegistry.h" 29 30 #define GET_INSTRINFO_MC_DESC 31 #include "RISCVGenInstrInfo.inc" 32 33 #define GET_REGINFO_MC_DESC 34 #include "RISCVGenRegisterInfo.inc" 35 36 #define GET_SUBTARGETINFO_MC_DESC 37 #include "RISCVGenSubtargetInfo.inc" 38 39 using namespace llvm; 40 41 static MCInstrInfo *createRISCVMCInstrInfo() { 42 MCInstrInfo *X = new MCInstrInfo(); 43 InitRISCVMCInstrInfo(X); 44 return X; 45 } 46 47 static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { 48 MCRegisterInfo *X = new MCRegisterInfo(); 49 InitRISCVMCRegisterInfo(X, RISCV::X1); 50 return X; 51 } 52 53 static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, 54 const Triple &TT, 55 const MCTargetOptions &Options) { 56 MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); 57 58 MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); 59 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); 60 MAI->addInitialFrameState(Inst); 61 62 return MAI; 63 } 64 65 static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, 66 StringRef CPU, StringRef FS) { 67 if (CPU.empty()) 68 CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; 69 if (CPU == "generic") 70 report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + 71 (TT.isArch64Bit() ? "generic-rv64" : "generic-rv32")); 72 return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 73 } 74 75 static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, 76 unsigned SyntaxVariant, 77 const MCAsmInfo &MAI, 78 const MCInstrInfo &MII, 79 const MCRegisterInfo &MRI) { 80 return new RISCVInstPrinter(MAI, MII, MRI); 81 } 82 83 static MCTargetStreamer * 84 createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 85 const Triple &TT = STI.getTargetTriple(); 86 if (TT.isOSBinFormatELF()) 87 return new RISCVTargetELFStreamer(S, STI); 88 return nullptr; 89 } 90 91 static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, 92 formatted_raw_ostream &OS, 93 MCInstPrinter *InstPrint, 94 bool isVerboseAsm) { 95 return new RISCVTargetAsmStreamer(S, OS); 96 } 97 98 static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) { 99 return new RISCVTargetStreamer(S); 100 } 101 102 namespace { 103 104 class RISCVMCInstrAnalysis : public MCInstrAnalysis { 105 public: 106 explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info) 107 : MCInstrAnalysis(Info) {} 108 109 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 110 uint64_t &Target) const override { 111 if (isConditionalBranch(Inst)) { 112 int64_t Imm; 113 if (Size == 2) 114 Imm = Inst.getOperand(1).getImm(); 115 else 116 Imm = Inst.getOperand(2).getImm(); 117 Target = Addr + Imm; 118 return true; 119 } 120 121 if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { 122 Target = Addr + Inst.getOperand(0).getImm(); 123 return true; 124 } 125 126 if (Inst.getOpcode() == RISCV::JAL) { 127 Target = Addr + Inst.getOperand(1).getImm(); 128 return true; 129 } 130 131 return false; 132 } 133 }; 134 135 } // end anonymous namespace 136 137 static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) { 138 return new RISCVMCInstrAnalysis(Info); 139 } 140 141 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() { 142 for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { 143 TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo); 144 TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo); 145 TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo); 146 TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); 147 TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); 148 TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); 149 TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo); 150 TargetRegistry::RegisterObjectTargetStreamer( 151 *T, createRISCVObjectTargetStreamer); 152 TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis); 153 154 // Register the asm target streamer. 155 TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer); 156 // Register the null target streamer. 157 TargetRegistry::RegisterNullTargetStreamer(*T, 158 createRISCVNullTargetStreamer); 159 } 160 } 161