1*0a6a1f1dSLionel Sambuc /* ===-- clear_cache.c - Implement __clear_cache ---------------------------===
2*0a6a1f1dSLionel Sambuc *
3*0a6a1f1dSLionel Sambuc * The LLVM Compiler Infrastructure
4*0a6a1f1dSLionel Sambuc *
5*0a6a1f1dSLionel Sambuc * This file is dual licensed under the MIT and the University of Illinois Open
6*0a6a1f1dSLionel Sambuc * Source Licenses. See LICENSE.TXT for details.
7*0a6a1f1dSLionel Sambuc *
8*0a6a1f1dSLionel Sambuc * ===----------------------------------------------------------------------===
9*0a6a1f1dSLionel Sambuc */
10*0a6a1f1dSLionel Sambuc
11*0a6a1f1dSLionel Sambuc #include "int_lib.h"
12*0a6a1f1dSLionel Sambuc
13*0a6a1f1dSLionel Sambuc #if __APPLE__
14*0a6a1f1dSLionel Sambuc #include <libkern/OSCacheControl.h>
15*0a6a1f1dSLionel Sambuc #endif
16*0a6a1f1dSLionel Sambuc #if defined(__NetBSD__) && defined(__arm__)
17*0a6a1f1dSLionel Sambuc #include <machine/sysarch.h>
18*0a6a1f1dSLionel Sambuc #endif
19*0a6a1f1dSLionel Sambuc
20*0a6a1f1dSLionel Sambuc #if defined(ANDROID) && defined(__mips__)
21*0a6a1f1dSLionel Sambuc #include <sys/cachectl.h>
22*0a6a1f1dSLionel Sambuc #endif
23*0a6a1f1dSLionel Sambuc
24*0a6a1f1dSLionel Sambuc #if defined(ANDROID) && defined(__arm__)
25*0a6a1f1dSLionel Sambuc #include <asm/unistd.h>
26*0a6a1f1dSLionel Sambuc #endif
27*0a6a1f1dSLionel Sambuc
28*0a6a1f1dSLionel Sambuc /*
29*0a6a1f1dSLionel Sambuc * The compiler generates calls to __clear_cache() when creating
30*0a6a1f1dSLionel Sambuc * trampoline functions on the stack for use with nested functions.
31*0a6a1f1dSLionel Sambuc * It is expected to invalidate the instruction cache for the
32*0a6a1f1dSLionel Sambuc * specified range.
33*0a6a1f1dSLionel Sambuc */
34*0a6a1f1dSLionel Sambuc
35*0a6a1f1dSLionel Sambuc COMPILER_RT_EXPORT void
__clear_cache(void * start,void * end)36*0a6a1f1dSLionel Sambuc __clear_cache(void* start, void* end)
37*0a6a1f1dSLionel Sambuc {
38*0a6a1f1dSLionel Sambuc #if __i386__ || __x86_64__
39*0a6a1f1dSLionel Sambuc /*
40*0a6a1f1dSLionel Sambuc * Intel processors have a unified instruction and data cache
41*0a6a1f1dSLionel Sambuc * so there is nothing to do
42*0a6a1f1dSLionel Sambuc */
43*0a6a1f1dSLionel Sambuc #elif defined(__arm__) && !defined(__APPLE__)
44*0a6a1f1dSLionel Sambuc #if defined(__NetBSD__)
45*0a6a1f1dSLionel Sambuc struct arm_sync_icache_args arg;
46*0a6a1f1dSLionel Sambuc
47*0a6a1f1dSLionel Sambuc arg.addr = (uintptr_t)start;
48*0a6a1f1dSLionel Sambuc arg.len = (uintptr_t)end - (uintptr_t)start;
49*0a6a1f1dSLionel Sambuc
50*0a6a1f1dSLionel Sambuc sysarch(ARM_SYNC_ICACHE, &arg);
51*0a6a1f1dSLionel Sambuc #elif defined(ANDROID)
52*0a6a1f1dSLionel Sambuc const register int start_reg __asm("r0") = (int) (intptr_t) start;
53*0a6a1f1dSLionel Sambuc const register int end_reg __asm("r1") = (int) (intptr_t) end;
54*0a6a1f1dSLionel Sambuc const register int flags __asm("r2") = 0;
55*0a6a1f1dSLionel Sambuc const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
56*0a6a1f1dSLionel Sambuc __asm __volatile("svc 0x0" : "=r"(start_reg)
57*0a6a1f1dSLionel Sambuc : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0");
58*0a6a1f1dSLionel Sambuc if (start_reg != 0) {
59*0a6a1f1dSLionel Sambuc compilerrt_abort();
60*0a6a1f1dSLionel Sambuc }
61*0a6a1f1dSLionel Sambuc #else
62*0a6a1f1dSLionel Sambuc compilerrt_abort();
63*0a6a1f1dSLionel Sambuc #endif
64*0a6a1f1dSLionel Sambuc #elif defined(ANDROID) && defined(__mips__)
65*0a6a1f1dSLionel Sambuc const uintptr_t start_int = (uintptr_t) start;
66*0a6a1f1dSLionel Sambuc const uintptr_t end_int = (uintptr_t) end;
67*0a6a1f1dSLionel Sambuc _flush_cache(start, (end_int - start_int), BCACHE);
68*0a6a1f1dSLionel Sambuc #elif defined(__aarch64__) && !defined(__APPLE__)
69*0a6a1f1dSLionel Sambuc uint64_t xstart = (uint64_t)(uintptr_t) start;
70*0a6a1f1dSLionel Sambuc uint64_t xend = (uint64_t)(uintptr_t) end;
71*0a6a1f1dSLionel Sambuc
72*0a6a1f1dSLionel Sambuc // Get Cache Type Info
73*0a6a1f1dSLionel Sambuc uint64_t ctr_el0;
74*0a6a1f1dSLionel Sambuc __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
75*0a6a1f1dSLionel Sambuc
76*0a6a1f1dSLionel Sambuc /*
77*0a6a1f1dSLionel Sambuc * dc & ic instructions must use 64bit registers so we don't use
78*0a6a1f1dSLionel Sambuc * uintptr_t in case this runs in an IPL32 environment.
79*0a6a1f1dSLionel Sambuc */
80*0a6a1f1dSLionel Sambuc const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
81*0a6a1f1dSLionel Sambuc for (uint64_t addr = xstart; addr < xend; addr += dcache_line_size)
82*0a6a1f1dSLionel Sambuc __asm __volatile("dc cvau, %0" :: "r"(addr));
83*0a6a1f1dSLionel Sambuc __asm __volatile("dsb ish");
84*0a6a1f1dSLionel Sambuc
85*0a6a1f1dSLionel Sambuc const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
86*0a6a1f1dSLionel Sambuc for (uint64_t addr = xstart; addr < xend; addr += icache_line_size)
87*0a6a1f1dSLionel Sambuc __asm __volatile("ic ivau, %0" :: "r"(addr));
88*0a6a1f1dSLionel Sambuc __asm __volatile("isb sy");
89*0a6a1f1dSLionel Sambuc #else
90*0a6a1f1dSLionel Sambuc #if __APPLE__
91*0a6a1f1dSLionel Sambuc /* On Darwin, sys_icache_invalidate() provides this functionality */
92*0a6a1f1dSLionel Sambuc sys_icache_invalidate(start, end-start);
93*0a6a1f1dSLionel Sambuc #else
94*0a6a1f1dSLionel Sambuc compilerrt_abort();
95*0a6a1f1dSLionel Sambuc #endif
96*0a6a1f1dSLionel Sambuc #endif
97*0a6a1f1dSLionel Sambuc }
98*0a6a1f1dSLionel Sambuc
99