17eb99bdaSLionel Sambuc /*- 2*0a6a1f1dSLionel Sambuc * $NetBSD: if_lmc.h,v 1.22 2015/09/06 06:01:00 dholland Exp $ 37eb99bdaSLionel Sambuc * 47eb99bdaSLionel Sambuc * Copyright (c) 2002-2006 David Boggs. (boggs@boggs.palo-alto.ca.us) 57eb99bdaSLionel Sambuc * All rights reserved. 67eb99bdaSLionel Sambuc * 77eb99bdaSLionel Sambuc * BSD LICENSE: 87eb99bdaSLionel Sambuc * 97eb99bdaSLionel Sambuc * Redistribution and use in source and binary forms, with or without 107eb99bdaSLionel Sambuc * modification, are permitted provided that the following conditions 117eb99bdaSLionel Sambuc * are met: 127eb99bdaSLionel Sambuc * 1. Redistributions of source code must retain the above copyright 137eb99bdaSLionel Sambuc * notice, this list of conditions and the following disclaimer. 147eb99bdaSLionel Sambuc * 2. Redistributions in binary form must reproduce the above copyright 157eb99bdaSLionel Sambuc * notice, this list of conditions and the following disclaimer in the 167eb99bdaSLionel Sambuc * documentation and/or other materials provided with the distribution. 177eb99bdaSLionel Sambuc * 187eb99bdaSLionel Sambuc * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 197eb99bdaSLionel Sambuc * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 207eb99bdaSLionel Sambuc * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 217eb99bdaSLionel Sambuc * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 227eb99bdaSLionel Sambuc * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 237eb99bdaSLionel Sambuc * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 247eb99bdaSLionel Sambuc * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 257eb99bdaSLionel Sambuc * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 267eb99bdaSLionel Sambuc * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 277eb99bdaSLionel Sambuc * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 287eb99bdaSLionel Sambuc * SUCH DAMAGE. 297eb99bdaSLionel Sambuc * 307eb99bdaSLionel Sambuc * GNU GENERAL PUBLIC LICENSE: 317eb99bdaSLionel Sambuc * 327eb99bdaSLionel Sambuc * This program is free software; you can redistribute it and/or modify it 337eb99bdaSLionel Sambuc * under the terms of the GNU General Public License as published by the Free 347eb99bdaSLionel Sambuc * Software Foundation; either version 2 of the License, or (at your option) 357eb99bdaSLionel Sambuc * any later version. 367eb99bdaSLionel Sambuc * 377eb99bdaSLionel Sambuc * This program is distributed in the hope that it will be useful, but WITHOUT 387eb99bdaSLionel Sambuc * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 397eb99bdaSLionel Sambuc * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 407eb99bdaSLionel Sambuc * more details. 417eb99bdaSLionel Sambuc * 427eb99bdaSLionel Sambuc * You should have received a copy of the GNU General Public License along with 437eb99bdaSLionel Sambuc * this program; if not, write to the Free Software Foundation, Inc., 59 447eb99bdaSLionel Sambuc * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 457eb99bdaSLionel Sambuc */ 467eb99bdaSLionel Sambuc 477eb99bdaSLionel Sambuc #ifndef IF_LMC_H 487eb99bdaSLionel Sambuc #define IF_LMC_H 497eb99bdaSLionel Sambuc 50*0a6a1f1dSLionel Sambuc #include <sys/ioccom.h> 51*0a6a1f1dSLionel Sambuc 52*0a6a1f1dSLionel Sambuc 537eb99bdaSLionel Sambuc #define DEVICE_NAME "lmc" 547eb99bdaSLionel Sambuc 557eb99bdaSLionel Sambuc #define VER_YEAR 2006 567eb99bdaSLionel Sambuc #define VER_MONTH 4 577eb99bdaSLionel Sambuc #define VER_DAY 11 587eb99bdaSLionel Sambuc 597eb99bdaSLionel Sambuc /* netgraph stuff */ 607eb99bdaSLionel Sambuc #define NG_LMC_NODE_TYPE "if_"DEVICE_NAME 617eb99bdaSLionel Sambuc #define NGM_LMC_COOKIE 1144752198 /* date -u +'%s' */ 627eb99bdaSLionel Sambuc 637eb99bdaSLionel Sambuc /* Tulip PCI configuration registers */ 647eb99bdaSLionel Sambuc #define TLP_CFID 0x00 /* 0: CFg ID register */ 657eb99bdaSLionel Sambuc #define TLP_CFCS 0x04 /* 1: CFg Command/Status */ 667eb99bdaSLionel Sambuc #define TLP_CFRV 0x08 /* 2: CFg ReVision */ 677eb99bdaSLionel Sambuc #define TLP_CFLT 0x0C /* 3: CFg Latency Timer */ 687eb99bdaSLionel Sambuc #define TLP_CBIO 0x10 /* 4: Cfg Base IO address */ 697eb99bdaSLionel Sambuc #define TLP_CBMA 0x14 /* 5: Cfg Base Mem Addr */ 707eb99bdaSLionel Sambuc #define TLP_CSID 0x2C /* 11: Cfg Subsys ID reg */ 717eb99bdaSLionel Sambuc #define TLP_CFIT 0x3C /* 15: CFg InTerrupt */ 727eb99bdaSLionel Sambuc #define TLP_CFDD 0x40 /* 16: CFg Driver Data */ 737eb99bdaSLionel Sambuc 747eb99bdaSLionel Sambuc #define TLP_CFID_TULIP 0x00091011 /* DEC 21140A Ethernet chip */ 757eb99bdaSLionel Sambuc 767eb99bdaSLionel Sambuc #define TLP_CFCS_MSTR_ABORT 0x20000000 777eb99bdaSLionel Sambuc #define TLP_CFCS_TARG_ABORT 0x10000000 787eb99bdaSLionel Sambuc #define TLP_CFCS_SYS_ERROR 0x00000100 797eb99bdaSLionel Sambuc #define TLP_CFCS_PAR_ERROR 0x00000040 807eb99bdaSLionel Sambuc #define TLP_CFCS_MWI_ENABLE 0x00000010 817eb99bdaSLionel Sambuc #define TLP_CFCS_BUS_MASTER 0x00000004 827eb99bdaSLionel Sambuc #define TLP_CFCS_MEM_ENABLE 0x00000002 837eb99bdaSLionel Sambuc #define TLP_CFCS_IO_ENABLE 0x00000001 847eb99bdaSLionel Sambuc 857eb99bdaSLionel Sambuc #define TLP_CFLT_LATENCY 0x0000FF00 867eb99bdaSLionel Sambuc #define TLP_CFLT_CACHE 0x000000FF 877eb99bdaSLionel Sambuc 887eb99bdaSLionel Sambuc #define CSID_LMC_HSSI 0x00031376 /* LMC 5200 HSSI card */ 897eb99bdaSLionel Sambuc #define CSID_LMC_T3 0x00041376 /* LMC 5245 T3 card */ 907eb99bdaSLionel Sambuc #define CSID_LMC_SSI 0x00051376 /* LMC 1000 SSI card */ 917eb99bdaSLionel Sambuc #define CSID_LMC_T1E1 0x00061376 /* LMC 1200 T1E1 card */ 927eb99bdaSLionel Sambuc #define CSID_LMC_HSSIc 0x00071376 /* LMC 5200 HSSI cPCI */ 937eb99bdaSLionel Sambuc #define CSID_LMC_SDSL 0x00081376 /* LMC 1168 SDSL card */ 947eb99bdaSLionel Sambuc 957eb99bdaSLionel Sambuc #define TLP_CFIT_MAX_LAT 0xFF000000 967eb99bdaSLionel Sambuc 977eb99bdaSLionel Sambuc #define TLP_CFDD_SLEEP 0x80000000 987eb99bdaSLionel Sambuc #define TLP_CFDD_SNOOZE 0x40000000 997eb99bdaSLionel Sambuc 1007eb99bdaSLionel Sambuc /* Tulip Control and Status Registers */ 1017eb99bdaSLionel Sambuc #define TLP_CSR_STRIDE 8 /* 64 bits */ 1027eb99bdaSLionel Sambuc #define TLP_BUS_MODE 0 * TLP_CSR_STRIDE 1037eb99bdaSLionel Sambuc #define TLP_TX_POLL 1 * TLP_CSR_STRIDE 1047eb99bdaSLionel Sambuc #define TLP_RX_POLL 2 * TLP_CSR_STRIDE 1057eb99bdaSLionel Sambuc #define TLP_RX_LIST 3 * TLP_CSR_STRIDE 1067eb99bdaSLionel Sambuc #define TLP_TX_LIST 4 * TLP_CSR_STRIDE 1077eb99bdaSLionel Sambuc #define TLP_STATUS 5 * TLP_CSR_STRIDE 1087eb99bdaSLionel Sambuc #define TLP_OP_MODE 6 * TLP_CSR_STRIDE 1097eb99bdaSLionel Sambuc #define TLP_INT_ENBL 7 * TLP_CSR_STRIDE 1107eb99bdaSLionel Sambuc #define TLP_MISSED 8 * TLP_CSR_STRIDE 1117eb99bdaSLionel Sambuc #define TLP_SROM_MII 9 * TLP_CSR_STRIDE 1127eb99bdaSLionel Sambuc #define TLP_BIOS_ROM 10 * TLP_CSR_STRIDE 1137eb99bdaSLionel Sambuc #define TLP_TIMER 11 * TLP_CSR_STRIDE 1147eb99bdaSLionel Sambuc #define TLP_GPIO 12 * TLP_CSR_STRIDE 1157eb99bdaSLionel Sambuc #define TLP_CSR13 13 * TLP_CSR_STRIDE 1167eb99bdaSLionel Sambuc #define TLP_CSR14 14 * TLP_CSR_STRIDE 1177eb99bdaSLionel Sambuc #define TLP_WDOG 15 * TLP_CSR_STRIDE 1187eb99bdaSLionel Sambuc #define TLP_CSR_SIZE 128 /* IO bus space size */ 1197eb99bdaSLionel Sambuc 1207eb99bdaSLionel Sambuc /* CSR 0 - PCI Bus Mode Register */ 1217eb99bdaSLionel Sambuc #define TLP_BUS_WRITE_INVAL 0x01000000 /* DONT USE! */ 1227eb99bdaSLionel Sambuc #define TLP_BUS_READ_LINE 0x00800000 1237eb99bdaSLionel Sambuc #define TLP_BUS_READ_MULT 0x00200000 1247eb99bdaSLionel Sambuc #define TLP_BUS_DESC_BIGEND 0x00100000 1257eb99bdaSLionel Sambuc #define TLP_BUS_TAP 0x000E0000 1267eb99bdaSLionel Sambuc #define TLP_BUS_CAL 0x0000C000 1277eb99bdaSLionel Sambuc #define TLP_BUS_PBL 0x00003F00 1287eb99bdaSLionel Sambuc #define TLP_BUS_DATA_BIGEND 0x00000080 1297eb99bdaSLionel Sambuc #define TLP_BUS_DSL 0x0000007C 1307eb99bdaSLionel Sambuc #define TLP_BUS_ARB 0x00000002 1317eb99bdaSLionel Sambuc #define TLP_BUS_RESET 0x00000001 1327eb99bdaSLionel Sambuc #define TLP_BUS_CAL_SHIFT 14 1337eb99bdaSLionel Sambuc #define TLP_BUS_PBL_SHIFT 8 1347eb99bdaSLionel Sambuc 1357eb99bdaSLionel Sambuc /* CSR 5 - Status Register */ 1367eb99bdaSLionel Sambuc #define TLP_STAT_FATAL_BITS 0x03800000 1377eb99bdaSLionel Sambuc #define TLP_STAT_TX_FSM 0x00700000 1387eb99bdaSLionel Sambuc #define TLP_STAT_RX_FSM 0x000E0000 1397eb99bdaSLionel Sambuc #define TLP_STAT_FATAL_ERROR 0x00002000 1407eb99bdaSLionel Sambuc #define TLP_STAT_TX_UNDERRUN 0x00000020 1417eb99bdaSLionel Sambuc #define TLP_STAT_FATAL_SHIFT 23 1427eb99bdaSLionel Sambuc 1437eb99bdaSLionel Sambuc /* CSR 6 - Operating Mode Register */ 1447eb99bdaSLionel Sambuc #define TLP_OP_RECEIVE_ALL 0x40000000 1457eb99bdaSLionel Sambuc #define TLP_OP_MUST_BE_ONE 0x02000000 1467eb99bdaSLionel Sambuc #define TLP_OP_NO_HEART_BEAT 0x00080000 1477eb99bdaSLionel Sambuc #define TLP_OP_PORT_SELECT 0x00040000 1487eb99bdaSLionel Sambuc #define TLP_OP_TX_THRESH 0x0000C000 1497eb99bdaSLionel Sambuc #define TLP_OP_TX_RUN 0x00002000 1507eb99bdaSLionel Sambuc #define TLP_OP_LOOP_MODE 0x00000C00 1517eb99bdaSLionel Sambuc #define TLP_OP_EXT_LOOP 0x00000800 1527eb99bdaSLionel Sambuc #define TLP_OP_INT_LOOP 0x00000400 1537eb99bdaSLionel Sambuc #define TLP_OP_FULL_DUPLEX 0x00000200 1547eb99bdaSLionel Sambuc #define TLP_OP_PROMISCUOUS 0x00000040 1557eb99bdaSLionel Sambuc #define TLP_OP_PASS_BAD_PKT 0x00000008 1567eb99bdaSLionel Sambuc #define TLP_OP_RX_RUN 0x00000002 1577eb99bdaSLionel Sambuc #define TLP_OP_TR_SHIFT 14 1587eb99bdaSLionel Sambuc #define TLP_OP_INIT (TLP_OP_PORT_SELECT | \ 1597eb99bdaSLionel Sambuc TLP_OP_FULL_DUPLEX | \ 1607eb99bdaSLionel Sambuc TLP_OP_MUST_BE_ONE | \ 1617eb99bdaSLionel Sambuc TLP_OP_NO_HEART_BEAT | \ 1627eb99bdaSLionel Sambuc TLP_OP_RECEIVE_ALL | \ 1637eb99bdaSLionel Sambuc TLP_OP_PROMISCUOUS | \ 1647eb99bdaSLionel Sambuc TLP_OP_PASS_BAD_PKT | \ 1657eb99bdaSLionel Sambuc TLP_OP_RX_RUN | \ 1667eb99bdaSLionel Sambuc TLP_OP_TX_RUN) 1677eb99bdaSLionel Sambuc 1687eb99bdaSLionel Sambuc /* CSR 7 - Interrupt Enable Register */ 1697eb99bdaSLionel Sambuc #define TLP_INT_NORMAL_INTR 0x00010000 1707eb99bdaSLionel Sambuc #define TLP_INT_ABNRML_INTR 0x00008000 1717eb99bdaSLionel Sambuc #define TLP_INT_FATAL_ERROR 0x00002000 1727eb99bdaSLionel Sambuc #define TLP_INT_RX_NO_BUFS 0x00000080 1737eb99bdaSLionel Sambuc #define TLP_INT_RX_INTR 0x00000040 1747eb99bdaSLionel Sambuc #define TLP_INT_TX_UNDERRUN 0x00000020 1757eb99bdaSLionel Sambuc #define TLP_INT_TX_INTR 0x00000001 1767eb99bdaSLionel Sambuc #define TLP_INT_DISABLE 0 1777eb99bdaSLionel Sambuc #define TLP_INT_TX (TLP_INT_NORMAL_INTR | \ 1787eb99bdaSLionel Sambuc TLP_INT_ABNRML_INTR | \ 1797eb99bdaSLionel Sambuc TLP_INT_FATAL_ERROR | \ 1807eb99bdaSLionel Sambuc TLP_INT_TX_UNDERRUN | \ 1817eb99bdaSLionel Sambuc TLP_INT_TX_INTR) 1827eb99bdaSLionel Sambuc #define TLP_INT_RX (TLP_INT_NORMAL_INTR | \ 1837eb99bdaSLionel Sambuc TLP_INT_ABNRML_INTR | \ 1847eb99bdaSLionel Sambuc TLP_INT_FATAL_ERROR | \ 1857eb99bdaSLionel Sambuc TLP_INT_RX_NO_BUFS | \ 1867eb99bdaSLionel Sambuc TLP_INT_RX_INTR) 1877eb99bdaSLionel Sambuc #define TLP_INT_TXRX (TLP_INT_TX | TLP_INT_RX) 1887eb99bdaSLionel Sambuc 1897eb99bdaSLionel Sambuc /* CSR 8 - RX Missed Frames & Overrun Register */ 1907eb99bdaSLionel Sambuc #define TLP_MISS_OCO 0x10000000 1917eb99bdaSLionel Sambuc #define TLP_MISS_OVERRUN 0x0FFE0000 1927eb99bdaSLionel Sambuc #define TLP_MISS_MFO 0x00010000 1937eb99bdaSLionel Sambuc #define TLP_MISS_MISSED 0x0000FFFF 1947eb99bdaSLionel Sambuc #define TLP_OVERRUN_SHIFT 17 1957eb99bdaSLionel Sambuc 1967eb99bdaSLionel Sambuc /* CSR 9 - SROM & MII & Boot ROM Register */ 1977eb99bdaSLionel Sambuc #define TLP_MII_MDIN 0x00080000 1987eb99bdaSLionel Sambuc #define TLP_MII_MDOE 0x00040000 1997eb99bdaSLionel Sambuc #define TLP_MII_MDOUT 0x00020000 2007eb99bdaSLionel Sambuc #define TLP_MII_MDC 0x00010000 2017eb99bdaSLionel Sambuc 2027eb99bdaSLionel Sambuc #define TLP_BIOS_RD 0x00004000 2037eb99bdaSLionel Sambuc #define TLP_BIOS_WR 0x00002000 2047eb99bdaSLionel Sambuc #define TLP_BIOS_SEL 0x00001000 2057eb99bdaSLionel Sambuc 2067eb99bdaSLionel Sambuc #define TLP_SROM_RD 0x00004000 2077eb99bdaSLionel Sambuc #define TLP_SROM_SEL 0x00000800 2087eb99bdaSLionel Sambuc #define TLP_SROM_DOUT 0x00000008 2097eb99bdaSLionel Sambuc #define TLP_SROM_DIN 0x00000004 2107eb99bdaSLionel Sambuc #define TLP_SROM_CLK 0x00000002 2117eb99bdaSLionel Sambuc #define TLP_SROM_CS 0x00000001 2127eb99bdaSLionel Sambuc 2137eb99bdaSLionel Sambuc /* CSR 12 - General Purpose IO register */ 2147eb99bdaSLionel Sambuc #define TLP_GPIO_DIR 0x00000100 2157eb99bdaSLionel Sambuc 2167eb99bdaSLionel Sambuc /* CSR 15 - Watchdog Timer Register */ 2177eb99bdaSLionel Sambuc #define TLP_WDOG_RX_OFF 0x00000010 2187eb99bdaSLionel Sambuc #define TLP_WDOG_TX_OFF 0x00000001 2197eb99bdaSLionel Sambuc #define TLP_WDOG_INIT (TLP_WDOG_TX_OFF | \ 2207eb99bdaSLionel Sambuc TLP_WDOG_RX_OFF) 2217eb99bdaSLionel Sambuc 2227eb99bdaSLionel Sambuc /* GPIO bits common to all cards */ 2237eb99bdaSLionel Sambuc #define GPIO_INIT 0x01 /* from Xilinx */ 2247eb99bdaSLionel Sambuc #define GPIO_RESET 0x02 /* to Xilinx */ 2257eb99bdaSLionel Sambuc /* bits 2 and 3 vary with card type -- see below */ 2267eb99bdaSLionel Sambuc #define GPIO_MODE 0x10 /* to Xilinx */ 2277eb99bdaSLionel Sambuc #define GPIO_DP 0x20 /* to/from Xilinx */ 2287eb99bdaSLionel Sambuc #define GPIO_DATA 0x40 /* serial data */ 2297eb99bdaSLionel Sambuc #define GPIO_CLK 0x80 /* serial clock */ 2307eb99bdaSLionel Sambuc 2317eb99bdaSLionel Sambuc /* HSSI GPIO bits */ 2327eb99bdaSLionel Sambuc #define GPIO_HSSI_ST 0x04 /* send timing sense (deprecated) */ 2337eb99bdaSLionel Sambuc #define GPIO_HSSI_TXCLK 0x08 /* clock source */ 2347eb99bdaSLionel Sambuc 2357eb99bdaSLionel Sambuc /* HSSIc GPIO bits */ 2367eb99bdaSLionel Sambuc #define GPIO_HSSI_SYNTH 0x04 /* Synth osc chip select */ 2377eb99bdaSLionel Sambuc #define GPIO_HSSI_DCE 0x08 /* provide clock on TXCLOCK output */ 2387eb99bdaSLionel Sambuc 2397eb99bdaSLionel Sambuc /* T3 GPIO bits */ 2407eb99bdaSLionel Sambuc #define GPIO_T3_DAC 0x04 /* DAC chip select */ 2417eb99bdaSLionel Sambuc #define GPIO_T3_INTEN 0x08 /* Framer Interupt enable */ 2427eb99bdaSLionel Sambuc 2437eb99bdaSLionel Sambuc /* SSI GPIO bits */ 2447eb99bdaSLionel Sambuc #define GPIO_SSI_SYNTH 0x04 /* Synth osc chip select */ 2457eb99bdaSLionel Sambuc #define GPIO_SSI_DCE 0x08 /* provide clock on TXCLOCK output */ 2467eb99bdaSLionel Sambuc 2477eb99bdaSLionel Sambuc /* T1E1 GPIO bits */ 2487eb99bdaSLionel Sambuc #define GPIO_T1_INTEN 0x08 /* Framer Interupt enable */ 2497eb99bdaSLionel Sambuc 2507eb99bdaSLionel Sambuc /* MII register 16 bits common to all cards */ 2517eb99bdaSLionel Sambuc /* NB: LEDs for HSSI & SSI are in DIFFERENT bits than for T1E1 & T3; oops */ 2527eb99bdaSLionel Sambuc /* NB: CRC32 for HSSI & SSI is in DIFFERENT bit than for T1E1 & T3; oops */ 2537eb99bdaSLionel Sambuc #define MII16_LED_ALL 0x0780 /* RW: LED bit mask */ 2547eb99bdaSLionel Sambuc #define MII16_FIFO 0x0800 /* RW: 1=reset, 0=not reset */ 2557eb99bdaSLionel Sambuc 2567eb99bdaSLionel Sambuc /* MII register 16 bits for HSSI */ 2577eb99bdaSLionel Sambuc #define MII16_HSSI_TA 0x0001 /* RW: host ready; host->modem */ 2587eb99bdaSLionel Sambuc #define MII16_HSSI_CA 0x0002 /* RO: modem ready; modem->host */ 2597eb99bdaSLionel Sambuc #define MII16_HSSI_LA 0x0004 /* RW: loopback A; host->modem */ 2607eb99bdaSLionel Sambuc #define MII16_HSSI_LB 0x0008 /* RW: loopback B; host->modem */ 2617eb99bdaSLionel Sambuc #define MII16_HSSI_LC 0x0010 /* RO: loopback C; modem->host */ 2627eb99bdaSLionel Sambuc #define MII16_HSSI_TM 0x0020 /* RO: test mode; modem->host */ 2637eb99bdaSLionel Sambuc #define MII16_HSSI_CRC32 0x0040 /* RW: CRC length 16/32 */ 2647eb99bdaSLionel Sambuc #define MII16_HSSI_LED_LL 0x0080 /* RW: lower left - green */ 2657eb99bdaSLionel Sambuc #define MII16_HSSI_LED_LR 0x0100 /* RW: lower right - green */ 2667eb99bdaSLionel Sambuc #define MII16_HSSI_LED_UL 0x0200 /* RW: upper left - green */ 2677eb99bdaSLionel Sambuc #define MII16_HSSI_LED_UR 0x0400 /* RW: upper right - red */ 2687eb99bdaSLionel Sambuc #define MII16_HSSI_FIFO 0x0800 /* RW: reset fifos */ 2697eb99bdaSLionel Sambuc #define MII16_HSSI_FORCECA 0x1000 /* RW: [cPCI] force CA on */ 2707eb99bdaSLionel Sambuc #define MII16_HSSI_CLKMUX 0x6000 /* RW: [cPCI] TX clock selection */ 2717eb99bdaSLionel Sambuc #define MII16_HSSI_LOOP 0x8000 /* RW: [cPCI] LOOP TX into RX */ 2727eb99bdaSLionel Sambuc #define MII16_HSSI_MODEM 0x003F /* TA+CA+LA+LB+LC+TM */ 2737eb99bdaSLionel Sambuc 2747eb99bdaSLionel Sambuc /* MII register 16 bits for DS3 */ 2757eb99bdaSLionel Sambuc #define MII16_DS3_ZERO 0x0001 /* RW: short/long cables */ 2767eb99bdaSLionel Sambuc #define MII16_DS3_TRLBK 0x0002 /* RW: loop towards host */ 2777eb99bdaSLionel Sambuc #define MII16_DS3_LNLBK 0x0004 /* RW: loop towards net */ 2787eb99bdaSLionel Sambuc #define MII16_DS3_RAIS 0x0008 /* RO: LIU receive AIS (depr) */ 2797eb99bdaSLionel Sambuc #define MII16_DS3_TAIS 0x0010 /* RW: LIU transmit AIS (depr) */ 2807eb99bdaSLionel Sambuc #define MII16_DS3_BIST 0x0020 /* RO: LIU QRSS patt match (depr) */ 2817eb99bdaSLionel Sambuc #define MII16_DS3_DLOS 0x0040 /* RO: LIU Digital LOS (depr) */ 2827eb99bdaSLionel Sambuc #define MII16_DS3_LED_BLU 0x0080 /* RW: lower right - blue */ 2837eb99bdaSLionel Sambuc #define MII16_DS3_LED_YEL 0x0100 /* RW: lower left - yellow */ 2847eb99bdaSLionel Sambuc #define MII16_DS3_LED_RED 0x0200 /* RW: upper right - red */ 2857eb99bdaSLionel Sambuc #define MII16_DS3_LED_GRN 0x0400 /* RW: upper left - green */ 2867eb99bdaSLionel Sambuc #define MII16_DS3_FIFO 0x0800 /* RW: reset fifos */ 2877eb99bdaSLionel Sambuc #define MII16_DS3_CRC32 0x1000 /* RW: CRC length 16/32 */ 2887eb99bdaSLionel Sambuc #define MII16_DS3_SCRAM 0x2000 /* RW: payload scrambler */ 2897eb99bdaSLionel Sambuc #define MII16_DS3_POLY 0x4000 /* RW: 1=Larse, 0=DigLink|Kentrox */ 2907eb99bdaSLionel Sambuc #define MII16_DS3_FRAME 0x8000 /* RW: 1=stop txframe pulses */ 2917eb99bdaSLionel Sambuc 2927eb99bdaSLionel Sambuc /* MII register 16 bits for SSI */ 2937eb99bdaSLionel Sambuc #define MII16_SSI_DTR 0x0001 /* RW: DTR host->modem */ 2947eb99bdaSLionel Sambuc #define MII16_SSI_DSR 0x0002 /* RO: DSR modem->host */ 2957eb99bdaSLionel Sambuc #define MII16_SSI_RTS 0x0004 /* RW: RTS host->modem */ 2967eb99bdaSLionel Sambuc #define MII16_SSI_CTS 0x0008 /* RO: CTS modem->host */ 2977eb99bdaSLionel Sambuc #define MII16_SSI_DCD 0x0010 /* RW: DCD modem<->host */ 2987eb99bdaSLionel Sambuc #define MII16_SSI_RI 0x0020 /* RO: RI modem->host */ 2997eb99bdaSLionel Sambuc #define MII16_SSI_CRC32 0x0040 /* RW: CRC length 16/32 */ 3007eb99bdaSLionel Sambuc #define MII16_SSI_LED_LL 0x0080 /* RW: lower left - green */ 3017eb99bdaSLionel Sambuc #define MII16_SSI_LED_LR 0x0100 /* RW: lower right - green */ 3027eb99bdaSLionel Sambuc #define MII16_SSI_LED_UL 0x0200 /* RW: upper left - green */ 3037eb99bdaSLionel Sambuc #define MII16_SSI_LED_UR 0x0400 /* RW: upper right - red */ 3047eb99bdaSLionel Sambuc #define MII16_SSI_FIFO 0x0800 /* RW: reset fifos */ 3057eb99bdaSLionel Sambuc #define MII16_SSI_LL 0x1000 /* RW: LL: host->modem */ 3067eb99bdaSLionel Sambuc #define MII16_SSI_RL 0x2000 /* RW: RL: host->modem */ 3077eb99bdaSLionel Sambuc #define MII16_SSI_TM 0x4000 /* RO: TM: modem->host */ 3087eb99bdaSLionel Sambuc #define MII16_SSI_LOOP 0x8000 /* RW: Loop at ext conn */ 3097eb99bdaSLionel Sambuc #define MII16_SSI_MODEM 0x703F /* DTR+DSR+RTS+CTS+DCD+RI+LL+RL+TM */ 3107eb99bdaSLionel Sambuc 3117eb99bdaSLionel Sambuc /* Mii register 17 has the SSI cable bits */ 3127eb99bdaSLionel Sambuc #define MII17_SSI_CABLE_SHIFT 3 /* shift to get cable type */ 3137eb99bdaSLionel Sambuc #define MII17_SSI_CABLE_MASK 0x0038 /* RO: mask to get cable type */ 3147eb99bdaSLionel Sambuc #define MII17_SSI_PRESCALE 0x0040 /* RW: divide by: 0=16; 1=512 */ 3157eb99bdaSLionel Sambuc #define MII17_SSI_ITF 0x0100 /* RW: fill with: 0=flags; 1=ones */ 3167eb99bdaSLionel Sambuc #define MII17_SSI_NRZI 0x0400 /* RW: coding: NRZ= 0; NRZI=1 */ 3177eb99bdaSLionel Sambuc 3187eb99bdaSLionel Sambuc /* MII register 16 bits for T1/E1 */ 3197eb99bdaSLionel Sambuc #define MII16_T1_UNUSED1 0x0001 3207eb99bdaSLionel Sambuc #define MII16_T1_INVERT 0x0002 /* RW: invert data (for SF/AMI) */ 3217eb99bdaSLionel Sambuc #define MII16_T1_XOE 0x0004 /* RW: TX Output Enable; 0=disable */ 3227eb99bdaSLionel Sambuc #define MII16_T1_RST 0x0008 /* RW: Bt8370 chip reset */ 3237eb99bdaSLionel Sambuc #define MII16_T1_Z 0x0010 /* RW: output impedance T1=1 E1=0 */ 3247eb99bdaSLionel Sambuc #define MII16_T1_INTR 0x0020 /* RO: interrupt from Bt8370 */ 3257eb99bdaSLionel Sambuc #define MII16_T1_ONESEC 0x0040 /* RO: one second square wave */ 3267eb99bdaSLionel Sambuc #define MII16_T1_LED_BLU 0x0080 /* RW: lower right - blue */ 3277eb99bdaSLionel Sambuc #define MII16_T1_LED_YEL 0x0100 /* RW: lower left - yellow */ 3287eb99bdaSLionel Sambuc #define MII16_T1_LED_RED 0x0200 /* RW: upper right - red */ 3297eb99bdaSLionel Sambuc #define MII16_T1_LED_GRN 0x0400 /* RW: upper left - green */ 3307eb99bdaSLionel Sambuc #define MII16_T1_FIFO 0x0800 /* RW: reset fifos */ 3317eb99bdaSLionel Sambuc #define MII16_T1_CRC32 0x1000 /* RW: CRC length 16/32 */ 3327eb99bdaSLionel Sambuc #define MII16_T1_UNUSED2 0xE000 3337eb99bdaSLionel Sambuc 3347eb99bdaSLionel Sambuc /* T3 framer: RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ 3357eb99bdaSLionel Sambuc #define T3CSR_STAT0 0x00 /* RO: real-time status */ 3367eb99bdaSLionel Sambuc #define T3CSR_CTL1 0x01 /* RW: global control bits */ 3377eb99bdaSLionel Sambuc #define T3CSR_FEBE 0x02 /* RC: Far End Block Error Counter */ 3387eb99bdaSLionel Sambuc #define T3CSR_CERR 0x03 /* RC: C-bit Parity Error Counter */ 3397eb99bdaSLionel Sambuc #define T3CSR_PERR 0x04 /* RC: P-bit Parity Error Counter */ 3407eb99bdaSLionel Sambuc #define T3CSR_TX_FEAC 0x05 /* RW: Far End Alarm & Control */ 3417eb99bdaSLionel Sambuc #define T3CSR_RX_FEAC 0x06 /* RO: Far End Alarm & Control */ 3427eb99bdaSLionel Sambuc #define T3CSR_STAT7 0x07 /* RL: latched real-time status */ 3437eb99bdaSLionel Sambuc #define T3CSR_CTL8 0x08 /* RW: extended global ctl bits */ 3447eb99bdaSLionel Sambuc #define T3CSR_STAT9 0x09 /* RL: extended status bits */ 3457eb99bdaSLionel Sambuc #define T3CSR_FERR 0x0A /* RC: F-bit Error Counter */ 3467eb99bdaSLionel Sambuc #define T3CSR_MERR 0x0B /* RC: M-bit Error Counter */ 3477eb99bdaSLionel Sambuc #define T3CSR_CTL12 0x0C /* RW: more extended ctl bits */ 3487eb99bdaSLionel Sambuc #define T3CSR_DBL_FEAC 0x0D /* RW: TX double FEAC */ 3497eb99bdaSLionel Sambuc #define T3CSR_CTL14 0x0E /* RW: even more extended ctl bits */ 3507eb99bdaSLionel Sambuc #define T3CSR_FEAC_STK 0x0F /* RO: RX FEAC stack */ 3517eb99bdaSLionel Sambuc #define T3CSR_STAT16 0x10 /* RL: extended latched status */ 3527eb99bdaSLionel Sambuc #define T3CSR_INTEN 0x11 /* RW: interrupt enable */ 3537eb99bdaSLionel Sambuc #define T3CSR_CVLO 0x12 /* RC: coding violation cntr LSB */ 3547eb99bdaSLionel Sambuc #define T3CSR_CVHI 0x13 /* RC: coding violation cntr MSB */ 3557eb99bdaSLionel Sambuc #define T3CSR_CTL20 0x14 /* RW: yet more extended ctl bits */ 3567eb99bdaSLionel Sambuc 3577eb99bdaSLionel Sambuc #define CTL1_XTX 0x01 /* Transmit X-bit value */ 3587eb99bdaSLionel Sambuc #define CTL1_3LOOP 0x02 /* framer loop back */ 3597eb99bdaSLionel Sambuc #define CTL1_SER 0x04 /* SERial interface selected */ 3607eb99bdaSLionel Sambuc #define CTL1_M13MODE 0x08 /* M13 frame format */ 3617eb99bdaSLionel Sambuc #define CTL1_TXIDL 0x10 /* Transmit Idle signal */ 3627eb99bdaSLionel Sambuc #define CTL1_ENAIS 0x20 /* Enable AIS upon LOS */ 3637eb99bdaSLionel Sambuc #define CTL1_TXAIS 0x40 /* Transmit Alarm Indication Sig */ 3647eb99bdaSLionel Sambuc #define CTL1_NOFEBE 0x80 /* No Far End Block Errors */ 3657eb99bdaSLionel Sambuc 3667eb99bdaSLionel Sambuc #define CTL5_EMODE 0x80 /* rev B Extended features enabled */ 3677eb99bdaSLionel Sambuc #define CTL5_START 0x40 /* transmit the FEAC msg now */ 3687eb99bdaSLionel Sambuc 3697eb99bdaSLionel Sambuc #define CTL8_FBEC 0x80 /* F-Bit Error Count control */ 3707eb99bdaSLionel Sambuc #define CTL8_TBLU 0x20 /* Transmit Blue signal */ 3717eb99bdaSLionel Sambuc #define CTL8_OUT_DIS 0x10 /* Output Disable */ 3727eb99bdaSLionel Sambuc 3737eb99bdaSLionel Sambuc #define STAT9_SEF 0x80 /* Severely Errored Frame */ 3747eb99bdaSLionel Sambuc #define STAT9_RBLU 0x20 /* Receive Blue signal */ 3757eb99bdaSLionel Sambuc 3767eb99bdaSLionel Sambuc #define CTL12_RTPLLEN 0x80 /* Rx-to-Tx Payload Lpbk Lock ENbl */ 3777eb99bdaSLionel Sambuc #define CTL12_RTPLOOP 0x40 /* Rx-to-Tx Payload Loopback */ 3787eb99bdaSLionel Sambuc #define CTL12_DLCB1 0x08 /* Data Link C-Bits forced to 1 */ 3797eb99bdaSLionel Sambuc #define CTL12_C21 0x04 /* C2 forced to 1 */ 3807eb99bdaSLionel Sambuc #define CTL12_MCB1 0x02 /* Most C-Bits forced to 1 */ 3817eb99bdaSLionel Sambuc 3827eb99bdaSLionel Sambuc #define CTL13_DFEXEC 0x40 /* Execute Double FEAC */ 3837eb99bdaSLionel Sambuc 3847eb99bdaSLionel Sambuc #define CTL14_FEAC10 0x80 /* Transmit FEAC word 10 times */ 3857eb99bdaSLionel Sambuc #define CTL14_RGCEN 0x20 /* Receive Gapped Clock Out Enbl */ 3867eb99bdaSLionel Sambuc #define CTL14_TGCEN 0x10 /* Timing Gen Gapped Clk Out Enbl */ 3877eb99bdaSLionel Sambuc 3887eb99bdaSLionel Sambuc #define FEAC_STK_MORE 0x80 /* FEAC stack has more FEACs */ 3897eb99bdaSLionel Sambuc #define FEAC_STK_VALID 0x40 /* FEAC stack is valid */ 3907eb99bdaSLionel Sambuc #define FEAC_STK_FEAC 0x3F /* FEAC stack FEAC data */ 3917eb99bdaSLionel Sambuc 3927eb99bdaSLionel Sambuc #define STAT16_XERR 0x01 /* X-bit Error */ 3937eb99bdaSLionel Sambuc #define STAT16_SEF 0x02 /* Severely Errored Frame */ 3947eb99bdaSLionel Sambuc #define STAT16_RTLOC 0x04 /* Rx/Tx Loss Of Clock */ 3957eb99bdaSLionel Sambuc #define STAT16_FEAC 0x08 /* new FEAC msg */ 3967eb99bdaSLionel Sambuc #define STAT16_RIDL 0x10 /* channel IDLe signal */ 3977eb99bdaSLionel Sambuc #define STAT16_RAIS 0x20 /* Alarm Indication Signal */ 3987eb99bdaSLionel Sambuc #define STAT16_ROOF 0x40 /* Out Of Frame sync */ 3997eb99bdaSLionel Sambuc #define STAT16_RLOS 0x80 /* Loss Of Signal */ 4007eb99bdaSLionel Sambuc 4017eb99bdaSLionel Sambuc #define CTL20_CVEN 0x01 /* Coding Violation Counter Enbl */ 4027eb99bdaSLionel Sambuc 4037eb99bdaSLionel Sambuc /* T1.107 Bit Oriented C-Bit Parity Far End Alarm Control and Status codes */ 4047eb99bdaSLionel Sambuc #define T3BOP_OOF 0x00 /* Yellow alarm status */ 4057eb99bdaSLionel Sambuc #define T3BOP_LINE_UP 0x07 /* line loopback activate */ 4067eb99bdaSLionel Sambuc #define T3BOP_LINE_DOWN 0x1C /* line loopback deactivate */ 4077eb99bdaSLionel Sambuc #define T3BOP_LOOP_DS3 0x1B /* loopback full DS3 */ 4087eb99bdaSLionel Sambuc #define T3BOP_IDLE 0x1A /* IDLE alarm status */ 4097eb99bdaSLionel Sambuc #define T3BOP_AIS 0x16 /* AIS alarm status */ 4107eb99bdaSLionel Sambuc #define T3BOP_LOS 0x0E /* LOS alarm status */ 4117eb99bdaSLionel Sambuc 4127eb99bdaSLionel Sambuc /* T1E1 regs; RW=Read/Write; RO=Read-Only; RC=Read/Clr; WO=Write-Only */ 4137eb99bdaSLionel Sambuc #define Bt8370_DID 0x000 /* RO: Device ID */ 4147eb99bdaSLionel Sambuc #define Bt8370_CR0 0x001 /* RW; Primary Control Register */ 4157eb99bdaSLionel Sambuc #define Bt8370_JAT_CR 0x002 /* RW: Jitter Attenuator CR */ 4167eb99bdaSLionel Sambuc #define Bt8370_IRR 0x003 /* RO: Interrupt Request Reg */ 4177eb99bdaSLionel Sambuc #define Bt8370_ISR7 0x004 /* RC: Alarm 1 Interrupt Status */ 4187eb99bdaSLionel Sambuc #define Bt8370_ISR6 0x005 /* RC: Alarm 2 Interrupt Status */ 4197eb99bdaSLionel Sambuc #define Bt8370_ISR5 0x006 /* RC: Error Interrupt Status */ 4207eb99bdaSLionel Sambuc #define Bt8370_ISR4 0x007 /* RC; Cntr Ovfl Interrupt Status */ 4217eb99bdaSLionel Sambuc #define Bt8370_ISR3 0x008 /* RC: Timer Interrupt Status */ 4227eb99bdaSLionel Sambuc #define Bt8370_ISR2 0x009 /* RC: Data Link 1 Int Status */ 4237eb99bdaSLionel Sambuc #define Bt8370_ISR1 0x00A /* RC: Data Link 2 Int Status */ 4247eb99bdaSLionel Sambuc #define Bt8370_ISR0 0x00B /* RC: Pattrn Interrupt Status */ 4257eb99bdaSLionel Sambuc #define Bt8370_IER7 0x00C /* RW: Alarm 1 Interrupt Enable */ 4267eb99bdaSLionel Sambuc #define Bt8370_IER6 0x00D /* RW: Alarm 2 Interrupt Enable */ 4277eb99bdaSLionel Sambuc #define Bt8370_IER5 0x00E /* RW: Error Interrupt Enable */ 4287eb99bdaSLionel Sambuc #define Bt8370_IER4 0x00F /* RW: Cntr Ovfl Interrupt Enable */ 4297eb99bdaSLionel Sambuc 4307eb99bdaSLionel Sambuc #define Bt8370_IER3 0x010 /* RW: Timer Interrupt Enable */ 4317eb99bdaSLionel Sambuc #define Bt8370_IER2 0x011 /* RW: Data Link 1 Int Enable */ 4327eb99bdaSLionel Sambuc #define Bt8370_IER1 0x012 /* RW: Data Link 2 Int Enable */ 4337eb99bdaSLionel Sambuc #define Bt8370_IER0 0x013 /* RW: Pattern Interrupt Enable */ 4347eb99bdaSLionel Sambuc #define Bt8370_LOOP 0x014 /* RW: Loopback Config Reg */ 4357eb99bdaSLionel Sambuc #define Bt8370_DL3_TS 0x015 /* RW: External Data Link Channel */ 4367eb99bdaSLionel Sambuc #define Bt8370_DL3_BIT 0x016 /* RW: External Data Link Bit */ 4377eb99bdaSLionel Sambuc #define Bt8370_FSTAT 0x017 /* RO: Offline Framer Status */ 4387eb99bdaSLionel Sambuc #define Bt8370_PIO 0x018 /* RW: Programmable Input/Output */ 4397eb99bdaSLionel Sambuc #define Bt8370_POE 0x019 /* RW: Programmable Output Enable */ 4407eb99bdaSLionel Sambuc #define Bt8370_CMUX 0x01A /* RW: Clock Input Mux */ 4417eb99bdaSLionel Sambuc #define Bt8370_TMUX 0x01B /* RW: Test Mux Config */ 4427eb99bdaSLionel Sambuc #define Bt8370_TEST 0x01C /* RW: Test Config */ 4437eb99bdaSLionel Sambuc 4447eb99bdaSLionel Sambuc #define Bt8370_LIU_CR 0x020 /* RW: Line Intf Unit Config Reg */ 4457eb99bdaSLionel Sambuc #define Bt8370_RSTAT 0x021 /* RO; Receive LIU Status */ 4467eb99bdaSLionel Sambuc #define Bt8370_RLIU_CR 0x022 /* RW: Receive LIU Config */ 4477eb99bdaSLionel Sambuc #define Bt8370_LPF 0x023 /* RW: RPLL Low Pass Filter */ 4487eb99bdaSLionel Sambuc #define Bt8370_VGA_MAX 0x024 /* RW: Variable Gain Amplifier Max */ 4497eb99bdaSLionel Sambuc #define Bt8370_EQ_DAT 0x025 /* RW: Equalizer Coeff Data Reg */ 4507eb99bdaSLionel Sambuc #define Bt8370_EQ_PTR 0x026 /* RW: Equzlizer Coeff Table Ptr */ 4517eb99bdaSLionel Sambuc #define Bt8370_DSLICE 0x027 /* RW: Data Slicer Threshold */ 4527eb99bdaSLionel Sambuc #define Bt8370_EQ_OUT 0x028 /* RW: Equalizer Output Levels */ 4537eb99bdaSLionel Sambuc #define Bt8370_VGA 0x029 /* RO: Variable Gain Ampl Status */ 4547eb99bdaSLionel Sambuc #define Bt8370_PRE_EQ 0x02A /* RW: Pre-Equalizer */ 4557eb99bdaSLionel Sambuc 4567eb99bdaSLionel Sambuc #define Bt8370_COEFF0 0x030 /* RO: LMS Adj Eq Coeff Status */ 4577eb99bdaSLionel Sambuc #define Bt8370_GAIN0 0x038 /* RW: Equalizer Gain Thresh */ 4587eb99bdaSLionel Sambuc #define Bt8370_GAIN1 0x039 /* RW: Equalizer Gain Thresh */ 4597eb99bdaSLionel Sambuc #define Bt8370_GAIN2 0x03A /* RW: Equalizer Gain Thresh */ 4607eb99bdaSLionel Sambuc #define Bt8370_GAIN3 0x03B /* RW: Equalizer Gain Thresh */ 4617eb99bdaSLionel Sambuc #define Bt8370_GAIN4 0x03C /* RW: Equalizer Gain Thresh */ 4627eb99bdaSLionel Sambuc 4637eb99bdaSLionel Sambuc #define Bt8370_RCR0 0x040 /* RW: Rx Configuration */ 4647eb99bdaSLionel Sambuc #define Bt8370_RPATT 0x041 /* RW: Rx Test Pattern Config */ 4657eb99bdaSLionel Sambuc #define Bt8370_RLB 0x042 /* RW: Rx Loopback Code Detr Conf */ 4667eb99bdaSLionel Sambuc #define Bt8370_LBA 0x043 /* RW: Loopback Activate Code Patt */ 4677eb99bdaSLionel Sambuc #define Bt8370_LBD 0x044 /* RW: Loopback Deact Code Patt */ 4687eb99bdaSLionel Sambuc #define Bt8370_RALM 0x045 /* RW: Rx Alarm Signal Config */ 4697eb99bdaSLionel Sambuc #define Bt8370_LATCH 0x046 /* RW: Alarm/Err/Cntr Latch Config */ 4707eb99bdaSLionel Sambuc #define Bt8370_ALM1 0x047 /* RO: Alarm 1 Status */ 4717eb99bdaSLionel Sambuc #define Bt8370_ALM2 0x048 /* RO: Alarm 2 Status */ 4727eb99bdaSLionel Sambuc #define Bt8370_ALM3 0x049 /* RO: Alarm 3 Status */ 4737eb99bdaSLionel Sambuc 4747eb99bdaSLionel Sambuc #define Bt8370_FERR_LO 0x050 /* RC: Framing Bit Error Cntr LSB */ 4757eb99bdaSLionel Sambuc #define Bt8370_FERR_HI 0x051 /* RC: Framing Bit Error Cntr MSB */ 4767eb99bdaSLionel Sambuc #define Bt8370_CRC_LO 0x052 /* RC: CRC Error Counter LSB */ 4777eb99bdaSLionel Sambuc #define Bt8370_CRC_HI 0x053 /* RC: CRC Error Counter MSB */ 4787eb99bdaSLionel Sambuc #define Bt8370_LCV_LO 0x054 /* RC: Line Code Viol Counter LSB */ 4797eb99bdaSLionel Sambuc #define Bt8370_LCV_HI 0x055 /* RC: Line Code Viol Counter MSB */ 4807eb99bdaSLionel Sambuc #define Bt8370_FEBE_LO 0x056 /* RC: Far End Block Err Cntr LSB */ 4817eb99bdaSLionel Sambuc #define Bt8370_FEBE_HI 0x057 /* RC: Far End Block Err Cntr MSB */ 4827eb99bdaSLionel Sambuc #define Bt8370_BERR_LO 0x058 /* RC: PRBS Bit Error Counter LSB */ 4837eb99bdaSLionel Sambuc #define Bt8370_BERR_HI 0x059 /* RC: PRBS Bit Error Counter MSB */ 4847eb99bdaSLionel Sambuc #define Bt8370_AERR 0x05A /* RC: SEF/LOF/COFA counter */ 4857eb99bdaSLionel Sambuc #define Bt8370_RSA4 0x05B /* RO: Rx Sa4 Byte Buffer */ 4867eb99bdaSLionel Sambuc #define Bt8370_RSA5 0x05C /* RO: Rx Sa5 Byte Buffer */ 4877eb99bdaSLionel Sambuc #define Bt8370_RSA6 0x05D /* RO: Rx Sa6 Byte Buffer */ 4887eb99bdaSLionel Sambuc #define Bt8370_RSA7 0x05E /* RO: Rx Sa7 Byte Buffer */ 4897eb99bdaSLionel Sambuc #define Bt8370_RSA8 0x05F /* RO: Rx Sa8 Byte Buffer */ 4907eb99bdaSLionel Sambuc 4917eb99bdaSLionel Sambuc #define Bt8370_SHAPE0 0x060 /* RW: Tx Pulse Shape Config */ 4927eb99bdaSLionel Sambuc #define Bt8370_TLIU_CR 0x068 /* RW: Tx LIU Config Reg */ 4937eb99bdaSLionel Sambuc 4947eb99bdaSLionel Sambuc #define Bt8370_TCR0 0x070 /* RW: Tx Framer Config */ 4957eb99bdaSLionel Sambuc #define Bt8370_TCR1 0x071 /* RW: Txter Configuration */ 4967eb99bdaSLionel Sambuc #define Bt8370_TFRM 0x072 /* RW: Tx Frame Format */ 4977eb99bdaSLionel Sambuc #define Bt8370_TERROR 0x073 /* RW: Tx Error Insert */ 4987eb99bdaSLionel Sambuc #define Bt8370_TMAN 0x074 /* RW: Tx Manual Sa/FEBE Config */ 4997eb99bdaSLionel Sambuc #define Bt8370_TALM 0x075 /* RW: Tx Alarm Signal Config */ 5007eb99bdaSLionel Sambuc #define Bt8370_TPATT 0x076 /* RW: Tx Test Pattern Config */ 5017eb99bdaSLionel Sambuc #define Bt8370_TLB 0x077 /* RW: Tx Inband Loopback Config */ 5027eb99bdaSLionel Sambuc #define Bt8370_LBP 0x078 /* RW: Tx Inband Loopback Patt */ 5037eb99bdaSLionel Sambuc #define Bt8370_TSA4 0x07B /* RW: Tx Sa4 Byte Buffer */ 5047eb99bdaSLionel Sambuc #define Bt8370_TSA5 0x07C /* RW: Tx Sa5 Byte Buffer */ 5057eb99bdaSLionel Sambuc #define Bt8370_TSA6 0x07D /* RW: Tx Sa6 Byte Buffer */ 5067eb99bdaSLionel Sambuc #define Bt8370_TSA7 0x07E /* RW: Tx Sa7 Byte Buffer */ 5077eb99bdaSLionel Sambuc #define Bt8370_TSA8 0x07F /* RW: Tx Sa8 Byte Buffer */ 5087eb99bdaSLionel Sambuc 5097eb99bdaSLionel Sambuc #define Bt8370_CLAD_CR 0x090 /* RW: Clock Rate Adapter Config */ 5107eb99bdaSLionel Sambuc #define Bt8370_CSEL 0x091 /* RW: CLAD Frequency Select */ 5117eb99bdaSLionel Sambuc #define Bt8370_CPHASE 0x092 /* RW: CLAD Phase Det Scale Factor */ 5127eb99bdaSLionel Sambuc #define Bt8370_CTEST 0x093 /* RW: CLAD Test */ 5137eb99bdaSLionel Sambuc 5147eb99bdaSLionel Sambuc #define Bt8370_BOP 0x0A0 /* RW: Bit Oriented Protocol Xcvr */ 5157eb99bdaSLionel Sambuc #define Bt8370_TBOP 0x0A1 /* RW: Tx BOP Codeword */ 5167eb99bdaSLionel Sambuc #define Bt8370_RBOP 0x0A2 /* RO; Rx BOP Codeword */ 5177eb99bdaSLionel Sambuc #define Bt8370_BOP_STAT 0x0A3 /* RO: BOP Status */ 5187eb99bdaSLionel Sambuc #define Bt8370_DL1_TS 0x0A4 /* RW: DL1 Time Slot Enable */ 5197eb99bdaSLionel Sambuc #define Bt8370_DL1_BIT 0x0A5 /* RW: DL1 Bit Enable */ 5207eb99bdaSLionel Sambuc #define Bt8370_DL1_CTL 0x0A6 /* RW: DL1 Control */ 5217eb99bdaSLionel Sambuc #define Bt8370_RDL1_FFC 0x0A7 /* RW: RDL1 FIFO Fill Control */ 5227eb99bdaSLionel Sambuc #define Bt8370_RDL1 0x0A8 /* RO: RDL1 FIFO */ 5237eb99bdaSLionel Sambuc #define Bt8370_RDL1_STAT 0x0A9 /* RO: RDL1 Status */ 5247eb99bdaSLionel Sambuc #define Bt8370_PRM 0x0AA /* RW: Performance Report Message */ 5257eb99bdaSLionel Sambuc #define Bt8370_TDL1_FEC 0x0AB /* RW: TDL1 FIFO Empty Control */ 5267eb99bdaSLionel Sambuc #define Bt8370_TDL1_EOM 0x0AC /* WO: TDL1 End Of Message Control */ 5277eb99bdaSLionel Sambuc #define Bt8370_TDL1 0x0AD /* RW: TDL1 FIFO */ 5287eb99bdaSLionel Sambuc #define Bt8370_TDL1_STAT 0x0AE /* RO: TDL1 Status */ 5297eb99bdaSLionel Sambuc #define Bt8370_DL2_TS 0x0AF /* RW: DL2 Time Slot Enable */ 5307eb99bdaSLionel Sambuc 5317eb99bdaSLionel Sambuc #define Bt8370_DL2_BIT 0x0B0 /* RW: DL2 Bit Enable */ 5327eb99bdaSLionel Sambuc #define Bt8370_DL2_CTL 0x0B1 /* RW: DL2 Control */ 5337eb99bdaSLionel Sambuc #define Bt8370_RDL2_FFC 0x0B2 /* RW: RDL2 FIFO Fill Control */ 5347eb99bdaSLionel Sambuc #define Bt8370_RDL2 0x0B3 /* RO: RDL2 FIFO */ 5357eb99bdaSLionel Sambuc #define Bt8370_RDL2_STAT 0x0B4 /* RO: RDL2 Status */ 5367eb99bdaSLionel Sambuc #define Bt8370_TDL2_FEC 0x0B6 /* RW: TDL2 FIFO Empty Control */ 5377eb99bdaSLionel Sambuc #define Bt8370_TDL2_EOM 0x0B7 /* WO; TDL2 End Of Message Control */ 5387eb99bdaSLionel Sambuc #define Bt8370_TDL2 0x0B8 /* RW: TDL2 FIFO */ 5397eb99bdaSLionel Sambuc #define Bt8370_TDL2_STAT 0x0B9 /* RO: TDL2 Status */ 5407eb99bdaSLionel Sambuc #define Bt8370_DL_TEST1 0x0BA /* RW: DLINK Test Config */ 5417eb99bdaSLionel Sambuc #define Bt8370_DL_TEST2 0x0BB /* RW: DLINK Test Status */ 5427eb99bdaSLionel Sambuc #define Bt8370_DL_TEST3 0x0BC /* RW: DLINK Test Status */ 5437eb99bdaSLionel Sambuc #define Bt8370_DL_TEST4 0x0BD /* RW: DLINK Test Control */ 5447eb99bdaSLionel Sambuc #define Bt8370_DL_TEST5 0x0BE /* RW: DLINK Test Control */ 5457eb99bdaSLionel Sambuc 5467eb99bdaSLionel Sambuc #define Bt8370_SBI_CR 0x0D0 /* RW: System Bus Interface Config */ 5477eb99bdaSLionel Sambuc #define Bt8370_RSB_CR 0x0D1 /* RW: Rx System Bus Config */ 5487eb99bdaSLionel Sambuc #define Bt8370_RSYNC_BIT 0x0D2 /* RW: Rx System Bus Sync Bit Offs */ 5497eb99bdaSLionel Sambuc #define Bt8370_RSYNC_TS 0x0D3 /* RW: Rx System Bus Sync TS Offs */ 5507eb99bdaSLionel Sambuc #define Bt8370_TSB_CR 0x0D4 /* RW: Tx System Bus Config */ 5517eb99bdaSLionel Sambuc #define Bt8370_TSYNC_BIT 0x0D5 /* RW: Tx System Bus Sync Bit OFfs */ 5527eb99bdaSLionel Sambuc #define Bt8370_TSYNC_TS 0x0D6 /* RW: Tx System Bus Sync TS Offs */ 5537eb99bdaSLionel Sambuc #define Bt8370_RSIG_CR 0x0D7 /* RW: Rx Siganalling Config */ 5547eb99bdaSLionel Sambuc #define Bt8370_RSYNC_FRM 0x0D8 /* RW: Sig Reinsertion Frame Offs */ 5557eb99bdaSLionel Sambuc #define Bt8370_SSTAT 0x0D9 /* RO: Slip Buffer Status */ 5567eb99bdaSLionel Sambuc #define Bt8370_STACK 0x0DA /* RO: Rx Signalling Stack */ 5577eb99bdaSLionel Sambuc #define Bt8370_RPHASE 0x0DB /* RO: RSLIP Phase Status */ 5587eb99bdaSLionel Sambuc #define Bt8370_TPHASE 0x0DC /* RO: TSLIP Phase Status */ 5597eb99bdaSLionel Sambuc #define Bt8370_PERR 0x0DD /* RO: RAM Parity Status */ 5607eb99bdaSLionel Sambuc 5617eb99bdaSLionel Sambuc #define Bt8370_SBCn 0x0E0 /* RW: System Bus Per-Channel Ctl */ 5627eb99bdaSLionel Sambuc #define Bt8370_TPCn 0x100 /* RW: Tx Per-Channel Control */ 5637eb99bdaSLionel Sambuc #define Bt8370_TSIGn 0x120 /* RW: Tx Signalling Buffer */ 5647eb99bdaSLionel Sambuc #define Bt8370_TSLIP_LOn 0x140 /* RW: Tx PCM Slip Buffer Lo */ 5657eb99bdaSLionel Sambuc #define Bt8370_TSLIP_HIn 0x160 /* RW: Tx PCM Slip Buffer Hi */ 5667eb99bdaSLionel Sambuc #define Bt8370_RPCn 0x180 /* RW: Rx Per-Channel Control */ 5677eb99bdaSLionel Sambuc #define Bt8370_RSIGn 0x1A0 /* RW: Rx Signalling Buffer */ 5687eb99bdaSLionel Sambuc #define Bt8370_RSLIP_LOn 0x1C0 /* RW: Rx PCM Slip Buffer Lo */ 5697eb99bdaSLionel Sambuc #define Bt8370_RSLIP_HIn 0x1E0 /* RW: Rx PCM Slip Buffer Hi */ 5707eb99bdaSLionel Sambuc 5717eb99bdaSLionel Sambuc /* Bt8370_LOOP (0x14) framer loopback control register bits */ 5727eb99bdaSLionel Sambuc #define LOOP_ANALOG 0x01 /* inward loop thru LIU */ 5737eb99bdaSLionel Sambuc #define LOOP_FRAMER 0x02 /* inward loop thru framer */ 5747eb99bdaSLionel Sambuc #define LOOP_LINE 0x04 /* outward loop thru LIU */ 5757eb99bdaSLionel Sambuc #define LOOP_PAYLOAD 0x08 /* outward loop of payload */ 5767eb99bdaSLionel Sambuc #define LOOP_DUAL 0x06 /* inward framer + outward line */ 5777eb99bdaSLionel Sambuc 5787eb99bdaSLionel Sambuc /* Bt8370_ALM1 (0x47) receiver alarm status register bits */ 5797eb99bdaSLionel Sambuc #define ALM1_SIGFRZ 0x01 /* Rx Signalling Freeze */ 5807eb99bdaSLionel Sambuc #define ALM1_RLOF 0x02 /* Rx loss of frame alignment */ 5817eb99bdaSLionel Sambuc #define ALM1_RLOS 0x04 /* Rx digital loss of signal */ 5827eb99bdaSLionel Sambuc #define ALM1_RALOS 0x08 /* Rx analog loss of signal */ 5837eb99bdaSLionel Sambuc #define ALM1_RAIS 0x10 /* Rx Alarm Indication Signal */ 5847eb99bdaSLionel Sambuc #define ALM1_RYEL 0x40 /* Rx Yellow alarm indication */ 5857eb99bdaSLionel Sambuc #define ALM1_RMYEL 0x80 /* Rx multiframe YELLOW alarm */ 5867eb99bdaSLionel Sambuc 5877eb99bdaSLionel Sambuc /* Bt8370_ALM3 (0x49) receive framer status register bits */ 5887eb99bdaSLionel Sambuc #define ALM3_FRED 0x04 /* Rx Out Of T1/FAS alignment */ 5897eb99bdaSLionel Sambuc #define ALM3_MRED 0x08 /* Rx Out Of MFAS alignment */ 5907eb99bdaSLionel Sambuc #define ALM3_SRED 0x10 /* Rx Out Of CAS alignment */ 5917eb99bdaSLionel Sambuc #define ALM3_SEF 0x20 /* Rx Severely Errored Frame */ 5927eb99bdaSLionel Sambuc #define ALM3_RMAIS 0x40 /* Rx TS16 AIS (CAS) */ 5937eb99bdaSLionel Sambuc 5947eb99bdaSLionel Sambuc /* Bt8370_TALM (0x75) transmit alarm control register bits */ 5957eb99bdaSLionel Sambuc #define TALM_TAIS 0x01 /* Tx Alarm Indication Signal */ 5967eb99bdaSLionel Sambuc #define TALM_TYEL 0x02 /* Tx Yellow alarm */ 5977eb99bdaSLionel Sambuc #define TALM_TMYEL 0x04 /* Tx Multiframe Yellow alarm */ 5987eb99bdaSLionel Sambuc #define TALM_AUTO_AIS 0x08 /* auto send AIS on LOS */ 5997eb99bdaSLionel Sambuc #define TALM_AUTO_YEL 0x10 /* auto send YEL on LOF */ 6007eb99bdaSLionel Sambuc #define TALM_AUTO_MYEL 0x20 /* auto send E1-Y16 on loss-of-CAS */ 6017eb99bdaSLionel Sambuc 6027eb99bdaSLionel Sambuc /* 8370 BOP (Bit Oriented Protocol) command fragments */ 6037eb99bdaSLionel Sambuc #define RBOP_OFF 0x00 /* BOP Rx disabled */ 6047eb99bdaSLionel Sambuc #define RBOP_25 0xE0 /* BOP Rx requires 25 BOPs */ 6057eb99bdaSLionel Sambuc #define TBOP_OFF 0x00 /* BOP Tx disabled */ 6067eb99bdaSLionel Sambuc #define TBOP_25 0x0B /* BOP Tx sends 25 BOPs */ 6077eb99bdaSLionel Sambuc #define TBOP_CONT 0x0F /* BOP Tx sends continuously */ 6087eb99bdaSLionel Sambuc 6097eb99bdaSLionel Sambuc /* T1.403 Bit-Oriented ESF Data-Link Message codes */ 6107eb99bdaSLionel Sambuc #define T1BOP_OOF 0x00 /* Yellow alarm status */ 6117eb99bdaSLionel Sambuc #define T1BOP_LINE_UP 0x07 /* line loopback activate */ 6127eb99bdaSLionel Sambuc #define T1BOP_LINE_DOWN 0x1C /* line loopback deactivate */ 6137eb99bdaSLionel Sambuc #define T1BOP_PAY_UP 0x0A /* payload loopback activate */ 6147eb99bdaSLionel Sambuc #define T1BOP_PAY_DOWN 0x19 /* payload loopback deactivate */ 6157eb99bdaSLionel Sambuc #define T1BOP_NET_UP 0x09 /* network loopback activate */ 6167eb99bdaSLionel Sambuc #define T1BOP_NET_DOWN 0x12 /* network loopback deactivate */ 6177eb99bdaSLionel Sambuc 6187eb99bdaSLionel Sambuc /* Unix & Linux reserve 16 device-private IOCTLs */ 6197eb99bdaSLionel Sambuc #if BSD 6207eb99bdaSLionel Sambuc # define LMCIOCGSTAT _IOWR('i', 240, struct status) 6217eb99bdaSLionel Sambuc # define LMCIOCGCFG _IOWR('i', 241, struct config) 6227eb99bdaSLionel Sambuc # define LMCIOCSCFG _IOW('i', 242, struct config) 6237eb99bdaSLionel Sambuc # define LMCIOCREAD _IOWR('i', 243, struct ioctl) 6247eb99bdaSLionel Sambuc # define LMCIOCWRITE _IOW('i', 244, struct ioctl) 6257eb99bdaSLionel Sambuc # define LMCIOCTL _IOWR('i', 245, struct ioctl) 6267eb99bdaSLionel Sambuc #endif 6277eb99bdaSLionel Sambuc 6287eb99bdaSLionel Sambuc struct iohdr /* all LMCIOCs begin with this */ 6297eb99bdaSLionel Sambuc { 6307eb99bdaSLionel Sambuc char ifname[IFNAMSIZ]; /* interface name, e.g. "lmc0" */ 6317eb99bdaSLionel Sambuc u_int32_t cookie; /* interface version number */ 6327eb99bdaSLionel Sambuc u_int16_t direction; /* missing in Linux IOCTL */ 6337eb99bdaSLionel Sambuc u_int16_t length; /* missing in Linux IOCTL */ 6347eb99bdaSLionel Sambuc struct iohdr *iohdr; /* missing in Linux IOCTL */ 6357eb99bdaSLionel Sambuc u_int32_t spare; /* pad this struct to **32 bytes** */ 6367eb99bdaSLionel Sambuc }; 6377eb99bdaSLionel Sambuc 6387eb99bdaSLionel Sambuc #define DIR_IO 0 6397eb99bdaSLionel Sambuc #define DIR_IOW 1 /* copy data user->kernel */ 6407eb99bdaSLionel Sambuc #define DIR_IOR 2 /* copy data kernel->user */ 6417eb99bdaSLionel Sambuc #define DIR_IOWR 3 /* copy data kernel<->user */ 6427eb99bdaSLionel Sambuc 6437eb99bdaSLionel Sambuc struct hssi_snmp 6447eb99bdaSLionel Sambuc { 6457eb99bdaSLionel Sambuc u_int16_t sigs; /* MII16_HSSI & MII16_HSSI_MODEM */ 6467eb99bdaSLionel Sambuc }; 6477eb99bdaSLionel Sambuc 6487eb99bdaSLionel Sambuc struct ssi_snmp 6497eb99bdaSLionel Sambuc { 6507eb99bdaSLionel Sambuc u_int16_t sigs; /* MII16_SSI & MII16_SSI_MODEM */ 6517eb99bdaSLionel Sambuc }; 6527eb99bdaSLionel Sambuc 6537eb99bdaSLionel Sambuc struct t3_snmp 6547eb99bdaSLionel Sambuc { 6557eb99bdaSLionel Sambuc u_int16_t febe; /* 8 bits - Far End Block err cnt */ 6567eb99bdaSLionel Sambuc u_int16_t lcv; /* 16 bits - BPV err cnt */ 6577eb99bdaSLionel Sambuc u_int16_t pcv; /* 8 bits - P-bit err cnt */ 6587eb99bdaSLionel Sambuc u_int16_t ccv; /* 8 bits - C-bit err cnt */ 6597eb99bdaSLionel Sambuc u_int16_t line; /* line status bit vector */ 6607eb99bdaSLionel Sambuc u_int16_t loop; /* loop status bit vector */ 6617eb99bdaSLionel Sambuc }; 6627eb99bdaSLionel Sambuc 6637eb99bdaSLionel Sambuc struct t1_snmp 6647eb99bdaSLionel Sambuc { 6657eb99bdaSLionel Sambuc u_int16_t prm[4]; /* T1.403 Performance Report Msg */ 6667eb99bdaSLionel Sambuc u_int16_t febe; /* 10 bits - E1 FAR CRC err cnt */ 6677eb99bdaSLionel Sambuc u_int16_t lcv; /* 16 bits - BPV + EXZ err cnt */ 6687eb99bdaSLionel Sambuc u_int16_t fe; /* 12 bits - Ft/Fs/FPS/FAS err cnt */ 6697eb99bdaSLionel Sambuc u_int16_t crc; /* 10 bits - CRC6/CRC4 err cnt */ 6707eb99bdaSLionel Sambuc u_int16_t line; /* line status bit vector */ 6717eb99bdaSLionel Sambuc u_int16_t loop; /* loop status bit vector */ 6727eb99bdaSLionel Sambuc }; 6737eb99bdaSLionel Sambuc 6747eb99bdaSLionel Sambuc /* SNMP trunk MIB Send codes */ 6757eb99bdaSLionel Sambuc #define TSEND_NORMAL 1 /* Send data (normal or looped) */ 6767eb99bdaSLionel Sambuc #define TSEND_LINE 2 /* Send 'line loopback activate' */ 6777eb99bdaSLionel Sambuc #define TSEND_PAYLOAD 3 /* Send 'payload loop activate' */ 6787eb99bdaSLionel Sambuc #define TSEND_RESET 4 /* Send 'loopback deactivate' */ 6797eb99bdaSLionel Sambuc #define TSEND_QRS 5 /* Send Quasi Random Signal */ 6807eb99bdaSLionel Sambuc 6817eb99bdaSLionel Sambuc /* ANSI T1.403 Performance Report Msg -- once a second from the far end */ 6827eb99bdaSLionel Sambuc #define T1PRM_FE 0x8000 /* Frame Sync Bit Error Event >= 1 */ 6837eb99bdaSLionel Sambuc #define T1PRM_SE 0x4000 /* Severely Err Framing Event >= 1 */ 6847eb99bdaSLionel Sambuc #define T1PRM_LB 0x2000 /* Payload Loopback Activated */ 6857eb99bdaSLionel Sambuc #define T1PRM_G1 0x1000 /* CRC Error Event = 1 */ 6867eb99bdaSLionel Sambuc #define T1PRM_R 0x0800 /* Reserved */ 6877eb99bdaSLionel Sambuc #define T1PRM_G2 0x0400 /* 1 < CRC Error Event <= 5 */ 6887eb99bdaSLionel Sambuc #define T1PRM_SEQ 0x0300 /* modulo 4 counter */ 6897eb99bdaSLionel Sambuc #define T1PRM_G3 0x0080 /* 5 < CRC Error Event <= 10 */ 6907eb99bdaSLionel Sambuc #define T1PRM_LV 0x0040 /* Line Code Violation Event >= 1 */ 6917eb99bdaSLionel Sambuc #define T1PRM_G4 0x0020 /* 10 < CRC Error Event <= 100 */ 6927eb99bdaSLionel Sambuc #define T1PRM_U 0x0018 /* Under study for synchronization */ 6937eb99bdaSLionel Sambuc #define T1PRM_G5 0x0004 /* 100 < CRC Error Event <= 319 */ 6947eb99bdaSLionel Sambuc #define T1PRM_SL 0x0002 /* Slip Event >= 1 */ 6957eb99bdaSLionel Sambuc #define T1PRM_G6 0x0001 /* CRC Error Event >= 320 */ 6967eb99bdaSLionel Sambuc 6977eb99bdaSLionel Sambuc /* SNMP Line Status */ 6987eb99bdaSLionel Sambuc #define TLINE_NORM 0x0001 /* no alarm present */ 6997eb99bdaSLionel Sambuc #define TLINE_RX_RAI 0x0002 /* receiving RAI = Yellow alarm */ 7007eb99bdaSLionel Sambuc #define TLINE_TX_RAI 0x0004 /* sending RAI = Yellow alarm */ 7017eb99bdaSLionel Sambuc #define TLINE_RX_AIS 0x0008 /* receiving AIS = blue alarm */ 7027eb99bdaSLionel Sambuc #define TLINE_TX_AIS 0x0010 /* sending AIS = blue alarm */ 7037eb99bdaSLionel Sambuc #define TLINE_LOF 0x0020 /* near end LOF = red alarm */ 7047eb99bdaSLionel Sambuc #define TLINE_LOS 0x0040 /* near end loss of Signal */ 7057eb99bdaSLionel Sambuc #define TLINE_LOOP 0x0080 /* near end is looped */ 7067eb99bdaSLionel Sambuc #define T1LINE_RX_TS16_AIS 0x0100 /* near end receiving TS16 AIS */ 7077eb99bdaSLionel Sambuc #define T1LINE_RX_TS16_LOMF 0x0200 /* near end sending TS16 LOMF */ 7087eb99bdaSLionel Sambuc #define T1LINE_TX_TS16_LOMF 0x0400 /* near end receiving TS16 LOMF */ 7097eb99bdaSLionel Sambuc #define T1LINE_RX_TEST 0x0800 /* near end receiving QRS Signal */ 7107eb99bdaSLionel Sambuc #define T1LINE_SEF 0x1000 /* near end severely errored frame */ 7117eb99bdaSLionel Sambuc #define T3LINE_RX_IDLE 0x0100 /* near end receiving IDLE signal */ 7127eb99bdaSLionel Sambuc #define T3LINE_SEF 0x0200 /* near end severely errored frame */ 7137eb99bdaSLionel Sambuc 7147eb99bdaSLionel Sambuc /* SNMP Loopback Status */ 7157eb99bdaSLionel Sambuc #define TLOOP_NONE 0x01 /* no loopback */ 7167eb99bdaSLionel Sambuc #define TLOOP_NEAR_PAYLOAD 0x02 /* near end payload loopback */ 7177eb99bdaSLionel Sambuc #define TLOOP_NEAR_LINE 0x04 /* near end line loopback */ 7187eb99bdaSLionel Sambuc #define TLOOP_NEAR_OTHER 0x08 /* near end looped somehow */ 7197eb99bdaSLionel Sambuc #define TLOOP_NEAR_INWARD 0x10 /* near end looped inward */ 7207eb99bdaSLionel Sambuc #define TLOOP_FAR_PAYLOAD 0x20 /* far end payload loopback */ 7217eb99bdaSLionel Sambuc #define TLOOP_FAR_LINE 0x40 /* far end line loopback */ 7227eb99bdaSLionel Sambuc 7237eb99bdaSLionel Sambuc /* event counters record interesting statistics */ 7247eb99bdaSLionel Sambuc struct cntrs 7257eb99bdaSLionel Sambuc { 7267eb99bdaSLionel Sambuc struct timeval reset_time; /* time when cntrs were reset */ 7277eb99bdaSLionel Sambuc u_int64_t ibytes; /* Rx bytes with good status */ 7287eb99bdaSLionel Sambuc u_int64_t obytes; /* Tx bytes */ 7297eb99bdaSLionel Sambuc u_int64_t ipackets; /* Rx packets with good status */ 7307eb99bdaSLionel Sambuc u_int64_t opackets; /* Tx packets */ 7317eb99bdaSLionel Sambuc u_int32_t ierrors; /* Rx packets with bad status */ 7327eb99bdaSLionel Sambuc u_int32_t oerrors; /* Tx packets with bad status */ 7337eb99bdaSLionel Sambuc u_int32_t idrops; /* Rx packets dropped by SW */ 7347eb99bdaSLionel Sambuc u_int32_t missed; /* Rx pkts missed: no DMA descs */ 7357eb99bdaSLionel Sambuc u_int32_t odrops; /* Tx packets dropped by SW */ 7367eb99bdaSLionel Sambuc u_int32_t fifo_over; /* Rx fifo overruns from DMA desc */ 7377eb99bdaSLionel Sambuc u_int32_t overruns; /* Rx fifo overruns from CSR */ 7387eb99bdaSLionel Sambuc u_int32_t fifo_under; /* Tx fifo underruns from DMA desc */ 7397eb99bdaSLionel Sambuc u_int32_t underruns; /* Rx fifo underruns from CSR */ 7407eb99bdaSLionel Sambuc u_int32_t fdl_pkts; /* Rx T1 Facility Data Link pkts */ 7417eb99bdaSLionel Sambuc u_int32_t crc_errs; /* Rx T1 frame CRC errors */ 7427eb99bdaSLionel Sambuc u_int32_t lcv_errs; /* Rx T1 T3 Line Coding Violation */ 7437eb99bdaSLionel Sambuc u_int32_t frm_errs; /* Rx T1 T3 Frame bit errors */ 7447eb99bdaSLionel Sambuc u_int32_t febe_errs; /* Rx T1 T3 Far End Bit Errors */ 7457eb99bdaSLionel Sambuc u_int32_t par_errs; /* Rx T3 P-bit parity errors */ 7467eb99bdaSLionel Sambuc u_int32_t cpar_errs; /* Rx T3 C-bit parity errors */ 7477eb99bdaSLionel Sambuc u_int32_t mfrm_errs; /* Rx T3 Multi-frame bit errors */ 7487eb99bdaSLionel Sambuc u_int32_t rxbuf; /* Rx out of packet buffers */ 7497eb99bdaSLionel Sambuc u_int32_t txdma; /* Tx out of DMA desciptors */ 7507eb99bdaSLionel Sambuc u_int32_t lck_watch; /* lock conflict in watchdog */ 7517eb99bdaSLionel Sambuc u_int32_t lck_intr; /* lock conflict in interrupt */ 7527eb99bdaSLionel Sambuc u_int32_t spare1; /* debugging temp */ 7537eb99bdaSLionel Sambuc u_int32_t spare2; /* debugging temp */ 7547eb99bdaSLionel Sambuc u_int32_t spare3; /* debugging temp */ 7557eb99bdaSLionel Sambuc u_int32_t spare4; /* debugging temp */ 7567eb99bdaSLionel Sambuc }; 7577eb99bdaSLionel Sambuc 7587eb99bdaSLionel Sambuc /* sc->status is the READ ONLY status of the card. */ 7597eb99bdaSLionel Sambuc /* Accessed using socket IO control calls or netgraph control messages. */ 7607eb99bdaSLionel Sambuc struct status 7617eb99bdaSLionel Sambuc { 7627eb99bdaSLionel Sambuc struct iohdr iohdr; /* common ioctl header */ 7637eb99bdaSLionel Sambuc u_int32_t card_type; /* PCI device number */ 7647eb99bdaSLionel Sambuc u_int16_t link_state; /* actual state: up, down, test */ 7657eb99bdaSLionel Sambuc u_int32_t tx_speed; /* measured TX bits/sec */ 7667eb99bdaSLionel Sambuc u_int32_t cable_type; /* SSI only: cable type */ 7677eb99bdaSLionel Sambuc u_int32_t time_slots; /* T1E1 only: actual TSs in use */ 7687eb99bdaSLionel Sambuc u_int32_t stack; /* actual line stack in use */ 7697eb99bdaSLionel Sambuc u_int32_t proto; /* actual line proto in use */ 7707eb99bdaSLionel Sambuc u_int32_t keep_alive; /* actual keep-alive status */ 7717eb99bdaSLionel Sambuc u_int32_t ticks; /* incremented by watchdog @ 1 Hz */ 7727eb99bdaSLionel Sambuc struct cntrs cntrs; /* event counters */ 7737eb99bdaSLionel Sambuc union 7747eb99bdaSLionel Sambuc { 7757eb99bdaSLionel Sambuc struct hssi_snmp hssi; /* data for RFC-???? HSSI MIB */ 7767eb99bdaSLionel Sambuc struct t3_snmp t3; /* data for RFC-2496 T3 MIB */ 7777eb99bdaSLionel Sambuc struct ssi_snmp ssi; /* data for RFC-1659 RS232 MIB */ 7787eb99bdaSLionel Sambuc struct t1_snmp t1; /* data for RFC-2495 T1 MIB */ 7797eb99bdaSLionel Sambuc } snmp; 7807eb99bdaSLionel Sambuc }; 7817eb99bdaSLionel Sambuc 7827eb99bdaSLionel Sambuc /* protocol stack codes */ 7837eb99bdaSLionel Sambuc #define STACK_NONE 0 /* not set fnobl */ 7847eb99bdaSLionel Sambuc #define STACK_RAWIP 1 /* driver yyyyy */ 7857eb99bdaSLionel Sambuc #define STACK_SPPP 2 /* fbsd, nbsd, obsd yyynn */ 7867eb99bdaSLionel Sambuc #define STACK_P2P 3 /* bsd/os nnnyn */ 7877eb99bdaSLionel Sambuc #define STACK_GEN_HDLC 4 /* linux nnnny */ 7887eb99bdaSLionel Sambuc #define STACK_SYNC_PPP 5 /* linux nnnny */ 7897eb99bdaSLionel Sambuc #define STACK_NETGRAPH 6 /* fbsd ynnnn */ 7907eb99bdaSLionel Sambuc 7917eb99bdaSLionel Sambuc /* line protocol codes */ 7927eb99bdaSLionel Sambuc #define PROTO_NONE 0 /* not set fnobl */ 7937eb99bdaSLionel Sambuc #define PROTO_IP_HDLC 1 /* raw IP4/6 pkts in HDLC yyyyy */ 7947eb99bdaSLionel Sambuc #define PROTO_PPP 2 /* Point-to-Point Protocol yyyyy */ 7957eb99bdaSLionel Sambuc #define PROTO_C_HDLC 3 /* Cisco HDLC Protocol yyyyy */ 7967eb99bdaSLionel Sambuc #define PROTO_FRM_RLY 4 /* Frame Relay Protocol ynnyy */ 7977eb99bdaSLionel Sambuc #define PROTO_ETH_HDLC 5 /* raw Ether pkts in HDLC nnnny */ 7987eb99bdaSLionel Sambuc #define PROTO_X25 6 /* X.25/LAPB Protocol nnnny */ 7997eb99bdaSLionel Sambuc 8007eb99bdaSLionel Sambuc /* oper_status codes (same as SNMP status codes) */ 8017eb99bdaSLionel Sambuc #define STATE_UP 1 /* may/will tx/rx pkts */ 8027eb99bdaSLionel Sambuc #define STATE_DOWN 2 /* can't/won't tx/rx pkts */ 8037eb99bdaSLionel Sambuc #define STATE_TEST 3 /* currently not used */ 8047eb99bdaSLionel Sambuc 8057eb99bdaSLionel Sambuc struct synth /* programmable oscillator params */ 8067eb99bdaSLionel Sambuc { 8077eb99bdaSLionel Sambuc unsigned n:7; /* numerator (3..127) */ 8087eb99bdaSLionel Sambuc unsigned m:7; /* denominator (3..127) */ 8097eb99bdaSLionel Sambuc unsigned v:1; /* mul by 1|8 */ 8107eb99bdaSLionel Sambuc unsigned x:2; /* div by 1|2|4|8 */ 8117eb99bdaSLionel Sambuc unsigned r:2; /* div by 1|2|4|8 */ 8127eb99bdaSLionel Sambuc unsigned prescale:13; /* log(final divisor): 2, 4 or 9 */ 8137eb99bdaSLionel Sambuc } __packed; 8147eb99bdaSLionel Sambuc 8157eb99bdaSLionel Sambuc #define SYNTH_FREF 20e6 /* reference xtal = 20 MHz */ 8167eb99bdaSLionel Sambuc #define SYNTH_FMIN 50e6 /* internal VCO min 50 MHz */ 8177eb99bdaSLionel Sambuc #define SYNTH_FMAX 250e6 /* internal VCO max 250 MHz */ 8187eb99bdaSLionel Sambuc 8197eb99bdaSLionel Sambuc /* sc->config is the READ/WRITE configuration of the card. */ 8207eb99bdaSLionel Sambuc /* Accessed using socket IO control calls or netgraph control messages. */ 8217eb99bdaSLionel Sambuc struct config 8227eb99bdaSLionel Sambuc { 8237eb99bdaSLionel Sambuc struct iohdr iohdr; /* common ioctl header */ 8247eb99bdaSLionel Sambuc u_int32_t crc_len; /* ALL: CRC-16 or CRC-32 or none */ 8257eb99bdaSLionel Sambuc u_int32_t loop_back; /* ALL: many kinds of loopbacks */ 8267eb99bdaSLionel Sambuc u_int32_t tx_clk_src; /* T1, HSSI: ST, RT, int, ext */ 8277eb99bdaSLionel Sambuc u_int32_t format; /* T3, T1: ckt framing format */ 8287eb99bdaSLionel Sambuc u_int32_t time_slots; /* T1: 64Kb time slot config */ 8297eb99bdaSLionel Sambuc u_int32_t cable_len; /* T3, T1: cable length in meters */ 8307eb99bdaSLionel Sambuc u_int32_t scrambler; /* T3: payload scrambler config */ 8317eb99bdaSLionel Sambuc u_int32_t dte_dce; /* SSI, HSSIc: drive TXCLK */ 8327eb99bdaSLionel Sambuc struct synth synth; /* SSI, HSSIc: synth oscil params */ 8337eb99bdaSLionel Sambuc u_int32_t rx_gain_max; /* T1: receiver gain limit 0-50 dB */ 8347eb99bdaSLionel Sambuc u_int32_t tx_pulse; /* T1: transmitter pulse shape */ 8357eb99bdaSLionel Sambuc u_int32_t tx_lbo; /* T1: transmitter atten 0-22.5 dB */ 8367eb99bdaSLionel Sambuc u_int32_t debug; /* ALL: extra printout */ 8377eb99bdaSLionel Sambuc u_int32_t stack; /* ALL: use this line stack */ 8387eb99bdaSLionel Sambuc u_int32_t proto; /* ALL: use this line proto */ 8397eb99bdaSLionel Sambuc u_int32_t keep_alive; /* SPPP: use keep-alive packets */ 8407eb99bdaSLionel Sambuc }; 8417eb99bdaSLionel Sambuc 8427eb99bdaSLionel Sambuc #define CFG_CRC_0 0 /* no CRC */ 8437eb99bdaSLionel Sambuc #define CFG_CRC_16 2 /* X^16+X^12+X^5+1 (default) */ 8447eb99bdaSLionel Sambuc #define CFG_CRC_32 4 /* X^32+X^26+X^23+X^22+X^16+X^12+ */ 8457eb99bdaSLionel Sambuc /* X^11+X^10+X^8+X^7+X^5+X^4+X^2+X+1 */ 8467eb99bdaSLionel Sambuc #define CFG_LOOP_NONE 1 /* SNMP don't loop back anything */ 8477eb99bdaSLionel Sambuc #define CFG_LOOP_PAYLOAD 2 /* SNMP loop outward thru framer */ 8487eb99bdaSLionel Sambuc #define CFG_LOOP_LINE 3 /* SNMP loop outward thru LIU */ 8497eb99bdaSLionel Sambuc #define CFG_LOOP_OTHER 4 /* SNMP loop inward thru LIU */ 8507eb99bdaSLionel Sambuc #define CFG_LOOP_INWARD 5 /* SNMP loop inward thru framer */ 8517eb99bdaSLionel Sambuc #define CFG_LOOP_DUAL 6 /* SNMP loop inward & outward */ 8527eb99bdaSLionel Sambuc #define CFG_LOOP_TULIP 16 /* ALL: loop inward thru Tulip */ 8537eb99bdaSLionel Sambuc #define CFG_LOOP_PINS 17 /* HSSIc, SSI: loop inward-pins */ 8547eb99bdaSLionel Sambuc #define CFG_LOOP_LL 18 /* HSSI, SSI: assert LA/LL mdm pin */ 8557eb99bdaSLionel Sambuc #define CFG_LOOP_RL 19 /* HSSI, SSI: assert LB/RL mdm pin */ 8567eb99bdaSLionel Sambuc 8577eb99bdaSLionel Sambuc #define CFG_CLKMUX_ST 1 /* TX clk <- Send timing */ 8587eb99bdaSLionel Sambuc #define CFG_CLKMUX_INT 2 /* TX clk <- internal source */ 8597eb99bdaSLionel Sambuc #define CFG_CLKMUX_RT 3 /* TX clk <- Receive (loop) timing */ 8607eb99bdaSLionel Sambuc #define CFG_CLKMUX_EXT 4 /* TX clk <- ext connector */ 8617eb99bdaSLionel Sambuc 8627eb99bdaSLionel Sambuc /* values 0-31 are Bt8370 CR0 register values (LSB is zero if E1). */ 8637eb99bdaSLionel Sambuc /* values 32-99 are reserved for other T1E1 formats, (even number if E1) */ 8647eb99bdaSLionel Sambuc /* values 100 and up are used for T3 frame formats. */ 8657eb99bdaSLionel Sambuc #define CFG_FORMAT_T1SF 9 /* T1-SF AMI */ 8667eb99bdaSLionel Sambuc #define CFG_FORMAT_T1ESF 27 /* T1-ESF+CRC B8ZS X^6+X+1 */ 8677eb99bdaSLionel Sambuc #define CFG_FORMAT_E1FAS 0 /* E1-FAS HDB3 TS0 */ 8687eb99bdaSLionel Sambuc #define CFG_FORMAT_E1FASCRC 8 /* E1-FAS+CRC HDB3 TS0 X^4+X+1 */ 8697eb99bdaSLionel Sambuc #define CFG_FORMAT_E1FASCAS 16 /* E1-FAS +CAS HDB3 TS0 & TS16 */ 8707eb99bdaSLionel Sambuc #define CFG_FORMAT_E1FASCRCCAS 24 /* E1-FAS+CRC+CAS HDB3 TS0 & TS16 */ 8717eb99bdaSLionel Sambuc #define CFG_FORMAT_E1NONE 32 /* E1-NO framing HDB3 */ 8727eb99bdaSLionel Sambuc #define CFG_FORMAT_T3CPAR 100 /* T3-C-Bit par B3ZS */ 8737eb99bdaSLionel Sambuc #define CFG_FORMAT_T3M13 101 /* T3-M13 format B3ZS */ 8747eb99bdaSLionel Sambuc 8757eb99bdaSLionel Sambuc /* format aliases that improve code readability */ 8767eb99bdaSLionel Sambuc #define FORMAT_T1ANY ((sc->config.format & 1)==1) 8777eb99bdaSLionel Sambuc #define FORMAT_E1ANY ((sc->config.format & 1)==0) 8787eb99bdaSLionel Sambuc #define FORMAT_E1CAS ((sc->config.format & 0x11)==0x10) 8797eb99bdaSLionel Sambuc #define FORMAT_E1CRC ((sc->config.format & 0x09)==0x08) 8807eb99bdaSLionel Sambuc #define FORMAT_E1NONE (sc->config.format == CFG_FORMAT_E1NONE) 8817eb99bdaSLionel Sambuc #define FORMAT_T1ESF (sc->config.format == CFG_FORMAT_T1ESF) 8827eb99bdaSLionel Sambuc #define FORMAT_T1SF (sc->config.format == CFG_FORMAT_T1SF) 8837eb99bdaSLionel Sambuc #define FORMAT_T3CPAR (sc->config.format == CFG_FORMAT_T3CPAR) 8847eb99bdaSLionel Sambuc 8857eb99bdaSLionel Sambuc #define CFG_SCRAM_OFF 1 /* DS3 payload scrambler off */ 8867eb99bdaSLionel Sambuc #define CFG_SCRAM_DL_KEN 2 /* DS3 DigitalLink/Kentrox X^43+1 */ 8877eb99bdaSLionel Sambuc #define CFG_SCRAM_LARS 3 /* DS3 Larscom X^20+X^17+1 w/28ZS */ 8887eb99bdaSLionel Sambuc 8897eb99bdaSLionel Sambuc #define CFG_DTE 1 /* HSSIc, SSI: rcv TXCLK; rcv DCD */ 8907eb99bdaSLionel Sambuc #define CFG_DCE 2 /* HSSIc, SSI: drv TXCLK; drv DCD */ 8917eb99bdaSLionel Sambuc 8927eb99bdaSLionel Sambuc #define CFG_GAIN_SHORT 0x24 /* 0-20 dB of equalized gain */ 8937eb99bdaSLionel Sambuc #define CFG_GAIN_MEDIUM 0x2C /* 0-30 dB of equalized gain */ 8947eb99bdaSLionel Sambuc #define CFG_GAIN_LONG 0x34 /* 0-40 dB of equalized gain */ 8957eb99bdaSLionel Sambuc #define CFG_GAIN_EXTEND 0x3F /* 0-64 dB of equalized gain */ 8967eb99bdaSLionel Sambuc #define CFG_GAIN_AUTO 0xFF /* auto-set based on cable length */ 8977eb99bdaSLionel Sambuc 8987eb99bdaSLionel Sambuc #define CFG_PULSE_T1DSX0 0 /* T1 DSX 0- 40 meters */ 8997eb99bdaSLionel Sambuc #define CFG_PULSE_T1DSX1 2 /* T1 DSX 40- 80 meters */ 9007eb99bdaSLionel Sambuc #define CFG_PULSE_T1DSX2 4 /* T1 DSX 80-120 meters */ 9017eb99bdaSLionel Sambuc #define CFG_PULSE_T1DSX3 6 /* T1 DSX 120-160 meters */ 9027eb99bdaSLionel Sambuc #define CFG_PULSE_T1DSX4 8 /* T1 DSX 160-200 meters */ 9037eb99bdaSLionel Sambuc #define CFG_PULSE_E1COAX 10 /* E1 75 ohm coax pair */ 9047eb99bdaSLionel Sambuc #define CFG_PULSE_E1TWIST 12 /* E1 120 ohm twisted pairs */ 9057eb99bdaSLionel Sambuc #define CFG_PULSE_T1CSU 14 /* T1 CSU 200-2000 meters; set LBO */ 9067eb99bdaSLionel Sambuc #define CFG_PULSE_AUTO 0xFF /* auto-set based on cable length */ 9077eb99bdaSLionel Sambuc 9087eb99bdaSLionel Sambuc #define CFG_LBO_0DB 0 /* T1CSU LBO = 0.0 dB; FCC opt A */ 9097eb99bdaSLionel Sambuc #define CFG_LBO_7DB 16 /* T1CSU LBO = 7.5 dB; FCC opt B */ 9107eb99bdaSLionel Sambuc #define CFG_LBO_15DB 32 /* T1CSU LBO = 15.0 dB; FCC opt C */ 9117eb99bdaSLionel Sambuc #define CFG_LBO_22DB 48 /* T1CSU LBO = 22.5 dB; final span */ 9127eb99bdaSLionel Sambuc #define CFG_LBO_AUTO 0xFF /* auto-set based on cable length */ 9137eb99bdaSLionel Sambuc 9147eb99bdaSLionel Sambuc struct ioctl 9157eb99bdaSLionel Sambuc { 9167eb99bdaSLionel Sambuc struct iohdr iohdr; /* common ioctl header */ 9177eb99bdaSLionel Sambuc u_int32_t cmd; /* command */ 9187eb99bdaSLionel Sambuc u_int32_t address; /* command address */ 9197eb99bdaSLionel Sambuc u_int32_t data; /* command data */ 9207eb99bdaSLionel Sambuc char *ucode; /* user-land address of ucode */ 9217eb99bdaSLionel Sambuc }; 9227eb99bdaSLionel Sambuc 9237eb99bdaSLionel Sambuc #define IOCTL_RW_PCI 1 /* RW: Tulip PCI config registers */ 9247eb99bdaSLionel Sambuc #define IOCTL_RW_CSR 2 /* RW: Tulip Control & Status Regs */ 9257eb99bdaSLionel Sambuc #define IOCTL_RW_SROM 3 /* RW: Tulip Serial Rom */ 9267eb99bdaSLionel Sambuc #define IOCTL_RW_BIOS 4 /* RW: Tulip Boot rom */ 9277eb99bdaSLionel Sambuc #define IOCTL_RW_MII 5 /* RW: MII registers */ 9287eb99bdaSLionel Sambuc #define IOCTL_RW_FRAME 6 /* RW: Framer registers */ 9297eb99bdaSLionel Sambuc #define IOCTL_WO_SYNTH 7 /* WO: Synthesized oscillator */ 9307eb99bdaSLionel Sambuc #define IOCTL_WO_DAC 8 /* WO: Digital/Analog Converter */ 9317eb99bdaSLionel Sambuc 9327eb99bdaSLionel Sambuc #define IOCTL_XILINX_RESET 16 /* reset Xilinx: all FFs set to 0 */ 9337eb99bdaSLionel Sambuc #define IOCTL_XILINX_ROM 17 /* load Xilinx program from ROM */ 9347eb99bdaSLionel Sambuc #define IOCTL_XILINX_FILE 18 /* load Xilinx program from file */ 9357eb99bdaSLionel Sambuc 9367eb99bdaSLionel Sambuc #define IOCTL_SET_STATUS 50 /* set mdm ctrl bits (internal) */ 9377eb99bdaSLionel Sambuc #define IOCTL_SNMP_SEND 51 /* trunk MIB send code */ 9387eb99bdaSLionel Sambuc #define IOCTL_SNMP_LOOP 52 /* trunk MIB loop configuration */ 9397eb99bdaSLionel Sambuc #define IOCTL_SNMP_SIGS 53 /* RS232-like modem control sigs */ 9407eb99bdaSLionel Sambuc #define IOCTL_RESET_CNTRS 54 /* reset event counters */ 9417eb99bdaSLionel Sambuc 9427eb99bdaSLionel Sambuc /* storage for these strings is allocated here! */ 9437eb99bdaSLionel Sambuc const char *ssi_cables[] = 9447eb99bdaSLionel Sambuc { 9457eb99bdaSLionel Sambuc "V.10/EIA423", 9467eb99bdaSLionel Sambuc "V.11/EIA530A", 9477eb99bdaSLionel Sambuc "RESERVED", 9487eb99bdaSLionel Sambuc "X.21", 9497eb99bdaSLionel Sambuc "V.35", 9507eb99bdaSLionel Sambuc "V.36/EIA449", 9517eb99bdaSLionel Sambuc "V.28/EIA232", 9527eb99bdaSLionel Sambuc "NO CABLE", 9537eb99bdaSLionel Sambuc NULL, 9547eb99bdaSLionel Sambuc }; 9557eb99bdaSLionel Sambuc 9567eb99bdaSLionel Sambuc /***************************************************************************/ 9577eb99bdaSLionel Sambuc /* Declarations above here are shared with the user lmcconfig program. */ 9587eb99bdaSLionel Sambuc /* Declarations below here are private to the kernel device driver. */ 9597eb99bdaSLionel Sambuc /***************************************************************************/ 9607eb99bdaSLionel Sambuc 9617eb99bdaSLionel Sambuc #if KERNEL || _KERNEL || __KERNEL__ 9627eb99bdaSLionel Sambuc 9637eb99bdaSLionel Sambuc /* Hide the minor differences between Operating Systems */ 9647eb99bdaSLionel Sambuc 9657eb99bdaSLionel Sambuc typedef int intr_return_t; 9667eb99bdaSLionel Sambuc # define READ_PCI_CFG(sc, addr) pci_conf_read ((sc)->pa_pc, (sc)->pa_tag, addr) 9677eb99bdaSLionel Sambuc # define WRITE_PCI_CFG(sc, addr, data) pci_conf_write((sc)->pa_pc, (sc)->pa_tag, addr, data) 9687eb99bdaSLionel Sambuc # define READ_CSR(sc, csr) bus_space_read_4 ((sc)->csr_tag, (sc)->csr_handle, csr) 9697eb99bdaSLionel Sambuc # define WRITE_CSR(sc, csr, val) bus_space_write_4((sc)->csr_tag, (sc)->csr_handle, csr, val) 9707eb99bdaSLionel Sambuc # define NAME_UNIT device_xname(sc->sc_dev) 9717eb99bdaSLionel Sambuc # define BOOT_VERBOSE (boothowto & AB_VERBOSE) 9727eb99bdaSLionel Sambuc # define TOP_LOCK(sc) (mutex_spin_enter(&(sc)->top_lock), 0) 9737eb99bdaSLionel Sambuc # define TOP_TRYLOCK(sc) mutex_tryenter(&(sc)->top_lock) 9747eb99bdaSLionel Sambuc # define TOP_UNLOCK(sc) mutex_spin_exit(&(sc)->top_lock) 9757eb99bdaSLionel Sambuc # define BOTTOM_TRYLOCK(sc) __cpu_simple_lock_try(&(sc)->bottom_lock) 9767eb99bdaSLionel Sambuc # define BOTTOM_UNLOCK(sc) __cpu_simple_unlock (&(sc)->bottom_lock) 9777eb99bdaSLionel Sambuc # define CHECK_CAP kauth_authorize_network(curlwp->l_cred, KAUTH_NETWORK_INTERFACE, KAUTH_REQ_NETWORK_INTERFACE_FIRMWARE, sc->ifp, NULL, NULL) 9787eb99bdaSLionel Sambuc # define DISABLE_INTR int spl = splnet() 9797eb99bdaSLionel Sambuc # define ENABLE_INTR splx(spl) 9807eb99bdaSLionel Sambuc # define IRQ_NONE 0 9817eb99bdaSLionel Sambuc # define IRQ_HANDLED 1 9827eb99bdaSLionel Sambuc # define IFP2SC(ifp) (ifp)->if_softc 9837eb99bdaSLionel Sambuc # define COPY_BREAK MHLEN 9847eb99bdaSLionel Sambuc # define SLEEP(usecs) tsleep(sc, PZERO, DEVICE_NAME, 1+(usecs/tick)) 9857eb99bdaSLionel Sambuc # define DMA_SYNC(map, size, flags) bus_dmamap_sync(ring->tag, map, 0, size, flags) 9867eb99bdaSLionel Sambuc # define DMA_LOAD(map, addr, size) bus_dmamap_load(ring->tag, map, addr, size, 0, BUS_DMA_NOWAIT) 9877eb99bdaSLionel Sambuc # define LMC_BPF_MTAP(sc, mbuf) bpf_mtap((sc)->ifp, mbuf) 9887eb99bdaSLionel Sambuc # define LMC_BPF_ATTACH(sc, dlt, len) bpf_attach((sc)->ifp, dlt, len) 9897eb99bdaSLionel Sambuc # define LMC_BPF_DETACH(sc) bpf_detach((sc)->ifp) 9907eb99bdaSLionel Sambuc 9917eb99bdaSLionel Sambuc static int driver_announced = 0; /* print driver info once only */ 9927eb99bdaSLionel Sambuc 9937eb99bdaSLionel Sambuc #define SNDQ_MAXLEN 32 /* packets awaiting transmission */ 9947eb99bdaSLionel Sambuc #define DESCS_PER_PKT 4 /* DMA descriptors per TX pkt */ 9957eb99bdaSLionel Sambuc #define NUM_TX_DESCS (DESCS_PER_PKT * SNDQ_MAXLEN) 9967eb99bdaSLionel Sambuc /* Increase DESCS_PER_PKT if status.cntrs.txdma increments. */ 9977eb99bdaSLionel Sambuc 9987eb99bdaSLionel Sambuc /* A Tulip DMA descriptor can point to two chunks of memory. 9997eb99bdaSLionel Sambuc * Each chunk has a max length of 2047 bytes (ask the VMS guys). 10007eb99bdaSLionel Sambuc * 2047 isn't a multiple of a cache line size (32 bytes typically). 10017eb99bdaSLionel Sambuc * So back off to 2048-32 = 2016 bytes per chunk (2 chunks per descr). 10027eb99bdaSLionel Sambuc */ 10037eb99bdaSLionel Sambuc #define MAX_CHUNK_LEN (2048-32) 10047eb99bdaSLionel Sambuc #define MAX_DESC_LEN (2 * MAX_CHUNK_LEN) 10057eb99bdaSLionel Sambuc 10067eb99bdaSLionel Sambuc /* Tulip DMA descriptor; THIS STRUCT MUST MATCH THE HARDWARE */ 10077eb99bdaSLionel Sambuc struct dma_desc 10087eb99bdaSLionel Sambuc { 10097eb99bdaSLionel Sambuc u_int32_t status; /* hardware->to->software */ 10107eb99bdaSLionel Sambuc #if BYTE_ORDER == LITTLE_ENDIAN /* left-to-right packing */ 10117eb99bdaSLionel Sambuc unsigned length1:11; /* buffer1 length */ 10127eb99bdaSLionel Sambuc unsigned length2:11; /* buffer2 length */ 10137eb99bdaSLionel Sambuc unsigned control:10; /* software->to->hardware */ 10147eb99bdaSLionel Sambuc #else /* right-to-left packing */ 10157eb99bdaSLionel Sambuc unsigned control:10; /* software->to->hardware */ 10167eb99bdaSLionel Sambuc unsigned length2:11; /* buffer2 length */ 10177eb99bdaSLionel Sambuc unsigned length1:11; /* buffer1 length */ 10187eb99bdaSLionel Sambuc #endif 10197eb99bdaSLionel Sambuc u_int32_t address1; /* buffer1 bus address */ 10207eb99bdaSLionel Sambuc u_int32_t address2; /* buffer2 bus address */ 10217eb99bdaSLionel Sambuc bus_dmamap_t map; /* bus dmamap for this descriptor */ 10227eb99bdaSLionel Sambuc # define TLP_BUS_DSL_VAL (sizeof(bus_dmamap_t) & TLP_BUS_DSL) 10237eb99bdaSLionel Sambuc } __packed; 10247eb99bdaSLionel Sambuc 10257eb99bdaSLionel Sambuc /* Tulip DMA descriptor status bits */ 10267eb99bdaSLionel Sambuc #define TLP_DSTS_OWNER 0x80000000 10277eb99bdaSLionel Sambuc #define TLP_DSTS_RX_DESC_ERR 0x00004000 10287eb99bdaSLionel Sambuc #define TLP_DSTS_RX_FIRST_DESC 0x00000200 10297eb99bdaSLionel Sambuc #define TLP_DSTS_RX_LAST_DESC 0x00000100 10307eb99bdaSLionel Sambuc #define TLP_DSTS_RX_MII_ERR 0x00000008 10317eb99bdaSLionel Sambuc #define TLP_DSTS_RX_DRIBBLE 0x00000004 10327eb99bdaSLionel Sambuc #define TLP_DSTS_TX_UNDERRUN 0x00000002 10337eb99bdaSLionel Sambuc #define TLP_DSTS_RX_OVERRUN 0x00000001 /* not documented in rev AF */ 10347eb99bdaSLionel Sambuc #define TLP_DSTS_RX_BAD (TLP_DSTS_RX_MII_ERR | \ 10357eb99bdaSLionel Sambuc TLP_DSTS_RX_DRIBBLE | \ 10367eb99bdaSLionel Sambuc TLP_DSTS_RX_DESC_ERR | \ 10377eb99bdaSLionel Sambuc TLP_DSTS_RX_OVERRUN) 10387eb99bdaSLionel Sambuc 10397eb99bdaSLionel Sambuc /* Tulip DMA descriptor control bits */ 10407eb99bdaSLionel Sambuc #define TLP_DCTL_TX_INTERRUPT 0x0200 10417eb99bdaSLionel Sambuc #define TLP_DCTL_TX_LAST_SEG 0x0100 10427eb99bdaSLionel Sambuc #define TLP_DCTL_TX_FIRST_SEG 0x0080 10437eb99bdaSLionel Sambuc #define TLP_DCTL_TX_NO_CRC 0x0010 10447eb99bdaSLionel Sambuc #define TLP_DCTL_END_RING 0x0008 10457eb99bdaSLionel Sambuc #define TLP_DCTL_TX_NO_PAD 0x0002 10467eb99bdaSLionel Sambuc 10477eb99bdaSLionel Sambuc /* DMA descriptors are kept in a ring. 10487eb99bdaSLionel Sambuc * Ring is empty when (read == write). 10497eb99bdaSLionel Sambuc * Ring is full when (read == wrap(write+1)), 10507eb99bdaSLionel Sambuc * The ring also contains a tailq of data buffers. 10517eb99bdaSLionel Sambuc */ 10527eb99bdaSLionel Sambuc struct desc_ring 10537eb99bdaSLionel Sambuc { 10547eb99bdaSLionel Sambuc struct dma_desc *read; /* next descriptor to be read */ 10557eb99bdaSLionel Sambuc struct dma_desc *write; /* next descriptor to be written */ 10567eb99bdaSLionel Sambuc struct dma_desc *first; /* first descriptor in ring */ 10577eb99bdaSLionel Sambuc struct dma_desc *last; /* last descriptor in ring */ 10587eb99bdaSLionel Sambuc struct dma_desc *temp; /* temporary write pointer for tx */ 10597eb99bdaSLionel Sambuc u_int32_t dma_addr; /* bus addr for desc array XXX */ 10607eb99bdaSLionel Sambuc int size_descs; /* bus_dmamap_sync needs this */ 10617eb99bdaSLionel Sambuc int num_descs; /* used to set rx quota */ 10627eb99bdaSLionel Sambuc #if IFNET || NETGRAPH 10637eb99bdaSLionel Sambuc struct mbuf *head; /* tail-queue of mbufs */ 10647eb99bdaSLionel Sambuc struct mbuf *tail; 10657eb99bdaSLionel Sambuc #elif NETDEV 10667eb99bdaSLionel Sambuc struct sk_buff *head; /* tail-queue of skbuffs */ 10677eb99bdaSLionel Sambuc struct sk_buff *tail; 10687eb99bdaSLionel Sambuc #endif 10697eb99bdaSLionel Sambuc bus_dma_tag_t tag; /* bus_dma_tag for desc array */ 10707eb99bdaSLionel Sambuc bus_dmamap_t map; /* bus_dmamap for desc array */ 10717eb99bdaSLionel Sambuc bus_dma_segment_t segs[2]; /* bus_dmamap_load() or bus_dmamem_alloc() */ 10727eb99bdaSLionel Sambuc int nsegs; /* bus_dmamap_load() or bus_dmamem_alloc() */ 10737eb99bdaSLionel Sambuc }; 10747eb99bdaSLionel Sambuc 10757eb99bdaSLionel Sambuc /* break circular definition */ 10767eb99bdaSLionel Sambuc typedef struct softc softc_t; 10777eb99bdaSLionel Sambuc 10787eb99bdaSLionel Sambuc struct card /* an object */ 10797eb99bdaSLionel Sambuc { 10807eb99bdaSLionel Sambuc void (*ident) (softc_t *); 10817eb99bdaSLionel Sambuc void (*watchdog) (softc_t *); 10827eb99bdaSLionel Sambuc int (*ioctl) (softc_t *, struct ioctl *); 10837eb99bdaSLionel Sambuc void (*attach) (softc_t *, struct config *); 10847eb99bdaSLionel Sambuc void (*detach) (softc_t *); 10857eb99bdaSLionel Sambuc }; 10867eb99bdaSLionel Sambuc 10877eb99bdaSLionel Sambuc struct stack /* an object */ 10887eb99bdaSLionel Sambuc { 10897eb99bdaSLionel Sambuc #if IFNET || NETGRAPH 10907eb99bdaSLionel Sambuc int (*ioctl) (softc_t *, u_long, void *); 10917eb99bdaSLionel Sambuc void (*input) (softc_t *, struct mbuf *); 10927eb99bdaSLionel Sambuc void (*output) (softc_t *); 10937eb99bdaSLionel Sambuc #elif NETDEV 10947eb99bdaSLionel Sambuc int (*ioctl) (softc_t *, struct ifreq *, int); 10957eb99bdaSLionel Sambuc int (*type) (softc_t *, struct sk_buff *); 10967eb99bdaSLionel Sambuc int (*mtu) (softc_t *, int); 10977eb99bdaSLionel Sambuc #endif 10987eb99bdaSLionel Sambuc void (*watchdog) (softc_t *); 10997eb99bdaSLionel Sambuc int (*open) (softc_t *, struct config *); 11007eb99bdaSLionel Sambuc int (*attach) (softc_t *, struct config *); 11017eb99bdaSLionel Sambuc int (*detach) (softc_t *); 11027eb99bdaSLionel Sambuc }; 11037eb99bdaSLionel Sambuc 11047eb99bdaSLionel Sambuc /* This is the instance data, or "software context" for the device driver. */ 11057eb99bdaSLionel Sambuc struct softc 11067eb99bdaSLionel Sambuc { 11077eb99bdaSLionel Sambuc 11087eb99bdaSLionel Sambuc device_t sc_dev; 11097eb99bdaSLionel Sambuc pcitag_t pa_tag; 11107eb99bdaSLionel Sambuc pci_chipset_tag_t pa_pc; 11117eb99bdaSLionel Sambuc bus_dma_tag_t pa_dmat; 11127eb99bdaSLionel Sambuc bus_space_tag_t csr_tag; 11137eb99bdaSLionel Sambuc bus_space_handle_t csr_handle; 11147eb99bdaSLionel Sambuc pci_intr_handle_t intr_handle; 11157eb99bdaSLionel Sambuc void *irq_cookie; 11167eb99bdaSLionel Sambuc void *sdh_cookie; 11177eb99bdaSLionel Sambuc struct mbuf *tx_mbuf; /* hang mbuf here while building dma descs */ 11187eb99bdaSLionel Sambuc kmutex_t top_lock; /* lock card->watchdog vs ioctls */ 11197eb99bdaSLionel Sambuc __cpu_simple_lock_t bottom_lock; /* lock buf queues & descriptor rings */ 11207eb99bdaSLionel Sambuc 11217eb99bdaSLionel Sambuc /* State for kernel-resident Line Protocols */ 11227eb99bdaSLionel Sambuc #if IFNET 11237eb99bdaSLionel Sambuc # if SPPP 11247eb99bdaSLionel Sambuc struct sppp spppcom; 11257eb99bdaSLionel Sambuc struct sppp *sppp; 11267eb99bdaSLionel Sambuc # elif P2P 11277eb99bdaSLionel Sambuc struct p2pcom p2pcom; 11287eb99bdaSLionel Sambuc struct p2pcom *p2p; 11297eb99bdaSLionel Sambuc # else 11307eb99bdaSLionel Sambuc struct ifnet ifnet; 11317eb99bdaSLionel Sambuc # endif 11327eb99bdaSLionel Sambuc struct ifnet *ifp; 11337eb99bdaSLionel Sambuc struct ifmedia ifm; 11347eb99bdaSLionel Sambuc #endif /* IFNET */ 11357eb99bdaSLionel Sambuc 11367eb99bdaSLionel Sambuc #if NETDEV 11377eb99bdaSLionel Sambuc # if GEN_HDLC 11387eb99bdaSLionel Sambuc hdlc_device *hdlcdev; /* contains struct net_device_stats */ 11397eb99bdaSLionel Sambuc # else 11407eb99bdaSLionel Sambuc struct net_device_stats netdev_stats; 11417eb99bdaSLionel Sambuc # endif 11427eb99bdaSLionel Sambuc # if SYNC_PPP 11437eb99bdaSLionel Sambuc struct ppp_device *ppd; 11447eb99bdaSLionel Sambuc struct ppp_device ppp_dev; /* contains a struct sppp */ 11457eb99bdaSLionel Sambuc struct sppp *sppp; 11467eb99bdaSLionel Sambuc # endif 11477eb99bdaSLionel Sambuc struct net_device *netdev; 11487eb99bdaSLionel Sambuc #endif /* NETDEV */ 11497eb99bdaSLionel Sambuc 11507eb99bdaSLionel Sambuc 11517eb99bdaSLionel Sambuc 11527eb99bdaSLionel Sambuc 11537eb99bdaSLionel Sambuc /* State used by all card types; lock with top_lock. */ 11547eb99bdaSLionel Sambuc struct status status; /* lmcconfig can read */ 11557eb99bdaSLionel Sambuc struct config config; /* lmcconfig can read/write */ 11567eb99bdaSLionel Sambuc const char *dev_desc; /* string describing card */ 11577eb99bdaSLionel Sambuc struct card *card; /* card methods */ 11587eb99bdaSLionel Sambuc struct stack *stack; /* line methods */ 11597eb99bdaSLionel Sambuc u_int32_t gpio_dir; /* s/w copy of GPIO direction reg */ 11607eb99bdaSLionel Sambuc u_int16_t led_state; /* last value written to mii16 */ 11617eb99bdaSLionel Sambuc int quota; /* used for packet flow control */ 11627eb99bdaSLionel Sambuc 11637eb99bdaSLionel Sambuc /* State used by card-specific watchdogs; lock with top_lock. */ 11647eb99bdaSLionel Sambuc u_int32_t last_mii16; /* SSI, HSSI: MII reg 16 one sec ago */ 11657eb99bdaSLionel Sambuc u_int32_t last_stat16; /* T3: framer reg 16 one sec ago */ 11667eb99bdaSLionel Sambuc u_int32_t last_alm1; /* T1E1: framer reg 47 one sec ago */ 11677eb99bdaSLionel Sambuc u_int32_t last_link_state; /* ALL: status.link_state 1 ec ago */ 11687eb99bdaSLionel Sambuc u_int32_t last_FEAC; /* T3: last FEAC msg code received */ 11697eb99bdaSLionel Sambuc u_int32_t loop_timer; /* T1E1, T3: secs until loop ends */ 11707eb99bdaSLionel Sambuc 11717eb99bdaSLionel Sambuc /* State used by the interrupt code; lock with bottom_lock. */ 11727eb99bdaSLionel Sambuc struct desc_ring txring; /* tx descriptor ring state */ 11737eb99bdaSLionel Sambuc struct desc_ring rxring; /* rx descriptor ring state */ 11747eb99bdaSLionel Sambuc }; /* end of softc */ 11757eb99bdaSLionel Sambuc 11767eb99bdaSLionel Sambuc 11777eb99bdaSLionel Sambuc #define HSSI_DESC "LMC5200 HSSI Card" 11787eb99bdaSLionel Sambuc #define T3_DESC "LMC5245 T3 Card" 11797eb99bdaSLionel Sambuc #define SSI_DESC "LMC1000 SSI Card" 11807eb99bdaSLionel Sambuc #define T1E1_DESC "LMC1200 T1E1 Card" 11817eb99bdaSLionel Sambuc 11827eb99bdaSLionel Sambuc /* procedure prototypes */ 11837eb99bdaSLionel Sambuc 11847eb99bdaSLionel Sambuc static void srom_shift_bits(softc_t *, u_int32_t, u_int32_t); 11857eb99bdaSLionel Sambuc static u_int16_t srom_read(softc_t *, u_int8_t); 11867eb99bdaSLionel Sambuc static void srom_write(softc_t *, u_int8_t, u_int16_t); 11877eb99bdaSLionel Sambuc 11887eb99bdaSLionel Sambuc static u_int8_t bios_read(softc_t *, u_int32_t); 11897eb99bdaSLionel Sambuc static void bios_write_phys(softc_t *, u_int32_t, u_int8_t); 11907eb99bdaSLionel Sambuc static void bios_write(softc_t *, u_int32_t, u_int8_t); 11917eb99bdaSLionel Sambuc static void bios_erase(softc_t *); 11927eb99bdaSLionel Sambuc 11937eb99bdaSLionel Sambuc static void mii_shift_bits(softc_t *, u_int32_t, u_int32_t); 11947eb99bdaSLionel Sambuc static u_int16_t mii_read(softc_t *, u_int8_t); 11957eb99bdaSLionel Sambuc static void mii_write(softc_t *, u_int8_t, u_int16_t); 11967eb99bdaSLionel Sambuc 11977eb99bdaSLionel Sambuc static void mii16_set_bits(softc_t *, u_int16_t); 11987eb99bdaSLionel Sambuc static void mii16_clr_bits(softc_t *, u_int16_t); 11997eb99bdaSLionel Sambuc static void mii17_set_bits(softc_t *, u_int16_t); 12007eb99bdaSLionel Sambuc static void mii17_clr_bits(softc_t *, u_int16_t); 12017eb99bdaSLionel Sambuc 12027eb99bdaSLionel Sambuc static void led_off(softc_t *, u_int16_t); 12037eb99bdaSLionel Sambuc static void led_on(softc_t *, u_int16_t); 12047eb99bdaSLionel Sambuc static void led_inv(softc_t *, u_int16_t); 12057eb99bdaSLionel Sambuc 12067eb99bdaSLionel Sambuc static void framer_write(softc_t *, u_int16_t, u_int8_t); 12077eb99bdaSLionel Sambuc static u_int8_t framer_read(softc_t *, u_int16_t); 12087eb99bdaSLionel Sambuc 12097eb99bdaSLionel Sambuc static void gpio_make_input(softc_t *, u_int32_t); 12107eb99bdaSLionel Sambuc static void gpio_make_output(softc_t *, u_int32_t); 12117eb99bdaSLionel Sambuc static u_int32_t gpio_read(softc_t *); 12127eb99bdaSLionel Sambuc static void gpio_set_bits(softc_t *, u_int32_t); 12137eb99bdaSLionel Sambuc static void gpio_clr_bits(softc_t *, u_int32_t); 12147eb99bdaSLionel Sambuc 12157eb99bdaSLionel Sambuc static void xilinx_reset(softc_t *); 12167eb99bdaSLionel Sambuc static void xilinx_load_from_rom(softc_t *); 12177eb99bdaSLionel Sambuc static int xilinx_load_from_file(softc_t *, char *, u_int32_t); 12187eb99bdaSLionel Sambuc 12197eb99bdaSLionel Sambuc static void synth_shift_bits(softc_t *, u_int32_t, u_int32_t); 12207eb99bdaSLionel Sambuc static void synth_write(softc_t *, struct synth *); 12217eb99bdaSLionel Sambuc 12227eb99bdaSLionel Sambuc static void dac_write(softc_t *, u_int16_t); 12237eb99bdaSLionel Sambuc 12247eb99bdaSLionel Sambuc static void hssi_ident(softc_t *); 12257eb99bdaSLionel Sambuc static void hssi_watchdog(softc_t *); 12267eb99bdaSLionel Sambuc static int hssi_ioctl(softc_t *, struct ioctl *); 12277eb99bdaSLionel Sambuc static void hssi_attach(softc_t *, struct config *); 12287eb99bdaSLionel Sambuc static void hssi_detach(softc_t *); 12297eb99bdaSLionel Sambuc 12307eb99bdaSLionel Sambuc static void t3_ident(softc_t *); 12317eb99bdaSLionel Sambuc static void t3_watchdog(softc_t *); 12327eb99bdaSLionel Sambuc static int t3_ioctl(softc_t *, struct ioctl *); 12337eb99bdaSLionel Sambuc static void t3_send_dbl_feac(softc_t *, int, int); 12347eb99bdaSLionel Sambuc static void t3_attach(softc_t *, struct config *); 12357eb99bdaSLionel Sambuc static void t3_detach(softc_t *); 12367eb99bdaSLionel Sambuc 12377eb99bdaSLionel Sambuc static void ssi_ident(softc_t *); 12387eb99bdaSLionel Sambuc static void ssi_watchdog(softc_t *); 12397eb99bdaSLionel Sambuc static int ssi_ioctl(softc_t *, struct ioctl *); 12407eb99bdaSLionel Sambuc static void ssi_attach(softc_t *, struct config *); 12417eb99bdaSLionel Sambuc static void ssi_detach(softc_t *); 12427eb99bdaSLionel Sambuc 12437eb99bdaSLionel Sambuc static void t1_ident(softc_t *); 12447eb99bdaSLionel Sambuc static void t1_watchdog(softc_t *); 12457eb99bdaSLionel Sambuc static int t1_ioctl(softc_t *, struct ioctl *); 12467eb99bdaSLionel Sambuc static void t1_send_bop(softc_t *, int); 12477eb99bdaSLionel Sambuc static void t1_attach(softc_t *, struct config *); 12487eb99bdaSLionel Sambuc static void t1_detach(softc_t *); 12497eb99bdaSLionel Sambuc 12507eb99bdaSLionel Sambuc 12517eb99bdaSLionel Sambuc #if SYNC_PPP 12527eb99bdaSLionel Sambuc static int sync_ppp_ioctl(softc_t *, struct ifreq *, int); 12537eb99bdaSLionel Sambuc static int sync_ppp_type(softc_t *, struct sk_buff *); 12547eb99bdaSLionel Sambuc static int sync_ppp_mtu(softc_t *, int); 12557eb99bdaSLionel Sambuc static void sync_ppp_watchdog(softc_t *); 12567eb99bdaSLionel Sambuc static int sync_ppp_open(softc_t *, struct config *); 12577eb99bdaSLionel Sambuc static int sync_ppp_attach(softc_t *, struct config *); 12587eb99bdaSLionel Sambuc static int sync_ppp_detach(softc_t *); 12597eb99bdaSLionel Sambuc #endif /* SYNC_PPP */ 12607eb99bdaSLionel Sambuc 12617eb99bdaSLionel Sambuc #if GEN_HDLC 12627eb99bdaSLionel Sambuc static int gen_hdlc_ioctl(softc_t *, struct ifreq *, int); 12637eb99bdaSLionel Sambuc static int gen_hdlc_type(softc_t *, struct sk_buff *); 12647eb99bdaSLionel Sambuc static int gen_hdlc_mtu(softc_t *, int); 12657eb99bdaSLionel Sambuc static void gen_hdlc_watchdog(softc_t *); 12667eb99bdaSLionel Sambuc static int gen_hdlc_open(softc_t *, struct config *); 12677eb99bdaSLionel Sambuc static int gen_hdlc_attach(softc_t *, struct config *); 12687eb99bdaSLionel Sambuc static int gen_hdlc_detach(softc_t *); 12697eb99bdaSLionel Sambuc static int gen_hdlc_card_params(struct net_device *, unsigned short, 12707eb99bdaSLionel Sambuc unsigned short); 12717eb99bdaSLionel Sambuc #endif /* GEN_HDLC */ 12727eb99bdaSLionel Sambuc 12737eb99bdaSLionel Sambuc #if P2P 12747eb99bdaSLionel Sambuc static int p2p_stack_ioctl(softc_t *, u_long, void *); 12757eb99bdaSLionel Sambuc static void p2p_stack_input(softc_t *, struct mbuf *); 12767eb99bdaSLionel Sambuc static void p2p_stack_output(softc_t *); 12777eb99bdaSLionel Sambuc static void p2p_stack_watchdog(softc_t *); 12787eb99bdaSLionel Sambuc static int p2p_stack_open(softc_t *, struct config *); 12797eb99bdaSLionel Sambuc static int p2p_stack_attach(softc_t *, struct config *); 12807eb99bdaSLionel Sambuc static int p2p_stack_detach(softc_t *); 12817eb99bdaSLionel Sambuc static int p2p_getmdm(struct p2pcom *, void *); 12827eb99bdaSLionel Sambuc static int p2p_mdmctl(struct p2pcom *, int); 12837eb99bdaSLionel Sambuc #endif /* P2P */ 12847eb99bdaSLionel Sambuc 12857eb99bdaSLionel Sambuc #if SPPP 12867eb99bdaSLionel Sambuc static int sppp_stack_ioctl(softc_t *, u_long, void *); 12877eb99bdaSLionel Sambuc static void sppp_stack_input(softc_t *, struct mbuf *); 12887eb99bdaSLionel Sambuc static void sppp_stack_output(softc_t *); 12897eb99bdaSLionel Sambuc static void sppp_stack_watchdog(softc_t *); 12907eb99bdaSLionel Sambuc static int sppp_stack_open(softc_t *, struct config *); 12917eb99bdaSLionel Sambuc static int sppp_stack_attach(softc_t *, struct config *); 12927eb99bdaSLionel Sambuc static int sppp_stack_detach(softc_t *); 12937eb99bdaSLionel Sambuc static void sppp_tls(struct sppp *); 12947eb99bdaSLionel Sambuc static void sppp_tlf(struct sppp *); 12957eb99bdaSLionel Sambuc #endif /* SPPP */ 12967eb99bdaSLionel Sambuc 12977eb99bdaSLionel Sambuc #if IFNET 12987eb99bdaSLionel Sambuc static int rawip_ioctl(softc_t *, u_long, void *); 12997eb99bdaSLionel Sambuc static void rawip_input(softc_t *, struct mbuf *); 13007eb99bdaSLionel Sambuc static void rawip_output(softc_t *); 13017eb99bdaSLionel Sambuc #elif NETDEV 13027eb99bdaSLionel Sambuc static int rawip_ioctl(softc_t *, struct ifreq *, int); 13037eb99bdaSLionel Sambuc static int rawip_type(softc_t *, struct sk_buff *); 13047eb99bdaSLionel Sambuc static int rawip_mtu(softc_t *, int); 13057eb99bdaSLionel Sambuc #endif 13067eb99bdaSLionel Sambuc static void rawip_watchdog(softc_t *); 13077eb99bdaSLionel Sambuc static int rawip_open(softc_t *, struct config *); 13087eb99bdaSLionel Sambuc static int rawip_attach(softc_t *, struct config *); 13097eb99bdaSLionel Sambuc static int rawip_detach(softc_t *); 13107eb99bdaSLionel Sambuc 13117eb99bdaSLionel Sambuc #if IFNET 13127eb99bdaSLionel Sambuc static void ifnet_input(struct ifnet *, struct mbuf *); 13137eb99bdaSLionel Sambuc static int ifnet_output(struct ifnet *, struct mbuf *, 13147eb99bdaSLionel Sambuc const struct sockaddr *, struct rtentry *); 13157eb99bdaSLionel Sambuc static int ifnet_ioctl(struct ifnet *, u_long, void *); 13167eb99bdaSLionel Sambuc static void ifnet_start(struct ifnet *); 13177eb99bdaSLionel Sambuc static void ifnet_watchdog(struct ifnet *); 13187eb99bdaSLionel Sambuc 13197eb99bdaSLionel Sambuc static void ifnet_setup(struct ifnet *); 13207eb99bdaSLionel Sambuc static int ifnet_attach(softc_t *); 13217eb99bdaSLionel Sambuc static void ifnet_detach(softc_t *); 13227eb99bdaSLionel Sambuc 13237eb99bdaSLionel Sambuc static void ifmedia_setup(softc_t *); 13247eb99bdaSLionel Sambuc static int lmc_ifmedia_change(struct ifnet *); 13257eb99bdaSLionel Sambuc static void ifmedia_status(struct ifnet *, struct ifmediareq *); 13267eb99bdaSLionel Sambuc #endif /* IFNET */ 13277eb99bdaSLionel Sambuc 13287eb99bdaSLionel Sambuc #if NETDEV 13297eb99bdaSLionel Sambuc static int netdev_open(struct net_device *); 13307eb99bdaSLionel Sambuc static int netdev_stop(struct net_device *); 13317eb99bdaSLionel Sambuc static int netdev_start(struct sk_buff *, struct net_device *); 13327eb99bdaSLionel Sambuc # if NAPI 13337eb99bdaSLionel Sambuc static int netdev_poll(struct net_device *, int *); 13347eb99bdaSLionel Sambuc # endif 13357eb99bdaSLionel Sambuc static int netdev_ioctl(struct net_device *, struct ifreq *, int); 13367eb99bdaSLionel Sambuc static int netdev_mtu(struct net_device *, int); 13377eb99bdaSLionel Sambuc static void netdev_timeout(struct net_device *); 13387eb99bdaSLionel Sambuc static struct net_device_stats *netdev_stats(struct net_device *); 13397eb99bdaSLionel Sambuc static void netdev_watchdog(unsigned long); 13407eb99bdaSLionel Sambuc 13417eb99bdaSLionel Sambuc static void netdev_setup(struct net_device *); 13427eb99bdaSLionel Sambuc static int netdev_attach(softc_t *); 13437eb99bdaSLionel Sambuc static void netdev_detach(softc_t *); 13447eb99bdaSLionel Sambuc #endif /* NETDEV */ 13457eb99bdaSLionel Sambuc 13467eb99bdaSLionel Sambuc 13477eb99bdaSLionel Sambuc #if BSD 13487eb99bdaSLionel Sambuc static int create_ring(softc_t *, struct desc_ring *, int); 13497eb99bdaSLionel Sambuc static void destroy_ring(softc_t *, struct desc_ring *); 13507eb99bdaSLionel Sambuc 13517eb99bdaSLionel Sambuc static void mbuf_enqueue(struct desc_ring *, struct mbuf *); 13527eb99bdaSLionel Sambuc static struct mbuf *mbuf_dequeue(struct desc_ring *); 13537eb99bdaSLionel Sambuc 13547eb99bdaSLionel Sambuc static int rxintr_cleanup(softc_t *); 13557eb99bdaSLionel Sambuc static int rxintr_setup(softc_t *); 13567eb99bdaSLionel Sambuc static int txintr_cleanup(softc_t *); 13577eb99bdaSLionel Sambuc static int txintr_setup_mbuf(softc_t *, struct mbuf *); 13587eb99bdaSLionel Sambuc static int txintr_setup(softc_t *); 13597eb99bdaSLionel Sambuc 13607eb99bdaSLionel Sambuc static intr_return_t bsd_interrupt(void *); 13617eb99bdaSLionel Sambuc # if DEVICE_POLLING 13627eb99bdaSLionel Sambuc static void bsd_poll(struct ifnet *, enum poll_cmd, int); 13637eb99bdaSLionel Sambuc # endif 13647eb99bdaSLionel Sambuc #endif /* BSD */ 13657eb99bdaSLionel Sambuc 13667eb99bdaSLionel Sambuc static int open_proto(softc_t *, struct config *); 13677eb99bdaSLionel Sambuc static int attach_stack(softc_t *, struct config *); 13687eb99bdaSLionel Sambuc 13697eb99bdaSLionel Sambuc static int lmc_ioctl(softc_t *, u_long, void *); 13707eb99bdaSLionel Sambuc static void lmc_watchdog(softc_t *); 13717eb99bdaSLionel Sambuc 13727eb99bdaSLionel Sambuc static void set_ready(softc_t *, int); 13737eb99bdaSLionel Sambuc static void reset_cntrs(softc_t *); 13747eb99bdaSLionel Sambuc 13757eb99bdaSLionel Sambuc static void lmc_interrupt(void *, int, int); 13767eb99bdaSLionel Sambuc static void check_intr_status(softc_t *); 13777eb99bdaSLionel Sambuc 13787eb99bdaSLionel Sambuc static int lmc_attach(softc_t *); 13797eb99bdaSLionel Sambuc static void lmc_detach(softc_t *); 13807eb99bdaSLionel Sambuc 13817eb99bdaSLionel Sambuc static void tulip_loop(softc_t *, struct config *); 13827eb99bdaSLionel Sambuc static int tulip_attach(softc_t *); 13837eb99bdaSLionel Sambuc static void tulip_detach(void *); 13847eb99bdaSLionel Sambuc 13857eb99bdaSLionel Sambuc static void print_driver_info(void); 13867eb99bdaSLionel Sambuc 13877eb99bdaSLionel Sambuc static int nbsd_match(device_t, cfdata_t, void *); 13887eb99bdaSLionel Sambuc static void nbsd_attach(device_t, device_t, void *); 13897eb99bdaSLionel Sambuc static int nbsd_detach(device_t, int); 13907eb99bdaSLionel Sambuc 13917eb99bdaSLionel Sambuc #endif /* KERNEL */ 13927eb99bdaSLionel Sambuc 13937eb99bdaSLionel Sambuc #endif /* IF_LMC_H */ 1394