xref: /minix3/sys/arch/i386/include/pmap.h (revision 0a6a1f1d05b60e214de2f05a7310ddd1f0e590e7)
1*0a6a1f1dSLionel Sambuc /*	$NetBSD: pmap.h,v 1.117 2014/04/21 19:12:11 christos Exp $	*/
2*0a6a1f1dSLionel Sambuc 
3*0a6a1f1dSLionel Sambuc /*
4*0a6a1f1dSLionel Sambuc  * Copyright (c) 1997 Charles D. Cranor and Washington University.
5*0a6a1f1dSLionel Sambuc  * All rights reserved.
6*0a6a1f1dSLionel Sambuc  *
7*0a6a1f1dSLionel Sambuc  * Redistribution and use in source and binary forms, with or without
8*0a6a1f1dSLionel Sambuc  * modification, are permitted provided that the following conditions
9*0a6a1f1dSLionel Sambuc  * are met:
10*0a6a1f1dSLionel Sambuc  * 1. Redistributions of source code must retain the above copyright
11*0a6a1f1dSLionel Sambuc  *    notice, this list of conditions and the following disclaimer.
12*0a6a1f1dSLionel Sambuc  * 2. Redistributions in binary form must reproduce the above copyright
13*0a6a1f1dSLionel Sambuc  *    notice, this list of conditions and the following disclaimer in the
14*0a6a1f1dSLionel Sambuc  *    documentation and/or other materials provided with the distribution.
15*0a6a1f1dSLionel Sambuc  *
16*0a6a1f1dSLionel Sambuc  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17*0a6a1f1dSLionel Sambuc  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18*0a6a1f1dSLionel Sambuc  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19*0a6a1f1dSLionel Sambuc  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20*0a6a1f1dSLionel Sambuc  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21*0a6a1f1dSLionel Sambuc  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22*0a6a1f1dSLionel Sambuc  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23*0a6a1f1dSLionel Sambuc  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24*0a6a1f1dSLionel Sambuc  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25*0a6a1f1dSLionel Sambuc  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26*0a6a1f1dSLionel Sambuc  */
27*0a6a1f1dSLionel Sambuc 
28*0a6a1f1dSLionel Sambuc /*
29*0a6a1f1dSLionel Sambuc  * Copyright (c) 2001 Wasabi Systems, Inc.
30*0a6a1f1dSLionel Sambuc  * All rights reserved.
31*0a6a1f1dSLionel Sambuc  *
32*0a6a1f1dSLionel Sambuc  * Written by Frank van der Linden for Wasabi Systems, Inc.
33*0a6a1f1dSLionel Sambuc  *
34*0a6a1f1dSLionel Sambuc  * Redistribution and use in source and binary forms, with or without
35*0a6a1f1dSLionel Sambuc  * modification, are permitted provided that the following conditions
36*0a6a1f1dSLionel Sambuc  * are met:
37*0a6a1f1dSLionel Sambuc  * 1. Redistributions of source code must retain the above copyright
38*0a6a1f1dSLionel Sambuc  *    notice, this list of conditions and the following disclaimer.
39*0a6a1f1dSLionel Sambuc  * 2. Redistributions in binary form must reproduce the above copyright
40*0a6a1f1dSLionel Sambuc  *    notice, this list of conditions and the following disclaimer in the
41*0a6a1f1dSLionel Sambuc  *    documentation and/or other materials provided with the distribution.
42*0a6a1f1dSLionel Sambuc  * 3. All advertising materials mentioning features or use of this software
43*0a6a1f1dSLionel Sambuc  *    must display the following acknowledgement:
44*0a6a1f1dSLionel Sambuc  *      This product includes software developed for the NetBSD Project by
45*0a6a1f1dSLionel Sambuc  *      Wasabi Systems, Inc.
46*0a6a1f1dSLionel Sambuc  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
47*0a6a1f1dSLionel Sambuc  *    or promote products derived from this software without specific prior
48*0a6a1f1dSLionel Sambuc  *    written permission.
49*0a6a1f1dSLionel Sambuc  *
50*0a6a1f1dSLionel Sambuc  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
51*0a6a1f1dSLionel Sambuc  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
52*0a6a1f1dSLionel Sambuc  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
53*0a6a1f1dSLionel Sambuc  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
54*0a6a1f1dSLionel Sambuc  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55*0a6a1f1dSLionel Sambuc  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56*0a6a1f1dSLionel Sambuc  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57*0a6a1f1dSLionel Sambuc  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58*0a6a1f1dSLionel Sambuc  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59*0a6a1f1dSLionel Sambuc  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60*0a6a1f1dSLionel Sambuc  * POSSIBILITY OF SUCH DAMAGE.
61*0a6a1f1dSLionel Sambuc  */
62*0a6a1f1dSLionel Sambuc 
63*0a6a1f1dSLionel Sambuc #ifndef	_I386_PMAP_H_
64*0a6a1f1dSLionel Sambuc #define	_I386_PMAP_H_
65*0a6a1f1dSLionel Sambuc 
66*0a6a1f1dSLionel Sambuc #if defined(_KERNEL_OPT)
67*0a6a1f1dSLionel Sambuc #include "opt_user_ldt.h"
68*0a6a1f1dSLionel Sambuc #include "opt_xen.h"
69*0a6a1f1dSLionel Sambuc #endif
70*0a6a1f1dSLionel Sambuc 
71*0a6a1f1dSLionel Sambuc #include <sys/atomic.h>
72*0a6a1f1dSLionel Sambuc 
73*0a6a1f1dSLionel Sambuc #include <i386/pte.h>
74*0a6a1f1dSLionel Sambuc #include <machine/segments.h>
75*0a6a1f1dSLionel Sambuc #if defined(_KERNEL)
76*0a6a1f1dSLionel Sambuc #include <machine/cpufunc.h>
77*0a6a1f1dSLionel Sambuc #endif
78*0a6a1f1dSLionel Sambuc 
79*0a6a1f1dSLionel Sambuc #include <uvm/uvm_object.h>
80*0a6a1f1dSLionel Sambuc #ifdef XEN
81*0a6a1f1dSLionel Sambuc #include <xen/xenfunc.h>
82*0a6a1f1dSLionel Sambuc #include <xen/xenpmap.h>
83*0a6a1f1dSLionel Sambuc #endif /* XEN */
84*0a6a1f1dSLionel Sambuc 
85*0a6a1f1dSLionel Sambuc /*
86*0a6a1f1dSLionel Sambuc  * see pte.h for a description of i386 MMU terminology and hardware
87*0a6a1f1dSLionel Sambuc  * interface.
88*0a6a1f1dSLionel Sambuc  *
89*0a6a1f1dSLionel Sambuc  * a pmap describes a processes' 4GB virtual address space.  when PAE
90*0a6a1f1dSLionel Sambuc  * is not in use, this virtual address space can be broken up into 1024 4MB
91*0a6a1f1dSLionel Sambuc  * regions which are described by PDEs in the PDP.  the PDEs are defined as
92*0a6a1f1dSLionel Sambuc  * follows:
93*0a6a1f1dSLionel Sambuc  *
94*0a6a1f1dSLionel Sambuc  * (ranges are inclusive -> exclusive, just like vm_map_entry start/end)
95*0a6a1f1dSLionel Sambuc  * (the following assumes that KERNBASE is 0xc0000000)
96*0a6a1f1dSLionel Sambuc  *
97*0a6a1f1dSLionel Sambuc  * PDE#s	VA range		usage
98*0a6a1f1dSLionel Sambuc  * 0->766	0x0 -> 0xbfc00000	user address space
99*0a6a1f1dSLionel Sambuc  * 767		0xbfc00000->		recursive mapping of PDP (used for
100*0a6a1f1dSLionel Sambuc  *			0xc0000000	linear mapping of PTPs)
101*0a6a1f1dSLionel Sambuc  * 768->1023	0xc0000000->		kernel address space (constant
102*0a6a1f1dSLionel Sambuc  *			0xffc00000	across all pmap's/processes)
103*0a6a1f1dSLionel Sambuc  *			<end>
104*0a6a1f1dSLionel Sambuc  *
105*0a6a1f1dSLionel Sambuc  *
106*0a6a1f1dSLionel Sambuc  * note: a recursive PDP mapping provides a way to map all the PTEs for
107*0a6a1f1dSLionel Sambuc  * a 4GB address space into a linear chunk of virtual memory.  in other
108*0a6a1f1dSLionel Sambuc  * words, the PTE for page 0 is the first int mapped into the 4MB recursive
109*0a6a1f1dSLionel Sambuc  * area.  the PTE for page 1 is the second int.  the very last int in the
110*0a6a1f1dSLionel Sambuc  * 4MB range is the PTE that maps VA 0xfffff000 (the last page in a 4GB
111*0a6a1f1dSLionel Sambuc  * address).
112*0a6a1f1dSLionel Sambuc  *
113*0a6a1f1dSLionel Sambuc  * all pmap's PD's must have the same values in slots 768->1023 so that
114*0a6a1f1dSLionel Sambuc  * the kernel is always mapped in every process.  these values are loaded
115*0a6a1f1dSLionel Sambuc  * into the PD at pmap creation time.
116*0a6a1f1dSLionel Sambuc  *
117*0a6a1f1dSLionel Sambuc  * at any one time only one pmap can be active on a processor.  this is
118*0a6a1f1dSLionel Sambuc  * the pmap whose PDP is pointed to by processor register %cr3.  this pmap
119*0a6a1f1dSLionel Sambuc  * will have all its PTEs mapped into memory at the recursive mapping
120*0a6a1f1dSLionel Sambuc  * point (slot #767 as show above).  when the pmap code wants to find the
121*0a6a1f1dSLionel Sambuc  * PTE for a virtual address, all it has to do is the following:
122*0a6a1f1dSLionel Sambuc  *
123*0a6a1f1dSLionel Sambuc  * address of PTE = (767 * 4MB) + (VA / PAGE_SIZE) * sizeof(pt_entry_t)
124*0a6a1f1dSLionel Sambuc  *                = 0xbfc00000 + (VA / 4096) * 4
125*0a6a1f1dSLionel Sambuc  *
126*0a6a1f1dSLionel Sambuc  * what happens if the pmap layer is asked to perform an operation
127*0a6a1f1dSLionel Sambuc  * on a pmap that is not the one which is currently active?  in that
128*0a6a1f1dSLionel Sambuc  * case we temporarily load this pmap, perform the operation, and mark
129*0a6a1f1dSLionel Sambuc  * the currently active one as pending lazy reload.
130*0a6a1f1dSLionel Sambuc  *
131*0a6a1f1dSLionel Sambuc  * the following figure shows the effects of the recursive PDP mapping:
132*0a6a1f1dSLionel Sambuc  *
133*0a6a1f1dSLionel Sambuc  *   PDP (%cr3)
134*0a6a1f1dSLionel Sambuc  *   +----+
135*0a6a1f1dSLionel Sambuc  *   |   0| -> PTP#0 that maps VA 0x0 -> 0x400000
136*0a6a1f1dSLionel Sambuc  *   |    |
137*0a6a1f1dSLionel Sambuc  *   |    |
138*0a6a1f1dSLionel Sambuc  *   | 767| -> points back to PDP (%cr3) mapping VA 0xbfc00000 -> 0xc0000000
139*0a6a1f1dSLionel Sambuc  *   | 768| -> first kernel PTP (maps 0xc0000000 -> 0xc0400000)
140*0a6a1f1dSLionel Sambuc  *   |    |
141*0a6a1f1dSLionel Sambuc  *   +----+
142*0a6a1f1dSLionel Sambuc  *
143*0a6a1f1dSLionel Sambuc  * note that the PDE#767 VA (0xbfc00000) is defined as "PTE_BASE"
144*0a6a1f1dSLionel Sambuc  *
145*0a6a1f1dSLionel Sambuc  * starting at VA 0xbfc00000 the current active PDP (%cr3) acts as a
146*0a6a1f1dSLionel Sambuc  * PTP:
147*0a6a1f1dSLionel Sambuc  *
148*0a6a1f1dSLionel Sambuc  * PTP#767 == PDP(%cr3) => maps VA 0xbfc00000 -> 0xc0000000
149*0a6a1f1dSLionel Sambuc  *   +----+
150*0a6a1f1dSLionel Sambuc  *   |   0| -> maps the contents of PTP#0 at VA 0xbfc00000->0xbfc01000
151*0a6a1f1dSLionel Sambuc  *   |    |
152*0a6a1f1dSLionel Sambuc  *   |    |
153*0a6a1f1dSLionel Sambuc  *   | 767| -> maps contents of PTP#767 (the PDP) at VA 0xbfeff000
154*0a6a1f1dSLionel Sambuc  *   | 768| -> maps contents of first kernel PTP
155*0a6a1f1dSLionel Sambuc  *   |    |
156*0a6a1f1dSLionel Sambuc  *   |1023|
157*0a6a1f1dSLionel Sambuc  *   +----+
158*0a6a1f1dSLionel Sambuc  *
159*0a6a1f1dSLionel Sambuc  * note that mapping of the PDP at PTP#767's VA (0xbfeff000) is
160*0a6a1f1dSLionel Sambuc  * defined as "PDP_BASE".... within that mapping there are two
161*0a6a1f1dSLionel Sambuc  * defines:
162*0a6a1f1dSLionel Sambuc  *   "PDP_PDE" (0xbfeffbfc) is the VA of the PDE in the PDP
163*0a6a1f1dSLionel Sambuc  *      which points back to itself.
164*0a6a1f1dSLionel Sambuc  *
165*0a6a1f1dSLionel Sambuc  * - PAE support -
166*0a6a1f1dSLionel Sambuc  * ---------------
167*0a6a1f1dSLionel Sambuc  *
168*0a6a1f1dSLionel Sambuc  * PAE adds another layer of indirection during address translation, breaking
169*0a6a1f1dSLionel Sambuc  * up the translation process in 3 different levels:
170*0a6a1f1dSLionel Sambuc  * - L3 page directory, containing 4 * 64-bits addresses (index determined by
171*0a6a1f1dSLionel Sambuc  * bits [31:30] from the virtual address). This breaks up the address space
172*0a6a1f1dSLionel Sambuc  * in 4 1GB regions.
173*0a6a1f1dSLionel Sambuc  * - the PD (L2), containing 512 64-bits addresses, breaking each L3 region
174*0a6a1f1dSLionel Sambuc  * in 512 * 2MB regions.
175*0a6a1f1dSLionel Sambuc  * - the PT (L1), also containing 512 64-bits addresses (at L1, the size of
176*0a6a1f1dSLionel Sambuc  * the pages is still 4K).
177*0a6a1f1dSLionel Sambuc  *
178*0a6a1f1dSLionel Sambuc  * The kernel virtual space is mapped by the last entry in the L3 page,
179*0a6a1f1dSLionel Sambuc  * the first 3 entries mapping the user VA space.
180*0a6a1f1dSLionel Sambuc  *
181*0a6a1f1dSLionel Sambuc  * Because the L3 has only 4 entries of 1GB each, we can't use recursive
182*0a6a1f1dSLionel Sambuc  * mappings at this level for PDP_PDE (this would eat up 2 of the 4GB
183*0a6a1f1dSLionel Sambuc  * virtual space). There are also restrictions imposed by Xen on the
184*0a6a1f1dSLionel Sambuc  * last entry of the L3 PD (reference count to this page cannot be
185*0a6a1f1dSLionel Sambuc  * bigger than 1), which makes it hard to use one L3 page per pmap to
186*0a6a1f1dSLionel Sambuc  * switch between pmaps using %cr3.
187*0a6a1f1dSLionel Sambuc  *
188*0a6a1f1dSLionel Sambuc  * As such, each CPU gets its own L3 page that is always loaded into its %cr3
189*0a6a1f1dSLionel Sambuc  * (ci_pae_l3_pd in the associated cpu_info struct). We claim that the VM has
190*0a6a1f1dSLionel Sambuc  * only a 2-level PTP (similar to the non-PAE case). L2 PD is now 4 contiguous
191*0a6a1f1dSLionel Sambuc  * pages long (corresponding to the 4 entries of the L3), and the different
192*0a6a1f1dSLionel Sambuc  * index/slots (like PDP_PDE) are adapted accordingly.
193*0a6a1f1dSLionel Sambuc  *
194*0a6a1f1dSLionel Sambuc  * Kernel space remains in L3[3], L3[0-2] maps the user VA space. Switching
195*0a6a1f1dSLionel Sambuc  * between pmaps consists in modifying the first 3 entries of the CPU's L3 page.
196*0a6a1f1dSLionel Sambuc  *
197*0a6a1f1dSLionel Sambuc  * PTE_BASE will need 4 entries in the L2 PD pages to map the L2 pages
198*0a6a1f1dSLionel Sambuc  * recursively.
199*0a6a1f1dSLionel Sambuc  *
200*0a6a1f1dSLionel Sambuc  * In addition, for Xen, we can't recursively map L3[3] (Xen wants the ref
201*0a6a1f1dSLionel Sambuc  * count on this page to be exactly one), so we use a shadow PD page for
202*0a6a1f1dSLionel Sambuc  * the last L2 PD. The shadow page could be static too, but to make pm_pdir[]
203*0a6a1f1dSLionel Sambuc  * contiguous we'll allocate/copy one page per pmap.
204*0a6a1f1dSLionel Sambuc  */
205*0a6a1f1dSLionel Sambuc 
206*0a6a1f1dSLionel Sambuc /*
207*0a6a1f1dSLionel Sambuc  * Mask to get rid of the sign-extended part of addresses.
208*0a6a1f1dSLionel Sambuc  */
209*0a6a1f1dSLionel Sambuc #define VA_SIGN_MASK		0
210*0a6a1f1dSLionel Sambuc #define VA_SIGN_NEG(va)		((va) | VA_SIGN_MASK)
211*0a6a1f1dSLionel Sambuc /*
212*0a6a1f1dSLionel Sambuc  * XXXfvdl this one's not right.
213*0a6a1f1dSLionel Sambuc  */
214*0a6a1f1dSLionel Sambuc #define VA_SIGN_POS(va)		((va) & ~VA_SIGN_MASK)
215*0a6a1f1dSLionel Sambuc 
216*0a6a1f1dSLionel Sambuc /*
217*0a6a1f1dSLionel Sambuc  * the following defines identify the slots used as described above.
218*0a6a1f1dSLionel Sambuc  */
219*0a6a1f1dSLionel Sambuc #ifdef PAE
220*0a6a1f1dSLionel Sambuc #define L2_SLOT_PTE	(KERNBASE/NBPD_L2-4) /* 1532: for recursive PDP map */
221*0a6a1f1dSLionel Sambuc #define L2_SLOT_KERN	(KERNBASE/NBPD_L2)   /* 1536: start of kernel space */
222*0a6a1f1dSLionel Sambuc #else /* PAE */
223*0a6a1f1dSLionel Sambuc #define L2_SLOT_PTE	(KERNBASE/NBPD_L2-1) /* 767: for recursive PDP map */
224*0a6a1f1dSLionel Sambuc #define L2_SLOT_KERN	(KERNBASE/NBPD_L2)   /* 768: start of kernel space */
225*0a6a1f1dSLionel Sambuc #endif /* PAE */
226*0a6a1f1dSLionel Sambuc 
227*0a6a1f1dSLionel Sambuc #define	L2_SLOT_KERNBASE L2_SLOT_KERN
228*0a6a1f1dSLionel Sambuc 
229*0a6a1f1dSLionel Sambuc #define PDIR_SLOT_KERN	L2_SLOT_KERN
230*0a6a1f1dSLionel Sambuc #define PDIR_SLOT_PTE	L2_SLOT_PTE
231*0a6a1f1dSLionel Sambuc 
232*0a6a1f1dSLionel Sambuc /*
233*0a6a1f1dSLionel Sambuc  * the following defines give the virtual addresses of various MMU
234*0a6a1f1dSLionel Sambuc  * data structures:
235*0a6a1f1dSLionel Sambuc  * PTE_BASE: the base VA of the linear PTE mappings
236*0a6a1f1dSLionel Sambuc  * PDP_BASE: the base VA of the recursive mapping of the PDP
237*0a6a1f1dSLionel Sambuc  * PDP_PDE: the VA of the PDE that points back to the PDP
238*0a6a1f1dSLionel Sambuc  */
239*0a6a1f1dSLionel Sambuc 
240*0a6a1f1dSLionel Sambuc #define PTE_BASE  ((pt_entry_t *) (PDIR_SLOT_PTE * NBPD_L2))
241*0a6a1f1dSLionel Sambuc 
242*0a6a1f1dSLionel Sambuc #define L1_BASE		PTE_BASE
243*0a6a1f1dSLionel Sambuc 
244*0a6a1f1dSLionel Sambuc #define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L2_SLOT_PTE * NBPD_L1))
245*0a6a1f1dSLionel Sambuc 
246*0a6a1f1dSLionel Sambuc #define PDP_PDE		(L2_BASE + PDIR_SLOT_PTE)
247*0a6a1f1dSLionel Sambuc 
248*0a6a1f1dSLionel Sambuc #define PDP_BASE	L2_BASE
249*0a6a1f1dSLionel Sambuc 
250*0a6a1f1dSLionel Sambuc /* largest value (-1 for APTP space) */
251*0a6a1f1dSLionel Sambuc #define NKL2_MAX_ENTRIES	(NTOPLEVEL_PDES - (KERNBASE/NBPD_L2) - 1)
252*0a6a1f1dSLionel Sambuc #define NKL1_MAX_ENTRIES	(unsigned long)(NKL2_MAX_ENTRIES * NPDPG)
253*0a6a1f1dSLionel Sambuc 
254*0a6a1f1dSLionel Sambuc #define NKL2_KIMG_ENTRIES	0	/* XXX unused */
255*0a6a1f1dSLionel Sambuc 
256*0a6a1f1dSLionel Sambuc #define NKL2_START_ENTRIES	0	/* XXX computed on runtime */
257*0a6a1f1dSLionel Sambuc #define NKL1_START_ENTRIES	0	/* XXX unused */
258*0a6a1f1dSLionel Sambuc 
259*0a6a1f1dSLionel Sambuc #ifndef XEN
260*0a6a1f1dSLionel Sambuc #define NTOPLEVEL_PDES		(PAGE_SIZE * PDP_SIZE / (sizeof (pd_entry_t)))
261*0a6a1f1dSLionel Sambuc #else	/* !XEN */
262*0a6a1f1dSLionel Sambuc #ifdef  PAE
263*0a6a1f1dSLionel Sambuc #define NTOPLEVEL_PDES		1964	/* 1964-2047 reserved by Xen */
264*0a6a1f1dSLionel Sambuc #else	/* PAE */
265*0a6a1f1dSLionel Sambuc #define NTOPLEVEL_PDES		1008	/* 1008-1023 reserved by Xen */
266*0a6a1f1dSLionel Sambuc #endif	/* PAE */
267*0a6a1f1dSLionel Sambuc #endif  /* !XEN */
268*0a6a1f1dSLionel Sambuc #define NPDPG			(PAGE_SIZE / sizeof (pd_entry_t))
269*0a6a1f1dSLionel Sambuc 
270*0a6a1f1dSLionel Sambuc #define PTP_MASK_INITIALIZER	{ L1_FRAME, L2_FRAME }
271*0a6a1f1dSLionel Sambuc #define PTP_SHIFT_INITIALIZER	{ L1_SHIFT, L2_SHIFT }
272*0a6a1f1dSLionel Sambuc #define NKPTP_INITIALIZER	{ NKL1_START_ENTRIES, NKL2_START_ENTRIES }
273*0a6a1f1dSLionel Sambuc #define NKPTPMAX_INITIALIZER	{ NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES }
274*0a6a1f1dSLionel Sambuc #define NBPD_INITIALIZER	{ NBPD_L1, NBPD_L2 }
275*0a6a1f1dSLionel Sambuc #define PDES_INITIALIZER	{ L2_BASE }
276*0a6a1f1dSLionel Sambuc 
277*0a6a1f1dSLionel Sambuc #define PTP_LEVELS	2
278*0a6a1f1dSLionel Sambuc 
279*0a6a1f1dSLionel Sambuc /*
280*0a6a1f1dSLionel Sambuc  * PG_AVAIL usage: we make use of the ignored bits of the PTE
281*0a6a1f1dSLionel Sambuc  */
282*0a6a1f1dSLionel Sambuc 
283*0a6a1f1dSLionel Sambuc #define PG_W		PG_AVAIL1	/* "wired" mapping */
284*0a6a1f1dSLionel Sambuc #define PG_PVLIST	PG_AVAIL2	/* mapping has entry on pvlist */
285*0a6a1f1dSLionel Sambuc #define PG_X		PG_AVAIL3	/* executable mapping */
286*0a6a1f1dSLionel Sambuc 
287*0a6a1f1dSLionel Sambuc /*
288*0a6a1f1dSLionel Sambuc  * Number of PTE's per cache line.  4 byte pte, 32-byte cache line
289*0a6a1f1dSLionel Sambuc  * Used to avoid false sharing of cache lines.
290*0a6a1f1dSLionel Sambuc  */
291*0a6a1f1dSLionel Sambuc #ifdef PAE
292*0a6a1f1dSLionel Sambuc #define NPTECL		4
293*0a6a1f1dSLionel Sambuc #else
294*0a6a1f1dSLionel Sambuc #define NPTECL		8
295*0a6a1f1dSLionel Sambuc #endif
296*0a6a1f1dSLionel Sambuc 
297*0a6a1f1dSLionel Sambuc #include <x86/pmap.h>
298*0a6a1f1dSLionel Sambuc 
299*0a6a1f1dSLionel Sambuc #ifndef XEN
300*0a6a1f1dSLionel Sambuc #define pmap_pa2pte(a)			(a)
301*0a6a1f1dSLionel Sambuc #define pmap_pte2pa(a)			((a) & PG_FRAME)
302*0a6a1f1dSLionel Sambuc #define pmap_pte_set(p, n)		do { *(p) = (n); } while (0)
303*0a6a1f1dSLionel Sambuc #define pmap_pte_flush()		/* nothing */
304*0a6a1f1dSLionel Sambuc 
305*0a6a1f1dSLionel Sambuc #ifdef PAE
306*0a6a1f1dSLionel Sambuc #define pmap_pte_cas(p, o, n)		atomic_cas_64((p), (o), (n))
307*0a6a1f1dSLionel Sambuc #define pmap_pte_testset(p, n)		\
308*0a6a1f1dSLionel Sambuc     atomic_swap_64((volatile uint64_t *)p, n)
309*0a6a1f1dSLionel Sambuc #define pmap_pte_setbits(p, b)		\
310*0a6a1f1dSLionel Sambuc     atomic_or_64((volatile uint64_t *)p, b)
311*0a6a1f1dSLionel Sambuc #define pmap_pte_clearbits(p, b)	\
312*0a6a1f1dSLionel Sambuc     atomic_and_64((volatile uint64_t *)p, ~(b))
313*0a6a1f1dSLionel Sambuc #else /* PAE */
314*0a6a1f1dSLionel Sambuc #define pmap_pte_cas(p, o, n)		atomic_cas_32((p), (o), (n))
315*0a6a1f1dSLionel Sambuc #define pmap_pte_testset(p, n)		\
316*0a6a1f1dSLionel Sambuc     atomic_swap_ulong((volatile unsigned long *)p, n)
317*0a6a1f1dSLionel Sambuc #define pmap_pte_setbits(p, b)		\
318*0a6a1f1dSLionel Sambuc     atomic_or_ulong((volatile unsigned long *)p, b)
319*0a6a1f1dSLionel Sambuc #define pmap_pte_clearbits(p, b)	\
320*0a6a1f1dSLionel Sambuc     atomic_and_ulong((volatile unsigned long *)p, ~(b))
321*0a6a1f1dSLionel Sambuc #endif /* PAE */
322*0a6a1f1dSLionel Sambuc 
323*0a6a1f1dSLionel Sambuc #else /* XEN */
324*0a6a1f1dSLionel Sambuc extern kmutex_t pte_lock;
325*0a6a1f1dSLionel Sambuc 
326*0a6a1f1dSLionel Sambuc static __inline pt_entry_t
pmap_pa2pte(paddr_t pa)327*0a6a1f1dSLionel Sambuc pmap_pa2pte(paddr_t pa)
328*0a6a1f1dSLionel Sambuc {
329*0a6a1f1dSLionel Sambuc 	return (pt_entry_t)xpmap_ptom_masked(pa);
330*0a6a1f1dSLionel Sambuc }
331*0a6a1f1dSLionel Sambuc 
332*0a6a1f1dSLionel Sambuc static __inline paddr_t
pmap_pte2pa(pt_entry_t pte)333*0a6a1f1dSLionel Sambuc pmap_pte2pa(pt_entry_t pte)
334*0a6a1f1dSLionel Sambuc {
335*0a6a1f1dSLionel Sambuc 	return xpmap_mtop_masked(pte & PG_FRAME);
336*0a6a1f1dSLionel Sambuc }
337*0a6a1f1dSLionel Sambuc static __inline void
pmap_pte_set(pt_entry_t * pte,pt_entry_t npte)338*0a6a1f1dSLionel Sambuc pmap_pte_set(pt_entry_t *pte, pt_entry_t npte)
339*0a6a1f1dSLionel Sambuc {
340*0a6a1f1dSLionel Sambuc 	int s = splvm();
341*0a6a1f1dSLionel Sambuc 	xpq_queue_pte_update(xpmap_ptetomach(pte), npte);
342*0a6a1f1dSLionel Sambuc 	splx(s);
343*0a6a1f1dSLionel Sambuc }
344*0a6a1f1dSLionel Sambuc 
345*0a6a1f1dSLionel Sambuc static __inline pt_entry_t
pmap_pte_cas(volatile pt_entry_t * ptep,pt_entry_t o,pt_entry_t n)346*0a6a1f1dSLionel Sambuc pmap_pte_cas(volatile pt_entry_t *ptep, pt_entry_t o, pt_entry_t n)
347*0a6a1f1dSLionel Sambuc {
348*0a6a1f1dSLionel Sambuc 	pt_entry_t opte;
349*0a6a1f1dSLionel Sambuc 
350*0a6a1f1dSLionel Sambuc 	mutex_enter(&pte_lock);
351*0a6a1f1dSLionel Sambuc 	opte = *ptep;
352*0a6a1f1dSLionel Sambuc 	if (opte == o) {
353*0a6a1f1dSLionel Sambuc 		xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(ptep)), n);
354*0a6a1f1dSLionel Sambuc 		xpq_flush_queue();
355*0a6a1f1dSLionel Sambuc 	}
356*0a6a1f1dSLionel Sambuc 	mutex_exit(&pte_lock);
357*0a6a1f1dSLionel Sambuc 	return opte;
358*0a6a1f1dSLionel Sambuc }
359*0a6a1f1dSLionel Sambuc 
360*0a6a1f1dSLionel Sambuc static __inline pt_entry_t
pmap_pte_testset(volatile pt_entry_t * pte,pt_entry_t npte)361*0a6a1f1dSLionel Sambuc pmap_pte_testset(volatile pt_entry_t *pte, pt_entry_t npte)
362*0a6a1f1dSLionel Sambuc {
363*0a6a1f1dSLionel Sambuc 	pt_entry_t opte;
364*0a6a1f1dSLionel Sambuc 
365*0a6a1f1dSLionel Sambuc 	mutex_enter(&pte_lock);
366*0a6a1f1dSLionel Sambuc 	opte = *pte;
367*0a6a1f1dSLionel Sambuc 	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)),
368*0a6a1f1dSLionel Sambuc 	    npte);
369*0a6a1f1dSLionel Sambuc 	xpq_flush_queue();
370*0a6a1f1dSLionel Sambuc 	mutex_exit(&pte_lock);
371*0a6a1f1dSLionel Sambuc 	return opte;
372*0a6a1f1dSLionel Sambuc }
373*0a6a1f1dSLionel Sambuc 
374*0a6a1f1dSLionel Sambuc static __inline void
pmap_pte_setbits(volatile pt_entry_t * pte,pt_entry_t bits)375*0a6a1f1dSLionel Sambuc pmap_pte_setbits(volatile pt_entry_t *pte, pt_entry_t bits)
376*0a6a1f1dSLionel Sambuc {
377*0a6a1f1dSLionel Sambuc 	mutex_enter(&pte_lock);
378*0a6a1f1dSLionel Sambuc 	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), (*pte) | bits);
379*0a6a1f1dSLionel Sambuc 	xpq_flush_queue();
380*0a6a1f1dSLionel Sambuc 	mutex_exit(&pte_lock);
381*0a6a1f1dSLionel Sambuc }
382*0a6a1f1dSLionel Sambuc 
383*0a6a1f1dSLionel Sambuc static __inline void
pmap_pte_clearbits(volatile pt_entry_t * pte,pt_entry_t bits)384*0a6a1f1dSLionel Sambuc pmap_pte_clearbits(volatile pt_entry_t *pte, pt_entry_t bits)
385*0a6a1f1dSLionel Sambuc {
386*0a6a1f1dSLionel Sambuc 	mutex_enter(&pte_lock);
387*0a6a1f1dSLionel Sambuc 	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)),
388*0a6a1f1dSLionel Sambuc 	    (*pte) & ~bits);
389*0a6a1f1dSLionel Sambuc 	xpq_flush_queue();
390*0a6a1f1dSLionel Sambuc 	mutex_exit(&pte_lock);
391*0a6a1f1dSLionel Sambuc }
392*0a6a1f1dSLionel Sambuc 
393*0a6a1f1dSLionel Sambuc static __inline void
pmap_pte_flush(void)394*0a6a1f1dSLionel Sambuc pmap_pte_flush(void)
395*0a6a1f1dSLionel Sambuc {
396*0a6a1f1dSLionel Sambuc 	int s = splvm();
397*0a6a1f1dSLionel Sambuc 	xpq_flush_queue();
398*0a6a1f1dSLionel Sambuc 	splx(s);
399*0a6a1f1dSLionel Sambuc }
400*0a6a1f1dSLionel Sambuc 
401*0a6a1f1dSLionel Sambuc #endif
402*0a6a1f1dSLionel Sambuc 
403*0a6a1f1dSLionel Sambuc struct vm_map;
404*0a6a1f1dSLionel Sambuc struct trapframe;
405*0a6a1f1dSLionel Sambuc struct pcb;
406*0a6a1f1dSLionel Sambuc 
407*0a6a1f1dSLionel Sambuc int	pmap_exec_fixup(struct vm_map *, struct trapframe *, struct pcb *);
408*0a6a1f1dSLionel Sambuc void	pmap_ldt_cleanup(struct lwp *);
409*0a6a1f1dSLionel Sambuc 
410*0a6a1f1dSLionel Sambuc #include <x86/pmap_pv.h>
411*0a6a1f1dSLionel Sambuc 
412*0a6a1f1dSLionel Sambuc #define	__HAVE_VM_PAGE_MD
413*0a6a1f1dSLionel Sambuc #define	VM_MDPAGE_INIT(pg) \
414*0a6a1f1dSLionel Sambuc 	memset(&(pg)->mdpage, 0, sizeof((pg)->mdpage)); \
415*0a6a1f1dSLionel Sambuc 	PMAP_PAGE_INIT(&(pg)->mdpage.mp_pp)
416*0a6a1f1dSLionel Sambuc 
417*0a6a1f1dSLionel Sambuc struct vm_page_md {
418*0a6a1f1dSLionel Sambuc 	struct pmap_page mp_pp;
419*0a6a1f1dSLionel Sambuc };
420*0a6a1f1dSLionel Sambuc 
421*0a6a1f1dSLionel Sambuc #endif	/* _I386_PMAP_H_ */
422