xref: /minix3/minix/kernel/arch/i386/serial.h (revision 433d6423c39e34ec4b79c950597bb2d236f886be)
1*433d6423SLionel Sambuc 
2*433d6423SLionel Sambuc #ifndef _KERN_SERIAL_H
3*433d6423SLionel Sambuc #define _KERN_SERIAL_H 1
4*433d6423SLionel Sambuc 
5*433d6423SLionel Sambuc #define THRREG  0	/* transmitter holding, write-only, DLAB must be clear */
6*433d6423SLionel Sambuc #define RBRREG  0	/* receiver buffer, read-only, DLAB must be clear */
7*433d6423SLionel Sambuc #define DLLREG  0	/* divisor latch LSB, read/write, DLAB must be set */
8*433d6423SLionel Sambuc #define DLMREG  1	/* divisor latch MSB, read/write, DLAB must be set */
9*433d6423SLionel Sambuc #define FICRREG 2	/* FIFO control, write-only */
10*433d6423SLionel Sambuc #define LCRREG  3	/* line control, read/write */
11*433d6423SLionel Sambuc #define LSRREG  5	/* line status, read-only */
12*433d6423SLionel Sambuc #define SPRREG  7
13*433d6423SLionel Sambuc 
14*433d6423SLionel Sambuc #define COM1_BASE	0x3F8
15*433d6423SLionel Sambuc #define COM1_THR	(COM1_BASE + THRREG)
16*433d6423SLionel Sambuc #define COM1_RBR	(COM1_BASE + RBRREG)
17*433d6423SLionel Sambuc #define COM1_DLL	(COM1_BASE + DLLREG)
18*433d6423SLionel Sambuc #define COM1_DLM	(COM1_BASE + DLMREG)
19*433d6423SLionel Sambuc #define COM1_LCR	(COM1_BASE + LCRREG)
20*433d6423SLionel Sambuc #define         LCR_5BIT	0x00 /* 5 bits per data word */
21*433d6423SLionel Sambuc #define         LCR_6BIT	0x01 /* 6 bits per data word */
22*433d6423SLionel Sambuc #define         LCR_7BIT	0x02 /* 7 bits per data word */
23*433d6423SLionel Sambuc #define         LCR_8BIT	0x03 /* 8 bits per data word */
24*433d6423SLionel Sambuc #define         LCR_1STOP	0x00 /* 1/1.5 stop bits */
25*433d6423SLionel Sambuc #define         LCR_2STOP	0x04 /* 2 stop bits */
26*433d6423SLionel Sambuc #define         LCR_NPAR	0x00 /* no parity */
27*433d6423SLionel Sambuc #define         LCR_OPAR	0x08 /* odd parity */
28*433d6423SLionel Sambuc #define         LCR_EPAR	0x18 /* even parity */
29*433d6423SLionel Sambuc #define         LCR_BREAK	0x40 /* enable break */
30*433d6423SLionel Sambuc #define         LCR_DLAB	0x80 /* access DLAB registers */
31*433d6423SLionel Sambuc #define COM1_LSR	(COM1_BASE + LSRREG)
32*433d6423SLionel Sambuc #define         LSR_DR          0x01
33*433d6423SLionel Sambuc #define         LSR_THRE        0x20
34*433d6423SLionel Sambuc #define         LCR_DLA         0x80
35*433d6423SLionel Sambuc 
36*433d6423SLionel Sambuc #define UART_BASE_FREQ	115200U
37*433d6423SLionel Sambuc 
38*433d6423SLionel Sambuc #endif
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