1*433d6423SLionel Sambuc #ifndef _CCNT_H 2*433d6423SLionel Sambuc #define _CCNT_H 3*433d6423SLionel Sambuc 4*433d6423SLionel Sambuc /* ARMV7 PMU (performance monitors) */ 5*433d6423SLionel Sambuc /* ARM ARM B4.1.116 */ 6*433d6423SLionel Sambuc #define PMU_PMCNTENSET_C (1 << 31) /* Enable PMCCNTR cycle counter */ 7*433d6423SLionel Sambuc 8*433d6423SLionel Sambuc /* ARM ARM B4.1.117 PMCR */ 9*433d6423SLionel Sambuc #define PMU_PMCR_DP (1 << 5) /* Disable when ev. cnt. prohibited */ 10*433d6423SLionel Sambuc #define PMU_PMCR_X (1 << 4) /* Export enable */ 11*433d6423SLionel Sambuc #define PMU_PMCR_D (1 << 3) /* Clock divider */ 12*433d6423SLionel Sambuc #define PMU_PMCR_C (1 << 2) /* Cycle counter reset */ 13*433d6423SLionel Sambuc #define PMU_PMCR_P (1 << 1) /* Event counter reset */ 14*433d6423SLionel Sambuc #define PMU_PMCR_E (1 << 0) /* Enable event counters */ 15*433d6423SLionel Sambuc 16*433d6423SLionel Sambuc /* ARM ARM B4.1.119 PMINTENSET */ 17*433d6423SLionel Sambuc #define PMU_PMINTENSET_C (1 << 31) /* PMCCNTR overflow int req. enable*/ 18*433d6423SLionel Sambuc 19*433d6423SLionel Sambuc /* ARM ARM B4.1.124 PMUSERENR */ 20*433d6423SLionel Sambuc #define PMU_PMUSERENR_EN (1 << 0) /* User mode access enable bit */ 21*433d6423SLionel Sambuc 22*433d6423SLionel Sambuc #endif /* _CCNT_H */ 23