1*433d6423SLionel Sambuc #include <sys/types.h>
2*433d6423SLionel Sambuc #include <machine/cpu.h>
3*433d6423SLionel Sambuc #include <minix/type.h>
4*433d6423SLionel Sambuc #include <minix/board.h>
5*433d6423SLionel Sambuc #include <io.h>
6*433d6423SLionel Sambuc
7*433d6423SLionel Sambuc #include "kernel/kernel.h"
8*433d6423SLionel Sambuc #include "kernel/proc.h"
9*433d6423SLionel Sambuc #include "kernel/vm.h"
10*433d6423SLionel Sambuc #include "kernel/proto.h"
11*433d6423SLionel Sambuc #include "arch_proto.h"
12*433d6423SLionel Sambuc #include "hw_intr.h"
13*433d6423SLionel Sambuc
14*433d6423SLionel Sambuc #include "omap_intr_registers.h"
15*433d6423SLionel Sambuc static struct omap_intr
16*433d6423SLionel Sambuc {
17*433d6423SLionel Sambuc vir_bytes base;
18*433d6423SLionel Sambuc int size;
19*433d6423SLionel Sambuc } omap_intr;
20*433d6423SLionel Sambuc
21*433d6423SLionel Sambuc static kern_phys_map intr_phys_map;
22*433d6423SLionel Sambuc
23*433d6423SLionel Sambuc int
intr_init(const int auto_eoi)24*433d6423SLionel Sambuc intr_init(const int auto_eoi)
25*433d6423SLionel Sambuc {
26*433d6423SLionel Sambuc if (BOARD_IS_BBXM(machine.board_id)) {
27*433d6423SLionel Sambuc omap_intr.base = OMAP3_DM37XX_INTR_BASE;
28*433d6423SLionel Sambuc } else if (BOARD_IS_BB(machine.board_id)) {
29*433d6423SLionel Sambuc omap_intr.base = OMAP3_AM335X_INTR_BASE;
30*433d6423SLionel Sambuc } else {
31*433d6423SLionel Sambuc panic
32*433d6423SLionel Sambuc ("Can not do the interrupt setup. machine (0x%08x) is unknown\n",
33*433d6423SLionel Sambuc machine.board_id);
34*433d6423SLionel Sambuc };
35*433d6423SLionel Sambuc omap_intr.size = 0x1000; /* 4K */
36*433d6423SLionel Sambuc
37*433d6423SLionel Sambuc kern_phys_map_ptr(omap_intr.base, omap_intr.size,
38*433d6423SLionel Sambuc VMMF_UNCACHED | VMMF_WRITE,
39*433d6423SLionel Sambuc &intr_phys_map, (vir_bytes) & omap_intr.base);
40*433d6423SLionel Sambuc return 0;
41*433d6423SLionel Sambuc }
42*433d6423SLionel Sambuc
43*433d6423SLionel Sambuc void
bsp_irq_handle(void)44*433d6423SLionel Sambuc bsp_irq_handle(void)
45*433d6423SLionel Sambuc {
46*433d6423SLionel Sambuc /* Function called from assembly to handle interrupts */
47*433d6423SLionel Sambuc
48*433d6423SLionel Sambuc /* get irq */
49*433d6423SLionel Sambuc int irq =
50*433d6423SLionel Sambuc mmio_read(omap_intr.base +
51*433d6423SLionel Sambuc OMAP3_INTCPS_SIR_IRQ) & OMAP3_INTR_ACTIVEIRQ_MASK;
52*433d6423SLionel Sambuc /* handle irq */
53*433d6423SLionel Sambuc irq_handle(irq);
54*433d6423SLionel Sambuc /* re-enable. this should not trigger interrupts due to current cpsr
55*433d6423SLionel Sambuc * state */
56*433d6423SLionel Sambuc mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL,
57*433d6423SLionel Sambuc OMAP3_INTR_NEWIRQAGR);
58*433d6423SLionel Sambuc }
59*433d6423SLionel Sambuc
60*433d6423SLionel Sambuc void
bsp_irq_unmask(int irq)61*433d6423SLionel Sambuc bsp_irq_unmask(int irq)
62*433d6423SLionel Sambuc {
63*433d6423SLionel Sambuc mmio_write(OMAP3_INTR_MIR_CLEAR(omap_intr.base, irq >> 5),
64*433d6423SLionel Sambuc 1 << (irq & 0x1f));
65*433d6423SLionel Sambuc }
66*433d6423SLionel Sambuc
67*433d6423SLionel Sambuc void
bsp_irq_mask(const int irq)68*433d6423SLionel Sambuc bsp_irq_mask(const int irq)
69*433d6423SLionel Sambuc {
70*433d6423SLionel Sambuc mmio_write(OMAP3_INTR_MIR_SET(omap_intr.base, irq >> 5),
71*433d6423SLionel Sambuc 1 << (irq & 0x1f));
72*433d6423SLionel Sambuc }
73