1*433d6423SLionel Sambuc /* 2*433d6423SLionel Sambuc ** File: wd.h 3*433d6423SLionel Sambuc ** 4*433d6423SLionel Sambuc ** Created: before Dec 28, 1992 by Philip Homburg 5*433d6423SLionel Sambuc ** $PchId: wdeth.h,v 1.4 1995/12/22 08:36:57 philip Exp $ 6*433d6423SLionel Sambuc ** 7*433d6423SLionel Sambuc ** $Log$ 8*433d6423SLionel Sambuc ** Revision 1.2 2005/08/22 15:17:40 beng 9*433d6423SLionel Sambuc ** Remove double-blank lines (Al) 10*433d6423SLionel Sambuc ** 11*433d6423SLionel Sambuc ** Revision 1.1 2005/06/29 10:16:46 beng 12*433d6423SLionel Sambuc ** Import of dpeth 3c501/3c509b/.. ethernet driver by 13*433d6423SLionel Sambuc ** Giovanni Falzoni <fgalzoni@inwind.it>. 14*433d6423SLionel Sambuc ** 15*433d6423SLionel Sambuc ** Revision 2.0 2005/06/26 16:16:46 lsodgf0 16*433d6423SLionel Sambuc ** Initial revision for Minix 3.0.6 17*433d6423SLionel Sambuc */ 18*433d6423SLionel Sambuc 19*433d6423SLionel Sambuc #ifndef WDETH_H 20*433d6423SLionel Sambuc #define WDETH_H 21*433d6423SLionel Sambuc 22*433d6423SLionel Sambuc /* Western Digital Ethercard Plus, or WD8003E card. */ 23*433d6423SLionel Sambuc 24*433d6423SLionel Sambuc #define EPL_REG0 0x0 /* Control(write) and status(read) */ 25*433d6423SLionel Sambuc #define EPL_REG1 0x1 26*433d6423SLionel Sambuc #define EPL_REG2 0x2 27*433d6423SLionel Sambuc #define EPL_REG3 0x3 28*433d6423SLionel Sambuc #define EPL_REG4 0x4 29*433d6423SLionel Sambuc #define EPL_REG5 0x5 30*433d6423SLionel Sambuc #define EPL_REG6 0x6 31*433d6423SLionel Sambuc #define EPL_REG7 0x7 32*433d6423SLionel Sambuc #define EPL_EA0 0x8 /* Most significant eaddr byte */ 33*433d6423SLionel Sambuc #define EPL_EA1 0x9 34*433d6423SLionel Sambuc #define EPL_EA2 0xA 35*433d6423SLionel Sambuc #define EPL_EA3 0xB 36*433d6423SLionel Sambuc #define EPL_EA4 0xC 37*433d6423SLionel Sambuc #define EPL_EA5 0xD /* Least significant eaddr byte */ 38*433d6423SLionel Sambuc #define EPL_TLB 0xE 39*433d6423SLionel Sambuc #define EPL_CHKSUM 0xF /* sum from epl_ea0 upto here is 0xFF */ 40*433d6423SLionel Sambuc #define EPL_DP8390 0x10 /* NatSemi chip */ 41*433d6423SLionel Sambuc 42*433d6423SLionel Sambuc #define EPL_MSR EPL_REG0/* memory select register */ 43*433d6423SLionel Sambuc #define EPL_ICR EPL_REG1/* interface configuration register */ 44*433d6423SLionel Sambuc #define EPL_IRR EPL_REG4/* interrupt request register (IRR) */ 45*433d6423SLionel Sambuc #define EPL_790_HWR EPL_REG4/* '790 hardware support register */ 46*433d6423SLionel Sambuc #define EPL_LAAR EPL_REG5/* LA address register (write only) */ 47*433d6423SLionel Sambuc #define EPL_790_ICR EPL_REG6/* '790 interrupt control register */ 48*433d6423SLionel Sambuc #define EPL_GP2 EPL_REG7/* general purpose register 2 */ 49*433d6423SLionel Sambuc #define EPL_790_B EPL_EA3 /* '790 memory register */ 50*433d6423SLionel Sambuc #define EPL_790_GCR EPL_EA5 /* '790 General Control Register */ 51*433d6423SLionel Sambuc 52*433d6423SLionel Sambuc /* Bits in EPL_MSR */ 53*433d6423SLionel Sambuc #define E_MSR_MEMADDR 0x3F /* Bits SA18-SA13, SA19 implicit 1 */ 54*433d6423SLionel Sambuc #define E_MSR_MENABLE 0x40 /* Memory Enable */ 55*433d6423SLionel Sambuc #define E_MSR_RESET 0x80 /* Software Reset */ 56*433d6423SLionel Sambuc 57*433d6423SLionel Sambuc /* Bits in EPL_ICR */ 58*433d6423SLionel Sambuc #define E_ICR_16BIT 0x01 /* 16 bit bus */ 59*433d6423SLionel Sambuc #define E_ICR_IR2 0x04 /* bit 2 of encoded IRQ */ 60*433d6423SLionel Sambuc #define E_ICR_MEMBIT 0x08 /* 583 mem size mask */ 61*433d6423SLionel Sambuc 62*433d6423SLionel Sambuc /* Bits in EPL_IRR */ 63*433d6423SLionel Sambuc #define E_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 64*433d6423SLionel Sambuc #define E_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 65*433d6423SLionel Sambuc #define E_IRR_IEN 0x80 /* enable interrupts */ 66*433d6423SLionel Sambuc 67*433d6423SLionel Sambuc /* Bits in EPL_LAAR */ 68*433d6423SLionel Sambuc #define E_LAAR_A19 0x01 /* address lines for above 1M ram */ 69*433d6423SLionel Sambuc #define E_LAAR_A20 0x02 /* address lines for above 1M ram */ 70*433d6423SLionel Sambuc #define E_LAAR_A21 0x04 /* address lines for above 1M ram */ 71*433d6423SLionel Sambuc #define E_LAAR_A22 0x08 /* address lines for above 1M ram */ 72*433d6423SLionel Sambuc #define E_LAAR_A23 0x10 /* address lines for above 1M ram */ 73*433d6423SLionel Sambuc #define E_LAAR_SOFTINT 0x20 /* enable software interrupt */ 74*433d6423SLionel Sambuc #define E_LAAR_LAN16E 0x40 /* enables 16 bit RAM for LAN */ 75*433d6423SLionel Sambuc #define E_LAAR_MEM16E 0x80 /* enables 16 bit RAM for host */ 76*433d6423SLionel Sambuc 77*433d6423SLionel Sambuc /* Bits and values in EPL_TLB */ 78*433d6423SLionel Sambuc #define E_TLB_EB 0x05 /* WD8013EB */ 79*433d6423SLionel Sambuc #define E_TLB_E 0x27 /* WD8013 Elite */ 80*433d6423SLionel Sambuc #define E_TLB_SMCE 0x29 /* SMC Elite 16 */ 81*433d6423SLionel Sambuc #define E_TLB_SMC8216C 0x2B /* SMC 8216 C */ 82*433d6423SLionel Sambuc 83*433d6423SLionel Sambuc #define E_TLB_REV 0x1F /* revision mask */ 84*433d6423SLionel Sambuc #define E_TLB_SOFT 0x20 /* soft config */ 85*433d6423SLionel Sambuc #define E_TLB_RAM 0x40 /* extra ram bit */ 86*433d6423SLionel Sambuc 87*433d6423SLionel Sambuc /* Bits in EPL_790_HWR */ 88*433d6423SLionel Sambuc #define E_790_HWR_SWH 0x80 /* switch register set */ 89*433d6423SLionel Sambuc 90*433d6423SLionel Sambuc /* Bits in EPL_790_ICR */ 91*433d6423SLionel Sambuc #define E_790_ICR_EIL 0x01 /* enable interrupts */ 92*433d6423SLionel Sambuc 93*433d6423SLionel Sambuc /* Bits in EPL_790_GCR when E_790_HWR_SWH is set in EPL_790_HWR */ 94*433d6423SLionel Sambuc #define E_790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 95*433d6423SLionel Sambuc #define E_790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 96*433d6423SLionel Sambuc #define E_790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 97*433d6423SLionel Sambuc 98*433d6423SLionel Sambuc #define inb_we(dep, reg) (inb(dep->de_base_port+reg)) 99*433d6423SLionel Sambuc #define outb_we(dep, reg, data) (outb(dep->de_base_port+reg, data)) 100*433d6423SLionel Sambuc 101*433d6423SLionel Sambuc #endif /* WDETH_H */ 102*433d6423SLionel Sambuc 103*433d6423SLionel Sambuc /** wd.h **/ 104