1*433d6423SLionel Sambuc /* 2*433d6423SLionel Sambuc ** File: 3c503.h Dec. 20, 1996 3*433d6423SLionel Sambuc ** 4*433d6423SLionel Sambuc ** Author: Giovanni Falzoni <gfalzoni@inwind.it> 5*433d6423SLionel Sambuc ** 6*433d6423SLionel Sambuc ** Interface description for 3Com Etherlink II boards 7*433d6423SLionel Sambuc ** 8*433d6423SLionel Sambuc ** $Log$ 9*433d6423SLionel Sambuc ** Revision 1.1 2005/06/29 10:16:46 beng 10*433d6423SLionel Sambuc ** Import of dpeth 3c501/3c509b/.. ethernet driver by 11*433d6423SLionel Sambuc ** Giovanni Falzoni <fgalzoni@inwind.it>. 12*433d6423SLionel Sambuc ** 13*433d6423SLionel Sambuc ** Revision 2.0 2005/06/26 16:16:46 lsodgf0 14*433d6423SLionel Sambuc ** Initial revision for Minix 3.0.6 15*433d6423SLionel Sambuc */ 16*433d6423SLionel Sambuc 17*433d6423SLionel Sambuc #define EL2_MEMTEST 0 /* Set to 1 for on board memory test */ 18*433d6423SLionel Sambuc 19*433d6423SLionel Sambuc #define EL2_GA 0x0400 /* Offset of registers in Gate Array */ 20*433d6423SLionel Sambuc 21*433d6423SLionel Sambuc /* EtherLink II card */ 22*433d6423SLionel Sambuc 23*433d6423SLionel Sambuc #define EL2_STARTPG (EL2_GA+0x00) /* Start page matching DP_PSTARTPG */ 24*433d6423SLionel Sambuc #define EL2_STOPPG (EL2_GA+0x01) /* Stop page matching DP_PSTOPPG */ 25*433d6423SLionel Sambuc #define EL2_DRQCNT (EL2_GA+0x02) /* DMA burst count */ 26*433d6423SLionel Sambuc #define EL2_IOBASE (EL2_GA+0x03) /* I/O base jumpers (bit coded) */ 27*433d6423SLionel Sambuc #define EL2_MEMBASE (EL2_GA+0x04) /* Memory base jumpers (bit coded) */ 28*433d6423SLionel Sambuc #define EL2_CFGR (EL2_GA+0x05) /* Configuration Register for GA */ 29*433d6423SLionel Sambuc #define EL2_CNTR (EL2_GA+0x06) /* Control(write) and status(read) */ 30*433d6423SLionel Sambuc #define EL2_STATUS (EL2_GA+0x07) 31*433d6423SLionel Sambuc #define EL2_IDCFG (EL2_GA+0x08) /* Interrupt/DMA configuration reg */ 32*433d6423SLionel Sambuc #define EL2_DMAAH (EL2_GA+0x09) /* DMA address register (High byte) */ 33*433d6423SLionel Sambuc #define EL2_DMAAL (EL2_GA+0x0A) /* DMA address register (Low byte) */ 34*433d6423SLionel Sambuc #define EL2_VP2 (EL2_GA+0x0B) /* Vector pointer - set to */ 35*433d6423SLionel Sambuc #define EL2_VP1 (EL2_GA+0x0C) /* reset address (0xFFFF:0) */ 36*433d6423SLionel Sambuc #define EL2_VP0 (EL2_GA+0x0D) /* */ 37*433d6423SLionel Sambuc #define EL2_FIFOH (EL2_GA+0x0E) /* FIFO for progr. I/O (High byte) */ 38*433d6423SLionel Sambuc #define EL2_FIFOL (EL2_GA+0x0F) /* FIFO for progr. I/O (Low byte) */ 39*433d6423SLionel Sambuc 40*433d6423SLionel Sambuc #define EL2_EA0 0x00 /* Most significant byte of ethernet address */ 41*433d6423SLionel Sambuc #define EL2_EA1 0x01 42*433d6423SLionel Sambuc #define EL2_EA2 0x02 43*433d6423SLionel Sambuc #define EL2_EA3 0x03 44*433d6423SLionel Sambuc #define EL2_EA4 0x04 45*433d6423SLionel Sambuc #define EL2_EA5 0x05 /* Least significant byte of ethernet address */ 46*433d6423SLionel Sambuc 47*433d6423SLionel Sambuc /* Bits in EL2_CNTR register */ 48*433d6423SLionel Sambuc #define ECNTR_RESET 0x01 /* Software Reset */ 49*433d6423SLionel Sambuc #define ECNTR_THIN 0x02 /* Onboard transceiver enable */ 50*433d6423SLionel Sambuc #define ECNTR_AUI 0x00 /* Onboard transceiver disable */ 51*433d6423SLionel Sambuc #define ECNTR_SAPROM 0x04 /* Map the station address prom */ 52*433d6423SLionel Sambuc 53*433d6423SLionel Sambuc /* Bits in EL2_CFGR register */ 54*433d6423SLionel Sambuc #define ECFGR_NORM 0x49 /* Enable 8k shared memory, no DMA, TC int */ 55*433d6423SLionel Sambuc #define ECFGR_IRQOFF 0xC9 /* As above, disable 8390 IRQ */ 56*433d6423SLionel Sambuc 57*433d6423SLionel Sambuc /* Shared memory management parameters */ 58*433d6423SLionel Sambuc #define EL2_SM_START_PG 0x20 /* First page of TX buffer */ 59*433d6423SLionel Sambuc #define EL2_SM_STOP_PG 0x40 /* Last page +1 of RX ring */ 60*433d6423SLionel Sambuc 61*433d6423SLionel Sambuc /* Physical addresses where an Etherlink board can be configured */ 62*433d6423SLionel Sambuc #define EL2_BASE_0C8000 0x0C8000 63*433d6423SLionel Sambuc #define EL2_BASE_0CC000 0x0CC000 64*433d6423SLionel Sambuc #define EL2_BASE_0D8000 0x0D8000 65*433d6423SLionel Sambuc #define EL2_BASE_0DC000 0x0DC000 66*433d6423SLionel Sambuc 67*433d6423SLionel Sambuc #define inb_el2(dep,reg) (inb((dep)->de_base_port+(reg))) 68*433d6423SLionel Sambuc #define outb_el2(dep,reg,data) (outb((dep)->de_base_port+(reg),(data))) 69*433d6423SLionel Sambuc 70*433d6423SLionel Sambuc /** 3c503.h **/ 71