1 /* 2 pci.c 3 4 Configure devices on the PCI bus 5 6 Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl> 7 */ 8 #include <minix/acpi.h> 9 #include <minix/chardriver.h> 10 #include <minix/driver.h> 11 #include <minix/ds.h> 12 #include <minix/param.h> 13 #include <minix/rs.h> 14 15 #include <machine/pci.h> 16 #include <machine/pci_amd.h> 17 #include <machine/pci_intel.h> 18 #include <machine/pci_sis.h> 19 #include <machine/pci_via.h> 20 #include <machine/vmparam.h> 21 22 #include <pci.h> 23 #include <stdlib.h> 24 #include <stdio.h> 25 26 #include "pci.h" 27 28 #define irq_mode_pci(irq) ((void)0) 29 30 #define PBT_INTEL_HOST 1 31 #define PBT_PCIBRIDGE 2 32 #define PBT_CARDBUS 3 33 34 #define BAM_NR 6 /* Number of base-address registers */ 35 36 struct pci_acl pci_acl[NR_DRIVERS]; 37 38 static struct pcibus 39 { 40 int pb_type; 41 int pb_needinit; 42 int pb_isabridge_dev; 43 int pb_isabridge_type; 44 45 int pb_devind; 46 int pb_busnr; 47 u8_t (*pb_rreg8)(int busind, int devind, int port); 48 u16_t (*pb_rreg16)(int busind, int devind, int port); 49 u32_t (*pb_rreg32)(int busind, int devind, int port); 50 void (*pb_wreg8)(int busind, int devind, int port, u8_t value); 51 void (*pb_wreg16)(int busind, int devind, int port, u16_t value); 52 void (*pb_wreg32)(int busind, int devind, int port, u32_t value); 53 u16_t (*pb_rsts)(int busind); 54 void (*pb_wsts)(int busind, u16_t value); 55 } pcibus[NR_PCIBUS]; 56 static int nr_pcibus= 0; 57 58 static struct pcidev 59 { 60 u8_t pd_busnr; 61 u8_t pd_dev; 62 u8_t pd_func; 63 u8_t pd_baseclass; 64 u8_t pd_subclass; 65 u8_t pd_infclass; 66 u16_t pd_vid; 67 u16_t pd_did; 68 u16_t pd_sub_vid; 69 u16_t pd_sub_did; 70 u8_t pd_ilr; 71 72 u8_t pd_inuse; 73 endpoint_t pd_proc; 74 75 struct bar 76 { 77 int pb_flags; 78 int pb_nr; 79 u32_t pb_base; 80 u32_t pb_size; 81 } pd_bar[BAM_NR]; 82 int pd_bar_nr; 83 } pcidev[NR_PCIDEV]; 84 85 /* pb_flags */ 86 #define PBF_IO 1 /* I/O else memory */ 87 #define PBF_INCOMPLETE 2 /* not allocated */ 88 89 static int nr_pcidev= 0; 90 91 static struct machine machine; 92 static endpoint_t acpi_ep; 93 94 /*===========================================================================* 95 * helper functions for I/O * 96 *===========================================================================*/ 97 static unsigned 98 pci_inb(u16_t port) { 99 u32_t value; 100 int s; 101 if ((s=sys_inb(port, &value)) !=OK) 102 printf("PCI: warning, sys_inb failed: %d\n", s); 103 return value; 104 } 105 106 static unsigned 107 pci_inw(u16_t port) { 108 u32_t value; 109 int s; 110 if ((s=sys_inw(port, &value)) !=OK) 111 printf("PCI: warning, sys_inw failed: %d\n", s); 112 return value; 113 } 114 115 static unsigned 116 pci_inl(u16_t port) { 117 u32_t value; 118 int s; 119 if ((s=sys_inl(port, &value)) !=OK) 120 printf("PCI: warning, sys_inl failed: %d\n", s); 121 return value; 122 } 123 124 static void 125 pci_outb(u16_t port, u8_t value) { 126 int s; 127 if ((s=sys_outb(port, value)) !=OK) 128 printf("PCI: warning, sys_outb failed: %d\n", s); 129 } 130 131 static void 132 pci_outw(u16_t port, u16_t value) { 133 int s; 134 if ((s=sys_outw(port, value)) !=OK) 135 printf("PCI: warning, sys_outw failed: %d\n", s); 136 } 137 138 static void 139 pci_outl(u16_t port, u32_t value) { 140 int s; 141 if ((s=sys_outl(port, value)) !=OK) 142 printf("PCI: warning, sys_outl failed: %d\n", s); 143 } 144 145 static u8_t 146 pcii_rreg8(int busind, int devind, int port) 147 { 148 u8_t v; 149 int s; 150 151 v= PCII_RREG8_(pcibus[busind].pb_busnr, 152 pcidev[devind].pd_dev, pcidev[devind].pd_func, 153 port); 154 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 155 printf("PCI: warning, sys_outl failed: %d\n", s); 156 #if 0 157 printf("pcii_rreg8(%d, %d, 0x%X): %d.%d.%d= 0x%X\n", 158 busind, devind, port, 159 pcibus[busind].pb_bus, pcidev[devind].pd_dev, 160 pcidev[devind].pd_func, v); 161 #endif 162 return v; 163 } 164 165 static u16_t 166 pcii_rreg16(int busind, int devind, int port) 167 { 168 u16_t v; 169 int s; 170 171 v= PCII_RREG16_(pcibus[busind].pb_busnr, 172 pcidev[devind].pd_dev, pcidev[devind].pd_func, 173 port); 174 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 175 printf("PCI: warning, sys_outl failed: %d\n", s); 176 #if 0 177 printf("pcii_rreg16(%d, %d, 0x%X): %d.%d.%d= 0x%X\n", 178 busind, devind, port, 179 pcibus[busind].pb_bus, pcidev[devind].pd_dev, 180 pcidev[devind].pd_func, v); 181 #endif 182 return v; 183 } 184 185 static u32_t 186 pcii_rreg32(int busind, int devind, int port) 187 { 188 u32_t v; 189 int s; 190 191 v= PCII_RREG32_(pcibus[busind].pb_busnr, 192 pcidev[devind].pd_dev, pcidev[devind].pd_func, 193 port); 194 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 195 printf("PCI: warning, sys_outl failed: %d\n", s); 196 #if 0 197 printf("pcii_rreg32(%d, %d, 0x%X): %d.%d.%d= 0x%X\n", 198 busind, devind, port, 199 pcibus[busind].pb_bus, pcidev[devind].pd_dev, 200 pcidev[devind].pd_func, v); 201 #endif 202 return v; 203 } 204 205 static void 206 pcii_wreg8(int busind, int devind, int port, u8_t value) 207 { 208 int s; 209 #if 0 210 printf("pcii_wreg8(%d, %d, 0x%X, 0x%X): %d.%d.%d\n", 211 busind, devind, port, value, 212 pcibus[busind].pb_bus, pcidev[devind].pd_dev, 213 pcidev[devind].pd_func); 214 #endif 215 PCII_WREG8_(pcibus[busind].pb_busnr, 216 pcidev[devind].pd_dev, pcidev[devind].pd_func, 217 port, value); 218 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 219 printf("PCI: warning, sys_outl failed: %d\n", s); 220 } 221 222 static void 223 pcii_wreg16(int busind, int devind, int port, u16_t value) 224 { 225 int s; 226 #if 0 227 printf("pcii_wreg16(%d, %d, 0x%X, 0x%X): %d.%d.%d\n", 228 busind, devind, port, value, 229 pcibus[busind].pb_bus, pcidev[devind].pd_dev, 230 pcidev[devind].pd_func); 231 #endif 232 PCII_WREG16_(pcibus[busind].pb_busnr, 233 pcidev[devind].pd_dev, pcidev[devind].pd_func, 234 port, value); 235 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 236 printf("PCI: warning, sys_outl failed: %d\n", s); 237 } 238 239 static void 240 pcii_wreg32(int busind, int devind, int port, u32_t value) 241 { 242 int s; 243 #if 0 244 printf("pcii_wreg32(%d, %d, 0x%X, 0x%X): %d.%d.%d\n", 245 busind, devind, port, value, 246 pcibus[busind].pb_busnr, pcidev[devind].pd_dev, 247 pcidev[devind].pd_func); 248 #endif 249 PCII_WREG32_(pcibus[busind].pb_busnr, 250 pcidev[devind].pd_dev, pcidev[devind].pd_func, 251 port, value); 252 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 253 printf("PCI: warning, sys_outl failed: %d\n",s); 254 } 255 256 /*===========================================================================* 257 * ntostr * 258 *===========================================================================*/ 259 static void 260 ntostr(unsigned int n, char **str, const char *end) 261 { 262 char tmpstr[20]; 263 int i; 264 265 if (n == 0) 266 { 267 tmpstr[0]= '0'; 268 i= 1; 269 } 270 else 271 { 272 for (i= 0; n; i++) 273 { 274 tmpstr[i]= '0' + (n%10); 275 n /= 10; 276 } 277 } 278 for (; i>0; i--) 279 { 280 if (*str == end) 281 { 282 break; 283 } 284 **str= tmpstr[i-1]; 285 (*str)++; 286 } 287 if (*str == end) 288 (*str)[-1]= '\0'; 289 else 290 **str= '\0'; 291 } 292 293 /*===========================================================================* 294 * get_busind * 295 *===========================================================================*/ 296 static int 297 get_busind(int busnr) 298 { 299 int i; 300 301 for (i= 0; i<nr_pcibus; i++) 302 { 303 if (pcibus[i].pb_busnr == busnr) 304 return i; 305 } 306 panic("get_busind: can't find bus: %d", busnr); 307 } 308 309 /*===========================================================================* 310 * Unprotected helper functions * 311 *===========================================================================*/ 312 static u8_t 313 __pci_attr_r8(int devind, int port) 314 { 315 int busnr, busind; 316 317 busnr= pcidev[devind].pd_busnr; 318 busind= get_busind(busnr); 319 return pcibus[busind].pb_rreg8(busind, devind, port); 320 } 321 322 static u16_t 323 __pci_attr_r16(int devind, int port) 324 { 325 int busnr, busind; 326 327 busnr= pcidev[devind].pd_busnr; 328 busind= get_busind(busnr); 329 return pcibus[busind].pb_rreg16(busind, devind, port); 330 } 331 332 static u32_t 333 __pci_attr_r32(int devind, int port) 334 { 335 int busnr, busind; 336 337 busnr= pcidev[devind].pd_busnr; 338 busind= get_busind(busnr); 339 return pcibus[busind].pb_rreg32(busind, devind, port); 340 } 341 342 static void 343 __pci_attr_w8(int devind, int port, u8_t value) 344 { 345 int busnr, busind; 346 347 busnr= pcidev[devind].pd_busnr; 348 busind= get_busind(busnr); 349 pcibus[busind].pb_wreg8(busind, devind, port, value); 350 } 351 352 static void 353 __pci_attr_w16(int devind, int port, u16_t value) 354 { 355 int busnr, busind; 356 357 busnr= pcidev[devind].pd_busnr; 358 busind= get_busind(busnr); 359 pcibus[busind].pb_wreg16(busind, devind, port, value); 360 } 361 362 static void 363 __pci_attr_w32(int devind, int port, u32_t value) 364 { 365 int busnr, busind; 366 367 busnr= pcidev[devind].pd_busnr; 368 busind= get_busind(busnr); 369 pcibus[busind].pb_wreg32(busind, devind, port, value); 370 } 371 372 /*===========================================================================* 373 * helpers * 374 *===========================================================================*/ 375 static u16_t 376 pci_attr_rsts(int devind) 377 { 378 int busnr, busind; 379 380 busnr= pcidev[devind].pd_busnr; 381 busind= get_busind(busnr); 382 return pcibus[busind].pb_rsts(busind); 383 } 384 385 static void 386 pci_attr_wsts(int devind, u16_t value) 387 { 388 int busnr, busind; 389 390 busnr= pcidev[devind].pd_busnr; 391 busind= get_busind(busnr); 392 pcibus[busind].pb_wsts(busind, value); 393 } 394 395 static u16_t 396 pcii_rsts(int busind) 397 { 398 u16_t v; 399 int s; 400 401 v= PCII_RREG16_(pcibus[busind].pb_busnr, 0, 0, PCI_SR); 402 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 403 printf("PCI: warning, sys_outl failed: %d\n", s); 404 return v; 405 } 406 407 static void 408 pcii_wsts(int busind, u16_t value) 409 { 410 int s; 411 PCII_WREG16_(pcibus[busind].pb_busnr, 0, 0, PCI_SR, value); 412 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 413 printf("PCI: warning, sys_outl failed: %d\n", s); 414 } 415 416 static int 417 is_duplicate(u8_t busnr, u8_t dev, u8_t func) 418 { 419 int i; 420 421 for (i= 0; i<nr_pcidev; i++) 422 { 423 if (pcidev[i].pd_busnr == busnr && 424 pcidev[i].pd_dev == dev && 425 pcidev[i].pd_func == func) 426 { 427 return 1; 428 } 429 } 430 return 0; 431 } 432 433 static int 434 get_freebus(void) 435 { 436 int i, freebus; 437 438 freebus= 1; 439 for (i= 0; i<nr_pcibus; i++) 440 { 441 if (pcibus[i].pb_needinit) 442 continue; 443 if (pcibus[i].pb_type == PBT_INTEL_HOST) 444 continue; 445 if (pcibus[i].pb_busnr <= freebus) 446 freebus= pcibus[i].pb_busnr+1; 447 printf("get_freebus: should check suboridinate bus number\n"); 448 } 449 return freebus; 450 } 451 452 static const char * 453 pci_vid_name(u16_t vid) 454 { 455 const char *name = pci_findvendor_real(vid); 456 if (NULL == name) 457 return "unknown"; 458 else 459 return name; 460 } 461 462 463 static void 464 print_hyper_cap(int devind, u8_t capptr) 465 { 466 u32_t v; 467 u16_t cmd; 468 int type0, type1; 469 470 printf("\n"); 471 v= __pci_attr_r32(devind, capptr); 472 printf("print_hyper_cap: @0x%x, off 0 (cap):", capptr); 473 cmd= (v >> 16) & 0xffff; 474 #if 0 475 if (v & 0x10000) 476 { 477 printf(" WarmReset"); 478 v &= ~0x10000; 479 } 480 if (v & 0x20000) 481 { 482 printf(" DblEnded"); 483 v &= ~0x20000; 484 } 485 printf(" DevNum %d", (v & 0x7C0000) >> 18); 486 v &= ~0x7C0000; 487 #endif 488 type0= (cmd & 0xE000) >> 13; 489 type1= (cmd & 0xF800) >> 11; 490 if (type0 == 0 || type0 == 1) 491 { 492 printf("Capability Type: %s\n", 493 type0 == 0 ? "Slave or Primary Interface" : 494 "Host or Secondary Interface"); 495 cmd &= ~0xE000; 496 } 497 else 498 { 499 printf(" Capability Type 0x%x", type1); 500 cmd &= ~0xF800; 501 } 502 if (cmd) 503 printf(" undecoded 0x%x\n", cmd); 504 505 #if 0 506 printf("print_hyper_cap: off 4 (ctl): 0x%x\n", 507 __pci_attr_r32(devind, capptr+4)); 508 printf("print_hyper_cap: off 8 (freq/rev): 0x%x\n", 509 __pci_attr_r32(devind, capptr+8)); 510 printf("print_hyper_cap: off 12 (cap): 0x%x\n", 511 __pci_attr_r32(devind, capptr+12)); 512 printf("print_hyper_cap: off 16 (buf count): 0x%x\n", 513 __pci_attr_r32(devind, capptr+16)); 514 v= __pci_attr_r32(devind, capptr+20); 515 printf("print_hyper_cap: @0x%x, off 20 (bus nr): ", 516 capptr+20); 517 printf("prim %d", v & 0xff); 518 printf(", sec %d", (v >> 8) & 0xff); 519 printf(", sub %d", (v >> 16) & 0xff); 520 if (v >> 24) 521 printf(", reserved %d", (v >> 24) & 0xff); 522 printf("\n"); 523 printf("print_hyper_cap: off 24 (type): 0x%x\n", 524 __pci_attr_r32(devind, capptr+24)); 525 #endif 526 } 527 528 static void 529 print_capabilities(int devind) 530 { 531 u8_t status, capptr, type, next, subtype; 532 const char *str; 533 534 /* Check capabilities bit in the device status register */ 535 status= __pci_attr_r16(devind, PCI_SR); 536 if (!(status & PSR_CAPPTR)) 537 return; 538 539 capptr= (__pci_attr_r8(devind, PCI_CAPPTR) & PCI_CP_MASK); 540 while (capptr != 0) 541 { 542 type = __pci_attr_r8(devind, capptr+CAP_TYPE); 543 next= (__pci_attr_r8(devind, capptr+CAP_NEXT) & PCI_CP_MASK); 544 switch(type) 545 { 546 case 1: str= "PCI Power Management"; break; 547 case 2: str= "AGP"; break; 548 case 3: str= "Vital Product Data"; break; 549 case 4: str= "Slot Identification"; break; 550 case 5: str= "Message Signaled Interrupts"; break; 551 case 6: str= "CompactPCI Hot Swap"; break; 552 case 8: str= "AMD HyperTransport"; break; 553 case 0xf: str= "Secure Device"; break; 554 default: str= "(unknown type)"; break; 555 } 556 557 printf(" @0x%x (0x%08x): capability type 0x%x: %s", 558 capptr, __pci_attr_r32(devind, capptr), type, str); 559 if (type == 0x08) 560 print_hyper_cap(devind, capptr); 561 else if (type == 0x0f) 562 { 563 subtype= (__pci_attr_r8(devind, capptr+2) & 0x07); 564 switch(subtype) 565 { 566 case 0: str= "Device Exclusion Vector"; break; 567 case 3: str= "IOMMU"; break; 568 default: str= "(unknown type)"; break; 569 } 570 printf(", sub type 0%o: %s", subtype, str); 571 } 572 printf("\n"); 573 capptr= next; 574 } 575 } 576 577 /*===========================================================================* 578 * ISA Bridge Helpers * 579 *===========================================================================*/ 580 static void 581 update_bridge4dev_io(int devind, u32_t io_base, u32_t io_size) 582 { 583 int busnr, busind, type, br_devind; 584 u16_t v16; 585 586 busnr= pcidev[devind].pd_busnr; 587 busind= get_busind(busnr); 588 type= pcibus[busind].pb_type; 589 if (type == PBT_INTEL_HOST) 590 return; /* Nothing to do for host controller */ 591 if (type == PBT_PCIBRIDGE) 592 { 593 printf( 594 "update_bridge4dev_io: not implemented for PCI bridges\n"); 595 return; 596 } 597 if (type != PBT_CARDBUS) 598 panic("update_bridge4dev_io: strange bus type: %d", type); 599 600 if (debug) 601 { 602 printf("update_bridge4dev_io: adding 0x%x at 0x%x\n", 603 io_size, io_base); 604 } 605 br_devind= pcibus[busind].pb_devind; 606 __pci_attr_w32(br_devind, CBB_IOLIMIT_0, io_base+io_size-1); 607 __pci_attr_w32(br_devind, CBB_IOBASE_0, io_base); 608 609 /* Enable I/O access. Enable busmaster access as well. */ 610 v16= __pci_attr_r16(devind, PCI_CR); 611 __pci_attr_w16(devind, PCI_CR, v16 | PCI_CR_IO_EN | PCI_CR_MAST_EN); 612 } 613 614 static int 615 do_piix(int devind) 616 { 617 int i, s, irqrc, irq; 618 u32_t elcr1, elcr2, elcr; 619 620 #if DEBUG 621 printf("in piix\n"); 622 #endif 623 if (OK != (s=sys_inb(PIIX_ELCR1, &elcr1))) 624 printf("Warning, sys_inb failed: %d\n", s); 625 if (OK != (s=sys_inb(PIIX_ELCR2, &elcr2))) 626 printf("Warning, sys_inb failed: %d\n", s); 627 elcr= elcr1 | (elcr2 << 8); 628 for (i= 0; i<4; i++) 629 { 630 irqrc= __pci_attr_r8(devind, PIIX_PIRQRCA+i); 631 if (irqrc & PIIX_IRQ_DI) 632 { 633 if (debug) 634 printf("INT%c: disabled\n", 'A'+i); 635 } 636 else 637 { 638 irq= irqrc & PIIX_IRQ_MASK; 639 if (debug) 640 printf("INT%c: %d\n", 'A'+i, irq); 641 if (!(elcr & (1 << irq))) 642 { 643 if (debug) 644 { 645 printf( 646 "(warning) IRQ %d is not level triggered\n", 647 irq); 648 } 649 } 650 irq_mode_pci(irq); 651 } 652 } 653 return 0; 654 } 655 656 static int 657 do_amd_isabr(int devind) 658 { 659 int i, busnr, dev, func, xdevind, irq, edge; 660 u8_t levmask; 661 u16_t pciirq; 662 663 /* Find required function */ 664 func= AMD_ISABR_FUNC; 665 busnr= pcidev[devind].pd_busnr; 666 dev= pcidev[devind].pd_dev; 667 668 /* Fake a device with the required function */ 669 if (nr_pcidev >= NR_PCIDEV) 670 panic("too many PCI devices: %d", nr_pcidev); 671 xdevind= nr_pcidev; 672 pcidev[xdevind].pd_busnr= busnr; 673 pcidev[xdevind].pd_dev= dev; 674 pcidev[xdevind].pd_func= func; 675 pcidev[xdevind].pd_inuse= 1; 676 nr_pcidev++; 677 678 levmask= __pci_attr_r8(xdevind, AMD_ISABR_PCIIRQ_LEV); 679 pciirq= __pci_attr_r16(xdevind, AMD_ISABR_PCIIRQ_ROUTE); 680 for (i= 0; i<4; i++) 681 { 682 edge= (levmask >> i) & 1; 683 irq= (pciirq >> (4*i)) & 0xf; 684 if (!irq) 685 { 686 if (debug) 687 printf("INT%c: disabled\n", 'A'+i); 688 } 689 else 690 { 691 if (debug) 692 printf("INT%c: %d\n", 'A'+i, irq); 693 if (edge && debug) 694 { 695 printf( 696 "(warning) IRQ %d is not level triggered\n", 697 irq); 698 } 699 irq_mode_pci(irq); 700 } 701 } 702 nr_pcidev--; 703 return 0; 704 } 705 706 static int 707 do_sis_isabr(int devind) 708 { 709 int i, irq; 710 711 irq= 0; /* lint */ 712 for (i= 0; i<4; i++) 713 { 714 irq= __pci_attr_r8(devind, SIS_ISABR_IRQ_A+i); 715 if (irq & SIS_IRQ_DISABLED) 716 { 717 if (debug) 718 printf("INT%c: disabled\n", 'A'+i); 719 } 720 else 721 { 722 irq &= SIS_IRQ_MASK; 723 if (debug) 724 printf("INT%c: %d\n", 'A'+i, irq); 725 irq_mode_pci(irq); 726 } 727 } 728 return 0; 729 } 730 731 static int 732 do_via_isabr(int devind) 733 { 734 int i, irq, edge; 735 u8_t levmask; 736 737 levmask= __pci_attr_r8(devind, VIA_ISABR_EL); 738 irq= 0; /* lint */ 739 edge= 0; /* lint */ 740 for (i= 0; i<4; i++) 741 { 742 switch(i) 743 { 744 case 0: 745 edge= (levmask & VIA_ISABR_EL_INTA); 746 irq= __pci_attr_r8(devind, VIA_ISABR_IRQ_R2) >> 4; 747 break; 748 case 1: 749 edge= (levmask & VIA_ISABR_EL_INTB); 750 irq= __pci_attr_r8(devind, VIA_ISABR_IRQ_R2); 751 break; 752 case 2: 753 edge= (levmask & VIA_ISABR_EL_INTC); 754 irq= __pci_attr_r8(devind, VIA_ISABR_IRQ_R3) >> 4; 755 break; 756 case 3: 757 edge= (levmask & VIA_ISABR_EL_INTD); 758 irq= __pci_attr_r8(devind, VIA_ISABR_IRQ_R1) >> 4; 759 break; 760 default: 761 panic("PCI: VIA ISA Bridge IRQ Detection Failed"); 762 } 763 irq &= 0xf; 764 if (!irq) 765 { 766 if (debug) 767 printf("INT%c: disabled\n", 'A'+i); 768 } 769 else 770 { 771 if (debug) 772 printf("INT%c: %d\n", 'A'+i, irq); 773 if (edge && debug) 774 { 775 printf( 776 "(warning) IRQ %d is not level triggered\n", 777 irq); 778 } 779 irq_mode_pci(irq); 780 } 781 } 782 return 0; 783 } 784 785 static int 786 do_isabridge(int busind) 787 { 788 int i, j, r, type, busnr, unknown_bridge, bridge_dev; 789 u16_t vid, did; 790 u32_t t3; 791 const char *dstr; 792 793 unknown_bridge= -1; 794 bridge_dev= -1; 795 j= 0; /* lint */ 796 vid= did= 0; /* lint */ 797 busnr= pcibus[busind].pb_busnr; 798 for (i= 0; i< nr_pcidev; i++) 799 { 800 if (pcidev[i].pd_busnr != busnr) 801 continue; 802 t3= ((pcidev[i].pd_baseclass << 16) | 803 (pcidev[i].pd_subclass << 8) | pcidev[i].pd_infclass); 804 if (t3 == PCI_T3_ISA) 805 { 806 /* ISA bridge. Report if no supported bridge is 807 * found. 808 */ 809 unknown_bridge= i; 810 } 811 812 vid= pcidev[i].pd_vid; 813 did= pcidev[i].pd_did; 814 for (j= 0; pci_isabridge[j].vid != 0; j++) 815 { 816 if (pci_isabridge[j].vid != vid) 817 continue; 818 if (pci_isabridge[j].did != did) 819 continue; 820 if (pci_isabridge[j].checkclass && 821 unknown_bridge != i) 822 { 823 /* This part of multifunction device is 824 * not the bridge. 825 */ 826 continue; 827 } 828 break; 829 } 830 if (pci_isabridge[j].vid) 831 { 832 bridge_dev= i; 833 break; 834 } 835 } 836 837 if (bridge_dev != -1) 838 { 839 dstr= _pci_dev_name(vid, did); 840 if (!dstr) 841 dstr= "unknown device"; 842 if (debug) 843 { 844 printf("found ISA bridge (%04X:%04X) %s\n", 845 vid, did, dstr); 846 } 847 pcibus[busind].pb_isabridge_dev= bridge_dev; 848 type= pci_isabridge[j].type; 849 pcibus[busind].pb_isabridge_type= type; 850 switch(type) 851 { 852 case PCI_IB_PIIX: 853 r= do_piix(bridge_dev); 854 break; 855 case PCI_IB_VIA: 856 r= do_via_isabr(bridge_dev); 857 break; 858 case PCI_IB_AMD: 859 r= do_amd_isabr(bridge_dev); 860 break; 861 case PCI_IB_SIS: 862 r= do_sis_isabr(bridge_dev); 863 break; 864 default: 865 panic("unknown ISA bridge type: %d", type); 866 } 867 return r; 868 } 869 870 if (unknown_bridge == -1) 871 { 872 if (debug) 873 { 874 printf("(warning) no ISA bridge found on bus %d\n", 875 busind); 876 } 877 return 0; 878 } 879 if (debug) 880 { 881 printf( 882 "(warning) unsupported ISA bridge %04X:%04X for bus %d\n", 883 pcidev[unknown_bridge].pd_vid, 884 pcidev[unknown_bridge].pd_did, busind); 885 } 886 return 0; 887 } 888 889 /*===========================================================================* 890 * IRQ handling * 891 *===========================================================================*/ 892 static int 893 acpi_get_irq(unsigned bus, unsigned dev, unsigned pin) 894 { 895 int err; 896 message m; 897 898 ((struct acpi_get_irq_req *)&m)->hdr.request = ACPI_REQ_GET_IRQ; 899 ((struct acpi_get_irq_req *)&m)->bus = bus; 900 ((struct acpi_get_irq_req *)&m)->dev = dev; 901 ((struct acpi_get_irq_req *)&m)->pin = pin; 902 903 if ((err = ipc_sendrec(acpi_ep, &m)) != OK) 904 panic("PCI: error %d while receiveing from ACPI\n", err); 905 906 return ((struct acpi_get_irq_resp *)&m)->irq; 907 } 908 909 static int 910 derive_irq(struct pcidev * dev, int pin) 911 { 912 struct pcidev * parent_bridge; 913 int slot; 914 915 parent_bridge = &pcidev[pcibus[get_busind(dev->pd_busnr)].pb_devind]; 916 917 /* 918 * We don't support PCI-Express, no ARI, decode the slot of the device 919 * and mangle the pin as the device is behind a bridge 920 */ 921 slot = ((dev->pd_func) >> 3) & 0x1f; 922 923 return acpi_get_irq(parent_bridge->pd_busnr, 924 parent_bridge->pd_dev, (pin + slot) % 4); 925 } 926 927 static void 928 record_irq(int devind) 929 { 930 int ilr, ipr, busnr, busind, cb_devind; 931 932 ilr= __pci_attr_r8(devind, PCI_ILR); 933 ipr= __pci_attr_r8(devind, PCI_IPR); 934 935 if (ipr && machine.apic_enabled) { 936 int irq; 937 938 irq = acpi_get_irq(pcidev[devind].pd_busnr, 939 pcidev[devind].pd_dev, ipr - 1); 940 941 if (irq < 0) 942 irq = derive_irq(&pcidev[devind], ipr - 1); 943 944 if (irq >= 0) { 945 ilr = irq; 946 __pci_attr_w8(devind, PCI_ILR, ilr); 947 if (debug) 948 printf("PCI: ACPI IRQ %d for " 949 "device %d.%d.%d INT%c\n", 950 irq, 951 pcidev[devind].pd_busnr, 952 pcidev[devind].pd_dev, 953 pcidev[devind].pd_func, 954 'A' + ipr-1); 955 } 956 else if (debug) { 957 printf("PCI: no ACPI IRQ routing for " 958 "device %d.%d.%d INT%c\n", 959 pcidev[devind].pd_busnr, 960 pcidev[devind].pd_dev, 961 pcidev[devind].pd_func, 962 'A' + ipr-1); 963 } 964 } 965 966 if (ilr == 0) 967 { 968 static int first= 1; 969 if (ipr && first && debug) 970 { 971 first= 0; 972 printf("PCI: strange, BIOS assigned IRQ0\n"); 973 } 974 ilr= PCI_ILR_UNKNOWN; 975 } 976 pcidev[devind].pd_ilr= ilr; 977 if (ilr == PCI_ILR_UNKNOWN && !ipr) 978 { 979 } 980 else if (ilr != PCI_ILR_UNKNOWN && ipr) 981 { 982 if (debug) 983 printf("\tIRQ %d for INT%c\n", ilr, 'A' + ipr-1); 984 } 985 else if (ilr != PCI_ILR_UNKNOWN) 986 { 987 printf( 988 "PCI: IRQ %d is assigned, but device %d.%d.%d does not need it\n", 989 ilr, pcidev[devind].pd_busnr, pcidev[devind].pd_dev, 990 pcidev[devind].pd_func); 991 } 992 else 993 { 994 /* Check for cardbus devices */ 995 busnr= pcidev[devind].pd_busnr; 996 busind= get_busind(busnr); 997 if (pcibus[busind].pb_type == PBT_CARDBUS) 998 { 999 cb_devind= pcibus[busind].pb_devind; 1000 ilr= pcidev[cb_devind].pd_ilr; 1001 if (ilr != PCI_ILR_UNKNOWN) 1002 { 1003 if (debug) 1004 { 1005 printf( 1006 "assigning IRQ %d to Cardbus device\n", 1007 ilr); 1008 } 1009 __pci_attr_w8(devind, PCI_ILR, ilr); 1010 pcidev[devind].pd_ilr= ilr; 1011 return; 1012 } 1013 } 1014 if(debug) { 1015 printf( 1016 "PCI: device %d.%d.%d uses INT%c but is not assigned any IRQ\n", 1017 pcidev[devind].pd_busnr, pcidev[devind].pd_dev, 1018 pcidev[devind].pd_func, 'A' + ipr-1); 1019 } 1020 } 1021 } 1022 1023 /*===========================================================================* 1024 * BAR helpers * 1025 *===========================================================================*/ 1026 static int 1027 record_bar(int devind, int bar_nr, int last) 1028 { 1029 int reg, prefetch, type, dev_bar_nr, width; 1030 u32_t bar, bar2; 1031 u16_t cmd; 1032 1033 /* Start by assuming that this is a 32-bit bar, taking up one DWORD. */ 1034 width = 1; 1035 1036 reg= PCI_BAR+4*bar_nr; 1037 1038 bar= __pci_attr_r32(devind, reg); 1039 if (bar & PCI_BAR_IO) 1040 { 1041 /* Disable I/O access before probing for BAR's size */ 1042 cmd = __pci_attr_r16(devind, PCI_CR); 1043 __pci_attr_w16(devind, PCI_CR, cmd & ~PCI_CR_IO_EN); 1044 1045 /* Probe BAR's size */ 1046 __pci_attr_w32(devind, reg, 0xffffffff); 1047 bar2= __pci_attr_r32(devind, reg); 1048 1049 /* Restore original state */ 1050 __pci_attr_w32(devind, reg, bar); 1051 __pci_attr_w16(devind, PCI_CR, cmd); 1052 1053 bar &= PCI_BAR_IO_MASK; /* Clear non-address bits */ 1054 bar2 &= PCI_BAR_IO_MASK; 1055 bar2= (~bar2 & 0xffff)+1; 1056 if (debug) 1057 { 1058 printf("\tbar_%d: %d bytes at 0x%x I/O\n", 1059 bar_nr, bar2, bar); 1060 } 1061 1062 dev_bar_nr= pcidev[devind].pd_bar_nr++; 1063 pcidev[devind].pd_bar[dev_bar_nr].pb_flags= PBF_IO; 1064 pcidev[devind].pd_bar[dev_bar_nr].pb_base= bar; 1065 pcidev[devind].pd_bar[dev_bar_nr].pb_size= bar2; 1066 pcidev[devind].pd_bar[dev_bar_nr].pb_nr= bar_nr; 1067 if (bar == 0) 1068 { 1069 pcidev[devind].pd_bar[dev_bar_nr].pb_flags |= 1070 PBF_INCOMPLETE; 1071 } 1072 } 1073 else 1074 { 1075 type= (bar & PCI_BAR_TYPE); 1076 1077 switch(type) { 1078 case PCI_TYPE_32: 1079 case PCI_TYPE_32_1M: 1080 break; 1081 1082 case PCI_TYPE_64: 1083 /* A 64-bit BAR takes up two consecutive DWORDs. */ 1084 if (last) 1085 { 1086 printf("PCI: device %d.%d.%d BAR %d extends" 1087 " beyond designated area\n", 1088 pcidev[devind].pd_busnr, 1089 pcidev[devind].pd_dev, 1090 pcidev[devind].pd_func, bar_nr); 1091 1092 return width; 1093 } 1094 width++; 1095 1096 bar2= __pci_attr_r32(devind, reg+4); 1097 1098 /* If the upper 32 bits of the BAR are not zero, the 1099 * memory is inaccessible to us; ignore the BAR. 1100 */ 1101 if (bar2 != 0) 1102 { 1103 if (debug) 1104 { 1105 printf("\tbar_%d: (64-bit BAR with" 1106 " high bits set)\n", bar_nr); 1107 } 1108 1109 return width; 1110 } 1111 1112 break; 1113 1114 default: 1115 /* Ignore the BAR. */ 1116 if (debug) 1117 { 1118 printf("\tbar_%d: (unknown type %x)\n", 1119 bar_nr, type); 1120 } 1121 1122 return width; 1123 } 1124 1125 /* Disable mem access before probing for BAR's size */ 1126 cmd = __pci_attr_r16(devind, PCI_CR); 1127 __pci_attr_w16(devind, PCI_CR, cmd & ~PCI_CR_MEM_EN); 1128 1129 /* Probe BAR's size */ 1130 __pci_attr_w32(devind, reg, 0xffffffff); 1131 bar2= __pci_attr_r32(devind, reg); 1132 1133 /* Restore original values */ 1134 __pci_attr_w32(devind, reg, bar); 1135 __pci_attr_w16(devind, PCI_CR, cmd); 1136 1137 if (bar2 == 0) 1138 return width; /* Reg. is not implemented */ 1139 1140 prefetch= !!(bar & PCI_BAR_PREFETCH); 1141 bar &= PCI_BAR_MEM_MASK; /* Clear non-address bits */ 1142 bar2 &= PCI_BAR_MEM_MASK; 1143 bar2= (~bar2)+1; 1144 if (debug) 1145 { 1146 printf("\tbar_%d: 0x%x bytes at 0x%x%s memory%s\n", 1147 bar_nr, bar2, bar, 1148 prefetch ? " prefetchable" : "", 1149 type == PCI_TYPE_64 ? ", 64-bit" : ""); 1150 } 1151 1152 dev_bar_nr= pcidev[devind].pd_bar_nr++; 1153 pcidev[devind].pd_bar[dev_bar_nr].pb_flags= 0; 1154 pcidev[devind].pd_bar[dev_bar_nr].pb_base= bar; 1155 pcidev[devind].pd_bar[dev_bar_nr].pb_size= bar2; 1156 pcidev[devind].pd_bar[dev_bar_nr].pb_nr= bar_nr; 1157 if (bar == 0) 1158 { 1159 pcidev[devind].pd_bar[dev_bar_nr].pb_flags |= 1160 PBF_INCOMPLETE; 1161 } 1162 } 1163 1164 return width; 1165 } 1166 1167 static void 1168 record_bars(int devind, int last_reg) 1169 { 1170 int i, reg, width; 1171 1172 for (i= 0, reg= PCI_BAR; reg <= last_reg; i += width, reg += 4 * width) 1173 { 1174 width = record_bar(devind, i, reg == last_reg); 1175 } 1176 } 1177 1178 static void 1179 record_bars_normal(int devind) 1180 { 1181 int i, j, clear_01, clear_23, pb_nr; 1182 1183 /* The BAR area of normal devices is six DWORDs in size. */ 1184 record_bars(devind, PCI_BAR_6); 1185 1186 /* Special case code for IDE controllers in compatibility mode */ 1187 if (pcidev[devind].pd_baseclass == PCI_BCR_MASS_STORAGE && 1188 pcidev[devind].pd_subclass == PCI_MS_IDE) 1189 { 1190 /* IDE device */ 1191 clear_01= 0; 1192 clear_23= 0; 1193 if (!(pcidev[devind].pd_infclass & PCI_IDE_PRI_NATIVE)) 1194 { 1195 if (debug) 1196 { 1197 printf( 1198 "primary channel is not in native mode, clearing BARs 0 and 1\n"); 1199 } 1200 clear_01= 1; 1201 } 1202 if (!(pcidev[devind].pd_infclass & PCI_IDE_SEC_NATIVE)) 1203 { 1204 if (debug) 1205 { 1206 printf( 1207 "secondary channel is not in native mode, clearing BARs 2 and 3\n"); 1208 } 1209 clear_23= 1; 1210 } 1211 1212 j= 0; 1213 for (i= 0; i<pcidev[devind].pd_bar_nr; i++) 1214 { 1215 pb_nr= pcidev[devind].pd_bar[i].pb_nr; 1216 if ((pb_nr == 0 || pb_nr == 1) && clear_01) 1217 { 1218 if (debug) printf("skipping bar %d\n", pb_nr); 1219 continue; /* Skip */ 1220 } 1221 if ((pb_nr == 2 || pb_nr == 3) && clear_23) 1222 { 1223 if (debug) printf("skipping bar %d\n", pb_nr); 1224 continue; /* Skip */ 1225 } 1226 if (i == j) 1227 { 1228 j++; 1229 continue; /* No need to copy */ 1230 } 1231 pcidev[devind].pd_bar[j]= 1232 pcidev[devind].pd_bar[i]; 1233 j++; 1234 } 1235 pcidev[devind].pd_bar_nr= j; 1236 } 1237 } 1238 1239 static void 1240 record_bars_bridge(int devind) 1241 { 1242 u32_t base, limit, size; 1243 1244 /* The generic BAR area of PCI-to-PCI bridges is two DWORDs in size. 1245 * It may contain up to two 32-bit BARs, or one 64-bit BAR. 1246 */ 1247 record_bars(devind, PCI_BAR_2); 1248 1249 base= ((__pci_attr_r8(devind, PPB_IOBASE) & PPB_IOB_MASK) << 8) | 1250 (__pci_attr_r16(devind, PPB_IOBASEU16) << 16); 1251 limit= 0xff | 1252 ((__pci_attr_r8(devind, PPB_IOLIMIT) & PPB_IOL_MASK) << 8) | 1253 ((~PPB_IOL_MASK & 0xff) << 8) | 1254 (__pci_attr_r16(devind, PPB_IOLIMITU16) << 16); 1255 size= limit-base + 1; 1256 if (debug) 1257 { 1258 printf("\tI/O window: base 0x%x, limit 0x%x, size %d\n", 1259 base, limit, size); 1260 } 1261 1262 base= ((__pci_attr_r16(devind, PPB_MEMBASE) & PPB_MEMB_MASK) << 16); 1263 limit= 0xffff | 1264 ((__pci_attr_r16(devind, PPB_MEMLIMIT) & PPB_MEML_MASK) << 16) | 1265 ((~PPB_MEML_MASK & 0xffff) << 16); 1266 size= limit-base + 1; 1267 if (debug) 1268 { 1269 printf("\tMemory window: base 0x%x, limit 0x%x, size 0x%x\n", 1270 base, limit, size); 1271 } 1272 1273 /* Ignore the upper 32 bits */ 1274 base= ((__pci_attr_r16(devind, PPB_PFMEMBASE) & PPB_PFMEMB_MASK) << 16); 1275 limit= 0xffff | 1276 ((__pci_attr_r16(devind, PPB_PFMEMLIMIT) & 1277 PPB_PFMEML_MASK) << 16) | 1278 ((~PPB_PFMEML_MASK & 0xffff) << 16); 1279 size= limit-base + 1; 1280 if (debug) 1281 { 1282 printf( 1283 "\tPrefetchable memory window: base 0x%x, limit 0x%x, size 0x%x\n", 1284 base, limit, size); 1285 } 1286 } 1287 1288 static void 1289 record_bars_cardbus(int devind) 1290 { 1291 u32_t base, limit, size; 1292 1293 /* The generic BAR area of CardBus devices is one DWORD in size. */ 1294 record_bars(devind, PCI_BAR); 1295 1296 base= __pci_attr_r32(devind, CBB_MEMBASE_0); 1297 limit= __pci_attr_r32(devind, CBB_MEMLIMIT_0) | 1298 (~CBB_MEML_MASK & 0xffffffff); 1299 size= limit-base + 1; 1300 if (debug) 1301 { 1302 printf("\tMemory window 0: base 0x%x, limit 0x%x, size %d\n", 1303 base, limit, size); 1304 } 1305 1306 base= __pci_attr_r32(devind, CBB_MEMBASE_1); 1307 limit= __pci_attr_r32(devind, CBB_MEMLIMIT_1) | 1308 (~CBB_MEML_MASK & 0xffffffff); 1309 size= limit-base + 1; 1310 if (debug) 1311 { 1312 printf("\tMemory window 1: base 0x%x, limit 0x%x, size %d\n", 1313 base, limit, size); 1314 } 1315 1316 base= __pci_attr_r32(devind, CBB_IOBASE_0); 1317 limit= __pci_attr_r32(devind, CBB_IOLIMIT_0) | 1318 (~CBB_IOL_MASK & 0xffffffff); 1319 size= limit-base + 1; 1320 if (debug) 1321 { 1322 printf("\tI/O window 0: base 0x%x, limit 0x%x, size %d\n", 1323 base, limit, size); 1324 } 1325 1326 base= __pci_attr_r32(devind, CBB_IOBASE_1); 1327 limit= __pci_attr_r32(devind, CBB_IOLIMIT_1) | 1328 (~CBB_IOL_MASK & 0xffffffff); 1329 size= limit-base + 1; 1330 if (debug) 1331 { 1332 printf("\tI/O window 1: base 0x%x, limit 0x%x, size %d\n", 1333 base, limit, size); 1334 } 1335 } 1336 1337 static void 1338 complete_bars(void) 1339 { 1340 int i, j, bar_nr, reg; 1341 u32_t memgap_low, memgap_high, iogap_low, iogap_high, io_high, 1342 base, size, v32, diff1, diff2; 1343 kinfo_t kinfo; 1344 1345 if(OK != sys_getkinfo(&kinfo)) 1346 panic("can't get kinfo"); 1347 1348 /* Set memgap_low to just above physical memory */ 1349 memgap_low= kinfo.mem_high_phys; 1350 memgap_high= 0xfe000000; /* Leave space for the CPU (APIC) */ 1351 1352 if (debug) 1353 { 1354 printf("complete_bars: initial gap: [0x%x .. 0x%x>\n", 1355 memgap_low, memgap_high); 1356 } 1357 1358 /* Find the lowest memory base */ 1359 for (i= 0; i<nr_pcidev; i++) 1360 { 1361 for (j= 0; j<pcidev[i].pd_bar_nr; j++) 1362 { 1363 if (pcidev[i].pd_bar[j].pb_flags & PBF_IO) 1364 continue; 1365 if (pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE) 1366 continue; 1367 base= pcidev[i].pd_bar[j].pb_base; 1368 size= pcidev[i].pd_bar[j].pb_size; 1369 1370 if (base >= memgap_high) 1371 continue; /* Not in the gap */ 1372 if (base+size <= memgap_low) 1373 continue; /* Not in the gap */ 1374 1375 /* Reduce the gap by the smallest amount */ 1376 diff1= base+size-memgap_low; 1377 diff2= memgap_high-base; 1378 1379 if (diff1 < diff2) 1380 memgap_low= base+size; 1381 else 1382 memgap_high= base; 1383 } 1384 } 1385 1386 if (debug) 1387 { 1388 printf("complete_bars: intermediate gap: [0x%x .. 0x%x>\n", 1389 memgap_low, memgap_high); 1390 } 1391 1392 /* Should check main memory size */ 1393 if (memgap_high < memgap_low) 1394 { 1395 printf("PCI: bad memory gap: [0x%x .. 0x%x>\n", 1396 memgap_low, memgap_high); 1397 panic(NULL); 1398 } 1399 1400 iogap_high= 0x10000; 1401 iogap_low= 0x400; 1402 1403 /* Find the free I/O space */ 1404 for (i= 0; i<nr_pcidev; i++) 1405 { 1406 for (j= 0; j<pcidev[i].pd_bar_nr; j++) 1407 { 1408 if (!(pcidev[i].pd_bar[j].pb_flags & PBF_IO)) 1409 continue; 1410 if (pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE) 1411 continue; 1412 base= pcidev[i].pd_bar[j].pb_base; 1413 size= pcidev[i].pd_bar[j].pb_size; 1414 if (base >= iogap_high) 1415 continue; 1416 if (base+size <= iogap_low) 1417 continue; 1418 #if 0 1419 if (debug) 1420 { 1421 printf( 1422 "pci device %d (%04x:%04x), bar %d: base 0x%x, size 0x%x\n", 1423 i, pcidev[i].pd_vid, pcidev[i].pd_did, 1424 j, base, size); 1425 } 1426 #endif 1427 if (base+size-iogap_low < iogap_high-base) 1428 iogap_low= base+size; 1429 else 1430 iogap_high= base; 1431 } 1432 } 1433 1434 if (iogap_high < iogap_low) 1435 { 1436 if (debug) 1437 { 1438 printf("iogap_high too low, should panic\n"); 1439 } 1440 else 1441 panic("iogap_high too low: %d", iogap_high); 1442 } 1443 if (debug) 1444 printf("I/O range = [0x%x..0x%x>\n", iogap_low, iogap_high); 1445 1446 for (i= 0; i<nr_pcidev; i++) 1447 { 1448 for (j= 0; j<pcidev[i].pd_bar_nr; j++) 1449 { 1450 if (pcidev[i].pd_bar[j].pb_flags & PBF_IO) 1451 continue; 1452 if (!(pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE)) 1453 continue; 1454 size= pcidev[i].pd_bar[j].pb_size; 1455 if (size < PAGE_SIZE) 1456 size= PAGE_SIZE; 1457 base= memgap_high-size; 1458 base &= ~(u32_t)(size-1); 1459 if (base < memgap_low) 1460 panic("memory base too low: %d", base); 1461 memgap_high= base; 1462 bar_nr= pcidev[i].pd_bar[j].pb_nr; 1463 reg= PCI_BAR + 4*bar_nr; 1464 v32= __pci_attr_r32(i, reg); 1465 __pci_attr_w32(i, reg, v32 | base); 1466 if (debug) 1467 { 1468 printf( 1469 "complete_bars: allocated 0x%x size %d to %d.%d.%d, bar_%d\n", 1470 base, size, pcidev[i].pd_busnr, 1471 pcidev[i].pd_dev, pcidev[i].pd_func, 1472 bar_nr); 1473 } 1474 pcidev[i].pd_bar[j].pb_base= base; 1475 pcidev[i].pd_bar[j].pb_flags &= ~PBF_INCOMPLETE; 1476 } 1477 1478 io_high= iogap_high; 1479 for (j= 0; j<pcidev[i].pd_bar_nr; j++) 1480 { 1481 if (!(pcidev[i].pd_bar[j].pb_flags & PBF_IO)) 1482 continue; 1483 if (!(pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE)) 1484 continue; 1485 size= pcidev[i].pd_bar[j].pb_size; 1486 base= iogap_high-size; 1487 base &= ~(u32_t)(size-1); 1488 1489 /* Assume that ISA compatibility is required. Only 1490 * use the lowest 256 bytes out of every 1024 bytes. 1491 */ 1492 base &= 0xfcff; 1493 1494 if (base < iogap_low) 1495 printf("I/O base too low: %d", base); 1496 1497 iogap_high= base; 1498 bar_nr= pcidev[i].pd_bar[j].pb_nr; 1499 reg= PCI_BAR + 4*bar_nr; 1500 v32= __pci_attr_r32(i, reg); 1501 __pci_attr_w32(i, reg, v32 | base); 1502 if (debug) 1503 { 1504 printf( 1505 "complete_bars: allocated 0x%x size %d to %d.%d.%d, bar_%d\n", 1506 base, size, pcidev[i].pd_busnr, 1507 pcidev[i].pd_dev, pcidev[i].pd_func, 1508 bar_nr); 1509 } 1510 pcidev[i].pd_bar[j].pb_base= base; 1511 pcidev[i].pd_bar[j].pb_flags &= ~PBF_INCOMPLETE; 1512 1513 } 1514 if (iogap_high != io_high) 1515 { 1516 update_bridge4dev_io(i, iogap_high, 1517 io_high-iogap_high); 1518 } 1519 } 1520 1521 for (i= 0; i<nr_pcidev; i++) 1522 { 1523 for (j= 0; j<pcidev[i].pd_bar_nr; j++) 1524 { 1525 if (!(pcidev[i].pd_bar[j].pb_flags & PBF_INCOMPLETE)) 1526 continue; 1527 printf("should allocate resources for device %d\n", i); 1528 } 1529 } 1530 return; 1531 } 1532 1533 /*===========================================================================* 1534 * PCI Bridge Helpers * 1535 *===========================================================================*/ 1536 static void 1537 probe_bus(int busind) 1538 { 1539 u32_t dev, func, t3; 1540 u16_t vid, did, sts, sub_vid, sub_did; 1541 u8_t headt; 1542 u8_t baseclass, subclass, infclass; 1543 int devind, busnr; 1544 const char *s, *dstr; 1545 1546 if (debug) 1547 printf("probe_bus(%d)\n", busind); 1548 if (nr_pcidev >= NR_PCIDEV) 1549 panic("too many PCI devices: %d", nr_pcidev); 1550 devind= nr_pcidev; 1551 1552 busnr= pcibus[busind].pb_busnr; 1553 for (dev= 0; dev<32; dev++) 1554 { 1555 1556 for (func= 0; func < 8; func++) 1557 { 1558 pcidev[devind].pd_busnr= busnr; 1559 pcidev[devind].pd_dev= dev; 1560 pcidev[devind].pd_func= func; 1561 1562 pci_attr_wsts(devind, 1563 PSR_SSE|PSR_RMAS|PSR_RTAS); 1564 vid= __pci_attr_r16(devind, PCI_VID); 1565 did= __pci_attr_r16(devind, PCI_DID); 1566 headt= __pci_attr_r8(devind, PCI_HEADT); 1567 sts= pci_attr_rsts(devind); 1568 1569 #if 0 1570 printf("vid 0x%x, did 0x%x, headt 0x%x, sts 0x%x\n", 1571 vid, did, headt, sts); 1572 #endif 1573 1574 if (vid == NO_VID && did == NO_VID) 1575 { 1576 if (func == 0) 1577 break; /* Nothing here */ 1578 1579 /* Scan all functions of a multifunction 1580 * device. 1581 */ 1582 continue; 1583 } 1584 1585 if (sts & (PSR_SSE|PSR_RMAS|PSR_RTAS)) 1586 { 1587 static int warned = 0; 1588 1589 if(!warned) { 1590 printf( 1591 "PCI: ignoring bad value 0x%x in sts for QEMU\n", 1592 sts & (PSR_SSE|PSR_RMAS|PSR_RTAS)); 1593 warned = 1; 1594 } 1595 } 1596 1597 sub_vid= __pci_attr_r16(devind, PCI_SUBVID); 1598 sub_did= __pci_attr_r16(devind, PCI_SUBDID); 1599 1600 dstr= _pci_dev_name(vid, did); 1601 if (debug) 1602 { 1603 if (dstr) 1604 { 1605 printf("%d.%lu.%lu: %s (%04X:%04X)\n", 1606 busnr, (unsigned long)dev, 1607 (unsigned long)func, dstr, 1608 vid, did); 1609 } 1610 else 1611 { 1612 printf( 1613 "%d.%lu.%lu: Unknown device, vendor %04X (%s), device %04X\n", 1614 busnr, (unsigned long)dev, 1615 (unsigned long)func, vid, 1616 pci_vid_name(vid), did); 1617 } 1618 printf("Device index: %d\n", devind); 1619 printf("Subsystem: Vid 0x%x, did 0x%x\n", 1620 sub_vid, sub_did); 1621 } 1622 1623 baseclass= __pci_attr_r8(devind, PCI_BCR); 1624 subclass= __pci_attr_r8(devind, PCI_SCR); 1625 infclass= __pci_attr_r8(devind, PCI_PIFR); 1626 s= pci_subclass_name(baseclass << 24 | subclass << 16); 1627 if (!s) 1628 s= pci_baseclass_name(baseclass << 24); 1629 { 1630 if (!s) 1631 s= "(unknown class)"; 1632 } 1633 if (debug) 1634 { 1635 printf("\tclass %s (%X/%X/%X)\n", s, 1636 baseclass, subclass, infclass); 1637 } 1638 1639 if (is_duplicate(busnr, dev, func)) 1640 { 1641 printf("\tduplicate!\n"); 1642 if (func == 0 && !(headt & PHT_MULTIFUNC)) 1643 break; 1644 continue; 1645 } 1646 1647 devind= nr_pcidev; 1648 nr_pcidev++; 1649 pcidev[devind].pd_baseclass= baseclass; 1650 pcidev[devind].pd_subclass= subclass; 1651 pcidev[devind].pd_infclass= infclass; 1652 pcidev[devind].pd_vid= vid; 1653 pcidev[devind].pd_did= did; 1654 pcidev[devind].pd_sub_vid= sub_vid; 1655 pcidev[devind].pd_sub_did= sub_did; 1656 pcidev[devind].pd_inuse= 0; 1657 pcidev[devind].pd_bar_nr= 0; 1658 record_irq(devind); 1659 switch(headt & PHT_MASK) 1660 { 1661 case PHT_NORMAL: 1662 record_bars_normal(devind); 1663 break; 1664 case PHT_BRIDGE: 1665 record_bars_bridge(devind); 1666 break; 1667 case PHT_CARDBUS: 1668 record_bars_cardbus(devind); 1669 break; 1670 default: 1671 printf("\t%d.%d.%d: unknown header type %d\n", 1672 busind, dev, func, 1673 headt & PHT_MASK); 1674 break; 1675 } 1676 if (debug) 1677 print_capabilities(devind); 1678 1679 t3= ((baseclass << 16) | (subclass << 8) | infclass); 1680 #if 0 1681 if (t3 == PCI_T3_VGA || t3 == PCI_T3_VGA_OLD) 1682 report_vga(devind); 1683 #endif 1684 1685 if (nr_pcidev >= NR_PCIDEV) 1686 panic("too many PCI devices: %d", nr_pcidev); 1687 devind= nr_pcidev; 1688 1689 if (func == 0 && !(headt & PHT_MULTIFUNC)) 1690 break; 1691 } 1692 } 1693 } 1694 1695 1696 static u16_t 1697 pcibr_std_rsts(int busind) 1698 { 1699 int devind; 1700 1701 devind= pcibus[busind].pb_devind; 1702 return __pci_attr_r16(devind, PPB_SSTS); 1703 } 1704 1705 static void 1706 pcibr_std_wsts(int busind, u16_t value) 1707 { 1708 int devind; 1709 devind= pcibus[busind].pb_devind; 1710 1711 #if 0 1712 printf("pcibr_std_wsts(%d, 0x%X), devind= %d\n", 1713 busind, value, devind); 1714 #endif 1715 __pci_attr_w16(devind, PPB_SSTS, value); 1716 } 1717 1718 static u16_t 1719 pcibr_cb_rsts(int busind) 1720 { 1721 int devind; 1722 devind= pcibus[busind].pb_devind; 1723 1724 return __pci_attr_r16(devind, CBB_SSTS); 1725 } 1726 1727 static void 1728 pcibr_cb_wsts(int busind, u16_t value) 1729 { 1730 int devind; 1731 devind= pcibus[busind].pb_devind; 1732 1733 #if 0 1734 printf("pcibr_cb_wsts(%d, 0x%X), devind= %d\n", 1735 busind, value, devind); 1736 #endif 1737 __pci_attr_w16(devind, CBB_SSTS, value); 1738 } 1739 1740 static u16_t 1741 pcibr_via_rsts(int busind) 1742 { 1743 return 0; 1744 } 1745 1746 static void 1747 pcibr_via_wsts(int busind, u16_t value) 1748 { 1749 int devind; 1750 devind= pcibus[busind].pb_devind; 1751 1752 #if 0 1753 printf("pcibr_via_wsts(%d, 0x%X), devind= %d (not implemented)\n", 1754 busind, value, devind); 1755 #endif 1756 } 1757 1758 static void 1759 complete_bridges(void) 1760 { 1761 int i, freebus, devind, prim_busnr; 1762 1763 for (i= 0; i<nr_pcibus; i++) 1764 { 1765 if (!pcibus[i].pb_needinit) 1766 continue; 1767 printf("should allocate bus number for bus %d\n", i); 1768 freebus= get_freebus(); 1769 printf("got bus number %d\n", freebus); 1770 1771 devind= pcibus[i].pb_devind; 1772 1773 prim_busnr= pcidev[devind].pd_busnr; 1774 if (prim_busnr != 0) 1775 { 1776 printf( 1777 "complete_bridge: updating subordinate bus number not implemented\n"); 1778 } 1779 1780 pcibus[i].pb_needinit= 0; 1781 pcibus[i].pb_busnr= freebus; 1782 1783 printf("devind = %d\n", devind); 1784 printf("prim_busnr= %d\n", prim_busnr); 1785 1786 __pci_attr_w8(devind, PPB_PRIMBN, prim_busnr); 1787 __pci_attr_w8(devind, PPB_SECBN, freebus); 1788 __pci_attr_w8(devind, PPB_SUBORDBN, freebus); 1789 1790 printf("CR = 0x%x\n", __pci_attr_r16(devind, PCI_CR)); 1791 printf("SECBLT = 0x%x\n", __pci_attr_r8(devind, PPB_SECBLT)); 1792 printf("BRIDGECTRL = 0x%x\n", 1793 __pci_attr_r16(devind, PPB_BRIDGECTRL)); 1794 } 1795 } 1796 1797 /* 1798 * tells acpi which two busses are connected by this bridge. The primary bus 1799 * (pbnr) must be already known to acpi and it must map dev as the connection to 1800 * the secondary (sbnr) bus 1801 */ 1802 static void 1803 acpi_map_bridge(unsigned int pbnr, unsigned int dev, unsigned int sbnr) 1804 { 1805 int err; 1806 message m; 1807 1808 ((struct acpi_map_bridge_req *)&m)->hdr.request = ACPI_REQ_MAP_BRIDGE; 1809 ((struct acpi_map_bridge_req *)&m)->primary_bus = pbnr; 1810 ((struct acpi_map_bridge_req *)&m)->secondary_bus = sbnr; 1811 ((struct acpi_map_bridge_req *)&m)->device = dev; 1812 1813 if ((err = ipc_sendrec(acpi_ep, &m)) != OK) 1814 panic("PCI: error %d while receiveing from ACPI\n", err); 1815 1816 if (((struct acpi_map_bridge_resp *)&m)->err != OK) 1817 printf("PCI: acpi failed to map pci (%d) to pci (%d) bridge\n", 1818 pbnr, sbnr); 1819 } 1820 1821 static void 1822 do_pcibridge(int busind) 1823 { 1824 int devind, busnr; 1825 int ind, type; 1826 u16_t vid, did; 1827 u8_t sbusn, baseclass, subclass, infclass, headt; 1828 u32_t t3; 1829 1830 vid= did= 0; /* lint */ 1831 busnr= pcibus[busind].pb_busnr; 1832 for (devind= 0; devind< nr_pcidev; devind++) 1833 { 1834 if (pcidev[devind].pd_busnr != busnr) 1835 { 1836 #if 0 1837 printf("wrong bus\n"); 1838 #endif 1839 continue; 1840 } 1841 1842 vid= pcidev[devind].pd_vid; 1843 did= pcidev[devind].pd_did; 1844 /* LSC: The table is empty, so always true... 1845 if (pci_pcibridge[i].vid == 0) */ 1846 { 1847 headt= __pci_attr_r8(devind, PCI_HEADT); 1848 type= 0; 1849 if ((headt & PHT_MASK) == PHT_BRIDGE) 1850 type= PCI_PPB_STD; 1851 else if ((headt & PHT_MASK) == PHT_CARDBUS) 1852 type= PCI_PPB_CB; 1853 else 1854 { 1855 #if 0 1856 printf("not a bridge\n"); 1857 #endif 1858 continue; /* Not a bridge */ 1859 } 1860 1861 baseclass= __pci_attr_r8(devind, PCI_BCR); 1862 subclass= __pci_attr_r8(devind, PCI_SCR); 1863 infclass= __pci_attr_r8(devind, PCI_PIFR); 1864 t3= ((baseclass << 16) | (subclass << 8) | infclass); 1865 if (type == PCI_PPB_STD && 1866 t3 != PCI_T3_PCI2PCI && 1867 t3 != PCI_T3_PCI2PCI_SUBTR) 1868 { 1869 printf( 1870 "Unknown PCI class %02x/%02x/%02x for PCI-to-PCI bridge, device %04X:%04X\n", 1871 baseclass, subclass, infclass, 1872 vid, did); 1873 continue; 1874 } 1875 if (type == PCI_PPB_CB && 1876 t3 != PCI_T3_CARDBUS) 1877 { 1878 printf( 1879 "Unknown PCI class %02x/%02x/%02x for Cardbus bridge, device %04X:%04X\n", 1880 baseclass, subclass, infclass, 1881 vid, did); 1882 continue; 1883 } 1884 } 1885 1886 if (debug) 1887 { 1888 printf("%u.%u.%u: PCI-to-PCI bridge: %04X:%04X\n", 1889 pcidev[devind].pd_busnr, 1890 pcidev[devind].pd_dev, 1891 pcidev[devind].pd_func, vid, did); 1892 } 1893 1894 /* Assume that the BIOS initialized the secondary bus 1895 * number. 1896 */ 1897 sbusn= __pci_attr_r8(devind, PPB_SECBN); 1898 1899 if (nr_pcibus >= NR_PCIBUS) 1900 panic("too many PCI busses: %d", nr_pcibus); 1901 ind= nr_pcibus; 1902 nr_pcibus++; 1903 pcibus[ind].pb_type= PBT_PCIBRIDGE; 1904 pcibus[ind].pb_needinit= 1; 1905 pcibus[ind].pb_isabridge_dev= -1; 1906 pcibus[ind].pb_isabridge_type= 0; 1907 pcibus[ind].pb_devind= devind; 1908 pcibus[ind].pb_busnr= sbusn; 1909 pcibus[ind].pb_rreg8= pcibus[busind].pb_rreg8; 1910 pcibus[ind].pb_rreg16= pcibus[busind].pb_rreg16; 1911 pcibus[ind].pb_rreg32= pcibus[busind].pb_rreg32; 1912 pcibus[ind].pb_wreg8= pcibus[busind].pb_wreg8; 1913 pcibus[ind].pb_wreg16= pcibus[busind].pb_wreg16; 1914 pcibus[ind].pb_wreg32= pcibus[busind].pb_wreg32; 1915 switch(type) 1916 { 1917 case PCI_PPB_STD: 1918 pcibus[ind].pb_rsts= pcibr_std_rsts; 1919 pcibus[ind].pb_wsts= pcibr_std_wsts; 1920 break; 1921 case PCI_PPB_CB: 1922 pcibus[ind].pb_type= PBT_CARDBUS; 1923 pcibus[ind].pb_rsts= pcibr_cb_rsts; 1924 pcibus[ind].pb_wsts= pcibr_cb_wsts; 1925 break; 1926 case PCI_AGPB_VIA: 1927 pcibus[ind].pb_rsts= pcibr_via_rsts; 1928 pcibus[ind].pb_wsts= pcibr_via_wsts; 1929 break; 1930 default: 1931 panic("unknown PCI-PCI bridge type: %d", type); 1932 } 1933 1934 if (machine.apic_enabled) 1935 acpi_map_bridge(pcidev[devind].pd_busnr, 1936 pcidev[devind].pd_dev, sbusn); 1937 1938 if (debug) 1939 { 1940 printf( 1941 "bus(table) = %d, bus(sec) = %d, bus(subord) = %d\n", 1942 ind, sbusn, __pci_attr_r8(devind, PPB_SUBORDBN)); 1943 } 1944 if (sbusn == 0) 1945 { 1946 printf("Secondary bus number not initialized\n"); 1947 continue; 1948 } 1949 pcibus[ind].pb_needinit= 0; 1950 1951 probe_bus(ind); 1952 1953 /* Look for PCI bridges */ 1954 do_pcibridge(ind); 1955 } 1956 } 1957 1958 /*===========================================================================* 1959 * pci_intel_init * 1960 *===========================================================================*/ 1961 static void 1962 pci_intel_init() 1963 { 1964 /* Try to detect a know PCI controller. Read the Vendor ID and 1965 * the Device ID for function 0 of device 0. 1966 * Two times the value 0xffff suggests a system without a (compatible) 1967 * PCI controller. 1968 */ 1969 u32_t bus, dev, func; 1970 u16_t vid, did; 1971 int s, i, r, busind, busnr; 1972 const char *dstr; 1973 1974 bus= 0; 1975 dev= 0; 1976 func= 0; 1977 1978 vid= PCII_RREG16_(bus, dev, func, PCI_VID); 1979 did= PCII_RREG16_(bus, dev, func, PCI_DID); 1980 if (OK != (s=sys_outl(PCII_CONFADD, PCII_UNSEL))) 1981 printf("PCI: warning, sys_outl failed: %d\n", s); 1982 1983 if (nr_pcibus >= NR_PCIBUS) 1984 panic("too many PCI busses: %d", nr_pcibus); 1985 busind= nr_pcibus; 1986 nr_pcibus++; 1987 pcibus[busind].pb_type= PBT_INTEL_HOST; 1988 pcibus[busind].pb_needinit= 0; 1989 pcibus[busind].pb_isabridge_dev= -1; 1990 pcibus[busind].pb_isabridge_type= 0; 1991 pcibus[busind].pb_devind= -1; 1992 pcibus[busind].pb_busnr= 0; 1993 pcibus[busind].pb_rreg8= pcii_rreg8; 1994 pcibus[busind].pb_rreg16= pcii_rreg16; 1995 pcibus[busind].pb_rreg32= pcii_rreg32; 1996 pcibus[busind].pb_wreg8= pcii_wreg8; 1997 pcibus[busind].pb_wreg16= pcii_wreg16; 1998 pcibus[busind].pb_wreg32= pcii_wreg32; 1999 pcibus[busind].pb_rsts= pcii_rsts; 2000 pcibus[busind].pb_wsts= pcii_wsts; 2001 2002 dstr= _pci_dev_name(vid, did); 2003 if (!dstr) 2004 dstr= "unknown device"; 2005 if (debug) 2006 { 2007 printf("pci_intel_init: %s (%04X:%04X)\n", 2008 dstr, vid, did); 2009 } 2010 2011 probe_bus(busind); 2012 2013 r= do_isabridge(busind); 2014 if (r != OK) 2015 { 2016 busnr= pcibus[busind].pb_busnr; 2017 2018 /* Disable all devices for this bus */ 2019 for (i= 0; i<nr_pcidev; i++) 2020 { 2021 if (pcidev[i].pd_busnr != busnr) 2022 continue; 2023 pcidev[i].pd_inuse= 1; 2024 } 2025 return; 2026 } 2027 2028 /* Look for PCI bridges */ 2029 do_pcibridge(busind); 2030 2031 /* Allocate bus numbers for uninitialized bridges */ 2032 complete_bridges(); 2033 2034 /* Allocate I/O and memory resources for uninitialized devices */ 2035 complete_bars(); 2036 } 2037 2038 #if 0 2039 /*===========================================================================* 2040 * report_vga * 2041 *===========================================================================*/ 2042 static void 2043 report_vga(int devind) 2044 { 2045 /* Report the amount of video memory. This is needed by the X11R6 2046 * postinstall script to chmem the X server. Hopefully this can be 2047 * removed when we get virtual memory. 2048 */ 2049 size_t amount, size; 2050 int i; 2051 2052 amount= 0; 2053 for (i= 0; i<pcidev[devind].pd_bar_nr; i++) 2054 { 2055 if (pcidev[devind].pd_bar[i].pb_flags & PBF_IO) 2056 continue; 2057 size= pcidev[devind].pd_bar[i].pb_size; 2058 if (size < amount) 2059 continue; 2060 amount= size; 2061 } 2062 if (size != 0) 2063 { 2064 printf("PCI: video memory for device at %d.%d.%d: %d bytes\n", 2065 pcidev[devind].pd_busnr, 2066 pcidev[devind].pd_dev, 2067 pcidev[devind].pd_func, 2068 amount); 2069 } 2070 } 2071 #endif 2072 2073 2074 /*===========================================================================* 2075 * visible * 2076 *===========================================================================*/ 2077 static int 2078 visible(struct rs_pci *aclp, int devind) 2079 { 2080 u16_t acl_sub_vid, acl_sub_did; 2081 int i; 2082 u32_t class_id; 2083 2084 if (!aclp) 2085 return TRUE; /* Should be changed when ACLs become 2086 * mandatory. Do note that procfs relies 2087 * on being able to see all devices. 2088 */ 2089 /* Check whether the caller is allowed to get this device. */ 2090 for (i= 0; i<aclp->rsp_nr_device; i++) 2091 { 2092 acl_sub_vid = aclp->rsp_device[i].sub_vid; 2093 acl_sub_did = aclp->rsp_device[i].sub_did; 2094 if (aclp->rsp_device[i].vid == pcidev[devind].pd_vid && 2095 aclp->rsp_device[i].did == pcidev[devind].pd_did && 2096 (acl_sub_vid == NO_SUB_VID || 2097 acl_sub_vid == pcidev[devind].pd_sub_vid) && 2098 (acl_sub_did == NO_SUB_DID || 2099 acl_sub_did == pcidev[devind].pd_sub_did)) 2100 { 2101 return TRUE; 2102 } 2103 } 2104 if (!aclp->rsp_nr_class) 2105 return FALSE; 2106 2107 class_id= (pcidev[devind].pd_baseclass << 16) | 2108 (pcidev[devind].pd_subclass << 8) | 2109 pcidev[devind].pd_infclass; 2110 for (i= 0; i<aclp->rsp_nr_class; i++) 2111 { 2112 if (aclp->rsp_class[i].pciclass == 2113 (class_id & aclp->rsp_class[i].mask)) 2114 { 2115 return TRUE; 2116 } 2117 } 2118 2119 return FALSE; 2120 } 2121 2122 /*===========================================================================* 2123 * sef_cb_init_fresh * 2124 *===========================================================================*/ 2125 int 2126 sef_cb_init(int type, sef_init_info_t *info) 2127 { 2128 /* Initialize the driver. */ 2129 int do_announce_driver = -1; 2130 2131 long v; 2132 int i, r; 2133 struct rprocpub rprocpub[NR_BOOT_PROCS]; 2134 2135 v= 0; 2136 env_parse("pci_debug", "d", 0, &v, 0, 1); 2137 debug= v; 2138 2139 if (sys_getmachine(&machine)) { 2140 printf("PCI: no machine\n"); 2141 return ENODEV; 2142 } 2143 if (machine.apic_enabled && 2144 ds_retrieve_label_endpt("acpi", &acpi_ep) != OK) { 2145 panic("PCI: Cannot use APIC mode without ACPI!\n"); 2146 } 2147 2148 /* Only Intel (compatible) PCI controllers are supported at the 2149 * moment. 2150 */ 2151 pci_intel_init(); 2152 2153 /* Map all the services in the boot image. */ 2154 if ((r = sys_safecopyfrom(RS_PROC_NR, info->rproctab_gid, 0, 2155 (vir_bytes) rprocpub, sizeof(rprocpub))) != OK) { 2156 panic("sys_safecopyfrom failed: %d", r); 2157 } 2158 for(i=0;i < NR_BOOT_PROCS;i++) { 2159 if (rprocpub[i].in_use) { 2160 if ((r = map_service(&rprocpub[i])) != OK) { 2161 panic("unable to map service: %d", r); 2162 } 2163 } 2164 } 2165 2166 switch(type) { 2167 case SEF_INIT_FRESH: 2168 case SEF_INIT_RESTART: 2169 do_announce_driver = TRUE; 2170 break; 2171 case SEF_INIT_LU: 2172 do_announce_driver = FALSE; 2173 break; 2174 default: 2175 panic("Unknown type of restart"); 2176 break; 2177 } 2178 2179 /* Announce we are up when necessary. */ 2180 if (TRUE == do_announce_driver) { 2181 chardriver_announce(); 2182 } 2183 2184 /* Initialization completed successfully. */ 2185 return OK; 2186 } 2187 2188 /*===========================================================================* 2189 * map_service * 2190 *===========================================================================*/ 2191 int 2192 map_service(struct rprocpub *rpub) 2193 { 2194 /* Map a new service by registering a new acl entry if required. */ 2195 int i; 2196 2197 /* Stop right now if no pci device or class is found. */ 2198 if(rpub->pci_acl.rsp_nr_device == 0 2199 && rpub->pci_acl.rsp_nr_class == 0) { 2200 return(OK); 2201 } 2202 2203 /* Find a free acl slot. */ 2204 for (i= 0; i<NR_DRIVERS; i++) 2205 { 2206 if (!pci_acl[i].inuse) 2207 break; 2208 } 2209 if (i >= NR_DRIVERS) 2210 { 2211 printf("PCI: map_service: table is full\n"); 2212 return ENOMEM; 2213 } 2214 2215 /* Initialize acl slot. */ 2216 pci_acl[i].inuse = 1; 2217 pci_acl[i].acl = rpub->pci_acl; 2218 2219 return OK; 2220 } 2221 2222 /*===========================================================================* 2223 * _pci_find_dev * 2224 *===========================================================================*/ 2225 int 2226 _pci_find_dev(u8_t bus, u8_t dev, u8_t func, int *devindp) 2227 { 2228 int devind; 2229 2230 for (devind= 0; devind < nr_pcidev; devind++) 2231 { 2232 if (pcidev[devind].pd_busnr == bus && 2233 pcidev[devind].pd_dev == dev && 2234 pcidev[devind].pd_func == func) 2235 { 2236 break; 2237 } 2238 } 2239 2240 if (devind >= nr_pcidev) 2241 return 0; 2242 2243 *devindp= devind; 2244 2245 return 1; 2246 } 2247 2248 /*===========================================================================* 2249 * _pci_first_dev * 2250 *===========================================================================*/ 2251 int 2252 _pci_first_dev(struct rs_pci *aclp, int *devindp, u16_t *vidp, 2253 u16_t *didp) 2254 { 2255 int devind; 2256 2257 for (devind= 0; devind < nr_pcidev; devind++) 2258 { 2259 if (!visible(aclp, devind)) 2260 continue; 2261 break; 2262 } 2263 if (devind >= nr_pcidev) 2264 return 0; 2265 *devindp= devind; 2266 *vidp= pcidev[devind].pd_vid; 2267 *didp= pcidev[devind].pd_did; 2268 return 1; 2269 } 2270 2271 /*===========================================================================* 2272 * _pci_next_dev * 2273 *===========================================================================*/ 2274 int 2275 _pci_next_dev(struct rs_pci *aclp, int *devindp, u16_t *vidp, u16_t *didp) 2276 { 2277 int devind; 2278 2279 for (devind= *devindp+1; devind < nr_pcidev; devind++) 2280 { 2281 if (!visible(aclp, devind)) 2282 continue; 2283 break; 2284 } 2285 if (devind >= nr_pcidev) 2286 return 0; 2287 *devindp= devind; 2288 *vidp= pcidev[devind].pd_vid; 2289 *didp= pcidev[devind].pd_did; 2290 return 1; 2291 } 2292 2293 /*===========================================================================* 2294 * _pci_grant_access * 2295 *===========================================================================*/ 2296 int 2297 _pci_grant_access(int devind, endpoint_t proc) 2298 { 2299 int i, ilr; 2300 int r = OK; 2301 struct io_range ior; 2302 struct minix_mem_range mr; 2303 2304 for (i= 0; i<pcidev[devind].pd_bar_nr; i++) 2305 { 2306 if (pcidev[devind].pd_bar[i].pb_flags & PBF_INCOMPLETE) 2307 { 2308 printf("pci_reserve_a: BAR %d is incomplete\n", i); 2309 continue; 2310 } 2311 if (pcidev[devind].pd_bar[i].pb_flags & PBF_IO) 2312 { 2313 ior.ior_base= pcidev[devind].pd_bar[i].pb_base; 2314 ior.ior_limit= ior.ior_base + 2315 pcidev[devind].pd_bar[i].pb_size-1; 2316 2317 if(debug) { 2318 printf( 2319 "pci_reserve_a: for proc %d, adding I/O range [0x%x..0x%x]\n", 2320 proc, ior.ior_base, ior.ior_limit); 2321 } 2322 r= sys_privctl(proc, SYS_PRIV_ADD_IO, &ior); 2323 if (r != OK) 2324 { 2325 printf("sys_privctl failed for proc %d: %d\n", 2326 proc, r); 2327 } 2328 } 2329 else 2330 { 2331 mr.mr_base= pcidev[devind].pd_bar[i].pb_base; 2332 mr.mr_limit= mr.mr_base + 2333 pcidev[devind].pd_bar[i].pb_size-1; 2334 2335 r= sys_privctl(proc, SYS_PRIV_ADD_MEM, &mr); 2336 if (r != OK) 2337 { 2338 printf("sys_privctl failed for proc %d: %d\n", 2339 proc, r); 2340 } 2341 } 2342 } 2343 ilr= pcidev[devind].pd_ilr; 2344 if (ilr != PCI_ILR_UNKNOWN) 2345 { 2346 if(debug) printf("pci_reserve_a: adding IRQ %d\n", ilr); 2347 r= sys_privctl(proc, SYS_PRIV_ADD_IRQ, &ilr); 2348 if (r != OK) 2349 { 2350 printf("sys_privctl failed for proc %d: %d\n", 2351 proc, r); 2352 } 2353 } 2354 2355 return r; 2356 } 2357 2358 /*===========================================================================* 2359 * _pci_reserve * 2360 *===========================================================================*/ 2361 int 2362 _pci_reserve(int devind, endpoint_t proc, struct rs_pci *aclp) 2363 { 2364 if (devind < 0 || devind >= nr_pcidev) 2365 { 2366 printf("pci_reserve_a: bad devind: %d\n", devind); 2367 return EINVAL; 2368 } 2369 if (!visible(aclp, devind)) 2370 { 2371 printf("pci_reserve_a: %u is not allowed to reserve %d\n", 2372 proc, devind); 2373 return EPERM; 2374 } 2375 2376 if(pcidev[devind].pd_inuse && pcidev[devind].pd_proc != proc) 2377 return EBUSY; 2378 2379 pcidev[devind].pd_inuse= 1; 2380 pcidev[devind].pd_proc= proc; 2381 2382 return _pci_grant_access(devind, proc); 2383 } 2384 2385 /*===========================================================================* 2386 * _pci_release * 2387 *===========================================================================*/ 2388 void 2389 _pci_release(endpoint_t proc) 2390 { 2391 int i; 2392 2393 for (i= 0; i<nr_pcidev; i++) 2394 { 2395 if (!pcidev[i].pd_inuse) 2396 continue; 2397 if (pcidev[i].pd_proc != proc) 2398 continue; 2399 pcidev[i].pd_inuse= 0; 2400 } 2401 } 2402 2403 /*===========================================================================* 2404 * _pci_ids * 2405 *===========================================================================*/ 2406 int 2407 _pci_ids(int devind, u16_t *vidp, u16_t *didp) 2408 { 2409 if (devind < 0 || devind >= nr_pcidev) 2410 return EINVAL; 2411 2412 *vidp= pcidev[devind].pd_vid; 2413 *didp= pcidev[devind].pd_did; 2414 return OK; 2415 } 2416 2417 /*===========================================================================* 2418 * _pci_rescan_bus * 2419 *===========================================================================*/ 2420 void 2421 _pci_rescan_bus(u8_t busnr) 2422 { 2423 int busind; 2424 2425 busind= get_busind(busnr); 2426 probe_bus(busind); 2427 2428 /* Allocate bus numbers for uninitialized bridges */ 2429 complete_bridges(); 2430 2431 /* Allocate I/O and memory resources for uninitialized devices */ 2432 complete_bars(); 2433 } 2434 2435 /*===========================================================================* 2436 * _pci_slot_name * 2437 *===========================================================================*/ 2438 int 2439 _pci_slot_name(int devind, char **cpp) 2440 { 2441 static char label[]= "ddd.ddd.ddd.ddd"; 2442 char *end; 2443 char *p; 2444 2445 if (devind < 0 || devind >= nr_pcidev) 2446 return EINVAL; 2447 2448 p= label; 2449 end= label+sizeof(label); 2450 2451 /* FIXME: domain nb is always 0 on 32bit system, but we should 2452 * retrieve it properly, somehow. */ 2453 ntostr(0, &p, end); 2454 *p++= '.'; 2455 2456 ntostr(pcidev[devind].pd_busnr, &p, end); 2457 *p++= '.'; 2458 2459 ntostr(pcidev[devind].pd_dev, &p, end); 2460 *p++= '.'; 2461 2462 ntostr(pcidev[devind].pd_func, &p, end); 2463 2464 *cpp= label; 2465 return OK; 2466 } 2467 2468 /*===========================================================================* 2469 * _pci_dev_name * 2470 *===========================================================================*/ 2471 const char * 2472 _pci_dev_name(u16_t vid, u16_t did) 2473 { 2474 2475 return pci_findproduct_real(did << 16 | vid); 2476 } 2477 2478 /*===========================================================================* 2479 * _pci_get_bar * 2480 *===========================================================================*/ 2481 int 2482 _pci_get_bar(int devind, int port, u32_t *base, u32_t *size, 2483 int *ioflag) 2484 { 2485 int i, reg; 2486 2487 if (devind < 0 || devind >= nr_pcidev) 2488 return EINVAL; 2489 2490 for (i= 0; i < pcidev[devind].pd_bar_nr; i++) 2491 { 2492 reg= PCI_BAR+4*pcidev[devind].pd_bar[i].pb_nr; 2493 2494 if (reg == port) 2495 { 2496 if (pcidev[devind].pd_bar[i].pb_flags & PBF_INCOMPLETE) 2497 return EINVAL; 2498 2499 *base= pcidev[devind].pd_bar[i].pb_base; 2500 *size= pcidev[devind].pd_bar[i].pb_size; 2501 *ioflag= 2502 !!(pcidev[devind].pd_bar[i].pb_flags & PBF_IO); 2503 return OK; 2504 } 2505 } 2506 return EINVAL; 2507 } 2508 2509 /*===========================================================================* 2510 * _pci_attr_r8 * 2511 *===========================================================================*/ 2512 int 2513 _pci_attr_r8(int devind, int port, u8_t *vp) 2514 { 2515 if (devind < 0 || devind >= nr_pcidev) 2516 return EINVAL; 2517 if (port < 0 || port > 256-1) 2518 return EINVAL; 2519 2520 *vp= __pci_attr_r8(devind, port); 2521 return OK; 2522 } 2523 2524 /*===========================================================================* 2525 * _pci_attr_r16 * 2526 *===========================================================================*/ 2527 int 2528 _pci_attr_r16(int devind, int port, u16_t *vp) 2529 { 2530 if (devind < 0 || devind >= nr_pcidev) 2531 return EINVAL; 2532 if (port < 0 || port > 256-2) 2533 return EINVAL; 2534 2535 *vp= __pci_attr_r16(devind, port); 2536 return OK; 2537 } 2538 2539 /*===========================================================================* 2540 * _pci_attr_r32 * 2541 *===========================================================================*/ 2542 int 2543 _pci_attr_r32(int devind, int port, u32_t *vp) 2544 { 2545 if (devind < 0 || devind >= nr_pcidev) 2546 return EINVAL; 2547 if (port < 0 || port > 256-4) 2548 return EINVAL; 2549 2550 *vp= __pci_attr_r32(devind, port); 2551 return OK; 2552 } 2553 2554 /*===========================================================================* 2555 * _pci_attr_w8 * 2556 *===========================================================================*/ 2557 int 2558 _pci_attr_w8(int devind, int port, u8_t value) 2559 { 2560 if (devind < 0 || devind >= nr_pcidev) 2561 return EINVAL; 2562 if (port < 0 || port > 256-1) 2563 return EINVAL; 2564 2565 __pci_attr_w8(devind, port, value); 2566 return OK; 2567 } 2568 2569 /*===========================================================================* 2570 * _pci_attr_w16 * 2571 *===========================================================================*/ 2572 int 2573 _pci_attr_w16(int devind, int port, u16_t value) 2574 { 2575 if (devind < 0 || devind >= nr_pcidev) 2576 return EINVAL; 2577 if (port < 0 || port > 256-2) 2578 return EINVAL; 2579 2580 __pci_attr_w16(devind, port, value); 2581 return OK; 2582 } 2583 2584 /*===========================================================================* 2585 * _pci_attr_w32 * 2586 *===========================================================================*/ 2587 int 2588 _pci_attr_w32(int devind, int port, u32_t value) 2589 { 2590 if (devind < 0 || devind >= nr_pcidev) 2591 return EINVAL; 2592 if (port < 0 || port > 256-4) 2593 return EINVAL; 2594 2595 __pci_attr_w32(devind, port, value); 2596 return OK; 2597 } 2598