1*433d6423SLionel Sambuc #ifndef _OMAP_I2C_REGISTERS_H 2*433d6423SLionel Sambuc #define _OMAP_I2C_REGISTERS_H 3*433d6423SLionel Sambuc 4*433d6423SLionel Sambuc /* I2C Addresses for am335x (BeagleBone White / BeagleBone Black) */ 5*433d6423SLionel Sambuc 6*433d6423SLionel Sambuc /* IRQ Numbers */ 7*433d6423SLionel Sambuc #define AM335X_I2C0_IRQ 70 8*433d6423SLionel Sambuc #define AM335X_I2C1_IRQ 71 9*433d6423SLionel Sambuc #define AM335X_I2C2_IRQ 30 10*433d6423SLionel Sambuc 11*433d6423SLionel Sambuc /* Base Addresses */ 12*433d6423SLionel Sambuc #define AM335X_I2C0_BASE 0x44e0b000 13*433d6423SLionel Sambuc #define AM335X_I2C1_BASE 0x4802a000 14*433d6423SLionel Sambuc #define AM335X_I2C2_BASE 0x4819c000 15*433d6423SLionel Sambuc 16*433d6423SLionel Sambuc /* Size of I2C Register Address Range */ 17*433d6423SLionel Sambuc #define AM335X_I2C0_SIZE 0x1000 18*433d6423SLionel Sambuc #define AM335X_I2C1_SIZE 0x1000 19*433d6423SLionel Sambuc #define AM335X_I2C2_SIZE 0x1000 20*433d6423SLionel Sambuc 21*433d6423SLionel Sambuc /* Register Offsets */ 22*433d6423SLionel Sambuc #define AM335X_I2C_REVNB_LO 0x00 23*433d6423SLionel Sambuc #define AM335X_I2C_REVNB_HI 0x04 24*433d6423SLionel Sambuc #define AM335X_I2C_SYSC 0x10 25*433d6423SLionel Sambuc #define AM335X_I2C_IRQSTATUS_RAW 0x24 26*433d6423SLionel Sambuc #define AM335X_I2C_IRQSTATUS 0x28 27*433d6423SLionel Sambuc #define AM335X_I2C_IRQENABLE_SET 0x2c 28*433d6423SLionel Sambuc #define AM335X_I2C_IRQENABLE_CLR 0x30 29*433d6423SLionel Sambuc #define AM335X_I2C_WE 0x34 30*433d6423SLionel Sambuc #define AM335X_I2C_DMARXENABLE_SET 0x38 31*433d6423SLionel Sambuc #define AM335X_I2C_DMATXENABLE_SET 0x3c 32*433d6423SLionel Sambuc #define AM335X_I2C_DMARXENABLE_CLR 0x40 33*433d6423SLionel Sambuc #define AM335X_I2C_DMATXENABLE_CLR 0x44 34*433d6423SLionel Sambuc #define AM335X_I2C_DMARXWAKE_EN 0x48 35*433d6423SLionel Sambuc #define AM335X_I2C_DMATXWAKE_EN 0x4c 36*433d6423SLionel Sambuc #define AM335X_I2C_SYSS 0x90 37*433d6423SLionel Sambuc #define AM335X_I2C_BUF 0x94 38*433d6423SLionel Sambuc #define AM335X_I2C_CNT 0x98 39*433d6423SLionel Sambuc #define AM335X_I2C_DATA 0x9c 40*433d6423SLionel Sambuc #define AM335X_I2C_CON 0xa4 41*433d6423SLionel Sambuc #define AM335X_I2C_OA 0xa8 42*433d6423SLionel Sambuc #define AM335X_I2C_SA 0xac 43*433d6423SLionel Sambuc #define AM335X_I2C_PSC 0xb0 44*433d6423SLionel Sambuc #define AM335X_I2C_SCLL 0xb4 45*433d6423SLionel Sambuc #define AM335X_I2C_SCLH 0xb8 46*433d6423SLionel Sambuc #define AM335X_I2C_SYSTEST 0xbc 47*433d6423SLionel Sambuc #define AM335X_I2C_BUFSTAT 0xc0 48*433d6423SLionel Sambuc #define AM335X_I2C_OA1 0xc4 49*433d6423SLionel Sambuc #define AM335X_I2C_OA2 0xc8 50*433d6423SLionel Sambuc #define AM335X_I2C_OA3 0xcc 51*433d6423SLionel Sambuc #define AM335X_I2C_ACTOA 0xd0 52*433d6423SLionel Sambuc #define AM335X_I2C_SBLOCK 0xd4 53*433d6423SLionel Sambuc 54*433d6423SLionel Sambuc /* Constants */ 55*433d6423SLionel Sambuc #define AM335X_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */ 56*433d6423SLionel Sambuc #define AM335X_MODULE_CLOCK 12000000 /* 12 MHz */ 57*433d6423SLionel Sambuc 58*433d6423SLionel Sambuc /* I2C_REV value found on the BeagleBone / BeagleBone Black */ 59*433d6423SLionel Sambuc #define AM335X_REV_MAJOR 0x00 60*433d6423SLionel Sambuc #define AM335X_REV_MINOR 0x0b 61*433d6423SLionel Sambuc 62*433d6423SLionel Sambuc /* I2C Addresses for dm37xx (BeagleBoard-xM) */ 63*433d6423SLionel Sambuc 64*433d6423SLionel Sambuc /* IRQ Numbers */ 65*433d6423SLionel Sambuc #define DM37XX_I2C0_IRQ 56 66*433d6423SLionel Sambuc #define DM37XX_I2C1_IRQ 57 67*433d6423SLionel Sambuc #define DM37XX_I2C2_IRQ 61 68*433d6423SLionel Sambuc 69*433d6423SLionel Sambuc /* Base Addresses */ 70*433d6423SLionel Sambuc #define DM37XX_I2C0_BASE 0x48070000 71*433d6423SLionel Sambuc #define DM37XX_I2C1_BASE 0x48072000 72*433d6423SLionel Sambuc #define DM37XX_I2C2_BASE 0x48060000 73*433d6423SLionel Sambuc 74*433d6423SLionel Sambuc /* Size of I2C Register Address Range */ 75*433d6423SLionel Sambuc #define DM37XX_I2C0_SIZE 0x1000 76*433d6423SLionel Sambuc #define DM37XX_I2C1_SIZE 0x1000 77*433d6423SLionel Sambuc #define DM37XX_I2C2_SIZE 0x1000 78*433d6423SLionel Sambuc 79*433d6423SLionel Sambuc /* Register Offsets */ 80*433d6423SLionel Sambuc #define DM37XX_I2C_REV 0x00 81*433d6423SLionel Sambuc #define DM37XX_I2C_IE 0x04 82*433d6423SLionel Sambuc #define DM37XX_I2C_STAT 0x08 83*433d6423SLionel Sambuc #define DM37XX_I2C_WE 0x0C 84*433d6423SLionel Sambuc #define DM37XX_I2C_SYSS 0x10 85*433d6423SLionel Sambuc #define DM37XX_I2C_BUF 0x14 86*433d6423SLionel Sambuc #define DM37XX_I2C_CNT 0x18 87*433d6423SLionel Sambuc #define DM37XX_I2C_DATA 0x1c 88*433d6423SLionel Sambuc #define DM37XX_I2C_SYSC 0x20 89*433d6423SLionel Sambuc #define DM37XX_I2C_CON 0x24 90*433d6423SLionel Sambuc #define DM37XX_I2C_OA0 0x28 91*433d6423SLionel Sambuc #define DM37XX_I2C_SA 0x2c 92*433d6423SLionel Sambuc #define DM37XX_I2C_PSC 0x30 93*433d6423SLionel Sambuc #define DM37XX_I2C_SCLL 0x34 94*433d6423SLionel Sambuc #define DM37XX_I2C_SCLH 0x38 95*433d6423SLionel Sambuc #define DM37XX_I2C_SYSTEST 0x3c 96*433d6423SLionel Sambuc #define DM37XX_I2C_BUFSTAT 0x40 97*433d6423SLionel Sambuc #define DM37XX_I2C_OA1 0x44 98*433d6423SLionel Sambuc #define DM37XX_I2C_OA2 0x48 99*433d6423SLionel Sambuc #define DM37XX_I2C_OA3 0x4c 100*433d6423SLionel Sambuc #define DM37XX_I2C_ACTOA 0x50 101*433d6423SLionel Sambuc #define DM37XX_I2C_SBLOCK 0x54 102*433d6423SLionel Sambuc 103*433d6423SLionel Sambuc /* Constants */ 104*433d6423SLionel Sambuc #define DM37XX_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */ 105*433d6423SLionel Sambuc #define DM37XX_MODULE_CLOCK 19200000 /* 19.2 MHz */ 106*433d6423SLionel Sambuc 107*433d6423SLionel Sambuc #define DM37XX_REV_MAJOR 0x04 108*433d6423SLionel Sambuc #define DM37XX_REV_MINOR 0x00 109*433d6423SLionel Sambuc 110*433d6423SLionel Sambuc /* Shared Values */ 111*433d6423SLionel Sambuc 112*433d6423SLionel Sambuc #define BUS_SPEED_100KHz 100000 /* 100 KHz */ 113*433d6423SLionel Sambuc #define BUS_SPEED_400KHz 400000 /* 400 KHz */ 114*433d6423SLionel Sambuc #define I2C_OWN_ADDRESS 0x01 115*433d6423SLionel Sambuc 116*433d6423SLionel Sambuc /* Masks */ 117*433d6423SLionel Sambuc 118*433d6423SLionel Sambuc #define MAX_I2C_SA_MASK (0x3ff) /* Highest 10 bit address -- 9..0 */ 119*433d6423SLionel Sambuc 120*433d6423SLionel Sambuc /* Bit Offsets within Registers (only those used are listed) */ 121*433d6423SLionel Sambuc 122*433d6423SLionel Sambuc /* Same offsets for both dm37xx and am335x */ 123*433d6423SLionel Sambuc 124*433d6423SLionel Sambuc #define I2C_EN 15 /* I2C_CON */ 125*433d6423SLionel Sambuc #define MST 10 /* I2C_CON */ 126*433d6423SLionel Sambuc #define TRX 9 /* I2C_CON */ 127*433d6423SLionel Sambuc #define XSA 8 /* I2C_CON */ 128*433d6423SLionel Sambuc #define STP 1 /* I2C_CON */ 129*433d6423SLionel Sambuc #define STT 0 /* I2C_CON */ 130*433d6423SLionel Sambuc 131*433d6423SLionel Sambuc #define CLKACTIVITY_S 9 /* I2C_SYSC */ 132*433d6423SLionel Sambuc #define CLKACTIVITY_I 8 /* I2C_SYSC */ 133*433d6423SLionel Sambuc #define SMART_WAKE_UP 4 /* I2C_SYSC */ 134*433d6423SLionel Sambuc #define NO_IDLE_MODE 3 /* I2C_SYSC */ 135*433d6423SLionel Sambuc #define SRST 1 /* I2C_SYSC */ 136*433d6423SLionel Sambuc #define AUTOIDLE 0 /* I2C_SYSC */ 137*433d6423SLionel Sambuc 138*433d6423SLionel Sambuc #define RDONE 0 /* I2C_SYSS */ 139*433d6423SLionel Sambuc 140*433d6423SLionel Sambuc #define RXFIFO_CLR 14 /* I2C_BUF */ 141*433d6423SLionel Sambuc #define TXFIFO_CLR 6 /* I2C_BUF */ 142*433d6423SLionel Sambuc 143*433d6423SLionel Sambuc #define BB 12 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 144*433d6423SLionel Sambuc #define ROVR 11 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 145*433d6423SLionel Sambuc #define AERR 7 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 146*433d6423SLionel Sambuc #define XRDY 4 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 147*433d6423SLionel Sambuc #define RRDY 3 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 148*433d6423SLionel Sambuc #define ARDY 2 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 149*433d6423SLionel Sambuc #define NACK 1 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 150*433d6423SLionel Sambuc #define AL 0 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */ 151*433d6423SLionel Sambuc 152*433d6423SLionel Sambuc #endif /* _OMAP_I2C_REGISTERS_H */ 153