1*eecf6d23SJia-Ju Bai #ifndef _SDR_H 2*eecf6d23SJia-Ju Bai #define _SDR_H 3*eecf6d23SJia-Ju Bai /* ======= General Parameter ======= */ 4*eecf6d23SJia-Ju Bai /* Global configure */ 5*eecf6d23SJia-Ju Bai #define DMA_LENGTH_BY_FRAME 6*eecf6d23SJia-Ju Bai #define MIXER_AC97 7*eecf6d23SJia-Ju Bai 8*eecf6d23SJia-Ju Bai #include <minix/audio_fw.h> 9*eecf6d23SJia-Ju Bai #include <sys/types.h> 10*eecf6d23SJia-Ju Bai #include <sys/ioc_sound.h> 11*eecf6d23SJia-Ju Bai #include <minix/sound.h> 12*eecf6d23SJia-Ju Bai #include <machine/pci.h> 13*eecf6d23SJia-Ju Bai #include <sys/mman.h> 14*eecf6d23SJia-Ju Bai #include "io.h" 15*eecf6d23SJia-Ju Bai 16*eecf6d23SJia-Ju Bai /* Subdevice type */ 17*eecf6d23SJia-Ju Bai #define DAC 0 18*eecf6d23SJia-Ju Bai #define ADC 1 19*eecf6d23SJia-Ju Bai #define MIX 2 20*eecf6d23SJia-Ju Bai 21*eecf6d23SJia-Ju Bai /* PCI number and driver name */ 22*eecf6d23SJia-Ju Bai #define VENDOR_ID 0x1023 23*eecf6d23SJia-Ju Bai #define DEVICE_ID 0x2000 24*eecf6d23SJia-Ju Bai #define DRIVER_NAME "Trident" 25*eecf6d23SJia-Ju Bai 26*eecf6d23SJia-Ju Bai /* Volume option */ 27*eecf6d23SJia-Ju Bai #define GET_VOL 0 28*eecf6d23SJia-Ju Bai #define SET_VOL 1 29*eecf6d23SJia-Ju Bai 30*eecf6d23SJia-Ju Bai /* Interrupt control */ 31*eecf6d23SJia-Ju Bai #define INTR_ENABLE 1 32*eecf6d23SJia-Ju Bai #define INTR_DISABLE 0 33*eecf6d23SJia-Ju Bai 34*eecf6d23SJia-Ju Bai /* Interrupt status */ 35*eecf6d23SJia-Ju Bai #define INTR_STS_DAC 0x0020 36*eecf6d23SJia-Ju Bai #define INTR_STS_ADC 0x0004 37*eecf6d23SJia-Ju Bai 38*eecf6d23SJia-Ju Bai /* ======= Self-defined Parameter ======= */ 39*eecf6d23SJia-Ju Bai #define REG_DMA0 0x00 40*eecf6d23SJia-Ju Bai #define REG_DMA4 0x04 41*eecf6d23SJia-Ju Bai #define REG_DMA6 0x06 42*eecf6d23SJia-Ju Bai #define REG_DMA11 0x0b 43*eecf6d23SJia-Ju Bai #define REG_DMA15 0x0f 44*eecf6d23SJia-Ju Bai #define REG_CODEC_WRITE 0x40 45*eecf6d23SJia-Ju Bai #define REG_CODEC_READ 0x44 46*eecf6d23SJia-Ju Bai #define REG_CODEC_CTRL 0x48 47*eecf6d23SJia-Ju Bai #define REG_GCTRL 0xa0 48*eecf6d23SJia-Ju Bai #define REG_SB_DELTA 0xac 49*eecf6d23SJia-Ju Bai #define REG_SB_BASE 0xc0 50*eecf6d23SJia-Ju Bai #define REG_SB_CTRL 0xc4 51*eecf6d23SJia-Ju Bai #define REG_CHAN_BASE 0xe0 52*eecf6d23SJia-Ju Bai #define REG_INTR_STS 0xb0 53*eecf6d23SJia-Ju Bai 54*eecf6d23SJia-Ju Bai #define REG_START_A 0x80 55*eecf6d23SJia-Ju Bai #define REG_STOP_A 0x84 56*eecf6d23SJia-Ju Bai #define REG_CSPF_A 0x90 57*eecf6d23SJia-Ju Bai #define REG_ADDR_INT_A 0x98 58*eecf6d23SJia-Ju Bai #define REG_INTR_CTRL_A 0xa4 59*eecf6d23SJia-Ju Bai #define REG_START_B 0xb4 60*eecf6d23SJia-Ju Bai #define REG_STOP_B 0xb8 61*eecf6d23SJia-Ju Bai #define REG_CSPF_B 0xbc 62*eecf6d23SJia-Ju Bai #define REG_ADDR_INT_B 0xd8 63*eecf6d23SJia-Ju Bai #define REG_INTR_CTRL_B 0xdc 64*eecf6d23SJia-Ju Bai 65*eecf6d23SJia-Ju Bai #define STS_CODEC_BUSY 0x8000 66*eecf6d23SJia-Ju Bai 67*eecf6d23SJia-Ju Bai #define CMD_FORMAT_BIT16 0x08 68*eecf6d23SJia-Ju Bai #define CMD_FORMAT_SIGN 0x02 69*eecf6d23SJia-Ju Bai #define CMD_FORMAT_STEREO 0x04 70*eecf6d23SJia-Ju Bai 71*eecf6d23SJia-Ju Bai typedef struct channel_info { 72*eecf6d23SJia-Ju Bai u32_t cso, alpha, fms, fmc, ec; 73*eecf6d23SJia-Ju Bai u32_t dma, eso, delta, bufhalf, index; 74*eecf6d23SJia-Ju Bai u32_t rvol, cvol, gvsel, pan, vol, ctrl; 75*eecf6d23SJia-Ju Bai } channel_info; 76*eecf6d23SJia-Ju Bai static channel_info my_chan; 77*eecf6d23SJia-Ju Bai 78*eecf6d23SJia-Ju Bai /* Driver Data Structure */ 79*eecf6d23SJia-Ju Bai typedef struct aud_sub_dev_conf_t { 80*eecf6d23SJia-Ju Bai u32_t stereo; 81*eecf6d23SJia-Ju Bai u16_t sample_rate; 82*eecf6d23SJia-Ju Bai u32_t nr_of_bits; 83*eecf6d23SJia-Ju Bai u32_t sign; 84*eecf6d23SJia-Ju Bai u32_t busy; 85*eecf6d23SJia-Ju Bai u32_t fragment_size; 86*eecf6d23SJia-Ju Bai u8_t format; 87*eecf6d23SJia-Ju Bai } aud_sub_dev_conf_t; 88*eecf6d23SJia-Ju Bai 89*eecf6d23SJia-Ju Bai typedef struct DEV_STRUCT { 90*eecf6d23SJia-Ju Bai char *name; 91*eecf6d23SJia-Ju Bai u16_t vid; 92*eecf6d23SJia-Ju Bai u16_t did; 93*eecf6d23SJia-Ju Bai u32_t devind; 94*eecf6d23SJia-Ju Bai u32_t base[6]; 95*eecf6d23SJia-Ju Bai char irq; 96*eecf6d23SJia-Ju Bai char revision; 97*eecf6d23SJia-Ju Bai u32_t intr_status; 98*eecf6d23SJia-Ju Bai } DEV_STRUCT; 99*eecf6d23SJia-Ju Bai 100*eecf6d23SJia-Ju Bai void dev_mixer_write(u32_t *base, u32_t reg, u32_t val); 101*eecf6d23SJia-Ju Bai u32_t dev_mixer_read(u32_t *base, u32_t reg); 102*eecf6d23SJia-Ju Bai 103*eecf6d23SJia-Ju Bai #endif 104