1 /* Best viewed with tabsize 4 */ 2 3 /* Original: 4 * November 2005 ES1371 driver (Laurens Bronwasser) 5 */ 6 7 /* Ensoniq ES1371 driver 8 * 9 * aka AudioPCI '97 10 * 11 * This is the main file of the ES1371 sound driver. There is no main function 12 * over here, instead the main function is located in the generic dma driver. 13 * All this driver does is implement the interface audio/audio_fw.h. All 14 * functions having the prefix 'drv_' are dictated by audio/audio_fw.h. The 15 * function prototypes you see below define a set of private helper functions. 16 * Control over the AC97 codec is delegated AC97.c. 17 * 18 * October 2007 ES1371 driver (Pieter Hijma), 19 * based on ES1370 driver which is based on the ES1371 driver 20 * by Laurens Bronwasser 21 */ 22 23 #include <machine/pci.h> 24 25 #include <minix/audio_fw.h> 26 #include "es1371.h" 27 #include "AC97.h" 28 #include "sample_rate_converter.h" 29 #include "pci_helper.h" 30 31 32 /* reg(n) will be the device specific addresses */ 33 #define reg(n) dev.base + n 34 35 36 /* prototypes of private functions */ 37 static int detect_hw(void); 38 static int disable_int(int sub_dev); 39 static int set_stereo(u32_t stereo, int sub_dev); 40 static int set_bits(u32_t nr_of_bits, int sub_dev); 41 static int set_sample_rate(u32_t rate, int sub_dev); 42 static int set_sign(u32_t val, int sub_dev); 43 static int get_max_frag_size(u32_t * val, int *len, int sub_dev); 44 static int set_frag_size(u32_t fragment_size, int sub_dev); 45 static int set_int_cnt(int sub_dev); 46 static int free_buf(u32_t *val, int *len, int sub_dev); 47 static int get_samples_in_buf(u32_t *val, int *len, int sub_dev); 48 static int get_set_volume(struct volume_level *level, int *len, int 49 sub_dev, int flag); 50 static int reset(int sub_dev); 51 52 53 DEV_STRUCT dev; 54 aud_sub_dev_conf_t aud_conf[4]; 55 56 57 sub_dev_t sub_dev[4]; 58 special_file_t special_file[4]; 59 drv_t drv; 60 61 62 int drv_init(void) { 63 drv.DriverName = DRIVER_NAME; 64 drv.NrOfSubDevices = 4; 65 drv.NrOfSpecialFiles = 4; 66 67 sub_dev[DAC1_CHAN].readable = 0; 68 sub_dev[DAC1_CHAN].writable = 1; 69 sub_dev[DAC1_CHAN].DmaSize = 64 * 1024; 70 sub_dev[DAC1_CHAN].NrOfDmaFragments = 2; 71 sub_dev[DAC1_CHAN].MinFragmentSize = 1024; 72 sub_dev[DAC1_CHAN].NrOfExtraBuffers = 4; 73 74 sub_dev[ADC1_CHAN].readable = 1; 75 sub_dev[ADC1_CHAN].writable = 0; 76 sub_dev[ADC1_CHAN].DmaSize = 64 * 1024; 77 sub_dev[ADC1_CHAN].NrOfDmaFragments = 2; 78 sub_dev[ADC1_CHAN].MinFragmentSize = 1024; 79 sub_dev[ADC1_CHAN].NrOfExtraBuffers = 4; 80 81 sub_dev[MIXER].writable = 0; 82 sub_dev[MIXER].readable = 0; 83 84 sub_dev[DAC2_CHAN].readable = 0; 85 sub_dev[DAC2_CHAN].writable = 1; 86 sub_dev[DAC2_CHAN].DmaSize = 64 * 1024; 87 sub_dev[DAC2_CHAN].NrOfDmaFragments = 2; 88 sub_dev[DAC2_CHAN].MinFragmentSize = 1024; 89 sub_dev[DAC2_CHAN].NrOfExtraBuffers = 4; 90 91 special_file[0].minor_dev_nr = 0; 92 special_file[0].write_chan = DAC1_CHAN; 93 special_file[0].read_chan = NO_CHANNEL; 94 special_file[0].io_ctl = DAC1_CHAN; 95 96 special_file[1].minor_dev_nr = 1; 97 special_file[1].write_chan = NO_CHANNEL; 98 special_file[1].read_chan = ADC1_CHAN; 99 special_file[1].io_ctl = ADC1_CHAN; 100 101 special_file[2].minor_dev_nr = 2; 102 special_file[2].write_chan = NO_CHANNEL; 103 special_file[2].read_chan = NO_CHANNEL; 104 special_file[2].io_ctl = MIXER; 105 106 special_file[3].minor_dev_nr = 3; 107 special_file[3].write_chan = DAC2_CHAN; 108 special_file[3].read_chan = NO_CHANNEL; 109 special_file[3].io_ctl = DAC2_CHAN; 110 111 return OK; 112 } 113 114 115 int drv_init_hw (void) { 116 u16_t i, j; 117 118 /* First, detect the hardware */ 119 if (detect_hw() != OK) { 120 return EIO; 121 } 122 123 /* PCI command register 124 * enable the SERR# driver, PCI bus mastering and I/O access 125 */ 126 pci_attr_w16 (dev.devind, PCI_CR, SERR_EN|PCI_MASTER|IO_ACCESS); 127 128 /* turn everything off */ 129 pci_outl(reg(CHIP_SEL_CTRL), 0x0UL); 130 131 /* turn off legacy (legacy control is undocumented) */ 132 pci_outl(reg(LEGACY), 0x0UL); 133 pci_outl(reg(LEGACY+4), 0x0UL); 134 135 /* turn off serial interface */ 136 pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x0UL); 137 /*pci_outl(reg(SERIAL_INTERFACE_CTRL), 0x3UL);*/ 138 139 140 /* clear all the memory */ 141 for (i = 0; i < 0x10; ++i) { 142 pci_outb(reg(MEM_PAGE), i); 143 for (j = 0; j < 0x10; j += 4) { 144 pci_outl (reg(MEMORY) + j, 0x0UL); 145 } 146 } 147 148 /* Sample Rate Converter initialization */ 149 if (src_init(&dev) != OK) { 150 return EIO; 151 } 152 if (AC97_init(&dev) != OK) { 153 return EIO; 154 } 155 156 /* initialize variables for each sub_device */ 157 for (i = 0; i < drv.NrOfSubDevices; i++) { 158 if(i != MIXER) { 159 aud_conf[i].busy = 0; 160 aud_conf[i].stereo = DEFAULT_STEREO; 161 aud_conf[i].sample_rate = DEFAULT_RATE; 162 aud_conf[i].nr_of_bits = DEFAULT_NR_OF_BITS; 163 aud_conf[i].sign = DEFAULT_SIGNED; 164 aud_conf[i].fragment_size = 165 sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments; 166 } 167 } 168 return OK; 169 } 170 171 172 static int detect_hw(void) { 173 u32_t device; 174 int devind; 175 u16_t v_id, d_id; 176 177 /* detect_hw tries to find device and get IRQ and base address 178 with a little (much) help from the PCI library. 179 This code is quite device independent and you can copy it. 180 (just make sure to get the bugs out first)*/ 181 182 pci_init(); 183 /* get first device and then search through the list */ 184 device = pci_first_dev(&devind, &v_id, &d_id); 185 while( device > 0 ) { 186 /* if we have a match...break */ 187 if (v_id == VENDOR_ID && d_id == DEVICE_ID) break; 188 device = pci_next_dev(&devind, &v_id, &d_id); 189 } 190 191 /* did we find anything? */ 192 if (v_id != VENDOR_ID || d_id != DEVICE_ID) { 193 return EIO; 194 } 195 196 pci_reserve(devind); 197 198 dev.name = pci_dev_name(v_id, d_id); 199 200 /* get base address of our device, ignore least signif. bit 201 this last bit thing could be device dependent, i don't know */ 202 dev.base = pci_attr_r32(devind, PCI_BAR) & 0xfffffffe; 203 204 /* get IRQ */ 205 dev.irq = pci_attr_r8(devind, PCI_ILR); 206 dev.revision = pci_attr_r8(devind, PCI_REV); 207 dev.d_id = d_id; 208 dev.v_id = v_id; 209 dev.devind = devind; /* pci device identifier */ 210 211 return OK; 212 } 213 214 215 static int reset(int chan) { 216 drv_stop(chan); 217 sub_dev[chan].OutOfData = 1; 218 219 return OK; 220 } 221 222 223 int drv_reset() { 224 return OK; 225 } 226 227 228 int drv_start(int sub_dev, int UNUSED(DmaMode)) { 229 u32_t enable_bit, result = 0; 230 231 /* Write default values to device in case user failed to configure. 232 If user did configure properly, everything is written twice. 233 please raise your hand if you object against to this strategy...*/ 234 result |= set_sample_rate(aud_conf[sub_dev].sample_rate, sub_dev); 235 result |= set_stereo(aud_conf[sub_dev].stereo, sub_dev); 236 result |= set_bits(aud_conf[sub_dev].nr_of_bits, sub_dev); 237 result |= set_sign(aud_conf[sub_dev].sign, sub_dev); 238 239 /* set the interrupt count */ 240 result |= set_int_cnt(sub_dev); 241 242 if (result) { 243 return EIO; 244 } 245 246 /* if device currently paused, resume */ 247 drv_resume(sub_dev); 248 249 switch(sub_dev) { 250 case ADC1_CHAN: enable_bit = ADC1_EN;break; 251 case DAC1_CHAN: enable_bit = DAC1_EN;break; 252 case DAC2_CHAN: enable_bit = DAC2_EN;break; 253 default: return EINVAL; 254 } 255 256 /* enable interrupts from 'sub device' */ 257 drv_reenable_int(sub_dev); 258 259 /* this means play!!! */ 260 pci_outw(reg(CHIP_SEL_CTRL), pci_inw(reg(CHIP_SEL_CTRL)) | enable_bit); 261 262 aud_conf[sub_dev].busy = 1; 263 264 return OK; 265 } 266 267 268 int drv_stop(int sub_dev) 269 { 270 u32_t enable_bit; 271 272 switch(sub_dev) { 273 case ADC1_CHAN: enable_bit = ADC1_EN;break; 274 case DAC1_CHAN: enable_bit = DAC1_EN;break; 275 case DAC2_CHAN: enable_bit = DAC2_EN;break; 276 default: return EINVAL; 277 } 278 279 /* stop the specified channel */ 280 pci_outw(reg(CHIP_SEL_CTRL), 281 pci_inw(reg(CHIP_SEL_CTRL)) & ~enable_bit); 282 aud_conf[sub_dev].busy = 0; 283 disable_int(sub_dev); 284 285 return OK; 286 } 287 288 289 /* all IO-ctl's sent to the upper driver are passed to this function */ 290 int drv_io_ctl(unsigned long request, void * val, int * len, int sub_dev) { 291 292 int status; 293 294 switch(request) { 295 case DSPIORATE: 296 status = set_sample_rate(*((u32_t *) val), sub_dev); break; 297 case DSPIOSTEREO: 298 status = set_stereo(*((u32_t *) val), sub_dev); break; 299 case DSPIOBITS: 300 status = set_bits(*((u32_t *) val), sub_dev); break; 301 case DSPIOSIZE: 302 status = set_frag_size(*((u32_t *) val), sub_dev); break; 303 case DSPIOSIGN: 304 status = set_sign(*((u32_t *) val), sub_dev); break; 305 case DSPIOMAX: 306 status = get_max_frag_size(val, len, sub_dev); break; 307 case DSPIORESET: 308 status = reset(sub_dev); break; 309 case DSPIOFREEBUF: 310 status = free_buf(val, len, sub_dev); break; 311 case DSPIOSAMPLESINBUF: 312 status = get_samples_in_buf(val, len, sub_dev); break; 313 case DSPIOPAUSE: 314 status = drv_pause(sub_dev); break; 315 case DSPIORESUME: 316 status = drv_resume(sub_dev); break; 317 case MIXIOGETVOLUME: 318 status = get_set_volume(val, len, sub_dev, 0); break; 319 case MIXIOSETVOLUME: 320 status = get_set_volume(val, len, sub_dev, 1); break; 321 default: 322 status = EINVAL; break; 323 } 324 325 return status; 326 } 327 328 329 int drv_get_irq(char *irq) { 330 *irq = dev.irq; 331 return OK; 332 } 333 334 335 int drv_get_frag_size(u32_t *frag_size, int sub_dev) { 336 *frag_size = aud_conf[sub_dev].fragment_size; 337 return OK; 338 } 339 340 341 int drv_set_dma(u32_t dma, u32_t length, int chan) { 342 /* dma length in bytes, 343 max is 64k long words for es1371 = 256k bytes */ 344 u32_t page, frame_count_reg, dma_add_reg; 345 346 switch(chan) { 347 case ADC1_CHAN: page = ADC_MEM_PAGE; 348 frame_count_reg = ADC_BUFFER_SIZE; 349 dma_add_reg = ADC_PCI_ADDRESS; 350 break; 351 case DAC1_CHAN: page = DAC_MEM_PAGE; 352 frame_count_reg = DAC1_BUFFER_SIZE; 353 dma_add_reg = DAC1_PCI_ADDRESS; 354 break;; 355 case DAC2_CHAN: page = DAC_MEM_PAGE; 356 frame_count_reg = DAC2_BUFFER_SIZE; 357 dma_add_reg = DAC2_PCI_ADDRESS; 358 break;; 359 default: return EIO; 360 } 361 pci_outb(reg(MEM_PAGE), page); 362 pci_outl(reg(dma_add_reg), dma); 363 364 /* device expects long word count in stead of bytes */ 365 length /= 4; 366 367 /* It seems that register _CURRENT_COUNT is overwritten, but this is 368 * the way to go. The register frame_count_reg is only longword 369 * addressable. 370 * It expects length -1 371 */ 372 pci_outl(reg(frame_count_reg), (u32_t) (length - 1)); 373 374 return OK; 375 } 376 377 378 /* return status of the interrupt summary bit */ 379 int drv_int_sum(void) { 380 return pci_inl(reg(INTERRUPT_STATUS)) & INTR; 381 } 382 383 384 int drv_int(int sub_dev) { 385 u32_t int_status; 386 u32_t bit; 387 388 /* return status of interrupt bit of specified channel*/ 389 switch (sub_dev) { 390 case DAC1_CHAN: bit = DAC1;break; 391 case DAC2_CHAN: bit = DAC2;break; 392 case ADC1_CHAN: bit = ADC;break; 393 default: return EINVAL; 394 } 395 396 int_status = pci_inl(reg(INTERRUPT_STATUS)) & bit; 397 398 return int_status; 399 } 400 401 402 int drv_reenable_int(int chan) { 403 u16_t ser_interface, int_en_bit; 404 405 switch(chan) { 406 case ADC1_CHAN: int_en_bit = R1_INT_EN; break; 407 case DAC1_CHAN: int_en_bit = P1_INTR_EN; break; 408 case DAC2_CHAN: int_en_bit = P2_INTR_EN; break; 409 default: return EINVAL; 410 } 411 412 /* clear and reenable an interrupt */ 413 ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL)); 414 pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit); 415 pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface | int_en_bit); 416 417 return OK; 418 } 419 420 421 int drv_pause(int sub_dev) { 422 u32_t pause_bit; 423 424 disable_int(sub_dev); /* don't send interrupts */ 425 426 switch(sub_dev) { 427 case DAC1_CHAN: pause_bit = P1_PAUSE;break; 428 case DAC2_CHAN: pause_bit = P2_PAUSE;break; 429 default: return EINVAL; 430 } 431 432 /* pause */ 433 pci_outl(reg(SERIAL_INTERFACE_CTRL), 434 pci_inl(reg(SERIAL_INTERFACE_CTRL)) | pause_bit); 435 436 return OK; 437 } 438 439 440 int drv_resume(int sub_dev) { 441 u32_t pause_bit = 0; 442 443 drv_reenable_int(sub_dev); /* enable interrupts */ 444 445 switch(sub_dev) { 446 case DAC1_CHAN: pause_bit = P1_PAUSE;break; 447 case DAC2_CHAN: pause_bit = P2_PAUSE;break; 448 default: return EINVAL; 449 } 450 451 /* clear pause bit */ 452 pci_outl(reg(SERIAL_INTERFACE_CTRL), 453 pci_inl(reg(SERIAL_INTERFACE_CTRL)) & ~pause_bit); 454 455 return OK; 456 } 457 458 459 static int set_bits(u32_t nr_of_bits, int sub_dev) { 460 /* set format bits for specified channel. */ 461 u16_t size_16_bit, ser_interface; 462 463 switch(sub_dev) { 464 case ADC1_CHAN: size_16_bit = R1_S_EB; break; 465 case DAC1_CHAN: size_16_bit = P1_S_EB; break; 466 case DAC2_CHAN: size_16_bit = P2_S_EB; break; 467 default: return EINVAL; 468 } 469 470 ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL)); 471 ser_interface &= ~size_16_bit; 472 switch(nr_of_bits) { 473 case 16: ser_interface |= size_16_bit;break; 474 case 8: break; 475 default: return EINVAL; 476 } 477 pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface); 478 aud_conf[sub_dev].nr_of_bits = nr_of_bits; 479 return OK; 480 } 481 482 483 static int set_stereo(u32_t stereo, int sub_dev) { 484 /* set format bits for specified channel. */ 485 u16_t stereo_bit, ser_interface; 486 487 switch(sub_dev) { 488 case ADC1_CHAN: stereo_bit = R1_S_MB; break; 489 case DAC1_CHAN: stereo_bit = P1_S_MB; break; 490 case DAC2_CHAN: stereo_bit = P2_S_MB; break; 491 default: return EINVAL; 492 } 493 ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL)); 494 ser_interface &= ~stereo_bit; 495 if (stereo) { 496 ser_interface |= stereo_bit; 497 } 498 pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface); 499 aud_conf[sub_dev].stereo = stereo; 500 501 return OK; 502 } 503 504 505 static int set_sign(u32_t UNUSED(val), int UNUSED(sub_dev)) { 506 return OK; 507 } 508 509 510 static int set_frag_size(u32_t fragment_size, int sub_dev_nr) { 511 if (fragment_size > (sub_dev[sub_dev_nr].DmaSize / 512 sub_dev[sub_dev_nr].NrOfDmaFragments) || 513 fragment_size < sub_dev[sub_dev_nr].MinFragmentSize) { 514 return EINVAL; 515 } 516 aud_conf[sub_dev_nr].fragment_size = fragment_size; 517 518 return OK; 519 } 520 521 522 static int set_sample_rate(u32_t rate, int sub_dev) { 523 u32_t src_base_reg; 524 525 if (rate > MAX_RATE || rate < MIN_RATE) { 526 return EINVAL; 527 } 528 /* set the sample rate for the specified channel*/ 529 switch(sub_dev) { 530 case ADC1_CHAN: src_base_reg = SRC_ADC_BASE;break; 531 case DAC1_CHAN: src_base_reg = SRC_SYNTH_BASE;break; 532 case DAC2_CHAN: src_base_reg = SRC_DAC_BASE;break; 533 default: return EINVAL; 534 } 535 src_set_rate(&dev, src_base_reg, rate); 536 aud_conf[sub_dev].sample_rate = rate; 537 return OK; 538 } 539 540 541 static int set_int_cnt(int chan) { 542 /* Write interrupt count for specified channel. 543 After <DspFragmentSize> bytes, an interrupt will be generated */ 544 545 int sample_count; 546 u16_t int_cnt_reg; 547 548 if (aud_conf[chan].fragment_size > 549 (sub_dev[chan].DmaSize / sub_dev[chan].NrOfDmaFragments) 550 || aud_conf[chan].fragment_size < sub_dev[chan].MinFragmentSize) { 551 return EINVAL; 552 } 553 554 switch(chan) { 555 case ADC1_CHAN: int_cnt_reg = ADC_SAMP_CT; break; 556 case DAC1_CHAN: int_cnt_reg = DAC1_SAMP_CT; break; 557 case DAC2_CHAN: int_cnt_reg = DAC2_SAMP_CT; break; 558 default: return EINVAL; 559 } 560 561 sample_count = aud_conf[chan].fragment_size; 562 563 /* adjust sample count according to sample format */ 564 if( aud_conf[chan].stereo == TRUE ) sample_count >>= 1; 565 switch(aud_conf[chan].nr_of_bits) { 566 case 16: sample_count >>= 1;break; 567 case 8: break; 568 default: return EINVAL; 569 } 570 571 /* set the sample count - 1 for the specified channel. */ 572 pci_outw(reg(int_cnt_reg), sample_count - 1); 573 574 return OK; 575 } 576 577 578 static int get_max_frag_size(u32_t * val, int * len, int sub_dev_nr) { 579 *len = sizeof(*val); 580 *val = (sub_dev[sub_dev_nr].DmaSize / 581 sub_dev[sub_dev_nr].NrOfDmaFragments); 582 return OK; 583 } 584 585 586 static int disable_int(int chan) { 587 u16_t ser_interface, int_en_bit; 588 589 switch(chan) { 590 case ADC1_CHAN: int_en_bit = R1_INT_EN; break; 591 case DAC1_CHAN: int_en_bit = P1_INTR_EN; break; 592 case DAC2_CHAN: int_en_bit = P2_INTR_EN; break; 593 default: return EINVAL; 594 } 595 /* clear the interrupt */ 596 ser_interface = pci_inw(reg(SERIAL_INTERFACE_CTRL)); 597 pci_outw(reg(SERIAL_INTERFACE_CTRL), ser_interface & ~int_en_bit); 598 return OK; 599 } 600 601 602 static int get_samples_in_buf (u32_t *samples_in_buf, int *len, int chan) { 603 u16_t samp_ct_reg; 604 u16_t curr_samp_ct_reg; 605 u16_t curr_samp_ct; /* counts back from SAMP_CT till 0 */ 606 607 *len = sizeof(*samples_in_buf); 608 609 switch(chan) { 610 case ADC1_CHAN: 611 curr_samp_ct_reg = ADC_CURR_SAMP_CT; 612 samp_ct_reg = ADC_SAMP_CT; break; 613 case DAC1_CHAN: 614 curr_samp_ct_reg = DAC1_CURR_SAMP_CT; 615 samp_ct_reg = DAC1_SAMP_CT; break; 616 case DAC2_CHAN: 617 curr_samp_ct_reg = DAC2_CURR_SAMP_CT; 618 samp_ct_reg = DAC2_SAMP_CT; break; 619 default: return EINVAL; 620 } 621 622 /* TODO: is this statement useful? */ 623 (void) pci_inw(reg(samp_ct_reg)); 624 curr_samp_ct = pci_inw(reg(curr_samp_ct_reg)); 625 626 *samples_in_buf = (u32_t) (sub_dev[chan].BufLength * 8192) + 627 curr_samp_ct; 628 629 return OK; 630 } 631 632 633 /* returns 1 if there are free buffers */ 634 static int free_buf (u32_t *val, int *len, int sub_dev_nr) { 635 *len = sizeof(*val); 636 if (sub_dev[sub_dev_nr].BufLength == 637 sub_dev[sub_dev_nr].NrOfExtraBuffers) { 638 *val = 0; 639 } 640 else { 641 *val = 1; 642 } 643 return OK; 644 } 645 646 647 static int get_set_volume(struct volume_level *level, int *len, int sub_dev, 648 int flag) { 649 *len = sizeof(struct volume_level); 650 if (sub_dev == MIXER) { 651 return AC97_get_set_volume(level, flag); 652 } 653 else { 654 return EINVAL; 655 } 656 } 657