1*433d6423SLionel Sambuc #ifndef ES1370_H 2*433d6423SLionel Sambuc #define ES1370_H 3*433d6423SLionel Sambuc /* best viewed with tabsize=4 */ 4*433d6423SLionel Sambuc 5*433d6423SLionel Sambuc #include <sys/types.h> 6*433d6423SLionel Sambuc #include <sys/ioc_sound.h> 7*433d6423SLionel Sambuc 8*433d6423SLionel Sambuc 9*433d6423SLionel Sambuc /* set your vendor and device ID's here */ 10*433d6423SLionel Sambuc #define VENDOR_ID 0x1274 11*433d6423SLionel Sambuc #define DEVICE_ID 0x5000 12*433d6423SLionel Sambuc #define DRIVER_NAME "ES1370" 13*433d6423SLionel Sambuc 14*433d6423SLionel Sambuc 15*433d6423SLionel Sambuc /* channels or subdevices */ 16*433d6423SLionel Sambuc #define DAC1_CHAN 0 17*433d6423SLionel Sambuc #define ADC1_CHAN 1 18*433d6423SLionel Sambuc #define MIXER 2 19*433d6423SLionel Sambuc #define DAC2_CHAN 3 20*433d6423SLionel Sambuc 21*433d6423SLionel Sambuc 22*433d6423SLionel Sambuc /* PCI command register defines */ 23*433d6423SLionel Sambuc #define SERR_EN 0x0100 24*433d6423SLionel Sambuc #define PCI_MASTER 0x0004 25*433d6423SLionel Sambuc #define IO_ACCESS 0x0001 26*433d6423SLionel Sambuc 27*433d6423SLionel Sambuc 28*433d6423SLionel Sambuc /* Interrupt/Chip Select Control */ 29*433d6423SLionel Sambuc #define CHIP_SEL_CTRL 0x00 30*433d6423SLionel Sambuc #define FREQ_44K100 0x3000 /* 44.1 Khz */ 31*433d6423SLionel Sambuc #define CDC_EN 0x0002 /* codec enable */ 32*433d6423SLionel Sambuc #define ADC1_EN 0x0010 33*433d6423SLionel Sambuc #define DAC1_EN 0x0040 34*433d6423SLionel Sambuc #define DAC2_EN 0x0020 35*433d6423SLionel Sambuc #define XCTL0 0x0100 36*433d6423SLionel Sambuc #define CCB_INTRM 0x0400 37*433d6423SLionel Sambuc 38*433d6423SLionel Sambuc 39*433d6423SLionel Sambuc /* Interrupt/Chip Select Status */ 40*433d6423SLionel Sambuc #define INTERRUPT_STATUS 0x04 41*433d6423SLionel Sambuc #define ADC 0x0001 42*433d6423SLionel Sambuc #define DAC2 0x0002 43*433d6423SLionel Sambuc #define DAC1 0x0004 44*433d6423SLionel Sambuc #define CSTAT 0x0400 /* == CBUSY || CWRIP */ 45*433d6423SLionel Sambuc #define CWRIP 0x0100 /* == CBUSY || CWRIP */ 46*433d6423SLionel Sambuc #define INTR 0x80000000 47*433d6423SLionel Sambuc 48*433d6423SLionel Sambuc 49*433d6423SLionel Sambuc /* AK4531 address */ 50*433d6423SLionel Sambuc #define CODEC_WRITE_ADDRESS 0x10 51*433d6423SLionel Sambuc 52*433d6423SLionel Sambuc 53*433d6423SLionel Sambuc /* Legacy address */ 54*433d6423SLionel Sambuc #define LEGACY 0x18 55*433d6423SLionel Sambuc 56*433d6423SLionel Sambuc 57*433d6423SLionel Sambuc /* Memory related defines */ 58*433d6423SLionel Sambuc #define MEM_PAGE 0x0c 59*433d6423SLionel Sambuc #define ADC_MEM_PAGE 0x0d 60*433d6423SLionel Sambuc #define DAC_MEM_PAGE 0x0c /* for DAC1 and DAC2 */ 61*433d6423SLionel Sambuc 62*433d6423SLionel Sambuc #define MEMORY 0x30 63*433d6423SLionel Sambuc #define ADC_BUFFER_SIZE 0x34 64*433d6423SLionel Sambuc #define DAC1_BUFFER_SIZE 0x34 65*433d6423SLionel Sambuc #define DAC2_BUFFER_SIZE 0X3c 66*433d6423SLionel Sambuc #define ADC_PCI_ADDRESS 0x30 67*433d6423SLionel Sambuc #define DAC1_PCI_ADDRESS 0x30 68*433d6423SLionel Sambuc #define DAC2_PCI_ADDRESS 0x38 69*433d6423SLionel Sambuc 70*433d6423SLionel Sambuc 71*433d6423SLionel Sambuc /* Serial Interface Control */ 72*433d6423SLionel Sambuc #define SERIAL_INTERFACE_CTRL 0x20 73*433d6423SLionel Sambuc #define P1_S_MB 0x0001 /* DAC1 Stereo/Mono bit */ 74*433d6423SLionel Sambuc #define P1_S_EB 0x0002 /* DAC1 Sixteen/Eight bit */ 75*433d6423SLionel Sambuc #define P2_S_MB 0x0004 /* DAC2 Stereo/Mono bit */ 76*433d6423SLionel Sambuc #define P2_S_EB 0x0008 /* DAC2 Sixteen/Eight bit */ 77*433d6423SLionel Sambuc #define R1_S_MB 0x0010 /* ADC Stereo/Mono bit */ 78*433d6423SLionel Sambuc #define R1_S_EB 0x0020 /* ADC Sixteen/Eight bit */ 79*433d6423SLionel Sambuc #define P1_INTR_EN 0x0100 80*433d6423SLionel Sambuc #define P2_INTR_EN 0x0200 81*433d6423SLionel Sambuc #define R1_INT_EN 0x0400 82*433d6423SLionel Sambuc #define P1_PAUSE 0x0800 83*433d6423SLionel Sambuc #define P2_PAUSE 0x1000 84*433d6423SLionel Sambuc 85*433d6423SLionel Sambuc 86*433d6423SLionel Sambuc #define DAC1_SAMP_CT 0x24 87*433d6423SLionel Sambuc #define DAC1_CURR_SAMP_CT 0x26 88*433d6423SLionel Sambuc #define DAC2_SAMP_CT 0x28 89*433d6423SLionel Sambuc #define DAC2_CURR_SAMP_CT 0x2a 90*433d6423SLionel Sambuc #define ADC_SAMP_CT 0x2c 91*433d6423SLionel Sambuc #define ADC_CURR_SAMP_CT 0x2e 92*433d6423SLionel Sambuc 93*433d6423SLionel Sambuc 94*433d6423SLionel Sambuc typedef struct { 95*433d6423SLionel Sambuc u32_t stereo; 96*433d6423SLionel Sambuc u16_t sample_rate; 97*433d6423SLionel Sambuc u32_t nr_of_bits; 98*433d6423SLionel Sambuc u32_t sign; 99*433d6423SLionel Sambuc u32_t busy; 100*433d6423SLionel Sambuc u32_t fragment_size; 101*433d6423SLionel Sambuc } aud_sub_dev_conf_t; 102*433d6423SLionel Sambuc 103*433d6423SLionel Sambuc /* Some defaults for the aud_sub_dev_conf_t*/ 104*433d6423SLionel Sambuc #define DEFAULT_RATE 44100 /* Sample rate */ 105*433d6423SLionel Sambuc #define DEFAULT_NR_OF_BITS 16 /* Nr. of bits per sample per chan */ 106*433d6423SLionel Sambuc #define DEFAULT_SIGNED 0 /* 0 = unsigned, 1 = signed */ 107*433d6423SLionel Sambuc #define DEFAULT_STEREO 1 /* 0 = mono, 1 = stereo */ 108*433d6423SLionel Sambuc #define MAX_RATE 44100 /* Max sample speed in KHz */ 109*433d6423SLionel Sambuc #define MIN_RATE 4000 /* Min sample speed in KHz */ 110*433d6423SLionel Sambuc 111*433d6423SLionel Sambuc 112*433d6423SLionel Sambuc typedef struct DEVSTRUCT { 113*433d6423SLionel Sambuc char* name; 114*433d6423SLionel Sambuc u16_t v_id; /* vendor id */ 115*433d6423SLionel Sambuc u16_t d_id; /* device id */ 116*433d6423SLionel Sambuc u32_t devind; /* minix pci device id, for 117*433d6423SLionel Sambuc * pci configuration space */ 118*433d6423SLionel Sambuc u32_t base; /* changed to 32 bits */ 119*433d6423SLionel Sambuc char irq; 120*433d6423SLionel Sambuc char revision; /* version of the device */ 121*433d6423SLionel Sambuc } DEV_STRUCT; 122*433d6423SLionel Sambuc 123*433d6423SLionel Sambuc 124*433d6423SLionel Sambuc #endif /* ES1370_H */ 125