xref: /minix3/minix/drivers/audio/cmi8738/cmi8738.h (revision 37e23b1cc7a8bf4f9734839628f9e4ce93b7b5d8)
1*37e23b1cSJia-Ju Bai #ifndef _SDR_H
2*37e23b1cSJia-Ju Bai #define _SDR_H
3*37e23b1cSJia-Ju Bai /* ======= General Parameter ======= */
4*37e23b1cSJia-Ju Bai /* Global configure */
5*37e23b1cSJia-Ju Bai #define DMA_LENGTH_BY_FRAME
6*37e23b1cSJia-Ju Bai #define MIXER_SB16
7*37e23b1cSJia-Ju Bai 
8*37e23b1cSJia-Ju Bai #include <minix/audio_fw.h>
9*37e23b1cSJia-Ju Bai #include <sys/types.h>
10*37e23b1cSJia-Ju Bai #include <sys/ioc_sound.h>
11*37e23b1cSJia-Ju Bai #include <minix/sound.h>
12*37e23b1cSJia-Ju Bai #include <machine/pci.h>
13*37e23b1cSJia-Ju Bai #include <sys/mman.h>
14*37e23b1cSJia-Ju Bai #include "io.h"
15*37e23b1cSJia-Ju Bai 
16*37e23b1cSJia-Ju Bai /* Subdevice type */
17*37e23b1cSJia-Ju Bai #define DAC		0
18*37e23b1cSJia-Ju Bai #define ADC		1
19*37e23b1cSJia-Ju Bai #define MIX		2
20*37e23b1cSJia-Ju Bai 
21*37e23b1cSJia-Ju Bai /* PCI number and driver name */
22*37e23b1cSJia-Ju Bai #define VENDOR_ID		0x13f6
23*37e23b1cSJia-Ju Bai #define DEVICE_ID		0x0111
24*37e23b1cSJia-Ju Bai #define DRIVER_NAME		"CMI8738"
25*37e23b1cSJia-Ju Bai 
26*37e23b1cSJia-Ju Bai /* Volume option */
27*37e23b1cSJia-Ju Bai #define GET_VOL			0
28*37e23b1cSJia-Ju Bai #define SET_VOL			1
29*37e23b1cSJia-Ju Bai 
30*37e23b1cSJia-Ju Bai /* Interrupt control */
31*37e23b1cSJia-Ju Bai #define INTR_ENABLE		1
32*37e23b1cSJia-Ju Bai #define INTR_DISABLE	0
33*37e23b1cSJia-Ju Bai 
34*37e23b1cSJia-Ju Bai /* Interrupt status */
35*37e23b1cSJia-Ju Bai #define INTR_STS_DAC		0x00000001
36*37e23b1cSJia-Ju Bai #define INTR_STS_ADC		0x00000002
37*37e23b1cSJia-Ju Bai 
38*37e23b1cSJia-Ju Bai /* ======= Self-defined Parameter ======= */
39*37e23b1cSJia-Ju Bai #define REG_FUNC_CTRL			0x00
40*37e23b1cSJia-Ju Bai #define REG_FUNC_CTRL1			0x04
41*37e23b1cSJia-Ju Bai #define REG_FORMAT				0x08
42*37e23b1cSJia-Ju Bai #define REG_MISC_CTRL			0x18
43*37e23b1cSJia-Ju Bai #define REG_SB_DATA				0x22
44*37e23b1cSJia-Ju Bai #define REG_SB_ADDR				0x23
45*37e23b1cSJia-Ju Bai #define REG_MIX_INPUT			0x25
46*37e23b1cSJia-Ju Bai #define REG_EXT_MISC			0x90
47*37e23b1cSJia-Ju Bai #define REG_DAC_SAMPLE_COUNT	0x86
48*37e23b1cSJia-Ju Bai #define REG_ADC_SAMPLE_COUNT	0x8e
49*37e23b1cSJia-Ju Bai #define REG_DAC_DMA_ADDR		0x80
50*37e23b1cSJia-Ju Bai #define REG_DAC_DMA_LEN			0x84
51*37e23b1cSJia-Ju Bai #define REG_DAC_CUR_ADDR		0x80
52*37e23b1cSJia-Ju Bai #define REG_ADC_DMA_ADDR		0x88
53*37e23b1cSJia-Ju Bai #define REG_ADC_DMA_LEN			0x8c
54*37e23b1cSJia-Ju Bai #define REG_ADC_CUR_ADDR		0x88
55*37e23b1cSJia-Ju Bai #define REG_EXT_INDEX			0xf0
56*37e23b1cSJia-Ju Bai #define REG_INTR_CTRL			0x0c
57*37e23b1cSJia-Ju Bai #define REG_INTR_STS			0x10
58*37e23b1cSJia-Ju Bai 
59*37e23b1cSJia-Ju Bai #define FMT_BIT16		0x02
60*37e23b1cSJia-Ju Bai #define FMT_STEREO		0x01
61*37e23b1cSJia-Ju Bai 
62*37e23b1cSJia-Ju Bai #define MIXER_ADCL		0x3d
63*37e23b1cSJia-Ju Bai #define MIXER_ADCR		0x3e
64*37e23b1cSJia-Ju Bai #define MIXER_OUT_MUTE	0x3c
65*37e23b1cSJia-Ju Bai 
66*37e23b1cSJia-Ju Bai #define CMD_POWER_DOWN	0x80000000
67*37e23b1cSJia-Ju Bai #define CMD_RESET		0x40000000
68*37e23b1cSJia-Ju Bai #define CMD_ADC_C0		0x00000001
69*37e23b1cSJia-Ju Bai #define CMD_ADC_C1		0x00000002
70*37e23b1cSJia-Ju Bai #define CMD_N4SPK3D		0x04000000
71*37e23b1cSJia-Ju Bai #define CMD_SPDIF_ENA	0x00000200
72*37e23b1cSJia-Ju Bai #define CMD_SPDIF_LOOP	0x00000080
73*37e23b1cSJia-Ju Bai #define CMD_ENA_C0		0x00010000
74*37e23b1cSJia-Ju Bai #define CMD_ENA_C1		0x00020000
75*37e23b1cSJia-Ju Bai #define CMD_INTR_C0		0x00010000
76*37e23b1cSJia-Ju Bai #define CMD_INTR_C1		0x00020000
77*37e23b1cSJia-Ju Bai #define CMD_RESET_C0	0x00040000
78*37e23b1cSJia-Ju Bai #define CMD_RESET_C1	0x00080000
79*37e23b1cSJia-Ju Bai #define CMD_PAUSE_C0	0x00000004
80*37e23b1cSJia-Ju Bai #define CMD_PAUSE_C1	0x00000008
81*37e23b1cSJia-Ju Bai 
82*37e23b1cSJia-Ju Bai #define CMD_INTR_ENABLE	0x00030000
83*37e23b1cSJia-Ju Bai 
84*37e23b1cSJia-Ju Bai static u32_t g_sample_rate[] = {
85*37e23b1cSJia-Ju Bai 	5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000
86*37e23b1cSJia-Ju Bai };
87*37e23b1cSJia-Ju Bai 
88*37e23b1cSJia-Ju Bai /* Driver Data Structure */
89*37e23b1cSJia-Ju Bai typedef struct aud_sub_dev_conf_t {
90*37e23b1cSJia-Ju Bai 	u32_t stereo;
91*37e23b1cSJia-Ju Bai 	u16_t sample_rate;
92*37e23b1cSJia-Ju Bai 	u32_t nr_of_bits;
93*37e23b1cSJia-Ju Bai 	u32_t sign;
94*37e23b1cSJia-Ju Bai 	u32_t busy;
95*37e23b1cSJia-Ju Bai 	u32_t fragment_size;
96*37e23b1cSJia-Ju Bai 	u8_t format;
97*37e23b1cSJia-Ju Bai } aud_sub_dev_conf_t;
98*37e23b1cSJia-Ju Bai 
99*37e23b1cSJia-Ju Bai typedef struct DEV_STRUCT {
100*37e23b1cSJia-Ju Bai 	char *name;
101*37e23b1cSJia-Ju Bai 	u16_t vid;
102*37e23b1cSJia-Ju Bai 	u16_t did;
103*37e23b1cSJia-Ju Bai 	u32_t devind;
104*37e23b1cSJia-Ju Bai 	u32_t base[6];
105*37e23b1cSJia-Ju Bai 	char irq;
106*37e23b1cSJia-Ju Bai 	char revision;
107*37e23b1cSJia-Ju Bai 	u32_t intr_status;
108*37e23b1cSJia-Ju Bai } DEV_STRUCT;
109*37e23b1cSJia-Ju Bai 
110*37e23b1cSJia-Ju Bai void dev_mixer_write(u32_t *base, u32_t reg, u32_t val);
111*37e23b1cSJia-Ju Bai u32_t dev_mixer_read(u32_t *base, u32_t reg);
112*37e23b1cSJia-Ju Bai 
113*37e23b1cSJia-Ju Bai #endif
114