xref: /minix3/minix/drivers/audio/als4000/als4000.h (revision 86fd71a2c95f57d1ee45ed621a52209d481544b4)
1*86fd71a2SJia-Ju Bai #ifndef _SDR_H
2*86fd71a2SJia-Ju Bai #define _SDR_H
3*86fd71a2SJia-Ju Bai /* ======= General Parameter ======= */
4*86fd71a2SJia-Ju Bai /* Global configure */
5*86fd71a2SJia-Ju Bai #define MIXER_SB16
6*86fd71a2SJia-Ju Bai 
7*86fd71a2SJia-Ju Bai #include <minix/audio_fw.h>
8*86fd71a2SJia-Ju Bai #include <sys/types.h>
9*86fd71a2SJia-Ju Bai #include <sys/ioc_sound.h>
10*86fd71a2SJia-Ju Bai #include <minix/sound.h>
11*86fd71a2SJia-Ju Bai #include <machine/pci.h>
12*86fd71a2SJia-Ju Bai #include <sys/mman.h>
13*86fd71a2SJia-Ju Bai #include "io.h"
14*86fd71a2SJia-Ju Bai 
15*86fd71a2SJia-Ju Bai /* Subdevice type */
16*86fd71a2SJia-Ju Bai #define DAC		0
17*86fd71a2SJia-Ju Bai #define ADC		1
18*86fd71a2SJia-Ju Bai #define MIX		2
19*86fd71a2SJia-Ju Bai 
20*86fd71a2SJia-Ju Bai /* PCI number and driver name */
21*86fd71a2SJia-Ju Bai #define VENDOR_ID		0x4005
22*86fd71a2SJia-Ju Bai #define DEVICE_ID		0x4000
23*86fd71a2SJia-Ju Bai #define DRIVER_NAME		"ALS4000"
24*86fd71a2SJia-Ju Bai 
25*86fd71a2SJia-Ju Bai /* Volume option */
26*86fd71a2SJia-Ju Bai #define GET_VOL			0
27*86fd71a2SJia-Ju Bai #define SET_VOL			1
28*86fd71a2SJia-Ju Bai 
29*86fd71a2SJia-Ju Bai /* Interrupt control */
30*86fd71a2SJia-Ju Bai #define INTR_ENABLE		1
31*86fd71a2SJia-Ju Bai #define INTR_DISABLE	0
32*86fd71a2SJia-Ju Bai 
33*86fd71a2SJia-Ju Bai /* Interrupt status */
34*86fd71a2SJia-Ju Bai #define INTR_STS_DAC		0x80
35*86fd71a2SJia-Ju Bai #define INTR_STS_ADC		0x40
36*86fd71a2SJia-Ju Bai 
37*86fd71a2SJia-Ju Bai /* ======= Self-defined Parameter ======= */
38*86fd71a2SJia-Ju Bai #define REG_MIXER_ADDR		0x04
39*86fd71a2SJia-Ju Bai #define REG_MIXER_DATA		0x05
40*86fd71a2SJia-Ju Bai #define REG_GCR_DATA		0x08
41*86fd71a2SJia-Ju Bai #define REG_GCR_INDEX		0x0c
42*86fd71a2SJia-Ju Bai #define REG_INTR_STS		0x0e
43*86fd71a2SJia-Ju Bai #define REG_INTR_CTRL		0x8c
44*86fd71a2SJia-Ju Bai #define REG_DMA_EM_CTRL		0x99
45*86fd71a2SJia-Ju Bai 
46*86fd71a2SJia-Ju Bai #define REG_DAC_DMA_ADDR	0x91
47*86fd71a2SJia-Ju Bai #define REG_DAC_DMA_LEN		0x92
48*86fd71a2SJia-Ju Bai #define REG_DAC_CUR_ADDR	0xa0
49*86fd71a2SJia-Ju Bai #define REG_ADC_DMA_ADDR	0xa2
50*86fd71a2SJia-Ju Bai #define REG_ADC_DMA_LEN		0xa3
51*86fd71a2SJia-Ju Bai #define REG_ADC_CUR_ADDR	0xa4
52*86fd71a2SJia-Ju Bai 
53*86fd71a2SJia-Ju Bai #define REG_SB_CONFIG		0x00
54*86fd71a2SJia-Ju Bai #define REG_SB_RESET		0x06
55*86fd71a2SJia-Ju Bai #define REG_SB_READ			0x0a
56*86fd71a2SJia-Ju Bai #define REG_SB_CMD			0x0c
57*86fd71a2SJia-Ju Bai #define REG_SB_DATA			0x0e
58*86fd71a2SJia-Ju Bai #define REG_SB_BASE			0x10
59*86fd71a2SJia-Ju Bai #define REG_SB_FIFO_LEN_LO	0x1c
60*86fd71a2SJia-Ju Bai #define REG_SB_FIFO_LEN_HI	0x1d
61*86fd71a2SJia-Ju Bai #define REG_SB_FIFO_CTRL	0x1e
62*86fd71a2SJia-Ju Bai #define REG_SB_DMA_SETUP	0x81
63*86fd71a2SJia-Ju Bai #define REG_SB_IRQ_STATUS	0x82
64*86fd71a2SJia-Ju Bai #define REG_SB_CTRL			0xc0
65*86fd71a2SJia-Ju Bai 
66*86fd71a2SJia-Ju Bai #define CMD_MIXER_WRITE_ENABLE	0x80
67*86fd71a2SJia-Ju Bai #define CMD_SOUND_ON			0xd1
68*86fd71a2SJia-Ju Bai #define CMD_INTR_ENABLE			0x28000
69*86fd71a2SJia-Ju Bai #define CMD_SAMPLE_RATE_OUT		0x41
70*86fd71a2SJia-Ju Bai #define CMD_SIGN_MONO			0x10
71*86fd71a2SJia-Ju Bai #define CMD_SIGN_STEREO			0x30
72*86fd71a2SJia-Ju Bai #define CMD_UNSIGN_MONO			0x00
73*86fd71a2SJia-Ju Bai #define CMD_UNSIGN_STEREO		0x20
74*86fd71a2SJia-Ju Bai #define CMD_BIT16_AI			0xb6
75*86fd71a2SJia-Ju Bai #define CMD_BIT16_DMA_OFF		0xd5
76*86fd71a2SJia-Ju Bai #define CMD_BIT16_DMA_ON		0xd6
77*86fd71a2SJia-Ju Bai #define CMD_BIT8_AI				0xc6
78*86fd71a2SJia-Ju Bai #define CMD_BIT8_DMA_OFF		0xd0
79*86fd71a2SJia-Ju Bai #define CMD_BIT8_DMA_ON			0xd4
80*86fd71a2SJia-Ju Bai 
81*86fd71a2SJia-Ju Bai #define CMD_REC_WIDTH8			0x04
82*86fd71a2SJia-Ju Bai #define CMD_REC_STEREO			0x20
83*86fd71a2SJia-Ju Bai #define CMD_REC_SIGN			0x10
84*86fd71a2SJia-Ju Bai 
85*86fd71a2SJia-Ju Bai static u32_t g_sample_rate[] = {
86*86fd71a2SJia-Ju Bai 	5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000
87*86fd71a2SJia-Ju Bai };
88*86fd71a2SJia-Ju Bai 
89*86fd71a2SJia-Ju Bai /* Driver Data Structure */
90*86fd71a2SJia-Ju Bai typedef struct aud_sub_dev_conf_t {
91*86fd71a2SJia-Ju Bai 	u32_t stereo;
92*86fd71a2SJia-Ju Bai 	u16_t sample_rate;
93*86fd71a2SJia-Ju Bai 	u32_t nr_of_bits;
94*86fd71a2SJia-Ju Bai 	u32_t sign;
95*86fd71a2SJia-Ju Bai 	u32_t busy;
96*86fd71a2SJia-Ju Bai 	u32_t fragment_size;
97*86fd71a2SJia-Ju Bai 	u8_t format;
98*86fd71a2SJia-Ju Bai } aud_sub_dev_conf_t;
99*86fd71a2SJia-Ju Bai 
100*86fd71a2SJia-Ju Bai typedef struct DEV_STRUCT {
101*86fd71a2SJia-Ju Bai 	char *name;
102*86fd71a2SJia-Ju Bai 	u16_t vid;
103*86fd71a2SJia-Ju Bai 	u16_t did;
104*86fd71a2SJia-Ju Bai 	u32_t devind;
105*86fd71a2SJia-Ju Bai 	u32_t base[6];
106*86fd71a2SJia-Ju Bai 	char irq;
107*86fd71a2SJia-Ju Bai 	char revision;
108*86fd71a2SJia-Ju Bai 	u32_t intr_status;
109*86fd71a2SJia-Ju Bai } DEV_STRUCT;
110*86fd71a2SJia-Ju Bai 
111*86fd71a2SJia-Ju Bai void dev_mixer_write(u32_t *base, u32_t reg, u32_t val);
112*86fd71a2SJia-Ju Bai u32_t dev_mixer_read(u32_t *base, u32_t reg);
113*86fd71a2SJia-Ju Bai 
114*86fd71a2SJia-Ju Bai #endif
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