1*0a6a1f1dSLionel Sambuc; RUN: llc -march=cpp -o - %s | FileCheck %s 2*0a6a1f1dSLionel Sambuc 3*0a6a1f1dSLionel Sambucdefine void @test_atomicrmw(i32* %addr, i32 %inc) { 4*0a6a1f1dSLionel Sambuc %inst0 = atomicrmw xchg i32* %addr, i32 %inc seq_cst 5*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThread 6*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst0"); 7*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 8*0a6a1f1dSLionel Sambuc 9*0a6a1f1dSLionel Sambuc %inst1 = atomicrmw add i32* %addr, i32 %inc seq_cst 10*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThread 11*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst1"); 12*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 13*0a6a1f1dSLionel Sambuc 14*0a6a1f1dSLionel Sambuc %inst2 = atomicrmw volatile sub i32* %addr, i32 %inc singlethread monotonic 15*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Monotonic, SingleThread 16*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst2"); 17*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(true); 18*0a6a1f1dSLionel Sambuc 19*0a6a1f1dSLionel Sambuc %inst3 = atomicrmw and i32* %addr, i32 %inc acq_rel 20*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, AcquireRelease, CrossThread 21*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst3"); 22*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 23*0a6a1f1dSLionel Sambuc 24*0a6a1f1dSLionel Sambuc %inst4 = atomicrmw nand i32* %addr, i32 %inc release 25*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.*}}, Release, CrossThread 26*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst4"); 27*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 28*0a6a1f1dSLionel Sambuc 29*0a6a1f1dSLionel Sambuc %inst5 = atomicrmw volatile or i32* %addr, i32 %inc singlethread seq_cst 30*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThread 31*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst5"); 32*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(true); 33*0a6a1f1dSLionel Sambuc 34*0a6a1f1dSLionel Sambuc %inst6 = atomicrmw xor i32* %addr, i32 %inc release 35*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.*}}, Release, CrossThread 36*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst6"); 37*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 38*0a6a1f1dSLionel Sambuc 39*0a6a1f1dSLionel Sambuc %inst7 = atomicrmw volatile max i32* %addr, i32 %inc singlethread monotonic 40*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.*}}, Monotonic, SingleThread 41*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst7"); 42*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(true); 43*0a6a1f1dSLionel Sambuc 44*0a6a1f1dSLionel Sambuc %inst8 = atomicrmw min i32* %addr, i32 %inc acquire 45*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.*}}, Acquire, CrossThread 46*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst8"); 47*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 48*0a6a1f1dSLionel Sambuc 49*0a6a1f1dSLionel Sambuc %inst9 = atomicrmw volatile umax i32* %addr, i32 %inc monotonic 50*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Monotonic, CrossThread 51*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst9"); 52*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(true); 53*0a6a1f1dSLionel Sambuc 54*0a6a1f1dSLionel Sambuc %inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release 55*0a6a1f1dSLionel Sambuc ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread 56*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst10"); 57*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 58*0a6a1f1dSLionel Sambuc 59*0a6a1f1dSLionel Sambuc 60*0a6a1f1dSLionel Sambuc ret void 61*0a6a1f1dSLionel Sambuc} 62*0a6a1f1dSLionel Sambuc 63*0a6a1f1dSLionel Sambucdefine void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) { 64*0a6a1f1dSLionel Sambuc %inst0 = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic 65*0a6a1f1dSLionel Sambuc ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread 66*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst0"); 67*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 68*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setWeak(false); 69*0a6a1f1dSLionel Sambuc 70*0a6a1f1dSLionel Sambuc %inst1 = cmpxchg volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire 71*0a6a1f1dSLionel Sambuc ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread 72*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst1"); 73*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(true); 74*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setWeak(false); 75*0a6a1f1dSLionel Sambuc 76*0a6a1f1dSLionel Sambuc %inst2 = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic 77*0a6a1f1dSLionel Sambuc ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread 78*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst2"); 79*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(false); 80*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setWeak(true); 81*0a6a1f1dSLionel Sambuc 82*0a6a1f1dSLionel Sambuc %inst3 = cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire 83*0a6a1f1dSLionel Sambuc ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread 84*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setName("inst3"); 85*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setVolatile(true); 86*0a6a1f1dSLionel Sambuc ; CHECK: [[INST]]->setWeak(true); 87*0a6a1f1dSLionel Sambuc 88*0a6a1f1dSLionel Sambuc ret void 89*0a6a1f1dSLionel Sambuc} 90