1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstrInfo.h" 15 #include "X86.h" 16 #include "X86InstrBuilder.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/CodeGen/LiveVariables.h" 22 #include "llvm/CodeGen/MachineConstantPool.h" 23 #include "llvm/CodeGen/MachineDominators.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/StackMaps.h" 28 #include "llvm/IR/DerivedTypes.h" 29 #include "llvm/IR/Function.h" 30 #include "llvm/IR/LLVMContext.h" 31 #include "llvm/MC/MCAsmInfo.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/MC/MCInst.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include "llvm/Target/TargetOptions.h" 39 #include <limits> 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "x86-instr-info" 44 45 #define GET_INSTRINFO_CTOR_DTOR 46 #include "X86GenInstrInfo.inc" 47 48 static cl::opt<bool> 49 NoFusing("disable-spill-fusing", 50 cl::desc("Disable fusing of spill code into instructions")); 51 static cl::opt<bool> 52 PrintFailedFusing("print-failed-fuse-candidates", 53 cl::desc("Print instructions that the allocator wants to" 54 " fuse, but the X86 backend currently can't"), 55 cl::Hidden); 56 static cl::opt<bool> 57 ReMatPICStubLoad("remat-pic-stub-load", 58 cl::desc("Re-materialize load from stub in PIC mode"), 59 cl::init(false), cl::Hidden); 60 61 enum { 62 // Select which memory operand is being unfolded. 63 // (stored in bits 0 - 3) 64 TB_INDEX_0 = 0, 65 TB_INDEX_1 = 1, 66 TB_INDEX_2 = 2, 67 TB_INDEX_3 = 3, 68 TB_INDEX_4 = 4, 69 TB_INDEX_MASK = 0xf, 70 71 // Do not insert the reverse map (MemOp -> RegOp) into the table. 72 // This may be needed because there is a many -> one mapping. 73 TB_NO_REVERSE = 1 << 4, 74 75 // Do not insert the forward map (RegOp -> MemOp) into the table. 76 // This is needed for Native Client, which prohibits branch 77 // instructions from using a memory operand. 78 TB_NO_FORWARD = 1 << 5, 79 80 TB_FOLDED_LOAD = 1 << 6, 81 TB_FOLDED_STORE = 1 << 7, 82 83 // Minimum alignment required for load/store. 84 // Used for RegOp->MemOp conversion. 85 // (stored in bits 8 - 15) 86 TB_ALIGN_SHIFT = 8, 87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT, 91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 92 }; 93 94 struct X86OpTblEntry { 95 uint16_t RegOp; 96 uint16_t MemOp; 97 uint16_t Flags; 98 }; 99 100 // Pin the vtable to this file. 101 void X86InstrInfo::anchor() {} 102 103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI) 104 : X86GenInstrInfo( 105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32), 106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)), 107 Subtarget(STI), RI(STI) { 108 109 static const X86OpTblEntry OpTbl2Addr[] = { 110 { X86::ADC32ri, X86::ADC32mi, 0 }, 111 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 112 { X86::ADC32rr, X86::ADC32mr, 0 }, 113 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 114 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 115 { X86::ADC64rr, X86::ADC64mr, 0 }, 116 { X86::ADD16ri, X86::ADD16mi, 0 }, 117 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 120 { X86::ADD16rr, X86::ADD16mr, 0 }, 121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 122 { X86::ADD32ri, X86::ADD32mi, 0 }, 123 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 126 { X86::ADD32rr, X86::ADD32mr, 0 }, 127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 128 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 129 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 132 { X86::ADD64rr, X86::ADD64mr, 0 }, 133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 134 { X86::ADD8ri, X86::ADD8mi, 0 }, 135 { X86::ADD8rr, X86::ADD8mr, 0 }, 136 { X86::AND16ri, X86::AND16mi, 0 }, 137 { X86::AND16ri8, X86::AND16mi8, 0 }, 138 { X86::AND16rr, X86::AND16mr, 0 }, 139 { X86::AND32ri, X86::AND32mi, 0 }, 140 { X86::AND32ri8, X86::AND32mi8, 0 }, 141 { X86::AND32rr, X86::AND32mr, 0 }, 142 { X86::AND64ri32, X86::AND64mi32, 0 }, 143 { X86::AND64ri8, X86::AND64mi8, 0 }, 144 { X86::AND64rr, X86::AND64mr, 0 }, 145 { X86::AND8ri, X86::AND8mi, 0 }, 146 { X86::AND8rr, X86::AND8mr, 0 }, 147 { X86::DEC16r, X86::DEC16m, 0 }, 148 { X86::DEC32r, X86::DEC32m, 0 }, 149 { X86::DEC64r, X86::DEC64m, 0 }, 150 { X86::DEC8r, X86::DEC8m, 0 }, 151 { X86::INC16r, X86::INC16m, 0 }, 152 { X86::INC32r, X86::INC32m, 0 }, 153 { X86::INC64r, X86::INC64m, 0 }, 154 { X86::INC8r, X86::INC8m, 0 }, 155 { X86::NEG16r, X86::NEG16m, 0 }, 156 { X86::NEG32r, X86::NEG32m, 0 }, 157 { X86::NEG64r, X86::NEG64m, 0 }, 158 { X86::NEG8r, X86::NEG8m, 0 }, 159 { X86::NOT16r, X86::NOT16m, 0 }, 160 { X86::NOT32r, X86::NOT32m, 0 }, 161 { X86::NOT64r, X86::NOT64m, 0 }, 162 { X86::NOT8r, X86::NOT8m, 0 }, 163 { X86::OR16ri, X86::OR16mi, 0 }, 164 { X86::OR16ri8, X86::OR16mi8, 0 }, 165 { X86::OR16rr, X86::OR16mr, 0 }, 166 { X86::OR32ri, X86::OR32mi, 0 }, 167 { X86::OR32ri8, X86::OR32mi8, 0 }, 168 { X86::OR32rr, X86::OR32mr, 0 }, 169 { X86::OR64ri32, X86::OR64mi32, 0 }, 170 { X86::OR64ri8, X86::OR64mi8, 0 }, 171 { X86::OR64rr, X86::OR64mr, 0 }, 172 { X86::OR8ri, X86::OR8mi, 0 }, 173 { X86::OR8rr, X86::OR8mr, 0 }, 174 { X86::ROL16r1, X86::ROL16m1, 0 }, 175 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 176 { X86::ROL16ri, X86::ROL16mi, 0 }, 177 { X86::ROL32r1, X86::ROL32m1, 0 }, 178 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 179 { X86::ROL32ri, X86::ROL32mi, 0 }, 180 { X86::ROL64r1, X86::ROL64m1, 0 }, 181 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 182 { X86::ROL64ri, X86::ROL64mi, 0 }, 183 { X86::ROL8r1, X86::ROL8m1, 0 }, 184 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 185 { X86::ROL8ri, X86::ROL8mi, 0 }, 186 { X86::ROR16r1, X86::ROR16m1, 0 }, 187 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 188 { X86::ROR16ri, X86::ROR16mi, 0 }, 189 { X86::ROR32r1, X86::ROR32m1, 0 }, 190 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 191 { X86::ROR32ri, X86::ROR32mi, 0 }, 192 { X86::ROR64r1, X86::ROR64m1, 0 }, 193 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 194 { X86::ROR64ri, X86::ROR64mi, 0 }, 195 { X86::ROR8r1, X86::ROR8m1, 0 }, 196 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 197 { X86::ROR8ri, X86::ROR8mi, 0 }, 198 { X86::SAR16r1, X86::SAR16m1, 0 }, 199 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 200 { X86::SAR16ri, X86::SAR16mi, 0 }, 201 { X86::SAR32r1, X86::SAR32m1, 0 }, 202 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 203 { X86::SAR32ri, X86::SAR32mi, 0 }, 204 { X86::SAR64r1, X86::SAR64m1, 0 }, 205 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 206 { X86::SAR64ri, X86::SAR64mi, 0 }, 207 { X86::SAR8r1, X86::SAR8m1, 0 }, 208 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 209 { X86::SAR8ri, X86::SAR8mi, 0 }, 210 { X86::SBB32ri, X86::SBB32mi, 0 }, 211 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 212 { X86::SBB32rr, X86::SBB32mr, 0 }, 213 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 214 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 215 { X86::SBB64rr, X86::SBB64mr, 0 }, 216 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 217 { X86::SHL16ri, X86::SHL16mi, 0 }, 218 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 219 { X86::SHL32ri, X86::SHL32mi, 0 }, 220 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 221 { X86::SHL64ri, X86::SHL64mi, 0 }, 222 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 223 { X86::SHL8ri, X86::SHL8mi, 0 }, 224 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 225 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 226 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 227 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 228 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 229 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 230 { X86::SHR16r1, X86::SHR16m1, 0 }, 231 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 232 { X86::SHR16ri, X86::SHR16mi, 0 }, 233 { X86::SHR32r1, X86::SHR32m1, 0 }, 234 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 235 { X86::SHR32ri, X86::SHR32mi, 0 }, 236 { X86::SHR64r1, X86::SHR64m1, 0 }, 237 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 238 { X86::SHR64ri, X86::SHR64mi, 0 }, 239 { X86::SHR8r1, X86::SHR8m1, 0 }, 240 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 241 { X86::SHR8ri, X86::SHR8mi, 0 }, 242 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 243 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 244 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 245 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 246 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 247 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 248 { X86::SUB16ri, X86::SUB16mi, 0 }, 249 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 250 { X86::SUB16rr, X86::SUB16mr, 0 }, 251 { X86::SUB32ri, X86::SUB32mi, 0 }, 252 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 253 { X86::SUB32rr, X86::SUB32mr, 0 }, 254 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 255 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 256 { X86::SUB64rr, X86::SUB64mr, 0 }, 257 { X86::SUB8ri, X86::SUB8mi, 0 }, 258 { X86::SUB8rr, X86::SUB8mr, 0 }, 259 { X86::XOR16ri, X86::XOR16mi, 0 }, 260 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 261 { X86::XOR16rr, X86::XOR16mr, 0 }, 262 { X86::XOR32ri, X86::XOR32mi, 0 }, 263 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 264 { X86::XOR32rr, X86::XOR32mr, 0 }, 265 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 266 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 267 { X86::XOR64rr, X86::XOR64mr, 0 }, 268 { X86::XOR8ri, X86::XOR8mi, 0 }, 269 { X86::XOR8rr, X86::XOR8mr, 0 } 270 }; 271 272 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 273 unsigned RegOp = OpTbl2Addr[i].RegOp; 274 unsigned MemOp = OpTbl2Addr[i].MemOp; 275 unsigned Flags = OpTbl2Addr[i].Flags; 276 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 277 RegOp, MemOp, 278 // Index 0, folded load and store, no alignment requirement. 279 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 280 } 281 282 static const X86OpTblEntry OpTbl0[] = { 283 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 284 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 285 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 286 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 287 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 288 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 289 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 290 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 291 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 292 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 293 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 294 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 295 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 296 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 297 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 298 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 299 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 300 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 301 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 302 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 303 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE }, 304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 336 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 337 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 338 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 339 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 340 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 341 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 342 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 343 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 344 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 345 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 346 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 347 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 348 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 349 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 350 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 351 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 352 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 353 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 354 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 355 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 356 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 357 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 358 // AVX 128-bit versions of foldable instructions 359 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, 360 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 361 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 362 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 365 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 366 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 367 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 368 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 369 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 370 // AVX 256-bit foldable instructions 371 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 372 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 373 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 374 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 376 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }, 377 // AVX-512 foldable instructions 378 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE }, 379 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 380 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 381 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 382 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 }, 383 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE }, 384 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE }, 385 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE }, 386 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE }, 387 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE }, 388 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE }, 389 // AVX-512 foldable instructions (256-bit versions) 390 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 391 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 392 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 393 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 }, 394 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE }, 395 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE }, 396 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE }, 397 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE }, 398 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE }, 399 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE }, 400 // AVX-512 foldable instructions (128-bit versions) 401 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 402 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 403 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 404 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 405 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE }, 406 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE }, 407 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE }, 408 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE }, 409 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE }, 410 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE } 411 }; 412 413 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 414 unsigned RegOp = OpTbl0[i].RegOp; 415 unsigned MemOp = OpTbl0[i].MemOp; 416 unsigned Flags = OpTbl0[i].Flags; 417 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 418 RegOp, MemOp, TB_INDEX_0 | Flags); 419 } 420 421 static const X86OpTblEntry OpTbl1[] = { 422 { X86::CMP16rr, X86::CMP16rm, 0 }, 423 { X86::CMP32rr, X86::CMP32rm, 0 }, 424 { X86::CMP64rr, X86::CMP64rm, 0 }, 425 { X86::CMP8rr, X86::CMP8rm, 0 }, 426 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 427 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 428 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 429 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 430 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 431 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 432 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 433 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 434 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 435 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 436 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 437 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 438 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 439 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 440 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 441 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 442 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 443 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 444 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 445 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 446 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 447 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 448 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 }, 449 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 }, 450 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 }, 451 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 }, 452 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 453 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 454 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 455 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 456 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 457 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 458 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 459 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 460 { X86::MOV16rr, X86::MOV16rm, 0 }, 461 { X86::MOV32rr, X86::MOV32rm, 0 }, 462 { X86::MOV64rr, X86::MOV64rm, 0 }, 463 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 464 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 465 { X86::MOV8rr, X86::MOV8rm, 0 }, 466 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 467 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 468 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 469 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 470 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 471 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 472 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 473 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 474 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 475 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 476 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 477 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 478 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 479 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 480 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 481 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 482 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 483 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 484 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 485 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 486 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 487 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 488 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 489 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 490 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 491 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 492 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 493 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 494 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 495 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 496 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 497 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 498 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 499 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 500 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 501 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 502 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 503 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 504 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 505 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 506 { X86::TEST16rr, X86::TEST16rm, 0 }, 507 { X86::TEST32rr, X86::TEST32rm, 0 }, 508 { X86::TEST64rr, X86::TEST64rm, 0 }, 509 { X86::TEST8rr, X86::TEST8rm, 0 }, 510 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 511 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 512 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 513 // AVX 128-bit versions of foldable instructions 514 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 515 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 516 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 517 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 518 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 519 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 520 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 521 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 522 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 523 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 524 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 525 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 526 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 527 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 528 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 529 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 530 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 }, 531 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 }, 532 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 }, 533 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 }, 534 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 }, 535 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, 536 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 537 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 538 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 539 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 540 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 541 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 542 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 543 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 544 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 545 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 546 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 }, 547 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 548 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 549 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 550 { X86::VPABSBrr128, X86::VPABSBrm128, 0 }, 551 { X86::VPABSDrr128, X86::VPABSDrm128, 0 }, 552 { X86::VPABSWrr128, X86::VPABSWrm128, 0 }, 553 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 }, 554 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 }, 555 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 }, 556 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 }, 557 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 }, 558 { X86::VRCPPSr, X86::VRCPPSm, 0 }, 559 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 }, 560 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, 561 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 }, 562 { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, 563 { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, 564 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 565 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 566 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 567 568 // AVX 256-bit foldable instructions 569 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 }, 570 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 }, 571 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 }, 572 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 }, 573 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 }, 574 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 }, 575 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 576 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 577 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 578 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 579 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 580 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 }, 581 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 }, 582 { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, 583 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 }, 584 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, 585 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, 586 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, 587 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 588 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 589 590 // AVX2 foldable instructions 591 { X86::VPABSBrr256, X86::VPABSBrm256, 0 }, 592 { X86::VPABSDrr256, X86::VPABSDrm256, 0 }, 593 { X86::VPABSWrr256, X86::VPABSWrm256, 0 }, 594 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 }, 595 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 }, 596 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 }, 597 598 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions 599 { X86::BEXTR32rr, X86::BEXTR32rm, 0 }, 600 { X86::BEXTR64rr, X86::BEXTR64rm, 0 }, 601 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 }, 602 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 }, 603 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 }, 604 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 }, 605 { X86::BLCI32rr, X86::BLCI32rm, 0 }, 606 { X86::BLCI64rr, X86::BLCI64rm, 0 }, 607 { X86::BLCIC32rr, X86::BLCIC32rm, 0 }, 608 { X86::BLCIC64rr, X86::BLCIC64rm, 0 }, 609 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 }, 610 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 }, 611 { X86::BLCS32rr, X86::BLCS32rm, 0 }, 612 { X86::BLCS64rr, X86::BLCS64rm, 0 }, 613 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 }, 614 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 }, 615 { X86::BLSI32rr, X86::BLSI32rm, 0 }, 616 { X86::BLSI64rr, X86::BLSI64rm, 0 }, 617 { X86::BLSIC32rr, X86::BLSIC32rm, 0 }, 618 { X86::BLSIC64rr, X86::BLSIC64rm, 0 }, 619 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 }, 620 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 }, 621 { X86::BLSR32rr, X86::BLSR32rm, 0 }, 622 { X86::BLSR64rr, X86::BLSR64rm, 0 }, 623 { X86::BZHI32rr, X86::BZHI32rm, 0 }, 624 { X86::BZHI64rr, X86::BZHI64rm, 0 }, 625 { X86::LZCNT16rr, X86::LZCNT16rm, 0 }, 626 { X86::LZCNT32rr, X86::LZCNT32rm, 0 }, 627 { X86::LZCNT64rr, X86::LZCNT64rm, 0 }, 628 { X86::POPCNT16rr, X86::POPCNT16rm, 0 }, 629 { X86::POPCNT32rr, X86::POPCNT32rm, 0 }, 630 { X86::POPCNT64rr, X86::POPCNT64rm, 0 }, 631 { X86::RORX32ri, X86::RORX32mi, 0 }, 632 { X86::RORX64ri, X86::RORX64mi, 0 }, 633 { X86::SARX32rr, X86::SARX32rm, 0 }, 634 { X86::SARX64rr, X86::SARX64rm, 0 }, 635 { X86::SHRX32rr, X86::SHRX32rm, 0 }, 636 { X86::SHRX64rr, X86::SHRX64rm, 0 }, 637 { X86::SHLX32rr, X86::SHLX32rm, 0 }, 638 { X86::SHLX64rr, X86::SHLX64rm, 0 }, 639 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 }, 640 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 }, 641 { X86::TZCNT16rr, X86::TZCNT16rm, 0 }, 642 { X86::TZCNT32rr, X86::TZCNT32rm, 0 }, 643 { X86::TZCNT64rr, X86::TZCNT64rm, 0 }, 644 { X86::TZMSK32rr, X86::TZMSK32rm, 0 }, 645 { X86::TZMSK64rr, X86::TZMSK64rm, 0 }, 646 647 // AVX-512 foldable instructions 648 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 }, 649 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 }, 650 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 }, 651 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 }, 652 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 }, 653 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 }, 654 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 }, 655 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 }, 656 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 }, 657 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 }, 658 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 }, 659 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 }, 660 { X86::VPABSDZrr, X86::VPABSDZrm, 0 }, 661 { X86::VPABSQZrr, X86::VPABSQZrm, 0 }, 662 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE }, 663 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE }, 664 // AVX-512 foldable instructions (256-bit versions) 665 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 }, 666 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 }, 667 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 }, 668 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 }, 669 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 }, 670 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 }, 671 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 }, 672 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 }, 673 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 }, 674 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 }, 675 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE }, 676 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE }, 677 // AVX-512 foldable instructions (256-bit versions) 678 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 }, 679 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 }, 680 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 }, 681 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 }, 682 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 }, 683 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 }, 684 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 }, 685 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 }, 686 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 }, 687 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 }, 688 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE }, 689 690 // AES foldable instructions 691 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 }, 692 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 }, 693 { X86::VAESIMCrr, X86::VAESIMCrm, TB_ALIGN_16 }, 694 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 } 695 }; 696 697 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 698 unsigned RegOp = OpTbl1[i].RegOp; 699 unsigned MemOp = OpTbl1[i].MemOp; 700 unsigned Flags = OpTbl1[i].Flags; 701 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 702 RegOp, MemOp, 703 // Index 1, folded load 704 Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 705 } 706 707 static const X86OpTblEntry OpTbl2[] = { 708 { X86::ADC32rr, X86::ADC32rm, 0 }, 709 { X86::ADC64rr, X86::ADC64rm, 0 }, 710 { X86::ADD16rr, X86::ADD16rm, 0 }, 711 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 712 { X86::ADD32rr, X86::ADD32rm, 0 }, 713 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 714 { X86::ADD64rr, X86::ADD64rm, 0 }, 715 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 716 { X86::ADD8rr, X86::ADD8rm, 0 }, 717 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 718 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 719 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 720 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 721 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 722 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 723 { X86::AND16rr, X86::AND16rm, 0 }, 724 { X86::AND32rr, X86::AND32rm, 0 }, 725 { X86::AND64rr, X86::AND64rm, 0 }, 726 { X86::AND8rr, X86::AND8rm, 0 }, 727 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 728 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 729 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 730 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 731 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 732 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 733 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 734 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 735 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 736 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 737 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 738 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 739 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 740 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 741 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 742 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 743 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 744 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 745 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 746 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 747 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 748 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 749 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 750 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 751 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 752 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 753 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 754 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 755 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 756 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 757 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 758 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 759 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 760 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 761 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 762 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 763 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 764 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 765 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 766 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 767 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 768 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 769 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 770 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 771 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 772 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 773 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 774 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 775 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 776 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 777 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 778 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 779 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 780 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 781 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 782 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 783 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 784 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 785 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 786 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 787 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 788 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 789 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 790 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 791 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 792 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 793 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 794 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 795 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 796 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 797 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 798 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 799 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 800 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 801 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 802 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 803 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 804 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 805 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 806 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 807 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 808 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 809 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 810 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 811 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 812 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 813 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 814 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 815 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 816 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 817 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 818 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 819 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 820 { X86::MINSDrr, X86::MINSDrm, 0 }, 821 { X86::MINSSrr, X86::MINSSrm, 0 }, 822 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 823 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 824 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 825 { X86::MULSDrr, X86::MULSDrm, 0 }, 826 { X86::MULSSrr, X86::MULSSrm, 0 }, 827 { X86::OR16rr, X86::OR16rm, 0 }, 828 { X86::OR32rr, X86::OR32rm, 0 }, 829 { X86::OR64rr, X86::OR64rm, 0 }, 830 { X86::OR8rr, X86::OR8rm, 0 }, 831 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 832 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 833 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 834 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 835 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 836 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 837 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 838 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 839 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 840 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 841 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 842 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 843 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 844 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 845 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 846 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 847 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 848 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 849 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 850 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 851 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 852 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 853 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 854 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 855 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 856 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 857 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 858 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 859 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 860 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 861 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 862 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 863 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 864 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 865 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 866 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 867 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 868 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 869 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 870 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 871 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 872 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 }, 873 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 }, 874 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 }, 875 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 }, 876 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, 877 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 }, 878 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 }, 879 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 }, 880 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 881 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 882 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 883 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 884 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 885 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 886 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 887 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 888 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 889 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 890 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 891 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 892 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 893 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 894 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 895 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 896 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 897 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 898 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 899 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 900 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 901 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 902 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 903 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 904 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 905 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 906 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 907 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 908 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 909 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 910 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 911 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 912 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 913 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 914 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 915 { X86::SBB32rr, X86::SBB32rm, 0 }, 916 { X86::SBB64rr, X86::SBB64rm, 0 }, 917 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 918 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 919 { X86::SUB16rr, X86::SUB16rm, 0 }, 920 { X86::SUB32rr, X86::SUB32rm, 0 }, 921 { X86::SUB64rr, X86::SUB64rm, 0 }, 922 { X86::SUB8rr, X86::SUB8rm, 0 }, 923 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 924 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 925 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 926 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 927 // FIXME: TEST*rr -> swapped operand of TEST*mr. 928 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 929 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 930 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 931 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 932 { X86::XOR16rr, X86::XOR16rm, 0 }, 933 { X86::XOR32rr, X86::XOR32rm, 0 }, 934 { X86::XOR64rr, X86::XOR64rm, 0 }, 935 { X86::XOR8rr, X86::XOR8rm, 0 }, 936 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 937 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 938 // AVX 128-bit versions of foldable instructions 939 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 940 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 941 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 942 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 943 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 944 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 945 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 946 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 947 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 948 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 949 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 950 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 951 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 952 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 953 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 954 { X86::VADDPDrr, X86::VADDPDrm, 0 }, 955 { X86::VADDPSrr, X86::VADDPSrm, 0 }, 956 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 957 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 958 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 }, 959 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 }, 960 { X86::VANDNPDrr, X86::VANDNPDrm, 0 }, 961 { X86::VANDNPSrr, X86::VANDNPSrm, 0 }, 962 { X86::VANDPDrr, X86::VANDPDrm, 0 }, 963 { X86::VANDPSrr, X86::VANDPSrm, 0 }, 964 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 }, 965 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 }, 966 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 }, 967 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 }, 968 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 }, 969 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 }, 970 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 971 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 972 { X86::VDIVPDrr, X86::VDIVPDrm, 0 }, 973 { X86::VDIVPSrr, X86::VDIVPSrm, 0 }, 974 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 975 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 976 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 977 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 978 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 979 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 980 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 981 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 982 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 983 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 984 { X86::VHADDPDrr, X86::VHADDPDrm, 0 }, 985 { X86::VHADDPSrr, X86::VHADDPSrm, 0 }, 986 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 }, 987 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 }, 988 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 989 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 990 { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, 991 { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, 992 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 993 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 994 { X86::VMINPDrr, X86::VMINPDrm, 0 }, 995 { X86::VMINPSrr, X86::VMINPSrm, 0 }, 996 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 997 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 998 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, 999 { X86::VMULPDrr, X86::VMULPDrm, 0 }, 1000 { X86::VMULPSrr, X86::VMULPSrm, 0 }, 1001 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 1002 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 1003 { X86::VORPDrr, X86::VORPDrm, 0 }, 1004 { X86::VORPSrr, X86::VORPSrm, 0 }, 1005 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 }, 1006 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 }, 1007 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 }, 1008 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 }, 1009 { X86::VPADDBrr, X86::VPADDBrm, 0 }, 1010 { X86::VPADDDrr, X86::VPADDDrm, 0 }, 1011 { X86::VPADDQrr, X86::VPADDQrm, 0 }, 1012 { X86::VPADDSBrr, X86::VPADDSBrm, 0 }, 1013 { X86::VPADDSWrr, X86::VPADDSWrm, 0 }, 1014 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 }, 1015 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 }, 1016 { X86::VPADDWrr, X86::VPADDWrm, 0 }, 1017 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 }, 1018 { X86::VPANDNrr, X86::VPANDNrm, 0 }, 1019 { X86::VPANDrr, X86::VPANDrm, 0 }, 1020 { X86::VPAVGBrr, X86::VPAVGBrm, 0 }, 1021 { X86::VPAVGWrr, X86::VPAVGWrm, 0 }, 1022 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 }, 1023 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 }, 1024 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 }, 1025 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 }, 1026 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 }, 1027 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 }, 1028 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 }, 1029 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 }, 1030 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 }, 1031 { X86::VPHADDDrr, X86::VPHADDDrm, 0 }, 1032 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 }, 1033 { X86::VPHADDWrr, X86::VPHADDWrm, 0 }, 1034 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 }, 1035 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 }, 1036 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, 1037 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, 1038 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, 1039 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 }, 1040 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 }, 1041 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, 1042 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 }, 1043 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 }, 1044 { X86::VPMINSWrr, X86::VPMINSWrm, 0 }, 1045 { X86::VPMINUBrr, X86::VPMINUBrm, 0 }, 1046 { X86::VPMINSBrr, X86::VPMINSBrm, 0 }, 1047 { X86::VPMINSDrr, X86::VPMINSDrm, 0 }, 1048 { X86::VPMINUDrr, X86::VPMINUDrm, 0 }, 1049 { X86::VPMINUWrr, X86::VPMINUWrm, 0 }, 1050 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, 1051 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 }, 1052 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 }, 1053 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 }, 1054 { X86::VPMULDQrr, X86::VPMULDQrm, 0 }, 1055 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 }, 1056 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 }, 1057 { X86::VPMULHWrr, X86::VPMULHWrm, 0 }, 1058 { X86::VPMULLDrr, X86::VPMULLDrm, 0 }, 1059 { X86::VPMULLWrr, X86::VPMULLWrm, 0 }, 1060 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 }, 1061 { X86::VPORrr, X86::VPORrm, 0 }, 1062 { X86::VPSADBWrr, X86::VPSADBWrm, 0 }, 1063 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 }, 1064 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 }, 1065 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 }, 1066 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 }, 1067 { X86::VPSLLDrr, X86::VPSLLDrm, 0 }, 1068 { X86::VPSLLQrr, X86::VPSLLQrm, 0 }, 1069 { X86::VPSLLWrr, X86::VPSLLWrm, 0 }, 1070 { X86::VPSRADrr, X86::VPSRADrm, 0 }, 1071 { X86::VPSRAWrr, X86::VPSRAWrm, 0 }, 1072 { X86::VPSRLDrr, X86::VPSRLDrm, 0 }, 1073 { X86::VPSRLQrr, X86::VPSRLQrm, 0 }, 1074 { X86::VPSRLWrr, X86::VPSRLWrm, 0 }, 1075 { X86::VPSUBBrr, X86::VPSUBBrm, 0 }, 1076 { X86::VPSUBDrr, X86::VPSUBDrm, 0 }, 1077 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 }, 1078 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 }, 1079 { X86::VPSUBWrr, X86::VPSUBWrm, 0 }, 1080 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 }, 1081 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 }, 1082 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 }, 1083 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 }, 1084 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 }, 1085 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 }, 1086 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 }, 1087 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 }, 1088 { X86::VPXORrr, X86::VPXORrm, 0 }, 1089 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 }, 1090 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 }, 1091 { X86::VSUBPDrr, X86::VSUBPDrm, 0 }, 1092 { X86::VSUBPSrr, X86::VSUBPSrm, 0 }, 1093 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 1094 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 1095 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 }, 1096 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 }, 1097 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 }, 1098 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 }, 1099 { X86::VXORPDrr, X86::VXORPDrm, 0 }, 1100 { X86::VXORPSrr, X86::VXORPSrm, 0 }, 1101 // AVX 256-bit foldable instructions 1102 { X86::VADDPDYrr, X86::VADDPDYrm, 0 }, 1103 { X86::VADDPSYrr, X86::VADDPSYrm, 0 }, 1104 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 }, 1105 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 }, 1106 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 }, 1107 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 }, 1108 { X86::VANDPDYrr, X86::VANDPDYrm, 0 }, 1109 { X86::VANDPSYrr, X86::VANDPSYrm, 0 }, 1110 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 }, 1111 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 }, 1112 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 }, 1113 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 }, 1114 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 }, 1115 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 }, 1116 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 }, 1117 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 }, 1118 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 }, 1119 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 }, 1120 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 }, 1121 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, 1122 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, 1123 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, 1124 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, 1125 { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, 1126 { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, 1127 { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, 1128 { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, 1129 { X86::VORPDYrr, X86::VORPDYrm, 0 }, 1130 { X86::VORPSYrr, X86::VORPSYrm, 0 }, 1131 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 }, 1132 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 }, 1133 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 }, 1134 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 }, 1135 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 }, 1136 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 }, 1137 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 }, 1138 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 }, 1139 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 }, 1140 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 }, 1141 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 }, 1142 { X86::VXORPDYrr, X86::VXORPDYrm, 0 }, 1143 { X86::VXORPSYrr, X86::VXORPSYrm, 0 }, 1144 // AVX2 foldable instructions 1145 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 }, 1146 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 }, 1147 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 }, 1148 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 }, 1149 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 }, 1150 { X86::VPADDBYrr, X86::VPADDBYrm, 0 }, 1151 { X86::VPADDDYrr, X86::VPADDDYrm, 0 }, 1152 { X86::VPADDQYrr, X86::VPADDQYrm, 0 }, 1153 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 }, 1154 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 }, 1155 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 }, 1156 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 }, 1157 { X86::VPADDWYrr, X86::VPADDWYrm, 0 }, 1158 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 }, 1159 { X86::VPANDNYrr, X86::VPANDNYrm, 0 }, 1160 { X86::VPANDYrr, X86::VPANDYrm, 0 }, 1161 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 }, 1162 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 }, 1163 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 }, 1164 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 }, 1165 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 }, 1166 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 }, 1167 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 }, 1168 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 }, 1169 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 }, 1170 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 }, 1171 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 }, 1172 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 }, 1173 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 }, 1174 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 }, 1175 { X86::VPERMDYrr, X86::VPERMDYrm, 0 }, 1176 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 }, 1177 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 }, 1178 { X86::VPERMQYri, X86::VPERMQYmi, 0 }, 1179 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 }, 1180 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 }, 1181 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 }, 1182 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 }, 1183 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 }, 1184 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 }, 1185 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 }, 1186 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 }, 1187 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 }, 1188 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 }, 1189 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 }, 1190 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 }, 1191 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 }, 1192 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 }, 1193 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 }, 1194 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 }, 1195 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 }, 1196 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 }, 1197 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 }, 1198 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 }, 1199 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 }, 1200 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 }, 1201 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 }, 1202 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 }, 1203 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 }, 1204 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 }, 1205 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 }, 1206 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 }, 1207 { X86::VPORYrr, X86::VPORYrm, 0 }, 1208 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 }, 1209 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 }, 1210 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 }, 1211 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 }, 1212 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 }, 1213 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 }, 1214 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 }, 1215 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 }, 1216 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 }, 1217 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 }, 1218 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 }, 1219 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 }, 1220 { X86::VPSRADYrr, X86::VPSRADYrm, 0 }, 1221 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 }, 1222 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 }, 1223 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 }, 1224 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 }, 1225 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 }, 1226 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 }, 1227 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 }, 1228 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 }, 1229 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 }, 1230 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 }, 1231 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 }, 1232 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 }, 1233 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 }, 1234 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 }, 1235 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 }, 1236 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 }, 1237 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 }, 1238 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 }, 1239 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 }, 1240 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 }, 1241 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 }, 1242 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 }, 1243 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 }, 1244 { X86::VPXORYrr, X86::VPXORYrm, 0 }, 1245 // FIXME: add AVX 256-bit foldable instructions 1246 1247 // FMA4 foldable patterns 1248 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 }, 1249 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 }, 1250 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 }, 1251 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 }, 1252 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 }, 1253 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 }, 1254 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 }, 1255 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 }, 1256 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 }, 1257 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 }, 1258 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 }, 1259 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 }, 1260 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 }, 1261 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 }, 1262 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 }, 1263 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 }, 1264 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 }, 1265 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 }, 1266 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 }, 1267 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 }, 1268 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 }, 1269 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 }, 1270 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 }, 1271 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 }, 1272 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 }, 1273 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 }, 1274 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 }, 1275 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 }, 1276 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 }, 1277 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 }, 1278 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 }, 1279 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 }, 1280 1281 // BMI/BMI2 foldable instructions 1282 { X86::ANDN32rr, X86::ANDN32rm, 0 }, 1283 { X86::ANDN64rr, X86::ANDN64rm, 0 }, 1284 { X86::MULX32rr, X86::MULX32rm, 0 }, 1285 { X86::MULX64rr, X86::MULX64rm, 0 }, 1286 { X86::PDEP32rr, X86::PDEP32rm, 0 }, 1287 { X86::PDEP64rr, X86::PDEP64rm, 0 }, 1288 { X86::PEXT32rr, X86::PEXT32rm, 0 }, 1289 { X86::PEXT64rr, X86::PEXT64rm, 0 }, 1290 1291 // AVX-512 foldable instructions 1292 { X86::VADDPSZrr, X86::VADDPSZrm, 0 }, 1293 { X86::VADDPDZrr, X86::VADDPDZrm, 0 }, 1294 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 }, 1295 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 }, 1296 { X86::VMULPSZrr, X86::VMULPSZrm, 0 }, 1297 { X86::VMULPDZrr, X86::VMULPDZrm, 0 }, 1298 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 }, 1299 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 }, 1300 { X86::VMINPSZrr, X86::VMINPSZrm, 0 }, 1301 { X86::VMINPDZrr, X86::VMINPDZrm, 0 }, 1302 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 }, 1303 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 }, 1304 { X86::VPADDDZrr, X86::VPADDDZrm, 0 }, 1305 { X86::VPADDQZrr, X86::VPADDQZrm, 0 }, 1306 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 }, 1307 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 }, 1308 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 }, 1309 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 }, 1310 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 }, 1311 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 }, 1312 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 }, 1313 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 }, 1314 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 }, 1315 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 }, 1316 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 }, 1317 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 }, 1318 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 }, 1319 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 }, 1320 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 }, 1321 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 }, 1322 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 }, 1323 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 }, 1324 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 }, 1325 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 }, 1326 { X86::VALIGNQrri, X86::VALIGNQrmi, 0 }, 1327 { X86::VALIGNDrri, X86::VALIGNDrmi, 0 }, 1328 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 }, 1329 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE }, 1330 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE }, 1331 1332 // AVX-512{F,VL} foldable instructions 1333 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE }, 1334 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE }, 1335 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE }, 1336 1337 // AVX-512{F,VL} foldable instructions 1338 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 }, 1339 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 }, 1340 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 }, 1341 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 }, 1342 1343 // AES foldable instructions 1344 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 }, 1345 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 }, 1346 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 }, 1347 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 }, 1348 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, TB_ALIGN_16 }, 1349 { X86::VAESDECrr, X86::VAESDECrm, TB_ALIGN_16 }, 1350 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, TB_ALIGN_16 }, 1351 { X86::VAESENCrr, X86::VAESENCrm, TB_ALIGN_16 }, 1352 1353 // SHA foldable instructions 1354 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 }, 1355 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 }, 1356 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 }, 1357 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 }, 1358 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 }, 1359 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 }, 1360 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }, 1361 }; 1362 1363 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1364 unsigned RegOp = OpTbl2[i].RegOp; 1365 unsigned MemOp = OpTbl2[i].MemOp; 1366 unsigned Flags = OpTbl2[i].Flags; 1367 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1368 RegOp, MemOp, 1369 // Index 2, folded load 1370 Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1371 } 1372 1373 static const X86OpTblEntry OpTbl3[] = { 1374 // FMA foldable instructions 1375 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE }, 1376 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE }, 1377 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE }, 1378 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE }, 1379 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE }, 1380 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE }, 1381 1382 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE }, 1383 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE }, 1384 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE }, 1385 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE }, 1386 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE }, 1387 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE }, 1388 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE }, 1389 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE }, 1390 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE }, 1391 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE }, 1392 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE }, 1393 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE }, 1394 1395 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE }, 1396 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE }, 1397 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE }, 1398 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE }, 1399 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE }, 1400 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE }, 1401 1402 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE }, 1403 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE }, 1404 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE }, 1405 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE }, 1406 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE }, 1407 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE }, 1408 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE }, 1409 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE }, 1410 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE }, 1411 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE }, 1412 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE }, 1413 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE }, 1414 1415 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE }, 1416 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE }, 1417 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE }, 1418 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE }, 1419 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE }, 1420 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE }, 1421 1422 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE }, 1423 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE }, 1424 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE }, 1425 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE }, 1426 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE }, 1427 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE }, 1428 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE }, 1429 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE }, 1430 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE }, 1431 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE }, 1432 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE }, 1433 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE }, 1434 1435 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE }, 1436 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE }, 1437 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE }, 1438 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE }, 1439 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE }, 1440 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE }, 1441 1442 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE }, 1443 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE }, 1444 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE }, 1445 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE }, 1446 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE }, 1447 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE }, 1448 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE }, 1449 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE }, 1450 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE }, 1451 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE }, 1452 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE }, 1453 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE }, 1454 1455 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE }, 1456 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE }, 1457 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE }, 1458 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE }, 1459 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE }, 1460 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE }, 1461 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE }, 1462 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE }, 1463 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE }, 1464 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE }, 1465 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE }, 1466 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE }, 1467 1468 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE }, 1469 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE }, 1470 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE }, 1471 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE }, 1472 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE }, 1473 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE }, 1474 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE }, 1475 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE }, 1476 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE }, 1477 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE }, 1478 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE }, 1479 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE }, 1480 1481 // FMA4 foldable patterns 1482 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 }, 1483 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 }, 1484 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 }, 1485 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 }, 1486 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 }, 1487 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 }, 1488 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 }, 1489 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 }, 1490 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 }, 1491 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 }, 1492 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 }, 1493 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 }, 1494 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 }, 1495 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 }, 1496 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 }, 1497 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 }, 1498 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 }, 1499 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 }, 1500 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 }, 1501 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 }, 1502 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 }, 1503 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 }, 1504 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 }, 1505 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 }, 1506 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 }, 1507 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 }, 1508 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 }, 1509 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 }, 1510 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 }, 1511 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 }, 1512 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 }, 1513 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 }, 1514 // AVX-512 VPERMI instructions with 3 source operands. 1515 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 }, 1516 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 }, 1517 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 }, 1518 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 }, 1519 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 }, 1520 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 }, 1521 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 }, 1522 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }, 1523 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE }, 1524 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE }, 1525 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE }, 1526 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE }, 1527 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE }, 1528 // AVX-512 arithmetic instructions 1529 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 }, 1530 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 }, 1531 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 }, 1532 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 }, 1533 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 }, 1534 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 }, 1535 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 }, 1536 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 }, 1537 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 }, 1538 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 }, 1539 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 }, 1540 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 }, 1541 // AVX-512{F,VL} arithmetic instructions 256-bit 1542 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 }, 1543 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 }, 1544 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 }, 1545 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 }, 1546 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 }, 1547 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 }, 1548 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 }, 1549 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 }, 1550 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 }, 1551 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 }, 1552 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 }, 1553 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 }, 1554 // AVX-512{F,VL} arithmetic instructions 128-bit 1555 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 }, 1556 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 }, 1557 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 }, 1558 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 }, 1559 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 }, 1560 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 }, 1561 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 }, 1562 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 }, 1563 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 }, 1564 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 }, 1565 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 }, 1566 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 } 1567 }; 1568 1569 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1570 unsigned RegOp = OpTbl3[i].RegOp; 1571 unsigned MemOp = OpTbl3[i].MemOp; 1572 unsigned Flags = OpTbl3[i].Flags; 1573 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1574 RegOp, MemOp, 1575 // Index 3, folded load 1576 Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1577 } 1578 1579 static const X86OpTblEntry OpTbl4[] = { 1580 // AVX-512 foldable instructions 1581 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 }, 1582 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 }, 1583 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 }, 1584 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 }, 1585 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 }, 1586 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 }, 1587 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 }, 1588 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 }, 1589 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 }, 1590 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 }, 1591 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 }, 1592 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 }, 1593 // AVX-512{F,VL} foldable instructions 256-bit 1594 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 }, 1595 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 }, 1596 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 }, 1597 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 }, 1598 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 }, 1599 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 }, 1600 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 }, 1601 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 }, 1602 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 }, 1603 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 }, 1604 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 }, 1605 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 }, 1606 // AVX-512{F,VL} foldable instructions 128-bit 1607 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 }, 1608 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 }, 1609 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 }, 1610 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 }, 1611 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 }, 1612 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 }, 1613 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 }, 1614 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 }, 1615 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 }, 1616 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 }, 1617 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 }, 1618 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 } 1619 }; 1620 1621 for (unsigned i = 0, e = array_lengthof(OpTbl4); i != e; ++i) { 1622 unsigned RegOp = OpTbl4[i].RegOp; 1623 unsigned MemOp = OpTbl4[i].MemOp; 1624 unsigned Flags = OpTbl4[i].Flags; 1625 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable, 1626 RegOp, MemOp, 1627 // Index 4, folded load 1628 Flags | TB_INDEX_4 | TB_FOLDED_LOAD); 1629 } 1630 } 1631 1632 void 1633 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1634 MemOp2RegOpTableType &M2RTable, 1635 unsigned RegOp, unsigned MemOp, unsigned Flags) { 1636 if ((Flags & TB_NO_FORWARD) == 0) { 1637 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1638 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1639 } 1640 if ((Flags & TB_NO_REVERSE) == 0) { 1641 assert(!M2RTable.count(MemOp) && 1642 "Duplicated entries in unfolding maps?"); 1643 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1644 } 1645 } 1646 1647 bool 1648 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1649 unsigned &SrcReg, unsigned &DstReg, 1650 unsigned &SubIdx) const { 1651 switch (MI.getOpcode()) { 1652 default: break; 1653 case X86::MOVSX16rr8: 1654 case X86::MOVZX16rr8: 1655 case X86::MOVSX32rr8: 1656 case X86::MOVZX32rr8: 1657 case X86::MOVSX64rr8: 1658 if (!Subtarget.is64Bit()) 1659 // It's not always legal to reference the low 8-bit of the larger 1660 // register in 32-bit mode. 1661 return false; 1662 case X86::MOVSX32rr16: 1663 case X86::MOVZX32rr16: 1664 case X86::MOVSX64rr16: 1665 case X86::MOVSX64rr32: { 1666 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1667 // Be conservative. 1668 return false; 1669 SrcReg = MI.getOperand(1).getReg(); 1670 DstReg = MI.getOperand(0).getReg(); 1671 switch (MI.getOpcode()) { 1672 default: llvm_unreachable("Unreachable!"); 1673 case X86::MOVSX16rr8: 1674 case X86::MOVZX16rr8: 1675 case X86::MOVSX32rr8: 1676 case X86::MOVZX32rr8: 1677 case X86::MOVSX64rr8: 1678 SubIdx = X86::sub_8bit; 1679 break; 1680 case X86::MOVSX32rr16: 1681 case X86::MOVZX32rr16: 1682 case X86::MOVSX64rr16: 1683 SubIdx = X86::sub_16bit; 1684 break; 1685 case X86::MOVSX64rr32: 1686 SubIdx = X86::sub_32bit; 1687 break; 1688 } 1689 return true; 1690 } 1691 } 1692 return false; 1693 } 1694 1695 /// isFrameOperand - Return true and the FrameIndex if the specified 1696 /// operand and follow operands form a reference to the stack frame. 1697 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1698 int &FrameIndex) const { 1699 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() && 1700 MI->getOperand(Op+X86::AddrScaleAmt).isImm() && 1701 MI->getOperand(Op+X86::AddrIndexReg).isReg() && 1702 MI->getOperand(Op+X86::AddrDisp).isImm() && 1703 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 && 1704 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 && 1705 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) { 1706 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex(); 1707 return true; 1708 } 1709 return false; 1710 } 1711 1712 static bool isFrameLoadOpcode(int Opcode) { 1713 switch (Opcode) { 1714 default: 1715 return false; 1716 case X86::MOV8rm: 1717 case X86::MOV16rm: 1718 case X86::MOV32rm: 1719 case X86::MOV64rm: 1720 case X86::LD_Fp64m: 1721 case X86::MOVSSrm: 1722 case X86::MOVSDrm: 1723 case X86::MOVAPSrm: 1724 case X86::MOVAPDrm: 1725 case X86::MOVDQArm: 1726 case X86::VMOVSSrm: 1727 case X86::VMOVSDrm: 1728 case X86::VMOVAPSrm: 1729 case X86::VMOVAPDrm: 1730 case X86::VMOVDQArm: 1731 case X86::VMOVUPSYrm: 1732 case X86::VMOVAPSYrm: 1733 case X86::VMOVUPDYrm: 1734 case X86::VMOVAPDYrm: 1735 case X86::VMOVDQUYrm: 1736 case X86::VMOVDQAYrm: 1737 case X86::MMX_MOVD64rm: 1738 case X86::MMX_MOVQ64rm: 1739 case X86::VMOVAPSZrm: 1740 case X86::VMOVUPSZrm: 1741 return true; 1742 } 1743 } 1744 1745 static bool isFrameStoreOpcode(int Opcode) { 1746 switch (Opcode) { 1747 default: break; 1748 case X86::MOV8mr: 1749 case X86::MOV16mr: 1750 case X86::MOV32mr: 1751 case X86::MOV64mr: 1752 case X86::ST_FpP64m: 1753 case X86::MOVSSmr: 1754 case X86::MOVSDmr: 1755 case X86::MOVAPSmr: 1756 case X86::MOVAPDmr: 1757 case X86::MOVDQAmr: 1758 case X86::VMOVSSmr: 1759 case X86::VMOVSDmr: 1760 case X86::VMOVAPSmr: 1761 case X86::VMOVAPDmr: 1762 case X86::VMOVDQAmr: 1763 case X86::VMOVUPSYmr: 1764 case X86::VMOVAPSYmr: 1765 case X86::VMOVUPDYmr: 1766 case X86::VMOVAPDYmr: 1767 case X86::VMOVDQUYmr: 1768 case X86::VMOVDQAYmr: 1769 case X86::VMOVUPSZmr: 1770 case X86::VMOVAPSZmr: 1771 case X86::MMX_MOVD64mr: 1772 case X86::MMX_MOVQ64mr: 1773 case X86::MMX_MOVNTQmr: 1774 return true; 1775 } 1776 return false; 1777 } 1778 1779 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1780 int &FrameIndex) const { 1781 if (isFrameLoadOpcode(MI->getOpcode())) 1782 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1783 return MI->getOperand(0).getReg(); 1784 return 0; 1785 } 1786 1787 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1788 int &FrameIndex) const { 1789 if (isFrameLoadOpcode(MI->getOpcode())) { 1790 unsigned Reg; 1791 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1792 return Reg; 1793 // Check for post-frame index elimination operations 1794 const MachineMemOperand *Dummy; 1795 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1796 } 1797 return 0; 1798 } 1799 1800 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1801 int &FrameIndex) const { 1802 if (isFrameStoreOpcode(MI->getOpcode())) 1803 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1804 isFrameOperand(MI, 0, FrameIndex)) 1805 return MI->getOperand(X86::AddrNumOperands).getReg(); 1806 return 0; 1807 } 1808 1809 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1810 int &FrameIndex) const { 1811 if (isFrameStoreOpcode(MI->getOpcode())) { 1812 unsigned Reg; 1813 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1814 return Reg; 1815 // Check for post-frame index elimination operations 1816 const MachineMemOperand *Dummy; 1817 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1818 } 1819 return 0; 1820 } 1821 1822 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1823 /// X86::MOVPC32r. 1824 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1825 // Don't waste compile time scanning use-def chains of physregs. 1826 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1827 return false; 1828 bool isPICBase = false; 1829 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), 1830 E = MRI.def_instr_end(); I != E; ++I) { 1831 MachineInstr *DefMI = &*I; 1832 if (DefMI->getOpcode() != X86::MOVPC32r) 1833 return false; 1834 assert(!isPICBase && "More than one PIC base?"); 1835 isPICBase = true; 1836 } 1837 return isPICBase; 1838 } 1839 1840 bool 1841 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1842 AliasAnalysis *AA) const { 1843 switch (MI->getOpcode()) { 1844 default: break; 1845 case X86::MOV8rm: 1846 case X86::MOV16rm: 1847 case X86::MOV32rm: 1848 case X86::MOV64rm: 1849 case X86::LD_Fp64m: 1850 case X86::MOVSSrm: 1851 case X86::MOVSDrm: 1852 case X86::MOVAPSrm: 1853 case X86::MOVUPSrm: 1854 case X86::MOVAPDrm: 1855 case X86::MOVDQArm: 1856 case X86::MOVDQUrm: 1857 case X86::VMOVSSrm: 1858 case X86::VMOVSDrm: 1859 case X86::VMOVAPSrm: 1860 case X86::VMOVUPSrm: 1861 case X86::VMOVAPDrm: 1862 case X86::VMOVDQArm: 1863 case X86::VMOVDQUrm: 1864 case X86::VMOVAPSYrm: 1865 case X86::VMOVUPSYrm: 1866 case X86::VMOVAPDYrm: 1867 case X86::VMOVDQAYrm: 1868 case X86::VMOVDQUYrm: 1869 case X86::MMX_MOVD64rm: 1870 case X86::MMX_MOVQ64rm: 1871 case X86::FsVMOVAPSrm: 1872 case X86::FsVMOVAPDrm: 1873 case X86::FsMOVAPSrm: 1874 case X86::FsMOVAPDrm: { 1875 // Loads from constant pools are trivially rematerializable. 1876 if (MI->getOperand(1+X86::AddrBaseReg).isReg() && 1877 MI->getOperand(1+X86::AddrScaleAmt).isImm() && 1878 MI->getOperand(1+X86::AddrIndexReg).isReg() && 1879 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 && 1880 MI->isInvariantLoad(AA)) { 1881 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); 1882 if (BaseReg == 0 || BaseReg == X86::RIP) 1883 return true; 1884 // Allow re-materialization of PIC load. 1885 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal()) 1886 return false; 1887 const MachineFunction &MF = *MI->getParent()->getParent(); 1888 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1889 return regIsPICBase(BaseReg, MRI); 1890 } 1891 return false; 1892 } 1893 1894 case X86::LEA32r: 1895 case X86::LEA64r: { 1896 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() && 1897 MI->getOperand(1+X86::AddrIndexReg).isReg() && 1898 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 && 1899 !MI->getOperand(1+X86::AddrDisp).isReg()) { 1900 // lea fi#, lea GV, etc. are all rematerializable. 1901 if (!MI->getOperand(1+X86::AddrBaseReg).isReg()) 1902 return true; 1903 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); 1904 if (BaseReg == 0) 1905 return true; 1906 // Allow re-materialization of lea PICBase + x. 1907 const MachineFunction &MF = *MI->getParent()->getParent(); 1908 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1909 return regIsPICBase(BaseReg, MRI); 1910 } 1911 return false; 1912 } 1913 } 1914 1915 // All other instructions marked M_REMATERIALIZABLE are always trivially 1916 // rematerializable. 1917 return true; 1918 } 1919 1920 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1921 MachineBasicBlock::iterator I) const { 1922 MachineBasicBlock::iterator E = MBB.end(); 1923 1924 // For compile time consideration, if we are not able to determine the 1925 // safety after visiting 4 instructions in each direction, we will assume 1926 // it's not safe. 1927 MachineBasicBlock::iterator Iter = I; 1928 for (unsigned i = 0; Iter != E && i < 4; ++i) { 1929 bool SeenDef = false; 1930 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1931 MachineOperand &MO = Iter->getOperand(j); 1932 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1933 SeenDef = true; 1934 if (!MO.isReg()) 1935 continue; 1936 if (MO.getReg() == X86::EFLAGS) { 1937 if (MO.isUse()) 1938 return false; 1939 SeenDef = true; 1940 } 1941 } 1942 1943 if (SeenDef) 1944 // This instruction defines EFLAGS, no need to look any further. 1945 return true; 1946 ++Iter; 1947 // Skip over DBG_VALUE. 1948 while (Iter != E && Iter->isDebugValue()) 1949 ++Iter; 1950 } 1951 1952 // It is safe to clobber EFLAGS at the end of a block of no successor has it 1953 // live in. 1954 if (Iter == E) { 1955 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1956 SE = MBB.succ_end(); SI != SE; ++SI) 1957 if ((*SI)->isLiveIn(X86::EFLAGS)) 1958 return false; 1959 return true; 1960 } 1961 1962 MachineBasicBlock::iterator B = MBB.begin(); 1963 Iter = I; 1964 for (unsigned i = 0; i < 4; ++i) { 1965 // If we make it to the beginning of the block, it's safe to clobber 1966 // EFLAGS iff EFLAGS is not live-in. 1967 if (Iter == B) 1968 return !MBB.isLiveIn(X86::EFLAGS); 1969 1970 --Iter; 1971 // Skip over DBG_VALUE. 1972 while (Iter != B && Iter->isDebugValue()) 1973 --Iter; 1974 1975 bool SawKill = false; 1976 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1977 MachineOperand &MO = Iter->getOperand(j); 1978 // A register mask may clobber EFLAGS, but we should still look for a 1979 // live EFLAGS def. 1980 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1981 SawKill = true; 1982 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1983 if (MO.isDef()) return MO.isDead(); 1984 if (MO.isKill()) SawKill = true; 1985 } 1986 } 1987 1988 if (SawKill) 1989 // This instruction kills EFLAGS and doesn't redefine it, so 1990 // there's no need to look further. 1991 return true; 1992 } 1993 1994 // Conservative answer. 1995 return false; 1996 } 1997 1998 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1999 MachineBasicBlock::iterator I, 2000 unsigned DestReg, unsigned SubIdx, 2001 const MachineInstr *Orig, 2002 const TargetRegisterInfo &TRI) const { 2003 // MOV32r0 is implemented with a xor which clobbers condition code. 2004 // Re-materialize it as movri instructions to avoid side effects. 2005 unsigned Opc = Orig->getOpcode(); 2006 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) { 2007 DebugLoc DL = Orig->getDebugLoc(); 2008 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0)) 2009 .addImm(0); 2010 } else { 2011 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 2012 MBB.insert(I, MI); 2013 } 2014 2015 MachineInstr *NewMI = std::prev(I); 2016 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 2017 } 2018 2019 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 2020 /// is not marked dead. 2021 static bool hasLiveCondCodeDef(MachineInstr *MI) { 2022 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2023 MachineOperand &MO = MI->getOperand(i); 2024 if (MO.isReg() && MO.isDef() && 2025 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 2026 return true; 2027 } 2028 } 2029 return false; 2030 } 2031 2032 /// getTruncatedShiftCount - check whether the shift count for a machine operand 2033 /// is non-zero. 2034 inline static unsigned getTruncatedShiftCount(MachineInstr *MI, 2035 unsigned ShiftAmtOperandIdx) { 2036 // The shift count is six bits with the REX.W prefix and five bits without. 2037 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31; 2038 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm(); 2039 return Imm & ShiftCountMask; 2040 } 2041 2042 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate 2043 /// can be represented by a LEA instruction. 2044 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) { 2045 // Left shift instructions can be transformed into load-effective-address 2046 // instructions if we can encode them appropriately. 2047 // A LEA instruction utilizes a SIB byte to encode it's scale factor. 2048 // The SIB.scale field is two bits wide which means that we can encode any 2049 // shift amount less than 4. 2050 return ShAmt < 4 && ShAmt > 0; 2051 } 2052 2053 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, 2054 unsigned Opc, bool AllowSP, 2055 unsigned &NewSrc, bool &isKill, bool &isUndef, 2056 MachineOperand &ImplicitOp) const { 2057 MachineFunction &MF = *MI->getParent()->getParent(); 2058 const TargetRegisterClass *RC; 2059 if (AllowSP) { 2060 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; 2061 } else { 2062 RC = Opc != X86::LEA32r ? 2063 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; 2064 } 2065 unsigned SrcReg = Src.getReg(); 2066 2067 // For both LEA64 and LEA32 the register already has essentially the right 2068 // type (32-bit or 64-bit) we may just need to forbid SP. 2069 if (Opc != X86::LEA64_32r) { 2070 NewSrc = SrcReg; 2071 isKill = Src.isKill(); 2072 isUndef = Src.isUndef(); 2073 2074 if (TargetRegisterInfo::isVirtualRegister(NewSrc) && 2075 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) 2076 return false; 2077 2078 return true; 2079 } 2080 2081 // This is for an LEA64_32r and incoming registers are 32-bit. One way or 2082 // another we need to add 64-bit registers to the final MI. 2083 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 2084 ImplicitOp = Src; 2085 ImplicitOp.setImplicit(); 2086 2087 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64); 2088 MachineBasicBlock::LivenessQueryResult LQR = 2089 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI); 2090 2091 switch (LQR) { 2092 case MachineBasicBlock::LQR_Unknown: 2093 // We can't give sane liveness flags to the instruction, abandon LEA 2094 // formation. 2095 return false; 2096 case MachineBasicBlock::LQR_Live: 2097 isKill = MI->killsRegister(SrcReg); 2098 isUndef = false; 2099 break; 2100 default: 2101 // The physreg itself is dead, so we have to use it as an <undef>. 2102 isKill = false; 2103 isUndef = true; 2104 break; 2105 } 2106 } else { 2107 // Virtual register of the wrong class, we have to create a temporary 64-bit 2108 // vreg to feed into the LEA. 2109 NewSrc = MF.getRegInfo().createVirtualRegister(RC); 2110 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 2111 get(TargetOpcode::COPY)) 2112 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) 2113 .addOperand(Src); 2114 2115 // Which is obviously going to be dead after we're done with it. 2116 isKill = true; 2117 isUndef = false; 2118 } 2119 2120 // We've set all the parameters without issue. 2121 return true; 2122 } 2123 2124 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 2125 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 2126 /// to a 32-bit superregister and then truncating back down to a 16-bit 2127 /// subregister. 2128 MachineInstr * 2129 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 2130 MachineFunction::iterator &MFI, 2131 MachineBasicBlock::iterator &MBBI, 2132 LiveVariables *LV) const { 2133 MachineInstr *MI = MBBI; 2134 unsigned Dest = MI->getOperand(0).getReg(); 2135 unsigned Src = MI->getOperand(1).getReg(); 2136 bool isDead = MI->getOperand(0).isDead(); 2137 bool isKill = MI->getOperand(1).isKill(); 2138 2139 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 2140 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 2141 unsigned Opc, leaInReg; 2142 if (Subtarget.is64Bit()) { 2143 Opc = X86::LEA64_32r; 2144 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 2145 } else { 2146 Opc = X86::LEA32r; 2147 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 2148 } 2149 2150 // Build and insert into an implicit UNDEF value. This is OK because 2151 // well be shifting and then extracting the lower 16-bits. 2152 // This has the potential to cause partial register stall. e.g. 2153 // movw (%rbp,%rcx,2), %dx 2154 // leal -65(%rdx), %esi 2155 // But testing has shown this *does* help performance in 64-bit mode (at 2156 // least on modern x86 machines). 2157 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 2158 MachineInstr *InsMI = 2159 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2160 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 2161 .addReg(Src, getKillRegState(isKill)); 2162 2163 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 2164 get(Opc), leaOutReg); 2165 switch (MIOpc) { 2166 default: llvm_unreachable("Unreachable!"); 2167 case X86::SHL16ri: { 2168 unsigned ShAmt = MI->getOperand(2).getImm(); 2169 MIB.addReg(0).addImm(1 << ShAmt) 2170 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 2171 break; 2172 } 2173 case X86::INC16r: 2174 addRegOffset(MIB, leaInReg, true, 1); 2175 break; 2176 case X86::DEC16r: 2177 addRegOffset(MIB, leaInReg, true, -1); 2178 break; 2179 case X86::ADD16ri: 2180 case X86::ADD16ri8: 2181 case X86::ADD16ri_DB: 2182 case X86::ADD16ri8_DB: 2183 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 2184 break; 2185 case X86::ADD16rr: 2186 case X86::ADD16rr_DB: { 2187 unsigned Src2 = MI->getOperand(2).getReg(); 2188 bool isKill2 = MI->getOperand(2).isKill(); 2189 unsigned leaInReg2 = 0; 2190 MachineInstr *InsMI2 = nullptr; 2191 if (Src == Src2) { 2192 // ADD16rr %reg1028<kill>, %reg1028 2193 // just a single insert_subreg. 2194 addRegReg(MIB, leaInReg, true, leaInReg, false); 2195 } else { 2196 if (Subtarget.is64Bit()) 2197 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 2198 else 2199 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 2200 // Build and insert into an implicit UNDEF value. This is OK because 2201 // well be shifting and then extracting the lower 16-bits. 2202 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 2203 InsMI2 = 2204 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2205 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 2206 .addReg(Src2, getKillRegState(isKill2)); 2207 addRegReg(MIB, leaInReg, true, leaInReg2, true); 2208 } 2209 if (LV && isKill2 && InsMI2) 2210 LV->replaceKillInstruction(Src2, MI, InsMI2); 2211 break; 2212 } 2213 } 2214 2215 MachineInstr *NewMI = MIB; 2216 MachineInstr *ExtMI = 2217 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 2218 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 2219 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 2220 2221 if (LV) { 2222 // Update live variables 2223 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 2224 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 2225 if (isKill) 2226 LV->replaceKillInstruction(Src, MI, InsMI); 2227 if (isDead) 2228 LV->replaceKillInstruction(Dest, MI, ExtMI); 2229 } 2230 2231 return ExtMI; 2232 } 2233 2234 /// convertToThreeAddress - This method must be implemented by targets that 2235 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2236 /// may be able to convert a two-address instruction into a true 2237 /// three-address instruction on demand. This allows the X86 target (for 2238 /// example) to convert ADD and SHL instructions into LEA instructions if they 2239 /// would require register copies due to two-addressness. 2240 /// 2241 /// This method returns a null pointer if the transformation cannot be 2242 /// performed, otherwise it returns the new instruction. 2243 /// 2244 MachineInstr * 2245 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 2246 MachineBasicBlock::iterator &MBBI, 2247 LiveVariables *LV) const { 2248 MachineInstr *MI = MBBI; 2249 2250 // The following opcodes also sets the condition code register(s). Only 2251 // convert them to equivalent lea if the condition code register def's 2252 // are dead! 2253 if (hasLiveCondCodeDef(MI)) 2254 return nullptr; 2255 2256 MachineFunction &MF = *MI->getParent()->getParent(); 2257 // All instructions input are two-addr instructions. Get the known operands. 2258 const MachineOperand &Dest = MI->getOperand(0); 2259 const MachineOperand &Src = MI->getOperand(1); 2260 2261 MachineInstr *NewMI = nullptr; 2262 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 2263 // we have better subtarget support, enable the 16-bit LEA generation here. 2264 // 16-bit LEA is also slow on Core2. 2265 bool DisableLEA16 = true; 2266 bool is64Bit = Subtarget.is64Bit(); 2267 2268 unsigned MIOpc = MI->getOpcode(); 2269 switch (MIOpc) { 2270 default: return nullptr; 2271 case X86::SHL64ri: { 2272 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2273 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2274 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2275 2276 // LEA can't handle RSP. 2277 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2278 !MF.getRegInfo().constrainRegClass(Src.getReg(), 2279 &X86::GR64_NOSPRegClass)) 2280 return nullptr; 2281 2282 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2283 .addOperand(Dest) 2284 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2285 break; 2286 } 2287 case X86::SHL32ri: { 2288 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2289 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2290 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2291 2292 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2293 2294 // LEA can't handle ESP. 2295 bool isKill, isUndef; 2296 unsigned SrcReg; 2297 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2298 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2299 SrcReg, isKill, isUndef, ImplicitOp)) 2300 return nullptr; 2301 2302 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2303 .addOperand(Dest) 2304 .addReg(0).addImm(1 << ShAmt) 2305 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 2306 .addImm(0).addReg(0); 2307 if (ImplicitOp.getReg() != 0) 2308 MIB.addOperand(ImplicitOp); 2309 NewMI = MIB; 2310 2311 break; 2312 } 2313 case X86::SHL16ri: { 2314 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2315 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2316 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr; 2317 2318 if (DisableLEA16) 2319 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr; 2320 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2321 .addOperand(Dest) 2322 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2323 break; 2324 } 2325 case X86::INC64r: 2326 case X86::INC32r: { 2327 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2328 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 2329 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2330 bool isKill, isUndef; 2331 unsigned SrcReg; 2332 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2333 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2334 SrcReg, isKill, isUndef, ImplicitOp)) 2335 return nullptr; 2336 2337 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2338 .addOperand(Dest) 2339 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)); 2340 if (ImplicitOp.getReg() != 0) 2341 MIB.addOperand(ImplicitOp); 2342 2343 NewMI = addOffset(MIB, 1); 2344 break; 2345 } 2346 case X86::INC16r: 2347 if (DisableLEA16) 2348 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2349 : nullptr; 2350 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2351 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2352 .addOperand(Dest).addOperand(Src), 1); 2353 break; 2354 case X86::DEC64r: 2355 case X86::DEC32r: { 2356 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2357 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 2358 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2359 2360 bool isKill, isUndef; 2361 unsigned SrcReg; 2362 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2363 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2364 SrcReg, isKill, isUndef, ImplicitOp)) 2365 return nullptr; 2366 2367 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2368 .addOperand(Dest) 2369 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2370 if (ImplicitOp.getReg() != 0) 2371 MIB.addOperand(ImplicitOp); 2372 2373 NewMI = addOffset(MIB, -1); 2374 2375 break; 2376 } 2377 case X86::DEC16r: 2378 if (DisableLEA16) 2379 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2380 : nullptr; 2381 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2382 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2383 .addOperand(Dest).addOperand(Src), -1); 2384 break; 2385 case X86::ADD64rr: 2386 case X86::ADD64rr_DB: 2387 case X86::ADD32rr: 2388 case X86::ADD32rr_DB: { 2389 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2390 unsigned Opc; 2391 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) 2392 Opc = X86::LEA64r; 2393 else 2394 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2395 2396 bool isKill, isUndef; 2397 unsigned SrcReg; 2398 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2399 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2400 SrcReg, isKill, isUndef, ImplicitOp)) 2401 return nullptr; 2402 2403 const MachineOperand &Src2 = MI->getOperand(2); 2404 bool isKill2, isUndef2; 2405 unsigned SrcReg2; 2406 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false); 2407 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 2408 SrcReg2, isKill2, isUndef2, ImplicitOp2)) 2409 return nullptr; 2410 2411 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2412 .addOperand(Dest); 2413 if (ImplicitOp.getReg() != 0) 2414 MIB.addOperand(ImplicitOp); 2415 if (ImplicitOp2.getReg() != 0) 2416 MIB.addOperand(ImplicitOp2); 2417 2418 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); 2419 2420 // Preserve undefness of the operands. 2421 NewMI->getOperand(1).setIsUndef(isUndef); 2422 NewMI->getOperand(3).setIsUndef(isUndef2); 2423 2424 if (LV && Src2.isKill()) 2425 LV->replaceKillInstruction(SrcReg2, MI, NewMI); 2426 break; 2427 } 2428 case X86::ADD16rr: 2429 case X86::ADD16rr_DB: { 2430 if (DisableLEA16) 2431 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2432 : nullptr; 2433 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2434 unsigned Src2 = MI->getOperand(2).getReg(); 2435 bool isKill2 = MI->getOperand(2).isKill(); 2436 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2437 .addOperand(Dest), 2438 Src.getReg(), Src.isKill(), Src2, isKill2); 2439 2440 // Preserve undefness of the operands. 2441 bool isUndef = MI->getOperand(1).isUndef(); 2442 bool isUndef2 = MI->getOperand(2).isUndef(); 2443 NewMI->getOperand(1).setIsUndef(isUndef); 2444 NewMI->getOperand(3).setIsUndef(isUndef2); 2445 2446 if (LV && isKill2) 2447 LV->replaceKillInstruction(Src2, MI, NewMI); 2448 break; 2449 } 2450 case X86::ADD64ri32: 2451 case X86::ADD64ri8: 2452 case X86::ADD64ri32_DB: 2453 case X86::ADD64ri8_DB: 2454 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2455 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2456 .addOperand(Dest).addOperand(Src), 2457 MI->getOperand(2).getImm()); 2458 break; 2459 case X86::ADD32ri: 2460 case X86::ADD32ri8: 2461 case X86::ADD32ri_DB: 2462 case X86::ADD32ri8_DB: { 2463 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2464 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2465 2466 bool isKill, isUndef; 2467 unsigned SrcReg; 2468 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2469 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2470 SrcReg, isKill, isUndef, ImplicitOp)) 2471 return nullptr; 2472 2473 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2474 .addOperand(Dest) 2475 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2476 if (ImplicitOp.getReg() != 0) 2477 MIB.addOperand(ImplicitOp); 2478 2479 NewMI = addOffset(MIB, MI->getOperand(2).getImm()); 2480 break; 2481 } 2482 case X86::ADD16ri: 2483 case X86::ADD16ri8: 2484 case X86::ADD16ri_DB: 2485 case X86::ADD16ri8_DB: 2486 if (DisableLEA16) 2487 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) 2488 : nullptr; 2489 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2490 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2491 .addOperand(Dest).addOperand(Src), 2492 MI->getOperand(2).getImm()); 2493 break; 2494 } 2495 2496 if (!NewMI) return nullptr; 2497 2498 if (LV) { // Update live variables 2499 if (Src.isKill()) 2500 LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2501 if (Dest.isDead()) 2502 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2503 } 2504 2505 MFI->insert(MBBI, NewMI); // Insert the new inst 2506 return NewMI; 2507 } 2508 2509 /// commuteInstruction - We have a few instructions that must be hacked on to 2510 /// commute them. 2511 /// 2512 MachineInstr * 2513 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2514 switch (MI->getOpcode()) { 2515 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2516 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2517 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2518 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2519 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2520 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2521 unsigned Opc; 2522 unsigned Size; 2523 switch (MI->getOpcode()) { 2524 default: llvm_unreachable("Unreachable!"); 2525 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2526 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2527 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2528 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2529 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2530 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2531 } 2532 unsigned Amt = MI->getOperand(3).getImm(); 2533 if (NewMI) { 2534 MachineFunction &MF = *MI->getParent()->getParent(); 2535 MI = MF.CloneMachineInstr(MI); 2536 NewMI = false; 2537 } 2538 MI->setDesc(get(Opc)); 2539 MI->getOperand(3).setImm(Size-Amt); 2540 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2541 } 2542 case X86::BLENDPDrri: 2543 case X86::BLENDPSrri: 2544 case X86::PBLENDWrri: 2545 case X86::VBLENDPDrri: 2546 case X86::VBLENDPSrri: 2547 case X86::VBLENDPDYrri: 2548 case X86::VBLENDPSYrri: 2549 case X86::VPBLENDDrri: 2550 case X86::VPBLENDWrri: 2551 case X86::VPBLENDDYrri: 2552 case X86::VPBLENDWYrri:{ 2553 unsigned Mask; 2554 switch (MI->getOpcode()) { 2555 default: llvm_unreachable("Unreachable!"); 2556 case X86::BLENDPDrri: Mask = 0x03; break; 2557 case X86::BLENDPSrri: Mask = 0x0F; break; 2558 case X86::PBLENDWrri: Mask = 0xFF; break; 2559 case X86::VBLENDPDrri: Mask = 0x03; break; 2560 case X86::VBLENDPSrri: Mask = 0x0F; break; 2561 case X86::VBLENDPDYrri: Mask = 0x0F; break; 2562 case X86::VBLENDPSYrri: Mask = 0xFF; break; 2563 case X86::VPBLENDDrri: Mask = 0x0F; break; 2564 case X86::VPBLENDWrri: Mask = 0xFF; break; 2565 case X86::VPBLENDDYrri: Mask = 0xFF; break; 2566 case X86::VPBLENDWYrri: Mask = 0xFF; break; 2567 } 2568 // Only the least significant bits of Imm are used. 2569 unsigned Imm = MI->getOperand(3).getImm() & Mask; 2570 if (NewMI) { 2571 MachineFunction &MF = *MI->getParent()->getParent(); 2572 MI = MF.CloneMachineInstr(MI); 2573 NewMI = false; 2574 } 2575 MI->getOperand(3).setImm(Mask ^ Imm); 2576 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2577 } 2578 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2579 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2580 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2581 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2582 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2583 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2584 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2585 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2586 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2587 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2588 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2589 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2590 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2591 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2592 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2593 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2594 unsigned Opc; 2595 switch (MI->getOpcode()) { 2596 default: llvm_unreachable("Unreachable!"); 2597 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2598 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2599 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2600 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2601 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2602 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2603 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2604 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2605 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2606 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2607 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2608 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2609 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2610 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2611 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2612 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2613 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2614 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2615 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2616 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2617 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2618 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2619 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2620 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2621 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2622 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2623 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2624 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2625 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2626 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2627 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2628 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2629 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2630 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2631 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2632 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2633 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2634 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2635 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2636 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2637 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2638 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2639 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2640 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2641 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2642 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2643 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2644 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2645 } 2646 if (NewMI) { 2647 MachineFunction &MF = *MI->getParent()->getParent(); 2648 MI = MF.CloneMachineInstr(MI); 2649 NewMI = false; 2650 } 2651 MI->setDesc(get(Opc)); 2652 // Fallthrough intended. 2653 } 2654 default: 2655 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2656 } 2657 } 2658 2659 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 2660 unsigned &SrcOpIdx2) const { 2661 switch (MI->getOpcode()) { 2662 case X86::BLENDPDrri: 2663 case X86::BLENDPSrri: 2664 case X86::PBLENDWrri: 2665 case X86::VBLENDPDrri: 2666 case X86::VBLENDPSrri: 2667 case X86::VBLENDPDYrri: 2668 case X86::VBLENDPSYrri: 2669 case X86::VPBLENDDrri: 2670 case X86::VPBLENDDYrri: 2671 case X86::VPBLENDWrri: 2672 case X86::VPBLENDWYrri: 2673 SrcOpIdx1 = 1; 2674 SrcOpIdx2 = 2; 2675 return true; 2676 case X86::VFMADDPDr231r: 2677 case X86::VFMADDPSr231r: 2678 case X86::VFMADDSDr231r: 2679 case X86::VFMADDSSr231r: 2680 case X86::VFMSUBPDr231r: 2681 case X86::VFMSUBPSr231r: 2682 case X86::VFMSUBSDr231r: 2683 case X86::VFMSUBSSr231r: 2684 case X86::VFNMADDPDr231r: 2685 case X86::VFNMADDPSr231r: 2686 case X86::VFNMADDSDr231r: 2687 case X86::VFNMADDSSr231r: 2688 case X86::VFNMSUBPDr231r: 2689 case X86::VFNMSUBPSr231r: 2690 case X86::VFNMSUBSDr231r: 2691 case X86::VFNMSUBSSr231r: 2692 case X86::VFMADDPDr231rY: 2693 case X86::VFMADDPSr231rY: 2694 case X86::VFMSUBPDr231rY: 2695 case X86::VFMSUBPSr231rY: 2696 case X86::VFNMADDPDr231rY: 2697 case X86::VFNMADDPSr231rY: 2698 case X86::VFNMSUBPDr231rY: 2699 case X86::VFNMSUBPSr231rY: 2700 SrcOpIdx1 = 2; 2701 SrcOpIdx2 = 3; 2702 return true; 2703 default: 2704 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2); 2705 } 2706 } 2707 2708 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2709 switch (BrOpc) { 2710 default: return X86::COND_INVALID; 2711 case X86::JE_1: return X86::COND_E; 2712 case X86::JNE_1: return X86::COND_NE; 2713 case X86::JL_1: return X86::COND_L; 2714 case X86::JLE_1: return X86::COND_LE; 2715 case X86::JG_1: return X86::COND_G; 2716 case X86::JGE_1: return X86::COND_GE; 2717 case X86::JB_1: return X86::COND_B; 2718 case X86::JBE_1: return X86::COND_BE; 2719 case X86::JA_1: return X86::COND_A; 2720 case X86::JAE_1: return X86::COND_AE; 2721 case X86::JS_1: return X86::COND_S; 2722 case X86::JNS_1: return X86::COND_NS; 2723 case X86::JP_1: return X86::COND_P; 2724 case X86::JNP_1: return X86::COND_NP; 2725 case X86::JO_1: return X86::COND_O; 2726 case X86::JNO_1: return X86::COND_NO; 2727 } 2728 } 2729 2730 /// getCondFromSETOpc - return condition code of a SET opcode. 2731 static X86::CondCode getCondFromSETOpc(unsigned Opc) { 2732 switch (Opc) { 2733 default: return X86::COND_INVALID; 2734 case X86::SETAr: case X86::SETAm: return X86::COND_A; 2735 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2736 case X86::SETBr: case X86::SETBm: return X86::COND_B; 2737 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2738 case X86::SETEr: case X86::SETEm: return X86::COND_E; 2739 case X86::SETGr: case X86::SETGm: return X86::COND_G; 2740 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2741 case X86::SETLr: case X86::SETLm: return X86::COND_L; 2742 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2743 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2744 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2745 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2746 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2747 case X86::SETOr: case X86::SETOm: return X86::COND_O; 2748 case X86::SETPr: case X86::SETPm: return X86::COND_P; 2749 case X86::SETSr: case X86::SETSm: return X86::COND_S; 2750 } 2751 } 2752 2753 /// getCondFromCmovOpc - return condition code of a CMov opcode. 2754 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 2755 switch (Opc) { 2756 default: return X86::COND_INVALID; 2757 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2758 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2759 return X86::COND_A; 2760 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2761 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2762 return X86::COND_AE; 2763 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2764 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2765 return X86::COND_B; 2766 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2767 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2768 return X86::COND_BE; 2769 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2770 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2771 return X86::COND_E; 2772 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2773 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2774 return X86::COND_G; 2775 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2776 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2777 return X86::COND_GE; 2778 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2779 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2780 return X86::COND_L; 2781 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2782 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2783 return X86::COND_LE; 2784 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2785 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2786 return X86::COND_NE; 2787 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2788 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2789 return X86::COND_NO; 2790 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2791 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2792 return X86::COND_NP; 2793 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2794 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2795 return X86::COND_NS; 2796 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2797 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2798 return X86::COND_O; 2799 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2800 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2801 return X86::COND_P; 2802 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2803 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2804 return X86::COND_S; 2805 } 2806 } 2807 2808 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2809 switch (CC) { 2810 default: llvm_unreachable("Illegal condition code!"); 2811 case X86::COND_E: return X86::JE_1; 2812 case X86::COND_NE: return X86::JNE_1; 2813 case X86::COND_L: return X86::JL_1; 2814 case X86::COND_LE: return X86::JLE_1; 2815 case X86::COND_G: return X86::JG_1; 2816 case X86::COND_GE: return X86::JGE_1; 2817 case X86::COND_B: return X86::JB_1; 2818 case X86::COND_BE: return X86::JBE_1; 2819 case X86::COND_A: return X86::JA_1; 2820 case X86::COND_AE: return X86::JAE_1; 2821 case X86::COND_S: return X86::JS_1; 2822 case X86::COND_NS: return X86::JNS_1; 2823 case X86::COND_P: return X86::JP_1; 2824 case X86::COND_NP: return X86::JNP_1; 2825 case X86::COND_O: return X86::JO_1; 2826 case X86::COND_NO: return X86::JNO_1; 2827 } 2828 } 2829 2830 /// GetOppositeBranchCondition - Return the inverse of the specified condition, 2831 /// e.g. turning COND_E to COND_NE. 2832 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2833 switch (CC) { 2834 default: llvm_unreachable("Illegal condition code!"); 2835 case X86::COND_E: return X86::COND_NE; 2836 case X86::COND_NE: return X86::COND_E; 2837 case X86::COND_L: return X86::COND_GE; 2838 case X86::COND_LE: return X86::COND_G; 2839 case X86::COND_G: return X86::COND_LE; 2840 case X86::COND_GE: return X86::COND_L; 2841 case X86::COND_B: return X86::COND_AE; 2842 case X86::COND_BE: return X86::COND_A; 2843 case X86::COND_A: return X86::COND_BE; 2844 case X86::COND_AE: return X86::COND_B; 2845 case X86::COND_S: return X86::COND_NS; 2846 case X86::COND_NS: return X86::COND_S; 2847 case X86::COND_P: return X86::COND_NP; 2848 case X86::COND_NP: return X86::COND_P; 2849 case X86::COND_O: return X86::COND_NO; 2850 case X86::COND_NO: return X86::COND_O; 2851 } 2852 } 2853 2854 /// getSwappedCondition - assume the flags are set by MI(a,b), return 2855 /// the condition code if we modify the instructions such that flags are 2856 /// set by MI(b,a). 2857 static X86::CondCode getSwappedCondition(X86::CondCode CC) { 2858 switch (CC) { 2859 default: return X86::COND_INVALID; 2860 case X86::COND_E: return X86::COND_E; 2861 case X86::COND_NE: return X86::COND_NE; 2862 case X86::COND_L: return X86::COND_G; 2863 case X86::COND_LE: return X86::COND_GE; 2864 case X86::COND_G: return X86::COND_L; 2865 case X86::COND_GE: return X86::COND_LE; 2866 case X86::COND_B: return X86::COND_A; 2867 case X86::COND_BE: return X86::COND_AE; 2868 case X86::COND_A: return X86::COND_B; 2869 case X86::COND_AE: return X86::COND_BE; 2870 } 2871 } 2872 2873 /// getSETFromCond - Return a set opcode for the given condition and 2874 /// whether it has memory operand. 2875 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) { 2876 static const uint16_t Opc[16][2] = { 2877 { X86::SETAr, X86::SETAm }, 2878 { X86::SETAEr, X86::SETAEm }, 2879 { X86::SETBr, X86::SETBm }, 2880 { X86::SETBEr, X86::SETBEm }, 2881 { X86::SETEr, X86::SETEm }, 2882 { X86::SETGr, X86::SETGm }, 2883 { X86::SETGEr, X86::SETGEm }, 2884 { X86::SETLr, X86::SETLm }, 2885 { X86::SETLEr, X86::SETLEm }, 2886 { X86::SETNEr, X86::SETNEm }, 2887 { X86::SETNOr, X86::SETNOm }, 2888 { X86::SETNPr, X86::SETNPm }, 2889 { X86::SETNSr, X86::SETNSm }, 2890 { X86::SETOr, X86::SETOm }, 2891 { X86::SETPr, X86::SETPm }, 2892 { X86::SETSr, X86::SETSm } 2893 }; 2894 2895 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes"); 2896 return Opc[CC][HasMemoryOperand ? 1 : 0]; 2897 } 2898 2899 /// getCMovFromCond - Return a cmov opcode for the given condition, 2900 /// register size in bytes, and operand type. 2901 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, 2902 bool HasMemoryOperand) { 2903 static const uint16_t Opc[32][3] = { 2904 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2905 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2906 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2907 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2908 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2909 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2910 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2911 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2912 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2913 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2914 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2915 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2916 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2917 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2918 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2919 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2920 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2921 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2922 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2923 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2924 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2925 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2926 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2927 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2928 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2929 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2930 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2931 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2932 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2933 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2934 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2935 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2936 }; 2937 2938 assert(CC < 16 && "Can only handle standard cond codes"); 2939 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2940 switch(RegBytes) { 2941 default: llvm_unreachable("Illegal register size!"); 2942 case 2: return Opc[Idx][0]; 2943 case 4: return Opc[Idx][1]; 2944 case 8: return Opc[Idx][2]; 2945 } 2946 } 2947 2948 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2949 if (!MI->isTerminator()) return false; 2950 2951 // Conditional branch is a special case. 2952 if (MI->isBranch() && !MI->isBarrier()) 2953 return true; 2954 if (!MI->isPredicable()) 2955 return true; 2956 return !isPredicated(MI); 2957 } 2958 2959 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2960 MachineBasicBlock *&TBB, 2961 MachineBasicBlock *&FBB, 2962 SmallVectorImpl<MachineOperand> &Cond, 2963 bool AllowModify) const { 2964 // Start from the bottom of the block and work up, examining the 2965 // terminator instructions. 2966 MachineBasicBlock::iterator I = MBB.end(); 2967 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2968 while (I != MBB.begin()) { 2969 --I; 2970 if (I->isDebugValue()) 2971 continue; 2972 2973 // Working from the bottom, when we see a non-terminator instruction, we're 2974 // done. 2975 if (!isUnpredicatedTerminator(I)) 2976 break; 2977 2978 // A terminator that isn't a branch can't easily be handled by this 2979 // analysis. 2980 if (!I->isBranch()) 2981 return true; 2982 2983 // Handle unconditional branches. 2984 if (I->getOpcode() == X86::JMP_1) { 2985 UnCondBrIter = I; 2986 2987 if (!AllowModify) { 2988 TBB = I->getOperand(0).getMBB(); 2989 continue; 2990 } 2991 2992 // If the block has any instructions after a JMP, delete them. 2993 while (std::next(I) != MBB.end()) 2994 std::next(I)->eraseFromParent(); 2995 2996 Cond.clear(); 2997 FBB = nullptr; 2998 2999 // Delete the JMP if it's equivalent to a fall-through. 3000 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 3001 TBB = nullptr; 3002 I->eraseFromParent(); 3003 I = MBB.end(); 3004 UnCondBrIter = MBB.end(); 3005 continue; 3006 } 3007 3008 // TBB is used to indicate the unconditional destination. 3009 TBB = I->getOperand(0).getMBB(); 3010 continue; 3011 } 3012 3013 // Handle conditional branches. 3014 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 3015 if (BranchCode == X86::COND_INVALID) 3016 return true; // Can't handle indirect branch. 3017 3018 // Working from the bottom, handle the first conditional branch. 3019 if (Cond.empty()) { 3020 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 3021 if (AllowModify && UnCondBrIter != MBB.end() && 3022 MBB.isLayoutSuccessor(TargetBB)) { 3023 // If we can modify the code and it ends in something like: 3024 // 3025 // jCC L1 3026 // jmp L2 3027 // L1: 3028 // ... 3029 // L2: 3030 // 3031 // Then we can change this to: 3032 // 3033 // jnCC L2 3034 // L1: 3035 // ... 3036 // L2: 3037 // 3038 // Which is a bit more efficient. 3039 // We conditionally jump to the fall-through block. 3040 BranchCode = GetOppositeBranchCondition(BranchCode); 3041 unsigned JNCC = GetCondBranchFromCond(BranchCode); 3042 MachineBasicBlock::iterator OldInst = I; 3043 3044 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 3045 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 3046 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1)) 3047 .addMBB(TargetBB); 3048 3049 OldInst->eraseFromParent(); 3050 UnCondBrIter->eraseFromParent(); 3051 3052 // Restart the analysis. 3053 UnCondBrIter = MBB.end(); 3054 I = MBB.end(); 3055 continue; 3056 } 3057 3058 FBB = TBB; 3059 TBB = I->getOperand(0).getMBB(); 3060 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 3061 continue; 3062 } 3063 3064 // Handle subsequent conditional branches. Only handle the case where all 3065 // conditional branches branch to the same destination and their condition 3066 // opcodes fit one of the special multi-branch idioms. 3067 assert(Cond.size() == 1); 3068 assert(TBB); 3069 3070 // Only handle the case where all conditional branches branch to the same 3071 // destination. 3072 if (TBB != I->getOperand(0).getMBB()) 3073 return true; 3074 3075 // If the conditions are the same, we can leave them alone. 3076 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 3077 if (OldBranchCode == BranchCode) 3078 continue; 3079 3080 // If they differ, see if they fit one of the known patterns. Theoretically, 3081 // we could handle more patterns here, but we shouldn't expect to see them 3082 // if instruction selection has done a reasonable job. 3083 if ((OldBranchCode == X86::COND_NP && 3084 BranchCode == X86::COND_E) || 3085 (OldBranchCode == X86::COND_E && 3086 BranchCode == X86::COND_NP)) 3087 BranchCode = X86::COND_NP_OR_E; 3088 else if ((OldBranchCode == X86::COND_P && 3089 BranchCode == X86::COND_NE) || 3090 (OldBranchCode == X86::COND_NE && 3091 BranchCode == X86::COND_P)) 3092 BranchCode = X86::COND_NE_OR_P; 3093 else 3094 return true; 3095 3096 // Update the MachineOperand. 3097 Cond[0].setImm(BranchCode); 3098 } 3099 3100 return false; 3101 } 3102 3103 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 3104 MachineBasicBlock::iterator I = MBB.end(); 3105 unsigned Count = 0; 3106 3107 while (I != MBB.begin()) { 3108 --I; 3109 if (I->isDebugValue()) 3110 continue; 3111 if (I->getOpcode() != X86::JMP_1 && 3112 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 3113 break; 3114 // Remove the branch. 3115 I->eraseFromParent(); 3116 I = MBB.end(); 3117 ++Count; 3118 } 3119 3120 return Count; 3121 } 3122 3123 unsigned 3124 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3125 MachineBasicBlock *FBB, 3126 const SmallVectorImpl<MachineOperand> &Cond, 3127 DebugLoc DL) const { 3128 // Shouldn't be a fall through. 3129 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 3130 assert((Cond.size() == 1 || Cond.size() == 0) && 3131 "X86 branch conditions have one component!"); 3132 3133 if (Cond.empty()) { 3134 // Unconditional branch? 3135 assert(!FBB && "Unconditional branch with multiple successors!"); 3136 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB); 3137 return 1; 3138 } 3139 3140 // Conditional branch. 3141 unsigned Count = 0; 3142 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 3143 switch (CC) { 3144 case X86::COND_NP_OR_E: 3145 // Synthesize NP_OR_E with two branches. 3146 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB); 3147 ++Count; 3148 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB); 3149 ++Count; 3150 break; 3151 case X86::COND_NE_OR_P: 3152 // Synthesize NE_OR_P with two branches. 3153 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB); 3154 ++Count; 3155 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB); 3156 ++Count; 3157 break; 3158 default: { 3159 unsigned Opc = GetCondBranchFromCond(CC); 3160 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 3161 ++Count; 3162 } 3163 } 3164 if (FBB) { 3165 // Two-way Conditional branch. Insert the second branch. 3166 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB); 3167 ++Count; 3168 } 3169 return Count; 3170 } 3171 3172 bool X86InstrInfo:: 3173 canInsertSelect(const MachineBasicBlock &MBB, 3174 const SmallVectorImpl<MachineOperand> &Cond, 3175 unsigned TrueReg, unsigned FalseReg, 3176 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 3177 // Not all subtargets have cmov instructions. 3178 if (!Subtarget.hasCMov()) 3179 return false; 3180 if (Cond.size() != 1) 3181 return false; 3182 // We cannot do the composite conditions, at least not in SSA form. 3183 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 3184 return false; 3185 3186 // Check register classes. 3187 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 3188 const TargetRegisterClass *RC = 3189 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 3190 if (!RC) 3191 return false; 3192 3193 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 3194 if (X86::GR16RegClass.hasSubClassEq(RC) || 3195 X86::GR32RegClass.hasSubClassEq(RC) || 3196 X86::GR64RegClass.hasSubClassEq(RC)) { 3197 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 3198 // Bridge. Probably Ivy Bridge as well. 3199 CondCycles = 2; 3200 TrueCycles = 2; 3201 FalseCycles = 2; 3202 return true; 3203 } 3204 3205 // Can't do vectors. 3206 return false; 3207 } 3208 3209 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 3210 MachineBasicBlock::iterator I, DebugLoc DL, 3211 unsigned DstReg, 3212 const SmallVectorImpl<MachineOperand> &Cond, 3213 unsigned TrueReg, unsigned FalseReg) const { 3214 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 3215 assert(Cond.size() == 1 && "Invalid Cond array"); 3216 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 3217 MRI.getRegClass(DstReg)->getSize(), 3218 false/*HasMemoryOperand*/); 3219 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 3220 } 3221 3222 /// isHReg - Test if the given register is a physical h register. 3223 static bool isHReg(unsigned Reg) { 3224 return X86::GR8_ABCD_HRegClass.contains(Reg); 3225 } 3226 3227 // Try and copy between VR128/VR64 and GR64 registers. 3228 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 3229 const X86Subtarget &Subtarget) { 3230 3231 // SrcReg(VR128) -> DestReg(GR64) 3232 // SrcReg(VR64) -> DestReg(GR64) 3233 // SrcReg(GR64) -> DestReg(VR128) 3234 // SrcReg(GR64) -> DestReg(VR64) 3235 3236 bool HasAVX = Subtarget.hasAVX(); 3237 bool HasAVX512 = Subtarget.hasAVX512(); 3238 if (X86::GR64RegClass.contains(DestReg)) { 3239 if (X86::VR128XRegClass.contains(SrcReg)) 3240 // Copy from a VR128 register to a GR64 register. 3241 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr : 3242 X86::MOVPQIto64rr); 3243 if (X86::VR64RegClass.contains(SrcReg)) 3244 // Copy from a VR64 register to a GR64 register. 3245 return X86::MOVSDto64rr; 3246 } else if (X86::GR64RegClass.contains(SrcReg)) { 3247 // Copy from a GR64 register to a VR128 register. 3248 if (X86::VR128XRegClass.contains(DestReg)) 3249 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr : 3250 X86::MOV64toPQIrr); 3251 // Copy from a GR64 register to a VR64 register. 3252 if (X86::VR64RegClass.contains(DestReg)) 3253 return X86::MOV64toSDrr; 3254 } 3255 3256 // SrcReg(FR32) -> DestReg(GR32) 3257 // SrcReg(GR32) -> DestReg(FR32) 3258 3259 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg)) 3260 // Copy from a FR32 register to a GR32 register. 3261 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr); 3262 3263 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 3264 // Copy from a GR32 register to a FR32 register. 3265 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr); 3266 return 0; 3267 } 3268 3269 inline static bool MaskRegClassContains(unsigned Reg) { 3270 return X86::VK8RegClass.contains(Reg) || 3271 X86::VK16RegClass.contains(Reg) || 3272 X86::VK32RegClass.contains(Reg) || 3273 X86::VK64RegClass.contains(Reg) || 3274 X86::VK1RegClass.contains(Reg); 3275 } 3276 static 3277 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) { 3278 if (X86::VR128XRegClass.contains(DestReg, SrcReg) || 3279 X86::VR256XRegClass.contains(DestReg, SrcReg) || 3280 X86::VR512RegClass.contains(DestReg, SrcReg)) { 3281 DestReg = get512BitSuperRegister(DestReg); 3282 SrcReg = get512BitSuperRegister(SrcReg); 3283 return X86::VMOVAPSZrr; 3284 } 3285 if (MaskRegClassContains(DestReg) && 3286 MaskRegClassContains(SrcReg)) 3287 return X86::KMOVWkk; 3288 if (MaskRegClassContains(DestReg) && 3289 (X86::GR32RegClass.contains(SrcReg) || 3290 X86::GR16RegClass.contains(SrcReg) || 3291 X86::GR8RegClass.contains(SrcReg))) { 3292 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32); 3293 return X86::KMOVWkr; 3294 } 3295 if ((X86::GR32RegClass.contains(DestReg) || 3296 X86::GR16RegClass.contains(DestReg) || 3297 X86::GR8RegClass.contains(DestReg)) && 3298 MaskRegClassContains(SrcReg)) { 3299 DestReg = getX86SubSuperRegister(DestReg, MVT::i32); 3300 return X86::KMOVWrk; 3301 } 3302 return 0; 3303 } 3304 3305 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 3306 MachineBasicBlock::iterator MI, DebugLoc DL, 3307 unsigned DestReg, unsigned SrcReg, 3308 bool KillSrc) const { 3309 // First deal with the normal symmetric copies. 3310 bool HasAVX = Subtarget.hasAVX(); 3311 bool HasAVX512 = Subtarget.hasAVX512(); 3312 unsigned Opc = 0; 3313 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 3314 Opc = X86::MOV64rr; 3315 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 3316 Opc = X86::MOV32rr; 3317 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 3318 Opc = X86::MOV16rr; 3319 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 3320 // Copying to or from a physical H register on x86-64 requires a NOREX 3321 // move. Otherwise use a normal move. 3322 if ((isHReg(DestReg) || isHReg(SrcReg)) && 3323 Subtarget.is64Bit()) { 3324 Opc = X86::MOV8rr_NOREX; 3325 // Both operands must be encodable without an REX prefix. 3326 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 3327 "8-bit H register can not be copied outside GR8_NOREX"); 3328 } else 3329 Opc = X86::MOV8rr; 3330 } 3331 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 3332 Opc = X86::MMX_MOVQ64rr; 3333 else if (HasAVX512) 3334 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg); 3335 else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 3336 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 3337 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 3338 Opc = X86::VMOVAPSYrr; 3339 if (!Opc) 3340 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget); 3341 3342 if (Opc) { 3343 BuildMI(MBB, MI, DL, get(Opc), DestReg) 3344 .addReg(SrcReg, getKillRegState(KillSrc)); 3345 return; 3346 } 3347 3348 // Moving EFLAGS to / from another register requires a push and a pop. 3349 // Notice that we have to adjust the stack if we don't want to clobber the 3350 // first frame index. See X86FrameLowering.cpp - clobbersTheStack. 3351 if (SrcReg == X86::EFLAGS) { 3352 if (X86::GR64RegClass.contains(DestReg)) { 3353 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 3354 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 3355 return; 3356 } 3357 if (X86::GR32RegClass.contains(DestReg)) { 3358 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 3359 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 3360 return; 3361 } 3362 } 3363 if (DestReg == X86::EFLAGS) { 3364 if (X86::GR64RegClass.contains(SrcReg)) { 3365 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 3366 .addReg(SrcReg, getKillRegState(KillSrc)); 3367 BuildMI(MBB, MI, DL, get(X86::POPF64)); 3368 return; 3369 } 3370 if (X86::GR32RegClass.contains(SrcReg)) { 3371 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 3372 .addReg(SrcReg, getKillRegState(KillSrc)); 3373 BuildMI(MBB, MI, DL, get(X86::POPF32)); 3374 return; 3375 } 3376 } 3377 3378 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 3379 << " to " << RI.getName(DestReg) << '\n'); 3380 llvm_unreachable("Cannot emit physreg copy instruction"); 3381 } 3382 3383 static unsigned getLoadStoreRegOpcode(unsigned Reg, 3384 const TargetRegisterClass *RC, 3385 bool isStackAligned, 3386 const X86Subtarget &STI, 3387 bool load) { 3388 if (STI.hasAVX512()) { 3389 if (X86::VK8RegClass.hasSubClassEq(RC) || 3390 X86::VK16RegClass.hasSubClassEq(RC)) 3391 return load ? X86::KMOVWkm : X86::KMOVWmk; 3392 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC)) 3393 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr; 3394 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC)) 3395 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr; 3396 if (X86::VR512RegClass.hasSubClassEq(RC)) 3397 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; 3398 } 3399 3400 bool HasAVX = STI.hasAVX(); 3401 switch (RC->getSize()) { 3402 default: 3403 llvm_unreachable("Unknown spill size"); 3404 case 1: 3405 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 3406 if (STI.is64Bit()) 3407 // Copying to or from a physical H register on x86-64 requires a NOREX 3408 // move. Otherwise use a normal move. 3409 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 3410 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 3411 return load ? X86::MOV8rm : X86::MOV8mr; 3412 case 2: 3413 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 3414 return load ? X86::MOV16rm : X86::MOV16mr; 3415 case 4: 3416 if (X86::GR32RegClass.hasSubClassEq(RC)) 3417 return load ? X86::MOV32rm : X86::MOV32mr; 3418 if (X86::FR32RegClass.hasSubClassEq(RC)) 3419 return load ? 3420 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 3421 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 3422 if (X86::RFP32RegClass.hasSubClassEq(RC)) 3423 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 3424 llvm_unreachable("Unknown 4-byte regclass"); 3425 case 8: 3426 if (X86::GR64RegClass.hasSubClassEq(RC)) 3427 return load ? X86::MOV64rm : X86::MOV64mr; 3428 if (X86::FR64RegClass.hasSubClassEq(RC)) 3429 return load ? 3430 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 3431 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 3432 if (X86::VR64RegClass.hasSubClassEq(RC)) 3433 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 3434 if (X86::RFP64RegClass.hasSubClassEq(RC)) 3435 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 3436 llvm_unreachable("Unknown 8-byte regclass"); 3437 case 10: 3438 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 3439 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 3440 case 16: { 3441 assert((X86::VR128RegClass.hasSubClassEq(RC) || 3442 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass"); 3443 // If stack is realigned we can use aligned stores. 3444 if (isStackAligned) 3445 return load ? 3446 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 3447 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 3448 else 3449 return load ? 3450 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 3451 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 3452 } 3453 case 32: 3454 assert((X86::VR256RegClass.hasSubClassEq(RC) || 3455 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass"); 3456 // If stack is realigned we can use aligned stores. 3457 if (isStackAligned) 3458 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 3459 else 3460 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 3461 case 64: 3462 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); 3463 if (isStackAligned) 3464 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr; 3465 else 3466 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr; 3467 } 3468 } 3469 3470 static unsigned getStoreRegOpcode(unsigned SrcReg, 3471 const TargetRegisterClass *RC, 3472 bool isStackAligned, 3473 const X86Subtarget &STI) { 3474 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false); 3475 } 3476 3477 3478 static unsigned getLoadRegOpcode(unsigned DestReg, 3479 const TargetRegisterClass *RC, 3480 bool isStackAligned, 3481 const X86Subtarget &STI) { 3482 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true); 3483 } 3484 3485 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 3486 MachineBasicBlock::iterator MI, 3487 unsigned SrcReg, bool isKill, int FrameIdx, 3488 const TargetRegisterClass *RC, 3489 const TargetRegisterInfo *TRI) const { 3490 const MachineFunction &MF = *MBB.getParent(); 3491 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 3492 "Stack slot too small for store"); 3493 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3494 bool isAligned = (MF.getTarget() 3495 .getSubtargetImpl() 3496 ->getFrameLowering() 3497 ->getStackAlignment() >= Alignment) || 3498 RI.canRealignStack(MF); 3499 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 3500 DebugLoc DL = MBB.findDebugLoc(MI); 3501 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 3502 .addReg(SrcReg, getKillRegState(isKill)); 3503 } 3504 3505 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 3506 bool isKill, 3507 SmallVectorImpl<MachineOperand> &Addr, 3508 const TargetRegisterClass *RC, 3509 MachineInstr::mmo_iterator MMOBegin, 3510 MachineInstr::mmo_iterator MMOEnd, 3511 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3512 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3513 bool isAligned = MMOBegin != MMOEnd && 3514 (*MMOBegin)->getAlignment() >= Alignment; 3515 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); 3516 DebugLoc DL; 3517 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 3518 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3519 MIB.addOperand(Addr[i]); 3520 MIB.addReg(SrcReg, getKillRegState(isKill)); 3521 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3522 NewMIs.push_back(MIB); 3523 } 3524 3525 3526 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 3527 MachineBasicBlock::iterator MI, 3528 unsigned DestReg, int FrameIdx, 3529 const TargetRegisterClass *RC, 3530 const TargetRegisterInfo *TRI) const { 3531 const MachineFunction &MF = *MBB.getParent(); 3532 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3533 bool isAligned = (MF.getTarget() 3534 .getSubtargetImpl() 3535 ->getFrameLowering() 3536 ->getStackAlignment() >= Alignment) || 3537 RI.canRealignStack(MF); 3538 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 3539 DebugLoc DL = MBB.findDebugLoc(MI); 3540 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 3541 } 3542 3543 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 3544 SmallVectorImpl<MachineOperand> &Addr, 3545 const TargetRegisterClass *RC, 3546 MachineInstr::mmo_iterator MMOBegin, 3547 MachineInstr::mmo_iterator MMOEnd, 3548 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3549 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16); 3550 bool isAligned = MMOBegin != MMOEnd && 3551 (*MMOBegin)->getAlignment() >= Alignment; 3552 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); 3553 DebugLoc DL; 3554 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 3555 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3556 MIB.addOperand(Addr[i]); 3557 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3558 NewMIs.push_back(MIB); 3559 } 3560 3561 bool X86InstrInfo:: 3562 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 3563 int &CmpMask, int &CmpValue) const { 3564 switch (MI->getOpcode()) { 3565 default: break; 3566 case X86::CMP64ri32: 3567 case X86::CMP64ri8: 3568 case X86::CMP32ri: 3569 case X86::CMP32ri8: 3570 case X86::CMP16ri: 3571 case X86::CMP16ri8: 3572 case X86::CMP8ri: 3573 SrcReg = MI->getOperand(0).getReg(); 3574 SrcReg2 = 0; 3575 CmpMask = ~0; 3576 CmpValue = MI->getOperand(1).getImm(); 3577 return true; 3578 // A SUB can be used to perform comparison. 3579 case X86::SUB64rm: 3580 case X86::SUB32rm: 3581 case X86::SUB16rm: 3582 case X86::SUB8rm: 3583 SrcReg = MI->getOperand(1).getReg(); 3584 SrcReg2 = 0; 3585 CmpMask = ~0; 3586 CmpValue = 0; 3587 return true; 3588 case X86::SUB64rr: 3589 case X86::SUB32rr: 3590 case X86::SUB16rr: 3591 case X86::SUB8rr: 3592 SrcReg = MI->getOperand(1).getReg(); 3593 SrcReg2 = MI->getOperand(2).getReg(); 3594 CmpMask = ~0; 3595 CmpValue = 0; 3596 return true; 3597 case X86::SUB64ri32: 3598 case X86::SUB64ri8: 3599 case X86::SUB32ri: 3600 case X86::SUB32ri8: 3601 case X86::SUB16ri: 3602 case X86::SUB16ri8: 3603 case X86::SUB8ri: 3604 SrcReg = MI->getOperand(1).getReg(); 3605 SrcReg2 = 0; 3606 CmpMask = ~0; 3607 CmpValue = MI->getOperand(2).getImm(); 3608 return true; 3609 case X86::CMP64rr: 3610 case X86::CMP32rr: 3611 case X86::CMP16rr: 3612 case X86::CMP8rr: 3613 SrcReg = MI->getOperand(0).getReg(); 3614 SrcReg2 = MI->getOperand(1).getReg(); 3615 CmpMask = ~0; 3616 CmpValue = 0; 3617 return true; 3618 case X86::TEST8rr: 3619 case X86::TEST16rr: 3620 case X86::TEST32rr: 3621 case X86::TEST64rr: 3622 SrcReg = MI->getOperand(0).getReg(); 3623 if (MI->getOperand(1).getReg() != SrcReg) return false; 3624 // Compare against zero. 3625 SrcReg2 = 0; 3626 CmpMask = ~0; 3627 CmpValue = 0; 3628 return true; 3629 } 3630 return false; 3631 } 3632 3633 /// isRedundantFlagInstr - check whether the first instruction, whose only 3634 /// purpose is to update flags, can be made redundant. 3635 /// CMPrr can be made redundant by SUBrr if the operands are the same. 3636 /// This function can be extended later on. 3637 /// SrcReg, SrcRegs: register operands for FlagI. 3638 /// ImmValue: immediate for FlagI if it takes an immediate. 3639 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3640 unsigned SrcReg2, int ImmValue, 3641 MachineInstr *OI) { 3642 if (((FlagI->getOpcode() == X86::CMP64rr && 3643 OI->getOpcode() == X86::SUB64rr) || 3644 (FlagI->getOpcode() == X86::CMP32rr && 3645 OI->getOpcode() == X86::SUB32rr)|| 3646 (FlagI->getOpcode() == X86::CMP16rr && 3647 OI->getOpcode() == X86::SUB16rr)|| 3648 (FlagI->getOpcode() == X86::CMP8rr && 3649 OI->getOpcode() == X86::SUB8rr)) && 3650 ((OI->getOperand(1).getReg() == SrcReg && 3651 OI->getOperand(2).getReg() == SrcReg2) || 3652 (OI->getOperand(1).getReg() == SrcReg2 && 3653 OI->getOperand(2).getReg() == SrcReg))) 3654 return true; 3655 3656 if (((FlagI->getOpcode() == X86::CMP64ri32 && 3657 OI->getOpcode() == X86::SUB64ri32) || 3658 (FlagI->getOpcode() == X86::CMP64ri8 && 3659 OI->getOpcode() == X86::SUB64ri8) || 3660 (FlagI->getOpcode() == X86::CMP32ri && 3661 OI->getOpcode() == X86::SUB32ri) || 3662 (FlagI->getOpcode() == X86::CMP32ri8 && 3663 OI->getOpcode() == X86::SUB32ri8) || 3664 (FlagI->getOpcode() == X86::CMP16ri && 3665 OI->getOpcode() == X86::SUB16ri) || 3666 (FlagI->getOpcode() == X86::CMP16ri8 && 3667 OI->getOpcode() == X86::SUB16ri8) || 3668 (FlagI->getOpcode() == X86::CMP8ri && 3669 OI->getOpcode() == X86::SUB8ri)) && 3670 OI->getOperand(1).getReg() == SrcReg && 3671 OI->getOperand(2).getImm() == ImmValue) 3672 return true; 3673 return false; 3674 } 3675 3676 /// isDefConvertible - check whether the definition can be converted 3677 /// to remove a comparison against zero. 3678 inline static bool isDefConvertible(MachineInstr *MI) { 3679 switch (MI->getOpcode()) { 3680 default: return false; 3681 3682 // The shift instructions only modify ZF if their shift count is non-zero. 3683 // N.B.: The processor truncates the shift count depending on the encoding. 3684 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri: 3685 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri: 3686 return getTruncatedShiftCount(MI, 2) != 0; 3687 3688 // Some left shift instructions can be turned into LEA instructions but only 3689 // if their flags aren't used. Avoid transforming such instructions. 3690 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{ 3691 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 3692 if (isTruncatedShiftCountForLEA(ShAmt)) return false; 3693 return ShAmt != 0; 3694 } 3695 3696 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8: 3697 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8: 3698 return getTruncatedShiftCount(MI, 3) != 0; 3699 3700 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3701 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3702 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3703 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3704 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3705 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 3706 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3707 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3708 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3709 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3710 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3711 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 3712 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3713 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3714 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3715 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3716 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3717 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3718 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3719 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3720 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3721 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3722 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3723 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3724 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3725 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3726 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3727 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r: 3728 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1: 3729 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1: 3730 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1: 3731 case X86::ADC32ri: case X86::ADC32ri8: 3732 case X86::ADC32rr: case X86::ADC64ri32: 3733 case X86::ADC64ri8: case X86::ADC64rr: 3734 case X86::SBB32ri: case X86::SBB32ri8: 3735 case X86::SBB32rr: case X86::SBB64ri32: 3736 case X86::SBB64ri8: case X86::SBB64rr: 3737 case X86::ANDN32rr: case X86::ANDN32rm: 3738 case X86::ANDN64rr: case X86::ANDN64rm: 3739 case X86::BEXTR32rr: case X86::BEXTR64rr: 3740 case X86::BEXTR32rm: case X86::BEXTR64rm: 3741 case X86::BLSI32rr: case X86::BLSI32rm: 3742 case X86::BLSI64rr: case X86::BLSI64rm: 3743 case X86::BLSMSK32rr:case X86::BLSMSK32rm: 3744 case X86::BLSMSK64rr:case X86::BLSMSK64rm: 3745 case X86::BLSR32rr: case X86::BLSR32rm: 3746 case X86::BLSR64rr: case X86::BLSR64rm: 3747 case X86::BZHI32rr: case X86::BZHI32rm: 3748 case X86::BZHI64rr: case X86::BZHI64rm: 3749 case X86::LZCNT16rr: case X86::LZCNT16rm: 3750 case X86::LZCNT32rr: case X86::LZCNT32rm: 3751 case X86::LZCNT64rr: case X86::LZCNT64rm: 3752 case X86::POPCNT16rr:case X86::POPCNT16rm: 3753 case X86::POPCNT32rr:case X86::POPCNT32rm: 3754 case X86::POPCNT64rr:case X86::POPCNT64rm: 3755 case X86::TZCNT16rr: case X86::TZCNT16rm: 3756 case X86::TZCNT32rr: case X86::TZCNT32rm: 3757 case X86::TZCNT64rr: case X86::TZCNT64rm: 3758 return true; 3759 } 3760 } 3761 3762 /// isUseDefConvertible - check whether the use can be converted 3763 /// to remove a comparison against zero. 3764 static X86::CondCode isUseDefConvertible(MachineInstr *MI) { 3765 switch (MI->getOpcode()) { 3766 default: return X86::COND_INVALID; 3767 case X86::LZCNT16rr: case X86::LZCNT16rm: 3768 case X86::LZCNT32rr: case X86::LZCNT32rm: 3769 case X86::LZCNT64rr: case X86::LZCNT64rm: 3770 return X86::COND_B; 3771 case X86::POPCNT16rr:case X86::POPCNT16rm: 3772 case X86::POPCNT32rr:case X86::POPCNT32rm: 3773 case X86::POPCNT64rr:case X86::POPCNT64rm: 3774 return X86::COND_E; 3775 case X86::TZCNT16rr: case X86::TZCNT16rm: 3776 case X86::TZCNT32rr: case X86::TZCNT32rm: 3777 case X86::TZCNT64rr: case X86::TZCNT64rm: 3778 return X86::COND_B; 3779 } 3780 } 3781 3782 /// optimizeCompareInstr - Check if there exists an earlier instruction that 3783 /// operates on the same source operands and sets flags in the same way as 3784 /// Compare; remove Compare if possible. 3785 bool X86InstrInfo:: 3786 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3787 int CmpMask, int CmpValue, 3788 const MachineRegisterInfo *MRI) const { 3789 // Check whether we can replace SUB with CMP. 3790 unsigned NewOpcode = 0; 3791 switch (CmpInstr->getOpcode()) { 3792 default: break; 3793 case X86::SUB64ri32: 3794 case X86::SUB64ri8: 3795 case X86::SUB32ri: 3796 case X86::SUB32ri8: 3797 case X86::SUB16ri: 3798 case X86::SUB16ri8: 3799 case X86::SUB8ri: 3800 case X86::SUB64rm: 3801 case X86::SUB32rm: 3802 case X86::SUB16rm: 3803 case X86::SUB8rm: 3804 case X86::SUB64rr: 3805 case X86::SUB32rr: 3806 case X86::SUB16rr: 3807 case X86::SUB8rr: { 3808 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3809 return false; 3810 // There is no use of the destination register, we can replace SUB with CMP. 3811 switch (CmpInstr->getOpcode()) { 3812 default: llvm_unreachable("Unreachable!"); 3813 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3814 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3815 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3816 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3817 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3818 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3819 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3820 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3821 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3822 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3823 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3824 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3825 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3826 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3827 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3828 } 3829 CmpInstr->setDesc(get(NewOpcode)); 3830 CmpInstr->RemoveOperand(0); 3831 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3832 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3833 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3834 return false; 3835 } 3836 } 3837 3838 // Get the unique definition of SrcReg. 3839 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3840 if (!MI) return false; 3841 3842 // CmpInstr is the first instruction of the BB. 3843 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3844 3845 // If we are comparing against zero, check whether we can use MI to update 3846 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3847 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3848 if (IsCmpZero && MI->getParent() != CmpInstr->getParent()) 3849 return false; 3850 3851 // If we have a use of the source register between the def and our compare 3852 // instruction we can eliminate the compare iff the use sets EFLAGS in the 3853 // right way. 3854 bool ShouldUpdateCC = false; 3855 X86::CondCode NewCC = X86::COND_INVALID; 3856 if (IsCmpZero && !isDefConvertible(MI)) { 3857 // Scan forward from the use until we hit the use we're looking for or the 3858 // compare instruction. 3859 for (MachineBasicBlock::iterator J = MI;; ++J) { 3860 // Do we have a convertible instruction? 3861 NewCC = isUseDefConvertible(J); 3862 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() && 3863 J->getOperand(1).getReg() == SrcReg) { 3864 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!"); 3865 ShouldUpdateCC = true; // Update CC later on. 3866 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going 3867 // with the new def. 3868 MI = Def = J; 3869 break; 3870 } 3871 3872 if (J == I) 3873 return false; 3874 } 3875 } 3876 3877 // We are searching for an earlier instruction that can make CmpInstr 3878 // redundant and that instruction will be saved in Sub. 3879 MachineInstr *Sub = nullptr; 3880 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3881 3882 // We iterate backward, starting from the instruction before CmpInstr and 3883 // stop when reaching the definition of a source register or done with the BB. 3884 // RI points to the instruction before CmpInstr. 3885 // If the definition is in this basic block, RE points to the definition; 3886 // otherwise, RE is the rend of the basic block. 3887 MachineBasicBlock::reverse_iterator 3888 RI = MachineBasicBlock::reverse_iterator(I), 3889 RE = CmpInstr->getParent() == MI->getParent() ? 3890 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3891 CmpInstr->getParent()->rend(); 3892 MachineInstr *Movr0Inst = nullptr; 3893 for (; RI != RE; ++RI) { 3894 MachineInstr *Instr = &*RI; 3895 // Check whether CmpInstr can be made redundant by the current instruction. 3896 if (!IsCmpZero && 3897 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3898 Sub = Instr; 3899 break; 3900 } 3901 3902 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3903 Instr->readsRegister(X86::EFLAGS, TRI)) { 3904 // This instruction modifies or uses EFLAGS. 3905 3906 // MOV32r0 etc. are implemented with xor which clobbers condition code. 3907 // They are safe to move up, if the definition to EFLAGS is dead and 3908 // earlier instructions do not read or write EFLAGS. 3909 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 && 3910 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3911 Movr0Inst = Instr; 3912 continue; 3913 } 3914 3915 // We can't remove CmpInstr. 3916 return false; 3917 } 3918 } 3919 3920 // Return false if no candidates exist. 3921 if (!IsCmpZero && !Sub) 3922 return false; 3923 3924 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3925 Sub->getOperand(2).getReg() == SrcReg); 3926 3927 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3928 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3929 // If we are done with the basic block, we need to check whether EFLAGS is 3930 // live-out. 3931 bool IsSafe = false; 3932 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3933 MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3934 for (++I; I != E; ++I) { 3935 const MachineInstr &Instr = *I; 3936 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3937 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3938 // We should check the usage if this instruction uses and updates EFLAGS. 3939 if (!UseEFLAGS && ModifyEFLAGS) { 3940 // It is safe to remove CmpInstr if EFLAGS is updated again. 3941 IsSafe = true; 3942 break; 3943 } 3944 if (!UseEFLAGS && !ModifyEFLAGS) 3945 continue; 3946 3947 // EFLAGS is used by this instruction. 3948 X86::CondCode OldCC = X86::COND_INVALID; 3949 bool OpcIsSET = false; 3950 if (IsCmpZero || IsSwapped) { 3951 // We decode the condition code from opcode. 3952 if (Instr.isBranch()) 3953 OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3954 else { 3955 OldCC = getCondFromSETOpc(Instr.getOpcode()); 3956 if (OldCC != X86::COND_INVALID) 3957 OpcIsSET = true; 3958 else 3959 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 3960 } 3961 if (OldCC == X86::COND_INVALID) return false; 3962 } 3963 if (IsCmpZero) { 3964 switch (OldCC) { 3965 default: break; 3966 case X86::COND_A: case X86::COND_AE: 3967 case X86::COND_B: case X86::COND_BE: 3968 case X86::COND_G: case X86::COND_GE: 3969 case X86::COND_L: case X86::COND_LE: 3970 case X86::COND_O: case X86::COND_NO: 3971 // CF and OF are used, we can't perform this optimization. 3972 return false; 3973 } 3974 3975 // If we're updating the condition code check if we have to reverse the 3976 // condition. 3977 if (ShouldUpdateCC) 3978 switch (OldCC) { 3979 default: 3980 return false; 3981 case X86::COND_E: 3982 break; 3983 case X86::COND_NE: 3984 NewCC = GetOppositeBranchCondition(NewCC); 3985 break; 3986 } 3987 } else if (IsSwapped) { 3988 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3989 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3990 // We swap the condition code and synthesize the new opcode. 3991 NewCC = getSwappedCondition(OldCC); 3992 if (NewCC == X86::COND_INVALID) return false; 3993 } 3994 3995 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) { 3996 // Synthesize the new opcode. 3997 bool HasMemoryOperand = Instr.hasOneMemOperand(); 3998 unsigned NewOpc; 3999 if (Instr.isBranch()) 4000 NewOpc = GetCondBranchFromCond(NewCC); 4001 else if(OpcIsSET) 4002 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 4003 else { 4004 unsigned DstReg = Instr.getOperand(0).getReg(); 4005 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 4006 HasMemoryOperand); 4007 } 4008 4009 // Push the MachineInstr to OpsToUpdate. 4010 // If it is safe to remove CmpInstr, the condition code of these 4011 // instructions will be modified. 4012 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 4013 } 4014 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 4015 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 4016 IsSafe = true; 4017 break; 4018 } 4019 } 4020 4021 // If EFLAGS is not killed nor re-defined, we should check whether it is 4022 // live-out. If it is live-out, do not optimize. 4023 if ((IsCmpZero || IsSwapped) && !IsSafe) { 4024 MachineBasicBlock *MBB = CmpInstr->getParent(); 4025 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 4026 SE = MBB->succ_end(); SI != SE; ++SI) 4027 if ((*SI)->isLiveIn(X86::EFLAGS)) 4028 return false; 4029 } 4030 4031 // The instruction to be updated is either Sub or MI. 4032 Sub = IsCmpZero ? MI : Sub; 4033 // Move Movr0Inst to the appropriate place before Sub. 4034 if (Movr0Inst) { 4035 // Look backwards until we find a def that doesn't use the current EFLAGS. 4036 Def = Sub; 4037 MachineBasicBlock::reverse_iterator 4038 InsertI = MachineBasicBlock::reverse_iterator(++Def), 4039 InsertE = Sub->getParent()->rend(); 4040 for (; InsertI != InsertE; ++InsertI) { 4041 MachineInstr *Instr = &*InsertI; 4042 if (!Instr->readsRegister(X86::EFLAGS, TRI) && 4043 Instr->modifiesRegister(X86::EFLAGS, TRI)) { 4044 Sub->getParent()->remove(Movr0Inst); 4045 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr), 4046 Movr0Inst); 4047 break; 4048 } 4049 } 4050 if (InsertI == InsertE) 4051 return false; 4052 } 4053 4054 // Make sure Sub instruction defines EFLAGS and mark the def live. 4055 unsigned i = 0, e = Sub->getNumOperands(); 4056 for (; i != e; ++i) { 4057 MachineOperand &MO = Sub->getOperand(i); 4058 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) { 4059 MO.setIsDead(false); 4060 break; 4061 } 4062 } 4063 assert(i != e && "Unable to locate a def EFLAGS operand"); 4064 4065 CmpInstr->eraseFromParent(); 4066 4067 // Modify the condition code of instructions in OpsToUpdate. 4068 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 4069 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 4070 return true; 4071 } 4072 4073 /// optimizeLoadInstr - Try to remove the load by folding it to a register 4074 /// operand at the use. We fold the load instructions if load defines a virtual 4075 /// register, the virtual register is used once in the same BB, and the 4076 /// instructions in-between do not load or store, and have no side effects. 4077 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI, 4078 const MachineRegisterInfo *MRI, 4079 unsigned &FoldAsLoadDefReg, 4080 MachineInstr *&DefMI) const { 4081 if (FoldAsLoadDefReg == 0) 4082 return nullptr; 4083 // To be conservative, if there exists another load, clear the load candidate. 4084 if (MI->mayLoad()) { 4085 FoldAsLoadDefReg = 0; 4086 return nullptr; 4087 } 4088 4089 // Check whether we can move DefMI here. 4090 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 4091 assert(DefMI); 4092 bool SawStore = false; 4093 if (!DefMI->isSafeToMove(this, nullptr, SawStore)) 4094 return nullptr; 4095 4096 // Collect information about virtual register operands of MI. 4097 unsigned SrcOperandId = 0; 4098 bool FoundSrcOperand = false; 4099 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 4100 MachineOperand &MO = MI->getOperand(i); 4101 if (!MO.isReg()) 4102 continue; 4103 unsigned Reg = MO.getReg(); 4104 if (Reg != FoldAsLoadDefReg) 4105 continue; 4106 // Do not fold if we have a subreg use or a def or multiple uses. 4107 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 4108 return nullptr; 4109 4110 SrcOperandId = i; 4111 FoundSrcOperand = true; 4112 } 4113 if (!FoundSrcOperand) 4114 return nullptr; 4115 4116 // Check whether we can fold the def into SrcOperandId. 4117 SmallVector<unsigned, 8> Ops; 4118 Ops.push_back(SrcOperandId); 4119 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 4120 if (FoldMI) { 4121 FoldAsLoadDefReg = 0; 4122 return FoldMI; 4123 } 4124 4125 return nullptr; 4126 } 4127 4128 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 4129 /// instruction with two undef reads of the register being defined. This is 4130 /// used for mapping: 4131 /// %xmm4 = V_SET0 4132 /// to: 4133 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 4134 /// 4135 static bool Expand2AddrUndef(MachineInstrBuilder &MIB, 4136 const MCInstrDesc &Desc) { 4137 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 4138 unsigned Reg = MIB->getOperand(0).getReg(); 4139 MIB->setDesc(Desc); 4140 4141 // MachineInstr::addOperand() will insert explicit operands before any 4142 // implicit operands. 4143 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 4144 // But we don't trust that. 4145 assert(MIB->getOperand(1).getReg() == Reg && 4146 MIB->getOperand(2).getReg() == Reg && "Misplaced operand"); 4147 return true; 4148 } 4149 4150 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different 4151 // code sequence is needed for other targets. 4152 static void expandLoadStackGuard(MachineInstrBuilder &MIB, 4153 const TargetInstrInfo &TII) { 4154 MachineBasicBlock &MBB = *MIB->getParent(); 4155 DebugLoc DL = MIB->getDebugLoc(); 4156 unsigned Reg = MIB->getOperand(0).getReg(); 4157 const GlobalValue *GV = 4158 cast<GlobalValue>((*MIB->memoperands_begin())->getValue()); 4159 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant; 4160 MachineMemOperand *MMO = MBB.getParent()-> 4161 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8); 4162 MachineBasicBlock::iterator I = MIB.getInstr(); 4163 4164 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1) 4165 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0) 4166 .addMemOperand(MMO); 4167 MIB->setDebugLoc(DL); 4168 MIB->setDesc(TII.get(X86::MOV64rm)); 4169 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0); 4170 } 4171 4172 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 4173 bool HasAVX = Subtarget.hasAVX(); 4174 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 4175 switch (MI->getOpcode()) { 4176 case X86::MOV32r0: 4177 return Expand2AddrUndef(MIB, get(X86::XOR32rr)); 4178 case X86::SETB_C8r: 4179 return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 4180 case X86::SETB_C16r: 4181 return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 4182 case X86::SETB_C32r: 4183 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 4184 case X86::SETB_C64r: 4185 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 4186 case X86::V_SET0: 4187 case X86::FsFLD0SS: 4188 case X86::FsFLD0SD: 4189 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 4190 case X86::AVX_SET0: 4191 assert(HasAVX && "AVX not supported"); 4192 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr)); 4193 case X86::AVX512_512_SET0: 4194 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); 4195 case X86::V_SETALLONES: 4196 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 4197 case X86::AVX2_SETALLONES: 4198 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 4199 case X86::TEST8ri_NOREX: 4200 MI->setDesc(get(X86::TEST8ri)); 4201 return true; 4202 case X86::KSET0B: 4203 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr)); 4204 case X86::KSET1B: 4205 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr)); 4206 case TargetOpcode::LOAD_STACK_GUARD: 4207 expandLoadStackGuard(MIB, *this); 4208 return true; 4209 } 4210 return false; 4211 } 4212 4213 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 4214 const SmallVectorImpl<MachineOperand> &MOs, 4215 MachineInstr *MI, 4216 const TargetInstrInfo &TII) { 4217 // Create the base instruction with the memory operand as the first part. 4218 // Omit the implicit operands, something BuildMI can't do. 4219 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 4220 MI->getDebugLoc(), true); 4221 MachineInstrBuilder MIB(MF, NewMI); 4222 unsigned NumAddrOps = MOs.size(); 4223 for (unsigned i = 0; i != NumAddrOps; ++i) 4224 MIB.addOperand(MOs[i]); 4225 if (NumAddrOps < 4) // FrameIndex only 4226 addOffset(MIB, 0); 4227 4228 // Loop over the rest of the ri operands, converting them over. 4229 unsigned NumOps = MI->getDesc().getNumOperands()-2; 4230 for (unsigned i = 0; i != NumOps; ++i) { 4231 MachineOperand &MO = MI->getOperand(i+2); 4232 MIB.addOperand(MO); 4233 } 4234 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 4235 MachineOperand &MO = MI->getOperand(i); 4236 MIB.addOperand(MO); 4237 } 4238 return MIB; 4239 } 4240 4241 static MachineInstr *FuseInst(MachineFunction &MF, 4242 unsigned Opcode, unsigned OpNo, 4243 const SmallVectorImpl<MachineOperand> &MOs, 4244 MachineInstr *MI, const TargetInstrInfo &TII) { 4245 // Omit the implicit operands, something BuildMI can't do. 4246 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 4247 MI->getDebugLoc(), true); 4248 MachineInstrBuilder MIB(MF, NewMI); 4249 4250 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4251 MachineOperand &MO = MI->getOperand(i); 4252 if (i == OpNo) { 4253 assert(MO.isReg() && "Expected to fold into reg operand!"); 4254 unsigned NumAddrOps = MOs.size(); 4255 for (unsigned i = 0; i != NumAddrOps; ++i) 4256 MIB.addOperand(MOs[i]); 4257 if (NumAddrOps < 4) // FrameIndex only 4258 addOffset(MIB, 0); 4259 } else { 4260 MIB.addOperand(MO); 4261 } 4262 } 4263 return MIB; 4264 } 4265 4266 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 4267 const SmallVectorImpl<MachineOperand> &MOs, 4268 MachineInstr *MI) { 4269 MachineFunction &MF = *MI->getParent()->getParent(); 4270 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 4271 4272 unsigned NumAddrOps = MOs.size(); 4273 for (unsigned i = 0; i != NumAddrOps; ++i) 4274 MIB.addOperand(MOs[i]); 4275 if (NumAddrOps < 4) // FrameIndex only 4276 addOffset(MIB, 0); 4277 return MIB.addImm(0); 4278 } 4279 4280 MachineInstr* 4281 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 4282 MachineInstr *MI, unsigned i, 4283 const SmallVectorImpl<MachineOperand> &MOs, 4284 unsigned Size, unsigned Align, 4285 bool AllowCommute) const { 4286 const DenseMap<unsigned, 4287 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr; 4288 bool isCallRegIndirect = Subtarget.callRegIndirect(); 4289 bool isTwoAddrFold = false; 4290 4291 // Atom favors register form of call. So, we do not fold loads into calls 4292 // when X86Subtarget is Atom. 4293 if (isCallRegIndirect && 4294 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) { 4295 return nullptr; 4296 } 4297 4298 unsigned NumOps = MI->getDesc().getNumOperands(); 4299 bool isTwoAddr = NumOps > 1 && 4300 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4301 4302 // FIXME: AsmPrinter doesn't know how to handle 4303 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4304 if (MI->getOpcode() == X86::ADD32ri && 4305 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4306 return nullptr; 4307 4308 MachineInstr *NewMI = nullptr; 4309 // Folding a memory location into the two-address part of a two-address 4310 // instruction is different than folding it other places. It requires 4311 // replacing the *two* registers with the memory location. 4312 if (isTwoAddr && NumOps >= 2 && i < 2 && 4313 MI->getOperand(0).isReg() && 4314 MI->getOperand(1).isReg() && 4315 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 4316 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4317 isTwoAddrFold = true; 4318 } else if (i == 0) { // If operand 0 4319 if (MI->getOpcode() == X86::MOV32r0) { 4320 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 4321 if (NewMI) 4322 return NewMI; 4323 } 4324 4325 OpcodeTablePtr = &RegOp2MemOpTable0; 4326 } else if (i == 1) { 4327 OpcodeTablePtr = &RegOp2MemOpTable1; 4328 } else if (i == 2) { 4329 OpcodeTablePtr = &RegOp2MemOpTable2; 4330 } else if (i == 3) { 4331 OpcodeTablePtr = &RegOp2MemOpTable3; 4332 } else if (i == 4) { 4333 OpcodeTablePtr = &RegOp2MemOpTable4; 4334 } 4335 4336 // If table selected... 4337 if (OpcodeTablePtr) { 4338 // Find the Opcode to fuse 4339 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4340 OpcodeTablePtr->find(MI->getOpcode()); 4341 if (I != OpcodeTablePtr->end()) { 4342 unsigned Opcode = I->second.first; 4343 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 4344 if (Align < MinAlign) 4345 return nullptr; 4346 bool NarrowToMOV32rm = false; 4347 if (Size) { 4348 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 4349 if (Size < RCSize) { 4350 // Check if it's safe to fold the load. If the size of the object is 4351 // narrower than the load width, then it's not. 4352 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 4353 return nullptr; 4354 // If this is a 64-bit load, but the spill slot is 32, then we can do 4355 // a 32-bit load which is implicitly zero-extended. This likely is 4356 // due to live interval analysis remat'ing a load from stack slot. 4357 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 4358 return nullptr; 4359 Opcode = X86::MOV32rm; 4360 NarrowToMOV32rm = true; 4361 } 4362 } 4363 4364 if (isTwoAddrFold) 4365 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 4366 else 4367 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 4368 4369 if (NarrowToMOV32rm) { 4370 // If this is the special case where we use a MOV32rm to load a 32-bit 4371 // value and zero-extend the top bits. Change the destination register 4372 // to a 32-bit one. 4373 unsigned DstReg = NewMI->getOperand(0).getReg(); 4374 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 4375 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit)); 4376 else 4377 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 4378 } 4379 return NewMI; 4380 } 4381 } 4382 4383 // If the instruction and target operand are commutable, commute the 4384 // instruction and try again. 4385 if (AllowCommute) { 4386 unsigned OriginalOpIdx = i, CommuteOpIdx1, CommuteOpIdx2; 4387 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) { 4388 bool HasDef = MI->getDesc().getNumDefs(); 4389 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; 4390 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg(); 4391 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg(); 4392 bool Tied0 = 4393 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO); 4394 bool Tied1 = 4395 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO); 4396 4397 // If either of the commutable operands are tied to the destination 4398 // then we can not commute + fold. 4399 if ((HasDef && Reg0 == Reg1 && Tied0) || 4400 (HasDef && Reg0 == Reg2 && Tied1)) 4401 return nullptr; 4402 4403 if ((CommuteOpIdx1 == OriginalOpIdx) || 4404 (CommuteOpIdx2 == OriginalOpIdx)) { 4405 MachineInstr *CommutedMI = commuteInstruction(MI, false); 4406 if (!CommutedMI) { 4407 // Unable to commute. 4408 return nullptr; 4409 } 4410 if (CommutedMI != MI) { 4411 // New instruction. We can't fold from this. 4412 CommutedMI->eraseFromParent(); 4413 return nullptr; 4414 } 4415 4416 // Attempt to fold with the commuted version of the instruction. 4417 unsigned CommuteOp = 4418 (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1); 4419 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align, 4420 /*AllowCommute=*/false); 4421 if (NewMI) 4422 return NewMI; 4423 4424 // Folding failed again - undo the commute before returning. 4425 MachineInstr *UncommutedMI = commuteInstruction(MI, false); 4426 if (!UncommutedMI) { 4427 // Unable to commute. 4428 return nullptr; 4429 } 4430 if (UncommutedMI != MI) { 4431 // New instruction. It doesn't need to be kept. 4432 UncommutedMI->eraseFromParent(); 4433 return nullptr; 4434 } 4435 4436 // Return here to prevent duplicate fuse failure report. 4437 return nullptr; 4438 } 4439 } 4440 } 4441 4442 // No fusion 4443 if (PrintFailedFusing && !MI->isCopy()) 4444 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 4445 return nullptr; 4446 } 4447 4448 /// hasPartialRegUpdate - Return true for all instructions that only update 4449 /// the first 32 or 64-bits of the destination register and leave the rest 4450 /// unmodified. This can be used to avoid folding loads if the instructions 4451 /// only update part of the destination register, and the non-updated part is 4452 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 4453 /// instructions breaks the partial register dependency and it can improve 4454 /// performance. e.g.: 4455 /// 4456 /// movss (%rdi), %xmm0 4457 /// cvtss2sd %xmm0, %xmm0 4458 /// 4459 /// Instead of 4460 /// cvtss2sd (%rdi), %xmm0 4461 /// 4462 /// FIXME: This should be turned into a TSFlags. 4463 /// 4464 static bool hasPartialRegUpdate(unsigned Opcode) { 4465 switch (Opcode) { 4466 case X86::CVTSI2SSrr: 4467 case X86::CVTSI2SSrm: 4468 case X86::CVTSI2SS64rr: 4469 case X86::CVTSI2SS64rm: 4470 case X86::CVTSI2SDrr: 4471 case X86::CVTSI2SDrm: 4472 case X86::CVTSI2SD64rr: 4473 case X86::CVTSI2SD64rm: 4474 case X86::CVTSD2SSrr: 4475 case X86::CVTSD2SSrm: 4476 case X86::Int_CVTSD2SSrr: 4477 case X86::Int_CVTSD2SSrm: 4478 case X86::CVTSS2SDrr: 4479 case X86::CVTSS2SDrm: 4480 case X86::Int_CVTSS2SDrr: 4481 case X86::Int_CVTSS2SDrm: 4482 case X86::RCPSSr: 4483 case X86::RCPSSm: 4484 case X86::RCPSSr_Int: 4485 case X86::RCPSSm_Int: 4486 case X86::ROUNDSDr: 4487 case X86::ROUNDSDm: 4488 case X86::ROUNDSDr_Int: 4489 case X86::ROUNDSSr: 4490 case X86::ROUNDSSm: 4491 case X86::ROUNDSSr_Int: 4492 case X86::RSQRTSSr: 4493 case X86::RSQRTSSm: 4494 case X86::RSQRTSSr_Int: 4495 case X86::RSQRTSSm_Int: 4496 case X86::SQRTSSr: 4497 case X86::SQRTSSm: 4498 case X86::SQRTSSr_Int: 4499 case X86::SQRTSSm_Int: 4500 case X86::SQRTSDr: 4501 case X86::SQRTSDm: 4502 case X86::SQRTSDr_Int: 4503 case X86::SQRTSDm_Int: 4504 return true; 4505 } 4506 4507 return false; 4508 } 4509 4510 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 4511 /// instructions we would like before a partial register update. 4512 unsigned X86InstrInfo:: 4513 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 4514 const TargetRegisterInfo *TRI) const { 4515 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 4516 return 0; 4517 4518 // If MI is marked as reading Reg, the partial register update is wanted. 4519 const MachineOperand &MO = MI->getOperand(0); 4520 unsigned Reg = MO.getReg(); 4521 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 4522 if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 4523 return 0; 4524 } else { 4525 if (MI->readsRegister(Reg, TRI)) 4526 return 0; 4527 } 4528 4529 // If any of the preceding 16 instructions are reading Reg, insert a 4530 // dependency breaking instruction. The magic number is based on a few 4531 // Nehalem experiments. 4532 return 16; 4533 } 4534 4535 // Return true for any instruction the copies the high bits of the first source 4536 // operand into the unused high bits of the destination operand. 4537 static bool hasUndefRegUpdate(unsigned Opcode) { 4538 switch (Opcode) { 4539 case X86::VCVTSI2SSrr: 4540 case X86::VCVTSI2SSrm: 4541 case X86::Int_VCVTSI2SSrr: 4542 case X86::Int_VCVTSI2SSrm: 4543 case X86::VCVTSI2SS64rr: 4544 case X86::VCVTSI2SS64rm: 4545 case X86::Int_VCVTSI2SS64rr: 4546 case X86::Int_VCVTSI2SS64rm: 4547 case X86::VCVTSI2SDrr: 4548 case X86::VCVTSI2SDrm: 4549 case X86::Int_VCVTSI2SDrr: 4550 case X86::Int_VCVTSI2SDrm: 4551 case X86::VCVTSI2SD64rr: 4552 case X86::VCVTSI2SD64rm: 4553 case X86::Int_VCVTSI2SD64rr: 4554 case X86::Int_VCVTSI2SD64rm: 4555 case X86::VCVTSD2SSrr: 4556 case X86::VCVTSD2SSrm: 4557 case X86::Int_VCVTSD2SSrr: 4558 case X86::Int_VCVTSD2SSrm: 4559 case X86::VCVTSS2SDrr: 4560 case X86::VCVTSS2SDrm: 4561 case X86::Int_VCVTSS2SDrr: 4562 case X86::Int_VCVTSS2SDrm: 4563 case X86::VRCPSSr: 4564 case X86::VRCPSSm: 4565 case X86::VRCPSSm_Int: 4566 case X86::VROUNDSDr: 4567 case X86::VROUNDSDm: 4568 case X86::VROUNDSDr_Int: 4569 case X86::VROUNDSSr: 4570 case X86::VROUNDSSm: 4571 case X86::VROUNDSSr_Int: 4572 case X86::VRSQRTSSr: 4573 case X86::VRSQRTSSm: 4574 case X86::VRSQRTSSm_Int: 4575 case X86::VSQRTSSr: 4576 case X86::VSQRTSSm: 4577 case X86::VSQRTSSm_Int: 4578 case X86::VSQRTSDr: 4579 case X86::VSQRTSDm: 4580 case X86::VSQRTSDm_Int: 4581 // AVX-512 4582 case X86::VCVTSD2SSZrr: 4583 case X86::VCVTSD2SSZrm: 4584 case X86::VCVTSS2SDZrr: 4585 case X86::VCVTSS2SDZrm: 4586 return true; 4587 } 4588 4589 return false; 4590 } 4591 4592 /// Inform the ExeDepsFix pass how many idle instructions we would like before 4593 /// certain undef register reads. 4594 /// 4595 /// This catches the VCVTSI2SD family of instructions: 4596 /// 4597 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 4598 /// 4599 /// We should to be careful *not* to catch VXOR idioms which are presumably 4600 /// handled specially in the pipeline: 4601 /// 4602 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1 4603 /// 4604 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the 4605 /// high bits that are passed-through are not live. 4606 unsigned X86InstrInfo:: 4607 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 4608 const TargetRegisterInfo *TRI) const { 4609 if (!hasUndefRegUpdate(MI->getOpcode())) 4610 return 0; 4611 4612 // Set the OpNum parameter to the first source operand. 4613 OpNum = 1; 4614 4615 const MachineOperand &MO = MI->getOperand(OpNum); 4616 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { 4617 // Use the same magic number as getPartialRegUpdateClearance. 4618 return 16; 4619 } 4620 return 0; 4621 } 4622 4623 void X86InstrInfo:: 4624 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 4625 const TargetRegisterInfo *TRI) const { 4626 unsigned Reg = MI->getOperand(OpNum).getReg(); 4627 // If MI kills this register, the false dependence is already broken. 4628 if (MI->killsRegister(Reg, TRI)) 4629 return; 4630 if (X86::VR128RegClass.contains(Reg)) { 4631 // These instructions are all floating point domain, so xorps is the best 4632 // choice. 4633 bool HasAVX = Subtarget.hasAVX(); 4634 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 4635 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 4636 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 4637 } else if (X86::VR256RegClass.contains(Reg)) { 4638 // Use vxorps to clear the full ymm register. 4639 // It wants to read and write the xmm sub-register. 4640 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 4641 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 4642 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 4643 .addReg(Reg, RegState::ImplicitDefine); 4644 } else 4645 return; 4646 MI->addRegisterKilled(Reg, TRI, true); 4647 } 4648 4649 MachineInstr* 4650 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 4651 const SmallVectorImpl<unsigned> &Ops, 4652 int FrameIndex) const { 4653 // Check switch flag 4654 if (NoFusing) return nullptr; 4655 4656 // Unless optimizing for size, don't fold to avoid partial 4657 // register update stalls 4658 if (!MF.getFunction()->getAttributes(). 4659 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 4660 hasPartialRegUpdate(MI->getOpcode())) 4661 return nullptr; 4662 4663 const MachineFrameInfo *MFI = MF.getFrameInfo(); 4664 unsigned Size = MFI->getObjectSize(FrameIndex); 4665 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 4666 // If the function stack isn't realigned we don't want to fold instructions 4667 // that need increased alignment. 4668 if (!RI.needsStackRealignment(MF)) 4669 Alignment = std::min(Alignment, MF.getTarget() 4670 .getSubtargetImpl() 4671 ->getFrameLowering() 4672 ->getStackAlignment()); 4673 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4674 unsigned NewOpc = 0; 4675 unsigned RCSize = 0; 4676 switch (MI->getOpcode()) { 4677 default: return nullptr; 4678 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 4679 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 4680 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 4681 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 4682 } 4683 // Check if it's safe to fold the load. If the size of the object is 4684 // narrower than the load width, then it's not. 4685 if (Size < RCSize) 4686 return nullptr; 4687 // Change to CMPXXri r, 0 first. 4688 MI->setDesc(get(NewOpc)); 4689 MI->getOperand(1).ChangeToImmediate(0); 4690 } else if (Ops.size() != 1) 4691 return nullptr; 4692 4693 SmallVector<MachineOperand,4> MOs; 4694 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 4695 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 4696 Size, Alignment, /*AllowCommute=*/true); 4697 } 4698 4699 static bool isPartialRegisterLoad(const MachineInstr &LoadMI, 4700 const MachineFunction &MF) { 4701 unsigned Opc = LoadMI.getOpcode(); 4702 unsigned RegSize = 4703 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize(); 4704 4705 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) 4706 // These instructions only load 32 bits, we can't fold them if the 4707 // destination register is wider than 32 bits (4 bytes). 4708 return true; 4709 4710 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) 4711 // These instructions only load 64 bits, we can't fold them if the 4712 // destination register is wider than 64 bits (8 bytes). 4713 return true; 4714 4715 return false; 4716 } 4717 4718 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 4719 MachineInstr *MI, 4720 const SmallVectorImpl<unsigned> &Ops, 4721 MachineInstr *LoadMI) const { 4722 // If loading from a FrameIndex, fold directly from the FrameIndex. 4723 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 4724 int FrameIndex; 4725 if (isLoadFromStackSlot(LoadMI, FrameIndex)) { 4726 if (isPartialRegisterLoad(*LoadMI, MF)) 4727 return nullptr; 4728 return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex); 4729 } 4730 4731 // Check switch flag 4732 if (NoFusing) return nullptr; 4733 4734 // Unless optimizing for size, don't fold to avoid partial 4735 // register update stalls 4736 if (!MF.getFunction()->getAttributes(). 4737 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 4738 hasPartialRegUpdate(MI->getOpcode())) 4739 return nullptr; 4740 4741 // Determine the alignment of the load. 4742 unsigned Alignment = 0; 4743 if (LoadMI->hasOneMemOperand()) 4744 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 4745 else 4746 switch (LoadMI->getOpcode()) { 4747 case X86::AVX2_SETALLONES: 4748 case X86::AVX_SET0: 4749 Alignment = 32; 4750 break; 4751 case X86::V_SET0: 4752 case X86::V_SETALLONES: 4753 Alignment = 16; 4754 break; 4755 case X86::FsFLD0SD: 4756 Alignment = 8; 4757 break; 4758 case X86::FsFLD0SS: 4759 Alignment = 4; 4760 break; 4761 default: 4762 return nullptr; 4763 } 4764 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4765 unsigned NewOpc = 0; 4766 switch (MI->getOpcode()) { 4767 default: return nullptr; 4768 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 4769 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 4770 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 4771 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 4772 } 4773 // Change to CMPXXri r, 0 first. 4774 MI->setDesc(get(NewOpc)); 4775 MI->getOperand(1).ChangeToImmediate(0); 4776 } else if (Ops.size() != 1) 4777 return nullptr; 4778 4779 // Make sure the subregisters match. 4780 // Otherwise we risk changing the size of the load. 4781 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 4782 return nullptr; 4783 4784 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 4785 switch (LoadMI->getOpcode()) { 4786 case X86::V_SET0: 4787 case X86::V_SETALLONES: 4788 case X86::AVX2_SETALLONES: 4789 case X86::AVX_SET0: 4790 case X86::FsFLD0SD: 4791 case X86::FsFLD0SS: { 4792 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 4793 // Create a constant-pool entry and operands to load from it. 4794 4795 // Medium and large mode can't fold loads this way. 4796 if (MF.getTarget().getCodeModel() != CodeModel::Small && 4797 MF.getTarget().getCodeModel() != CodeModel::Kernel) 4798 return nullptr; 4799 4800 // x86-32 PIC requires a PIC base register for constant pools. 4801 unsigned PICBase = 0; 4802 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) { 4803 if (Subtarget.is64Bit()) 4804 PICBase = X86::RIP; 4805 else 4806 // FIXME: PICBase = getGlobalBaseReg(&MF); 4807 // This doesn't work for several reasons. 4808 // 1. GlobalBaseReg may have been spilled. 4809 // 2. It may not be live at MI. 4810 return nullptr; 4811 } 4812 4813 // Create a constant-pool entry. 4814 MachineConstantPool &MCP = *MF.getConstantPool(); 4815 Type *Ty; 4816 unsigned Opc = LoadMI->getOpcode(); 4817 if (Opc == X86::FsFLD0SS) 4818 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 4819 else if (Opc == X86::FsFLD0SD) 4820 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 4821 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 4822 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 4823 else 4824 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 4825 4826 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 4827 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 4828 Constant::getNullValue(Ty); 4829 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 4830 4831 // Create operands to load from the constant pool entry. 4832 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 4833 MOs.push_back(MachineOperand::CreateImm(1)); 4834 MOs.push_back(MachineOperand::CreateReg(0, false)); 4835 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 4836 MOs.push_back(MachineOperand::CreateReg(0, false)); 4837 break; 4838 } 4839 default: { 4840 if (isPartialRegisterLoad(*LoadMI, MF)) 4841 return nullptr; 4842 4843 // Folding a normal load. Just copy the load's address operands. 4844 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 4845 MOs.push_back(LoadMI->getOperand(i)); 4846 break; 4847 } 4848 } 4849 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 4850 /*Size=*/0, Alignment, /*AllowCommute=*/true); 4851 } 4852 4853 4854 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 4855 const SmallVectorImpl<unsigned> &Ops) const { 4856 // Check switch flag 4857 if (NoFusing) return 0; 4858 4859 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4860 switch (MI->getOpcode()) { 4861 default: return false; 4862 case X86::TEST8rr: 4863 case X86::TEST16rr: 4864 case X86::TEST32rr: 4865 case X86::TEST64rr: 4866 return true; 4867 case X86::ADD32ri: 4868 // FIXME: AsmPrinter doesn't know how to handle 4869 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4870 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4871 return false; 4872 break; 4873 } 4874 } 4875 4876 if (Ops.size() != 1) 4877 return false; 4878 4879 unsigned OpNum = Ops[0]; 4880 unsigned Opc = MI->getOpcode(); 4881 unsigned NumOps = MI->getDesc().getNumOperands(); 4882 bool isTwoAddr = NumOps > 1 && 4883 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4884 4885 // Folding a memory location into the two-address part of a two-address 4886 // instruction is different than folding it other places. It requires 4887 // replacing the *two* registers with the memory location. 4888 const DenseMap<unsigned, 4889 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr; 4890 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 4891 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4892 } else if (OpNum == 0) { // If operand 0 4893 if (Opc == X86::MOV32r0) 4894 return true; 4895 4896 OpcodeTablePtr = &RegOp2MemOpTable0; 4897 } else if (OpNum == 1) { 4898 OpcodeTablePtr = &RegOp2MemOpTable1; 4899 } else if (OpNum == 2) { 4900 OpcodeTablePtr = &RegOp2MemOpTable2; 4901 } else if (OpNum == 3) { 4902 OpcodeTablePtr = &RegOp2MemOpTable3; 4903 } 4904 4905 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 4906 return true; 4907 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops); 4908 } 4909 4910 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 4911 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 4912 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4913 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4914 MemOp2RegOpTable.find(MI->getOpcode()); 4915 if (I == MemOp2RegOpTable.end()) 4916 return false; 4917 unsigned Opc = I->second.first; 4918 unsigned Index = I->second.second & TB_INDEX_MASK; 4919 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4920 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4921 if (UnfoldLoad && !FoldedLoad) 4922 return false; 4923 UnfoldLoad &= FoldedLoad; 4924 if (UnfoldStore && !FoldedStore) 4925 return false; 4926 UnfoldStore &= FoldedStore; 4927 4928 const MCInstrDesc &MCID = get(Opc); 4929 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4930 if (!MI->hasOneMemOperand() && 4931 RC == &X86::VR128RegClass && 4932 !Subtarget.isUnalignedMemAccessFast()) 4933 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 4934 // conservatively assume the address is unaligned. That's bad for 4935 // performance. 4936 return false; 4937 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 4938 SmallVector<MachineOperand,2> BeforeOps; 4939 SmallVector<MachineOperand,2> AfterOps; 4940 SmallVector<MachineOperand,4> ImpOps; 4941 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4942 MachineOperand &Op = MI->getOperand(i); 4943 if (i >= Index && i < Index + X86::AddrNumOperands) 4944 AddrOps.push_back(Op); 4945 else if (Op.isReg() && Op.isImplicit()) 4946 ImpOps.push_back(Op); 4947 else if (i < Index) 4948 BeforeOps.push_back(Op); 4949 else if (i > Index) 4950 AfterOps.push_back(Op); 4951 } 4952 4953 // Emit the load instruction. 4954 if (UnfoldLoad) { 4955 std::pair<MachineInstr::mmo_iterator, 4956 MachineInstr::mmo_iterator> MMOs = 4957 MF.extractLoadMemRefs(MI->memoperands_begin(), 4958 MI->memoperands_end()); 4959 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4960 if (UnfoldStore) { 4961 // Address operands cannot be marked isKill. 4962 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4963 MachineOperand &MO = NewMIs[0]->getOperand(i); 4964 if (MO.isReg()) 4965 MO.setIsKill(false); 4966 } 4967 } 4968 } 4969 4970 // Emit the data processing instruction. 4971 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4972 MachineInstrBuilder MIB(MF, DataMI); 4973 4974 if (FoldedStore) 4975 MIB.addReg(Reg, RegState::Define); 4976 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4977 MIB.addOperand(BeforeOps[i]); 4978 if (FoldedLoad) 4979 MIB.addReg(Reg); 4980 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4981 MIB.addOperand(AfterOps[i]); 4982 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4983 MachineOperand &MO = ImpOps[i]; 4984 MIB.addReg(MO.getReg(), 4985 getDefRegState(MO.isDef()) | 4986 RegState::Implicit | 4987 getKillRegState(MO.isKill()) | 4988 getDeadRegState(MO.isDead()) | 4989 getUndefRegState(MO.isUndef())); 4990 } 4991 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4992 switch (DataMI->getOpcode()) { 4993 default: break; 4994 case X86::CMP64ri32: 4995 case X86::CMP64ri8: 4996 case X86::CMP32ri: 4997 case X86::CMP32ri8: 4998 case X86::CMP16ri: 4999 case X86::CMP16ri8: 5000 case X86::CMP8ri: { 5001 MachineOperand &MO0 = DataMI->getOperand(0); 5002 MachineOperand &MO1 = DataMI->getOperand(1); 5003 if (MO1.getImm() == 0) { 5004 unsigned NewOpc; 5005 switch (DataMI->getOpcode()) { 5006 default: llvm_unreachable("Unreachable!"); 5007 case X86::CMP64ri8: 5008 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 5009 case X86::CMP32ri8: 5010 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 5011 case X86::CMP16ri8: 5012 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 5013 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 5014 } 5015 DataMI->setDesc(get(NewOpc)); 5016 MO1.ChangeToRegister(MO0.getReg(), false); 5017 } 5018 } 5019 } 5020 NewMIs.push_back(DataMI); 5021 5022 // Emit the store instruction. 5023 if (UnfoldStore) { 5024 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 5025 std::pair<MachineInstr::mmo_iterator, 5026 MachineInstr::mmo_iterator> MMOs = 5027 MF.extractStoreMemRefs(MI->memoperands_begin(), 5028 MI->memoperands_end()); 5029 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 5030 } 5031 5032 return true; 5033 } 5034 5035 bool 5036 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 5037 SmallVectorImpl<SDNode*> &NewNodes) const { 5038 if (!N->isMachineOpcode()) 5039 return false; 5040 5041 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 5042 MemOp2RegOpTable.find(N->getMachineOpcode()); 5043 if (I == MemOp2RegOpTable.end()) 5044 return false; 5045 unsigned Opc = I->second.first; 5046 unsigned Index = I->second.second & TB_INDEX_MASK; 5047 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 5048 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 5049 const MCInstrDesc &MCID = get(Opc); 5050 MachineFunction &MF = DAG.getMachineFunction(); 5051 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 5052 unsigned NumDefs = MCID.NumDefs; 5053 std::vector<SDValue> AddrOps; 5054 std::vector<SDValue> BeforeOps; 5055 std::vector<SDValue> AfterOps; 5056 SDLoc dl(N); 5057 unsigned NumOps = N->getNumOperands(); 5058 for (unsigned i = 0; i != NumOps-1; ++i) { 5059 SDValue Op = N->getOperand(i); 5060 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 5061 AddrOps.push_back(Op); 5062 else if (i < Index-NumDefs) 5063 BeforeOps.push_back(Op); 5064 else if (i > Index-NumDefs) 5065 AfterOps.push_back(Op); 5066 } 5067 SDValue Chain = N->getOperand(NumOps-1); 5068 AddrOps.push_back(Chain); 5069 5070 // Emit the load instruction. 5071 SDNode *Load = nullptr; 5072 if (FoldedLoad) { 5073 EVT VT = *RC->vt_begin(); 5074 std::pair<MachineInstr::mmo_iterator, 5075 MachineInstr::mmo_iterator> MMOs = 5076 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 5077 cast<MachineSDNode>(N)->memoperands_end()); 5078 if (!(*MMOs.first) && 5079 RC == &X86::VR128RegClass && 5080 !Subtarget.isUnalignedMemAccessFast()) 5081 // Do not introduce a slow unaligned load. 5082 return false; 5083 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 5084 bool isAligned = (*MMOs.first) && 5085 (*MMOs.first)->getAlignment() >= Alignment; 5086 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl, 5087 VT, MVT::Other, AddrOps); 5088 NewNodes.push_back(Load); 5089 5090 // Preserve memory reference information. 5091 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 5092 } 5093 5094 // Emit the data processing instruction. 5095 std::vector<EVT> VTs; 5096 const TargetRegisterClass *DstRC = nullptr; 5097 if (MCID.getNumDefs() > 0) { 5098 DstRC = getRegClass(MCID, 0, &RI, MF); 5099 VTs.push_back(*DstRC->vt_begin()); 5100 } 5101 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 5102 EVT VT = N->getValueType(i); 5103 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 5104 VTs.push_back(VT); 5105 } 5106 if (Load) 5107 BeforeOps.push_back(SDValue(Load, 0)); 5108 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 5109 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); 5110 NewNodes.push_back(NewNode); 5111 5112 // Emit the store instruction. 5113 if (FoldedStore) { 5114 AddrOps.pop_back(); 5115 AddrOps.push_back(SDValue(NewNode, 0)); 5116 AddrOps.push_back(Chain); 5117 std::pair<MachineInstr::mmo_iterator, 5118 MachineInstr::mmo_iterator> MMOs = 5119 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 5120 cast<MachineSDNode>(N)->memoperands_end()); 5121 if (!(*MMOs.first) && 5122 RC == &X86::VR128RegClass && 5123 !Subtarget.isUnalignedMemAccessFast()) 5124 // Do not introduce a slow unaligned store. 5125 return false; 5126 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 5127 bool isAligned = (*MMOs.first) && 5128 (*MMOs.first)->getAlignment() >= Alignment; 5129 SDNode *Store = 5130 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget), 5131 dl, MVT::Other, AddrOps); 5132 NewNodes.push_back(Store); 5133 5134 // Preserve memory reference information. 5135 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 5136 } 5137 5138 return true; 5139 } 5140 5141 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 5142 bool UnfoldLoad, bool UnfoldStore, 5143 unsigned *LoadRegIndex) const { 5144 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 5145 MemOp2RegOpTable.find(Opc); 5146 if (I == MemOp2RegOpTable.end()) 5147 return 0; 5148 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 5149 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 5150 if (UnfoldLoad && !FoldedLoad) 5151 return 0; 5152 if (UnfoldStore && !FoldedStore) 5153 return 0; 5154 if (LoadRegIndex) 5155 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 5156 return I->second.first; 5157 } 5158 5159 bool 5160 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 5161 int64_t &Offset1, int64_t &Offset2) const { 5162 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 5163 return false; 5164 unsigned Opc1 = Load1->getMachineOpcode(); 5165 unsigned Opc2 = Load2->getMachineOpcode(); 5166 switch (Opc1) { 5167 default: return false; 5168 case X86::MOV8rm: 5169 case X86::MOV16rm: 5170 case X86::MOV32rm: 5171 case X86::MOV64rm: 5172 case X86::LD_Fp32m: 5173 case X86::LD_Fp64m: 5174 case X86::LD_Fp80m: 5175 case X86::MOVSSrm: 5176 case X86::MOVSDrm: 5177 case X86::MMX_MOVD64rm: 5178 case X86::MMX_MOVQ64rm: 5179 case X86::FsMOVAPSrm: 5180 case X86::FsMOVAPDrm: 5181 case X86::MOVAPSrm: 5182 case X86::MOVUPSrm: 5183 case X86::MOVAPDrm: 5184 case X86::MOVDQArm: 5185 case X86::MOVDQUrm: 5186 // AVX load instructions 5187 case X86::VMOVSSrm: 5188 case X86::VMOVSDrm: 5189 case X86::FsVMOVAPSrm: 5190 case X86::FsVMOVAPDrm: 5191 case X86::VMOVAPSrm: 5192 case X86::VMOVUPSrm: 5193 case X86::VMOVAPDrm: 5194 case X86::VMOVDQArm: 5195 case X86::VMOVDQUrm: 5196 case X86::VMOVAPSYrm: 5197 case X86::VMOVUPSYrm: 5198 case X86::VMOVAPDYrm: 5199 case X86::VMOVDQAYrm: 5200 case X86::VMOVDQUYrm: 5201 break; 5202 } 5203 switch (Opc2) { 5204 default: return false; 5205 case X86::MOV8rm: 5206 case X86::MOV16rm: 5207 case X86::MOV32rm: 5208 case X86::MOV64rm: 5209 case X86::LD_Fp32m: 5210 case X86::LD_Fp64m: 5211 case X86::LD_Fp80m: 5212 case X86::MOVSSrm: 5213 case X86::MOVSDrm: 5214 case X86::MMX_MOVD64rm: 5215 case X86::MMX_MOVQ64rm: 5216 case X86::FsMOVAPSrm: 5217 case X86::FsMOVAPDrm: 5218 case X86::MOVAPSrm: 5219 case X86::MOVUPSrm: 5220 case X86::MOVAPDrm: 5221 case X86::MOVDQArm: 5222 case X86::MOVDQUrm: 5223 // AVX load instructions 5224 case X86::VMOVSSrm: 5225 case X86::VMOVSDrm: 5226 case X86::FsVMOVAPSrm: 5227 case X86::FsVMOVAPDrm: 5228 case X86::VMOVAPSrm: 5229 case X86::VMOVUPSrm: 5230 case X86::VMOVAPDrm: 5231 case X86::VMOVDQArm: 5232 case X86::VMOVDQUrm: 5233 case X86::VMOVAPSYrm: 5234 case X86::VMOVUPSYrm: 5235 case X86::VMOVAPDYrm: 5236 case X86::VMOVDQAYrm: 5237 case X86::VMOVDQUYrm: 5238 break; 5239 } 5240 5241 // Check if chain operands and base addresses match. 5242 if (Load1->getOperand(0) != Load2->getOperand(0) || 5243 Load1->getOperand(5) != Load2->getOperand(5)) 5244 return false; 5245 // Segment operands should match as well. 5246 if (Load1->getOperand(4) != Load2->getOperand(4)) 5247 return false; 5248 // Scale should be 1, Index should be Reg0. 5249 if (Load1->getOperand(1) == Load2->getOperand(1) && 5250 Load1->getOperand(2) == Load2->getOperand(2)) { 5251 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 5252 return false; 5253 5254 // Now let's examine the displacements. 5255 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 5256 isa<ConstantSDNode>(Load2->getOperand(3))) { 5257 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 5258 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 5259 return true; 5260 } 5261 } 5262 return false; 5263 } 5264 5265 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 5266 int64_t Offset1, int64_t Offset2, 5267 unsigned NumLoads) const { 5268 assert(Offset2 > Offset1); 5269 if ((Offset2 - Offset1) / 8 > 64) 5270 return false; 5271 5272 unsigned Opc1 = Load1->getMachineOpcode(); 5273 unsigned Opc2 = Load2->getMachineOpcode(); 5274 if (Opc1 != Opc2) 5275 return false; // FIXME: overly conservative? 5276 5277 switch (Opc1) { 5278 default: break; 5279 case X86::LD_Fp32m: 5280 case X86::LD_Fp64m: 5281 case X86::LD_Fp80m: 5282 case X86::MMX_MOVD64rm: 5283 case X86::MMX_MOVQ64rm: 5284 return false; 5285 } 5286 5287 EVT VT = Load1->getValueType(0); 5288 switch (VT.getSimpleVT().SimpleTy) { 5289 default: 5290 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 5291 // have 16 of them to play with. 5292 if (Subtarget.is64Bit()) { 5293 if (NumLoads >= 3) 5294 return false; 5295 } else if (NumLoads) { 5296 return false; 5297 } 5298 break; 5299 case MVT::i8: 5300 case MVT::i16: 5301 case MVT::i32: 5302 case MVT::i64: 5303 case MVT::f32: 5304 case MVT::f64: 5305 if (NumLoads) 5306 return false; 5307 break; 5308 } 5309 5310 return true; 5311 } 5312 5313 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First, 5314 MachineInstr *Second) const { 5315 // Check if this processor supports macro-fusion. Since this is a minor 5316 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent 5317 // proxy for SandyBridge+. 5318 if (!Subtarget.hasAVX()) 5319 return false; 5320 5321 enum { 5322 FuseTest, 5323 FuseCmp, 5324 FuseInc 5325 } FuseKind; 5326 5327 switch(Second->getOpcode()) { 5328 default: 5329 return false; 5330 case X86::JE_1: 5331 case X86::JNE_1: 5332 case X86::JL_1: 5333 case X86::JLE_1: 5334 case X86::JG_1: 5335 case X86::JGE_1: 5336 FuseKind = FuseInc; 5337 break; 5338 case X86::JB_1: 5339 case X86::JBE_1: 5340 case X86::JA_1: 5341 case X86::JAE_1: 5342 FuseKind = FuseCmp; 5343 break; 5344 case X86::JS_1: 5345 case X86::JNS_1: 5346 case X86::JP_1: 5347 case X86::JNP_1: 5348 case X86::JO_1: 5349 case X86::JNO_1: 5350 FuseKind = FuseTest; 5351 break; 5352 } 5353 switch (First->getOpcode()) { 5354 default: 5355 return false; 5356 case X86::TEST8rr: 5357 case X86::TEST16rr: 5358 case X86::TEST32rr: 5359 case X86::TEST64rr: 5360 case X86::TEST8ri: 5361 case X86::TEST16ri: 5362 case X86::TEST32ri: 5363 case X86::TEST32i32: 5364 case X86::TEST64i32: 5365 case X86::TEST64ri32: 5366 case X86::TEST8rm: 5367 case X86::TEST16rm: 5368 case X86::TEST32rm: 5369 case X86::TEST64rm: 5370 case X86::TEST8ri_NOREX: 5371 case X86::AND16i16: 5372 case X86::AND16ri: 5373 case X86::AND16ri8: 5374 case X86::AND16rm: 5375 case X86::AND16rr: 5376 case X86::AND32i32: 5377 case X86::AND32ri: 5378 case X86::AND32ri8: 5379 case X86::AND32rm: 5380 case X86::AND32rr: 5381 case X86::AND64i32: 5382 case X86::AND64ri32: 5383 case X86::AND64ri8: 5384 case X86::AND64rm: 5385 case X86::AND64rr: 5386 case X86::AND8i8: 5387 case X86::AND8ri: 5388 case X86::AND8rm: 5389 case X86::AND8rr: 5390 return true; 5391 case X86::CMP16i16: 5392 case X86::CMP16ri: 5393 case X86::CMP16ri8: 5394 case X86::CMP16rm: 5395 case X86::CMP16rr: 5396 case X86::CMP32i32: 5397 case X86::CMP32ri: 5398 case X86::CMP32ri8: 5399 case X86::CMP32rm: 5400 case X86::CMP32rr: 5401 case X86::CMP64i32: 5402 case X86::CMP64ri32: 5403 case X86::CMP64ri8: 5404 case X86::CMP64rm: 5405 case X86::CMP64rr: 5406 case X86::CMP8i8: 5407 case X86::CMP8ri: 5408 case X86::CMP8rm: 5409 case X86::CMP8rr: 5410 case X86::ADD16i16: 5411 case X86::ADD16ri: 5412 case X86::ADD16ri8: 5413 case X86::ADD16ri8_DB: 5414 case X86::ADD16ri_DB: 5415 case X86::ADD16rm: 5416 case X86::ADD16rr: 5417 case X86::ADD16rr_DB: 5418 case X86::ADD32i32: 5419 case X86::ADD32ri: 5420 case X86::ADD32ri8: 5421 case X86::ADD32ri8_DB: 5422 case X86::ADD32ri_DB: 5423 case X86::ADD32rm: 5424 case X86::ADD32rr: 5425 case X86::ADD32rr_DB: 5426 case X86::ADD64i32: 5427 case X86::ADD64ri32: 5428 case X86::ADD64ri32_DB: 5429 case X86::ADD64ri8: 5430 case X86::ADD64ri8_DB: 5431 case X86::ADD64rm: 5432 case X86::ADD64rr: 5433 case X86::ADD64rr_DB: 5434 case X86::ADD8i8: 5435 case X86::ADD8mi: 5436 case X86::ADD8mr: 5437 case X86::ADD8ri: 5438 case X86::ADD8rm: 5439 case X86::ADD8rr: 5440 case X86::SUB16i16: 5441 case X86::SUB16ri: 5442 case X86::SUB16ri8: 5443 case X86::SUB16rm: 5444 case X86::SUB16rr: 5445 case X86::SUB32i32: 5446 case X86::SUB32ri: 5447 case X86::SUB32ri8: 5448 case X86::SUB32rm: 5449 case X86::SUB32rr: 5450 case X86::SUB64i32: 5451 case X86::SUB64ri32: 5452 case X86::SUB64ri8: 5453 case X86::SUB64rm: 5454 case X86::SUB64rr: 5455 case X86::SUB8i8: 5456 case X86::SUB8ri: 5457 case X86::SUB8rm: 5458 case X86::SUB8rr: 5459 return FuseKind == FuseCmp || FuseKind == FuseInc; 5460 case X86::INC16r: 5461 case X86::INC32r: 5462 case X86::INC64r: 5463 case X86::INC8r: 5464 case X86::DEC16r: 5465 case X86::DEC32r: 5466 case X86::DEC64r: 5467 case X86::DEC8r: 5468 return FuseKind == FuseInc; 5469 } 5470 } 5471 5472 bool X86InstrInfo:: 5473 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 5474 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 5475 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 5476 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 5477 return true; 5478 Cond[0].setImm(GetOppositeBranchCondition(CC)); 5479 return false; 5480 } 5481 5482 bool X86InstrInfo:: 5483 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 5484 // FIXME: Return false for x87 stack register classes for now. We can't 5485 // allow any loads of these registers before FpGet_ST0_80. 5486 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 5487 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 5488 } 5489 5490 /// getGlobalBaseReg - Return a virtual register initialized with the 5491 /// the global base register value. Output instructions required to 5492 /// initialize the register in the function entry block, if necessary. 5493 /// 5494 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 5495 /// 5496 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 5497 assert(!Subtarget.is64Bit() && 5498 "X86-64 PIC uses RIP relative addressing"); 5499 5500 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 5501 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 5502 if (GlobalBaseReg != 0) 5503 return GlobalBaseReg; 5504 5505 // Create the register. The code to initialize it is inserted 5506 // later, by the CGBR pass (below). 5507 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 5508 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 5509 X86FI->setGlobalBaseReg(GlobalBaseReg); 5510 return GlobalBaseReg; 5511 } 5512 5513 // These are the replaceable SSE instructions. Some of these have Int variants 5514 // that we don't include here. We don't want to replace instructions selected 5515 // by intrinsics. 5516 static const uint16_t ReplaceableInstrs[][3] = { 5517 //PackedSingle PackedDouble PackedInt 5518 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 5519 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 5520 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 5521 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 5522 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 5523 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 5524 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 5525 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 5526 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 5527 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 5528 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 5529 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 5530 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 5531 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 5532 // AVX 128-bit support 5533 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 5534 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 5535 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 5536 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 5537 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 5538 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 5539 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 5540 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 5541 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 5542 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 5543 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 5544 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 5545 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 5546 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 5547 // AVX 256-bit support 5548 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 5549 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 5550 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 5551 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 5552 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 5553 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 5554 }; 5555 5556 static const uint16_t ReplaceableInstrsAVX2[][3] = { 5557 //PackedSingle PackedDouble PackedInt 5558 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 5559 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 5560 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 5561 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 5562 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 5563 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 5564 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 5565 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 5566 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 5567 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 5568 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 5569 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 5570 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 5571 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }, 5572 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm}, 5573 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr}, 5574 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr}, 5575 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm}, 5576 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr}, 5577 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm} 5578 }; 5579 5580 // FIXME: Some shuffle and unpack instructions have equivalents in different 5581 // domains, but they require a bit more work than just switching opcodes. 5582 5583 static const uint16_t *lookup(unsigned opcode, unsigned domain) { 5584 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 5585 if (ReplaceableInstrs[i][domain-1] == opcode) 5586 return ReplaceableInstrs[i]; 5587 return nullptr; 5588 } 5589 5590 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 5591 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 5592 if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 5593 return ReplaceableInstrsAVX2[i]; 5594 return nullptr; 5595 } 5596 5597 std::pair<uint16_t, uint16_t> 5598 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 5599 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 5600 bool hasAVX2 = Subtarget.hasAVX2(); 5601 uint16_t validDomains = 0; 5602 if (domain && lookup(MI->getOpcode(), domain)) 5603 validDomains = 0xe; 5604 else if (domain && lookupAVX2(MI->getOpcode(), domain)) 5605 validDomains = hasAVX2 ? 0xe : 0x6; 5606 return std::make_pair(domain, validDomains); 5607 } 5608 5609 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 5610 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 5611 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 5612 assert(dom && "Not an SSE instruction"); 5613 const uint16_t *table = lookup(MI->getOpcode(), dom); 5614 if (!table) { // try the other table 5615 assert((Subtarget.hasAVX2() || Domain < 3) && 5616 "256-bit vector operations only available in AVX2"); 5617 table = lookupAVX2(MI->getOpcode(), dom); 5618 } 5619 assert(table && "Cannot change domain"); 5620 MI->setDesc(get(table[Domain-1])); 5621 } 5622 5623 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 5624 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 5625 NopInst.setOpcode(X86::NOOP); 5626 } 5627 5628 // This code must remain in sync with getJumpInstrTableEntryBound in this class! 5629 // In particular, getJumpInstrTableEntryBound must always return an upper bound 5630 // on the encoding lengths of the instructions generated by 5631 // getUnconditionalBranch and getTrap. 5632 void X86InstrInfo::getUnconditionalBranch( 5633 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const { 5634 Branch.setOpcode(X86::JMP_1); 5635 Branch.addOperand(MCOperand::CreateExpr(BranchTarget)); 5636 } 5637 5638 // This code must remain in sync with getJumpInstrTableEntryBound in this class! 5639 // In particular, getJumpInstrTableEntryBound must always return an upper bound 5640 // on the encoding lengths of the instructions generated by 5641 // getUnconditionalBranch and getTrap. 5642 void X86InstrInfo::getTrap(MCInst &MI) const { 5643 MI.setOpcode(X86::TRAP); 5644 } 5645 5646 // See getTrap and getUnconditionalBranch for conditions on the value returned 5647 // by this function. 5648 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const { 5649 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4 5650 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B). 5651 return 5; 5652 } 5653 5654 bool X86InstrInfo::isHighLatencyDef(int opc) const { 5655 switch (opc) { 5656 default: return false; 5657 case X86::DIVSDrm: 5658 case X86::DIVSDrm_Int: 5659 case X86::DIVSDrr: 5660 case X86::DIVSDrr_Int: 5661 case X86::DIVSSrm: 5662 case X86::DIVSSrm_Int: 5663 case X86::DIVSSrr: 5664 case X86::DIVSSrr_Int: 5665 case X86::SQRTPDm: 5666 case X86::SQRTPDr: 5667 case X86::SQRTPSm: 5668 case X86::SQRTPSr: 5669 case X86::SQRTSDm: 5670 case X86::SQRTSDm_Int: 5671 case X86::SQRTSDr: 5672 case X86::SQRTSDr_Int: 5673 case X86::SQRTSSm: 5674 case X86::SQRTSSm_Int: 5675 case X86::SQRTSSr: 5676 case X86::SQRTSSr_Int: 5677 // AVX instructions with high latency 5678 case X86::VDIVSDrm: 5679 case X86::VDIVSDrm_Int: 5680 case X86::VDIVSDrr: 5681 case X86::VDIVSDrr_Int: 5682 case X86::VDIVSSrm: 5683 case X86::VDIVSSrm_Int: 5684 case X86::VDIVSSrr: 5685 case X86::VDIVSSrr_Int: 5686 case X86::VSQRTPDm: 5687 case X86::VSQRTPDr: 5688 case X86::VSQRTPSm: 5689 case X86::VSQRTPSr: 5690 case X86::VSQRTSDm: 5691 case X86::VSQRTSDm_Int: 5692 case X86::VSQRTSDr: 5693 case X86::VSQRTSSm: 5694 case X86::VSQRTSSm_Int: 5695 case X86::VSQRTSSr: 5696 case X86::VSQRTPDZm: 5697 case X86::VSQRTPDZr: 5698 case X86::VSQRTPSZm: 5699 case X86::VSQRTPSZr: 5700 case X86::VSQRTSDZm: 5701 case X86::VSQRTSDZm_Int: 5702 case X86::VSQRTSDZr: 5703 case X86::VSQRTSSZm_Int: 5704 case X86::VSQRTSSZr: 5705 case X86::VSQRTSSZm: 5706 case X86::VDIVSDZrm: 5707 case X86::VDIVSDZrr: 5708 case X86::VDIVSSZrm: 5709 case X86::VDIVSSZrr: 5710 5711 case X86::VGATHERQPSZrm: 5712 case X86::VGATHERQPDZrm: 5713 case X86::VGATHERDPDZrm: 5714 case X86::VGATHERDPSZrm: 5715 case X86::VPGATHERQDZrm: 5716 case X86::VPGATHERQQZrm: 5717 case X86::VPGATHERDDZrm: 5718 case X86::VPGATHERDQZrm: 5719 case X86::VSCATTERQPDZmr: 5720 case X86::VSCATTERQPSZmr: 5721 case X86::VSCATTERDPDZmr: 5722 case X86::VSCATTERDPSZmr: 5723 case X86::VPSCATTERQDZmr: 5724 case X86::VPSCATTERQQZmr: 5725 case X86::VPSCATTERDDZmr: 5726 case X86::VPSCATTERDQZmr: 5727 return true; 5728 } 5729 } 5730 5731 bool X86InstrInfo:: 5732 hasHighOperandLatency(const InstrItineraryData *ItinData, 5733 const MachineRegisterInfo *MRI, 5734 const MachineInstr *DefMI, unsigned DefIdx, 5735 const MachineInstr *UseMI, unsigned UseIdx) const { 5736 return isHighLatencyDef(DefMI->getOpcode()); 5737 } 5738 5739 namespace { 5740 /// CGBR - Create Global Base Reg pass. This initializes the PIC 5741 /// global base register for x86-32. 5742 struct CGBR : public MachineFunctionPass { 5743 static char ID; 5744 CGBR() : MachineFunctionPass(ID) {} 5745 5746 bool runOnMachineFunction(MachineFunction &MF) override { 5747 const X86TargetMachine *TM = 5748 static_cast<const X86TargetMachine *>(&MF.getTarget()); 5749 5750 // Don't do anything if this is 64-bit as 64-bit PIC 5751 // uses RIP relative addressing. 5752 if (TM->getSubtarget<X86Subtarget>().is64Bit()) 5753 return false; 5754 5755 // Only emit a global base reg in PIC mode. 5756 if (TM->getRelocationModel() != Reloc::PIC_) 5757 return false; 5758 5759 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 5760 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 5761 5762 // If we didn't need a GlobalBaseReg, don't insert code. 5763 if (GlobalBaseReg == 0) 5764 return false; 5765 5766 // Insert the set of GlobalBaseReg into the first MBB of the function 5767 MachineBasicBlock &FirstMBB = MF.front(); 5768 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 5769 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 5770 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5771 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo(); 5772 5773 unsigned PC; 5774 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 5775 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 5776 else 5777 PC = GlobalBaseReg; 5778 5779 // Operand of MovePCtoStack is completely ignored by asm printer. It's 5780 // only used in JIT code emission as displacement to pc. 5781 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 5782 5783 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 5784 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 5785 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 5786 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 5787 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 5788 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 5789 X86II::MO_GOT_ABSOLUTE_ADDRESS); 5790 } 5791 5792 return true; 5793 } 5794 5795 const char *getPassName() const override { 5796 return "X86 PIC Global Base Reg Initialization"; 5797 } 5798 5799 void getAnalysisUsage(AnalysisUsage &AU) const override { 5800 AU.setPreservesCFG(); 5801 MachineFunctionPass::getAnalysisUsage(AU); 5802 } 5803 }; 5804 } 5805 5806 char CGBR::ID = 0; 5807 FunctionPass* 5808 llvm::createX86GlobalBaseRegPass() { return new CGBR(); } 5809 5810 namespace { 5811 struct LDTLSCleanup : public MachineFunctionPass { 5812 static char ID; 5813 LDTLSCleanup() : MachineFunctionPass(ID) {} 5814 5815 bool runOnMachineFunction(MachineFunction &MF) override { 5816 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 5817 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 5818 // No point folding accesses if there isn't at least two. 5819 return false; 5820 } 5821 5822 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 5823 return VisitNode(DT->getRootNode(), 0); 5824 } 5825 5826 // Visit the dominator subtree rooted at Node in pre-order. 5827 // If TLSBaseAddrReg is non-null, then use that to replace any 5828 // TLS_base_addr instructions. Otherwise, create the register 5829 // when the first such instruction is seen, and then use it 5830 // as we encounter more instructions. 5831 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 5832 MachineBasicBlock *BB = Node->getBlock(); 5833 bool Changed = false; 5834 5835 // Traverse the current block. 5836 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 5837 ++I) { 5838 switch (I->getOpcode()) { 5839 case X86::TLS_base_addr32: 5840 case X86::TLS_base_addr64: 5841 if (TLSBaseAddrReg) 5842 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 5843 else 5844 I = SetRegister(I, &TLSBaseAddrReg); 5845 Changed = true; 5846 break; 5847 default: 5848 break; 5849 } 5850 } 5851 5852 // Visit the children of this block in the dominator tree. 5853 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 5854 I != E; ++I) { 5855 Changed |= VisitNode(*I, TLSBaseAddrReg); 5856 } 5857 5858 return Changed; 5859 } 5860 5861 // Replace the TLS_base_addr instruction I with a copy from 5862 // TLSBaseAddrReg, returning the new instruction. 5863 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 5864 unsigned TLSBaseAddrReg) { 5865 MachineFunction *MF = I->getParent()->getParent(); 5866 const X86TargetMachine *TM = 5867 static_cast<const X86TargetMachine *>(&MF->getTarget()); 5868 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 5869 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo(); 5870 5871 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 5872 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 5873 TII->get(TargetOpcode::COPY), 5874 is64Bit ? X86::RAX : X86::EAX) 5875 .addReg(TLSBaseAddrReg); 5876 5877 // Erase the TLS_base_addr instruction. 5878 I->eraseFromParent(); 5879 5880 return Copy; 5881 } 5882 5883 // Create a virtal register in *TLSBaseAddrReg, and populate it by 5884 // inserting a copy instruction after I. Returns the new instruction. 5885 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 5886 MachineFunction *MF = I->getParent()->getParent(); 5887 const X86TargetMachine *TM = 5888 static_cast<const X86TargetMachine *>(&MF->getTarget()); 5889 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 5890 const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo(); 5891 5892 // Create a virtual register for the TLS base address. 5893 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 5894 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 5895 ? &X86::GR64RegClass 5896 : &X86::GR32RegClass); 5897 5898 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 5899 MachineInstr *Next = I->getNextNode(); 5900 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 5901 TII->get(TargetOpcode::COPY), 5902 *TLSBaseAddrReg) 5903 .addReg(is64Bit ? X86::RAX : X86::EAX); 5904 5905 return Copy; 5906 } 5907 5908 const char *getPassName() const override { 5909 return "Local Dynamic TLS Access Clean-up"; 5910 } 5911 5912 void getAnalysisUsage(AnalysisUsage &AU) const override { 5913 AU.setPreservesCFG(); 5914 AU.addRequired<MachineDominatorTree>(); 5915 MachineFunctionPass::getAnalysisUsage(AU); 5916 } 5917 }; 5918 } 5919 5920 char LDTLSCleanup::ID = 0; 5921 FunctionPass* 5922 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 5923